Unified Coverage Report :: Group Instance : key_version

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7008

1

T4

8

T15

18

T16

19

auto[1]

306

1

T42

16

T141

3

T142

5

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	2898	1			T4	4		T15	7		T16	7
auto[134217728:268435455]	163	1			T42	1		T24	1		T93	3
auto[268435456:402653183]	151	1			T15	1		T24	1		T29	2
auto[402653184:536870911]	166	1			T15	2		T16	1		T140	1
auto[536870912:671088639]	152	1			T53	1		T101	2		T45	2
auto[671088640:805306367]	159	1			T15	2		T42	2		T24	1
auto[805306368:939524095]	159	1			T4	1		T42	1		T38	1
auto[939524096:1073741823]	138	1			T42	1		T38	1		T108	2
auto[1073741824:1207959551]	143	1			T16	1		T25	2		T44	1
auto[1207959552:1342177279]	131	1			T42	1		T101	1		T12	3
auto[1342177280:1476395007]	124	1			T4	1		T42	1		T44	1
auto[1476395008:1610612735]	174	1			T16	1		T29	1		T101	1
auto[1610612736:1744830463]	132	1			T41	3		T108	1		T45	1
auto[1744830464:1879048191]	121	1			T53	1		T142	1		T12	1
auto[1879048192:2013265919]	130	1			T28	1		T42	1		T41	1
auto[2013265920:2147483647]	129	1			T15	1		T16	1		T28	1
auto[2147483648:2281701375]	137	1			T42	1		T53	1		T26	1
auto[2281701376:2415919103]	144	1			T15	2		T42	2		T229	1
auto[2415919104:2550136831]	152	1			T16	1		T42	1		T229	1
auto[2550136832:2684354559]	133	1			T28	1		T42	1		T41	1
auto[2684354560:2818572287]	130	1			T4	1		T15	1		T16	1
auto[2818572288:2952790015]	131	1			T15	1		T16	2		T71	1
auto[2952790016:3087007743]	139	1			T16	1		T29	1		T53	1
auto[3087007744:3221225471]	130	1			T77	1		T93	1		T141	1
auto[3221225472:3355443199]	139	1			T16	1		T25	1		T77	1
auto[3355443200:3489660927]	141	1			T24	1		T108	1		T93	1
auto[3489660928:3623878655]	154	1			T4	1		T38	1		T29	2
auto[3623878656:3758096383]	141	1			T42	2		T25	1		T93	1
auto[3758096384:3892314111]	140	1			T15	1		T16	2		T42	1
auto[3892314112:4026531839]	139	1			T29	1		T25	1		T108	2
auto[4026531840:4160749567]	119	1			T28	1		T42	1		T41	1
auto[4160749568:4294967295]	175	1			T42	1		T41	2		T108	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	2889	1			T4	4		T15	7		T16	7
auto[0:134217727]	auto[1]	9	1			T42	1		T85	1		T123	1
auto[134217728:268435455]	auto[0]	155	1			T24	1		T93	3		T53	1
auto[134217728:268435455]	auto[1]	8	1			T42	1		T85	1		T272	1
auto[268435456:402653183]	auto[0]	140	1			T15	1		T24	1		T29	2
auto[268435456:402653183]	auto[1]	11	1			T142	1		T272	1		T270	1
auto[402653184:536870911]	auto[0]	157	1			T15	2		T16	1		T140	1
auto[402653184:536870911]	auto[1]	9	1			T85	1		T123	1		T128	1
auto[536870912:671088639]	auto[0]	145	1			T53	1		T101	2		T45	2
auto[536870912:671088639]	auto[1]	7	1			T435	1		T411	1		T436	1
auto[671088640:805306367]	auto[0]	142	1			T15	2		T42	1		T24	1
auto[671088640:805306367]	auto[1]	17	1			T42	1		T85	2		T272	1
auto[805306368:939524095]	auto[0]	148	1			T4	1		T38	1		T107	1
auto[805306368:939524095]	auto[1]	11	1			T42	1		T129	1		T310	1
auto[939524096:1073741823]	auto[0]	130	1			T38	1		T108	2		T230	1
auto[939524096:1073741823]	auto[1]	8	1			T42	1		T142	1		T85	1
auto[1073741824:1207959551]	auto[0]	134	1			T16	1		T25	2		T44	1
auto[1073741824:1207959551]	auto[1]	9	1			T85	1		T126	1		T270	1
auto[1207959552:1342177279]	auto[0]	122	1			T101	1		T12	3		T207	1
auto[1207959552:1342177279]	auto[1]	9	1			T42	1		T216	1		T124	1
auto[1342177280:1476395007]	auto[0]	112	1			T4	1		T44	1		T93	1
auto[1342177280:1476395007]	auto[1]	12	1			T42	1		T123	1		T128	1
auto[1476395008:1610612735]	auto[0]	159	1			T16	1		T29	1		T101	1
auto[1476395008:1610612735]	auto[1]	15	1			T85	1		T86	1		T123	3
auto[1610612736:1744830463]	auto[0]	123	1			T41	3		T108	1		T45	1
auto[1610612736:1744830463]	auto[1]	9	1			T216	1		T123	1		T124	1
auto[1744830464:1879048191]	auto[0]	112	1			T53	1		T12	1		T22	1
auto[1744830464:1879048191]	auto[1]	9	1			T142	1		T128	1		T309	1
auto[1879048192:2013265919]	auto[0]	119	1			T28	1		T41	1		T101	2
auto[1879048192:2013265919]	auto[1]	11	1			T42	1		T216	1		T272	2
auto[2013265920:2147483647]	auto[0]	117	1			T15	1		T16	1		T28	1
auto[2013265920:2147483647]	auto[1]	12	1			T141	1		T142	1		T216	1
auto[2147483648:2281701375]	auto[0]	131	1			T42	1		T53	1		T26	1
auto[2147483648:2281701375]	auto[1]	6	1			T129	1		T437	1		T438	1
auto[2281701376:2415919103]	auto[0]	133	1			T15	2		T42	1		T229	1
auto[2281701376:2415919103]	auto[1]	11	1			T42	1		T272	1		T123	1
auto[2415919104:2550136831]	auto[0]	146	1			T16	1		T229	1		T71	1
auto[2415919104:2550136831]	auto[1]	6	1			T42	1		T85	1		T345	1
auto[2550136832:2684354559]	auto[0]	122	1			T28	1		T41	1		T77	1
auto[2550136832:2684354559]	auto[1]	11	1			T42	1		T272	1		T123	1
auto[2684354560:2818572287]	auto[0]	117	1			T4	1		T15	1		T16	1
auto[2684354560:2818572287]	auto[1]	13	1			T42	2		T141	1		T216	1
auto[2818572288:2952790015]	auto[0]	125	1			T15	1		T16	2		T71	1
auto[2818572288:2952790015]	auto[1]	6	1			T216	1		T272	1		T435	1
auto[2952790016:3087007743]	auto[0]	133	1			T16	1		T29	1		T53	1
auto[2952790016:3087007743]	auto[1]	6	1			T142	1		T378	1		T292	1
auto[3087007744:3221225471]	auto[0]	121	1			T77	1		T93	1		T141	1
auto[3087007744:3221225471]	auto[1]	9	1			T123	1		T129	1		T439	1
auto[3221225472:3355443199]	auto[0]	128	1			T16	1		T25	1		T77	1
auto[3221225472:3355443199]	auto[1]	11	1			T122	2		T216	1		T123	2
auto[3355443200:3489660927]	auto[0]	131	1			T24	1		T108	1		T93	1
auto[3355443200:3489660927]	auto[1]	10	1			T216	2		T345	1		T275	1
auto[3489660928:3623878655]	auto[0]	141	1			T4	1		T38	1		T29	2
auto[3489660928:3623878655]	auto[1]	13	1			T123	1		T270	1		T275	1
auto[3623878656:3758096383]	auto[0]	137	1			T42	1		T25	1		T93	1
auto[3623878656:3758096383]	auto[1]	4	1			T42	1		T309	1		T437	1
auto[3758096384:3892314111]	auto[0]	132	1			T15	1		T16	2		T42	1
auto[3758096384:3892314111]	auto[1]	8	1			T123	1		T270	1		T309	1
auto[3892314112:4026531839]	auto[0]	131	1			T29	1		T25	1		T108	2
auto[3892314112:4026531839]	auto[1]	8	1			T126	1		T128	1		T345	1
auto[4026531840:4160749567]	auto[0]	114	1			T28	1		T41	1		T25	1
auto[4026531840:4160749567]	auto[1]	5	1			T42	1		T141	1		T124	1
auto[4160749568:4294967295]	auto[0]	162	1			T41	2		T108	2		T93	1
auto[4160749568:4294967295]	auto[1]	13	1			T42	1		T85	1		T216	2