Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.83 99.07 98.10 98.53 100.00 99.11 98.41 91.58


Total test records in report: 1072
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T1005 /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.1763013510 Feb 29 01:10:39 PM PST 24 Feb 29 01:10:40 PM PST 24 129188124 ps
T1006 /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.1477894146 Feb 29 01:10:17 PM PST 24 Feb 29 01:10:19 PM PST 24 570247452 ps
T1007 /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.1615228602 Feb 29 01:10:34 PM PST 24 Feb 29 01:10:35 PM PST 24 121448242 ps
T1008 /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.3690328523 Feb 29 01:10:18 PM PST 24 Feb 29 01:10:20 PM PST 24 379515814 ps
T1009 /workspace/coverage/cover_reg_top/26.keymgr_intr_test.1535082944 Feb 29 01:10:41 PM PST 24 Feb 29 01:10:42 PM PST 24 11166847 ps
T157 /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.1669714305 Feb 29 01:10:39 PM PST 24 Feb 29 01:10:43 PM PST 24 104292654 ps
T1010 /workspace/coverage/cover_reg_top/40.keymgr_intr_test.1720570890 Feb 29 01:10:55 PM PST 24 Feb 29 01:10:57 PM PST 24 53777551 ps
T1011 /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.3174573077 Feb 29 01:10:04 PM PST 24 Feb 29 01:10:13 PM PST 24 657366963 ps
T1012 /workspace/coverage/cover_reg_top/7.keymgr_intr_test.870743540 Feb 29 01:10:15 PM PST 24 Feb 29 01:10:16 PM PST 24 16326967 ps
T1013 /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.2084722716 Feb 29 01:10:36 PM PST 24 Feb 29 01:10:39 PM PST 24 173339852 ps
T1014 /workspace/coverage/cover_reg_top/42.keymgr_intr_test.2078944240 Feb 29 01:10:57 PM PST 24 Feb 29 01:10:59 PM PST 24 77666118 ps
T1015 /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.4066567677 Feb 29 01:10:19 PM PST 24 Feb 29 01:10:20 PM PST 24 61676578 ps
T1016 /workspace/coverage/cover_reg_top/27.keymgr_intr_test.1042163772 Feb 29 01:10:39 PM PST 24 Feb 29 01:10:40 PM PST 24 43601225 ps
T1017 /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.1244060836 Feb 29 01:10:40 PM PST 24 Feb 29 01:10:43 PM PST 24 236373676 ps
T1018 /workspace/coverage/cover_reg_top/37.keymgr_intr_test.4002929113 Feb 29 01:10:56 PM PST 24 Feb 29 01:10:58 PM PST 24 48576642 ps
T1019 /workspace/coverage/cover_reg_top/2.keymgr_intr_test.246609654 Feb 29 01:10:04 PM PST 24 Feb 29 01:10:05 PM PST 24 19508305 ps
T1020 /workspace/coverage/cover_reg_top/41.keymgr_intr_test.2798720819 Feb 29 01:10:56 PM PST 24 Feb 29 01:10:58 PM PST 24 36727904 ps
T1021 /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.556834593 Feb 29 01:10:18 PM PST 24 Feb 29 01:10:25 PM PST 24 199903145 ps
T1022 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.1603003559 Feb 29 01:10:36 PM PST 24 Feb 29 01:10:41 PM PST 24 885967641 ps
T1023 /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.3995040324 Feb 29 01:10:05 PM PST 24 Feb 29 01:10:06 PM PST 24 23616214 ps
T1024 /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.2828787415 Feb 29 01:10:19 PM PST 24 Feb 29 01:10:25 PM PST 24 290030780 ps
T1025 /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.3758589780 Feb 29 01:10:20 PM PST 24 Feb 29 01:10:22 PM PST 24 258814552 ps
T1026 /workspace/coverage/cover_reg_top/28.keymgr_intr_test.2976554897 Feb 29 01:10:55 PM PST 24 Feb 29 01:10:57 PM PST 24 9068939 ps
T1027 /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.1667585321 Feb 29 01:10:02 PM PST 24 Feb 29 01:10:11 PM PST 24 903823587 ps
T1028 /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.1396186979 Feb 29 01:10:34 PM PST 24 Feb 29 01:10:38 PM PST 24 469570219 ps
T1029 /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.655823565 Feb 29 01:10:07 PM PST 24 Feb 29 01:10:08 PM PST 24 29145724 ps
T1030 /workspace/coverage/cover_reg_top/25.keymgr_intr_test.394206801 Feb 29 01:10:38 PM PST 24 Feb 29 01:10:39 PM PST 24 69639769 ps
T1031 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.1788569193 Feb 29 01:10:40 PM PST 24 Feb 29 01:10:45 PM PST 24 436911513 ps
T1032 /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.2276433283 Feb 29 01:10:26 PM PST 24 Feb 29 01:10:28 PM PST 24 43088782 ps
T1033 /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.761557895 Feb 29 01:10:18 PM PST 24 Feb 29 01:10:19 PM PST 24 25635755 ps
T160 /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.3251018426 Feb 29 01:10:38 PM PST 24 Feb 29 01:10:48 PM PST 24 862976441 ps
T1034 /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.303325913 Feb 29 01:10:35 PM PST 24 Feb 29 01:10:36 PM PST 24 38997704 ps
T1035 /workspace/coverage/cover_reg_top/48.keymgr_intr_test.3333002777 Feb 29 01:10:55 PM PST 24 Feb 29 01:10:58 PM PST 24 38118503 ps
T1036 /workspace/coverage/cover_reg_top/30.keymgr_intr_test.4169669746 Feb 29 01:10:56 PM PST 24 Feb 29 01:10:59 PM PST 24 10480314 ps
T1037 /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.1037173404 Feb 29 01:10:10 PM PST 24 Feb 29 01:10:13 PM PST 24 518561052 ps
T1038 /workspace/coverage/cover_reg_top/23.keymgr_intr_test.1605423387 Feb 29 01:10:41 PM PST 24 Feb 29 01:10:42 PM PST 24 31365622 ps
T1039 /workspace/coverage/cover_reg_top/15.keymgr_intr_test.3327288778 Feb 29 01:10:38 PM PST 24 Feb 29 01:10:39 PM PST 24 65628198 ps
T1040 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.2848830604 Feb 29 01:10:35 PM PST 24 Feb 29 01:10:38 PM PST 24 289905583 ps
T1041 /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.3614428882 Feb 29 01:10:40 PM PST 24 Feb 29 01:10:42 PM PST 24 70714353 ps
T1042 /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.1064203786 Feb 29 01:10:15 PM PST 24 Feb 29 01:10:25 PM PST 24 2726607792 ps
T1043 /workspace/coverage/cover_reg_top/18.keymgr_intr_test.914516686 Feb 29 01:10:40 PM PST 24 Feb 29 01:10:41 PM PST 24 35943482 ps
T1044 /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.4209361424 Feb 29 01:10:04 PM PST 24 Feb 29 01:10:07 PM PST 24 250719253 ps
T1045 /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.1604224369 Feb 29 01:10:03 PM PST 24 Feb 29 01:10:21 PM PST 24 5359238901 ps
T1046 /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.304848674 Feb 29 01:10:04 PM PST 24 Feb 29 01:10:08 PM PST 24 236662227 ps
T1047 /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.855158274 Feb 29 01:10:22 PM PST 24 Feb 29 01:10:25 PM PST 24 1771937668 ps
T1048 /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.1656277456 Feb 29 01:10:05 PM PST 24 Feb 29 01:10:07 PM PST 24 160157024 ps
T1049 /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.4031034742 Feb 29 01:10:22 PM PST 24 Feb 29 01:10:24 PM PST 24 402861949 ps
T1050 /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.211587726 Feb 29 01:10:17 PM PST 24 Feb 29 01:10:19 PM PST 24 44541725 ps
T1051 /workspace/coverage/cover_reg_top/47.keymgr_intr_test.1728277564 Feb 29 01:10:56 PM PST 24 Feb 29 01:10:59 PM PST 24 9134431 ps
T1052 /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.565808469 Feb 29 01:10:07 PM PST 24 Feb 29 01:10:10 PM PST 24 102688720 ps
T1053 /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.155443117 Feb 29 01:10:17 PM PST 24 Feb 29 01:10:19 PM PST 24 110827610 ps
T1054 /workspace/coverage/cover_reg_top/34.keymgr_intr_test.2189961015 Feb 29 01:10:54 PM PST 24 Feb 29 01:10:57 PM PST 24 11316569 ps
T1055 /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.1815515650 Feb 29 01:10:21 PM PST 24 Feb 29 01:10:24 PM PST 24 1592220796 ps
T1056 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.497403678 Feb 29 01:10:34 PM PST 24 Feb 29 01:10:48 PM PST 24 1294309434 ps
T1057 /workspace/coverage/cover_reg_top/14.keymgr_intr_test.1156403048 Feb 29 01:10:39 PM PST 24 Feb 29 01:10:40 PM PST 24 48937639 ps
T1058 /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.3001044770 Feb 29 01:10:15 PM PST 24 Feb 29 01:10:17 PM PST 24 95065212 ps
T159 /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.1621909194 Feb 29 01:10:37 PM PST 24 Feb 29 01:10:48 PM PST 24 1551275278 ps
T1059 /workspace/coverage/cover_reg_top/44.keymgr_intr_test.1396624321 Feb 29 01:10:56 PM PST 24 Feb 29 01:10:59 PM PST 24 37130201 ps
T164 /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.1299634366 Feb 29 01:10:40 PM PST 24 Feb 29 01:10:47 PM PST 24 151129205 ps
T1060 /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.134887878 Feb 29 01:10:38 PM PST 24 Feb 29 01:10:40 PM PST 24 534084425 ps
T1061 /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.1523503779 Feb 29 01:10:07 PM PST 24 Feb 29 01:10:11 PM PST 24 80566257 ps
T1062 /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.1589754035 Feb 29 01:10:21 PM PST 24 Feb 29 01:10:22 PM PST 24 59521978 ps
T1063 /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.463850129 Feb 29 01:10:19 PM PST 24 Feb 29 01:10:20 PM PST 24 155819797 ps
T1064 /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.2383286388 Feb 29 01:10:16 PM PST 24 Feb 29 01:10:18 PM PST 24 82334657 ps
T1065 /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.2314904736 Feb 29 01:10:37 PM PST 24 Feb 29 01:10:39 PM PST 24 330279927 ps
T1066 /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.4057401939 Feb 29 01:10:06 PM PST 24 Feb 29 01:10:07 PM PST 24 22042074 ps
T1067 /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.3806982045 Feb 29 01:10:02 PM PST 24 Feb 29 01:10:03 PM PST 24 22545533 ps
T1068 /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.2539681091 Feb 29 01:10:01 PM PST 24 Feb 29 01:10:04 PM PST 24 120424208 ps
T1069 /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.2676601930 Feb 29 01:10:18 PM PST 24 Feb 29 01:10:20 PM PST 24 21122912 ps
T1070 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.4288823812 Feb 29 01:10:41 PM PST 24 Feb 29 01:10:50 PM PST 24 171060110 ps
T1071 /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.1691332774 Feb 29 01:10:20 PM PST 24 Feb 29 01:10:28 PM PST 24 768126933 ps
T1072 /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.1458593810 Feb 29 01:10:38 PM PST 24 Feb 29 01:10:43 PM PST 24 308917641 ps

Test location /workspace/coverage/default/19.keymgr_stress_all_with_rand_reset.2150854763
Short name T15
Test name
Test status
Simulation time 939066201 ps
CPU time 10.58 seconds
Started Feb 29 02:03:13 PM PST 24
Finished Feb 29 02:03:24 PM PST 24
Peak memory 221984 kb
Host smart-168ca61e-1654-4658-ab23-faa57aca7451
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2150854763 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all_with_rand_reset.2150854763
Directory /workspace/19.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.441160599
Short name T12
Test name
Test status
Simulation time 1658216901 ps
CPU time 22.73 seconds
Started Feb 29 02:03:20 PM PST 24
Finished Feb 29 02:03:44 PM PST 24
Peak memory 221808 kb
Host smart-194b5cc7-4579-43fd-bfc5-6d34e6e6462b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=441160599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.441160599
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.1958463880
Short name T41
Test name
Test status
Simulation time 118023503 ps
CPU time 5.62 seconds
Started Feb 29 02:03:42 PM PST 24
Finished Feb 29 02:03:48 PM PST 24
Peak memory 221780 kb
Host smart-ebf8fd55-a7a5-4d99-8759-b09e9ae013b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958463880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.1958463880
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_stress_all_with_rand_reset.3809287256
Short name T7
Test name
Test status
Simulation time 270971014 ps
CPU time 17.4 seconds
Started Feb 29 02:04:16 PM PST 24
Finished Feb 29 02:04:33 PM PST 24
Peak memory 222792 kb
Host smart-31a0b7b0-3f23-4969-9623-061631f4c4a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809287256 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all_with_rand_reset.3809287256
Directory /workspace/32.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.677406425
Short name T6
Test name
Test status
Simulation time 664313338 ps
CPU time 22.19 seconds
Started Feb 29 02:01:22 PM PST 24
Finished Feb 29 02:01:44 PM PST 24
Peak memory 232544 kb
Host smart-b3c2488b-a0ef-4c88-a29d-dd0bcd862fb6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677406425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.677406425
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.3023023844
Short name T42
Test name
Test status
Simulation time 1456005876 ps
CPU time 38.39 seconds
Started Feb 29 02:01:57 PM PST 24
Finished Feb 29 02:02:36 PM PST 24
Peak memory 214052 kb
Host smart-48b5ecbe-5bb0-4d25-ba2f-9ead1fcc3d4a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3023023844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.3023023844
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.2093632940
Short name T55
Test name
Test status
Simulation time 2080394612 ps
CPU time 56.16 seconds
Started Feb 29 02:01:14 PM PST 24
Finished Feb 29 02:02:10 PM PST 24
Peak memory 221852 kb
Host smart-30848979-d922-4684-a2cc-cd3e18fa249d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093632940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.2093632940
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.1384340725
Short name T152
Test name
Test status
Simulation time 1187312206 ps
CPU time 25.99 seconds
Started Feb 29 01:10:07 PM PST 24
Finished Feb 29 01:10:33 PM PST 24
Peak memory 221876 kb
Host smart-09198c95-8094-4bf2-ae30-3241d5fd71a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384340725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.1384340725
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/20.keymgr_stress_all_with_rand_reset.701620358
Short name T49
Test name
Test status
Simulation time 416255287 ps
CPU time 17.95 seconds
Started Feb 29 02:03:12 PM PST 24
Finished Feb 29 02:03:31 PM PST 24
Peak memory 222120 kb
Host smart-d93cdee9-a109-469f-999a-3568e32bd538
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=701620358 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all_with_rand_reset.701620358
Directory /workspace/20.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.3848668163
Short name T8
Test name
Test status
Simulation time 22131106187 ps
CPU time 284.96 seconds
Started Feb 29 02:05:10 PM PST 24
Finished Feb 29 02:09:55 PM PST 24
Peak memory 221908 kb
Host smart-c7677895-886d-4f0e-9b0b-aa7ed3a5fd0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3848668163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.3848668163
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.2828177982
Short name T62
Test name
Test status
Simulation time 402111873 ps
CPU time 19 seconds
Started Feb 29 02:04:31 PM PST 24
Finished Feb 29 02:04:50 PM PST 24
Peak memory 214872 kb
Host smart-beaac02b-cbe0-4099-bc13-294869141d8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828177982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.2828177982
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.1528549901
Short name T9
Test name
Test status
Simulation time 45426661 ps
CPU time 2.59 seconds
Started Feb 29 02:05:20 PM PST 24
Finished Feb 29 02:05:23 PM PST 24
Peak memory 207204 kb
Host smart-b53084db-2cd8-47d1-b684-e6244e746937
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1528549901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.1528549901
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.3381581501
Short name T27
Test name
Test status
Simulation time 43177492 ps
CPU time 2.89 seconds
Started Feb 29 02:04:02 PM PST 24
Finished Feb 29 02:04:05 PM PST 24
Peak memory 220952 kb
Host smart-e5605846-7d57-4019-bd11-8b52ac34df6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381581501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.3381581501
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.1531797535
Short name T111
Test name
Test status
Simulation time 414204420 ps
CPU time 9.62 seconds
Started Feb 29 01:10:10 PM PST 24
Finished Feb 29 01:10:20 PM PST 24
Peak memory 213924 kb
Host smart-7f008745-71dc-4748-acf1-db60129951b3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531797535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.1531797535
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.1861438884
Short name T123
Test name
Test status
Simulation time 334932477 ps
CPU time 9.26 seconds
Started Feb 29 02:04:36 PM PST 24
Finished Feb 29 02:04:48 PM PST 24
Peak memory 213684 kb
Host smart-ed86887d-71fc-4ca2-9d8f-6c4270449c65
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1861438884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.1861438884
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.2645703074
Short name T16
Test name
Test status
Simulation time 778099246 ps
CPU time 12.81 seconds
Started Feb 29 02:04:21 PM PST 24
Finished Feb 29 02:04:34 PM PST 24
Peak memory 213672 kb
Host smart-44fd369a-bc6e-4e41-9c8b-6d876be57f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645703074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.2645703074
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.391723174
Short name T216
Test name
Test status
Simulation time 4818043428 ps
CPU time 15.86 seconds
Started Feb 29 02:04:15 PM PST 24
Finished Feb 29 02:04:31 PM PST 24
Peak memory 213728 kb
Host smart-01905087-d881-4d94-a4e1-08b1a0674ee4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=391723174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.391723174
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.1384547701
Short name T45
Test name
Test status
Simulation time 741259391 ps
CPU time 17.83 seconds
Started Feb 29 02:02:43 PM PST 24
Finished Feb 29 02:03:01 PM PST 24
Peak memory 221964 kb
Host smart-8be0327f-10dd-4097-b4ae-9097b6ef4c1a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1384547701 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.1384547701
Directory /workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.1329638980
Short name T272
Test name
Test status
Simulation time 192711215 ps
CPU time 10.54 seconds
Started Feb 29 02:04:20 PM PST 24
Finished Feb 29 02:04:31 PM PST 24
Peak memory 214688 kb
Host smart-b937f135-f0f3-44be-944f-2a731900cb3a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1329638980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.1329638980
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.3593726828
Short name T56
Test name
Test status
Simulation time 9692109129 ps
CPU time 30.47 seconds
Started Feb 29 02:05:25 PM PST 24
Finished Feb 29 02:05:56 PM PST 24
Peak memory 220672 kb
Host smart-49f6697b-87c0-4341-96ac-46333386e329
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3593726828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.3593726828
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.882480257
Short name T128
Test name
Test status
Simulation time 169342345 ps
CPU time 9.87 seconds
Started Feb 29 02:05:10 PM PST 24
Finished Feb 29 02:05:22 PM PST 24
Peak memory 213672 kb
Host smart-96bf74f8-c9ee-4432-87a4-ef7d2b33b22f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=882480257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.882480257
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.3995226560
Short name T38
Test name
Test status
Simulation time 88975473 ps
CPU time 4.32 seconds
Started Feb 29 02:01:57 PM PST 24
Finished Feb 29 02:02:02 PM PST 24
Peak memory 208976 kb
Host smart-b1d674be-bb6f-474f-b0ad-ad881bbb680f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3995226560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.3995226560
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.2945940502
Short name T22
Test name
Test status
Simulation time 96912988 ps
CPU time 4.57 seconds
Started Feb 29 02:05:09 PM PST 24
Finished Feb 29 02:05:15 PM PST 24
Peak memory 213612 kb
Host smart-7cbc5c82-4c0f-42a6-a7a8-53d19448b84b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945940502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.2945940502
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.2524799693
Short name T275
Test name
Test status
Simulation time 188170216 ps
CPU time 10.04 seconds
Started Feb 29 02:04:18 PM PST 24
Finished Feb 29 02:04:28 PM PST 24
Peak memory 215100 kb
Host smart-77385752-902b-4899-bc71-e2d2be9ebe50
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2524799693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.2524799693
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.2580408560
Short name T250
Test name
Test status
Simulation time 281290364 ps
CPU time 3.9 seconds
Started Feb 29 02:03:20 PM PST 24
Finished Feb 29 02:03:25 PM PST 24
Peak memory 213624 kb
Host smart-7e761000-faca-4b50-9c4e-b3842fd3d17b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580408560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.2580408560
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.268935293
Short name T85
Test name
Test status
Simulation time 2053412741 ps
CPU time 106.29 seconds
Started Feb 29 02:05:09 PM PST 24
Finished Feb 29 02:06:56 PM PST 24
Peak memory 213912 kb
Host smart-63187467-17ba-4ec1-bc54-9461728c07fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=268935293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.268935293
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.1268460623
Short name T101
Test name
Test status
Simulation time 895265515 ps
CPU time 6.7 seconds
Started Feb 29 02:05:08 PM PST 24
Finished Feb 29 02:05:15 PM PST 24
Peak memory 221884 kb
Host smart-f306083b-612d-4338-931e-1da6da23bd7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268460623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.1268460623
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.436678320
Short name T965
Test name
Test status
Simulation time 79242097 ps
CPU time 3.88 seconds
Started Feb 29 01:10:26 PM PST 24
Finished Feb 29 01:10:30 PM PST 24
Peak memory 213896 kb
Host smart-f3c782d0-b2c6-471a-a272-72dee29cd129
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436678320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
keymgr_shadow_reg_errors_with_csr_rw.436678320
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.3499320183
Short name T21
Test name
Test status
Simulation time 39108595 ps
CPU time 2.5 seconds
Started Feb 29 02:03:00 PM PST 24
Finished Feb 29 02:03:03 PM PST 24
Peak memory 214148 kb
Host smart-a842f952-0e66-4922-9668-2ea4cae63c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3499320183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.3499320183
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.3134948208
Short name T5
Test name
Test status
Simulation time 327093972 ps
CPU time 2.42 seconds
Started Feb 29 02:02:06 PM PST 24
Finished Feb 29 02:02:08 PM PST 24
Peak memory 209600 kb
Host smart-dd75f7e6-d8ed-43c8-a3f7-acfd2d3ceb55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134948208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.3134948208
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.3382507835
Short name T310
Test name
Test status
Simulation time 1387805848 ps
CPU time 75.19 seconds
Started Feb 29 02:03:32 PM PST 24
Finished Feb 29 02:04:47 PM PST 24
Peak memory 215216 kb
Host smart-63148db7-9042-4203-9530-9234913a8a6a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3382507835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.3382507835
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.184588542
Short name T81
Test name
Test status
Simulation time 1545856843 ps
CPU time 40.34 seconds
Started Feb 29 02:05:21 PM PST 24
Finished Feb 29 02:06:02 PM PST 24
Peak memory 214964 kb
Host smart-5f94130c-88b3-496b-9c9c-40aa69c576bf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=184588542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.184588542
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.1623016752
Short name T149
Test name
Test status
Simulation time 1251149790 ps
CPU time 4.34 seconds
Started Feb 29 02:05:18 PM PST 24
Finished Feb 29 02:05:23 PM PST 24
Peak memory 216820 kb
Host smart-6971d504-8ddb-4221-b1fc-9ece6d1856d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623016752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.1623016752
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.874011260
Short name T256
Test name
Test status
Simulation time 1184249467 ps
CPU time 49.55 seconds
Started Feb 29 02:03:14 PM PST 24
Finished Feb 29 02:04:04 PM PST 24
Peak memory 216208 kb
Host smart-619ccf44-9860-4fac-b06c-b4142b84b8fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874011260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.874011260
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.990763333
Short name T320
Test name
Test status
Simulation time 6616125586 ps
CPU time 66.36 seconds
Started Feb 29 02:05:25 PM PST 24
Finished Feb 29 02:06:31 PM PST 24
Peak memory 215348 kb
Host smart-71bd1df7-96c2-446b-b16d-3c89b90364e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990763333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.990763333
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.586814805
Short name T168
Test name
Test status
Simulation time 420058666 ps
CPU time 8.73 seconds
Started Feb 29 01:10:04 PM PST 24
Finished Feb 29 01:10:13 PM PST 24
Peak memory 209152 kb
Host smart-f2ce0150-1452-40d7-abb6-90108d4d6ca9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586814805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err.
586814805
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.702136644
Short name T462
Test name
Test status
Simulation time 16812919 ps
CPU time 0.73 seconds
Started Feb 29 02:02:10 PM PST 24
Finished Feb 29 02:02:11 PM PST 24
Peak memory 205280 kb
Host smart-03582b20-bcec-4f64-9fbf-970e090ad5f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=702136644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.702136644
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.1620063881
Short name T436
Test name
Test status
Simulation time 191174915 ps
CPU time 10.31 seconds
Started Feb 29 02:04:54 PM PST 24
Finished Feb 29 02:05:05 PM PST 24
Peak memory 214988 kb
Host smart-39b8984d-6e48-4882-83df-fdafc6d25133
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1620063881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.1620063881
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.758931638
Short name T53
Test name
Test status
Simulation time 131504637 ps
CPU time 4.98 seconds
Started Feb 29 02:02:15 PM PST 24
Finished Feb 29 02:02:21 PM PST 24
Peak memory 221712 kb
Host smart-0bd300d7-618d-4631-a1e0-a53bd7ed63f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758931638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.758931638
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.4051295032
Short name T86
Test name
Test status
Simulation time 196409531 ps
CPU time 3.43 seconds
Started Feb 29 02:02:37 PM PST 24
Finished Feb 29 02:02:41 PM PST 24
Peak memory 214456 kb
Host smart-28536a2e-2df0-4684-a5d7-151290ba05f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4051295032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.4051295032
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_random.3533166002
Short name T236
Test name
Test status
Simulation time 314479526 ps
CPU time 5.44 seconds
Started Feb 29 02:02:36 PM PST 24
Finished Feb 29 02:02:42 PM PST 24
Peak memory 209116 kb
Host smart-6ded42f1-62ad-4221-a1d1-1f149aa23398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533166002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.3533166002
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.1924367306
Short name T404
Test name
Test status
Simulation time 244964195 ps
CPU time 3.01 seconds
Started Feb 29 02:03:46 PM PST 24
Finished Feb 29 02:03:49 PM PST 24
Peak memory 207784 kb
Host smart-f55c8420-e185-47fa-9446-2d77dcc8af62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924367306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.1924367306
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.3472107268
Short name T153
Test name
Test status
Simulation time 414097143 ps
CPU time 8.36 seconds
Started Feb 29 01:10:16 PM PST 24
Finished Feb 29 01:10:25 PM PST 24
Peak memory 208848 kb
Host smart-5df14d9e-5c07-4802-a5ae-3559a9eefc98
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472107268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.3472107268
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.3266744573
Short name T260
Test name
Test status
Simulation time 7637624805 ps
CPU time 47.11 seconds
Started Feb 29 02:02:56 PM PST 24
Finished Feb 29 02:03:45 PM PST 24
Peak memory 221200 kb
Host smart-f52e29f8-c0fb-4f16-9b8c-101dc3040c21
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266744573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.3266744573
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.3964358085
Short name T281
Test name
Test status
Simulation time 144085034 ps
CPU time 5.84 seconds
Started Feb 29 02:04:18 PM PST 24
Finished Feb 29 02:04:24 PM PST 24
Peak memory 207964 kb
Host smart-ff615689-6fa0-4606-bb4e-1ce55fd00bcb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964358085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.3964358085
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.541790332
Short name T437
Test name
Test status
Simulation time 770270638 ps
CPU time 7.49 seconds
Started Feb 29 02:04:40 PM PST 24
Finished Feb 29 02:04:49 PM PST 24
Peak memory 214380 kb
Host smart-c7c1b9df-019e-4c25-8e0d-43fa5501a133
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=541790332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.541790332
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.672875237
Short name T143
Test name
Test status
Simulation time 67859006 ps
CPU time 3.66 seconds
Started Feb 29 02:02:37 PM PST 24
Finished Feb 29 02:02:40 PM PST 24
Peak memory 217412 kb
Host smart-2f53764f-f9d4-4ab9-9222-b827ff7a73c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672875237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.672875237
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.2768791374
Short name T283
Test name
Test status
Simulation time 10171266454 ps
CPU time 56.71 seconds
Started Feb 29 02:02:24 PM PST 24
Finished Feb 29 02:03:21 PM PST 24
Peak memory 221768 kb
Host smart-a91a395b-5450-451d-a7d1-4668b9591c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768791374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.2768791374
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.1783885683
Short name T251
Test name
Test status
Simulation time 16861576129 ps
CPU time 60.94 seconds
Started Feb 29 02:02:58 PM PST 24
Finished Feb 29 02:04:01 PM PST 24
Peak memory 215872 kb
Host smart-9b28c45f-a179-4199-b4b1-8990b7654c5b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1783885683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.1783885683
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.767718444
Short name T277
Test name
Test status
Simulation time 495474911 ps
CPU time 6.93 seconds
Started Feb 29 02:04:42 PM PST 24
Finished Feb 29 02:04:50 PM PST 24
Peak memory 210252 kb
Host smart-5c942f56-78a2-4846-96e5-11646636a32a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767718444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.767718444
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.1621909194
Short name T159
Test name
Test status
Simulation time 1551275278 ps
CPU time 10.57 seconds
Started Feb 29 01:10:37 PM PST 24
Finished Feb 29 01:10:48 PM PST 24
Peak memory 208908 kb
Host smart-4dc6c2b3-16ef-4988-bc6b-7d695a8234eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621909194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.1621909194
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.4008524593
Short name T174
Test name
Test status
Simulation time 4023074157 ps
CPU time 15.21 seconds
Started Feb 29 02:01:56 PM PST 24
Finished Feb 29 02:02:11 PM PST 24
Peak memory 211004 kb
Host smart-abd85dcd-1c40-48f2-8133-a65d736b45df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008524593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.4008524593
Directory /workspace/9.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.4233319334
Short name T76
Test name
Test status
Simulation time 380961743 ps
CPU time 3.54 seconds
Started Feb 29 02:04:04 PM PST 24
Finished Feb 29 02:04:08 PM PST 24
Peak memory 215928 kb
Host smart-cea9677d-c4ff-4280-9309-384ba384032d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233319334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.4233319334
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.212130486
Short name T288
Test name
Test status
Simulation time 49955396 ps
CPU time 3.81 seconds
Started Feb 29 02:02:27 PM PST 24
Finished Feb 29 02:02:31 PM PST 24
Peak memory 213988 kb
Host smart-3b445fe4-5b42-444d-a5cd-35971a22ee4a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=212130486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.212130486
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.4270195390
Short name T245
Test name
Test status
Simulation time 2176378980 ps
CPU time 29.78 seconds
Started Feb 29 02:03:26 PM PST 24
Finished Feb 29 02:03:56 PM PST 24
Peak memory 216508 kb
Host smart-bde5cd0c-c615-4145-9878-88e433613068
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270195390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.4270195390
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.3051938421
Short name T183
Test name
Test status
Simulation time 510592894 ps
CPU time 8.53 seconds
Started Feb 29 02:05:19 PM PST 24
Finished Feb 29 02:05:28 PM PST 24
Peak memory 209900 kb
Host smart-48fb4d78-98ad-4f58-8f9a-29c24316c4fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051938421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.3051938421
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.1027594060
Short name T144
Test name
Test status
Simulation time 85964894 ps
CPU time 3.65 seconds
Started Feb 29 02:01:38 PM PST 24
Finished Feb 29 02:01:42 PM PST 24
Peak memory 221968 kb
Host smart-a46c95a2-cba7-4d89-8bda-ceb0b9f12d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027594060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.1027594060
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.2952075606
Short name T110
Test name
Test status
Simulation time 294330737 ps
CPU time 3.98 seconds
Started Feb 29 01:10:06 PM PST 24
Finished Feb 29 01:10:10 PM PST 24
Peak memory 214216 kb
Host smart-365fa880-b1f9-4b20-979c-bc608296b013
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2952075606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.2952075606
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.3251018426
Short name T160
Test name
Test status
Simulation time 862976441 ps
CPU time 9.79 seconds
Started Feb 29 01:10:38 PM PST 24
Finished Feb 29 01:10:48 PM PST 24
Peak memory 208776 kb
Host smart-a5587a06-8a93-46aa-ac82-3abf3d8bd09e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251018426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.3251018426
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.404526859
Short name T147
Test name
Test status
Simulation time 61744147 ps
CPU time 4.93 seconds
Started Feb 29 02:02:20 PM PST 24
Finished Feb 29 02:02:25 PM PST 24
Peak memory 217804 kb
Host smart-42dc13cf-d8bc-4e63-894d-c47adb37c930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=404526859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.404526859
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.3888677988
Short name T109
Test name
Test status
Simulation time 79351455 ps
CPU time 3.15 seconds
Started Feb 29 02:01:01 PM PST 24
Finished Feb 29 02:01:05 PM PST 24
Peak memory 207992 kb
Host smart-57dbb37d-0adf-4c32-b33b-d604210bc4f3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3888677988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.3888677988
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.1184711866
Short name T374
Test name
Test status
Simulation time 277008305 ps
CPU time 6.06 seconds
Started Feb 29 02:04:04 PM PST 24
Finished Feb 29 02:04:10 PM PST 24
Peak memory 221832 kb
Host smart-cce9956b-573e-46fd-81e8-843ee208c142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184711866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.1184711866
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.1073163711
Short name T63
Test name
Test status
Simulation time 1521504145 ps
CPU time 29.27 seconds
Started Feb 29 02:04:00 PM PST 24
Finished Feb 29 02:04:29 PM PST 24
Peak memory 214376 kb
Host smart-f3fdd355-ed4b-469d-9434-2cf96b5cf485
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1073163711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.1073163711
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.3139362043
Short name T364
Test name
Test status
Simulation time 689043228 ps
CPU time 7.6 seconds
Started Feb 29 02:04:18 PM PST 24
Finished Feb 29 02:04:25 PM PST 24
Peak memory 208312 kb
Host smart-435caf41-110a-4f57-95a9-3bc0fb476a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139362043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.3139362043
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.1923543876
Short name T253
Test name
Test status
Simulation time 2042533890 ps
CPU time 28.78 seconds
Started Feb 29 02:04:44 PM PST 24
Finished Feb 29 02:05:14 PM PST 24
Peak memory 222004 kb
Host smart-40ccea57-b784-46ec-88e1-95bd28c09b19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1923543876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.1923543876
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.1908972396
Short name T304
Test name
Test status
Simulation time 1931411838 ps
CPU time 36.71 seconds
Started Feb 29 02:01:56 PM PST 24
Finished Feb 29 02:02:34 PM PST 24
Peak memory 214156 kb
Host smart-95aba8a7-0cc9-4e15-9805-6c91af9e552a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908972396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.1908972396
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.4086333749
Short name T150
Test name
Test status
Simulation time 353280959 ps
CPU time 11.57 seconds
Started Feb 29 01:10:17 PM PST 24
Finished Feb 29 01:10:29 PM PST 24
Peak memory 208656 kb
Host smart-98556bf2-2290-4151-a8b4-0d161ee7dae6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4086333749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.4086333749
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.4039981484
Short name T146
Test name
Test status
Simulation time 162285919 ps
CPU time 2.09 seconds
Started Feb 29 02:01:14 PM PST 24
Finished Feb 29 02:01:17 PM PST 24
Peak memory 216400 kb
Host smart-5eca863d-95b8-484a-8e99-7c1ee82b9191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039981484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.4039981484
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.848300115
Short name T359
Test name
Test status
Simulation time 7312476003 ps
CPU time 67.37 seconds
Started Feb 29 02:01:01 PM PST 24
Finished Feb 29 02:02:09 PM PST 24
Peak memory 213708 kb
Host smart-08081e81-c9f0-42a0-8817-d4df13fe2d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848300115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.848300115
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.3221765230
Short name T243
Test name
Test status
Simulation time 325642127 ps
CPU time 3.74 seconds
Started Feb 29 02:01:01 PM PST 24
Finished Feb 29 02:01:05 PM PST 24
Peak memory 219232 kb
Host smart-06899c2f-1516-4032-83b2-ee26307f8bae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221765230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.3221765230
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.4009411350
Short name T94
Test name
Test status
Simulation time 288444421 ps
CPU time 7.13 seconds
Started Feb 29 02:02:23 PM PST 24
Finished Feb 29 02:02:31 PM PST 24
Peak memory 209940 kb
Host smart-735b3723-507f-40be-a2bc-af29f32d3412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009411350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.4009411350
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.217959151
Short name T215
Test name
Test status
Simulation time 7672594691 ps
CPU time 79.92 seconds
Started Feb 29 02:02:59 PM PST 24
Finished Feb 29 02:04:20 PM PST 24
Peak memory 207732 kb
Host smart-0ac00d47-6caa-4b9b-ab7c-80338310caae
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217959151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.217959151
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.1324723177
Short name T259
Test name
Test status
Simulation time 975592128 ps
CPU time 20.63 seconds
Started Feb 29 02:01:17 PM PST 24
Finished Feb 29 02:01:38 PM PST 24
Peak memory 214872 kb
Host smart-c1c2a4af-39fd-4209-8db0-bacb11e247da
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324723177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.1324723177
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.1130199746
Short name T322
Test name
Test status
Simulation time 8779282918 ps
CPU time 68.71 seconds
Started Feb 29 02:03:13 PM PST 24
Finished Feb 29 02:04:22 PM PST 24
Peak memory 219076 kb
Host smart-52baec64-ff0d-48c1-9f15-2e8095682d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1130199746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.1130199746
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.995363944
Short name T2
Test name
Test status
Simulation time 3238695027 ps
CPU time 25.71 seconds
Started Feb 29 02:03:40 PM PST 24
Finished Feb 29 02:04:06 PM PST 24
Peak memory 208088 kb
Host smart-737b96ff-0d8f-4429-bfc9-93f2a30c0668
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=995363944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.995363944
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.3196111800
Short name T339
Test name
Test status
Simulation time 40884567 ps
CPU time 2.95 seconds
Started Feb 29 02:04:19 PM PST 24
Finished Feb 29 02:04:22 PM PST 24
Peak memory 210980 kb
Host smart-e6bb109c-125f-422e-b04a-aac5c85a1ac4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196111800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.3196111800
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.1942201848
Short name T378
Test name
Test status
Simulation time 5079389141 ps
CPU time 136.91 seconds
Started Feb 29 02:04:22 PM PST 24
Finished Feb 29 02:06:39 PM PST 24
Peak memory 221840 kb
Host smart-fb4ed551-5b17-4fc8-b7f0-2a64dc6382f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1942201848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.1942201848
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.3859390760
Short name T381
Test name
Test status
Simulation time 579937891 ps
CPU time 3.79 seconds
Started Feb 29 02:04:41 PM PST 24
Finished Feb 29 02:04:45 PM PST 24
Peak memory 206068 kb
Host smart-ca3df602-7f38-4194-91db-f62d25c33975
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859390760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.3859390760
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.1669714305
Short name T157
Test name
Test status
Simulation time 104292654 ps
CPU time 3.8 seconds
Started Feb 29 01:10:39 PM PST 24
Finished Feb 29 01:10:43 PM PST 24
Peak memory 209104 kb
Host smart-708b2ea7-13e2-4acb-9ab1-6b40c3ee345b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669714305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.1669714305
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.102284106
Short name T170
Test name
Test status
Simulation time 3118417819 ps
CPU time 28.28 seconds
Started Feb 29 01:10:41 PM PST 24
Finished Feb 29 01:11:09 PM PST 24
Peak memory 213908 kb
Host smart-7f555259-05ee-441e-8a8a-e8e7630f53d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102284106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_err
.102284106
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.3417589241
Short name T155
Test name
Test status
Simulation time 681000482 ps
CPU time 6.4 seconds
Started Feb 29 01:10:04 PM PST 24
Finished Feb 29 01:10:11 PM PST 24
Peak memory 209012 kb
Host smart-2e8d20b8-db8b-45fe-9cf6-4409ddcf0bdf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417589241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err
.3417589241
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.2288370766
Short name T166
Test name
Test status
Simulation time 695388068 ps
CPU time 8.61 seconds
Started Feb 29 01:10:21 PM PST 24
Finished Feb 29 01:10:30 PM PST 24
Peak memory 213688 kb
Host smart-8967a550-bc03-4c99-be4d-381a5845d097
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2288370766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.2288370766
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.1245749762
Short name T145
Test name
Test status
Simulation time 3192089753 ps
CPU time 7.14 seconds
Started Feb 29 02:04:35 PM PST 24
Finished Feb 29 02:04:43 PM PST 24
Peak memory 222088 kb
Host smart-8fa98ded-c31a-4d80-9294-4e53cc799ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245749762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.1245749762
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.1842581193
Short name T905
Test name
Test status
Simulation time 10545947499 ps
CPU time 344.29 seconds
Started Feb 29 02:00:59 PM PST 24
Finished Feb 29 02:06:44 PM PST 24
Peak memory 221852 kb
Host smart-9b1907ce-0de9-4f7f-84cc-9d82372072f0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1842581193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.1842581193
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.3663101989
Short name T233
Test name
Test status
Simulation time 62192015 ps
CPU time 2.68 seconds
Started Feb 29 02:01:03 PM PST 24
Finished Feb 29 02:01:06 PM PST 24
Peak memory 211120 kb
Host smart-f6c0ec73-17f7-48ec-9c36-f4a667552c22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663101989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.3663101989
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.3119741561
Short name T79
Test name
Test status
Simulation time 81528625567 ps
CPU time 184.31 seconds
Started Feb 29 02:01:02 PM PST 24
Finished Feb 29 02:04:07 PM PST 24
Peak memory 215576 kb
Host smart-77b3740b-7aaf-4b95-9300-b759c5fa84bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3119741561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.3119741561
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.3185509573
Short name T213
Test name
Test status
Simulation time 250963106 ps
CPU time 2.9 seconds
Started Feb 29 02:01:02 PM PST 24
Finished Feb 29 02:01:06 PM PST 24
Peak memory 209092 kb
Host smart-5aa13f21-5ccb-4328-ab9c-490ee74535f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185509573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.3185509573
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.2769741600
Short name T264
Test name
Test status
Simulation time 39961717 ps
CPU time 3.11 seconds
Started Feb 29 02:02:10 PM PST 24
Finished Feb 29 02:02:13 PM PST 24
Peak memory 214544 kb
Host smart-e6e3981b-8867-4ab0-a8aa-530a1f97735e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2769741600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.2769741600
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.3450873751
Short name T358
Test name
Test status
Simulation time 81191820 ps
CPU time 3.5 seconds
Started Feb 29 02:02:11 PM PST 24
Finished Feb 29 02:02:15 PM PST 24
Peak memory 209276 kb
Host smart-6a603447-7bc4-4d96-8b05-fcca45cfaae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450873751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.3450873751
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_random.4184155242
Short name T269
Test name
Test status
Simulation time 61637739 ps
CPU time 4.21 seconds
Started Feb 29 02:02:02 PM PST 24
Finished Feb 29 02:02:07 PM PST 24
Peak memory 209144 kb
Host smart-1ec36ea9-1255-4f4b-ae72-28705c45240a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184155242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.4184155242
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.1055661859
Short name T51
Test name
Test status
Simulation time 2303222483 ps
CPU time 75.77 seconds
Started Feb 29 02:02:09 PM PST 24
Finished Feb 29 02:03:25 PM PST 24
Peak memory 214420 kb
Host smart-40b629a0-5e95-4d4e-a143-4a318990d082
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055661859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.1055661859
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.1823926042
Short name T331
Test name
Test status
Simulation time 247349772 ps
CPU time 5.4 seconds
Started Feb 29 02:02:17 PM PST 24
Finished Feb 29 02:02:24 PM PST 24
Peak memory 214792 kb
Host smart-17d8f6e4-f9ec-47bf-b068-c593b1911a67
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1823926042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.1823926042
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.1898013471
Short name T337
Test name
Test status
Simulation time 44173111 ps
CPU time 3.18 seconds
Started Feb 29 02:02:59 PM PST 24
Finished Feb 29 02:03:03 PM PST 24
Peak memory 214488 kb
Host smart-686eafed-e3a1-4504-a619-155dc2af00a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1898013471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.1898013471
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_stress_all_with_rand_reset.3245344724
Short name T121
Test name
Test status
Simulation time 240259966 ps
CPU time 13.02 seconds
Started Feb 29 02:01:13 PM PST 24
Finished Feb 29 02:01:27 PM PST 24
Peak memory 222080 kb
Host smart-7cee4d2c-9699-4678-bd0d-287e4ab145fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245344724 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all_with_rand_reset.3245344724
Directory /workspace/2.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.2584041895
Short name T387
Test name
Test status
Simulation time 185915247 ps
CPU time 7.9 seconds
Started Feb 29 02:03:19 PM PST 24
Finished Feb 29 02:03:27 PM PST 24
Peak memory 213556 kb
Host smart-4115de79-7636-4676-b5cc-3ac34de6465f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2584041895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.2584041895
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.3005858826
Short name T103
Test name
Test status
Simulation time 837292665 ps
CPU time 7.64 seconds
Started Feb 29 02:04:03 PM PST 24
Finished Feb 29 02:04:11 PM PST 24
Peak memory 213668 kb
Host smart-9940bda9-c7d2-48b1-b044-c8d48531189f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005858826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.3005858826
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.3340416066
Short name T367
Test name
Test status
Simulation time 756974121 ps
CPU time 3.43 seconds
Started Feb 29 02:04:20 PM PST 24
Finished Feb 29 02:04:23 PM PST 24
Peak memory 207276 kb
Host smart-fb80ac96-a5a8-4691-b770-9a43903afddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340416066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.3340416066
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.1161633864
Short name T261
Test name
Test status
Simulation time 3066273241 ps
CPU time 17.44 seconds
Started Feb 29 02:04:20 PM PST 24
Finished Feb 29 02:04:38 PM PST 24
Peak memory 221860 kb
Host smart-f785d929-23bb-4e6e-9885-c90c9bf4a02f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161633864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.1161633864
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.4286718020
Short name T242
Test name
Test status
Simulation time 1220938538 ps
CPU time 41.55 seconds
Started Feb 29 02:04:34 PM PST 24
Finished Feb 29 02:05:17 PM PST 24
Peak memory 214528 kb
Host smart-b14b0d7b-cf26-416d-a51a-e3b5008b5d10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286718020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.4286718020
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_stress_all_with_rand_reset.2989242247
Short name T819
Test name
Test status
Simulation time 1305480554 ps
CPU time 19.83 seconds
Started Feb 29 02:05:11 PM PST 24
Finished Feb 29 02:05:33 PM PST 24
Peak memory 222016 kb
Host smart-7c752e3d-a10c-4d6b-baa4-8a35e8de123b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989242247 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all_with_rand_reset.2989242247
Directory /workspace/44.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.1766847639
Short name T279
Test name
Test status
Simulation time 212148390 ps
CPU time 5.56 seconds
Started Feb 29 02:01:55 PM PST 24
Finished Feb 29 02:02:01 PM PST 24
Peak memory 209740 kb
Host smart-901e14e8-6d5c-4b5a-9c10-4369b4930cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766847639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.1766847639
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.1410303944
Short name T148
Test name
Test status
Simulation time 323765108 ps
CPU time 3.78 seconds
Started Feb 29 02:00:51 PM PST 24
Finished Feb 29 02:00:57 PM PST 24
Peak memory 217188 kb
Host smart-50c135cb-8060-41c4-bf22-af5fd44efbfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1410303944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.1410303944
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.304848674
Short name T1046
Test name
Test status
Simulation time 236662227 ps
CPU time 3.96 seconds
Started Feb 29 01:10:04 PM PST 24
Finished Feb 29 01:10:08 PM PST 24
Peak memory 205564 kb
Host smart-5c7d81b0-541c-4826-b29c-8d29bced3e83
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304848674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.304848674
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.1667585321
Short name T1027
Test name
Test status
Simulation time 903823587 ps
CPU time 8.62 seconds
Started Feb 29 01:10:02 PM PST 24
Finished Feb 29 01:10:11 PM PST 24
Peak memory 205492 kb
Host smart-0a916906-4a51-4948-9837-58332eb85d5b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667585321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.1
667585321
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.3806982045
Short name T1067
Test name
Test status
Simulation time 22545533 ps
CPU time 1.06 seconds
Started Feb 29 01:10:02 PM PST 24
Finished Feb 29 01:10:03 PM PST 24
Peak memory 205472 kb
Host smart-213d31f1-da14-48b7-81a4-bb72a1928f8e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806982045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.3
806982045
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.4199702865
Short name T941
Test name
Test status
Simulation time 147590816 ps
CPU time 1.23 seconds
Started Feb 29 01:10:05 PM PST 24
Finished Feb 29 01:10:06 PM PST 24
Peak memory 213840 kb
Host smart-ebce1e2a-6db2-46cf-b7aa-bb2fb1d44243
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199702865 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.4199702865
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.4057401939
Short name T1066
Test name
Test status
Simulation time 22042074 ps
CPU time 0.9 seconds
Started Feb 29 01:10:06 PM PST 24
Finished Feb 29 01:10:07 PM PST 24
Peak memory 205576 kb
Host smart-4e6d96f5-fc1e-41f5-82d4-ff8f758e7692
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4057401939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.4057401939
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.155957076
Short name T969
Test name
Test status
Simulation time 46522886 ps
CPU time 0.67 seconds
Started Feb 29 01:10:03 PM PST 24
Finished Feb 29 01:10:04 PM PST 24
Peak memory 205360 kb
Host smart-9e7f2f42-4e61-4a95-8adf-e1fd631bdf8e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155957076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.155957076
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.753872351
Short name T132
Test name
Test status
Simulation time 322613898 ps
CPU time 2.43 seconds
Started Feb 29 01:10:06 PM PST 24
Finished Feb 29 01:10:09 PM PST 24
Peak memory 205480 kb
Host smart-6f6d0e01-10ee-47e3-90fd-a03fe571ee9e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753872351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sam
e_csr_outstanding.753872351
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.3956270756
Short name T980
Test name
Test status
Simulation time 615022699 ps
CPU time 4.93 seconds
Started Feb 29 01:10:06 PM PST 24
Finished Feb 29 01:10:11 PM PST 24
Peak memory 213932 kb
Host smart-e150f1b8-c452-44c3-a1b9-d3c445ed6843
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956270756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
keymgr_shadow_reg_errors_with_csr_rw.3956270756
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.866321646
Short name T910
Test name
Test status
Simulation time 171476852 ps
CPU time 1.94 seconds
Started Feb 29 01:10:04 PM PST 24
Finished Feb 29 01:10:06 PM PST 24
Peak memory 213704 kb
Host smart-091cc6a0-07b2-49c8-95dc-465cffea6e18
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866321646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.866321646
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.1422735768
Short name T173
Test name
Test status
Simulation time 223733965 ps
CPU time 8.56 seconds
Started Feb 29 01:10:04 PM PST 24
Finished Feb 29 01:10:13 PM PST 24
Peak memory 209252 kb
Host smart-2a1919a7-b89d-4170-a1a0-f60455d19c24
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1422735768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.1422735768
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.3820991778
Short name T135
Test name
Test status
Simulation time 1492494065 ps
CPU time 9.79 seconds
Started Feb 29 01:10:06 PM PST 24
Finished Feb 29 01:10:16 PM PST 24
Peak memory 205500 kb
Host smart-14daf321-1c19-41c6-97dd-81188694a0d4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820991778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.3
820991778
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.1604224369
Short name T1045
Test name
Test status
Simulation time 5359238901 ps
CPU time 18.02 seconds
Started Feb 29 01:10:03 PM PST 24
Finished Feb 29 01:10:21 PM PST 24
Peak memory 205588 kb
Host smart-a8429911-6d0d-4e25-ab3b-b7499b1696f5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604224369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.1
604224369
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.137823480
Short name T997
Test name
Test status
Simulation time 23868281 ps
CPU time 1.01 seconds
Started Feb 29 01:10:06 PM PST 24
Finished Feb 29 01:10:07 PM PST 24
Peak memory 205436 kb
Host smart-edcbbb00-ef60-4812-ace6-676b4847ecce
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=137823480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.137823480
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.3964901344
Short name T989
Test name
Test status
Simulation time 38497212 ps
CPU time 1.75 seconds
Started Feb 29 01:10:03 PM PST 24
Finished Feb 29 01:10:05 PM PST 24
Peak memory 205656 kb
Host smart-6fb2c06c-1b7f-437e-a294-96b5f76e658d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3964901344 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.3964901344
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.4218621561
Short name T943
Test name
Test status
Simulation time 108441362 ps
CPU time 0.98 seconds
Started Feb 29 01:10:04 PM PST 24
Finished Feb 29 01:10:05 PM PST 24
Peak memory 205432 kb
Host smart-6b429de5-8bd8-4c14-859c-3f0a5383fa2c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4218621561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.4218621561
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.3886136489
Short name T923
Test name
Test status
Simulation time 23336030 ps
CPU time 0.72 seconds
Started Feb 29 01:10:02 PM PST 24
Finished Feb 29 01:10:03 PM PST 24
Peak memory 205292 kb
Host smart-cec1971c-2764-4c2b-9539-750b21810942
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886136489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.3886136489
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.565808469
Short name T1052
Test name
Test status
Simulation time 102688720 ps
CPU time 2.52 seconds
Started Feb 29 01:10:07 PM PST 24
Finished Feb 29 01:10:10 PM PST 24
Peak memory 205612 kb
Host smart-4f626674-6a49-4fc4-988a-e56350578850
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=565808469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sam
e_csr_outstanding.565808469
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.2695756565
Short name T975
Test name
Test status
Simulation time 435956177 ps
CPU time 4.16 seconds
Started Feb 29 01:10:03 PM PST 24
Finished Feb 29 01:10:08 PM PST 24
Peak memory 218540 kb
Host smart-09fc55bf-dc08-48ea-889f-69e7913848e4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2695756565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.2695756565
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.3055002951
Short name T960
Test name
Test status
Simulation time 71167472 ps
CPU time 3.39 seconds
Started Feb 29 01:10:03 PM PST 24
Finished Feb 29 01:10:07 PM PST 24
Peak memory 222076 kb
Host smart-5d29e05f-4885-416b-ae05-5faa37e63d51
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3055002951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.3055002951
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.2539681091
Short name T1068
Test name
Test status
Simulation time 120424208 ps
CPU time 2.78 seconds
Started Feb 29 01:10:01 PM PST 24
Finished Feb 29 01:10:04 PM PST 24
Peak memory 216556 kb
Host smart-72410533-d5fe-490b-9d72-4f67bf2cfff3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539681091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.2539681091
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.4031034742
Short name T1049
Test name
Test status
Simulation time 402861949 ps
CPU time 1.15 seconds
Started Feb 29 01:10:22 PM PST 24
Finished Feb 29 01:10:24 PM PST 24
Peak memory 205572 kb
Host smart-25866990-88f9-4eec-bddd-04ac5be1f4e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4031034742 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.4031034742
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.4261123042
Short name T131
Test name
Test status
Simulation time 19001702 ps
CPU time 1.29 seconds
Started Feb 29 01:10:20 PM PST 24
Finished Feb 29 01:10:21 PM PST 24
Peak memory 205444 kb
Host smart-9709ba78-7b42-46ad-b1ea-a0739b1f0ddf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261123042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.4261123042
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.389508550
Short name T995
Test name
Test status
Simulation time 12454132 ps
CPU time 0.74 seconds
Started Feb 29 01:10:17 PM PST 24
Finished Feb 29 01:10:18 PM PST 24
Peak memory 205204 kb
Host smart-6c4de3be-95a7-4793-9aa5-d1515dc257e6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389508550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.389508550
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.202303132
Short name T134
Test name
Test status
Simulation time 51563048 ps
CPU time 1.39 seconds
Started Feb 29 01:10:20 PM PST 24
Finished Feb 29 01:10:21 PM PST 24
Peak memory 205548 kb
Host smart-e985be39-c5a1-4912-a01e-4de89cd46f87
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=202303132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_sa
me_csr_outstanding.202303132
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.3674899608
Short name T958
Test name
Test status
Simulation time 497484198 ps
CPU time 11.42 seconds
Started Feb 29 01:10:19 PM PST 24
Finished Feb 29 01:10:31 PM PST 24
Peak memory 214008 kb
Host smart-14be1fc3-cfc6-4a51-894f-da7315e7486c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3674899608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.3674899608
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.1064203786
Short name T1042
Test name
Test status
Simulation time 2726607792 ps
CPU time 9.95 seconds
Started Feb 29 01:10:15 PM PST 24
Finished Feb 29 01:10:25 PM PST 24
Peak memory 213968 kb
Host smart-a195453d-02ba-45c7-8d89-b8c9ebb5b5d1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064203786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.keymgr_shadow_reg_errors_with_csr_rw.1064203786
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.2383286388
Short name T1064
Test name
Test status
Simulation time 82334657 ps
CPU time 1.88 seconds
Started Feb 29 01:10:16 PM PST 24
Finished Feb 29 01:10:18 PM PST 24
Peak memory 215800 kb
Host smart-c1f59b68-059e-4659-be1e-08aa3e8f4777
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383286388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.2383286388
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.1603103689
Short name T151
Test name
Test status
Simulation time 195075701 ps
CPU time 6.43 seconds
Started Feb 29 01:10:19 PM PST 24
Finished Feb 29 01:10:25 PM PST 24
Peak memory 208524 kb
Host smart-12fe1dfc-0578-4c0f-affc-3378e70f4c67
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603103689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_er
r.1603103689
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.2276433283
Short name T1032
Test name
Test status
Simulation time 43088782 ps
CPU time 1.55 seconds
Started Feb 29 01:10:26 PM PST 24
Finished Feb 29 01:10:28 PM PST 24
Peak memory 205632 kb
Host smart-451ea16a-912a-4999-ab5f-9913edfdd3e8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2276433283 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.2276433283
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.3804935371
Short name T913
Test name
Test status
Simulation time 9591884 ps
CPU time 1.02 seconds
Started Feb 29 01:10:20 PM PST 24
Finished Feb 29 01:10:21 PM PST 24
Peak memory 205556 kb
Host smart-55eeead2-51b3-4ab2-9151-3411c2c24410
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804935371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.3804935371
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.2738676269
Short name T932
Test name
Test status
Simulation time 40814248 ps
CPU time 0.67 seconds
Started Feb 29 01:10:15 PM PST 24
Finished Feb 29 01:10:16 PM PST 24
Peak memory 205212 kb
Host smart-ea7b859c-e51b-4758-8058-81b3ecd4bd27
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2738676269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.2738676269
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.949825639
Short name T956
Test name
Test status
Simulation time 96736016 ps
CPU time 2.65 seconds
Started Feb 29 01:10:26 PM PST 24
Finished Feb 29 01:10:29 PM PST 24
Peak memory 205552 kb
Host smart-5eb1657e-35df-44ca-94e8-3dd294bf1127
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=949825639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_sa
me_csr_outstanding.949825639
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.1892287388
Short name T973
Test name
Test status
Simulation time 174616977 ps
CPU time 3.47 seconds
Started Feb 29 01:10:20 PM PST 24
Finished Feb 29 01:10:24 PM PST 24
Peak memory 213956 kb
Host smart-b300f916-e3fc-4c88-972a-cccd50d9067e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892287388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.1892287388
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.556834593
Short name T1021
Test name
Test status
Simulation time 199903145 ps
CPU time 6.93 seconds
Started Feb 29 01:10:18 PM PST 24
Finished Feb 29 01:10:25 PM PST 24
Peak memory 213952 kb
Host smart-eafceb77-1031-47dd-97d5-373b1369e1fd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556834593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
keymgr_shadow_reg_errors_with_csr_rw.556834593
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.1815515650
Short name T1055
Test name
Test status
Simulation time 1592220796 ps
CPU time 2.9 seconds
Started Feb 29 01:10:21 PM PST 24
Finished Feb 29 01:10:24 PM PST 24
Peak memory 215872 kb
Host smart-d897df15-f77e-49dd-adb1-00c1a2afcf52
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815515650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.1815515650
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.3933536100
Short name T162
Test name
Test status
Simulation time 1189226007 ps
CPU time 11.66 seconds
Started Feb 29 01:10:18 PM PST 24
Finished Feb 29 01:10:30 PM PST 24
Peak memory 208676 kb
Host smart-82b30b05-013e-47db-8389-41a1af7354e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933536100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.3933536100
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.3030527810
Short name T922
Test name
Test status
Simulation time 37124846 ps
CPU time 1.17 seconds
Started Feb 29 01:10:39 PM PST 24
Finished Feb 29 01:10:41 PM PST 24
Peak memory 205556 kb
Host smart-d1fb7908-c3ac-4a0e-b40a-48e25f8d27b0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030527810 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.3030527810
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.1763013510
Short name T1005
Test name
Test status
Simulation time 129188124 ps
CPU time 1.25 seconds
Started Feb 29 01:10:39 PM PST 24
Finished Feb 29 01:10:40 PM PST 24
Peak memory 205508 kb
Host smart-6db64014-a2a2-478a-94a7-65dd6ee5c7c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763013510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.1763013510
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.1045673733
Short name T1000
Test name
Test status
Simulation time 10863832 ps
CPU time 0.79 seconds
Started Feb 29 01:10:35 PM PST 24
Finished Feb 29 01:10:36 PM PST 24
Peak memory 205352 kb
Host smart-9fa377a5-71a3-464b-bc65-3df151bf4626
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1045673733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.1045673733
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.4122297285
Short name T130
Test name
Test status
Simulation time 454662686 ps
CPU time 3.72 seconds
Started Feb 29 01:10:36 PM PST 24
Finished Feb 29 01:10:40 PM PST 24
Peak memory 205576 kb
Host smart-ddd34067-df27-4e57-b1b0-b47c5107aea6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122297285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.4122297285
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.234240112
Short name T977
Test name
Test status
Simulation time 310960574 ps
CPU time 3 seconds
Started Feb 29 01:10:18 PM PST 24
Finished Feb 29 01:10:21 PM PST 24
Peak memory 213964 kb
Host smart-6d939570-42d8-45bd-8aff-a26e6a042da8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=234240112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shado
w_reg_errors.234240112
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.3614428882
Short name T1041
Test name
Test status
Simulation time 70714353 ps
CPU time 1.44 seconds
Started Feb 29 01:10:40 PM PST 24
Finished Feb 29 01:10:42 PM PST 24
Peak memory 215032 kb
Host smart-47ed7209-1701-4fd7-996f-9627d2751e97
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614428882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.3614428882
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.303325913
Short name T1034
Test name
Test status
Simulation time 38997704 ps
CPU time 1.45 seconds
Started Feb 29 01:10:35 PM PST 24
Finished Feb 29 01:10:36 PM PST 24
Peak memory 213756 kb
Host smart-aef3e26b-3130-4c2f-b91d-c814f37582a7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303325913 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.303325913
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.3384282129
Short name T936
Test name
Test status
Simulation time 13410628 ps
CPU time 1.04 seconds
Started Feb 29 01:10:38 PM PST 24
Finished Feb 29 01:10:39 PM PST 24
Peak memory 205456 kb
Host smart-c9f910b4-4c16-4be1-8ed2-fd92e8635e18
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384282129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.3384282129
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.3932387877
Short name T918
Test name
Test status
Simulation time 111225938 ps
CPU time 0.83 seconds
Started Feb 29 01:10:36 PM PST 24
Finished Feb 29 01:10:37 PM PST 24
Peak memory 205192 kb
Host smart-0a483507-03b3-4f8f-890c-94d3bf132b98
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932387877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.3932387877
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.1001505912
Short name T959
Test name
Test status
Simulation time 179322237 ps
CPU time 2.67 seconds
Started Feb 29 01:10:39 PM PST 24
Finished Feb 29 01:10:42 PM PST 24
Peak memory 205508 kb
Host smart-2ab23dc0-cf9a-4ac8-ac48-b2a41c956247
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1001505912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.1001505912
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.2848830604
Short name T1040
Test name
Test status
Simulation time 289905583 ps
CPU time 2.67 seconds
Started Feb 29 01:10:35 PM PST 24
Finished Feb 29 01:10:38 PM PST 24
Peak memory 214152 kb
Host smart-c164018b-4570-4365-9a07-04b45a41007a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848830604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.2848830604
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.497403678
Short name T1056
Test name
Test status
Simulation time 1294309434 ps
CPU time 13.68 seconds
Started Feb 29 01:10:34 PM PST 24
Finished Feb 29 01:10:48 PM PST 24
Peak memory 213760 kb
Host smart-910dc4b3-be60-4b8c-9792-29a7ae8231c0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497403678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.
keymgr_shadow_reg_errors_with_csr_rw.497403678
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.2553229673
Short name T964
Test name
Test status
Simulation time 52005523 ps
CPU time 2.77 seconds
Started Feb 29 01:10:35 PM PST 24
Finished Feb 29 01:10:38 PM PST 24
Peak memory 214052 kb
Host smart-882aa2fc-7b52-41a2-add1-565e83566cb7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2553229673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.2553229673
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.2696339453
Short name T167
Test name
Test status
Simulation time 191312509 ps
CPU time 4.78 seconds
Started Feb 29 01:10:36 PM PST 24
Finished Feb 29 01:10:41 PM PST 24
Peak memory 209244 kb
Host smart-e8626b82-09fb-4c81-a8f1-5476f3ad1a8a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696339453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er
r.2696339453
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.1094273392
Short name T972
Test name
Test status
Simulation time 119975628 ps
CPU time 2.31 seconds
Started Feb 29 01:10:38 PM PST 24
Finished Feb 29 01:10:40 PM PST 24
Peak memory 213776 kb
Host smart-ad9693da-8fd5-474e-a8d5-290865079b62
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094273392 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.1094273392
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.3625087895
Short name T136
Test name
Test status
Simulation time 37522582 ps
CPU time 1.28 seconds
Started Feb 29 01:10:39 PM PST 24
Finished Feb 29 01:10:41 PM PST 24
Peak memory 205432 kb
Host smart-f9ee3886-5e8d-4197-a777-987cb5d28fbe
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625087895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.3625087895
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.1156403048
Short name T1057
Test name
Test status
Simulation time 48937639 ps
CPU time 0.73 seconds
Started Feb 29 01:10:39 PM PST 24
Finished Feb 29 01:10:40 PM PST 24
Peak memory 205288 kb
Host smart-4b43d226-fdfc-4a14-ac54-c50d30a069f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156403048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.1156403048
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.1396186979
Short name T1028
Test name
Test status
Simulation time 469570219 ps
CPU time 3.05 seconds
Started Feb 29 01:10:34 PM PST 24
Finished Feb 29 01:10:38 PM PST 24
Peak memory 205588 kb
Host smart-68b86bc9-9e54-40b5-8030-734aae01c60e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396186979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s
ame_csr_outstanding.1396186979
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.2776239158
Short name T117
Test name
Test status
Simulation time 102578192 ps
CPU time 2.89 seconds
Started Feb 29 01:10:38 PM PST 24
Finished Feb 29 01:10:41 PM PST 24
Peak memory 213960 kb
Host smart-8fe488c5-3a0a-4e90-b09f-91ec52d02992
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776239158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.2776239158
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.1603003559
Short name T1022
Test name
Test status
Simulation time 885967641 ps
CPU time 5.32 seconds
Started Feb 29 01:10:36 PM PST 24
Finished Feb 29 01:10:41 PM PST 24
Peak memory 213984 kb
Host smart-fef0fb30-ef4b-4dc6-8a4f-3955ff4947be
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603003559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.1603003559
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.4188335850
Short name T199
Test name
Test status
Simulation time 154250521 ps
CPU time 5.14 seconds
Started Feb 29 01:10:36 PM PST 24
Finished Feb 29 01:10:42 PM PST 24
Peak memory 215976 kb
Host smart-e61e5dc9-9f47-4da3-a80f-86f5c67a695e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188335850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.4188335850
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.1646135428
Short name T966
Test name
Test status
Simulation time 377666523 ps
CPU time 1.89 seconds
Started Feb 29 01:10:38 PM PST 24
Finished Feb 29 01:10:40 PM PST 24
Peak memory 213768 kb
Host smart-b9c46ab5-4b38-4a81-828c-0cca99585f58
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646135428 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.1646135428
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.1615228602
Short name T1007
Test name
Test status
Simulation time 121448242 ps
CPU time 1.19 seconds
Started Feb 29 01:10:34 PM PST 24
Finished Feb 29 01:10:35 PM PST 24
Peak memory 205572 kb
Host smart-28d1e12e-8bbe-4c41-b3d6-52883d33a6a2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615228602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.1615228602
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.3327288778
Short name T1039
Test name
Test status
Simulation time 65628198 ps
CPU time 0.8 seconds
Started Feb 29 01:10:38 PM PST 24
Finished Feb 29 01:10:39 PM PST 24
Peak memory 205296 kb
Host smart-4eb7b9b4-d002-41d7-acfa-7cf13830dcfa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327288778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.3327288778
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.2314904736
Short name T1065
Test name
Test status
Simulation time 330279927 ps
CPU time 2.43 seconds
Started Feb 29 01:10:37 PM PST 24
Finished Feb 29 01:10:39 PM PST 24
Peak memory 205568 kb
Host smart-8ff76ddd-75cb-4adf-a178-cb5a2bd2992f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314904736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.2314904736
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.2084722716
Short name T1013
Test name
Test status
Simulation time 173339852 ps
CPU time 3.62 seconds
Started Feb 29 01:10:36 PM PST 24
Finished Feb 29 01:10:39 PM PST 24
Peak memory 213872 kb
Host smart-19e92112-526a-4a59-9585-7297fd9f67ad
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2084722716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.2084722716
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.711851886
Short name T990
Test name
Test status
Simulation time 159460042 ps
CPU time 3.86 seconds
Started Feb 29 01:10:39 PM PST 24
Finished Feb 29 01:10:43 PM PST 24
Peak memory 219508 kb
Host smart-08a212b6-70e8-46b4-b797-796c579713d2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711851886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
keymgr_shadow_reg_errors_with_csr_rw.711851886
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.3863394887
Short name T934
Test name
Test status
Simulation time 105913488 ps
CPU time 3.44 seconds
Started Feb 29 01:10:34 PM PST 24
Finished Feb 29 01:10:38 PM PST 24
Peak memory 214404 kb
Host smart-c2e7b74c-f70c-46a2-a6ae-7cc30eeecd06
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3863394887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.3863394887
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.3567020686
Short name T957
Test name
Test status
Simulation time 23947628 ps
CPU time 1.12 seconds
Started Feb 29 01:10:40 PM PST 24
Finished Feb 29 01:10:41 PM PST 24
Peak memory 205544 kb
Host smart-9ff7ffcf-c254-42c3-b69f-983b0bba5ef1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567020686 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.3567020686
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.4092927271
Short name T911
Test name
Test status
Simulation time 88948721 ps
CPU time 1.05 seconds
Started Feb 29 01:10:38 PM PST 24
Finished Feb 29 01:10:39 PM PST 24
Peak memory 205336 kb
Host smart-74934a49-e561-4d7f-88cc-29a880fb1c89
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4092927271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.4092927271
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.828428537
Short name T963
Test name
Test status
Simulation time 45104766 ps
CPU time 0.86 seconds
Started Feb 29 01:10:40 PM PST 24
Finished Feb 29 01:10:41 PM PST 24
Peak memory 205352 kb
Host smart-6633cad8-6ce9-4333-8e13-28a0e7327f9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828428537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.828428537
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.3475673236
Short name T978
Test name
Test status
Simulation time 319541715 ps
CPU time 3.71 seconds
Started Feb 29 01:10:35 PM PST 24
Finished Feb 29 01:10:39 PM PST 24
Peak memory 205576 kb
Host smart-d1fc5323-f6ab-4205-81f7-6262fb5d5924
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475673236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.3475673236
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.3956433832
Short name T951
Test name
Test status
Simulation time 143012751 ps
CPU time 2.27 seconds
Started Feb 29 01:10:35 PM PST 24
Finished Feb 29 01:10:37 PM PST 24
Peak memory 213976 kb
Host smart-dd255924-3aa3-435f-b031-dec2e7c11c5a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956433832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.3956433832
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.1458593810
Short name T1072
Test name
Test status
Simulation time 308917641 ps
CPU time 4.7 seconds
Started Feb 29 01:10:38 PM PST 24
Finished Feb 29 01:10:43 PM PST 24
Peak memory 213844 kb
Host smart-1ec1d437-ac83-40dd-a5d4-f72b65690000
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1458593810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.1458593810
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.134887878
Short name T1060
Test name
Test status
Simulation time 534084425 ps
CPU time 1.91 seconds
Started Feb 29 01:10:38 PM PST 24
Finished Feb 29 01:10:40 PM PST 24
Peak memory 213844 kb
Host smart-bafd3b6e-5e68-4cba-941f-02aee88e67b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134887878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.134887878
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.1299634366
Short name T164
Test name
Test status
Simulation time 151129205 ps
CPU time 6.88 seconds
Started Feb 29 01:10:40 PM PST 24
Finished Feb 29 01:10:47 PM PST 24
Peak memory 208880 kb
Host smart-7e5e474b-0be6-4c00-a41a-d47b3fec553e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299634366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.1299634366
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.857245540
Short name T154
Test name
Test status
Simulation time 86994058 ps
CPU time 1.73 seconds
Started Feb 29 01:10:39 PM PST 24
Finished Feb 29 01:10:40 PM PST 24
Peak memory 213812 kb
Host smart-63244a48-a34d-4f20-aa0e-6cba1c446ab9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857245540 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.857245540
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.3326886029
Short name T909
Test name
Test status
Simulation time 65556332 ps
CPU time 1.14 seconds
Started Feb 29 01:10:41 PM PST 24
Finished Feb 29 01:10:42 PM PST 24
Peak memory 205416 kb
Host smart-f917e306-6fa8-463a-8ba1-6d3e453d8f63
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326886029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.3326886029
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.3384940538
Short name T970
Test name
Test status
Simulation time 29945806 ps
CPU time 0.67 seconds
Started Feb 29 01:10:36 PM PST 24
Finished Feb 29 01:10:37 PM PST 24
Peak memory 205288 kb
Host smart-763d95ad-0cf3-40e1-a55f-284a751904ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384940538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.3384940538
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.401930840
Short name T137
Test name
Test status
Simulation time 355195729 ps
CPU time 3.31 seconds
Started Feb 29 01:10:39 PM PST 24
Finished Feb 29 01:10:42 PM PST 24
Peak memory 205580 kb
Host smart-1540481b-b3ae-41f1-9359-9c44fa33e46b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401930840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_sa
me_csr_outstanding.401930840
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.225597569
Short name T114
Test name
Test status
Simulation time 245269438 ps
CPU time 3.76 seconds
Started Feb 29 01:10:35 PM PST 24
Finished Feb 29 01:10:39 PM PST 24
Peak memory 213936 kb
Host smart-6463be09-23f8-4980-bcf8-0f06e6b1c540
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=225597569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shado
w_reg_errors.225597569
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.3402129709
Short name T112
Test name
Test status
Simulation time 850581292 ps
CPU time 4.92 seconds
Started Feb 29 01:10:39 PM PST 24
Finished Feb 29 01:10:44 PM PST 24
Peak memory 213884 kb
Host smart-d0e423cf-90e0-433d-81b8-52d6fad8e11e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402129709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.keymgr_shadow_reg_errors_with_csr_rw.3402129709
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.1244060836
Short name T1017
Test name
Test status
Simulation time 236373676 ps
CPU time 3.28 seconds
Started Feb 29 01:10:40 PM PST 24
Finished Feb 29 01:10:43 PM PST 24
Peak memory 215996 kb
Host smart-94468b3c-0e79-4dee-929a-a3b5a86e4072
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1244060836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.1244060836
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.2627520482
Short name T938
Test name
Test status
Simulation time 122847667 ps
CPU time 6.01 seconds
Started Feb 29 01:10:35 PM PST 24
Finished Feb 29 01:10:41 PM PST 24
Peak memory 208924 kb
Host smart-1ce83ac3-e4a3-4b38-9dc8-74e1c8ab7364
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2627520482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.2627520482
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.288126948
Short name T982
Test name
Test status
Simulation time 49971237 ps
CPU time 1.8 seconds
Started Feb 29 01:10:40 PM PST 24
Finished Feb 29 01:10:42 PM PST 24
Peak memory 218404 kb
Host smart-84c3c024-cd75-48e7-8d71-67105523d89d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288126948 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.288126948
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.343781822
Short name T915
Test name
Test status
Simulation time 26167922 ps
CPU time 1.2 seconds
Started Feb 29 01:10:40 PM PST 24
Finished Feb 29 01:10:41 PM PST 24
Peak memory 205584 kb
Host smart-8a8f0b70-ebc6-40a6-9d1e-85bd53136356
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343781822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.343781822
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.914516686
Short name T1043
Test name
Test status
Simulation time 35943482 ps
CPU time 0.75 seconds
Started Feb 29 01:10:40 PM PST 24
Finished Feb 29 01:10:41 PM PST 24
Peak memory 205208 kb
Host smart-fa512e36-258f-452a-9af2-21a36b9b3956
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=914516686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.914516686
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.223744496
Short name T937
Test name
Test status
Simulation time 226878352 ps
CPU time 1.44 seconds
Started Feb 29 01:10:39 PM PST 24
Finished Feb 29 01:10:40 PM PST 24
Peak memory 205632 kb
Host smart-0e836a3a-0680-4cc2-9885-c6510f01309b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=223744496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_sa
me_csr_outstanding.223744496
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.2979993270
Short name T974
Test name
Test status
Simulation time 54240610 ps
CPU time 2.33 seconds
Started Feb 29 01:10:42 PM PST 24
Finished Feb 29 01:10:45 PM PST 24
Peak memory 214008 kb
Host smart-fc5f3102-c2ce-4b0a-9638-dd462a48a2c2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979993270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.2979993270
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.1155781747
Short name T996
Test name
Test status
Simulation time 194894593 ps
CPU time 6.69 seconds
Started Feb 29 01:10:42 PM PST 24
Finished Feb 29 01:10:49 PM PST 24
Peak memory 213940 kb
Host smart-1b569c97-6056-44b7-8d5a-ca26e24212ab
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155781747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.1155781747
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.950390682
Short name T945
Test name
Test status
Simulation time 440880624 ps
CPU time 3.08 seconds
Started Feb 29 01:10:38 PM PST 24
Finished Feb 29 01:10:41 PM PST 24
Peak memory 213728 kb
Host smart-9a087d59-6d04-4f95-a734-e92d160ea1f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=950390682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.950390682
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.1087103054
Short name T165
Test name
Test status
Simulation time 245977961 ps
CPU time 6.23 seconds
Started Feb 29 01:10:36 PM PST 24
Finished Feb 29 01:10:42 PM PST 24
Peak memory 208936 kb
Host smart-41495451-00ed-4313-80a9-5636728336e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087103054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.1087103054
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.3432502226
Short name T954
Test name
Test status
Simulation time 72213342 ps
CPU time 2.23 seconds
Started Feb 29 01:10:40 PM PST 24
Finished Feb 29 01:10:42 PM PST 24
Peak memory 213772 kb
Host smart-2502c5fe-0130-496a-8357-42ecff758f3d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432502226 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.3432502226
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.1455517832
Short name T976
Test name
Test status
Simulation time 33859246 ps
CPU time 1.01 seconds
Started Feb 29 01:10:41 PM PST 24
Finished Feb 29 01:10:42 PM PST 24
Peak memory 205396 kb
Host smart-266733dc-e079-41be-930e-06fa82d52730
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455517832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.1455517832
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.1569421517
Short name T921
Test name
Test status
Simulation time 22276122 ps
CPU time 0.7 seconds
Started Feb 29 01:10:39 PM PST 24
Finished Feb 29 01:10:40 PM PST 24
Peak memory 205344 kb
Host smart-a5aa10d8-0ae8-49a5-b2c1-251235392e22
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569421517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.1569421517
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.270129942
Short name T927
Test name
Test status
Simulation time 121413711 ps
CPU time 4.8 seconds
Started Feb 29 01:10:39 PM PST 24
Finished Feb 29 01:10:44 PM PST 24
Peak memory 205516 kb
Host smart-6d544d34-777b-41d3-b895-d10f354cdd8b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270129942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_sa
me_csr_outstanding.270129942
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.1788569193
Short name T1031
Test name
Test status
Simulation time 436911513 ps
CPU time 4.94 seconds
Started Feb 29 01:10:40 PM PST 24
Finished Feb 29 01:10:45 PM PST 24
Peak memory 213896 kb
Host smart-2e956db4-8e10-40f0-9977-f078573e3408
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788569193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.1788569193
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.4288823812
Short name T1070
Test name
Test status
Simulation time 171060110 ps
CPU time 8.19 seconds
Started Feb 29 01:10:41 PM PST 24
Finished Feb 29 01:10:50 PM PST 24
Peak memory 213996 kb
Host smart-00386492-aa97-4435-b15f-e48eeeae3553
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288823812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.4288823812
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.1416327843
Short name T907
Test name
Test status
Simulation time 321348218 ps
CPU time 2.83 seconds
Started Feb 29 01:10:40 PM PST 24
Finished Feb 29 01:10:43 PM PST 24
Peak memory 215076 kb
Host smart-b99313b5-f93c-4b49-ad67-2c386ca11e7e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1416327843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.1416327843
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.3691380393
Short name T988
Test name
Test status
Simulation time 260643576 ps
CPU time 6.01 seconds
Started Feb 29 01:10:02 PM PST 24
Finished Feb 29 01:10:08 PM PST 24
Peak memory 205448 kb
Host smart-64654306-daba-49c5-ab6e-48d22bf6eb56
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691380393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.3
691380393
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.1473645283
Short name T926
Test name
Test status
Simulation time 4407902074 ps
CPU time 32.23 seconds
Started Feb 29 01:10:04 PM PST 24
Finished Feb 29 01:10:36 PM PST 24
Peak memory 205500 kb
Host smart-25f9fdcf-4d27-4114-b035-3a0eab31145b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1473645283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.1
473645283
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.396391069
Short name T983
Test name
Test status
Simulation time 74452526 ps
CPU time 0.93 seconds
Started Feb 29 01:10:04 PM PST 24
Finished Feb 29 01:10:05 PM PST 24
Peak memory 205212 kb
Host smart-331e9f83-5d3d-443f-a75f-8670946819b6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396391069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.396391069
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.1656277456
Short name T1048
Test name
Test status
Simulation time 160157024 ps
CPU time 1.63 seconds
Started Feb 29 01:10:05 PM PST 24
Finished Feb 29 01:10:07 PM PST 24
Peak memory 213796 kb
Host smart-b52e8d5d-b4ea-461a-99a4-6b110ee883df
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1656277456 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.1656277456
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.335761679
Short name T133
Test name
Test status
Simulation time 46742161 ps
CPU time 1.09 seconds
Started Feb 29 01:10:04 PM PST 24
Finished Feb 29 01:10:06 PM PST 24
Peak memory 205512 kb
Host smart-72711a01-c5e1-4e62-9b07-eccc9eb58ac2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335761679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.335761679
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.246609654
Short name T1019
Test name
Test status
Simulation time 19508305 ps
CPU time 0.75 seconds
Started Feb 29 01:10:04 PM PST 24
Finished Feb 29 01:10:05 PM PST 24
Peak memory 205288 kb
Host smart-84c9de53-4d79-47c9-8ebe-f4f51908161b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=246609654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.246609654
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.2928250915
Short name T138
Test name
Test status
Simulation time 65701573 ps
CPU time 1.6 seconds
Started Feb 29 01:10:03 PM PST 24
Finished Feb 29 01:10:05 PM PST 24
Peak memory 205532 kb
Host smart-ab0c5bfd-1d13-48f4-b1b2-e5fb9c81bf71
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928250915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.2928250915
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.4209361424
Short name T1044
Test name
Test status
Simulation time 250719253 ps
CPU time 2.46 seconds
Started Feb 29 01:10:04 PM PST 24
Finished Feb 29 01:10:07 PM PST 24
Peak memory 213884 kb
Host smart-1af88edc-7635-477f-889f-490f0f42c50e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209361424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.4209361424
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.3670272440
Short name T942
Test name
Test status
Simulation time 668713777 ps
CPU time 4.44 seconds
Started Feb 29 01:10:04 PM PST 24
Finished Feb 29 01:10:08 PM PST 24
Peak memory 214048 kb
Host smart-8c612310-45a7-48b6-a31d-37b108d398c4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3670272440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.3670272440
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.1138290236
Short name T971
Test name
Test status
Simulation time 185594853 ps
CPU time 3.97 seconds
Started Feb 29 01:10:03 PM PST 24
Finished Feb 29 01:10:07 PM PST 24
Peak memory 213700 kb
Host smart-d870c6f7-8ddd-4651-9ffd-ee378e740a13
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138290236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.1138290236
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.924409524
Short name T171
Test name
Test status
Simulation time 1515008050 ps
CPU time 10.1 seconds
Started Feb 29 01:10:02 PM PST 24
Finished Feb 29 01:10:12 PM PST 24
Peak memory 213716 kb
Host smart-bd026deb-2825-43b8-8860-1a52469ada48
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=924409524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err.
924409524
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.9131249
Short name T931
Test name
Test status
Simulation time 31118761 ps
CPU time 0.72 seconds
Started Feb 29 01:10:37 PM PST 24
Finished Feb 29 01:10:38 PM PST 24
Peak memory 205576 kb
Host smart-9381c0a0-67a5-4c3d-9485-cc692690e34b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=9131249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.9131249
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.2626401514
Short name T947
Test name
Test status
Simulation time 11432883 ps
CPU time 0.84 seconds
Started Feb 29 01:10:40 PM PST 24
Finished Feb 29 01:10:41 PM PST 24
Peak memory 205296 kb
Host smart-b31d2f96-5a24-4d50-9bdb-6b0211d12872
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2626401514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.2626401514
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.653161542
Short name T928
Test name
Test status
Simulation time 8905684 ps
CPU time 0.71 seconds
Started Feb 29 01:10:41 PM PST 24
Finished Feb 29 01:10:42 PM PST 24
Peak memory 205368 kb
Host smart-86718efa-40f7-4ff0-b70f-bb7b6ed99a3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=653161542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.653161542
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.1605423387
Short name T1038
Test name
Test status
Simulation time 31365622 ps
CPU time 0.78 seconds
Started Feb 29 01:10:41 PM PST 24
Finished Feb 29 01:10:42 PM PST 24
Peak memory 205264 kb
Host smart-ef56f76f-eaf8-43a1-8a31-e5fdbdb2b0a1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605423387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.1605423387
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.370479769
Short name T961
Test name
Test status
Simulation time 10695479 ps
CPU time 0.71 seconds
Started Feb 29 01:10:40 PM PST 24
Finished Feb 29 01:10:41 PM PST 24
Peak memory 205368 kb
Host smart-f6eab0b0-1883-49e6-be3e-4fd7daae84b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370479769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.370479769
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.394206801
Short name T1030
Test name
Test status
Simulation time 69639769 ps
CPU time 0.87 seconds
Started Feb 29 01:10:38 PM PST 24
Finished Feb 29 01:10:39 PM PST 24
Peak memory 205508 kb
Host smart-39ebb2c4-e26e-4cbd-ae43-ef5bd84609dd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=394206801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.394206801
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.1535082944
Short name T1009
Test name
Test status
Simulation time 11166847 ps
CPU time 0.81 seconds
Started Feb 29 01:10:41 PM PST 24
Finished Feb 29 01:10:42 PM PST 24
Peak memory 205264 kb
Host smart-f27120cb-b245-486f-8e89-5471e4620df7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535082944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.1535082944
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.1042163772
Short name T1016
Test name
Test status
Simulation time 43601225 ps
CPU time 0.86 seconds
Started Feb 29 01:10:39 PM PST 24
Finished Feb 29 01:10:40 PM PST 24
Peak memory 205256 kb
Host smart-43649c5c-2e1e-4647-80eb-32c9344f9c4e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042163772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.1042163772
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.2976554897
Short name T1026
Test name
Test status
Simulation time 9068939 ps
CPU time 0.79 seconds
Started Feb 29 01:10:55 PM PST 24
Finished Feb 29 01:10:57 PM PST 24
Peak memory 205300 kb
Host smart-89249f6b-29b4-4389-afcf-3486de17d7e8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2976554897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.2976554897
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.2094082437
Short name T967
Test name
Test status
Simulation time 12681976 ps
CPU time 0.78 seconds
Started Feb 29 01:10:56 PM PST 24
Finished Feb 29 01:10:58 PM PST 24
Peak memory 205244 kb
Host smart-659de7f9-311a-4a09-bcac-3ac487c84eb5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2094082437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.2094082437
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.3193098676
Short name T999
Test name
Test status
Simulation time 1985693099 ps
CPU time 13.38 seconds
Started Feb 29 01:10:06 PM PST 24
Finished Feb 29 01:10:20 PM PST 24
Peak memory 205520 kb
Host smart-9f312fb9-73b7-49f3-97ba-987e0bfa1015
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193098676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.3
193098676
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.3540744492
Short name T949
Test name
Test status
Simulation time 534907614 ps
CPU time 11.81 seconds
Started Feb 29 01:10:03 PM PST 24
Finished Feb 29 01:10:15 PM PST 24
Peak memory 205440 kb
Host smart-7892ccce-5c91-43e7-8433-13c4999af991
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3540744492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.3
540744492
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.4073634612
Short name T925
Test name
Test status
Simulation time 43921840 ps
CPU time 0.88 seconds
Started Feb 29 01:10:06 PM PST 24
Finished Feb 29 01:10:07 PM PST 24
Peak memory 205268 kb
Host smart-0e57048c-7e7f-43b2-8611-2486fe9f4359
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073634612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.4
073634612
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.1098708496
Short name T984
Test name
Test status
Simulation time 50402660 ps
CPU time 2.13 seconds
Started Feb 29 01:10:07 PM PST 24
Finished Feb 29 01:10:09 PM PST 24
Peak memory 213768 kb
Host smart-66ff952e-ae84-4f7b-94d8-04f2ed15f89f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098708496 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.1098708496
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.2274866000
Short name T933
Test name
Test status
Simulation time 60991360 ps
CPU time 1.3 seconds
Started Feb 29 01:10:06 PM PST 24
Finished Feb 29 01:10:07 PM PST 24
Peak memory 205444 kb
Host smart-d473e78f-51d9-4ac4-b0b8-cfad72391e0c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274866000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.2274866000
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.4205586338
Short name T920
Test name
Test status
Simulation time 15710562 ps
CPU time 0.7 seconds
Started Feb 29 01:10:03 PM PST 24
Finished Feb 29 01:10:04 PM PST 24
Peak memory 205276 kb
Host smart-4ca9cd6a-1a4a-4f74-ba62-1bdaf2cbbcff
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4205586338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.4205586338
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.1717101003
Short name T939
Test name
Test status
Simulation time 56490597 ps
CPU time 1.73 seconds
Started Feb 29 01:10:03 PM PST 24
Finished Feb 29 01:10:04 PM PST 24
Peak memory 205604 kb
Host smart-f8bddd1c-e094-4520-9700-dc4e24d2c97e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1717101003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.1717101003
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.1195816726
Short name T113
Test name
Test status
Simulation time 319807211 ps
CPU time 2.18 seconds
Started Feb 29 01:10:04 PM PST 24
Finished Feb 29 01:10:06 PM PST 24
Peak memory 213964 kb
Host smart-3de7a4dd-bbe9-4c25-bdae-fd795277e05c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195816726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.1195816726
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.3669533046
Short name T116
Test name
Test status
Simulation time 662885390 ps
CPU time 8.41 seconds
Started Feb 29 01:10:02 PM PST 24
Finished Feb 29 01:10:11 PM PST 24
Peak memory 219820 kb
Host smart-c29db2a8-1811-480d-bcc4-4e6f93378d76
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669533046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.3669533046
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.1137115236
Short name T1003
Test name
Test status
Simulation time 244232981 ps
CPU time 4.69 seconds
Started Feb 29 01:10:03 PM PST 24
Finished Feb 29 01:10:08 PM PST 24
Peak memory 213752 kb
Host smart-32b2e873-09f9-4f24-b328-3b8d4acaa573
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1137115236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.1137115236
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.4169669746
Short name T1036
Test name
Test status
Simulation time 10480314 ps
CPU time 0.89 seconds
Started Feb 29 01:10:56 PM PST 24
Finished Feb 29 01:10:59 PM PST 24
Peak memory 205376 kb
Host smart-5952d8c3-0751-4133-8158-bc4d072cff8d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169669746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.4169669746
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.903881574
Short name T929
Test name
Test status
Simulation time 49941997 ps
CPU time 0.73 seconds
Started Feb 29 01:10:57 PM PST 24
Finished Feb 29 01:10:59 PM PST 24
Peak memory 205288 kb
Host smart-386ae4eb-bef8-4dcd-a26a-751c64d12144
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=903881574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.903881574
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.3380840117
Short name T968
Test name
Test status
Simulation time 21108879 ps
CPU time 0.95 seconds
Started Feb 29 01:10:54 PM PST 24
Finished Feb 29 01:10:57 PM PST 24
Peak memory 205452 kb
Host smart-edd319ec-0246-471f-b416-edd7bd2ea43c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380840117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.3380840117
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.648508113
Short name T1001
Test name
Test status
Simulation time 116033199 ps
CPU time 0.83 seconds
Started Feb 29 01:10:56 PM PST 24
Finished Feb 29 01:10:58 PM PST 24
Peak memory 205356 kb
Host smart-eecb4d38-3c41-43a7-9753-b96fb32f2ffb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648508113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.648508113
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.2189961015
Short name T1054
Test name
Test status
Simulation time 11316569 ps
CPU time 0.7 seconds
Started Feb 29 01:10:54 PM PST 24
Finished Feb 29 01:10:57 PM PST 24
Peak memory 205364 kb
Host smart-bb42f8fa-8693-49bc-a3da-eb91c30048d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189961015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.2189961015
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.2229345321
Short name T950
Test name
Test status
Simulation time 10595635 ps
CPU time 0.81 seconds
Started Feb 29 01:10:55 PM PST 24
Finished Feb 29 01:10:57 PM PST 24
Peak memory 205300 kb
Host smart-0d600f96-1bc4-4155-b05b-03912f6b1b5d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229345321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.2229345321
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.2331170308
Short name T940
Test name
Test status
Simulation time 42477021 ps
CPU time 0.72 seconds
Started Feb 29 01:10:55 PM PST 24
Finished Feb 29 01:10:58 PM PST 24
Peak memory 205312 kb
Host smart-4d7b5056-55ac-49d6-92fc-f2b115c60f71
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331170308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.2331170308
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.4002929113
Short name T1018
Test name
Test status
Simulation time 48576642 ps
CPU time 0.75 seconds
Started Feb 29 01:10:56 PM PST 24
Finished Feb 29 01:10:58 PM PST 24
Peak memory 205228 kb
Host smart-b321807a-b428-4f84-9e57-896998304225
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002929113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.4002929113
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.2850038996
Short name T924
Test name
Test status
Simulation time 9031468 ps
CPU time 0.75 seconds
Started Feb 29 01:10:55 PM PST 24
Finished Feb 29 01:10:57 PM PST 24
Peak memory 205364 kb
Host smart-f56b2767-b29e-43fd-bd4f-9612bef3d96b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2850038996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.2850038996
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.1959079880
Short name T908
Test name
Test status
Simulation time 9971508 ps
CPU time 0.85 seconds
Started Feb 29 01:11:00 PM PST 24
Finished Feb 29 01:11:01 PM PST 24
Peak memory 205360 kb
Host smart-ec841fa2-69e6-40b5-af15-1705589b15b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1959079880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.1959079880
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.347241474
Short name T985
Test name
Test status
Simulation time 1236534553 ps
CPU time 5.11 seconds
Started Feb 29 01:10:06 PM PST 24
Finished Feb 29 01:10:11 PM PST 24
Peak memory 205496 kb
Host smart-49efd73e-88c4-4c44-a086-e11997ce5eab
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347241474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.347241474
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.3326727270
Short name T979
Test name
Test status
Simulation time 2330086016 ps
CPU time 15.43 seconds
Started Feb 29 01:10:10 PM PST 24
Finished Feb 29 01:10:26 PM PST 24
Peak memory 205608 kb
Host smart-57444714-35ab-4d3f-bb4d-3727bddb9654
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326727270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.3
326727270
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.3995040324
Short name T1023
Test name
Test status
Simulation time 23616214 ps
CPU time 1.27 seconds
Started Feb 29 01:10:05 PM PST 24
Finished Feb 29 01:10:06 PM PST 24
Peak memory 205524 kb
Host smart-3a42e5a8-d111-4631-908a-cd1db43c3b83
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995040324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.3
995040324
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.3044377114
Short name T919
Test name
Test status
Simulation time 38526443 ps
CPU time 1.92 seconds
Started Feb 29 01:10:06 PM PST 24
Finished Feb 29 01:10:08 PM PST 24
Peak memory 205736 kb
Host smart-4fcf0ccd-856b-4cbd-a7ed-d88107c0c173
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044377114 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.3044377114
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.655823565
Short name T1029
Test name
Test status
Simulation time 29145724 ps
CPU time 1.09 seconds
Started Feb 29 01:10:07 PM PST 24
Finished Feb 29 01:10:08 PM PST 24
Peak memory 205452 kb
Host smart-c2d59196-b6c2-4b94-883c-e2c8b1957200
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655823565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.655823565
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.1037351250
Short name T946
Test name
Test status
Simulation time 179059897 ps
CPU time 0.75 seconds
Started Feb 29 01:10:05 PM PST 24
Finished Feb 29 01:10:06 PM PST 24
Peak memory 205296 kb
Host smart-7cece7da-3784-41f6-a8f3-ef856792452d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037351250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.1037351250
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.1345824962
Short name T955
Test name
Test status
Simulation time 158384487 ps
CPU time 1.52 seconds
Started Feb 29 01:10:05 PM PST 24
Finished Feb 29 01:10:07 PM PST 24
Peak memory 205552 kb
Host smart-594b0243-649f-44d4-92e6-8a98867092ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345824962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.1345824962
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.3174573077
Short name T1011
Test name
Test status
Simulation time 657366963 ps
CPU time 8.27 seconds
Started Feb 29 01:10:04 PM PST 24
Finished Feb 29 01:10:13 PM PST 24
Peak memory 213964 kb
Host smart-4106c7d1-d2c2-4d2f-a20d-d9a2483b157c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174573077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.3174573077
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.1037173404
Short name T1037
Test name
Test status
Simulation time 518561052 ps
CPU time 3.44 seconds
Started Feb 29 01:10:10 PM PST 24
Finished Feb 29 01:10:13 PM PST 24
Peak memory 213852 kb
Host smart-d6e5ec08-8372-41cc-b6d1-8e3aea5a4f61
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1037173404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.1037173404
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.1720570890
Short name T1010
Test name
Test status
Simulation time 53777551 ps
CPU time 0.73 seconds
Started Feb 29 01:10:55 PM PST 24
Finished Feb 29 01:10:57 PM PST 24
Peak memory 205332 kb
Host smart-611baa2b-e621-4931-9e6b-489530d572a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720570890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.1720570890
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.2798720819
Short name T1020
Test name
Test status
Simulation time 36727904 ps
CPU time 0.69 seconds
Started Feb 29 01:10:56 PM PST 24
Finished Feb 29 01:10:58 PM PST 24
Peak memory 205420 kb
Host smart-3ed9152b-3cb4-4714-b221-d43d01b3e6aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798720819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.2798720819
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.2078944240
Short name T1014
Test name
Test status
Simulation time 77666118 ps
CPU time 0.87 seconds
Started Feb 29 01:10:57 PM PST 24
Finished Feb 29 01:10:59 PM PST 24
Peak memory 205224 kb
Host smart-4822efd9-2bda-4ae5-a15f-1031970b2290
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2078944240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.2078944240
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.2191087438
Short name T917
Test name
Test status
Simulation time 13256673 ps
CPU time 0.72 seconds
Started Feb 29 01:10:56 PM PST 24
Finished Feb 29 01:10:59 PM PST 24
Peak memory 205204 kb
Host smart-aecbe8fb-1966-4031-aae6-62728f4375ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2191087438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.2191087438
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.1396624321
Short name T1059
Test name
Test status
Simulation time 37130201 ps
CPU time 0.79 seconds
Started Feb 29 01:10:56 PM PST 24
Finished Feb 29 01:10:59 PM PST 24
Peak memory 205436 kb
Host smart-48a29729-6a14-4a86-92e9-992ed32fb72e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396624321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.1396624321
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.1639781645
Short name T944
Test name
Test status
Simulation time 8057666 ps
CPU time 0.72 seconds
Started Feb 29 01:10:57 PM PST 24
Finished Feb 29 01:10:59 PM PST 24
Peak memory 205376 kb
Host smart-ad7dc418-d23c-4378-97a3-ba93044cfbc9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1639781645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.1639781645
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.31560834
Short name T962
Test name
Test status
Simulation time 114683425 ps
CPU time 0.88 seconds
Started Feb 29 01:10:53 PM PST 24
Finished Feb 29 01:10:55 PM PST 24
Peak memory 205420 kb
Host smart-ce312147-505d-448f-b987-526f6ce6cd9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31560834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.31560834
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.1728277564
Short name T1051
Test name
Test status
Simulation time 9134431 ps
CPU time 0.68 seconds
Started Feb 29 01:10:56 PM PST 24
Finished Feb 29 01:10:59 PM PST 24
Peak memory 205376 kb
Host smart-afa9f7c3-1822-48e0-a814-40dc8271f598
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728277564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.1728277564
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.3333002777
Short name T1035
Test name
Test status
Simulation time 38118503 ps
CPU time 0.83 seconds
Started Feb 29 01:10:55 PM PST 24
Finished Feb 29 01:10:58 PM PST 24
Peak memory 205376 kb
Host smart-1c5fd632-6ced-4f5d-a0fb-981b202fd177
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333002777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.3333002777
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.4130492549
Short name T912
Test name
Test status
Simulation time 16984591 ps
CPU time 0.78 seconds
Started Feb 29 01:10:56 PM PST 24
Finished Feb 29 01:10:59 PM PST 24
Peak memory 205376 kb
Host smart-36413ae4-cceb-4b3a-b0c4-c571595427f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130492549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.4130492549
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.3690328523
Short name T1008
Test name
Test status
Simulation time 379515814 ps
CPU time 2.03 seconds
Started Feb 29 01:10:18 PM PST 24
Finished Feb 29 01:10:20 PM PST 24
Peak memory 213748 kb
Host smart-7d20e047-e848-45b1-8abc-c557eed4d16f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690328523 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.3690328523
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.2865147194
Short name T181
Test name
Test status
Simulation time 223290511 ps
CPU time 1.53 seconds
Started Feb 29 01:10:18 PM PST 24
Finished Feb 29 01:10:19 PM PST 24
Peak memory 205456 kb
Host smart-61aea6d8-f8cf-432a-a72d-25c37f9adb22
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865147194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.2865147194
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.2771530351
Short name T948
Test name
Test status
Simulation time 41743888 ps
CPU time 0.87 seconds
Started Feb 29 01:10:59 PM PST 24
Finished Feb 29 01:11:01 PM PST 24
Peak memory 205320 kb
Host smart-426b8367-0ed3-4ad9-9657-ddd55ae84d40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2771530351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.2771530351
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.855158274
Short name T1047
Test name
Test status
Simulation time 1771937668 ps
CPU time 3.1 seconds
Started Feb 29 01:10:22 PM PST 24
Finished Feb 29 01:10:25 PM PST 24
Peak memory 205772 kb
Host smart-c8c6cc61-29ce-4866-8c3f-419fc14bd443
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=855158274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sam
e_csr_outstanding.855158274
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.506986966
Short name T998
Test name
Test status
Simulation time 95408786 ps
CPU time 3.21 seconds
Started Feb 29 01:10:04 PM PST 24
Finished Feb 29 01:10:07 PM PST 24
Peak memory 213968 kb
Host smart-011d66df-a88b-461c-b58e-07a3e770fba0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506986966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shadow
_reg_errors.506986966
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.1523503779
Short name T1061
Test name
Test status
Simulation time 80566257 ps
CPU time 4.54 seconds
Started Feb 29 01:10:07 PM PST 24
Finished Feb 29 01:10:11 PM PST 24
Peak memory 219860 kb
Host smart-8c8db3d3-7dc2-4c85-ae67-19c6c63025cf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1523503779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
keymgr_shadow_reg_errors_with_csr_rw.1523503779
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.155443117
Short name T1053
Test name
Test status
Simulation time 110827610 ps
CPU time 2.08 seconds
Started Feb 29 01:10:17 PM PST 24
Finished Feb 29 01:10:19 PM PST 24
Peak memory 214760 kb
Host smart-46d7f0a3-6fe1-4852-a9f6-ae597e308bf2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155443117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.155443117
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.2676601930
Short name T1069
Test name
Test status
Simulation time 21122912 ps
CPU time 1.28 seconds
Started Feb 29 01:10:18 PM PST 24
Finished Feb 29 01:10:20 PM PST 24
Peak memory 213840 kb
Host smart-9afa893f-0f2a-4717-8b1a-61168e73d74d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676601930 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.2676601930
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.4066567677
Short name T1015
Test name
Test status
Simulation time 61676578 ps
CPU time 0.89 seconds
Started Feb 29 01:10:19 PM PST 24
Finished Feb 29 01:10:20 PM PST 24
Peak memory 205448 kb
Host smart-8ee96fc8-88e0-4685-8efa-fce041f40622
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066567677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.4066567677
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.3759561530
Short name T992
Test name
Test status
Simulation time 53880217 ps
CPU time 0.7 seconds
Started Feb 29 01:10:18 PM PST 24
Finished Feb 29 01:10:19 PM PST 24
Peak memory 205336 kb
Host smart-fcb481f1-0357-4e73-aeed-5e235a322ed1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759561530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.3759561530
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.2023177444
Short name T953
Test name
Test status
Simulation time 87879948 ps
CPU time 1.38 seconds
Started Feb 29 01:10:21 PM PST 24
Finished Feb 29 01:10:22 PM PST 24
Peak memory 205492 kb
Host smart-4d901efe-e3d1-427a-b65e-01cea93bd820
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2023177444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.2023177444
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.1295089864
Short name T115
Test name
Test status
Simulation time 847171113 ps
CPU time 3.16 seconds
Started Feb 29 01:10:17 PM PST 24
Finished Feb 29 01:10:20 PM PST 24
Peak memory 214028 kb
Host smart-f93f42fc-617c-454d-b079-f22787a185a3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295089864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.1295089864
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.3955257840
Short name T987
Test name
Test status
Simulation time 374899830 ps
CPU time 4.59 seconds
Started Feb 29 01:10:19 PM PST 24
Finished Feb 29 01:10:24 PM PST 24
Peak memory 213920 kb
Host smart-6ccab3a7-14bd-4444-848f-206a3c2497bb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3955257840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
keymgr_shadow_reg_errors_with_csr_rw.3955257840
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.3758589780
Short name T1025
Test name
Test status
Simulation time 258814552 ps
CPU time 1.64 seconds
Started Feb 29 01:10:20 PM PST 24
Finished Feb 29 01:10:22 PM PST 24
Peak memory 213764 kb
Host smart-e8d13a4c-26d9-40e9-ad40-9cf9673924f7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758589780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.3758589780
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.463850129
Short name T1063
Test name
Test status
Simulation time 155819797 ps
CPU time 1.47 seconds
Started Feb 29 01:10:19 PM PST 24
Finished Feb 29 01:10:20 PM PST 24
Peak memory 205656 kb
Host smart-63d867e4-3672-4242-9608-95b56def2221
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463850129 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.463850129
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.761557895
Short name T1033
Test name
Test status
Simulation time 25635755 ps
CPU time 0.9 seconds
Started Feb 29 01:10:18 PM PST 24
Finished Feb 29 01:10:19 PM PST 24
Peak memory 205364 kb
Host smart-766588e6-a979-4014-ad23-85c9e38fd859
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761557895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.761557895
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.870743540
Short name T1012
Test name
Test status
Simulation time 16326967 ps
CPU time 0.67 seconds
Started Feb 29 01:10:15 PM PST 24
Finished Feb 29 01:10:16 PM PST 24
Peak memory 205336 kb
Host smart-3b4cd480-00e2-4239-87f3-9db439e7de31
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870743540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.870743540
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.211587726
Short name T1050
Test name
Test status
Simulation time 44541725 ps
CPU time 1.64 seconds
Started Feb 29 01:10:17 PM PST 24
Finished Feb 29 01:10:19 PM PST 24
Peak memory 205576 kb
Host smart-55e168c1-1716-4d07-b7c3-69b2b00ecc0a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=211587726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sam
e_csr_outstanding.211587726
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.2828787415
Short name T1024
Test name
Test status
Simulation time 290030780 ps
CPU time 6 seconds
Started Feb 29 01:10:19 PM PST 24
Finished Feb 29 01:10:25 PM PST 24
Peak memory 213964 kb
Host smart-babc5c45-9c31-4ae0-b8f8-ada737ef4935
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828787415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.2828787415
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.1691332774
Short name T1071
Test name
Test status
Simulation time 768126933 ps
CPU time 7.7 seconds
Started Feb 29 01:10:20 PM PST 24
Finished Feb 29 01:10:28 PM PST 24
Peak memory 213992 kb
Host smart-740e2462-24a2-4f56-a3a5-e01b7b012d18
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1691332774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
keymgr_shadow_reg_errors_with_csr_rw.1691332774
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.1735961731
Short name T935
Test name
Test status
Simulation time 267522564 ps
CPU time 2.68 seconds
Started Feb 29 01:10:18 PM PST 24
Finished Feb 29 01:10:21 PM PST 24
Peak memory 213616 kb
Host smart-6a95c28b-0831-4051-b418-ea970af5779a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735961731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.1735961731
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.618334750
Short name T163
Test name
Test status
Simulation time 5979609980 ps
CPU time 43.2 seconds
Started Feb 29 01:10:22 PM PST 24
Finished Feb 29 01:11:05 PM PST 24
Peak memory 213876 kb
Host smart-b9f89f51-6e5f-4429-ac7f-6641848a5458
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=618334750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err.
618334750
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.160759196
Short name T981
Test name
Test status
Simulation time 120151123 ps
CPU time 1.07 seconds
Started Feb 29 01:10:21 PM PST 24
Finished Feb 29 01:10:23 PM PST 24
Peak memory 205564 kb
Host smart-aba5003a-8caf-4ff5-856d-3f71288f3e23
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160759196 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.160759196
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.2116009233
Short name T916
Test name
Test status
Simulation time 27099188 ps
CPU time 1.2 seconds
Started Feb 29 01:10:16 PM PST 24
Finished Feb 29 01:10:18 PM PST 24
Peak memory 205736 kb
Host smart-e79b2695-b2f1-490d-9d92-275b4673310f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2116009233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.2116009233
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.185632936
Short name T914
Test name
Test status
Simulation time 57228723 ps
CPU time 0.74 seconds
Started Feb 29 01:10:20 PM PST 24
Finished Feb 29 01:10:20 PM PST 24
Peak memory 205352 kb
Host smart-82ed74e7-3587-4577-abe7-369e7d23edaf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185632936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.185632936
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.3001044770
Short name T1058
Test name
Test status
Simulation time 95065212 ps
CPU time 1.83 seconds
Started Feb 29 01:10:15 PM PST 24
Finished Feb 29 01:10:17 PM PST 24
Peak memory 205576 kb
Host smart-221bcabd-d0e5-40e6-bb92-1784a271f638
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001044770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.3001044770
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.2785372564
Short name T1004
Test name
Test status
Simulation time 179333192 ps
CPU time 3.45 seconds
Started Feb 29 01:10:18 PM PST 24
Finished Feb 29 01:10:21 PM PST 24
Peak memory 213952 kb
Host smart-b93ff58c-3948-483c-9380-2dc1d36b8057
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2785372564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.2785372564
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.1581438861
Short name T952
Test name
Test status
Simulation time 662139502 ps
CPU time 4.24 seconds
Started Feb 29 01:10:19 PM PST 24
Finished Feb 29 01:10:23 PM PST 24
Peak memory 213940 kb
Host smart-a2e79d76-724e-4bf5-8162-5fb3aa71a947
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1581438861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
keymgr_shadow_reg_errors_with_csr_rw.1581438861
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.1477894146
Short name T1006
Test name
Test status
Simulation time 570247452 ps
CPU time 1.86 seconds
Started Feb 29 01:10:17 PM PST 24
Finished Feb 29 01:10:19 PM PST 24
Peak memory 213800 kb
Host smart-4b0436b1-5e50-4420-8dfb-e477c44ccae8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1477894146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.1477894146
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.2077505836
Short name T158
Test name
Test status
Simulation time 502659032 ps
CPU time 5.25 seconds
Started Feb 29 01:10:17 PM PST 24
Finished Feb 29 01:10:22 PM PST 24
Peak memory 213768 kb
Host smart-1470cbc3-ff58-483f-9333-3e82aebc0579
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2077505836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.2077505836
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.2936862819
Short name T930
Test name
Test status
Simulation time 46638611 ps
CPU time 1.54 seconds
Started Feb 29 01:10:19 PM PST 24
Finished Feb 29 01:10:21 PM PST 24
Peak memory 213792 kb
Host smart-b2eece1e-2057-4c5a-a813-a63124e353cc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936862819 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.2936862819
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.1589754035
Short name T1062
Test name
Test status
Simulation time 59521978 ps
CPU time 1.06 seconds
Started Feb 29 01:10:21 PM PST 24
Finished Feb 29 01:10:22 PM PST 24
Peak memory 205428 kb
Host smart-eaad8859-01b4-4c2f-becf-758353a1faaa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589754035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.1589754035
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.3172706439
Short name T993
Test name
Test status
Simulation time 31617109 ps
CPU time 0.75 seconds
Started Feb 29 01:10:16 PM PST 24
Finished Feb 29 01:10:17 PM PST 24
Peak memory 205200 kb
Host smart-a78e19c6-d137-4992-8612-5297f6480fb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3172706439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.3172706439
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.4199798826
Short name T994
Test name
Test status
Simulation time 46653692 ps
CPU time 2.39 seconds
Started Feb 29 01:10:21 PM PST 24
Finished Feb 29 01:10:24 PM PST 24
Peak memory 205588 kb
Host smart-b120e56b-df80-46ff-888f-bbfb3ca486f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199798826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.4199798826
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.2410457256
Short name T1002
Test name
Test status
Simulation time 81347181 ps
CPU time 2.54 seconds
Started Feb 29 01:10:20 PM PST 24
Finished Feb 29 01:10:22 PM PST 24
Peak memory 218348 kb
Host smart-14665b39-28b5-4251-a5cf-6f0402a31eb0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410457256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.2410457256
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.423013917
Short name T991
Test name
Test status
Simulation time 278765133 ps
CPU time 7.94 seconds
Started Feb 29 01:10:26 PM PST 24
Finished Feb 29 01:10:34 PM PST 24
Peak memory 219600 kb
Host smart-a04bf7b9-65b0-4a56-9de0-57ae5464c9de
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423013917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.k
eymgr_shadow_reg_errors_with_csr_rw.423013917
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.2756623024
Short name T986
Test name
Test status
Simulation time 63084219 ps
CPU time 2.51 seconds
Started Feb 29 01:10:21 PM PST 24
Finished Feb 29 01:10:23 PM PST 24
Peak memory 213884 kb
Host smart-b757b9d1-d531-4e47-86e2-b934a8444bd1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756623024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.2756623024
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.364276423
Short name T698
Test name
Test status
Simulation time 61646367 ps
CPU time 0.75 seconds
Started Feb 29 02:01:00 PM PST 24
Finished Feb 29 02:01:01 PM PST 24
Peak memory 205284 kb
Host smart-ee648f25-26e8-42ec-9d29-d29398c96028
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364276423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.364276423
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.1951176466
Short name T344
Test name
Test status
Simulation time 522041997 ps
CPU time 7.77 seconds
Started Feb 29 02:00:49 PM PST 24
Finished Feb 29 02:00:58 PM PST 24
Peak memory 221996 kb
Host smart-0df5264f-9e59-49d3-8d86-15f16428675c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1951176466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.1951176466
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.3227369875
Short name T392
Test name
Test status
Simulation time 35232784 ps
CPU time 2.18 seconds
Started Feb 29 02:00:54 PM PST 24
Finished Feb 29 02:00:58 PM PST 24
Peak memory 206568 kb
Host smart-20e8bc05-9952-499f-bdbb-703fd862831e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227369875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.3227369875
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.3373362208
Short name T471
Test name
Test status
Simulation time 116383468 ps
CPU time 3.55 seconds
Started Feb 29 02:00:54 PM PST 24
Finished Feb 29 02:00:59 PM PST 24
Peak memory 208564 kb
Host smart-54856134-cc54-4a07-bfe3-399365e34d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3373362208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.3373362208
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.2964648268
Short name T305
Test name
Test status
Simulation time 163348691 ps
CPU time 5.04 seconds
Started Feb 29 02:00:51 PM PST 24
Finished Feb 29 02:00:58 PM PST 24
Peak memory 220760 kb
Host smart-d913ecd3-eec9-4fdd-bd71-b2b0d56db164
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964648268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.2964648268
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.1008697053
Short name T498
Test name
Test status
Simulation time 874966140 ps
CPU time 5.27 seconds
Started Feb 29 02:00:53 PM PST 24
Finished Feb 29 02:01:01 PM PST 24
Peak memory 219496 kb
Host smart-33af0bbf-da80-4a51-97bc-0f2c9e1f145a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008697053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.1008697053
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.2764556276
Short name T432
Test name
Test status
Simulation time 377679938 ps
CPU time 4.14 seconds
Started Feb 29 02:00:52 PM PST 24
Finished Feb 29 02:00:59 PM PST 24
Peak memory 208260 kb
Host smart-dee85c3c-8402-49c7-b68b-dc1bb08666b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764556276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.2764556276
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.232907905
Short name T104
Test name
Test status
Simulation time 2369720378 ps
CPU time 19.37 seconds
Started Feb 29 02:01:00 PM PST 24
Finished Feb 29 02:01:20 PM PST 24
Peak memory 233396 kb
Host smart-f811791e-4170-4dbf-af8b-3c2113d50c2d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232907905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.232907905
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload.3202329433
Short name T463
Test name
Test status
Simulation time 211738358 ps
CPU time 6.74 seconds
Started Feb 29 02:00:49 PM PST 24
Finished Feb 29 02:00:57 PM PST 24
Peak memory 207124 kb
Host smart-4a606e50-52c4-48d6-bb73-7c032bab02b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202329433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.3202329433
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.1168497271
Short name T566
Test name
Test status
Simulation time 340738195 ps
CPU time 4.31 seconds
Started Feb 29 02:00:54 PM PST 24
Finished Feb 29 02:01:00 PM PST 24
Peak memory 205992 kb
Host smart-d8a1a346-c9a6-4629-9c5e-a6148eaa4dfe
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168497271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.1168497271
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.4173008598
Short name T582
Test name
Test status
Simulation time 73554035 ps
CPU time 2.7 seconds
Started Feb 29 02:00:52 PM PST 24
Finished Feb 29 02:00:58 PM PST 24
Peak memory 207744 kb
Host smart-11712975-1812-4b0b-b033-3f264c734198
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173008598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.4173008598
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.2719757282
Short name T430
Test name
Test status
Simulation time 149235764 ps
CPU time 4.63 seconds
Started Feb 29 02:00:49 PM PST 24
Finished Feb 29 02:00:54 PM PST 24
Peak memory 207232 kb
Host smart-9b8163de-06b9-4f38-9b7d-d8b3642a0b3b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2719757282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.2719757282
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.3622704128
Short name T781
Test name
Test status
Simulation time 487471284 ps
CPU time 6.22 seconds
Started Feb 29 02:01:00 PM PST 24
Finished Feb 29 02:01:07 PM PST 24
Peak memory 208528 kb
Host smart-654dc15d-8810-4008-a1e4-f769f37b473f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622704128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.3622704128
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.194747257
Short name T533
Test name
Test status
Simulation time 145126967 ps
CPU time 2.73 seconds
Started Feb 29 02:00:48 PM PST 24
Finished Feb 29 02:00:52 PM PST 24
Peak memory 207732 kb
Host smart-0acaeabe-de73-443b-b45c-61bec4c3c54f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194747257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.194747257
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all_with_rand_reset.1960711414
Short name T175
Test name
Test status
Simulation time 3871248751 ps
CPU time 28.65 seconds
Started Feb 29 02:01:05 PM PST 24
Finished Feb 29 02:01:34 PM PST 24
Peak memory 222000 kb
Host smart-fa3db7a5-ae4a-48bc-9123-7efdbb9e6abd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960711414 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all_with_rand_reset.1960711414
Directory /workspace/0.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.1614092899
Short name T716
Test name
Test status
Simulation time 61196609 ps
CPU time 3.74 seconds
Started Feb 29 02:00:48 PM PST 24
Finished Feb 29 02:00:52 PM PST 24
Peak memory 208728 kb
Host smart-4cef40e2-c7f2-4b7c-bc4d-37b5523e691f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1614092899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.1614092899
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.3918512306
Short name T821
Test name
Test status
Simulation time 60544887 ps
CPU time 2.35 seconds
Started Feb 29 02:00:58 PM PST 24
Finished Feb 29 02:01:01 PM PST 24
Peak memory 209240 kb
Host smart-4804e451-e564-475c-b1ec-becbc88b871b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918512306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.3918512306
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.2673032158
Short name T696
Test name
Test status
Simulation time 17287244 ps
CPU time 0.77 seconds
Started Feb 29 02:01:00 PM PST 24
Finished Feb 29 02:01:02 PM PST 24
Peak memory 205504 kb
Host smart-3205cf33-2d3b-4eba-a75a-92204eafbf7c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673032158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.2673032158
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.4153112196
Short name T442
Test name
Test status
Simulation time 103496953 ps
CPU time 6.53 seconds
Started Feb 29 02:01:02 PM PST 24
Finished Feb 29 02:01:09 PM PST 24
Peak memory 213748 kb
Host smart-bee16ad5-5592-4871-9625-066e6c2ec253
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4153112196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.4153112196
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.2532287035
Short name T833
Test name
Test status
Simulation time 658414254 ps
CPU time 5.2 seconds
Started Feb 29 02:01:03 PM PST 24
Finished Feb 29 02:01:08 PM PST 24
Peak memory 219092 kb
Host smart-0e873a3b-18d7-4aa9-a3b5-3b9e3f8026ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532287035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.2532287035
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.3441448887
Short name T861
Test name
Test status
Simulation time 2649536373 ps
CPU time 35.35 seconds
Started Feb 29 02:01:00 PM PST 24
Finished Feb 29 02:01:36 PM PST 24
Peak memory 217860 kb
Host smart-0f77242f-668b-436a-9790-94e3cd5f9cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441448887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.3441448887
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_random.2633767581
Short name T813
Test name
Test status
Simulation time 77142341 ps
CPU time 3.06 seconds
Started Feb 29 02:01:02 PM PST 24
Finished Feb 29 02:01:05 PM PST 24
Peak memory 206868 kb
Host smart-3cdd7434-fd26-4f8a-94a7-04be7cede5b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633767581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.2633767581
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.2839173303
Short name T105
Test name
Test status
Simulation time 31228249845 ps
CPU time 176.37 seconds
Started Feb 29 02:01:02 PM PST 24
Finished Feb 29 02:03:59 PM PST 24
Peak memory 274864 kb
Host smart-138baa7b-3717-44fa-9c69-040176136558
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839173303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.2839173303
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload.2245685923
Short name T777
Test name
Test status
Simulation time 112943147 ps
CPU time 2.37 seconds
Started Feb 29 02:01:03 PM PST 24
Finished Feb 29 02:01:06 PM PST 24
Peak memory 205788 kb
Host smart-891f09e8-cdb5-4ff4-9a21-a07f9ad71b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245685923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.2245685923
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.1121602155
Short name T239
Test name
Test status
Simulation time 834754943 ps
CPU time 5.82 seconds
Started Feb 29 02:01:01 PM PST 24
Finished Feb 29 02:01:07 PM PST 24
Peak memory 207032 kb
Host smart-769bb8e2-6ecc-4883-80f5-f29620aa1f4c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1121602155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.1121602155
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.2591899530
Short name T858
Test name
Test status
Simulation time 285821691 ps
CPU time 3.47 seconds
Started Feb 29 02:01:02 PM PST 24
Finished Feb 29 02:01:06 PM PST 24
Peak memory 205956 kb
Host smart-53dbb4c7-26c3-444e-892f-8f8db57826c5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2591899530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.2591899530
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.1029252485
Short name T508
Test name
Test status
Simulation time 102671554 ps
CPU time 4.3 seconds
Started Feb 29 02:01:04 PM PST 24
Finished Feb 29 02:01:08 PM PST 24
Peak memory 217732 kb
Host smart-afd5f34c-43b4-460e-9ce5-989e9cffc766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029252485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.1029252485
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.3849834255
Short name T650
Test name
Test status
Simulation time 237141843 ps
CPU time 3.38 seconds
Started Feb 29 02:01:01 PM PST 24
Finished Feb 29 02:01:04 PM PST 24
Peak memory 207756 kb
Host smart-2f0fe246-de88-4916-b6c7-11652194968e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849834255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.3849834255
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all_with_rand_reset.126005850
Short name T705
Test name
Test status
Simulation time 230064389 ps
CPU time 9.1 seconds
Started Feb 29 02:00:59 PM PST 24
Finished Feb 29 02:01:08 PM PST 24
Peak memory 219612 kb
Host smart-3943af11-44e4-4570-beb7-fbf8902223fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126005850 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all_with_rand_reset.126005850
Directory /workspace/1.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.388616381
Short name T588
Test name
Test status
Simulation time 1955935202 ps
CPU time 19.74 seconds
Started Feb 29 02:01:00 PM PST 24
Finished Feb 29 02:01:20 PM PST 24
Peak memory 213696 kb
Host smart-6f31837a-82fb-485b-a52a-f880f61a3b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=388616381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.388616381
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.4122524269
Short name T458
Test name
Test status
Simulation time 253354291 ps
CPU time 3.67 seconds
Started Feb 29 02:02:09 PM PST 24
Finished Feb 29 02:02:13 PM PST 24
Peak memory 206540 kb
Host smart-36fa093a-8571-4c12-b9db-ec975e85cccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122524269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.4122524269
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.1825120372
Short name T95
Test name
Test status
Simulation time 241378128 ps
CPU time 6.84 seconds
Started Feb 29 02:02:10 PM PST 24
Finished Feb 29 02:02:17 PM PST 24
Peak memory 213616 kb
Host smart-796cf5e3-34c6-4a45-9522-7b690b1acada
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825120372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.1825120372
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.2510516663
Short name T52
Test name
Test status
Simulation time 240979835 ps
CPU time 3.04 seconds
Started Feb 29 02:02:11 PM PST 24
Finished Feb 29 02:02:14 PM PST 24
Peak memory 207268 kb
Host smart-7e628338-378c-4690-907a-7d28d6adc59e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510516663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.2510516663
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_sideload.2396530290
Short name T853
Test name
Test status
Simulation time 60669486 ps
CPU time 3.15 seconds
Started Feb 29 02:02:02 PM PST 24
Finished Feb 29 02:02:06 PM PST 24
Peak memory 205940 kb
Host smart-9311de5b-1f79-48c1-8bb2-94b6b2d6e91f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396530290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.2396530290
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.2906971222
Short name T681
Test name
Test status
Simulation time 8048587281 ps
CPU time 82.82 seconds
Started Feb 29 02:01:55 PM PST 24
Finished Feb 29 02:03:18 PM PST 24
Peak memory 207816 kb
Host smart-d95950d6-bff2-4899-b89c-6300d4e8c182
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906971222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.2906971222
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.3818384980
Short name T884
Test name
Test status
Simulation time 896377053 ps
CPU time 29.85 seconds
Started Feb 29 02:02:01 PM PST 24
Finished Feb 29 02:02:32 PM PST 24
Peak memory 208032 kb
Host smart-a0b20794-564b-4118-9173-8713c7cef1d6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818384980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.3818384980
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.1824271537
Short name T286
Test name
Test status
Simulation time 72740000 ps
CPU time 3.56 seconds
Started Feb 29 02:01:56 PM PST 24
Finished Feb 29 02:02:00 PM PST 24
Peak memory 208016 kb
Host smart-a476aab7-75ff-46b6-bf4f-cbd27155a83a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824271537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.1824271537
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.3992254760
Short name T831
Test name
Test status
Simulation time 221609658 ps
CPU time 4.49 seconds
Started Feb 29 02:02:09 PM PST 24
Finished Feb 29 02:02:14 PM PST 24
Peak memory 208604 kb
Host smart-d903ccb9-5bac-4c93-822c-026b38cc1800
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3992254760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.3992254760
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.1263470483
Short name T721
Test name
Test status
Simulation time 1369949262 ps
CPU time 9.94 seconds
Started Feb 29 02:01:56 PM PST 24
Finished Feb 29 02:02:07 PM PST 24
Peak memory 208004 kb
Host smart-4bf3c9a4-17de-4ce1-9661-1b9776428e47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1263470483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.1263470483
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all_with_rand_reset.3068224816
Short name T176
Test name
Test status
Simulation time 892673615 ps
CPU time 9.45 seconds
Started Feb 29 02:02:10 PM PST 24
Finished Feb 29 02:02:19 PM PST 24
Peak memory 219164 kb
Host smart-53c94db6-0412-412d-ab7b-4d328988ff70
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3068224816 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all_with_rand_reset.3068224816
Directory /workspace/10.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.4001578342
Short name T108
Test name
Test status
Simulation time 486132236 ps
CPU time 5.35 seconds
Started Feb 29 02:02:09 PM PST 24
Finished Feb 29 02:02:15 PM PST 24
Peak memory 217528 kb
Host smart-fc0ed9ca-9345-42c3-b0a5-db45b821ca59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4001578342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.4001578342
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.2035287757
Short name T562
Test name
Test status
Simulation time 441504673 ps
CPU time 2.23 seconds
Started Feb 29 02:02:11 PM PST 24
Finished Feb 29 02:02:13 PM PST 24
Peak memory 209416 kb
Host smart-a33e3d27-bf43-4988-98ad-5a71f611437d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035287757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.2035287757
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.271153133
Short name T593
Test name
Test status
Simulation time 15329279 ps
CPU time 0.76 seconds
Started Feb 29 02:02:14 PM PST 24
Finished Feb 29 02:02:15 PM PST 24
Peak memory 205280 kb
Host smart-748965f2-ba66-4875-8db9-d4109f71651f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271153133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.271153133
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.2063283777
Short name T444
Test name
Test status
Simulation time 1961689716 ps
CPU time 113.19 seconds
Started Feb 29 02:02:12 PM PST 24
Finished Feb 29 02:04:06 PM PST 24
Peak memory 221752 kb
Host smart-0d8d88d1-41cb-4635-8aa8-412af9e22970
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2063283777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.2063283777
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.3709863535
Short name T718
Test name
Test status
Simulation time 2328711854 ps
CPU time 16.47 seconds
Started Feb 29 02:02:13 PM PST 24
Finished Feb 29 02:02:30 PM PST 24
Peak memory 213984 kb
Host smart-0220f1be-3737-4201-b4dd-8aca45b0514b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709863535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.3709863535
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.2087509108
Short name T427
Test name
Test status
Simulation time 192972924 ps
CPU time 5.38 seconds
Started Feb 29 02:02:12 PM PST 24
Finished Feb 29 02:02:18 PM PST 24
Peak memory 207672 kb
Host smart-0df3eceb-f8e5-435b-86c5-0f94eea5d829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2087509108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.2087509108
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.3817519403
Short name T284
Test name
Test status
Simulation time 1553629374 ps
CPU time 28.26 seconds
Started Feb 29 02:02:14 PM PST 24
Finished Feb 29 02:02:43 PM PST 24
Peak memory 209232 kb
Host smart-10d9cc05-7839-4d63-bc94-4482a19b3542
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817519403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.3817519403
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.1026064038
Short name T300
Test name
Test status
Simulation time 736733679 ps
CPU time 7.97 seconds
Started Feb 29 02:02:12 PM PST 24
Finished Feb 29 02:02:20 PM PST 24
Peak memory 221732 kb
Host smart-f6fa1154-d30a-41c0-ba0d-9bc4d30d59bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026064038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.1026064038
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.2018718095
Short name T263
Test name
Test status
Simulation time 62766801 ps
CPU time 3.5 seconds
Started Feb 29 02:02:13 PM PST 24
Finished Feb 29 02:02:17 PM PST 24
Peak memory 206972 kb
Host smart-6f625cd0-b90d-4a7b-9902-efc5705dd2c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2018718095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.2018718095
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.542263107
Short name T725
Test name
Test status
Simulation time 192819494 ps
CPU time 6.88 seconds
Started Feb 29 02:02:13 PM PST 24
Finished Feb 29 02:02:20 PM PST 24
Peak memory 207428 kb
Host smart-f8c69ca8-62f8-4976-9466-69f031abf224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542263107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.542263107
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.1475375396
Short name T792
Test name
Test status
Simulation time 238898571 ps
CPU time 2.22 seconds
Started Feb 29 02:02:13 PM PST 24
Finished Feb 29 02:02:16 PM PST 24
Peak memory 207988 kb
Host smart-31d39437-bd26-4c1b-8dce-08978568c5cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475375396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.1475375396
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.2770841527
Short name T202
Test name
Test status
Simulation time 1074720183 ps
CPU time 15.15 seconds
Started Feb 29 02:02:16 PM PST 24
Finished Feb 29 02:02:31 PM PST 24
Peak memory 208304 kb
Host smart-93568d1f-a482-43f1-b139-9747678d50c2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770841527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.2770841527
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.922089550
Short name T390
Test name
Test status
Simulation time 385944675 ps
CPU time 6.19 seconds
Started Feb 29 02:02:13 PM PST 24
Finished Feb 29 02:02:20 PM PST 24
Peak memory 207784 kb
Host smart-4f6e85b8-953a-437a-905f-5b38e04ca30c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922089550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.922089550
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.847181874
Short name T234
Test name
Test status
Simulation time 220682889 ps
CPU time 3.68 seconds
Started Feb 29 02:02:10 PM PST 24
Finished Feb 29 02:02:14 PM PST 24
Peak memory 207828 kb
Host smart-d477c9d8-0f5f-4844-812b-6d024f095ec5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847181874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.847181874
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.2978920694
Short name T636
Test name
Test status
Simulation time 103187141 ps
CPU time 2.47 seconds
Started Feb 29 02:02:14 PM PST 24
Finished Feb 29 02:02:17 PM PST 24
Peak memory 208600 kb
Host smart-43f90f5a-6581-476b-9a03-7f7e072452e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978920694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.2978920694
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.834300023
Short name T847
Test name
Test status
Simulation time 1015175566 ps
CPU time 8.83 seconds
Started Feb 29 02:02:11 PM PST 24
Finished Feb 29 02:02:20 PM PST 24
Peak memory 207452 kb
Host smart-db45f3e5-07f6-4ae4-b94a-139b181727cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834300023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.834300023
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.1377261772
Short name T271
Test name
Test status
Simulation time 165166071767 ps
CPU time 424.44 seconds
Started Feb 29 02:02:13 PM PST 24
Finished Feb 29 02:09:18 PM PST 24
Peak memory 221908 kb
Host smart-a998ebf5-166d-462b-affe-7c009166d63c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1377261772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.1377261772
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.4286353006
Short name T640
Test name
Test status
Simulation time 224996007 ps
CPU time 4.11 seconds
Started Feb 29 02:02:15 PM PST 24
Finished Feb 29 02:02:20 PM PST 24
Peak memory 213616 kb
Host smart-e1d4ba6d-7895-466c-a731-941fb8b47d5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286353006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.4286353006
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.1339438603
Short name T806
Test name
Test status
Simulation time 77417681 ps
CPU time 1.51 seconds
Started Feb 29 02:02:15 PM PST 24
Finished Feb 29 02:02:17 PM PST 24
Peak memory 209072 kb
Host smart-085f786a-0553-4f99-96bc-9d84b4e0a01c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339438603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.1339438603
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.1407710447
Short name T518
Test name
Test status
Simulation time 12417698 ps
CPU time 0.88 seconds
Started Feb 29 02:02:15 PM PST 24
Finished Feb 29 02:02:17 PM PST 24
Peak memory 205344 kb
Host smart-2cb67814-13f9-4de3-aa9c-7239faba09b1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1407710447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.1407710447
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.2747543803
Short name T333
Test name
Test status
Simulation time 134073267 ps
CPU time 3.85 seconds
Started Feb 29 02:02:15 PM PST 24
Finished Feb 29 02:02:19 PM PST 24
Peak memory 208684 kb
Host smart-42e0786e-5c98-4ed7-afb2-4dbbae2b888b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2747543803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.2747543803
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.1863813542
Short name T96
Test name
Test status
Simulation time 52831189 ps
CPU time 3.14 seconds
Started Feb 29 02:02:16 PM PST 24
Finished Feb 29 02:02:20 PM PST 24
Peak memory 213852 kb
Host smart-8ad611e8-e04b-4066-894e-9a810f85494e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1863813542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.1863813542
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.4214446821
Short name T50
Test name
Test status
Simulation time 129423431 ps
CPU time 3.24 seconds
Started Feb 29 02:02:16 PM PST 24
Finished Feb 29 02:02:20 PM PST 24
Peak memory 213840 kb
Host smart-a6f30eaf-bbe7-4a61-81ab-731b5cd08de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214446821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.4214446821
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.2056501766
Short name T315
Test name
Test status
Simulation time 175705179 ps
CPU time 3.22 seconds
Started Feb 29 02:02:17 PM PST 24
Finished Feb 29 02:02:21 PM PST 24
Peak memory 208428 kb
Host smart-8dd8c37c-78ee-4f8a-a3f3-219b975fc0cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056501766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.2056501766
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.1766475135
Short name T332
Test name
Test status
Simulation time 297730378 ps
CPU time 3.04 seconds
Started Feb 29 02:02:14 PM PST 24
Finished Feb 29 02:02:18 PM PST 24
Peak memory 207024 kb
Host smart-8e987a89-1fbc-423d-a431-e06c7c3bbaa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766475135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.1766475135
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.4102922612
Short name T394
Test name
Test status
Simulation time 337989254 ps
CPU time 3.39 seconds
Started Feb 29 02:02:17 PM PST 24
Finished Feb 29 02:02:23 PM PST 24
Peak memory 207660 kb
Host smart-d1e83960-f374-4147-9806-2026cc906490
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4102922612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.4102922612
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.2796909887
Short name T385
Test name
Test status
Simulation time 78396205 ps
CPU time 2.4 seconds
Started Feb 29 02:02:17 PM PST 24
Finished Feb 29 02:02:20 PM PST 24
Peak memory 206164 kb
Host smart-6c0467e0-491d-4c01-a780-6eaa48522ec9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796909887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.2796909887
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.3812407011
Short name T592
Test name
Test status
Simulation time 116664601 ps
CPU time 2.79 seconds
Started Feb 29 02:02:18 PM PST 24
Finished Feb 29 02:02:22 PM PST 24
Peak memory 207088 kb
Host smart-12cc8c73-566c-4d1d-afaa-53313103d410
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812407011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.3812407011
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.2027140033
Short name T879
Test name
Test status
Simulation time 51652913 ps
CPU time 2.11 seconds
Started Feb 29 02:02:21 PM PST 24
Finished Feb 29 02:02:23 PM PST 24
Peak memory 208336 kb
Host smart-f42d7006-7e6b-4286-860c-e18dea238e48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2027140033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.2027140033
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.3571625469
Short name T476
Test name
Test status
Simulation time 5446119830 ps
CPU time 47.91 seconds
Started Feb 29 02:02:13 PM PST 24
Finished Feb 29 02:03:01 PM PST 24
Peak memory 207592 kb
Host smart-d271f21a-6211-49fe-b2f0-777c1d1f4839
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571625469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.3571625469
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.2841474475
Short name T676
Test name
Test status
Simulation time 394980454 ps
CPU time 9.49 seconds
Started Feb 29 02:02:20 PM PST 24
Finished Feb 29 02:02:30 PM PST 24
Peak memory 215696 kb
Host smart-fbf954b6-e8fc-4568-b2f4-a08e576040ca
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841474475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.2841474475
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.348850094
Short name T887
Test name
Test status
Simulation time 2203498143 ps
CPU time 11.36 seconds
Started Feb 29 02:02:14 PM PST 24
Finished Feb 29 02:02:27 PM PST 24
Peak memory 209304 kb
Host smart-1e157e43-0028-4e03-a5f1-ef0c75bbbfb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348850094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.348850094
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.148843164
Short name T198
Test name
Test status
Simulation time 18954460 ps
CPU time 0.76 seconds
Started Feb 29 02:02:26 PM PST 24
Finished Feb 29 02:02:27 PM PST 24
Peak memory 205348 kb
Host smart-efe01846-bda2-4d90-9644-a7ce8fc51a1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148843164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.148843164
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.2719290168
Short name T370
Test name
Test status
Simulation time 64492074 ps
CPU time 2.71 seconds
Started Feb 29 02:02:23 PM PST 24
Finished Feb 29 02:02:27 PM PST 24
Peak memory 213752 kb
Host smart-7a4679fe-ebb6-4070-91b0-42e35ad40d6c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2719290168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.2719290168
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.1498587230
Short name T659
Test name
Test status
Simulation time 447246044 ps
CPU time 13.44 seconds
Started Feb 29 02:02:23 PM PST 24
Finished Feb 29 02:02:37 PM PST 24
Peak memory 213704 kb
Host smart-38e8ff54-66d9-4aee-8413-156472ad9bcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498587230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.1498587230
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.3500541041
Short name T574
Test name
Test status
Simulation time 30794817 ps
CPU time 2.12 seconds
Started Feb 29 02:02:21 PM PST 24
Finished Feb 29 02:02:23 PM PST 24
Peak memory 217484 kb
Host smart-7f4f1daf-2953-4a97-9d38-eb8372f2344a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500541041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.3500541041
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.2224306147
Short name T26
Test name
Test status
Simulation time 1081714267 ps
CPU time 10.77 seconds
Started Feb 29 02:02:22 PM PST 24
Finished Feb 29 02:02:34 PM PST 24
Peak memory 221840 kb
Host smart-6c121855-3497-44fb-b95a-b978c5db047b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224306147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.2224306147
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.3160777877
Short name T785
Test name
Test status
Simulation time 174442472 ps
CPU time 4.06 seconds
Started Feb 29 02:02:27 PM PST 24
Finished Feb 29 02:02:31 PM PST 24
Peak memory 208900 kb
Host smart-b9007593-bb83-4bdb-bb83-ad797f7d58be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3160777877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.3160777877
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.1281601771
Short name T822
Test name
Test status
Simulation time 70825437 ps
CPU time 3.35 seconds
Started Feb 29 02:02:24 PM PST 24
Finished Feb 29 02:02:28 PM PST 24
Peak memory 208780 kb
Host smart-63d9ddf8-0426-492a-8a92-0389493f6a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281601771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.1281601771
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.4250118684
Short name T723
Test name
Test status
Simulation time 72625073 ps
CPU time 3.43 seconds
Started Feb 29 02:02:20 PM PST 24
Finished Feb 29 02:02:24 PM PST 24
Peak memory 206040 kb
Host smart-da37dea4-559c-4128-b776-dd7355031eae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4250118684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.4250118684
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.2522143927
Short name T19
Test name
Test status
Simulation time 129630406 ps
CPU time 2.65 seconds
Started Feb 29 02:02:28 PM PST 24
Finished Feb 29 02:02:30 PM PST 24
Peak memory 205836 kb
Host smart-84bc0842-af06-463f-9e8b-bc440667a8cb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2522143927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.2522143927
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.664991495
Short name T523
Test name
Test status
Simulation time 204520001 ps
CPU time 5.98 seconds
Started Feb 29 02:02:16 PM PST 24
Finished Feb 29 02:02:22 PM PST 24
Peak memory 207180 kb
Host smart-f48cf78e-d73d-4423-9f8e-dfe41de6ea0e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664991495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.664991495
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.4025274604
Short name T668
Test name
Test status
Simulation time 139616089 ps
CPU time 4.81 seconds
Started Feb 29 02:02:28 PM PST 24
Finished Feb 29 02:02:33 PM PST 24
Peak memory 208000 kb
Host smart-48c62658-344d-46f1-b2e5-eb8803339ecb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025274604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.4025274604
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.2373189286
Short name T708
Test name
Test status
Simulation time 1370184754 ps
CPU time 3.99 seconds
Started Feb 29 02:02:23 PM PST 24
Finished Feb 29 02:02:27 PM PST 24
Peak memory 209244 kb
Host smart-0e70876f-891e-4b63-8d3c-c682d25e85c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373189286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.2373189286
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.400901007
Short name T554
Test name
Test status
Simulation time 187431444 ps
CPU time 2.52 seconds
Started Feb 29 02:02:15 PM PST 24
Finished Feb 29 02:02:18 PM PST 24
Peak memory 206156 kb
Host smart-a8ff1ad1-003a-4e70-8f1d-5d28a1d4a65c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400901007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.400901007
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.1307391352
Short name T830
Test name
Test status
Simulation time 8430293144 ps
CPU time 58.15 seconds
Started Feb 29 02:02:28 PM PST 24
Finished Feb 29 02:03:27 PM PST 24
Peak memory 215976 kb
Host smart-317753a9-10c9-4ebd-adf5-32248931d1ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307391352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.1307391352
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.3181904084
Short name T201
Test name
Test status
Simulation time 2424840624 ps
CPU time 6.95 seconds
Started Feb 29 02:02:28 PM PST 24
Finished Feb 29 02:02:35 PM PST 24
Peak memory 209744 kb
Host smart-b243414e-1705-4656-969b-5d4d3a9cb40a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181904084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.3181904084
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.4025424407
Short name T520
Test name
Test status
Simulation time 80174269 ps
CPU time 1.44 seconds
Started Feb 29 02:02:27 PM PST 24
Finished Feb 29 02:02:28 PM PST 24
Peak memory 209560 kb
Host smart-8d3556a5-088e-4ac1-af1d-6fcfef145a0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025424407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.4025424407
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.976308910
Short name T816
Test name
Test status
Simulation time 17938187 ps
CPU time 0.69 seconds
Started Feb 29 02:02:24 PM PST 24
Finished Feb 29 02:02:25 PM PST 24
Peak memory 205260 kb
Host smart-fbbb78c2-bdfa-4c22-8f90-dcac8aa1d259
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976308910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.976308910
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.535185740
Short name T877
Test name
Test status
Simulation time 301071315 ps
CPU time 4.49 seconds
Started Feb 29 02:02:26 PM PST 24
Finished Feb 29 02:02:31 PM PST 24
Peak memory 218368 kb
Host smart-0391375a-b3fd-4ced-8910-9d245b568ece
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=535185740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.535185740
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.1914346743
Short name T445
Test name
Test status
Simulation time 108627501 ps
CPU time 2.21 seconds
Started Feb 29 02:02:21 PM PST 24
Finished Feb 29 02:02:24 PM PST 24
Peak memory 207036 kb
Host smart-d0e1d891-e7f9-44c5-9945-c37c1646d526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914346743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.1914346743
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.499893122
Short name T552
Test name
Test status
Simulation time 492762943 ps
CPU time 9.94 seconds
Started Feb 29 02:02:24 PM PST 24
Finished Feb 29 02:02:35 PM PST 24
Peak memory 213688 kb
Host smart-4f01c5eb-a644-4773-850a-41c286c8ce57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499893122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.499893122
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.8122190
Short name T900
Test name
Test status
Simulation time 169593864 ps
CPU time 4.78 seconds
Started Feb 29 02:02:22 PM PST 24
Finished Feb 29 02:02:27 PM PST 24
Peak memory 219792 kb
Host smart-9b6ff140-be7d-4f18-b7f5-0384116842b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8122190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.8122190
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.1655012515
Short name T800
Test name
Test status
Simulation time 216841593 ps
CPU time 3.17 seconds
Started Feb 29 02:02:27 PM PST 24
Finished Feb 29 02:02:30 PM PST 24
Peak memory 206720 kb
Host smart-5c2f5e97-7ffa-4e63-99aa-a6603f1a38dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655012515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.1655012515
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.1000384880
Short name T791
Test name
Test status
Simulation time 38515729 ps
CPU time 2.3 seconds
Started Feb 29 02:02:23 PM PST 24
Finished Feb 29 02:02:26 PM PST 24
Peak memory 205972 kb
Host smart-a3a6a7f0-b07f-404a-868b-0b6604626b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000384880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.1000384880
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.2707069742
Short name T524
Test name
Test status
Simulation time 1576139130 ps
CPU time 19.49 seconds
Started Feb 29 02:02:24 PM PST 24
Finished Feb 29 02:02:44 PM PST 24
Peak memory 207872 kb
Host smart-987d9819-0a28-416c-b4a4-b2937ccbee2f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707069742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.2707069742
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.3406433742
Short name T748
Test name
Test status
Simulation time 78471643 ps
CPU time 3.52 seconds
Started Feb 29 02:02:23 PM PST 24
Finished Feb 29 02:02:27 PM PST 24
Peak memory 207824 kb
Host smart-b9413f78-3c9e-4ac8-9413-a5f20d9cabf4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406433742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.3406433742
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.723799797
Short name T598
Test name
Test status
Simulation time 289085429 ps
CPU time 5.14 seconds
Started Feb 29 02:02:24 PM PST 24
Finished Feb 29 02:02:30 PM PST 24
Peak memory 206080 kb
Host smart-1583d6e4-9e3d-4373-aead-c44e2b5e3665
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=723799797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.723799797
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.2054437812
Short name T509
Test name
Test status
Simulation time 150154560 ps
CPU time 2.79 seconds
Started Feb 29 02:02:26 PM PST 24
Finished Feb 29 02:02:29 PM PST 24
Peak memory 209172 kb
Host smart-50b67dff-44d5-4e54-8aef-73e55df887f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054437812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.2054437812
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.45732018
Short name T826
Test name
Test status
Simulation time 1262242245 ps
CPU time 3.83 seconds
Started Feb 29 02:02:24 PM PST 24
Finished Feb 29 02:02:28 PM PST 24
Peak memory 207736 kb
Host smart-b0a703c0-1342-4177-834a-1a3d585edb84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45732018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.45732018
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.611623618
Short name T384
Test name
Test status
Simulation time 978482559 ps
CPU time 25.27 seconds
Started Feb 29 02:02:28 PM PST 24
Finished Feb 29 02:02:53 PM PST 24
Peak memory 214920 kb
Host smart-e696726a-e8f1-4aa4-aa4f-5988345e651e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611623618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.611623618
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.3287421570
Short name T793
Test name
Test status
Simulation time 263275246 ps
CPU time 4.91 seconds
Started Feb 29 02:02:21 PM PST 24
Finished Feb 29 02:02:26 PM PST 24
Peak memory 206808 kb
Host smart-8b96a73b-345d-4b66-95fe-e3f38fbe4e9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287421570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.3287421570
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.1660014334
Short name T790
Test name
Test status
Simulation time 52072901 ps
CPU time 1.72 seconds
Started Feb 29 02:02:28 PM PST 24
Finished Feb 29 02:02:30 PM PST 24
Peak memory 208940 kb
Host smart-eaddc727-9fa7-4fed-80ef-33fdc1beda22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660014334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.1660014334
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.3898159324
Short name T514
Test name
Test status
Simulation time 14646608 ps
CPU time 0.92 seconds
Started Feb 29 02:02:39 PM PST 24
Finished Feb 29 02:02:40 PM PST 24
Peak memory 205468 kb
Host smart-48e1ed7b-1e49-48e9-9de2-c3cf8c41b32e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898159324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.3898159324
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.3377871697
Short name T495
Test name
Test status
Simulation time 5105359197 ps
CPU time 13.65 seconds
Started Feb 29 02:02:36 PM PST 24
Finished Feb 29 02:02:50 PM PST 24
Peak memory 215984 kb
Host smart-fe0b886f-34c1-49cb-a27d-b4d9a6d8400d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3377871697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.3377871697
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.3302950778
Short name T379
Test name
Test status
Simulation time 6174738137 ps
CPU time 15.29 seconds
Started Feb 29 02:02:38 PM PST 24
Finished Feb 29 02:02:54 PM PST 24
Peak memory 213724 kb
Host smart-0d0987f0-71f7-4cd4-936f-15ff142208ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302950778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.3302950778
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.3410554278
Short name T24
Test name
Test status
Simulation time 2323835514 ps
CPU time 60.82 seconds
Started Feb 29 02:02:38 PM PST 24
Finished Feb 29 02:03:39 PM PST 24
Peak memory 225284 kb
Host smart-03359aa3-0c04-4409-b8fc-b1eda368771c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410554278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.3410554278
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.562354093
Short name T71
Test name
Test status
Simulation time 236990466 ps
CPU time 4.69 seconds
Started Feb 29 02:02:38 PM PST 24
Finished Feb 29 02:02:43 PM PST 24
Peak memory 209424 kb
Host smart-3575f1e4-7e9b-4916-b6e4-901ba41e13eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562354093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.562354093
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_sideload.2177310170
Short name T585
Test name
Test status
Simulation time 47702745 ps
CPU time 2.66 seconds
Started Feb 29 02:02:22 PM PST 24
Finished Feb 29 02:02:25 PM PST 24
Peak memory 206536 kb
Host smart-6f58f38f-dadd-45d1-87d2-3b447a710ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177310170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.2177310170
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.1348083088
Short name T419
Test name
Test status
Simulation time 712808636 ps
CPU time 3.03 seconds
Started Feb 29 02:02:24 PM PST 24
Finished Feb 29 02:02:28 PM PST 24
Peak memory 206108 kb
Host smart-057fca00-4d58-443f-a233-9cc9456effe0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1348083088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.1348083088
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.886673425
Short name T545
Test name
Test status
Simulation time 234321107 ps
CPU time 3.97 seconds
Started Feb 29 02:02:27 PM PST 24
Finished Feb 29 02:02:31 PM PST 24
Peak memory 207832 kb
Host smart-509e6157-8891-4cf0-a7c4-36e3ca2326f2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886673425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.886673425
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.2458730436
Short name T594
Test name
Test status
Simulation time 158456091 ps
CPU time 5.15 seconds
Started Feb 29 02:02:24 PM PST 24
Finished Feb 29 02:02:30 PM PST 24
Peak memory 207784 kb
Host smart-2399b5ee-e0e4-4c9c-9927-876bf52b0437
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458730436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.2458730436
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.270696148
Short name T674
Test name
Test status
Simulation time 260664920 ps
CPU time 6.23 seconds
Started Feb 29 02:02:39 PM PST 24
Finished Feb 29 02:02:45 PM PST 24
Peak memory 207708 kb
Host smart-00c39547-c12f-4327-9e79-440a6291bfc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270696148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.270696148
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.1938945548
Short name T496
Test name
Test status
Simulation time 195999403 ps
CPU time 2.51 seconds
Started Feb 29 02:02:24 PM PST 24
Finished Feb 29 02:02:27 PM PST 24
Peak memory 207576 kb
Host smart-61e61f0c-511f-4108-99f8-261e4bd1646e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938945548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.1938945548
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.329159176
Short name T619
Test name
Test status
Simulation time 2148702822 ps
CPU time 28.35 seconds
Started Feb 29 02:02:39 PM PST 24
Finished Feb 29 02:03:08 PM PST 24
Peak memory 208000 kb
Host smart-7222c339-79a4-4301-9586-9a4b77bf7994
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329159176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.329159176
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.3703481491
Short name T893
Test name
Test status
Simulation time 340017207 ps
CPU time 7.52 seconds
Started Feb 29 02:02:37 PM PST 24
Finished Feb 29 02:02:45 PM PST 24
Peak memory 207132 kb
Host smart-a2db1040-891f-4543-a28d-29d00f05dcd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3703481491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.3703481491
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.800061228
Short name T699
Test name
Test status
Simulation time 1708491710 ps
CPU time 8.76 seconds
Started Feb 29 02:02:38 PM PST 24
Finished Feb 29 02:02:47 PM PST 24
Peak memory 209652 kb
Host smart-98f12010-898e-4cfd-9a32-5067e1112172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=800061228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.800061228
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.4263239687
Short name T774
Test name
Test status
Simulation time 12201894 ps
CPU time 0.75 seconds
Started Feb 29 02:03:01 PM PST 24
Finished Feb 29 02:03:01 PM PST 24
Peak memory 205256 kb
Host smart-852eea15-1e8f-4940-9a32-10534e01f84c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263239687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.4263239687
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.3831914433
Short name T412
Test name
Test status
Simulation time 455018617 ps
CPU time 3.79 seconds
Started Feb 29 02:02:43 PM PST 24
Finished Feb 29 02:02:47 PM PST 24
Peak memory 214336 kb
Host smart-84b893f2-799b-4a2d-8bd7-250c74cedf9e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3831914433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.3831914433
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.1586942483
Short name T30
Test name
Test status
Simulation time 608913116 ps
CPU time 6.23 seconds
Started Feb 29 02:02:40 PM PST 24
Finished Feb 29 02:02:46 PM PST 24
Peak memory 209756 kb
Host smart-910a6c35-4589-4f32-9408-cc6ce039fb2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1586942483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.1586942483
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.724183327
Short name T875
Test name
Test status
Simulation time 169002711 ps
CPU time 5.12 seconds
Started Feb 29 02:02:40 PM PST 24
Finished Feb 29 02:02:46 PM PST 24
Peak memory 208932 kb
Host smart-4b242989-c3fe-4485-a51e-edd54d5f3edc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724183327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.724183327
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.170693295
Short name T530
Test name
Test status
Simulation time 547815647 ps
CPU time 6.43 seconds
Started Feb 29 02:02:39 PM PST 24
Finished Feb 29 02:02:46 PM PST 24
Peak memory 213668 kb
Host smart-a5700f04-6573-49e1-a1cd-e4923a0f53cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170693295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.170693295
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.2638388983
Short name T325
Test name
Test status
Simulation time 197357983 ps
CPU time 3.89 seconds
Started Feb 29 02:02:40 PM PST 24
Finished Feb 29 02:02:44 PM PST 24
Peak memory 209968 kb
Host smart-1054a3a3-137a-4f46-bd89-a9be2048afbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2638388983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.2638388983
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.3034538709
Short name T262
Test name
Test status
Simulation time 167100653 ps
CPU time 3.5 seconds
Started Feb 29 02:02:42 PM PST 24
Finished Feb 29 02:02:45 PM PST 24
Peak memory 221740 kb
Host smart-1b0cbb08-9c81-4f06-9e3f-8258ca149958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034538709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.3034538709
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.3922179468
Short name T591
Test name
Test status
Simulation time 115830006 ps
CPU time 4.79 seconds
Started Feb 29 02:02:38 PM PST 24
Finished Feb 29 02:02:43 PM PST 24
Peak memory 213644 kb
Host smart-af3fb02d-614d-4c3a-9a24-348264888722
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922179468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.3922179468
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.196661572
Short name T665
Test name
Test status
Simulation time 49532941 ps
CPU time 2.67 seconds
Started Feb 29 02:02:40 PM PST 24
Finished Feb 29 02:02:43 PM PST 24
Peak memory 206072 kb
Host smart-e260cb4a-e6eb-4e48-9739-62ef7fde854b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196661572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.196661572
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.3550655419
Short name T1
Test name
Test status
Simulation time 488936426 ps
CPU time 3.95 seconds
Started Feb 29 02:02:41 PM PST 24
Finished Feb 29 02:02:45 PM PST 24
Peak memory 205960 kb
Host smart-d744412d-5ed7-442a-9792-47315eaf02cd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550655419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.3550655419
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.3073749880
Short name T290
Test name
Test status
Simulation time 841958529 ps
CPU time 7.5 seconds
Started Feb 29 02:02:39 PM PST 24
Finished Feb 29 02:02:47 PM PST 24
Peak memory 207280 kb
Host smart-a2508dc6-947c-4a24-8228-73e4c470584c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3073749880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.3073749880
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.3635288688
Short name T415
Test name
Test status
Simulation time 238329421 ps
CPU time 6.13 seconds
Started Feb 29 02:02:38 PM PST 24
Finished Feb 29 02:02:45 PM PST 24
Peak memory 207048 kb
Host smart-f7e5abd0-e305-4a24-a9dd-6cec304c5bd0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635288688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.3635288688
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.297080541
Short name T753
Test name
Test status
Simulation time 192022733 ps
CPU time 2.51 seconds
Started Feb 29 02:02:42 PM PST 24
Finished Feb 29 02:02:45 PM PST 24
Peak memory 208140 kb
Host smart-94b05093-e99a-49e8-a66f-24d65dfacca9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297080541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.297080541
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.3661823476
Short name T878
Test name
Test status
Simulation time 118383245 ps
CPU time 2.18 seconds
Started Feb 29 02:02:39 PM PST 24
Finished Feb 29 02:02:41 PM PST 24
Peak memory 205476 kb
Host smart-861d8f25-09dd-4a48-a85c-29786065480d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661823476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.3661823476
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all_with_rand_reset.3953612292
Short name T850
Test name
Test status
Simulation time 285407771 ps
CPU time 8.08 seconds
Started Feb 29 02:02:55 PM PST 24
Finished Feb 29 02:03:03 PM PST 24
Peak memory 219524 kb
Host smart-cdc8ca21-0960-44f2-801c-30b16fa7b3d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3953612292 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all_with_rand_reset.3953612292
Directory /workspace/16.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.3987669151
Short name T403
Test name
Test status
Simulation time 249598987 ps
CPU time 4.34 seconds
Started Feb 29 02:02:41 PM PST 24
Finished Feb 29 02:02:46 PM PST 24
Peak memory 207884 kb
Host smart-bff173be-5721-4c3a-8fea-7c4098a1e8f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3987669151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.3987669151
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.3210745484
Short name T570
Test name
Test status
Simulation time 207490846 ps
CPU time 4.05 seconds
Started Feb 29 02:02:41 PM PST 24
Finished Feb 29 02:02:45 PM PST 24
Peak memory 209136 kb
Host smart-c0596573-419e-4f21-aba2-139b020fc990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3210745484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.3210745484
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.1204209068
Short name T573
Test name
Test status
Simulation time 33147884 ps
CPU time 0.7 seconds
Started Feb 29 02:02:55 PM PST 24
Finished Feb 29 02:02:55 PM PST 24
Peak memory 205344 kb
Host smart-2df1498f-b6ca-4285-9418-fe646ef68859
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204209068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.1204209068
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.57805711
Short name T363
Test name
Test status
Simulation time 365157709 ps
CPU time 3.9 seconds
Started Feb 29 02:02:59 PM PST 24
Finished Feb 29 02:03:04 PM PST 24
Peak memory 214032 kb
Host smart-53e12e93-5f03-4fda-9953-96ec30ea0947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57805711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.57805711
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.2302185468
Short name T57
Test name
Test status
Simulation time 143635201 ps
CPU time 2.71 seconds
Started Feb 29 02:02:56 PM PST 24
Finished Feb 29 02:03:00 PM PST 24
Peak memory 209032 kb
Host smart-bdee3525-f720-443d-a40d-cadc4805215a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302185468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.2302185468
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.2298784814
Short name T714
Test name
Test status
Simulation time 784801175 ps
CPU time 6.79 seconds
Started Feb 29 02:02:55 PM PST 24
Finished Feb 29 02:03:02 PM PST 24
Peak memory 208072 kb
Host smart-906035b0-07db-4aa9-be8a-3cccab0524ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298784814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.2298784814
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.2945566595
Short name T630
Test name
Test status
Simulation time 972574473 ps
CPU time 6.59 seconds
Started Feb 29 02:02:58 PM PST 24
Finished Feb 29 02:03:04 PM PST 24
Peak memory 221840 kb
Host smart-83b66ab7-032c-4d2a-b7e9-5c32286cdc0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945566595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.2945566595
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.564827815
Short name T626
Test name
Test status
Simulation time 36368409 ps
CPU time 2.44 seconds
Started Feb 29 02:02:55 PM PST 24
Finished Feb 29 02:02:57 PM PST 24
Peak memory 219280 kb
Host smart-842fe5ac-a6b2-4a63-9d71-898e2dc6bcbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564827815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.564827815
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.3771450014
Short name T353
Test name
Test status
Simulation time 204766033 ps
CPU time 5.79 seconds
Started Feb 29 02:02:56 PM PST 24
Finished Feb 29 02:03:02 PM PST 24
Peak memory 208656 kb
Host smart-1eeec184-07ff-4a1f-94cc-9e3e77f197b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771450014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.3771450014
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.206385708
Short name T855
Test name
Test status
Simulation time 1659864651 ps
CPU time 22.33 seconds
Started Feb 29 02:03:00 PM PST 24
Finished Feb 29 02:03:22 PM PST 24
Peak memory 207948 kb
Host smart-a8e29036-4c99-44be-a97f-f2a9c0795d58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=206385708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.206385708
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.797078950
Short name T901
Test name
Test status
Simulation time 423298651 ps
CPU time 6.44 seconds
Started Feb 29 02:02:57 PM PST 24
Finished Feb 29 02:03:04 PM PST 24
Peak memory 207324 kb
Host smart-da18507f-1738-46be-a35a-b1b848f0f1e8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797078950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.797078950
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.82105066
Short name T772
Test name
Test status
Simulation time 3314806467 ps
CPU time 22.28 seconds
Started Feb 29 02:03:01 PM PST 24
Finished Feb 29 02:03:24 PM PST 24
Peak memory 208056 kb
Host smart-9d9ad0a6-f91c-40c7-80c7-1efbde32241f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82105066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.82105066
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.28285142
Short name T745
Test name
Test status
Simulation time 67359272 ps
CPU time 3.49 seconds
Started Feb 29 02:02:57 PM PST 24
Finished Feb 29 02:03:01 PM PST 24
Peak memory 207804 kb
Host smart-c188a750-1298-448e-b2e4-e17be5a64cae
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28285142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.28285142
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.2829274660
Short name T314
Test name
Test status
Simulation time 112044254 ps
CPU time 3.05 seconds
Started Feb 29 02:03:03 PM PST 24
Finished Feb 29 02:03:06 PM PST 24
Peak memory 214880 kb
Host smart-40485260-daaf-467d-834e-acc590a2797b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829274660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.2829274660
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.2013778651
Short name T487
Test name
Test status
Simulation time 348272466 ps
CPU time 4.71 seconds
Started Feb 29 02:03:00 PM PST 24
Finished Feb 29 02:03:05 PM PST 24
Peak memory 207568 kb
Host smart-85991b6e-a0f5-4ef7-9747-abf5b99207e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013778651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.2013778651
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.2291015205
Short name T870
Test name
Test status
Simulation time 598749423 ps
CPU time 7.31 seconds
Started Feb 29 02:02:58 PM PST 24
Finished Feb 29 02:03:05 PM PST 24
Peak memory 217616 kb
Host smart-7322b392-4825-4631-a158-8bf3329013e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291015205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.2291015205
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.3008868536
Short name T172
Test name
Test status
Simulation time 107085684 ps
CPU time 1.86 seconds
Started Feb 29 02:02:58 PM PST 24
Finished Feb 29 02:03:01 PM PST 24
Peak memory 209064 kb
Host smart-e3a34de9-82ce-4be6-85c2-cced9852f3d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008868536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.3008868536
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.1276939528
Short name T456
Test name
Test status
Simulation time 15403492 ps
CPU time 0.7 seconds
Started Feb 29 02:02:58 PM PST 24
Finished Feb 29 02:02:59 PM PST 24
Peak memory 205264 kb
Host smart-88f5a818-94c4-409a-8336-c0b9cfa7c774
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276939528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.1276939528
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.1846803812
Short name T815
Test name
Test status
Simulation time 1011164279 ps
CPU time 14.28 seconds
Started Feb 29 02:02:54 PM PST 24
Finished Feb 29 02:03:08 PM PST 24
Peak memory 213696 kb
Host smart-38b544af-54ea-44f8-b238-21a652d2bbca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1846803812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.1846803812
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.898567148
Short name T334
Test name
Test status
Simulation time 44955092 ps
CPU time 1.88 seconds
Started Feb 29 02:02:59 PM PST 24
Finished Feb 29 02:03:02 PM PST 24
Peak memory 206704 kb
Host smart-7fdfa1f4-3034-423e-80d1-31f9567d0544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898567148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.898567148
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.1024053768
Short name T389
Test name
Test status
Simulation time 53545781 ps
CPU time 3.5 seconds
Started Feb 29 02:02:58 PM PST 24
Finished Feb 29 02:03:01 PM PST 24
Peak memory 208640 kb
Host smart-f1da35a9-3c1f-424a-844d-277576d612dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024053768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.1024053768
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.982939063
Short name T413
Test name
Test status
Simulation time 2569729530 ps
CPU time 11.2 seconds
Started Feb 29 02:03:00 PM PST 24
Finished Feb 29 02:03:11 PM PST 24
Peak memory 210648 kb
Host smart-6a3998a7-03eb-41f9-b5a1-6712091655a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=982939063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.982939063
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.3374937449
Short name T61
Test name
Test status
Simulation time 139256027 ps
CPU time 2.64 seconds
Started Feb 29 02:02:55 PM PST 24
Finished Feb 29 02:02:58 PM PST 24
Peak memory 209792 kb
Host smart-da156779-bc8c-46f1-867e-8cb3dd514ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374937449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.3374937449
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.3808264947
Short name T778
Test name
Test status
Simulation time 460095037 ps
CPU time 5.4 seconds
Started Feb 29 02:02:55 PM PST 24
Finished Feb 29 02:03:01 PM PST 24
Peak memory 209376 kb
Host smart-544cd183-bae4-48e0-b2f4-242d88631910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3808264947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.3808264947
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.2757177822
Short name T704
Test name
Test status
Simulation time 139643574 ps
CPU time 3.33 seconds
Started Feb 29 02:02:56 PM PST 24
Finished Feb 29 02:03:00 PM PST 24
Peak memory 207448 kb
Host smart-fa543ade-faa5-4fa7-aa3b-199bb6a03b52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2757177822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.2757177822
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.2581672194
Short name T812
Test name
Test status
Simulation time 62193796 ps
CPU time 3.17 seconds
Started Feb 29 02:03:00 PM PST 24
Finished Feb 29 02:03:03 PM PST 24
Peak memory 207712 kb
Host smart-cf1f4496-d1af-4d7b-9460-1db1668a23fc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581672194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.2581672194
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.2208924325
Short name T846
Test name
Test status
Simulation time 167739781 ps
CPU time 2.53 seconds
Started Feb 29 02:02:56 PM PST 24
Finished Feb 29 02:02:59 PM PST 24
Peak memory 207492 kb
Host smart-d76ae7f2-023a-4d2a-9b80-83b57fcc4a30
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208924325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.2208924325
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.1167085842
Short name T803
Test name
Test status
Simulation time 169111107 ps
CPU time 4.37 seconds
Started Feb 29 02:03:00 PM PST 24
Finished Feb 29 02:03:04 PM PST 24
Peak memory 217572 kb
Host smart-67562938-28a0-44f2-828d-f716061a1cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1167085842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.1167085842
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.3213502014
Short name T464
Test name
Test status
Simulation time 492779374 ps
CPU time 4.1 seconds
Started Feb 29 02:02:57 PM PST 24
Finished Feb 29 02:03:02 PM PST 24
Peak memory 207100 kb
Host smart-37b52331-6f72-426c-b8e6-acbe8cbfe613
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3213502014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.3213502014
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.572811810
Short name T840
Test name
Test status
Simulation time 2765064086 ps
CPU time 21.41 seconds
Started Feb 29 02:02:59 PM PST 24
Finished Feb 29 02:03:21 PM PST 24
Peak memory 216036 kb
Host smart-7c54cf72-edd6-42dd-8786-6c4cbbf45b3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572811810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.572811810
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.2693278345
Short name T680
Test name
Test status
Simulation time 180777436 ps
CPU time 6 seconds
Started Feb 29 02:02:58 PM PST 24
Finished Feb 29 02:03:06 PM PST 24
Peak memory 217448 kb
Host smart-01a76630-f254-4594-ab5a-19e7cb4d32a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693278345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.2693278345
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.1619516861
Short name T409
Test name
Test status
Simulation time 120166586 ps
CPU time 1.74 seconds
Started Feb 29 02:03:03 PM PST 24
Finished Feb 29 02:03:05 PM PST 24
Peak memory 209092 kb
Host smart-01713d86-43e9-4ccf-8c93-65529ad107f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619516861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.1619516861
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.1015969642
Short name T811
Test name
Test status
Simulation time 11902994 ps
CPU time 0.78 seconds
Started Feb 29 02:03:15 PM PST 24
Finished Feb 29 02:03:16 PM PST 24
Peak memory 205352 kb
Host smart-de10830b-7a8a-4bae-9378-034ee9166ec3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1015969642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.1015969642
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.364013077
Short name T439
Test name
Test status
Simulation time 188298680 ps
CPU time 9.42 seconds
Started Feb 29 02:02:59 PM PST 24
Finished Feb 29 02:03:09 PM PST 24
Peak memory 214720 kb
Host smart-16b690db-7808-441e-8a40-84c04266ebee
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=364013077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.364013077
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.2046463721
Short name T36
Test name
Test status
Simulation time 114312232 ps
CPU time 4.87 seconds
Started Feb 29 02:03:03 PM PST 24
Finished Feb 29 02:03:08 PM PST 24
Peak memory 215688 kb
Host smart-dc0ce2f3-e304-4ebe-88c9-9099ba62c4d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046463721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.2046463721
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.4276475138
Short name T751
Test name
Test status
Simulation time 273034281 ps
CPU time 1.69 seconds
Started Feb 29 02:03:01 PM PST 24
Finished Feb 29 02:03:03 PM PST 24
Peak memory 213584 kb
Host smart-2e7f6e2e-adca-49d1-b811-12d432f7f70a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276475138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.4276475138
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.2709583831
Short name T210
Test name
Test status
Simulation time 1863698894 ps
CPU time 30.11 seconds
Started Feb 29 02:03:03 PM PST 24
Finished Feb 29 02:03:33 PM PST 24
Peak memory 213756 kb
Host smart-ca36cf46-b0a0-4e47-8c09-a89f5a62e1bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709583831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.2709583831
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.1779415531
Short name T77
Test name
Test status
Simulation time 10077987422 ps
CPU time 49.64 seconds
Started Feb 29 02:02:58 PM PST 24
Finished Feb 29 02:03:49 PM PST 24
Peak memory 216560 kb
Host smart-21232a3c-8c92-43e4-a43d-3b505eb385fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779415531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.1779415531
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.4017032965
Short name T522
Test name
Test status
Simulation time 77003799 ps
CPU time 3.09 seconds
Started Feb 29 02:03:03 PM PST 24
Finished Feb 29 02:03:06 PM PST 24
Peak memory 217472 kb
Host smart-cb7b6b8c-21bd-4fe1-b512-6d836a7b79f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017032965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.4017032965
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.507256325
Short name T798
Test name
Test status
Simulation time 250849805 ps
CPU time 4 seconds
Started Feb 29 02:02:59 PM PST 24
Finished Feb 29 02:03:04 PM PST 24
Peak memory 217788 kb
Host smart-c67bd5be-be80-440f-8910-d61a37976077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=507256325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.507256325
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.169906756
Short name T586
Test name
Test status
Simulation time 521344112 ps
CPU time 6.79 seconds
Started Feb 29 02:03:03 PM PST 24
Finished Feb 29 02:03:10 PM PST 24
Peak memory 207916 kb
Host smart-8e8764c4-2ee8-4b7d-9b28-96709be351b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169906756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.169906756
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.1402389995
Short name T506
Test name
Test status
Simulation time 762354126 ps
CPU time 7.86 seconds
Started Feb 29 02:03:01 PM PST 24
Finished Feb 29 02:03:09 PM PST 24
Peak memory 207568 kb
Host smart-dcf097a4-c50c-4654-aa79-d915f2c3199f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402389995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.1402389995
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.1569203256
Short name T209
Test name
Test status
Simulation time 747370314 ps
CPU time 8.5 seconds
Started Feb 29 02:02:59 PM PST 24
Finished Feb 29 02:03:08 PM PST 24
Peak memory 206160 kb
Host smart-c892a620-f018-4fbe-a5c2-1249587c29c7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569203256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.1569203256
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.2180455127
Short name T891
Test name
Test status
Simulation time 314685634 ps
CPU time 4.2 seconds
Started Feb 29 02:02:58 PM PST 24
Finished Feb 29 02:03:04 PM PST 24
Peak memory 206732 kb
Host smart-6fb80ec7-8af6-462e-bbde-37cce1533652
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180455127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.2180455127
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.3506508791
Short name T755
Test name
Test status
Simulation time 388233304 ps
CPU time 2.47 seconds
Started Feb 29 02:03:01 PM PST 24
Finished Feb 29 02:03:03 PM PST 24
Peak memory 209384 kb
Host smart-a5df174a-fce8-493b-843c-b6879acb03de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506508791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.3506508791
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.2975945693
Short name T581
Test name
Test status
Simulation time 293804215 ps
CPU time 2.94 seconds
Started Feb 29 02:02:58 PM PST 24
Finished Feb 29 02:03:01 PM PST 24
Peak memory 207760 kb
Host smart-8c307612-097c-4dc4-b953-19e2384872ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975945693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.2975945693
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.1212534937
Short name T372
Test name
Test status
Simulation time 2250011656 ps
CPU time 61.72 seconds
Started Feb 29 02:03:12 PM PST 24
Finished Feb 29 02:04:14 PM PST 24
Peak memory 221896 kb
Host smart-274cacf9-9e05-470d-8397-3c18db26ba1f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212534937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.1212534937
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.2796260097
Short name T297
Test name
Test status
Simulation time 118459370 ps
CPU time 6.05 seconds
Started Feb 29 02:03:01 PM PST 24
Finished Feb 29 02:03:07 PM PST 24
Peak memory 208440 kb
Host smart-fd633e1d-c7e7-4b25-90f1-2dcf8c20eb38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796260097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.2796260097
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.2800616766
Short name T757
Test name
Test status
Simulation time 53687586 ps
CPU time 2.72 seconds
Started Feb 29 02:03:14 PM PST 24
Finished Feb 29 02:03:17 PM PST 24
Peak memory 209212 kb
Host smart-756a3dce-4331-43e7-830b-0c1c44e4b0f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800616766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.2800616766
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.3078144510
Short name T649
Test name
Test status
Simulation time 64944181 ps
CPU time 0.89 seconds
Started Feb 29 02:01:13 PM PST 24
Finished Feb 29 02:01:15 PM PST 24
Peak memory 205344 kb
Host smart-869ecdbc-5f4d-4481-b317-10808e7992dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078144510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.3078144510
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.2897137892
Short name T129
Test name
Test status
Simulation time 52819324 ps
CPU time 4.03 seconds
Started Feb 29 02:01:00 PM PST 24
Finished Feb 29 02:01:05 PM PST 24
Peak memory 214652 kb
Host smart-8ad15c5b-bb35-488c-ac90-51b5e9b32a52
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2897137892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.2897137892
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.659521786
Short name T31
Test name
Test status
Simulation time 110118517 ps
CPU time 3.81 seconds
Started Feb 29 02:01:12 PM PST 24
Finished Feb 29 02:01:17 PM PST 24
Peak memory 220916 kb
Host smart-3712c6c5-da1a-4a04-90f3-a258a60621b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=659521786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.659521786
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.792201903
Short name T532
Test name
Test status
Simulation time 81529512 ps
CPU time 2.61 seconds
Started Feb 29 02:01:13 PM PST 24
Finished Feb 29 02:01:16 PM PST 24
Peak memory 207844 kb
Host smart-48a145e2-1a0f-4168-a31f-b9555d35db5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792201903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.792201903
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.3406787689
Short name T327
Test name
Test status
Simulation time 365544023 ps
CPU time 4.48 seconds
Started Feb 29 02:01:13 PM PST 24
Finished Feb 29 02:01:18 PM PST 24
Peak memory 209108 kb
Host smart-7a056506-24df-4678-9139-9db7b871fc5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406787689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.3406787689
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.392851757
Short name T388
Test name
Test status
Simulation time 370065756 ps
CPU time 9.88 seconds
Started Feb 29 02:01:16 PM PST 24
Finished Feb 29 02:01:26 PM PST 24
Peak memory 213568 kb
Host smart-e6755d11-7cb1-442e-9bd2-59ac3cbc1c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392851757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.392851757
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.4164794678
Short name T254
Test name
Test status
Simulation time 262124092 ps
CPU time 3.67 seconds
Started Feb 29 02:01:17 PM PST 24
Finished Feb 29 02:01:21 PM PST 24
Peak memory 219720 kb
Host smart-18b24d6a-1024-4a95-a128-6eab47eeca52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164794678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.4164794678
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.103025806
Short name T354
Test name
Test status
Simulation time 286263830 ps
CPU time 3.78 seconds
Started Feb 29 02:01:03 PM PST 24
Finished Feb 29 02:01:07 PM PST 24
Peak memory 213536 kb
Host smart-c9204037-c923-4979-9021-868917f1392c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103025806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.103025806
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.1196887752
Short name T14
Test name
Test status
Simulation time 1258229845 ps
CPU time 28 seconds
Started Feb 29 02:01:13 PM PST 24
Finished Feb 29 02:01:41 PM PST 24
Peak memory 238212 kb
Host smart-438fdb5f-5b75-4ba1-a19e-4e2a0fd86ce8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1196887752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.1196887752
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.2613795489
Short name T516
Test name
Test status
Simulation time 392735156 ps
CPU time 5.18 seconds
Started Feb 29 02:01:05 PM PST 24
Finished Feb 29 02:01:10 PM PST 24
Peak memory 207720 kb
Host smart-56d02572-935b-44ff-aab2-4d4275c5f8f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2613795489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.2613795489
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.2233077204
Short name T425
Test name
Test status
Simulation time 67406306 ps
CPU time 3.25 seconds
Started Feb 29 02:01:09 PM PST 24
Finished Feb 29 02:01:13 PM PST 24
Peak memory 206056 kb
Host smart-d2d7dffb-afa4-4627-bead-d8aa42f61977
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233077204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.2233077204
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.2998544267
Short name T691
Test name
Test status
Simulation time 26057868 ps
CPU time 1.98 seconds
Started Feb 29 02:01:00 PM PST 24
Finished Feb 29 02:01:03 PM PST 24
Peak memory 205924 kb
Host smart-ca93b2c2-ecc2-4a82-b5be-72803f7b3cf9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998544267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.2998544267
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.635154054
Short name T313
Test name
Test status
Simulation time 496716685 ps
CPU time 5.04 seconds
Started Feb 29 02:01:03 PM PST 24
Finished Feb 29 02:01:08 PM PST 24
Peak memory 206812 kb
Host smart-24a6651f-411a-4624-a6db-45b199ec6ed6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=635154054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.635154054
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.627714369
Short name T658
Test name
Test status
Simulation time 147558985 ps
CPU time 2.13 seconds
Started Feb 29 02:01:17 PM PST 24
Finished Feb 29 02:01:19 PM PST 24
Peak memory 206064 kb
Host smart-4d813096-4902-4fd2-ae99-bb46d6af7a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627714369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.627714369
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.1311220166
Short name T827
Test name
Test status
Simulation time 450906232 ps
CPU time 2.7 seconds
Started Feb 29 02:01:03 PM PST 24
Finished Feb 29 02:01:06 PM PST 24
Peak memory 206320 kb
Host smart-aa1a426f-386e-44fd-a579-f35f5692bde9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311220166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.1311220166
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.1425789899
Short name T824
Test name
Test status
Simulation time 147501408 ps
CPU time 3.1 seconds
Started Feb 29 02:01:12 PM PST 24
Finished Feb 29 02:01:15 PM PST 24
Peak memory 213684 kb
Host smart-9c1dd7a7-76fe-4533-8cdd-073b9519ef73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425789899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.1425789899
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.1680820249
Short name T200
Test name
Test status
Simulation time 124805550 ps
CPU time 2.02 seconds
Started Feb 29 02:01:16 PM PST 24
Finished Feb 29 02:01:18 PM PST 24
Peak memory 209204 kb
Host smart-7ded8084-d280-4038-8074-ff96bd6574c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680820249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.1680820249
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.1357992164
Short name T664
Test name
Test status
Simulation time 19412841 ps
CPU time 0.84 seconds
Started Feb 29 02:03:17 PM PST 24
Finished Feb 29 02:03:19 PM PST 24
Peak memory 205312 kb
Host smart-18b474d4-1eaf-431b-97f4-eecb09542eb1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357992164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.1357992164
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.3622510104
Short name T844
Test name
Test status
Simulation time 243111046 ps
CPU time 4.02 seconds
Started Feb 29 02:03:17 PM PST 24
Finished Feb 29 02:03:21 PM PST 24
Peak memory 214448 kb
Host smart-cf168065-5d96-48e8-99f7-e4fed5e3a633
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3622510104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.3622510104
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.2936028338
Short name T72
Test name
Test status
Simulation time 332870484 ps
CPU time 3.27 seconds
Started Feb 29 02:03:17 PM PST 24
Finished Feb 29 02:03:20 PM PST 24
Peak memory 221220 kb
Host smart-90b2873b-c608-47f6-8c74-8973667f667e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936028338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.2936028338
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.1573587852
Short name T868
Test name
Test status
Simulation time 47750504 ps
CPU time 2.33 seconds
Started Feb 29 02:03:12 PM PST 24
Finished Feb 29 02:03:15 PM PST 24
Peak memory 209116 kb
Host smart-61245ae7-bb6a-4827-8e1d-73c1479ddda4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573587852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.1573587852
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.2545259945
Short name T538
Test name
Test status
Simulation time 4881040894 ps
CPU time 63.82 seconds
Started Feb 29 02:03:12 PM PST 24
Finished Feb 29 02:04:16 PM PST 24
Peak memory 213724 kb
Host smart-32eba7ed-7e57-4524-a182-54b6e03a0a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545259945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.2545259945
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.629874518
Short name T303
Test name
Test status
Simulation time 143290543 ps
CPU time 5.32 seconds
Started Feb 29 02:03:14 PM PST 24
Finished Feb 29 02:03:20 PM PST 24
Peak memory 209588 kb
Host smart-7f03134b-9356-4200-8939-15950a9d239b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629874518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.629874518
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.3522254455
Short name T551
Test name
Test status
Simulation time 395301665 ps
CPU time 2.1 seconds
Started Feb 29 02:03:12 PM PST 24
Finished Feb 29 02:03:14 PM PST 24
Peak memory 205868 kb
Host smart-83b37183-14ff-4d06-9427-3edbc81dcfdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522254455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.3522254455
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.3293587572
Short name T274
Test name
Test status
Simulation time 55563661 ps
CPU time 2.39 seconds
Started Feb 29 02:03:13 PM PST 24
Finished Feb 29 02:03:16 PM PST 24
Peak memory 207268 kb
Host smart-3f3fb92f-1f7c-4fde-8dce-0736bfa38f0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293587572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.3293587572
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.11183153
Short name T871
Test name
Test status
Simulation time 271011436 ps
CPU time 2.49 seconds
Started Feb 29 02:03:13 PM PST 24
Finished Feb 29 02:03:16 PM PST 24
Peak memory 205872 kb
Host smart-0dc9846d-8d9b-49df-b1a2-c9d4a03bf0a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11183153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.11183153
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.1844952082
Short name T880
Test name
Test status
Simulation time 736030657 ps
CPU time 5.39 seconds
Started Feb 29 02:03:12 PM PST 24
Finished Feb 29 02:03:18 PM PST 24
Peak memory 207700 kb
Host smart-e6057195-6b36-4d62-b352-044b793e07cc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1844952082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.1844952082
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.3115730626
Short name T189
Test name
Test status
Simulation time 572360690 ps
CPU time 15.4 seconds
Started Feb 29 02:03:16 PM PST 24
Finished Feb 29 02:03:31 PM PST 24
Peak memory 207648 kb
Host smart-7a4bac76-2658-4e0b-9ea4-da184dcd3eb2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115730626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.3115730626
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.4073028674
Short name T642
Test name
Test status
Simulation time 353603593 ps
CPU time 5.79 seconds
Started Feb 29 02:03:14 PM PST 24
Finished Feb 29 02:03:20 PM PST 24
Peak memory 207912 kb
Host smart-cfed3ad9-eede-42db-b468-13efd5198146
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4073028674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.4073028674
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.1046787125
Short name T881
Test name
Test status
Simulation time 165526641 ps
CPU time 2.73 seconds
Started Feb 29 02:03:14 PM PST 24
Finished Feb 29 02:03:16 PM PST 24
Peak memory 208556 kb
Host smart-a8e3a2f3-3ba9-4c44-8ea0-31e99d3885b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046787125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.1046787125
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.758311037
Short name T224
Test name
Test status
Simulation time 2525635073 ps
CPU time 23.37 seconds
Started Feb 29 02:03:15 PM PST 24
Finished Feb 29 02:03:39 PM PST 24
Peak memory 206992 kb
Host smart-3710717e-193f-4025-8931-e64e85170481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758311037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.758311037
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.561067897
Short name T641
Test name
Test status
Simulation time 129059075109 ps
CPU time 1202.82 seconds
Started Feb 29 02:03:13 PM PST 24
Finished Feb 29 02:23:17 PM PST 24
Peak memory 222784 kb
Host smart-2fcf6a36-dd17-4671-9645-331f9f166b22
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561067897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.561067897
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.2268944707
Short name T828
Test name
Test status
Simulation time 518658124 ps
CPU time 5.2 seconds
Started Feb 29 02:03:13 PM PST 24
Finished Feb 29 02:03:19 PM PST 24
Peak memory 208952 kb
Host smart-9d0da3e8-d725-4026-a1e5-df2cd2dd5277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2268944707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.2268944707
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.2355414795
Short name T764
Test name
Test status
Simulation time 203012704 ps
CPU time 3.45 seconds
Started Feb 29 02:03:13 PM PST 24
Finished Feb 29 02:03:17 PM PST 24
Peak memory 209464 kb
Host smart-fa7aa530-00aa-462b-a148-161e4c67acd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355414795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.2355414795
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.1699728303
Short name T97
Test name
Test status
Simulation time 20841195 ps
CPU time 0.7 seconds
Started Feb 29 02:03:17 PM PST 24
Finished Feb 29 02:03:18 PM PST 24
Peak memory 205344 kb
Host smart-30a10b86-370a-421f-8456-96c2823c6f81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699728303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.1699728303
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.3886232774
Short name T395
Test name
Test status
Simulation time 251769378 ps
CPU time 3.66 seconds
Started Feb 29 02:03:15 PM PST 24
Finished Feb 29 02:03:19 PM PST 24
Peak memory 213716 kb
Host smart-70a70c37-6720-4153-b091-ea3e2562fd89
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3886232774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.3886232774
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.3820953237
Short name T491
Test name
Test status
Simulation time 337638593 ps
CPU time 3.02 seconds
Started Feb 29 02:03:30 PM PST 24
Finished Feb 29 02:03:33 PM PST 24
Peak memory 213588 kb
Host smart-abf1dd76-55e8-44d5-8f62-5831f8d3f623
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820953237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.3820953237
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.3884839554
Short name T580
Test name
Test status
Simulation time 179746998 ps
CPU time 4.13 seconds
Started Feb 29 02:03:13 PM PST 24
Finished Feb 29 02:03:18 PM PST 24
Peak memory 218024 kb
Host smart-fa6be40e-9042-45a8-92bb-3bad0fd6ef72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3884839554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.3884839554
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.967905940
Short name T326
Test name
Test status
Simulation time 109165262 ps
CPU time 2.43 seconds
Started Feb 29 02:03:12 PM PST 24
Finished Feb 29 02:03:15 PM PST 24
Peak memory 213740 kb
Host smart-c65e76a1-9c4c-4da2-9f72-3042c9e0ba82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=967905940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.967905940
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.1226380327
Short name T352
Test name
Test status
Simulation time 482523589 ps
CPU time 4.22 seconds
Started Feb 29 02:03:12 PM PST 24
Finished Feb 29 02:03:17 PM PST 24
Peak memory 221776 kb
Host smart-c8f9992e-d886-47f0-adc5-1875680bf893
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226380327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.1226380327
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.1098566272
Short name T346
Test name
Test status
Simulation time 226142208 ps
CPU time 3.64 seconds
Started Feb 29 02:03:36 PM PST 24
Finished Feb 29 02:03:40 PM PST 24
Peak memory 208796 kb
Host smart-ca5a7d61-8abc-4280-bf75-96e0f39f0b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098566272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.1098566272
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.792209368
Short name T686
Test name
Test status
Simulation time 50657386 ps
CPU time 2.57 seconds
Started Feb 29 02:03:14 PM PST 24
Finished Feb 29 02:03:16 PM PST 24
Peak memory 205852 kb
Host smart-4219919f-1298-4731-b32c-227e284277c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792209368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.792209368
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.2669642947
Short name T758
Test name
Test status
Simulation time 376727842 ps
CPU time 3.69 seconds
Started Feb 29 02:03:14 PM PST 24
Finished Feb 29 02:03:18 PM PST 24
Peak memory 208136 kb
Host smart-65019cd4-460a-45db-9faa-939683683dc9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669642947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.2669642947
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.1802002816
Short name T369
Test name
Test status
Simulation time 296671425 ps
CPU time 2.92 seconds
Started Feb 29 02:03:14 PM PST 24
Finished Feb 29 02:03:17 PM PST 24
Peak memory 205880 kb
Host smart-65806038-ce59-4572-83f3-2bbdfe5d501b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802002816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.1802002816
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.1235249967
Short name T241
Test name
Test status
Simulation time 121084809 ps
CPU time 4.23 seconds
Started Feb 29 02:03:14 PM PST 24
Finished Feb 29 02:03:18 PM PST 24
Peak memory 205756 kb
Host smart-315b69f7-6d38-444e-8c2c-cbbaf7bfc059
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235249967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.1235249967
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.953110836
Short name T899
Test name
Test status
Simulation time 45236151 ps
CPU time 1.99 seconds
Started Feb 29 02:03:17 PM PST 24
Finished Feb 29 02:03:19 PM PST 24
Peak memory 209440 kb
Host smart-2cca0d52-99c5-4512-ba76-c9f4fe35fe8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953110836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.953110836
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.1882528183
Short name T729
Test name
Test status
Simulation time 261919066 ps
CPU time 3.97 seconds
Started Feb 29 02:03:12 PM PST 24
Finished Feb 29 02:03:17 PM PST 24
Peak memory 207744 kb
Host smart-92ac443e-a677-4c8b-9774-681f9aeac45d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882528183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.1882528183
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all_with_rand_reset.3498026246
Short name T707
Test name
Test status
Simulation time 1822843031 ps
CPU time 23.74 seconds
Started Feb 29 02:03:14 PM PST 24
Finished Feb 29 02:03:38 PM PST 24
Peak memory 221956 kb
Host smart-a5d12d6f-38b2-49bf-a3c4-2709307a2fa9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498026246 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all_with_rand_reset.3498026246
Directory /workspace/21.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.1898334566
Short name T366
Test name
Test status
Simulation time 391730366 ps
CPU time 3.35 seconds
Started Feb 29 02:03:13 PM PST 24
Finished Feb 29 02:03:17 PM PST 24
Peak memory 207496 kb
Host smart-67213457-bf08-400b-b5a3-1d3605457af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1898334566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.1898334566
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.86296206
Short name T869
Test name
Test status
Simulation time 198998607 ps
CPU time 2.14 seconds
Started Feb 29 02:03:13 PM PST 24
Finished Feb 29 02:03:16 PM PST 24
Peak memory 209244 kb
Host smart-7c436d05-ba72-4405-a55d-9005dd035c5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86296206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.86296206
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.1925035526
Short name T98
Test name
Test status
Simulation time 28429666 ps
CPU time 0.8 seconds
Started Feb 29 02:03:18 PM PST 24
Finished Feb 29 02:03:20 PM PST 24
Peak memory 205328 kb
Host smart-fe2c77f8-4623-4515-8a69-fdbe7f9b19ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1925035526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.1925035526
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.1456760214
Short name T142
Test name
Test status
Simulation time 190716490 ps
CPU time 3.54 seconds
Started Feb 29 02:03:19 PM PST 24
Finished Feb 29 02:03:23 PM PST 24
Peak memory 213620 kb
Host smart-95a7d16c-e4f1-429d-b1ee-0564c16a3fc4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1456760214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.1456760214
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.1815727180
Short name T897
Test name
Test status
Simulation time 256768327 ps
CPU time 3.87 seconds
Started Feb 29 02:03:15 PM PST 24
Finished Feb 29 02:03:19 PM PST 24
Peak memory 220724 kb
Host smart-72e4aef6-9182-4b14-926a-551a2fb79bbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815727180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.1815727180
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.40528976
Short name T355
Test name
Test status
Simulation time 238499840 ps
CPU time 3.18 seconds
Started Feb 29 02:03:37 PM PST 24
Finished Feb 29 02:03:40 PM PST 24
Peak memory 206476 kb
Host smart-d9ef36a7-d0c1-4dd9-81ae-fdb4f154bb00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40528976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.40528976
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.1811855443
Short name T587
Test name
Test status
Simulation time 371786100 ps
CPU time 3.69 seconds
Started Feb 29 02:03:18 PM PST 24
Finished Feb 29 02:03:23 PM PST 24
Peak memory 208380 kb
Host smart-465e987a-ca62-442c-b288-09756d5a9a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811855443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.1811855443
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.3281651148
Short name T643
Test name
Test status
Simulation time 86822479 ps
CPU time 4.21 seconds
Started Feb 29 02:03:13 PM PST 24
Finished Feb 29 02:03:18 PM PST 24
Peak memory 219332 kb
Host smart-d6ba5c8f-748c-4428-9a75-2ea4dbe40bea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3281651148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.3281651148
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.981800356
Short name T380
Test name
Test status
Simulation time 158889279 ps
CPU time 2.97 seconds
Started Feb 29 02:03:18 PM PST 24
Finished Feb 29 02:03:22 PM PST 24
Peak memory 218360 kb
Host smart-df5a7ea0-a595-4e40-a86a-b10b3a8c5b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981800356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.981800356
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.808191861
Short name T318
Test name
Test status
Simulation time 96109090 ps
CPU time 3.59 seconds
Started Feb 29 02:03:17 PM PST 24
Finished Feb 29 02:03:21 PM PST 24
Peak memory 207496 kb
Host smart-3627ce1b-c712-4c51-aea3-63aa99ee2d63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=808191861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.808191861
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.1538294182
Short name T461
Test name
Test status
Simulation time 438752533 ps
CPU time 10.92 seconds
Started Feb 29 02:03:16 PM PST 24
Finished Feb 29 02:03:27 PM PST 24
Peak memory 207132 kb
Host smart-e0038e2d-9f22-4d8a-b9d5-20ec05614d0c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538294182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.1538294182
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.2367785323
Short name T683
Test name
Test status
Simulation time 537533478 ps
CPU time 3.47 seconds
Started Feb 29 02:03:17 PM PST 24
Finished Feb 29 02:03:21 PM PST 24
Peak memory 206036 kb
Host smart-3c7ad0a7-1a54-4415-8650-0bcf7aebc104
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2367785323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.2367785323
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.1908555336
Short name T597
Test name
Test status
Simulation time 25344302 ps
CPU time 1.91 seconds
Started Feb 29 02:03:13 PM PST 24
Finished Feb 29 02:03:15 PM PST 24
Peak memory 206028 kb
Host smart-ef1122d9-5eda-43ed-a16a-6da6d191bfbf
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908555336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.1908555336
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.1927687759
Short name T838
Test name
Test status
Simulation time 127750300 ps
CPU time 1.95 seconds
Started Feb 29 02:03:19 PM PST 24
Finished Feb 29 02:03:21 PM PST 24
Peak memory 207700 kb
Host smart-4f7fac12-003a-41c6-b560-fd5dab34e1df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927687759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.1927687759
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.628354863
Short name T531
Test name
Test status
Simulation time 294584095 ps
CPU time 3.21 seconds
Started Feb 29 02:03:18 PM PST 24
Finished Feb 29 02:03:22 PM PST 24
Peak memory 207720 kb
Host smart-da64e218-34e2-4ae7-87db-a30cb39678c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628354863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.628354863
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.3992722825
Short name T306
Test name
Test status
Simulation time 3561838177 ps
CPU time 30.68 seconds
Started Feb 29 02:03:16 PM PST 24
Finished Feb 29 02:03:47 PM PST 24
Peak memory 214964 kb
Host smart-90aa4355-0d1e-46f4-b00f-6686a824b745
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3992722825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.3992722825
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_stress_all_with_rand_reset.1580533632
Short name T100
Test name
Test status
Simulation time 3784979893 ps
CPU time 7.68 seconds
Started Feb 29 02:03:18 PM PST 24
Finished Feb 29 02:03:27 PM PST 24
Peak memory 222032 kb
Host smart-c26d43a6-de56-4ebb-a9c2-e806e6c5e82a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580533632 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all_with_rand_reset.1580533632
Directory /workspace/22.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.958663221
Short name T903
Test name
Test status
Simulation time 1812903098 ps
CPU time 7.07 seconds
Started Feb 29 02:03:22 PM PST 24
Finished Feb 29 02:03:31 PM PST 24
Peak memory 206344 kb
Host smart-31e46bde-7aed-4b3d-b897-1de2878d09a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958663221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.958663221
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.191856793
Short name T489
Test name
Test status
Simulation time 48628986 ps
CPU time 2.69 seconds
Started Feb 29 02:03:19 PM PST 24
Finished Feb 29 02:03:22 PM PST 24
Peak memory 209456 kb
Host smart-b7badb6b-483d-415e-9b6e-6f93861df5a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191856793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.191856793
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.754534739
Short name T512
Test name
Test status
Simulation time 10771801 ps
CPU time 0.74 seconds
Started Feb 29 02:03:20 PM PST 24
Finished Feb 29 02:03:21 PM PST 24
Peak memory 205296 kb
Host smart-1c7defe9-cd6b-47e8-9fd7-2e157b1baa41
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754534739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.754534739
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.2733131737
Short name T341
Test name
Test status
Simulation time 334498596 ps
CPU time 5.25 seconds
Started Feb 29 02:03:19 PM PST 24
Finished Feb 29 02:03:24 PM PST 24
Peak memory 215060 kb
Host smart-b1048749-33b4-4028-82cb-f3f2779d957d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2733131737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.2733131737
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.2630363645
Short name T752
Test name
Test status
Simulation time 479223405 ps
CPU time 10.36 seconds
Started Feb 29 02:03:16 PM PST 24
Finished Feb 29 02:03:26 PM PST 24
Peak memory 208880 kb
Host smart-67178023-b02a-4bba-9241-78ab23dc17f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630363645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.2630363645
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.3162221544
Short name T407
Test name
Test status
Simulation time 295068803 ps
CPU time 3.05 seconds
Started Feb 29 02:03:18 PM PST 24
Finished Feb 29 02:03:22 PM PST 24
Peak memory 213664 kb
Host smart-805c2a4f-e032-45a2-a25c-7cbee8bc9a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162221544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.3162221544
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.3481190063
Short name T235
Test name
Test status
Simulation time 530154087 ps
CPU time 7.9 seconds
Started Feb 29 02:03:22 PM PST 24
Finished Feb 29 02:03:32 PM PST 24
Peak memory 213548 kb
Host smart-0f363264-d94f-4105-b7aa-732c79a649c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481190063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.3481190063
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.2972815552
Short name T127
Test name
Test status
Simulation time 3655378561 ps
CPU time 9.11 seconds
Started Feb 29 02:03:20 PM PST 24
Finished Feb 29 02:03:29 PM PST 24
Peak memory 221840 kb
Host smart-e8655522-16d7-4df0-9848-9e95efac93d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2972815552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.2972815552
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.3981540006
Short name T548
Test name
Test status
Simulation time 239501504 ps
CPU time 6.33 seconds
Started Feb 29 02:03:19 PM PST 24
Finished Feb 29 02:03:26 PM PST 24
Peak memory 206488 kb
Host smart-aa9ee21b-65b2-440e-816b-e42b232bda77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981540006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.3981540006
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.3140231980
Short name T338
Test name
Test status
Simulation time 925074444 ps
CPU time 27.97 seconds
Started Feb 29 02:03:20 PM PST 24
Finished Feb 29 02:03:49 PM PST 24
Peak memory 207840 kb
Host smart-f186e624-bbd2-471c-8d6d-20ebde963afa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140231980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.3140231980
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.120106817
Short name T864
Test name
Test status
Simulation time 887275467 ps
CPU time 10.2 seconds
Started Feb 29 02:03:18 PM PST 24
Finished Feb 29 02:03:28 PM PST 24
Peak memory 207736 kb
Host smart-01da189c-d951-47bf-b96a-47d031db1032
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120106817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.120106817
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.3059310764
Short name T330
Test name
Test status
Simulation time 218544360 ps
CPU time 2.78 seconds
Started Feb 29 02:03:21 PM PST 24
Finished Feb 29 02:03:27 PM PST 24
Peak memory 207712 kb
Host smart-b1073ccb-d9b6-4b0e-9044-70c16b7f6510
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3059310764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.3059310764
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.1433003066
Short name T18
Test name
Test status
Simulation time 21763486 ps
CPU time 1.86 seconds
Started Feb 29 02:03:15 PM PST 24
Finished Feb 29 02:03:18 PM PST 24
Peak memory 205944 kb
Host smart-b135222c-91d3-4739-9ac3-45db185a218a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433003066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.1433003066
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.2555398572
Short name T227
Test name
Test status
Simulation time 227824831 ps
CPU time 2.47 seconds
Started Feb 29 02:03:21 PM PST 24
Finished Feb 29 02:03:26 PM PST 24
Peak memory 206776 kb
Host smart-6931bd0d-6fcd-4a9d-ac2f-8b72679b10c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2555398572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.2555398572
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.3672458430
Short name T759
Test name
Test status
Simulation time 515341220 ps
CPU time 4.01 seconds
Started Feb 29 02:03:21 PM PST 24
Finished Feb 29 02:03:28 PM PST 24
Peak memory 207744 kb
Host smart-18d620d0-b002-47e3-8b47-5892ecba4d10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672458430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.3672458430
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.1208395050
Short name T589
Test name
Test status
Simulation time 94278630 ps
CPU time 3.64 seconds
Started Feb 29 02:03:22 PM PST 24
Finished Feb 29 02:03:28 PM PST 24
Peak memory 206580 kb
Host smart-f8a2eb78-e54e-457f-9681-ff1262f1846b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208395050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.1208395050
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.4024472225
Short name T66
Test name
Test status
Simulation time 79211199 ps
CPU time 2.4 seconds
Started Feb 29 02:03:22 PM PST 24
Finished Feb 29 02:03:26 PM PST 24
Peak memory 209320 kb
Host smart-8d75f621-45ac-46c7-8158-7f4f467c8efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024472225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.4024472225
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.1776342546
Short name T700
Test name
Test status
Simulation time 14654671 ps
CPU time 0.94 seconds
Started Feb 29 02:03:27 PM PST 24
Finished Feb 29 02:03:28 PM PST 24
Peak memory 205460 kb
Host smart-97358868-4dfb-4935-b8ea-ab92b7d8bdf2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1776342546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.1776342546
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.1826663376
Short name T904
Test name
Test status
Simulation time 203160026 ps
CPU time 10.12 seconds
Started Feb 29 02:03:28 PM PST 24
Finished Feb 29 02:03:38 PM PST 24
Peak memory 221864 kb
Host smart-5085d7ac-bfb1-43cc-be8f-233e8397d208
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1826663376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.1826663376
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.1842953533
Short name T11
Test name
Test status
Simulation time 111037784 ps
CPU time 3.68 seconds
Started Feb 29 02:03:26 PM PST 24
Finished Feb 29 02:03:30 PM PST 24
Peak memory 220796 kb
Host smart-2023df64-2f6b-4be0-9a90-9dffe110a8bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842953533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.1842953533
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.3220384279
Short name T743
Test name
Test status
Simulation time 108827906 ps
CPU time 4.4 seconds
Started Feb 29 02:03:27 PM PST 24
Finished Feb 29 02:03:31 PM PST 24
Peak memory 209028 kb
Host smart-c4de308a-b5ad-45a9-928b-d9369c3e4cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220384279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.3220384279
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.1374782976
Short name T809
Test name
Test status
Simulation time 160362660 ps
CPU time 5.87 seconds
Started Feb 29 02:03:25 PM PST 24
Finished Feb 29 02:03:31 PM PST 24
Peak memory 219096 kb
Host smart-a3e47c7e-9b41-460e-aaeb-e4899373bb30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1374782976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.1374782976
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.3433630266
Short name T673
Test name
Test status
Simulation time 601616899 ps
CPU time 6.94 seconds
Started Feb 29 02:03:29 PM PST 24
Finished Feb 29 02:03:36 PM PST 24
Peak memory 221756 kb
Host smart-77b6deff-3b77-4bb8-984d-60c9c73d6ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433630266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.3433630266
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.1576672015
Short name T255
Test name
Test status
Simulation time 461151990 ps
CPU time 5.19 seconds
Started Feb 29 02:03:33 PM PST 24
Finished Feb 29 02:03:39 PM PST 24
Peak memory 208832 kb
Host smart-c17136c4-167e-4321-bb58-0476f7a64687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576672015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.1576672015
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.3524865184
Short name T291
Test name
Test status
Simulation time 76817983 ps
CPU time 2.93 seconds
Started Feb 29 02:03:27 PM PST 24
Finished Feb 29 02:03:31 PM PST 24
Peak memory 209476 kb
Host smart-e1d7838a-e351-4ab2-ad4a-66b20c2bbb9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524865184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.3524865184
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.2023271154
Short name T657
Test name
Test status
Simulation time 273154623 ps
CPU time 3.5 seconds
Started Feb 29 02:03:30 PM PST 24
Finished Feb 29 02:03:34 PM PST 24
Peak memory 207644 kb
Host smart-36412741-a572-479c-981d-5ab122513e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023271154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.2023271154
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.2552509539
Short name T849
Test name
Test status
Simulation time 227003317 ps
CPU time 3.91 seconds
Started Feb 29 02:03:33 PM PST 24
Finished Feb 29 02:03:37 PM PST 24
Peak memory 207864 kb
Host smart-da8b7b20-2edf-492f-a210-36eb566e7b2f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552509539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.2552509539
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.3456974709
Short name T447
Test name
Test status
Simulation time 190228265 ps
CPU time 2.8 seconds
Started Feb 29 02:03:28 PM PST 24
Finished Feb 29 02:03:31 PM PST 24
Peak memory 205972 kb
Host smart-14db56f0-67f0-42c8-a703-bf600fafcadf
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456974709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.3456974709
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.4286039446
Short name T377
Test name
Test status
Simulation time 2040644400 ps
CPU time 28.44 seconds
Started Feb 29 02:03:27 PM PST 24
Finished Feb 29 02:03:55 PM PST 24
Peak memory 208060 kb
Host smart-b25739b4-b2c6-44fc-bcae-7216a517039b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286039446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.4286039446
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.2920527301
Short name T795
Test name
Test status
Simulation time 187879147 ps
CPU time 2.55 seconds
Started Feb 29 02:03:28 PM PST 24
Finished Feb 29 02:03:31 PM PST 24
Peak memory 207264 kb
Host smart-5992b61b-559a-40d3-958e-2ae02f8aca93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920527301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.2920527301
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.3570446829
Short name T475
Test name
Test status
Simulation time 241565320 ps
CPU time 6.21 seconds
Started Feb 29 02:03:33 PM PST 24
Finished Feb 29 02:03:40 PM PST 24
Peak memory 205676 kb
Host smart-08e885b0-d025-4d5d-b4e1-c5204133ae91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570446829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.3570446829
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.1587500219
Short name T765
Test name
Test status
Simulation time 7374981708 ps
CPU time 116.39 seconds
Started Feb 29 02:03:29 PM PST 24
Finished Feb 29 02:05:26 PM PST 24
Peak memory 213708 kb
Host smart-d5ff587d-4a49-48a9-8053-da6c121703f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587500219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.1587500219
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.292426928
Short name T609
Test name
Test status
Simulation time 2170364355 ps
CPU time 6.48 seconds
Started Feb 29 02:03:24 PM PST 24
Finished Feb 29 02:03:31 PM PST 24
Peak memory 209544 kb
Host smart-66ae30f4-b923-43d6-86fb-83c958aaf82c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292426928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.292426928
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.2184197118
Short name T450
Test name
Test status
Simulation time 74485863 ps
CPU time 0.82 seconds
Started Feb 29 02:03:27 PM PST 24
Finished Feb 29 02:03:29 PM PST 24
Peak memory 205492 kb
Host smart-a1f9d6d9-0ce5-4bb9-9ddf-0c769fa8c121
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184197118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.2184197118
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.2424512447
Short name T874
Test name
Test status
Simulation time 127187721 ps
CPU time 4.58 seconds
Started Feb 29 02:03:27 PM PST 24
Finished Feb 29 02:03:32 PM PST 24
Peak memory 213816 kb
Host smart-cb99adcb-67c8-44f0-b421-7677b02a4218
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2424512447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.2424512447
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.309829535
Short name T28
Test name
Test status
Simulation time 117585537 ps
CPU time 4.36 seconds
Started Feb 29 02:03:32 PM PST 24
Finished Feb 29 02:03:36 PM PST 24
Peak memory 213992 kb
Host smart-51ab09b7-2407-41fe-a3fb-3304cc869285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309829535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.309829535
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.2456793377
Short name T539
Test name
Test status
Simulation time 30200705 ps
CPU time 1.99 seconds
Started Feb 29 02:03:27 PM PST 24
Finished Feb 29 02:03:30 PM PST 24
Peak memory 207344 kb
Host smart-a94e4aab-8762-4571-9983-a0d62f9fe934
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456793377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.2456793377
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.617882712
Short name T494
Test name
Test status
Simulation time 48044432 ps
CPU time 3.1 seconds
Started Feb 29 02:03:31 PM PST 24
Finished Feb 29 02:03:35 PM PST 24
Peak memory 207728 kb
Host smart-99c26bd1-de7e-4eba-918a-c05a00cd0e64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617882712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.617882712
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.3576602275
Short name T776
Test name
Test status
Simulation time 144983966 ps
CPU time 3.99 seconds
Started Feb 29 02:03:26 PM PST 24
Finished Feb 29 02:03:30 PM PST 24
Peak memory 217104 kb
Host smart-e3c5757d-c6c8-4209-a648-66b2cf9bb32d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576602275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.3576602275
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.3458988700
Short name T528
Test name
Test status
Simulation time 1342981875 ps
CPU time 31.23 seconds
Started Feb 29 02:03:33 PM PST 24
Finished Feb 29 02:04:05 PM PST 24
Peak memory 217464 kb
Host smart-f875daa4-b1ac-409e-bb69-c5908e701124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458988700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.3458988700
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.445668055
Short name T373
Test name
Test status
Simulation time 3625258507 ps
CPU time 71.35 seconds
Started Feb 29 02:03:27 PM PST 24
Finished Feb 29 02:04:38 PM PST 24
Peak memory 206944 kb
Host smart-47a6d8d5-ee1f-441f-9b5e-2a1959205f86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445668055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.445668055
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.3643836486
Short name T519
Test name
Test status
Simulation time 1603240117 ps
CPU time 11.79 seconds
Started Feb 29 02:03:27 PM PST 24
Finished Feb 29 02:03:39 PM PST 24
Peak memory 207988 kb
Host smart-17d77168-d699-45f3-8578-9a76379f17e7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643836486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.3643836486
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.3655682794
Short name T794
Test name
Test status
Simulation time 32649431 ps
CPU time 2.22 seconds
Started Feb 29 02:03:27 PM PST 24
Finished Feb 29 02:03:29 PM PST 24
Peak memory 206044 kb
Host smart-59ab3aac-da4a-4996-8c6c-21abe363d347
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655682794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.3655682794
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.1554216855
Short name T17
Test name
Test status
Simulation time 131544156 ps
CPU time 2.53 seconds
Started Feb 29 02:03:28 PM PST 24
Finished Feb 29 02:03:30 PM PST 24
Peak memory 205984 kb
Host smart-cb121f4b-12b6-48cd-a855-cea39a3dd9de
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554216855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.1554216855
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.625109529
Short name T107
Test name
Test status
Simulation time 199924466 ps
CPU time 2.87 seconds
Started Feb 29 02:03:32 PM PST 24
Finished Feb 29 02:03:36 PM PST 24
Peak memory 208452 kb
Host smart-d79282ed-7066-4665-b95e-6b5345c61b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=625109529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.625109529
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.4041741822
Short name T228
Test name
Test status
Simulation time 26321052 ps
CPU time 1.66 seconds
Started Feb 29 02:03:31 PM PST 24
Finished Feb 29 02:03:33 PM PST 24
Peak memory 205956 kb
Host smart-07f1edc1-6972-41a2-9de1-95dc4d231687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4041741822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.4041741822
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.468604478
Short name T393
Test name
Test status
Simulation time 275097051 ps
CPU time 12.36 seconds
Started Feb 29 02:03:45 PM PST 24
Finished Feb 29 02:03:57 PM PST 24
Peak memory 213584 kb
Host smart-2a5b32c5-0fbb-47c6-91c4-b0ab38cfc755
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468604478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.468604478
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.4138275237
Short name T484
Test name
Test status
Simulation time 81422585 ps
CPU time 3.51 seconds
Started Feb 29 02:03:32 PM PST 24
Finished Feb 29 02:03:36 PM PST 24
Peak memory 206196 kb
Host smart-a3a6cf32-78dc-4217-8c17-5711822d70ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138275237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.4138275237
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.399513896
Short name T457
Test name
Test status
Simulation time 103494250 ps
CPU time 2.1 seconds
Started Feb 29 02:03:31 PM PST 24
Finished Feb 29 02:03:34 PM PST 24
Peak memory 209020 kb
Host smart-4e826449-6c0a-4296-a2b6-2aabf306d1b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399513896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.399513896
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.2139139675
Short name T206
Test name
Test status
Simulation time 38927689 ps
CPU time 0.94 seconds
Started Feb 29 02:03:42 PM PST 24
Finished Feb 29 02:03:43 PM PST 24
Peak memory 205320 kb
Host smart-19e6e983-130f-424b-9f4c-2e8566c5487c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139139675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.2139139675
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.1207612795
Short name T125
Test name
Test status
Simulation time 179398376 ps
CPU time 4.61 seconds
Started Feb 29 02:03:45 PM PST 24
Finished Feb 29 02:03:50 PM PST 24
Peak memory 214096 kb
Host smart-c825eb31-47ad-4293-a730-9723b0ad75e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207612795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.1207612795
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.716170885
Short name T711
Test name
Test status
Simulation time 21375847 ps
CPU time 1.4 seconds
Started Feb 29 02:03:32 PM PST 24
Finished Feb 29 02:03:34 PM PST 24
Peak memory 206988 kb
Host smart-f0bc702e-cf83-4eec-94e4-ba3181642941
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=716170885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.716170885
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.2544181367
Short name T722
Test name
Test status
Simulation time 38503138 ps
CPU time 2.65 seconds
Started Feb 29 02:03:33 PM PST 24
Finished Feb 29 02:03:36 PM PST 24
Peak memory 207572 kb
Host smart-3a86320d-9cc8-485f-b8d5-47b470dc7bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2544181367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.2544181367
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.3021831139
Short name T902
Test name
Test status
Simulation time 514401347 ps
CPU time 15.03 seconds
Started Feb 29 02:03:33 PM PST 24
Finished Feb 29 02:03:48 PM PST 24
Peak memory 213700 kb
Host smart-88465e30-ce11-4e76-a0ed-1dfd266ebcb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021831139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.3021831139
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.1370454722
Short name T866
Test name
Test status
Simulation time 141547024 ps
CPU time 4.27 seconds
Started Feb 29 02:03:31 PM PST 24
Finished Feb 29 02:03:36 PM PST 24
Peak memory 205844 kb
Host smart-1f973741-c7fb-4bf0-b741-ca698f952f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370454722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.1370454722
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.1254312013
Short name T614
Test name
Test status
Simulation time 43804504 ps
CPU time 1.94 seconds
Started Feb 29 02:03:29 PM PST 24
Finished Feb 29 02:03:32 PM PST 24
Peak memory 207864 kb
Host smart-467d9b37-2874-401a-96f5-e9e094aeac6a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254312013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.1254312013
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.2671176367
Short name T693
Test name
Test status
Simulation time 439354533 ps
CPU time 5.34 seconds
Started Feb 29 02:03:33 PM PST 24
Finished Feb 29 02:03:38 PM PST 24
Peak memory 207960 kb
Host smart-69d8515b-818f-4c7f-a325-71b9484c88e6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671176367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.2671176367
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.4052757962
Short name T564
Test name
Test status
Simulation time 145492331 ps
CPU time 4.31 seconds
Started Feb 29 02:03:28 PM PST 24
Finished Feb 29 02:03:32 PM PST 24
Peak memory 206464 kb
Host smart-359b31af-f638-44cc-906d-bc5aff4497e3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052757962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.4052757962
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.3578139736
Short name T654
Test name
Test status
Simulation time 828021533 ps
CPU time 15.55 seconds
Started Feb 29 02:03:41 PM PST 24
Finished Feb 29 02:03:57 PM PST 24
Peak memory 207716 kb
Host smart-b4ee366a-c9e9-42e9-8b2c-f2fefd942d77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578139736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.3578139736
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.1144387133
Short name T492
Test name
Test status
Simulation time 6755679783 ps
CPU time 62.56 seconds
Started Feb 29 02:03:32 PM PST 24
Finished Feb 29 02:04:35 PM PST 24
Peak memory 208000 kb
Host smart-95dc0a05-5c6f-40ce-9f12-b0ae86e4848f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144387133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.1144387133
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.2243440712
Short name T247
Test name
Test status
Simulation time 5440096353 ps
CPU time 165.28 seconds
Started Feb 29 02:03:43 PM PST 24
Finished Feb 29 02:06:29 PM PST 24
Peak memory 217052 kb
Host smart-6ea33b6e-da4e-4a32-b118-0fceeffa032a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2243440712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.2243440712
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_stress_all_with_rand_reset.1662645738
Short name T294
Test name
Test status
Simulation time 166312853 ps
CPU time 9.15 seconds
Started Feb 29 02:03:42 PM PST 24
Finished Feb 29 02:03:51 PM PST 24
Peak memory 221972 kb
Host smart-e1faa7b8-8c52-45dd-81b4-b78b4fc8cac6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1662645738 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all_with_rand_reset.1662645738
Directory /workspace/26.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.2373311063
Short name T738
Test name
Test status
Simulation time 251298014 ps
CPU time 3.57 seconds
Started Feb 29 02:03:51 PM PST 24
Finished Feb 29 02:03:55 PM PST 24
Peak memory 206604 kb
Host smart-e552b7e0-1b6e-4f5d-b3f4-245b57b7e8a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373311063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.2373311063
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.513881201
Short name T734
Test name
Test status
Simulation time 43150764 ps
CPU time 1.79 seconds
Started Feb 29 02:03:41 PM PST 24
Finished Feb 29 02:03:43 PM PST 24
Peak memory 208884 kb
Host smart-b29ac7ab-a394-4404-b5b2-e7ac7548c829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513881201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.513881201
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.2488884425
Short name T724
Test name
Test status
Simulation time 16971743 ps
CPU time 0.72 seconds
Started Feb 29 02:03:40 PM PST 24
Finished Feb 29 02:03:42 PM PST 24
Peak memory 205372 kb
Host smart-2baab3f5-260f-4a01-b5db-e1549cb24a8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488884425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.2488884425
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.4290384892
Short name T270
Test name
Test status
Simulation time 98204249 ps
CPU time 3.95 seconds
Started Feb 29 02:03:42 PM PST 24
Finished Feb 29 02:03:46 PM PST 24
Peak memory 213680 kb
Host smart-92e6167e-c773-4146-8779-65991cd490d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4290384892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.4290384892
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.1297629015
Short name T23
Test name
Test status
Simulation time 210919968 ps
CPU time 2.35 seconds
Started Feb 29 02:03:41 PM PST 24
Finished Feb 29 02:03:44 PM PST 24
Peak memory 218004 kb
Host smart-45988093-6885-45e5-8c36-c3c370247945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297629015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.1297629015
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.2743621392
Short name T655
Test name
Test status
Simulation time 1455453871 ps
CPU time 5.81 seconds
Started Feb 29 02:03:43 PM PST 24
Finished Feb 29 02:03:49 PM PST 24
Peak memory 206812 kb
Host smart-4908fe79-e1c5-4d31-9f2f-3b817ee41ba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2743621392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.2743621392
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.1366480714
Short name T601
Test name
Test status
Simulation time 1219468464 ps
CPU time 5.23 seconds
Started Feb 29 02:03:43 PM PST 24
Finished Feb 29 02:03:48 PM PST 24
Peak memory 214124 kb
Host smart-26ba5af1-2e10-4ed5-850a-cf1e0e34c71e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1366480714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.1366480714
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.735650588
Short name T890
Test name
Test status
Simulation time 213624638 ps
CPU time 8.85 seconds
Started Feb 29 02:03:43 PM PST 24
Finished Feb 29 02:03:52 PM PST 24
Peak memory 213756 kb
Host smart-be42ed6e-b289-4b20-a3c3-59caf14523ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=735650588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.735650588
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.2848123512
Short name T46
Test name
Test status
Simulation time 914897679 ps
CPU time 7 seconds
Started Feb 29 02:03:46 PM PST 24
Finished Feb 29 02:03:53 PM PST 24
Peak memory 221824 kb
Host smart-4b09f675-b011-43e3-936d-d60ee8c33e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848123512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.2848123512
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.3990105239
Short name T391
Test name
Test status
Simulation time 2854532071 ps
CPU time 6.41 seconds
Started Feb 29 02:03:41 PM PST 24
Finished Feb 29 02:03:48 PM PST 24
Peak memory 209120 kb
Host smart-8ac8f43c-452c-47e9-9a0b-46a3ff04007a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990105239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.3990105239
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.341402880
Short name T231
Test name
Test status
Simulation time 236044263 ps
CPU time 1.81 seconds
Started Feb 29 02:03:43 PM PST 24
Finished Feb 29 02:03:45 PM PST 24
Peak memory 205944 kb
Host smart-b11a6fb6-8925-43a1-8474-d250808ae330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341402880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.341402880
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.1935949682
Short name T610
Test name
Test status
Simulation time 34263704 ps
CPU time 2.41 seconds
Started Feb 29 02:03:41 PM PST 24
Finished Feb 29 02:03:44 PM PST 24
Peak memory 205948 kb
Host smart-5a89f9b2-3bec-41e9-851c-f566f6c79540
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1935949682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.1935949682
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.1278386038
Short name T618
Test name
Test status
Simulation time 92497969 ps
CPU time 3.64 seconds
Started Feb 29 02:03:42 PM PST 24
Finished Feb 29 02:03:46 PM PST 24
Peak memory 208228 kb
Host smart-b2f5031c-b09e-4dd2-8598-0aa2a6d440fe
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278386038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.1278386038
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.797948598
Short name T565
Test name
Test status
Simulation time 733279088 ps
CPU time 18.5 seconds
Started Feb 29 02:03:43 PM PST 24
Finished Feb 29 02:04:02 PM PST 24
Peak memory 207644 kb
Host smart-508d014c-2e1d-4756-baa4-e1a5648c1eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797948598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.797948598
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.1777281539
Short name T727
Test name
Test status
Simulation time 56714537 ps
CPU time 2.28 seconds
Started Feb 29 02:03:42 PM PST 24
Finished Feb 29 02:03:45 PM PST 24
Peak memory 207492 kb
Host smart-1ffd367a-f0f6-46b0-917c-1e2d7f59eab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777281539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.1777281539
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.2676359728
Short name T485
Test name
Test status
Simulation time 154023275 ps
CPU time 3.97 seconds
Started Feb 29 02:03:43 PM PST 24
Finished Feb 29 02:03:47 PM PST 24
Peak memory 206412 kb
Host smart-d5b852b0-4ea0-487e-91db-b21ebf3ada90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676359728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.2676359728
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_stress_all_with_rand_reset.1886815272
Short name T119
Test name
Test status
Simulation time 1216214214 ps
CPU time 10.59 seconds
Started Feb 29 02:03:43 PM PST 24
Finished Feb 29 02:03:55 PM PST 24
Peak memory 221916 kb
Host smart-08ac0afc-42bc-4304-8335-2e4688f079e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886815272 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all_with_rand_reset.1886815272
Directory /workspace/27.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.208436251
Short name T273
Test name
Test status
Simulation time 120534359 ps
CPU time 5.18 seconds
Started Feb 29 02:03:45 PM PST 24
Finished Feb 29 02:03:51 PM PST 24
Peak memory 206632 kb
Host smart-607487ce-1d96-4919-934f-b180298f3377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208436251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.208436251
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.2841141243
Short name T747
Test name
Test status
Simulation time 68395419 ps
CPU time 3.04 seconds
Started Feb 29 02:03:41 PM PST 24
Finished Feb 29 02:03:45 PM PST 24
Peak memory 209112 kb
Host smart-3530b26e-eb44-4658-912b-f83fc8a80c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841141243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.2841141243
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.534135961
Short name T779
Test name
Test status
Simulation time 50461591 ps
CPU time 0.76 seconds
Started Feb 29 02:04:02 PM PST 24
Finished Feb 29 02:04:03 PM PST 24
Peak memory 205372 kb
Host smart-2b9f9c31-b8d3-4f10-99b8-1ee2b51ce767
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534135961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.534135961
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.857166895
Short name T124
Test name
Test status
Simulation time 204398262 ps
CPU time 4.09 seconds
Started Feb 29 02:04:03 PM PST 24
Finished Feb 29 02:04:07 PM PST 24
Peak memory 214612 kb
Host smart-6f50f95a-5cc3-4fbd-ae2c-0b72e272c471
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=857166895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.857166895
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.2583989722
Short name T834
Test name
Test status
Simulation time 161386975 ps
CPU time 3.13 seconds
Started Feb 29 02:04:02 PM PST 24
Finished Feb 29 02:04:06 PM PST 24
Peak memory 218664 kb
Host smart-f1951196-f3a2-43d7-b733-147eb8751d1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583989722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.2583989722
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.2033013608
Short name T187
Test name
Test status
Simulation time 27160092 ps
CPU time 2.22 seconds
Started Feb 29 02:04:01 PM PST 24
Finished Feb 29 02:04:04 PM PST 24
Peak memory 207424 kb
Host smart-9ba10319-b0cb-4996-bcda-6de3b2a89f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2033013608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.2033013608
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.3263281681
Short name T329
Test name
Test status
Simulation time 33099106 ps
CPU time 2.69 seconds
Started Feb 29 02:04:00 PM PST 24
Finished Feb 29 02:04:03 PM PST 24
Peak memory 208568 kb
Host smart-a30db007-fa48-483c-bf6e-34e8ff8dfe38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263281681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.3263281681
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.862976371
Short name T713
Test name
Test status
Simulation time 64887516 ps
CPU time 3.18 seconds
Started Feb 29 02:04:04 PM PST 24
Finished Feb 29 02:04:08 PM PST 24
Peak memory 213752 kb
Host smart-06ccfd59-62fc-4ae8-83f1-20857ad8d5ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862976371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.862976371
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.2883477279
Short name T749
Test name
Test status
Simulation time 1193041934 ps
CPU time 9.32 seconds
Started Feb 29 02:04:01 PM PST 24
Finished Feb 29 02:04:10 PM PST 24
Peak memory 207532 kb
Host smart-531ee676-831f-4af3-a4cc-7d700c1c9ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883477279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.2883477279
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.2886025195
Short name T735
Test name
Test status
Simulation time 59213139 ps
CPU time 2.2 seconds
Started Feb 29 02:04:01 PM PST 24
Finished Feb 29 02:04:03 PM PST 24
Peak memory 208044 kb
Host smart-e79c78cf-3544-4fbb-b8ed-4e4f95ff5ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886025195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.2886025195
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.4197436210
Short name T237
Test name
Test status
Simulation time 819004435 ps
CPU time 9.84 seconds
Started Feb 29 02:04:01 PM PST 24
Finished Feb 29 02:04:11 PM PST 24
Peak memory 207912 kb
Host smart-7a0aadba-7db1-455f-b375-31db330c823d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197436210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.4197436210
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.1097130922
Short name T517
Test name
Test status
Simulation time 4119383415 ps
CPU time 15.12 seconds
Started Feb 29 02:04:02 PM PST 24
Finished Feb 29 02:04:18 PM PST 24
Peak memory 207912 kb
Host smart-5c3ad77b-0b9b-48fa-bdc5-c6939651573e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1097130922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.1097130922
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.3935064069
Short name T421
Test name
Test status
Simulation time 324648980 ps
CPU time 5.25 seconds
Started Feb 29 02:04:03 PM PST 24
Finished Feb 29 02:04:09 PM PST 24
Peak memory 207148 kb
Host smart-c7f7e95a-790b-4c37-bd0d-5a024db9c2af
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3935064069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.3935064069
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.42894018
Short name T414
Test name
Test status
Simulation time 135621248 ps
CPU time 2.4 seconds
Started Feb 29 02:04:01 PM PST 24
Finished Feb 29 02:04:05 PM PST 24
Peak memory 208760 kb
Host smart-03be1d1b-b569-480d-bd44-0be07770be8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42894018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.42894018
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.506885018
Short name T468
Test name
Test status
Simulation time 116641534 ps
CPU time 2.76 seconds
Started Feb 29 02:03:47 PM PST 24
Finished Feb 29 02:03:50 PM PST 24
Peak memory 205804 kb
Host smart-e6dade03-c04c-469c-82e6-4c38f47db664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506885018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.506885018
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.4125189710
Short name T193
Test name
Test status
Simulation time 1837837780 ps
CPU time 23.83 seconds
Started Feb 29 02:03:59 PM PST 24
Finished Feb 29 02:04:23 PM PST 24
Peak memory 214604 kb
Host smart-b08b5805-8304-4399-82ab-fb0ea76dff0c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4125189710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.4125189710
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.3863476704
Short name T883
Test name
Test status
Simulation time 38854269 ps
CPU time 3.05 seconds
Started Feb 29 02:04:02 PM PST 24
Finished Feb 29 02:04:06 PM PST 24
Peak memory 207456 kb
Host smart-c41fd053-49e7-4e29-a430-59943621085e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863476704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.3863476704
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.1901377472
Short name T59
Test name
Test status
Simulation time 50498445 ps
CPU time 2.68 seconds
Started Feb 29 02:04:01 PM PST 24
Finished Feb 29 02:04:05 PM PST 24
Peak memory 209084 kb
Host smart-069f6671-ee18-49cd-971d-be1d22cd762c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901377472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.1901377472
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.1200014632
Short name T571
Test name
Test status
Simulation time 103756151 ps
CPU time 0.77 seconds
Started Feb 29 02:04:03 PM PST 24
Finished Feb 29 02:04:05 PM PST 24
Peak memory 205268 kb
Host smart-fde7831e-7c5e-45e1-ae20-117f578dea59
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200014632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.1200014632
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.4057472669
Short name T435
Test name
Test status
Simulation time 207909802 ps
CPU time 11.17 seconds
Started Feb 29 02:04:01 PM PST 24
Finished Feb 29 02:04:14 PM PST 24
Peak memory 214384 kb
Host smart-e756917a-22d3-4a2a-8484-44a216413c28
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4057472669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.4057472669
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.1903700850
Short name T799
Test name
Test status
Simulation time 67396755 ps
CPU time 3.86 seconds
Started Feb 29 02:04:04 PM PST 24
Finished Feb 29 02:04:08 PM PST 24
Peak memory 209224 kb
Host smart-2be876a6-daaf-4885-baa8-d9e730d722f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903700850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.1903700850
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.1755682668
Short name T47
Test name
Test status
Simulation time 24678006 ps
CPU time 1.86 seconds
Started Feb 29 02:04:01 PM PST 24
Finished Feb 29 02:04:04 PM PST 24
Peak memory 209008 kb
Host smart-234a8992-3c8b-4aa7-bc09-63169190fce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755682668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.1755682668
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.390460842
Short name T90
Test name
Test status
Simulation time 548213032 ps
CPU time 7.18 seconds
Started Feb 29 02:04:01 PM PST 24
Finished Feb 29 02:04:08 PM PST 24
Peak memory 213572 kb
Host smart-1e8a4684-f443-47fb-a1b8-faab059b00d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390460842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.390460842
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.2720242517
Short name T467
Test name
Test status
Simulation time 1014050923 ps
CPU time 3.71 seconds
Started Feb 29 02:04:04 PM PST 24
Finished Feb 29 02:04:08 PM PST 24
Peak memory 213700 kb
Host smart-ed95cbf2-5e70-438a-b32d-4def3c797025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720242517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.2720242517
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.1098906645
Short name T857
Test name
Test status
Simulation time 83647816 ps
CPU time 4.27 seconds
Started Feb 29 02:04:03 PM PST 24
Finished Feb 29 02:04:08 PM PST 24
Peak memory 217828 kb
Host smart-824ebfee-e2e6-47f4-acc0-b8d70fcf9762
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098906645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.1098906645
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.1014115544
Short name T876
Test name
Test status
Simulation time 156981314 ps
CPU time 3.16 seconds
Started Feb 29 02:04:02 PM PST 24
Finished Feb 29 02:04:06 PM PST 24
Peak memory 207748 kb
Host smart-e2cec23b-ca3e-4f3f-95c9-319ff99e6ed2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014115544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.1014115544
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.1889915467
Short name T607
Test name
Test status
Simulation time 82203251 ps
CPU time 1.83 seconds
Started Feb 29 02:04:15 PM PST 24
Finished Feb 29 02:04:16 PM PST 24
Peak memory 205908 kb
Host smart-ad649340-96a7-4cb4-b630-63ccdb647ad0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889915467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.1889915467
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.3724136120
Short name T684
Test name
Test status
Simulation time 61868199 ps
CPU time 3.32 seconds
Started Feb 29 02:04:04 PM PST 24
Finished Feb 29 02:04:08 PM PST 24
Peak memory 206028 kb
Host smart-5a109405-d217-4d45-abb2-e4e41a2f15c6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724136120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.3724136120
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.534009829
Short name T219
Test name
Test status
Simulation time 194583395 ps
CPU time 2.51 seconds
Started Feb 29 02:04:01 PM PST 24
Finished Feb 29 02:04:05 PM PST 24
Peak memory 206472 kb
Host smart-ce697cd7-084a-45bc-a97e-a29a0f2ec727
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=534009829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.534009829
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.4079680670
Short name T361
Test name
Test status
Simulation time 25867536 ps
CPU time 2.1 seconds
Started Feb 29 02:04:01 PM PST 24
Finished Feb 29 02:04:04 PM PST 24
Peak memory 214984 kb
Host smart-b3c7ebd9-dc84-42ca-8143-d41acc019cde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079680670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.4079680670
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.1998114328
Short name T446
Test name
Test status
Simulation time 34305202 ps
CPU time 2.27 seconds
Started Feb 29 02:04:03 PM PST 24
Finished Feb 29 02:04:05 PM PST 24
Peak memory 205884 kb
Host smart-d9da090d-6a0f-4085-a557-e856a18b965d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998114328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.1998114328
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.3445658550
Short name T590
Test name
Test status
Simulation time 292134013 ps
CPU time 4.25 seconds
Started Feb 29 02:04:02 PM PST 24
Finished Feb 29 02:04:07 PM PST 24
Peak memory 207256 kb
Host smart-e6efccfd-9bab-446d-978c-d195770095bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3445658550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.3445658550
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.1901043220
Short name T807
Test name
Test status
Simulation time 71873495 ps
CPU time 1.48 seconds
Started Feb 29 02:04:02 PM PST 24
Finished Feb 29 02:04:04 PM PST 24
Peak memory 209000 kb
Host smart-ab62ae56-3a39-4708-aa01-9db314b08eef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901043220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.1901043220
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.1762437674
Short name T829
Test name
Test status
Simulation time 31672945 ps
CPU time 0.72 seconds
Started Feb 29 02:01:22 PM PST 24
Finished Feb 29 02:01:23 PM PST 24
Peak memory 205268 kb
Host smart-0bdfc87d-c478-4249-8800-dd463785cc5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762437674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.1762437674
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.3044561332
Short name T122
Test name
Test status
Simulation time 45843231 ps
CPU time 3.35 seconds
Started Feb 29 02:01:12 PM PST 24
Finished Feb 29 02:01:16 PM PST 24
Peak memory 214996 kb
Host smart-cd16ba14-8b8a-4fac-93fb-f212babe8c26
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3044561332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.3044561332
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.518532429
Short name T638
Test name
Test status
Simulation time 45288858 ps
CPU time 1.63 seconds
Started Feb 29 02:01:16 PM PST 24
Finished Feb 29 02:01:18 PM PST 24
Peak memory 207948 kb
Host smart-c74236c8-75d0-46f7-b5c8-f4e7e682ab7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518532429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.518532429
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.635642804
Short name T730
Test name
Test status
Simulation time 109023247 ps
CPU time 3.87 seconds
Started Feb 29 02:01:13 PM PST 24
Finished Feb 29 02:01:18 PM PST 24
Peak memory 219592 kb
Host smart-dbc8693f-ae79-4e0e-a085-42f18b913de4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635642804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.635642804
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.3934506926
Short name T814
Test name
Test status
Simulation time 546028883 ps
CPU time 6.01 seconds
Started Feb 29 02:01:13 PM PST 24
Finished Feb 29 02:01:19 PM PST 24
Peak memory 217380 kb
Host smart-4e094fb1-5bb7-4654-9e08-b3d7c579a1cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934506926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.3934506926
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.2222387575
Short name T823
Test name
Test status
Simulation time 726339160 ps
CPU time 9.67 seconds
Started Feb 29 02:01:15 PM PST 24
Finished Feb 29 02:01:25 PM PST 24
Peak memory 213696 kb
Host smart-b999eba3-1fc2-472e-bda7-9a687a2d83bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2222387575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.2222387575
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.2899921245
Short name T13
Test name
Test status
Simulation time 291769431 ps
CPU time 10.72 seconds
Started Feb 29 02:01:23 PM PST 24
Finished Feb 29 02:01:34 PM PST 24
Peak memory 230740 kb
Host smart-9952b943-4ad0-404b-8146-deaf2227c814
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2899921245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.2899921245
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sideload.478000945
Short name T627
Test name
Test status
Simulation time 67233581 ps
CPU time 3.43 seconds
Started Feb 29 02:01:15 PM PST 24
Finished Feb 29 02:01:19 PM PST 24
Peak memory 205924 kb
Host smart-099cc776-18b2-4891-8b8c-335a4e9b5302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478000945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.478000945
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.1672978764
Short name T633
Test name
Test status
Simulation time 372319543 ps
CPU time 4.32 seconds
Started Feb 29 02:01:13 PM PST 24
Finished Feb 29 02:01:17 PM PST 24
Peak memory 207636 kb
Host smart-fbef7b81-7626-4dcc-a502-84dcf7f5e05d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672978764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.1672978764
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.1670816195
Short name T417
Test name
Test status
Simulation time 22703892 ps
CPU time 1.82 seconds
Started Feb 29 02:01:13 PM PST 24
Finished Feb 29 02:01:15 PM PST 24
Peak memory 206088 kb
Host smart-4d4379a4-58e2-48c7-a0bb-8a52538ccc91
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670816195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.1670816195
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.2386346183
Short name T418
Test name
Test status
Simulation time 16140446978 ps
CPU time 51.41 seconds
Started Feb 29 02:01:11 PM PST 24
Finished Feb 29 02:02:03 PM PST 24
Peak memory 207116 kb
Host smart-289362b6-8491-4052-855f-cb09298a0bb3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386346183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.2386346183
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.1141470720
Short name T230
Test name
Test status
Simulation time 65022141 ps
CPU time 1.78 seconds
Started Feb 29 02:01:13 PM PST 24
Finished Feb 29 02:01:16 PM PST 24
Peak memory 207412 kb
Host smart-36d82c0a-2193-4057-92a3-9089b0ecc285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141470720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.1141470720
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.259924396
Short name T906
Test name
Test status
Simulation time 834649531 ps
CPU time 8.16 seconds
Started Feb 29 02:01:14 PM PST 24
Finished Feb 29 02:01:23 PM PST 24
Peak memory 207304 kb
Host smart-0b861d54-9bc0-45ae-bfe0-fd42d708f273
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259924396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.259924396
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all_with_rand_reset.1021947102
Short name T177
Test name
Test status
Simulation time 380875328 ps
CPU time 8.51 seconds
Started Feb 29 02:01:21 PM PST 24
Finished Feb 29 02:01:29 PM PST 24
Peak memory 219424 kb
Host smart-2b72086c-45bb-44ef-8ebe-a4dbfc0bce99
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021947102 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all_with_rand_reset.1021947102
Directory /workspace/3.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.104535019
Short name T756
Test name
Test status
Simulation time 1062595776 ps
CPU time 7.54 seconds
Started Feb 29 02:01:12 PM PST 24
Finished Feb 29 02:01:20 PM PST 24
Peak memory 217688 kb
Host smart-75853645-ddb8-4741-a56f-5e4f0f841b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104535019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.104535019
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.1155834451
Short name T701
Test name
Test status
Simulation time 634136864 ps
CPU time 3.7 seconds
Started Feb 29 02:01:16 PM PST 24
Finished Feb 29 02:01:20 PM PST 24
Peak memory 209264 kb
Host smart-a7f79fd6-9c52-47c5-b839-e3b36448ef60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155834451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.1155834451
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.2721537331
Short name T712
Test name
Test status
Simulation time 43761595 ps
CPU time 0.71 seconds
Started Feb 29 02:04:18 PM PST 24
Finished Feb 29 02:04:18 PM PST 24
Peak memory 205336 kb
Host smart-123c4bf6-3f81-4212-9016-f0985c17974b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721537331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.2721537331
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.3011675444
Short name T438
Test name
Test status
Simulation time 214537770 ps
CPU time 4.24 seconds
Started Feb 29 02:04:05 PM PST 24
Finished Feb 29 02:04:09 PM PST 24
Peak memory 214280 kb
Host smart-a91ed348-e878-413d-88c1-fc2229131bfb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3011675444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.3011675444
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.2395651896
Short name T726
Test name
Test status
Simulation time 403505853 ps
CPU time 3.04 seconds
Started Feb 29 02:04:03 PM PST 24
Finished Feb 29 02:04:07 PM PST 24
Peak memory 213716 kb
Host smart-e2468e36-40ea-4215-8a2a-e7b6a90145ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395651896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.2395651896
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.619391499
Short name T301
Test name
Test status
Simulation time 67486470 ps
CPU time 3.9 seconds
Started Feb 29 02:04:03 PM PST 24
Finished Feb 29 02:04:08 PM PST 24
Peak memory 213704 kb
Host smart-ca297a5f-c22b-49c4-94c6-147282948792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=619391499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.619391499
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.1867793119
Short name T629
Test name
Test status
Simulation time 221929651 ps
CPU time 11.04 seconds
Started Feb 29 02:04:04 PM PST 24
Finished Feb 29 02:04:16 PM PST 24
Peak memory 219404 kb
Host smart-7a0802d9-4938-47a8-b191-fc61ae796990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867793119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.1867793119
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.1145493316
Short name T669
Test name
Test status
Simulation time 15026603883 ps
CPU time 96.58 seconds
Started Feb 29 02:04:02 PM PST 24
Finished Feb 29 02:05:39 PM PST 24
Peak memory 208332 kb
Host smart-e7daff97-c445-4409-9cfa-eb44c3bdcd9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1145493316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.1145493316
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.2491170324
Short name T625
Test name
Test status
Simulation time 213982647 ps
CPU time 6.12 seconds
Started Feb 29 02:04:04 PM PST 24
Finished Feb 29 02:04:11 PM PST 24
Peak memory 206884 kb
Host smart-584286db-82cf-45af-b94b-c9be42e1e6c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2491170324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.2491170324
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.2696965570
Short name T599
Test name
Test status
Simulation time 47721892 ps
CPU time 2.59 seconds
Started Feb 29 02:04:03 PM PST 24
Finished Feb 29 02:04:06 PM PST 24
Peak memory 206060 kb
Host smart-a50b4cab-fa2a-4c2d-94a3-25ec5394a5f5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2696965570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.2696965570
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.1526179540
Short name T537
Test name
Test status
Simulation time 550074472 ps
CPU time 6.14 seconds
Started Feb 29 02:04:02 PM PST 24
Finished Feb 29 02:04:09 PM PST 24
Peak memory 207896 kb
Host smart-7c6c0ae6-352e-49b4-8be9-046d694edd5c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1526179540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.1526179540
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.2399743078
Short name T501
Test name
Test status
Simulation time 55600161 ps
CPU time 3.17 seconds
Started Feb 29 02:04:05 PM PST 24
Finished Feb 29 02:04:08 PM PST 24
Peak memory 208076 kb
Host smart-8b7fe73b-f6a4-4451-9c7e-5ffbbb39c90a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399743078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.2399743078
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.599498080
Short name T398
Test name
Test status
Simulation time 93725865 ps
CPU time 3.76 seconds
Started Feb 29 02:04:03 PM PST 24
Finished Feb 29 02:04:08 PM PST 24
Peak memory 213736 kb
Host smart-1c6e00fd-2872-49a2-a9a5-3e49ca71d3fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599498080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.599498080
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.2734140545
Short name T634
Test name
Test status
Simulation time 1063486573 ps
CPU time 6.63 seconds
Started Feb 29 02:04:00 PM PST 24
Finished Feb 29 02:04:07 PM PST 24
Peak memory 207680 kb
Host smart-8a20e281-73dd-479f-9b6b-affaf75fa836
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734140545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.2734140545
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.3832645730
Short name T402
Test name
Test status
Simulation time 445231608 ps
CPU time 12.9 seconds
Started Feb 29 02:04:03 PM PST 24
Finished Feb 29 02:04:17 PM PST 24
Peak memory 215188 kb
Host smart-fb942070-56df-4209-bd84-6109353b26de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3832645730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.3832645730
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_stress_all_with_rand_reset.90877524
Short name T118
Test name
Test status
Simulation time 525094858 ps
CPU time 9.84 seconds
Started Feb 29 02:04:20 PM PST 24
Finished Feb 29 02:04:30 PM PST 24
Peak memory 222076 kb
Host smart-b96382ce-e103-46fe-b1a4-9bd51eb05ee3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90877524 -assert nopostp
roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all_with_rand_reset.90877524
Directory /workspace/30.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.3886323700
Short name T349
Test name
Test status
Simulation time 95189204 ps
CPU time 4.61 seconds
Started Feb 29 02:04:05 PM PST 24
Finished Feb 29 02:04:10 PM PST 24
Peak memory 206812 kb
Host smart-78bfdde9-3ecf-4897-9361-5d0b3215d6a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886323700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.3886323700
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.1192941378
Short name T848
Test name
Test status
Simulation time 385320534 ps
CPU time 2.95 seconds
Started Feb 29 02:04:03 PM PST 24
Finished Feb 29 02:04:07 PM PST 24
Peak memory 209188 kb
Host smart-85be5726-a0c0-496e-8a70-4a6908a3ef6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192941378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.1192941378
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.1762249294
Short name T448
Test name
Test status
Simulation time 20499498 ps
CPU time 0.78 seconds
Started Feb 29 02:04:19 PM PST 24
Finished Feb 29 02:04:20 PM PST 24
Peak memory 205268 kb
Host smart-16dc26b2-4fb6-4816-8092-9ddb1d2e77a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1762249294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.1762249294
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.4090080846
Short name T678
Test name
Test status
Simulation time 172874186 ps
CPU time 2.9 seconds
Started Feb 29 02:04:16 PM PST 24
Finished Feb 29 02:04:19 PM PST 24
Peak memory 209220 kb
Host smart-413440f7-c8d9-4d31-9199-b7a9fcb2918e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4090080846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.4090080846
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.4234981153
Short name T74
Test name
Test status
Simulation time 37330227 ps
CPU time 1.45 seconds
Started Feb 29 02:04:14 PM PST 24
Finished Feb 29 02:04:16 PM PST 24
Peak memory 207208 kb
Host smart-46b09d70-1ed1-4fab-ba31-fd6de19e6060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4234981153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.4234981153
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.2453722173
Short name T841
Test name
Test status
Simulation time 130509599 ps
CPU time 4.24 seconds
Started Feb 29 02:04:19 PM PST 24
Finished Feb 29 02:04:23 PM PST 24
Peak memory 213660 kb
Host smart-4e315a0f-3290-44f1-8be8-a8e41b4ea58b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453722173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.2453722173
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.2300096605
Short name T197
Test name
Test status
Simulation time 463361563 ps
CPU time 5.5 seconds
Started Feb 29 02:04:17 PM PST 24
Finished Feb 29 02:04:23 PM PST 24
Peak memory 220924 kb
Host smart-a5501831-25e1-41de-891a-d9c4b65085e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300096605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.2300096605
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.289910140
Short name T733
Test name
Test status
Simulation time 75442290 ps
CPU time 3.36 seconds
Started Feb 29 02:04:19 PM PST 24
Finished Feb 29 02:04:22 PM PST 24
Peak memory 213548 kb
Host smart-21238f1a-318b-4c7f-a69e-639aff4ce2eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289910140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.289910140
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.169482982
Short name T559
Test name
Test status
Simulation time 505282965 ps
CPU time 13.07 seconds
Started Feb 29 02:04:15 PM PST 24
Finished Feb 29 02:04:28 PM PST 24
Peak memory 213600 kb
Host smart-8f5da282-e85b-4a13-b6a1-28218b660449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169482982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.169482982
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.29085297
Short name T709
Test name
Test status
Simulation time 357144775 ps
CPU time 9.77 seconds
Started Feb 29 02:04:18 PM PST 24
Finished Feb 29 02:04:28 PM PST 24
Peak memory 207860 kb
Host smart-629abf38-067c-4de9-92d6-cd3c0fdfced1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29085297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.29085297
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.1194359097
Short name T513
Test name
Test status
Simulation time 276977881 ps
CPU time 3.61 seconds
Started Feb 29 02:04:19 PM PST 24
Finished Feb 29 02:04:23 PM PST 24
Peak memory 207768 kb
Host smart-01194393-bac6-45a7-9b5d-e1a0ce9d0831
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194359097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.1194359097
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.1978915156
Short name T770
Test name
Test status
Simulation time 95956188 ps
CPU time 2.07 seconds
Started Feb 29 02:04:20 PM PST 24
Finished Feb 29 02:04:22 PM PST 24
Peak memory 206720 kb
Host smart-fbf68e92-8e3c-48de-a266-55c69e27f860
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978915156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.1978915156
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.3157192592
Short name T499
Test name
Test status
Simulation time 197634778 ps
CPU time 4.65 seconds
Started Feb 29 02:04:16 PM PST 24
Finished Feb 29 02:04:21 PM PST 24
Peak memory 207520 kb
Host smart-7c80b78d-2ad4-46e0-a3ea-2dfde15b85ee
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157192592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.3157192592
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.3128908361
Short name T194
Test name
Test status
Simulation time 55144084 ps
CPU time 2.18 seconds
Started Feb 29 02:04:18 PM PST 24
Finished Feb 29 02:04:21 PM PST 24
Peak memory 208076 kb
Host smart-d1aaa383-a94e-4bc7-b756-5361f9cd1af3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128908361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.3128908361
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.2236239549
Short name T666
Test name
Test status
Simulation time 418669045 ps
CPU time 6.07 seconds
Started Feb 29 02:04:16 PM PST 24
Finished Feb 29 02:04:22 PM PST 24
Peak memory 207092 kb
Host smart-b99d12ad-0e73-4836-9637-209c9a17c81d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236239549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.2236239549
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.1285041644
Short name T192
Test name
Test status
Simulation time 3233068910 ps
CPU time 16.88 seconds
Started Feb 29 02:04:15 PM PST 24
Finished Feb 29 02:04:32 PM PST 24
Peak memory 213784 kb
Host smart-83226565-fd95-4cf9-81fe-5ab968991d5c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285041644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.1285041644
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.2417962183
Short name T578
Test name
Test status
Simulation time 171671035 ps
CPU time 5.31 seconds
Started Feb 29 02:04:17 PM PST 24
Finished Feb 29 02:04:22 PM PST 24
Peak memory 217760 kb
Host smart-02d93c2c-21a9-47f4-af74-c2569c9d4855
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417962183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.2417962183
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.3230511327
Short name T653
Test name
Test status
Simulation time 52011224 ps
CPU time 1.71 seconds
Started Feb 29 02:04:16 PM PST 24
Finished Feb 29 02:04:18 PM PST 24
Peak memory 208976 kb
Host smart-6500796f-5f2b-45c0-ad1f-803b68268a0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230511327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.3230511327
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.2271207351
Short name T453
Test name
Test status
Simulation time 16619252 ps
CPU time 0.92 seconds
Started Feb 29 02:04:15 PM PST 24
Finished Feb 29 02:04:16 PM PST 24
Peak memory 205392 kb
Host smart-1fa6e4c0-7bb2-48a4-94cb-89ae07df5985
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2271207351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.2271207351
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.403204905
Short name T351
Test name
Test status
Simulation time 147468198 ps
CPU time 3.21 seconds
Started Feb 29 02:04:16 PM PST 24
Finished Feb 29 02:04:19 PM PST 24
Peak memory 213668 kb
Host smart-9bf8b563-1578-493c-bbff-4b9b132823e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=403204905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.403204905
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.1335437172
Short name T896
Test name
Test status
Simulation time 278896263 ps
CPU time 3.75 seconds
Started Feb 29 02:04:19 PM PST 24
Finished Feb 29 02:04:23 PM PST 24
Peak memory 209520 kb
Host smart-9789c922-da47-4829-a560-a35e16472d9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335437172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.1335437172
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.3228588236
Short name T73
Test name
Test status
Simulation time 20679267 ps
CPU time 1.45 seconds
Started Feb 29 02:04:17 PM PST 24
Finished Feb 29 02:04:19 PM PST 24
Peak memory 207504 kb
Host smart-910e6cea-be8e-4372-86d1-70bc4a478c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228588236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.3228588236
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.3580976561
Short name T702
Test name
Test status
Simulation time 1270357085 ps
CPU time 5.06 seconds
Started Feb 29 02:04:18 PM PST 24
Finished Feb 29 02:04:24 PM PST 24
Peak memory 208400 kb
Host smart-e093887a-44d8-4112-b3fe-d402fadc7375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580976561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.3580976561
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.824551975
Short name T885
Test name
Test status
Simulation time 405635250 ps
CPU time 4.83 seconds
Started Feb 29 02:04:19 PM PST 24
Finished Feb 29 02:04:24 PM PST 24
Peak memory 210744 kb
Host smart-1de65757-bdf6-478f-b03f-7929aabf576f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824551975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.824551975
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.949287989
Short name T882
Test name
Test status
Simulation time 939337413 ps
CPU time 4.23 seconds
Started Feb 29 02:04:15 PM PST 24
Finished Feb 29 02:04:19 PM PST 24
Peak memory 219540 kb
Host smart-0bb7e985-d679-4de4-9109-c08748acadea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=949287989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.949287989
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.3285237936
Short name T540
Test name
Test status
Simulation time 700225587 ps
CPU time 8.02 seconds
Started Feb 29 02:04:17 PM PST 24
Finished Feb 29 02:04:25 PM PST 24
Peak memory 208052 kb
Host smart-2d635b1c-311a-437b-9614-3d2accd11af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285237936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.3285237936
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.938179728
Short name T620
Test name
Test status
Simulation time 258491855 ps
CPU time 3.37 seconds
Started Feb 29 02:04:16 PM PST 24
Finished Feb 29 02:04:19 PM PST 24
Peak memory 205984 kb
Host smart-8de9da01-f165-4221-be16-85312b0cc3bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=938179728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.938179728
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.3809744755
Short name T780
Test name
Test status
Simulation time 1676394032 ps
CPU time 3.23 seconds
Started Feb 29 02:04:17 PM PST 24
Finished Feb 29 02:04:21 PM PST 24
Peak memory 205996 kb
Host smart-33d26632-c823-4dc8-87a6-635c9b99bf48
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809744755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.3809744755
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.1588556843
Short name T786
Test name
Test status
Simulation time 670658072 ps
CPU time 10.26 seconds
Started Feb 29 02:04:17 PM PST 24
Finished Feb 29 02:04:28 PM PST 24
Peak memory 206356 kb
Host smart-b0391a15-846a-4959-8cb9-6e7575f749c2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588556843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.1588556843
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.4038676475
Short name T740
Test name
Test status
Simulation time 523227117 ps
CPU time 17.99 seconds
Started Feb 29 02:04:17 PM PST 24
Finished Feb 29 02:04:35 PM PST 24
Peak memory 217636 kb
Host smart-76cded7e-b61f-4789-9524-ebe14cdf9587
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038676475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.4038676475
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.242876578
Short name T694
Test name
Test status
Simulation time 162780652 ps
CPU time 2.46 seconds
Started Feb 29 02:04:15 PM PST 24
Finished Feb 29 02:04:17 PM PST 24
Peak memory 206036 kb
Host smart-586a1569-cabf-45b7-b9d2-7e0371b016f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242876578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.242876578
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.2345409787
Short name T335
Test name
Test status
Simulation time 981650112 ps
CPU time 38.84 seconds
Started Feb 29 02:04:20 PM PST 24
Finished Feb 29 02:04:59 PM PST 24
Peak memory 214824 kb
Host smart-2d26c050-9927-45bc-a906-4fd9a6edbcbe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345409787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.2345409787
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.1738303150
Short name T65
Test name
Test status
Simulation time 51063340 ps
CPU time 2.52 seconds
Started Feb 29 02:04:16 PM PST 24
Finished Feb 29 02:04:19 PM PST 24
Peak memory 208784 kb
Host smart-e4534fe8-1d0e-43fd-a80c-4c271b2ee6db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738303150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.1738303150
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.485612179
Short name T534
Test name
Test status
Simulation time 13774989 ps
CPU time 0.76 seconds
Started Feb 29 02:04:20 PM PST 24
Finished Feb 29 02:04:21 PM PST 24
Peak memory 205228 kb
Host smart-5719bce8-d44d-4261-923e-3f6972eca271
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485612179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.485612179
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.4166238082
Short name T32
Test name
Test status
Simulation time 82433017 ps
CPU time 3.16 seconds
Started Feb 29 02:04:19 PM PST 24
Finished Feb 29 02:04:22 PM PST 24
Peak memory 209600 kb
Host smart-48256b7c-26b6-4862-9054-1ea1ba372ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166238082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.4166238082
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.375793191
Short name T567
Test name
Test status
Simulation time 118175375 ps
CPU time 3.14 seconds
Started Feb 29 02:04:16 PM PST 24
Finished Feb 29 02:04:20 PM PST 24
Peak memory 207692 kb
Host smart-684eed1c-c374-4df2-ae51-97d4c752306e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=375793191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.375793191
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.3154682101
Short name T775
Test name
Test status
Simulation time 375697063 ps
CPU time 3.72 seconds
Started Feb 29 02:04:19 PM PST 24
Finished Feb 29 02:04:23 PM PST 24
Peak memory 220960 kb
Host smart-57b33466-e290-4875-864e-7acd3784ef6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154682101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.3154682101
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.1944406856
Short name T296
Test name
Test status
Simulation time 177779040 ps
CPU time 5.58 seconds
Started Feb 29 02:04:19 PM PST 24
Finished Feb 29 02:04:24 PM PST 24
Peak memory 217460 kb
Host smart-11058068-926d-4fe6-859d-180c96bc6a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944406856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.1944406856
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.2475156511
Short name T560
Test name
Test status
Simulation time 3423241127 ps
CPU time 22.52 seconds
Started Feb 29 02:04:21 PM PST 24
Finished Feb 29 02:04:43 PM PST 24
Peak memory 207824 kb
Host smart-ae75b10d-2c94-4990-bb92-fcfb94d021df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2475156511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.2475156511
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.3710343361
Short name T656
Test name
Test status
Simulation time 1415343829 ps
CPU time 14.97 seconds
Started Feb 29 02:04:17 PM PST 24
Finished Feb 29 02:04:32 PM PST 24
Peak memory 208216 kb
Host smart-439699a4-703f-43ba-9064-080225b63bc0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3710343361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.3710343361
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.1688069645
Short name T805
Test name
Test status
Simulation time 68541292 ps
CPU time 2.76 seconds
Started Feb 29 02:04:17 PM PST 24
Finished Feb 29 02:04:20 PM PST 24
Peak memory 206016 kb
Host smart-c7f6a984-07bd-482a-8c44-7e5ab09817db
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688069645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.1688069645
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.4250669183
Short name T217
Test name
Test status
Simulation time 980928252 ps
CPU time 34.62 seconds
Started Feb 29 02:04:21 PM PST 24
Finished Feb 29 02:04:56 PM PST 24
Peak memory 208112 kb
Host smart-677928e2-0c28-43cb-870a-98d00677ae71
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250669183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.4250669183
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.1925844115
Short name T307
Test name
Test status
Simulation time 369531739 ps
CPU time 2.91 seconds
Started Feb 29 02:04:21 PM PST 24
Finished Feb 29 02:04:24 PM PST 24
Peak memory 217540 kb
Host smart-b03747b4-04d6-433e-83be-5713aff253ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925844115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.1925844115
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.67722234
Short name T515
Test name
Test status
Simulation time 66170260 ps
CPU time 2.85 seconds
Started Feb 29 02:04:17 PM PST 24
Finished Feb 29 02:04:20 PM PST 24
Peak memory 207192 kb
Host smart-5aeafdb0-6af8-407b-b28a-e8894c26cd81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=67722234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.67722234
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.76646685
Short name T717
Test name
Test status
Simulation time 3414284034 ps
CPU time 9.66 seconds
Started Feb 29 02:04:17 PM PST 24
Finished Feb 29 02:04:27 PM PST 24
Peak memory 208236 kb
Host smart-18c0b03b-e71f-496c-ba34-56f1844136a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=76646685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.76646685
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.462132077
Short name T67
Test name
Test status
Simulation time 183459447 ps
CPU time 2.68 seconds
Started Feb 29 02:04:22 PM PST 24
Finished Feb 29 02:04:24 PM PST 24
Peak memory 208284 kb
Host smart-079a3866-7aad-472c-95ee-4253dd148ef7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462132077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.462132077
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.2350825759
Short name T873
Test name
Test status
Simulation time 25973044 ps
CPU time 0.8 seconds
Started Feb 29 02:04:20 PM PST 24
Finished Feb 29 02:04:21 PM PST 24
Peak memory 205372 kb
Host smart-5cf07dcc-04c3-4ad5-aaca-e3247da42fdf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350825759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.2350825759
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.972996855
Short name T35
Test name
Test status
Simulation time 218555271 ps
CPU time 4.58 seconds
Started Feb 29 02:04:21 PM PST 24
Finished Feb 29 02:04:25 PM PST 24
Peak memory 215352 kb
Host smart-97d12d15-ed04-4de6-b1aa-9067ae4a46ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972996855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.972996855
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.2939008355
Short name T671
Test name
Test status
Simulation time 33797064 ps
CPU time 2 seconds
Started Feb 29 02:04:22 PM PST 24
Finished Feb 29 02:04:24 PM PST 24
Peak memory 208540 kb
Host smart-9703a5d0-b681-4835-a754-48bf001318f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939008355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.2939008355
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.2976686310
Short name T386
Test name
Test status
Simulation time 274371093 ps
CPU time 4.54 seconds
Started Feb 29 02:04:18 PM PST 24
Finished Feb 29 02:04:22 PM PST 24
Peak memory 210736 kb
Host smart-d25ff2e0-d7d6-44d7-bdcd-c5f3487a8591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976686310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.2976686310
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.1978268045
Short name T852
Test name
Test status
Simulation time 784824032 ps
CPU time 5.98 seconds
Started Feb 29 02:04:26 PM PST 24
Finished Feb 29 02:04:32 PM PST 24
Peak memory 221856 kb
Host smart-31c9a243-ad1a-4e68-8f7b-95939c4d503e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978268045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.1978268045
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.463862456
Short name T672
Test name
Test status
Simulation time 244104679 ps
CPU time 8.37 seconds
Started Feb 29 02:04:22 PM PST 24
Finished Feb 29 02:04:30 PM PST 24
Peak memory 208236 kb
Host smart-e7a4da13-509f-437d-80c6-7df4dc219459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=463862456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.463862456
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.1905003029
Short name T223
Test name
Test status
Simulation time 81384298 ps
CPU time 3.24 seconds
Started Feb 29 02:04:21 PM PST 24
Finished Feb 29 02:04:24 PM PST 24
Peak memory 207684 kb
Host smart-f8a180bc-3caf-4cd3-88ff-c03706a06052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1905003029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.1905003029
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.561681676
Short name T602
Test name
Test status
Simulation time 67736079 ps
CPU time 3.44 seconds
Started Feb 29 02:04:22 PM PST 24
Finished Feb 29 02:04:25 PM PST 24
Peak memory 208268 kb
Host smart-cde3fee2-45e1-4f8c-8a56-e88cd2349573
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=561681676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.561681676
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.3123883910
Short name T480
Test name
Test status
Simulation time 193376482 ps
CPU time 7.58 seconds
Started Feb 29 02:04:21 PM PST 24
Finished Feb 29 02:04:28 PM PST 24
Peak memory 207288 kb
Host smart-3267685b-be71-439e-a4f6-cc90c531dfe7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123883910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.3123883910
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.2407975976
Short name T190
Test name
Test status
Simulation time 254741747 ps
CPU time 5.89 seconds
Started Feb 29 02:04:20 PM PST 24
Finished Feb 29 02:04:26 PM PST 24
Peak memory 207764 kb
Host smart-09cf3d46-9042-4600-8f45-e72f1504937a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407975976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.2407975976
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.4211511650
Short name T469
Test name
Test status
Simulation time 499956267 ps
CPU time 6.85 seconds
Started Feb 29 02:04:22 PM PST 24
Finished Feb 29 02:04:29 PM PST 24
Peak memory 207248 kb
Host smart-2d9f0dc6-ddc1-4b74-ad02-6d431d46ddb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211511650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.4211511650
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.2500343602
Short name T541
Test name
Test status
Simulation time 80387889 ps
CPU time 1.98 seconds
Started Feb 29 02:04:21 PM PST 24
Finished Feb 29 02:04:24 PM PST 24
Peak memory 207632 kb
Host smart-fb02d23f-ac38-4328-b4ce-7c85ff294bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2500343602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.2500343602
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.1044685817
Short name T312
Test name
Test status
Simulation time 190573984 ps
CPU time 5.23 seconds
Started Feb 29 02:04:21 PM PST 24
Finished Feb 29 02:04:26 PM PST 24
Peak memory 218012 kb
Host smart-8ab91cf4-e30f-413b-97c5-b07dcdece7fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044685817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.1044685817
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.182010534
Short name T867
Test name
Test status
Simulation time 450442026 ps
CPU time 9.13 seconds
Started Feb 29 02:04:18 PM PST 24
Finished Feb 29 02:04:27 PM PST 24
Peak memory 217468 kb
Host smart-5487f756-a317-4dda-ad63-1e10a53e24ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182010534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.182010534
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.3969477988
Short name T188
Test name
Test status
Simulation time 1173107269 ps
CPU time 5.6 seconds
Started Feb 29 02:04:23 PM PST 24
Finished Feb 29 02:04:29 PM PST 24
Peak memory 210148 kb
Host smart-7701516c-a077-44f4-a4cb-074b6c916320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969477988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.3969477988
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.1418928494
Short name T481
Test name
Test status
Simulation time 40057829 ps
CPU time 0.74 seconds
Started Feb 29 02:04:18 PM PST 24
Finished Feb 29 02:04:19 PM PST 24
Peak memory 205344 kb
Host smart-250074ee-9d60-47c7-aa30-0f326b0391f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418928494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.1418928494
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.581677132
Short name T767
Test name
Test status
Simulation time 43323224 ps
CPU time 2.22 seconds
Started Feb 29 02:04:31 PM PST 24
Finished Feb 29 02:04:33 PM PST 24
Peak memory 208632 kb
Host smart-4e4d49c0-8aa6-404b-91fa-5ef3243c38f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581677132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.581677132
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.1360500416
Short name T321
Test name
Test status
Simulation time 98946968 ps
CPU time 2.88 seconds
Started Feb 29 02:04:31 PM PST 24
Finished Feb 29 02:04:34 PM PST 24
Peak memory 208596 kb
Host smart-bdc64bd0-83a8-4300-8c7b-a1358ee5d183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360500416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.1360500416
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.366675152
Short name T25
Test name
Test status
Simulation time 104123924 ps
CPU time 4.26 seconds
Started Feb 29 02:04:20 PM PST 24
Finished Feb 29 02:04:25 PM PST 24
Peak memory 213660 kb
Host smart-d74c2c51-f991-4569-8dde-5afef3657e3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366675152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.366675152
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.2781003308
Short name T91
Test name
Test status
Simulation time 400678174 ps
CPU time 3.99 seconds
Started Feb 29 02:04:27 PM PST 24
Finished Feb 29 02:04:31 PM PST 24
Peak memory 210012 kb
Host smart-3517b543-e770-4104-bc42-46abb052d469
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781003308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.2781003308
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.134137452
Short name T258
Test name
Test status
Simulation time 305180167 ps
CPU time 4.27 seconds
Started Feb 29 02:04:27 PM PST 24
Finished Feb 29 02:04:31 PM PST 24
Peak memory 207864 kb
Host smart-c59647ba-6818-432f-8165-bac04f8ed130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134137452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.134137452
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.882985256
Short name T204
Test name
Test status
Simulation time 820645096 ps
CPU time 4.19 seconds
Started Feb 29 02:04:31 PM PST 24
Finished Feb 29 02:04:35 PM PST 24
Peak memory 217744 kb
Host smart-e8bb0308-22d0-4606-9f74-7a36ae0eb3c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882985256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.882985256
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.2815839630
Short name T368
Test name
Test status
Simulation time 181161675 ps
CPU time 4.6 seconds
Started Feb 29 02:04:19 PM PST 24
Finished Feb 29 02:04:24 PM PST 24
Peak memory 207668 kb
Host smart-87de91a3-1595-41e4-b4f4-cac30bc16bd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815839630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.2815839630
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.787676355
Short name T583
Test name
Test status
Simulation time 76657281 ps
CPU time 1.7 seconds
Started Feb 29 02:04:24 PM PST 24
Finished Feb 29 02:04:26 PM PST 24
Peak memory 205988 kb
Host smart-9e096ee9-463c-4a6f-93af-f21829944803
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787676355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.787676355
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.2025265247
Short name T555
Test name
Test status
Simulation time 50070794 ps
CPU time 2.79 seconds
Started Feb 29 02:04:23 PM PST 24
Finished Feb 29 02:04:26 PM PST 24
Peak memory 206032 kb
Host smart-ee15799b-7773-4b1c-ab77-c891154ea724
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025265247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.2025265247
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.3100338128
Short name T483
Test name
Test status
Simulation time 642173099 ps
CPU time 17.7 seconds
Started Feb 29 02:04:23 PM PST 24
Finished Feb 29 02:04:41 PM PST 24
Peak memory 207920 kb
Host smart-bfadc19a-248e-4166-be75-823f2be96436
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100338128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.3100338128
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.234285773
Short name T600
Test name
Test status
Simulation time 82225176 ps
CPU time 3.2 seconds
Started Feb 29 02:04:25 PM PST 24
Finished Feb 29 02:04:28 PM PST 24
Peak memory 206892 kb
Host smart-a3e6b5f4-7cbb-44f7-bf5a-d82bb0fb7cf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=234285773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.234285773
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.2110305332
Short name T839
Test name
Test status
Simulation time 60004578 ps
CPU time 2.32 seconds
Started Feb 29 02:04:21 PM PST 24
Finished Feb 29 02:04:23 PM PST 24
Peak memory 205892 kb
Host smart-20c89b2d-bd51-4918-82c2-34ad7487de8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2110305332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.2110305332
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.2560796125
Short name T178
Test name
Test status
Simulation time 341533392 ps
CPU time 12.93 seconds
Started Feb 29 02:04:20 PM PST 24
Finished Feb 29 02:04:33 PM PST 24
Peak memory 221964 kb
Host smart-84eeaad7-4e0d-4030-8406-77c231f9e864
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560796125 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.2560796125
Directory /workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.2798556224
Short name T317
Test name
Test status
Simulation time 1104684987 ps
CPU time 28.37 seconds
Started Feb 29 02:04:31 PM PST 24
Finished Feb 29 02:04:59 PM PST 24
Peak memory 217484 kb
Host smart-e38bb10c-66a8-4926-93f5-bb7fd73b5964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798556224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.2798556224
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.3498556754
Short name T169
Test name
Test status
Simulation time 212180335 ps
CPU time 2.49 seconds
Started Feb 29 02:04:31 PM PST 24
Finished Feb 29 02:04:33 PM PST 24
Peak memory 209244 kb
Host smart-2090bc72-cb2d-400c-ba33-4ef81f31058b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498556754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.3498556754
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.3217273451
Short name T99
Test name
Test status
Simulation time 69993541 ps
CPU time 0.84 seconds
Started Feb 29 02:04:35 PM PST 24
Finished Feb 29 02:04:39 PM PST 24
Peak memory 205216 kb
Host smart-8b063ab4-5dd9-4a54-859d-42bb2a72cff8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217273451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.3217273451
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.3868314491
Short name T443
Test name
Test status
Simulation time 74691138 ps
CPU time 3.2 seconds
Started Feb 29 02:04:18 PM PST 24
Finished Feb 29 02:04:22 PM PST 24
Peak memory 214008 kb
Host smart-49420d81-2730-47a0-8926-a3c8d627b7c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3868314491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.3868314491
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.3330846525
Short name T48
Test name
Test status
Simulation time 1111471517 ps
CPU time 3.34 seconds
Started Feb 29 02:04:21 PM PST 24
Finished Feb 29 02:04:24 PM PST 24
Peak memory 217652 kb
Host smart-4f6aba88-f2f8-496e-8742-27da7433eaa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330846525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.3330846525
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.666733918
Short name T308
Test name
Test status
Simulation time 148760328 ps
CPU time 5.38 seconds
Started Feb 29 02:04:29 PM PST 24
Finished Feb 29 02:04:34 PM PST 24
Peak memory 207796 kb
Host smart-661ef811-e81a-478b-8b0a-806c044b96df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=666733918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.666733918
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.1385852295
Short name T375
Test name
Test status
Simulation time 7722304297 ps
CPU time 87.37 seconds
Started Feb 29 02:04:34 PM PST 24
Finished Feb 29 02:06:01 PM PST 24
Peak memory 215860 kb
Host smart-e890d11f-26df-4013-a877-fe8cab30935e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385852295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.1385852295
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.2371895094
Short name T843
Test name
Test status
Simulation time 75799060 ps
CPU time 3.04 seconds
Started Feb 29 02:04:30 PM PST 24
Finished Feb 29 02:04:33 PM PST 24
Peak memory 214080 kb
Host smart-5c4e581a-ab59-4036-8c6c-4b6b0617f3b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371895094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.2371895094
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.3587696142
Short name T584
Test name
Test status
Simulation time 129774123 ps
CPU time 2.27 seconds
Started Feb 29 02:04:21 PM PST 24
Finished Feb 29 02:04:23 PM PST 24
Peak memory 206784 kb
Host smart-2766451d-f534-47f4-bfe3-3624003edf46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3587696142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.3587696142
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.1959985982
Short name T760
Test name
Test status
Simulation time 171039730 ps
CPU time 4.58 seconds
Started Feb 29 02:04:20 PM PST 24
Finished Feb 29 02:04:25 PM PST 24
Peak memory 207864 kb
Host smart-35af6cf0-09ad-4692-b5d8-1f8ba032e386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959985982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.1959985982
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.2022794181
Short name T285
Test name
Test status
Simulation time 123428550 ps
CPU time 5.35 seconds
Started Feb 29 02:04:18 PM PST 24
Finished Feb 29 02:04:24 PM PST 24
Peak memory 207792 kb
Host smart-60b985d4-9e5c-4fed-8e57-a1c407cf941e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022794181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.2022794181
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.788566839
Short name T736
Test name
Test status
Simulation time 478501800 ps
CPU time 3.97 seconds
Started Feb 29 02:04:20 PM PST 24
Finished Feb 29 02:04:24 PM PST 24
Peak memory 207820 kb
Host smart-754c4507-59ca-41dc-b880-e0e0720e443a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=788566839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.788566839
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.697402994
Short name T399
Test name
Test status
Simulation time 20042566 ps
CPU time 1.83 seconds
Started Feb 29 02:04:20 PM PST 24
Finished Feb 29 02:04:22 PM PST 24
Peak memory 206540 kb
Host smart-c517787a-8b27-490b-ab5d-e4f63c784d35
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697402994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.697402994
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.2327006318
Short name T500
Test name
Test status
Simulation time 113081058 ps
CPU time 3.23 seconds
Started Feb 29 02:04:30 PM PST 24
Finished Feb 29 02:04:33 PM PST 24
Peak memory 208348 kb
Host smart-657559b0-2b0a-4fab-bfaa-fb8e0d907d65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327006318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.2327006318
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.2768948816
Short name T454
Test name
Test status
Simulation time 52925814 ps
CPU time 2.37 seconds
Started Feb 29 02:04:18 PM PST 24
Finished Feb 29 02:04:21 PM PST 24
Peak memory 207340 kb
Host smart-7edf0929-87e3-48d7-9205-ea21e132bb74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2768948816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.2768948816
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.2124718366
Short name T397
Test name
Test status
Simulation time 377149366 ps
CPU time 15.13 seconds
Started Feb 29 02:04:43 PM PST 24
Finished Feb 29 02:04:59 PM PST 24
Peak memory 219700 kb
Host smart-55640590-0230-4fb2-810d-0b94195d3e73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124718366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.2124718366
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_stress_all_with_rand_reset.1504595022
Short name T180
Test name
Test status
Simulation time 2014491515 ps
CPU time 20.05 seconds
Started Feb 29 02:04:37 PM PST 24
Finished Feb 29 02:04:59 PM PST 24
Peak memory 220060 kb
Host smart-d5c1d1f7-da91-4f88-8984-21afa992cdcc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1504595022 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all_with_rand_reset.1504595022
Directory /workspace/36.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.3971765539
Short name T631
Test name
Test status
Simulation time 115242212 ps
CPU time 4.11 seconds
Started Feb 29 02:04:34 PM PST 24
Finished Feb 29 02:04:39 PM PST 24
Peak memory 213608 kb
Host smart-c2bf1877-f223-4862-a6a7-314bdff70768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971765539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.3971765539
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.1323934877
Short name T156
Test name
Test status
Simulation time 626648342 ps
CPU time 7.84 seconds
Started Feb 29 02:04:34 PM PST 24
Finished Feb 29 02:04:43 PM PST 24
Peak memory 210336 kb
Host smart-88c765d7-43ed-4835-a37f-0e5e53073c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323934877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.1323934877
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.1834987966
Short name T474
Test name
Test status
Simulation time 12463764 ps
CPU time 0.9 seconds
Started Feb 29 02:04:31 PM PST 24
Finished Feb 29 02:04:32 PM PST 24
Peak memory 205352 kb
Host smart-eb27958b-ff44-40c0-9dd8-c251a74137b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1834987966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.1834987966
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.2298809302
Short name T682
Test name
Test status
Simulation time 38251967 ps
CPU time 2.15 seconds
Started Feb 29 02:04:28 PM PST 24
Finished Feb 29 02:04:31 PM PST 24
Peak memory 213644 kb
Host smart-05afe853-9eb7-4a4f-8511-87112c738a01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298809302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.2298809302
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.1680903997
Short name T820
Test name
Test status
Simulation time 93690116 ps
CPU time 2.4 seconds
Started Feb 29 02:04:28 PM PST 24
Finished Feb 29 02:04:31 PM PST 24
Peak memory 217680 kb
Host smart-c2f9d296-d840-4f51-b3a8-091b4dc867c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680903997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.1680903997
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.58002576
Short name T507
Test name
Test status
Simulation time 519113560 ps
CPU time 7.15 seconds
Started Feb 29 02:04:28 PM PST 24
Finished Feb 29 02:04:35 PM PST 24
Peak memory 207436 kb
Host smart-6c8d6045-c0a7-4897-b625-e49524a8026b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58002576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.58002576
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.1482007317
Short name T102
Test name
Test status
Simulation time 733341761 ps
CPU time 4.08 seconds
Started Feb 29 02:04:35 PM PST 24
Finished Feb 29 02:04:40 PM PST 24
Peak memory 210876 kb
Host smart-ac5741c2-b23c-435a-ba1b-1b62bab6f193
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482007317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.1482007317
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.2740696997
Short name T818
Test name
Test status
Simulation time 100515807 ps
CPU time 4.23 seconds
Started Feb 29 02:04:31 PM PST 24
Finished Feb 29 02:04:35 PM PST 24
Peak memory 219620 kb
Host smart-462ce91b-f1a6-4bcc-a8c7-9f234517b200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2740696997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.2740696997
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.3048813729
Short name T784
Test name
Test status
Simulation time 106053099 ps
CPU time 4.45 seconds
Started Feb 29 02:04:32 PM PST 24
Finished Feb 29 02:04:37 PM PST 24
Peak memory 208444 kb
Host smart-e65cafea-a7cf-489c-84a7-47c2528d3fdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048813729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.3048813729
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.2440652501
Short name T490
Test name
Test status
Simulation time 54397022 ps
CPU time 2.65 seconds
Started Feb 29 02:04:37 PM PST 24
Finished Feb 29 02:04:42 PM PST 24
Peak memory 207288 kb
Host smart-c612bfed-65ee-4f02-92e7-7abb95f04afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440652501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.2440652501
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.397014303
Short name T856
Test name
Test status
Simulation time 230578299 ps
CPU time 3.31 seconds
Started Feb 29 02:04:30 PM PST 24
Finished Feb 29 02:04:34 PM PST 24
Peak memory 206032 kb
Host smart-86c8b65d-05f5-45bd-8dc1-4605b421c722
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=397014303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.397014303
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.252642894
Short name T773
Test name
Test status
Simulation time 156690254 ps
CPU time 6.25 seconds
Started Feb 29 02:04:30 PM PST 24
Finished Feb 29 02:04:36 PM PST 24
Peak memory 207668 kb
Host smart-6aaf16f0-ba18-4237-9ea9-57d4fbb6cd5e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=252642894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.252642894
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.1946254537
Short name T557
Test name
Test status
Simulation time 48954989 ps
CPU time 2.76 seconds
Started Feb 29 02:04:30 PM PST 24
Finished Feb 29 02:04:33 PM PST 24
Peak memory 206012 kb
Host smart-55b914df-d43f-4a20-bb40-ecd4fce163db
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1946254537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.1946254537
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.2789006154
Short name T763
Test name
Test status
Simulation time 92753288 ps
CPU time 3.18 seconds
Started Feb 29 02:04:29 PM PST 24
Finished Feb 29 02:04:32 PM PST 24
Peak memory 214916 kb
Host smart-8f216197-6b64-499e-bcba-8a7ac8c59efb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2789006154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.2789006154
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.2226795964
Short name T422
Test name
Test status
Simulation time 375191968 ps
CPU time 5.37 seconds
Started Feb 29 02:04:37 PM PST 24
Finished Feb 29 02:04:44 PM PST 24
Peak memory 207080 kb
Host smart-053b9ade-16c0-4eaa-b636-7f9a6f6442d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226795964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.2226795964
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.3795870058
Short name T319
Test name
Test status
Simulation time 54455925 ps
CPU time 3.76 seconds
Started Feb 29 02:04:30 PM PST 24
Finished Feb 29 02:04:34 PM PST 24
Peak memory 206608 kb
Host smart-62879a57-9592-4d41-811e-af3fc3085b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795870058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.3795870058
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.1789566907
Short name T688
Test name
Test status
Simulation time 98232173 ps
CPU time 3.97 seconds
Started Feb 29 02:04:27 PM PST 24
Finished Feb 29 02:04:31 PM PST 24
Peak memory 209772 kb
Host smart-44bc1b18-6870-4777-b3c7-733a54e5ece8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1789566907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.1789566907
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.520632041
Short name T502
Test name
Test status
Simulation time 111461965 ps
CPU time 1.1 seconds
Started Feb 29 02:04:41 PM PST 24
Finished Feb 29 02:04:42 PM PST 24
Peak memory 205344 kb
Host smart-9147917e-7911-4e13-aa19-16027b1d60ed
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=520632041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.520632041
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.3624848227
Short name T431
Test name
Test status
Simulation time 279720563 ps
CPU time 15.7 seconds
Started Feb 29 02:04:36 PM PST 24
Finished Feb 29 02:04:54 PM PST 24
Peak memory 214404 kb
Host smart-21d93ee1-d172-4687-89da-8018881382cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3624848227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.3624848227
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.3257248810
Short name T10
Test name
Test status
Simulation time 461023569 ps
CPU time 4.68 seconds
Started Feb 29 02:04:32 PM PST 24
Finished Feb 29 02:04:37 PM PST 24
Peak memory 207864 kb
Host smart-c56da418-ac46-40ff-a29e-0de79a78d316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257248810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.3257248810
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.3859674539
Short name T825
Test name
Test status
Simulation time 94944371 ps
CPU time 2.67 seconds
Started Feb 29 02:04:29 PM PST 24
Finished Feb 29 02:04:32 PM PST 24
Peak memory 217536 kb
Host smart-1f165823-aa46-42f6-8039-351e491490b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859674539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.3859674539
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.1845696724
Short name T406
Test name
Test status
Simulation time 255142164 ps
CPU time 3.43 seconds
Started Feb 29 02:04:34 PM PST 24
Finished Feb 29 02:04:39 PM PST 24
Peak memory 213648 kb
Host smart-eaaafc52-b7de-4a78-a912-108581a694bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845696724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.1845696724
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.695751298
Short name T244
Test name
Test status
Simulation time 83458907 ps
CPU time 2.53 seconds
Started Feb 29 02:04:37 PM PST 24
Finished Feb 29 02:04:41 PM PST 24
Peak memory 214700 kb
Host smart-21b7914a-661e-43bd-bc22-f6dec0c67d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695751298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.695751298
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.831236112
Short name T371
Test name
Test status
Simulation time 278159185 ps
CPU time 8.13 seconds
Started Feb 29 02:04:34 PM PST 24
Finished Feb 29 02:04:43 PM PST 24
Peak memory 208872 kb
Host smart-383669df-eb37-4326-b850-b4a3ba6fef3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831236112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.831236112
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.3737400598
Short name T536
Test name
Test status
Simulation time 1054248718 ps
CPU time 34.65 seconds
Started Feb 29 02:04:37 PM PST 24
Finished Feb 29 02:05:14 PM PST 24
Peak memory 207580 kb
Host smart-1f784ea8-e1fa-48a2-ae78-809d2a04dd02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737400598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.3737400598
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.655067495
Short name T561
Test name
Test status
Simulation time 144295500 ps
CPU time 2.83 seconds
Started Feb 29 02:04:29 PM PST 24
Finished Feb 29 02:04:32 PM PST 24
Peak memory 205912 kb
Host smart-de4c2cf7-d87e-4d56-acf1-20bb6d41b126
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=655067495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.655067495
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.1462280674
Short name T510
Test name
Test status
Simulation time 60673366 ps
CPU time 3.21 seconds
Started Feb 29 02:04:31 PM PST 24
Finished Feb 29 02:04:34 PM PST 24
Peak memory 207624 kb
Host smart-cafccbfc-b8db-4671-8cc4-d21d6b0e190d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462280674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.1462280674
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.1323169329
Short name T493
Test name
Test status
Simulation time 411801396 ps
CPU time 12.12 seconds
Started Feb 29 02:04:37 PM PST 24
Finished Feb 29 02:04:51 PM PST 24
Peak memory 207708 kb
Host smart-e40acee2-3dac-485a-8c81-96b5e0844bb0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323169329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.1323169329
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.4017650157
Short name T383
Test name
Test status
Simulation time 849101602 ps
CPU time 22.4 seconds
Started Feb 29 02:04:34 PM PST 24
Finished Feb 29 02:04:58 PM PST 24
Peak memory 207956 kb
Host smart-794b474e-50bb-45ea-85a5-98c5ef149d3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017650157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.4017650157
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.1119646931
Short name T695
Test name
Test status
Simulation time 365366393 ps
CPU time 4.46 seconds
Started Feb 29 02:04:32 PM PST 24
Finished Feb 29 02:04:37 PM PST 24
Peak memory 206536 kb
Host smart-576cc920-a8e1-429a-bd9e-18ed4240515b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119646931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.1119646931
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.3931189394
Short name T382
Test name
Test status
Simulation time 1628243187 ps
CPU time 35.34 seconds
Started Feb 29 02:04:34 PM PST 24
Finished Feb 29 02:05:11 PM PST 24
Peak memory 215712 kb
Host smart-b7def793-f794-432f-8d99-45abd0f89681
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931189394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.3931189394
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.2646302151
Short name T739
Test name
Test status
Simulation time 192804864 ps
CPU time 7.23 seconds
Started Feb 29 02:04:29 PM PST 24
Finished Feb 29 02:04:36 PM PST 24
Peak memory 207844 kb
Host smart-b4e61443-1714-4489-9390-f214b3609c2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646302151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.2646302151
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.1830984618
Short name T161
Test name
Test status
Simulation time 210129268 ps
CPU time 2.75 seconds
Started Feb 29 02:04:28 PM PST 24
Finished Feb 29 02:04:31 PM PST 24
Peak memory 209668 kb
Host smart-9c01e3cb-f12c-46cd-91fe-8834988d8274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830984618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.1830984618
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.2152668937
Short name T511
Test name
Test status
Simulation time 17995842 ps
CPU time 0.84 seconds
Started Feb 29 02:04:43 PM PST 24
Finished Feb 29 02:04:44 PM PST 24
Peak memory 205272 kb
Host smart-fc3b4439-f696-4687-9576-0e69821d3316
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152668937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.2152668937
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.1971035289
Short name T345
Test name
Test status
Simulation time 612375293 ps
CPU time 6.43 seconds
Started Feb 29 02:04:42 PM PST 24
Finished Feb 29 02:04:49 PM PST 24
Peak memory 213688 kb
Host smart-e52cd88b-9445-4283-b9fa-0bc3c2f7cfb6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1971035289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.1971035289
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.2498331692
Short name T268
Test name
Test status
Simulation time 329555046 ps
CPU time 3.63 seconds
Started Feb 29 02:04:42 PM PST 24
Finished Feb 29 02:04:46 PM PST 24
Peak memory 216880 kb
Host smart-c7b4a033-31be-471c-a7d5-88c2fbac2a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2498331692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.2498331692
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.288255525
Short name T478
Test name
Test status
Simulation time 827294360 ps
CPU time 7.95 seconds
Started Feb 29 02:04:41 PM PST 24
Finished Feb 29 02:04:49 PM PST 24
Peak memory 207928 kb
Host smart-f9f63aea-b16f-4c93-a6d5-4d2f2117e6c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288255525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.288255525
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.3641070849
Short name T761
Test name
Test status
Simulation time 306328936 ps
CPU time 6.2 seconds
Started Feb 29 02:04:44 PM PST 24
Finished Feb 29 02:04:51 PM PST 24
Peak memory 208248 kb
Host smart-6e36474b-3372-4e12-8ba4-d0704539edaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641070849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.3641070849
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.1102758872
Short name T797
Test name
Test status
Simulation time 107769499 ps
CPU time 3.92 seconds
Started Feb 29 02:04:43 PM PST 24
Finished Feb 29 02:04:47 PM PST 24
Peak memory 208288 kb
Host smart-9fe5a10d-8b61-4581-a6ab-2ce551da197f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1102758872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.1102758872
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.4125328010
Short name T482
Test name
Test status
Simulation time 3838633789 ps
CPU time 13.74 seconds
Started Feb 29 02:04:42 PM PST 24
Finished Feb 29 02:04:56 PM PST 24
Peak memory 207868 kb
Host smart-b39850b9-be2d-48f9-b659-5c3d81fa0eb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4125328010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.4125328010
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.3365916583
Short name T465
Test name
Test status
Simulation time 134309289 ps
CPU time 4.81 seconds
Started Feb 29 02:04:43 PM PST 24
Finished Feb 29 02:04:48 PM PST 24
Peak memory 207196 kb
Host smart-b7d12fc6-77ea-4ef9-bd17-30694941bc22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365916583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.3365916583
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.600440082
Short name T663
Test name
Test status
Simulation time 175545254 ps
CPU time 6.81 seconds
Started Feb 29 02:04:49 PM PST 24
Finished Feb 29 02:04:56 PM PST 24
Peak memory 207780 kb
Host smart-3182c785-2a4a-41ca-9b39-3a7c890da2f6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600440082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.600440082
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.224566260
Short name T232
Test name
Test status
Simulation time 1557080462 ps
CPU time 24.6 seconds
Started Feb 29 02:04:43 PM PST 24
Finished Feb 29 02:05:08 PM PST 24
Peak memory 207900 kb
Host smart-181568f3-a676-49cc-86a6-9583ebfba3bc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224566260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.224566260
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.115416465
Short name T706
Test name
Test status
Simulation time 99708276 ps
CPU time 2.09 seconds
Started Feb 29 02:04:41 PM PST 24
Finished Feb 29 02:04:44 PM PST 24
Peak memory 207688 kb
Host smart-113537f2-e53e-4bb4-b2dd-4a91318727e9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115416465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.115416465
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.879966691
Short name T287
Test name
Test status
Simulation time 1251404123 ps
CPU time 18 seconds
Started Feb 29 02:04:42 PM PST 24
Finished Feb 29 02:05:00 PM PST 24
Peak memory 207164 kb
Host smart-8588bef7-9779-400d-8498-1d6f601f296c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879966691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.879966691
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.3582932823
Short name T451
Test name
Test status
Simulation time 134893732 ps
CPU time 2.64 seconds
Started Feb 29 02:04:44 PM PST 24
Finished Feb 29 02:04:48 PM PST 24
Peak memory 208000 kb
Host smart-4311e52d-376f-41e4-bb30-1907cdf266c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582932823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.3582932823
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.4092904611
Short name T298
Test name
Test status
Simulation time 198239333 ps
CPU time 2.58 seconds
Started Feb 29 02:04:41 PM PST 24
Finished Feb 29 02:04:44 PM PST 24
Peak memory 206064 kb
Host smart-7cc80165-42ee-469a-913a-a73e94a5b6dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092904611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.4092904611
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.3286981745
Short name T667
Test name
Test status
Simulation time 93965593 ps
CPU time 1.54 seconds
Started Feb 29 02:04:42 PM PST 24
Finished Feb 29 02:04:43 PM PST 24
Peak memory 208756 kb
Host smart-65b8abbf-c80f-4baf-ab87-985af4733c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286981745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.3286981745
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.2237137348
Short name T452
Test name
Test status
Simulation time 50748905 ps
CPU time 0.88 seconds
Started Feb 29 02:01:22 PM PST 24
Finished Feb 29 02:01:23 PM PST 24
Peak memory 205332 kb
Host smart-bfb0352d-8546-4b7e-9131-f183023780b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2237137348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.2237137348
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.1382527321
Short name T141
Test name
Test status
Simulation time 228190809 ps
CPU time 4.34 seconds
Started Feb 29 02:01:24 PM PST 24
Finished Feb 29 02:01:29 PM PST 24
Peak memory 214176 kb
Host smart-0f984d7a-e0e4-436e-af48-3af5ad2239e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1382527321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.1382527321
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.379304737
Short name T732
Test name
Test status
Simulation time 60375361 ps
CPU time 2.04 seconds
Started Feb 29 02:01:23 PM PST 24
Finished Feb 29 02:01:25 PM PST 24
Peak memory 209056 kb
Host smart-ff8df53e-d635-49dd-9a03-352471fa61d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379304737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.379304737
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.4168372158
Short name T628
Test name
Test status
Simulation time 73202561 ps
CPU time 2.47 seconds
Started Feb 29 02:01:25 PM PST 24
Finished Feb 29 02:01:27 PM PST 24
Peak memory 206664 kb
Host smart-7fdf2233-3590-43c5-aac5-071729803e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4168372158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.4168372158
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.482770369
Short name T662
Test name
Test status
Simulation time 1711731667 ps
CPU time 5.9 seconds
Started Feb 29 02:01:26 PM PST 24
Finished Feb 29 02:01:32 PM PST 24
Peak memory 208696 kb
Host smart-3fb5e9f3-70cd-4961-8a4b-a55e1bba1495
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=482770369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.482770369
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.2189224646
Short name T278
Test name
Test status
Simulation time 1265876161 ps
CPU time 18.57 seconds
Started Feb 29 02:01:26 PM PST 24
Finished Feb 29 02:01:44 PM PST 24
Peak memory 221788 kb
Host smart-36e56d8f-6cb1-4086-9503-ffabe8f06a43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189224646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.2189224646
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_random.3214616097
Short name T365
Test name
Test status
Simulation time 1033454869 ps
CPU time 5.28 seconds
Started Feb 29 02:01:22 PM PST 24
Finished Feb 29 02:01:27 PM PST 24
Peak memory 206872 kb
Host smart-74c64914-bea6-4c80-9dbb-d84a5d822243
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214616097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.3214616097
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sideload.3668889351
Short name T203
Test name
Test status
Simulation time 202972722 ps
CPU time 2.77 seconds
Started Feb 29 02:01:23 PM PST 24
Finished Feb 29 02:01:26 PM PST 24
Peak memory 207024 kb
Host smart-1f894cec-3984-4afd-a16a-e666cb5ebccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668889351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.3668889351
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.3369138260
Short name T859
Test name
Test status
Simulation time 192227326 ps
CPU time 5.24 seconds
Started Feb 29 02:01:20 PM PST 24
Finished Feb 29 02:01:26 PM PST 24
Peak memory 207092 kb
Host smart-f361cae6-92a4-4fa9-81e5-8304ed76fde7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369138260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.3369138260
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.2875399190
Short name T692
Test name
Test status
Simulation time 218461210 ps
CPU time 2.95 seconds
Started Feb 29 02:01:23 PM PST 24
Finished Feb 29 02:01:26 PM PST 24
Peak memory 207800 kb
Host smart-ea9a5d40-69d4-4de9-a07a-cf34c712dbcc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875399190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.2875399190
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.1448022780
Short name T563
Test name
Test status
Simulation time 13155393919 ps
CPU time 40.58 seconds
Started Feb 29 02:01:22 PM PST 24
Finished Feb 29 02:02:03 PM PST 24
Peak memory 208096 kb
Host smart-74236926-10c9-4406-9f51-0fb4a0f93bea
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1448022780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.1448022780
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.1935894867
Short name T440
Test name
Test status
Simulation time 92034028 ps
CPU time 2.59 seconds
Started Feb 29 02:01:23 PM PST 24
Finished Feb 29 02:01:25 PM PST 24
Peak memory 213648 kb
Host smart-79cee9b0-bfa0-4972-8814-c151c54ac7a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935894867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.1935894867
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.2277195270
Short name T455
Test name
Test status
Simulation time 233305504 ps
CPU time 3.66 seconds
Started Feb 29 02:01:23 PM PST 24
Finished Feb 29 02:01:27 PM PST 24
Peak memory 207872 kb
Host smart-32b21d20-3cc9-4ceb-970d-3cddce074c99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277195270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.2277195270
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.2657008224
Short name T248
Test name
Test status
Simulation time 6798558064 ps
CPU time 202.97 seconds
Started Feb 29 02:01:27 PM PST 24
Finished Feb 29 02:04:51 PM PST 24
Peak memory 221936 kb
Host smart-db520f6a-27dc-42d2-af2a-66a68b79a811
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2657008224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.2657008224
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.3347585540
Short name T535
Test name
Test status
Simulation time 339624286 ps
CPU time 9.93 seconds
Started Feb 29 02:01:22 PM PST 24
Finished Feb 29 02:01:32 PM PST 24
Peak memory 221708 kb
Host smart-9f9f62b4-7c67-4187-993d-4135a531d72a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3347585540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.3347585540
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.386981235
Short name T410
Test name
Test status
Simulation time 85110708 ps
CPU time 1.73 seconds
Started Feb 29 02:01:25 PM PST 24
Finished Feb 29 02:01:27 PM PST 24
Peak memory 208816 kb
Host smart-a88d1bbe-4b13-4ce9-b480-e53ceba81df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386981235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.386981235
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.2978114926
Short name T886
Test name
Test status
Simulation time 19934164 ps
CPU time 0.89 seconds
Started Feb 29 02:05:01 PM PST 24
Finished Feb 29 02:05:02 PM PST 24
Peak memory 205504 kb
Host smart-00f784d9-9611-4f9a-baba-dcd14d921edc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978114926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.2978114926
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.3102420426
Short name T863
Test name
Test status
Simulation time 190467125 ps
CPU time 3.66 seconds
Started Feb 29 02:04:42 PM PST 24
Finished Feb 29 02:04:46 PM PST 24
Peak memory 217728 kb
Host smart-40dd4fc6-5f23-43d1-a99b-047da3fa844e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102420426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.3102420426
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.3589956817
Short name T196
Test name
Test status
Simulation time 261367117 ps
CPU time 2.04 seconds
Started Feb 29 02:04:43 PM PST 24
Finished Feb 29 02:04:45 PM PST 24
Peak memory 208472 kb
Host smart-fe4b39dd-6b4f-4864-ad13-ed564f2eaccd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589956817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.3589956817
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.827500380
Short name T89
Test name
Test status
Simulation time 503977661 ps
CPU time 6.36 seconds
Started Feb 29 02:04:42 PM PST 24
Finished Feb 29 02:04:49 PM PST 24
Peak memory 208756 kb
Host smart-ba233b6e-8d36-438e-bc15-d6c87cfa36fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=827500380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.827500380
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.3302148087
Short name T710
Test name
Test status
Simulation time 71711944 ps
CPU time 3.82 seconds
Started Feb 29 02:04:46 PM PST 24
Finished Feb 29 02:04:50 PM PST 24
Peak memory 213700 kb
Host smart-35fa278b-ba63-47e1-9786-7eef0ab38d83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302148087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.3302148087
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.2665455634
Short name T898
Test name
Test status
Simulation time 164339256 ps
CPU time 4.25 seconds
Started Feb 29 02:04:42 PM PST 24
Finished Feb 29 02:04:46 PM PST 24
Peak memory 206368 kb
Host smart-5c6a7d24-f4bc-4348-a066-f12b20c0f807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665455634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.2665455634
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.3653788490
Short name T525
Test name
Test status
Simulation time 1670453765 ps
CPU time 8.02 seconds
Started Feb 29 02:04:43 PM PST 24
Finished Feb 29 02:04:51 PM PST 24
Peak memory 208116 kb
Host smart-1313e87a-b89a-4550-95b1-3c9d6bb1bdf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3653788490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.3653788490
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.3570462721
Short name T182
Test name
Test status
Simulation time 488308087 ps
CPU time 6.13 seconds
Started Feb 29 02:04:41 PM PST 24
Finished Feb 29 02:04:48 PM PST 24
Peak memory 207868 kb
Host smart-ad2e42c6-9690-4e67-a2b5-a9affb095dc8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570462721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.3570462721
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.2481370567
Short name T449
Test name
Test status
Simulation time 77097442 ps
CPU time 3.39 seconds
Started Feb 29 02:04:44 PM PST 24
Finished Feb 29 02:04:47 PM PST 24
Peak memory 207300 kb
Host smart-e538c8c2-de3b-483f-b900-85f4a8dfc7fd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481370567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.2481370567
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.3243320349
Short name T648
Test name
Test status
Simulation time 67633553 ps
CPU time 2.94 seconds
Started Feb 29 02:04:43 PM PST 24
Finished Feb 29 02:04:47 PM PST 24
Peak memory 208904 kb
Host smart-dae51650-42f1-49b8-a41e-3345d5e95f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243320349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.3243320349
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.3912263482
Short name T728
Test name
Test status
Simulation time 513104733 ps
CPU time 15.08 seconds
Started Feb 29 02:04:43 PM PST 24
Finished Feb 29 02:04:59 PM PST 24
Peak memory 207820 kb
Host smart-3d140d31-0939-48f8-b5c6-86c5b058900b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3912263482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.3912263482
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.2616811049
Short name T835
Test name
Test status
Simulation time 1329190517 ps
CPU time 11.89 seconds
Started Feb 29 02:04:53 PM PST 24
Finished Feb 29 02:05:06 PM PST 24
Peak memory 215624 kb
Host smart-6dcda6a5-4d4e-4d9f-97a7-ec6f1d66d34f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2616811049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.2616811049
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.2741731657
Short name T229
Test name
Test status
Simulation time 142132644 ps
CPU time 3.91 seconds
Started Feb 29 02:04:43 PM PST 24
Finished Feb 29 02:04:48 PM PST 24
Peak memory 206892 kb
Host smart-4a5c22d7-a819-48bf-b43e-2e7cbfa2386f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2741731657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.2741731657
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.4068010631
Short name T460
Test name
Test status
Simulation time 256353974 ps
CPU time 2.02 seconds
Started Feb 29 02:04:50 PM PST 24
Finished Feb 29 02:04:53 PM PST 24
Peak memory 208876 kb
Host smart-d32d8de9-b978-4395-aac0-62d09bfc3d2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068010631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.4068010631
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.921387779
Short name T788
Test name
Test status
Simulation time 46379644 ps
CPU time 0.95 seconds
Started Feb 29 02:04:53 PM PST 24
Finished Feb 29 02:04:55 PM PST 24
Peak memory 205476 kb
Host smart-c413bfa1-d883-43b8-89f2-cc11d4023ffb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921387779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.921387779
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.3386902271
Short name T289
Test name
Test status
Simulation time 228296700 ps
CPU time 4.42 seconds
Started Feb 29 02:04:53 PM PST 24
Finished Feb 29 02:04:59 PM PST 24
Peak memory 213696 kb
Host smart-3d116d5c-83b8-4e51-83b0-99e060b67dd0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3386902271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.3386902271
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.3616820452
Short name T895
Test name
Test status
Simulation time 452522776 ps
CPU time 7.19 seconds
Started Feb 29 02:04:54 PM PST 24
Finished Feb 29 02:05:02 PM PST 24
Peak memory 213968 kb
Host smart-3f36a292-aa44-4106-81ee-19a48c9e211a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616820452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.3616820452
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.3003609598
Short name T746
Test name
Test status
Simulation time 100744895 ps
CPU time 2.58 seconds
Started Feb 29 02:04:53 PM PST 24
Finished Feb 29 02:04:57 PM PST 24
Peak memory 208264 kb
Host smart-83e40f76-1706-4cf9-a610-468fd8f40f7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003609598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.3003609598
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.2384937260
Short name T282
Test name
Test status
Simulation time 986795735 ps
CPU time 29.3 seconds
Started Feb 29 02:04:52 PM PST 24
Finished Feb 29 02:05:21 PM PST 24
Peak memory 209008 kb
Host smart-3081f28b-9d33-4549-84bc-8e6ff562600d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2384937260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.2384937260
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.2614693665
Short name T357
Test name
Test status
Simulation time 784675663 ps
CPU time 10.09 seconds
Started Feb 29 02:04:57 PM PST 24
Finished Feb 29 02:05:09 PM PST 24
Peak memory 213584 kb
Host smart-303ada86-c36a-46f6-b2fa-5e9662780cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614693665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.2614693665
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.366845868
Short name T616
Test name
Test status
Simulation time 124854807 ps
CPU time 5.77 seconds
Started Feb 29 02:04:54 PM PST 24
Finished Feb 29 02:05:01 PM PST 24
Peak memory 208600 kb
Host smart-6667cada-2146-4ac7-ae5e-833988a9091f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366845868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.366845868
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.68289374
Short name T576
Test name
Test status
Simulation time 570728398 ps
CPU time 5.92 seconds
Started Feb 29 02:04:54 PM PST 24
Finished Feb 29 02:05:01 PM PST 24
Peak memory 208908 kb
Host smart-d6f4e7ef-9979-4606-a92a-0ab9cbe5ea3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68289374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.68289374
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.1074215266
Short name T486
Test name
Test status
Simulation time 859017781 ps
CPU time 20.71 seconds
Started Feb 29 02:04:56 PM PST 24
Finished Feb 29 02:05:19 PM PST 24
Peak memory 207520 kb
Host smart-fbed60b5-813f-4938-913d-b26e0edea76b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1074215266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.1074215266
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.3505445172
Short name T238
Test name
Test status
Simulation time 8349744867 ps
CPU time 63.29 seconds
Started Feb 29 02:04:53 PM PST 24
Finished Feb 29 02:05:56 PM PST 24
Peak memory 207676 kb
Host smart-ebfe31aa-0211-4530-9447-faf7e7f778c2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3505445172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.3505445172
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.1148273192
Short name T429
Test name
Test status
Simulation time 74968505 ps
CPU time 3.5 seconds
Started Feb 29 02:04:50 PM PST 24
Finished Feb 29 02:04:54 PM PST 24
Peak memory 207740 kb
Host smart-fedc248d-919b-4522-9f4e-2bdb58dc3afd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148273192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.1148273192
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.1938412306
Short name T579
Test name
Test status
Simulation time 13288517052 ps
CPU time 24.21 seconds
Started Feb 29 02:04:55 PM PST 24
Finished Feb 29 02:05:20 PM PST 24
Peak memory 208068 kb
Host smart-7011e95c-c2dc-430c-9822-4489dbe1d518
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938412306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.1938412306
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.2772394567
Short name T651
Test name
Test status
Simulation time 105804676 ps
CPU time 2.37 seconds
Started Feb 29 02:04:54 PM PST 24
Finished Feb 29 02:04:57 PM PST 24
Peak memory 207012 kb
Host smart-b9a865f3-7f95-4c48-962e-003431fe8083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772394567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.2772394567
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.631234393
Short name T543
Test name
Test status
Simulation time 226142402 ps
CPU time 2.93 seconds
Started Feb 29 02:04:57 PM PST 24
Finished Feb 29 02:05:02 PM PST 24
Peak memory 207516 kb
Host smart-22124ed2-9c11-4cc3-8938-d529b234676f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631234393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.631234393
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.3144122845
Short name T750
Test name
Test status
Simulation time 52092703 ps
CPU time 3.38 seconds
Started Feb 29 02:04:52 PM PST 24
Finished Feb 29 02:04:56 PM PST 24
Peak memory 217724 kb
Host smart-edd9d125-c602-4978-8e62-f3e358a501b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144122845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.3144122845
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.344948999
Short name T575
Test name
Test status
Simulation time 408071382 ps
CPU time 4.23 seconds
Started Feb 29 02:05:01 PM PST 24
Finished Feb 29 02:05:05 PM PST 24
Peak memory 210064 kb
Host smart-85bf29f2-b5fd-4e28-a8c6-5ed700c9bc1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=344948999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.344948999
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.401994738
Short name T544
Test name
Test status
Simulation time 15090317 ps
CPU time 0.73 seconds
Started Feb 29 02:04:53 PM PST 24
Finished Feb 29 02:04:55 PM PST 24
Peak memory 205148 kb
Host smart-37840443-cc2f-456f-a12d-3d6329a7333f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=401994738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.401994738
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.4059433623
Short name T401
Test name
Test status
Simulation time 72575074 ps
CPU time 3.66 seconds
Started Feb 29 02:05:02 PM PST 24
Finished Feb 29 02:05:06 PM PST 24
Peak memory 208728 kb
Host smart-7686aeab-1ea1-4180-bcfc-825d50b007d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059433623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.4059433623
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.2317877335
Short name T632
Test name
Test status
Simulation time 38796359 ps
CPU time 1.59 seconds
Started Feb 29 02:05:00 PM PST 24
Finished Feb 29 02:05:02 PM PST 24
Peak memory 213672 kb
Host smart-f16a980d-27b5-4268-8041-a25153062d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317877335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.2317877335
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.1382130543
Short name T529
Test name
Test status
Simulation time 1470738619 ps
CPU time 5.16 seconds
Started Feb 29 02:04:51 PM PST 24
Finished Feb 29 02:04:56 PM PST 24
Peak memory 213876 kb
Host smart-150ebd30-b6e6-4e8a-a03f-2551a39b3d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1382130543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.1382130543
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.1742099391
Short name T715
Test name
Test status
Simulation time 60527053 ps
CPU time 3.23 seconds
Started Feb 29 02:05:02 PM PST 24
Finished Feb 29 02:05:06 PM PST 24
Peak memory 219216 kb
Host smart-df6fed86-36b3-4681-9784-b48abf703190
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1742099391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.1742099391
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.2375017810
Short name T679
Test name
Test status
Simulation time 191671156 ps
CPU time 2.82 seconds
Started Feb 29 02:04:53 PM PST 24
Finished Feb 29 02:04:57 PM PST 24
Peak memory 217424 kb
Host smart-a1f73e36-4701-4a83-abc3-871e225192a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2375017810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.2375017810
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.684994586
Short name T647
Test name
Test status
Simulation time 55825670 ps
CPU time 3.07 seconds
Started Feb 29 02:04:56 PM PST 24
Finished Feb 29 02:05:01 PM PST 24
Peak memory 205816 kb
Host smart-32b864b0-a8e1-4c09-88da-9a33f137cbbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684994586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.684994586
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.607927145
Short name T766
Test name
Test status
Simulation time 51255269 ps
CPU time 2.99 seconds
Started Feb 29 02:04:53 PM PST 24
Finished Feb 29 02:04:56 PM PST 24
Peak memory 207108 kb
Host smart-43799da7-70e7-45c7-9ffa-a9670c676ed6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=607927145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.607927145
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.155091306
Short name T889
Test name
Test status
Simulation time 70472726 ps
CPU time 1.8 seconds
Started Feb 29 02:04:54 PM PST 24
Finished Feb 29 02:04:56 PM PST 24
Peak memory 206140 kb
Host smart-70edaffd-af5b-4585-a2e1-e82bff996339
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=155091306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.155091306
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.243672884
Short name T479
Test name
Test status
Simulation time 251337648 ps
CPU time 7.61 seconds
Started Feb 29 02:04:54 PM PST 24
Finished Feb 29 02:05:03 PM PST 24
Peak memory 206552 kb
Host smart-348c6c83-b5f1-4c85-8c7f-5d388550810a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243672884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.243672884
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.1002891966
Short name T441
Test name
Test status
Simulation time 671774326 ps
CPU time 5.15 seconds
Started Feb 29 02:04:51 PM PST 24
Finished Feb 29 02:04:57 PM PST 24
Peak memory 208220 kb
Host smart-5346d0b1-0b97-492e-9a0c-e3656cb0d4bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002891966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.1002891966
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.2331330293
Short name T106
Test name
Test status
Simulation time 80133442 ps
CPU time 2.84 seconds
Started Feb 29 02:04:51 PM PST 24
Finished Feb 29 02:04:54 PM PST 24
Peak memory 207692 kb
Host smart-581dfd79-e6d0-4738-8a73-118c1062a8bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331330293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.2331330293
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.1470999588
Short name T82
Test name
Test status
Simulation time 903282902 ps
CPU time 10.8 seconds
Started Feb 29 02:04:55 PM PST 24
Finished Feb 29 02:05:06 PM PST 24
Peak memory 220404 kb
Host smart-d40e6a22-2990-462b-9692-30f101472730
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470999588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.1470999588
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_stress_all_with_rand_reset.1163686972
Short name T179
Test name
Test status
Simulation time 251746111 ps
CPU time 10.18 seconds
Started Feb 29 02:05:02 PM PST 24
Finished Feb 29 02:05:13 PM PST 24
Peak memory 221940 kb
Host smart-e2b56439-56b4-4ea0-a7dd-7f16f483dc14
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163686972 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all_with_rand_reset.1163686972
Directory /workspace/42.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.618955679
Short name T360
Test name
Test status
Simulation time 122893788 ps
CPU time 5.74 seconds
Started Feb 29 02:04:56 PM PST 24
Finished Feb 29 02:05:02 PM PST 24
Peak memory 209208 kb
Host smart-d29d2475-7585-4f8c-87ec-66e91c3fdfdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618955679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.618955679
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.3349010531
Short name T195
Test name
Test status
Simulation time 114515200 ps
CPU time 2.54 seconds
Started Feb 29 02:04:51 PM PST 24
Finished Feb 29 02:04:53 PM PST 24
Peak memory 209648 kb
Host smart-dc6d54fd-2613-4264-bec5-3b366e779cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349010531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.3349010531
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.405416577
Short name T526
Test name
Test status
Simulation time 69548943 ps
CPU time 0.93 seconds
Started Feb 29 02:05:13 PM PST 24
Finished Feb 29 02:05:15 PM PST 24
Peak memory 205332 kb
Host smart-8cd6dae5-ac09-4b85-b997-f8ef3254c04e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405416577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.405416577
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.2909790933
Short name T265
Test name
Test status
Simulation time 1768842042 ps
CPU time 73.93 seconds
Started Feb 29 02:04:56 PM PST 24
Finished Feb 29 02:06:10 PM PST 24
Peak memory 221268 kb
Host smart-d48dfbc2-77b3-406f-899c-c7e735c18e0e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2909790933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.2909790933
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.2835801551
Short name T33
Test name
Test status
Simulation time 241741738 ps
CPU time 2.72 seconds
Started Feb 29 02:04:53 PM PST 24
Finished Feb 29 02:04:57 PM PST 24
Peak memory 208656 kb
Host smart-6b493d04-de3c-40f9-adba-830356f5319f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2835801551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.2835801551
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.1567872521
Short name T80
Test name
Test status
Simulation time 274492997 ps
CPU time 2.68 seconds
Started Feb 29 02:05:01 PM PST 24
Finished Feb 29 02:05:04 PM PST 24
Peak memory 207900 kb
Host smart-45c27f5c-265c-4f06-96a0-6f4e9f67f48d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567872521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.1567872521
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.3199384024
Short name T93
Test name
Test status
Simulation time 450580581 ps
CPU time 9.97 seconds
Started Feb 29 02:04:56 PM PST 24
Finished Feb 29 02:05:08 PM PST 24
Peak memory 209200 kb
Host smart-93987929-330d-4c66-837b-7d9c2ad3252c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3199384024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.3199384024
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.1046564158
Short name T324
Test name
Test status
Simulation time 404678292 ps
CPU time 8.61 seconds
Started Feb 29 02:04:50 PM PST 24
Finished Feb 29 02:04:59 PM PST 24
Peak memory 221768 kb
Host smart-defd3ea6-3b43-4955-acf6-abcb346adb73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046564158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.1046564158
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.2606519675
Short name T252
Test name
Test status
Simulation time 54110984 ps
CPU time 2.75 seconds
Started Feb 29 02:04:57 PM PST 24
Finished Feb 29 02:05:01 PM PST 24
Peak memory 209204 kb
Host smart-936e9f61-02bd-4e66-865c-e4613a71088c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606519675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.2606519675
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.3626396110
Short name T652
Test name
Test status
Simulation time 208049691 ps
CPU time 5.31 seconds
Started Feb 29 02:04:57 PM PST 24
Finished Feb 29 02:05:04 PM PST 24
Peak memory 217752 kb
Host smart-8c5bec71-a7a0-4bd5-b46a-b7460afcaf4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3626396110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.3626396110
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.4142109492
Short name T186
Test name
Test status
Simulation time 243020121 ps
CPU time 2.71 seconds
Started Feb 29 02:04:54 PM PST 24
Finished Feb 29 02:04:57 PM PST 24
Peak memory 205936 kb
Host smart-2d0fd8e6-34f2-45c7-92c9-09599d46ae8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4142109492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.4142109492
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.2296587329
Short name T88
Test name
Test status
Simulation time 152043405 ps
CPU time 2.6 seconds
Started Feb 29 02:04:56 PM PST 24
Finished Feb 29 02:05:01 PM PST 24
Peak memory 206060 kb
Host smart-95e09525-c6b5-448b-b853-5b84429da50d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296587329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.2296587329
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.370019108
Short name T488
Test name
Test status
Simulation time 303022369 ps
CPU time 5.81 seconds
Started Feb 29 02:04:57 PM PST 24
Finished Feb 29 02:05:05 PM PST 24
Peak memory 207112 kb
Host smart-f097be72-8768-4514-a4e5-24d8d791bc11
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370019108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.370019108
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.2161802025
Short name T611
Test name
Test status
Simulation time 8473272203 ps
CPU time 58.19 seconds
Started Feb 29 02:04:52 PM PST 24
Finished Feb 29 02:05:50 PM PST 24
Peak memory 207180 kb
Host smart-1d421669-c424-4453-813f-c88dd44b8362
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161802025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.2161802025
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.1009983323
Short name T542
Test name
Test status
Simulation time 1292756682 ps
CPU time 9.5 seconds
Started Feb 29 02:05:09 PM PST 24
Finished Feb 29 02:05:19 PM PST 24
Peak memory 217736 kb
Host smart-538b60c9-e336-4a00-8f41-3b04198143c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009983323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.1009983323
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.1092404650
Short name T596
Test name
Test status
Simulation time 249981178 ps
CPU time 4.19 seconds
Started Feb 29 02:04:58 PM PST 24
Finished Feb 29 02:05:03 PM PST 24
Peak memory 207524 kb
Host smart-889b3cf9-1681-4f67-8544-5640ab2cc9ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1092404650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.1092404650
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.3645416007
Short name T376
Test name
Test status
Simulation time 233591772 ps
CPU time 10.07 seconds
Started Feb 29 02:05:11 PM PST 24
Finished Feb 29 02:05:23 PM PST 24
Peak memory 217860 kb
Host smart-6ebb64a0-201c-4d18-ab85-4df9fa15e469
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645416007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.3645416007
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.2744138351
Short name T295
Test name
Test status
Simulation time 4075927751 ps
CPU time 39.99 seconds
Started Feb 29 02:04:54 PM PST 24
Finished Feb 29 02:05:35 PM PST 24
Peak memory 208512 kb
Host smart-554ffd24-685b-4553-aaf4-1ed568d5f543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744138351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.2744138351
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.2277554378
Short name T416
Test name
Test status
Simulation time 1280676583 ps
CPU time 4.93 seconds
Started Feb 29 02:05:12 PM PST 24
Finished Feb 29 02:05:18 PM PST 24
Peak memory 209492 kb
Host smart-d30cc0e4-7bd3-4ad7-83a1-0872479b1d0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277554378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.2277554378
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.975848544
Short name T577
Test name
Test status
Simulation time 16670887 ps
CPU time 0.98 seconds
Started Feb 29 02:05:09 PM PST 24
Finished Feb 29 02:05:11 PM PST 24
Peak memory 205392 kb
Host smart-a84d1e7f-4a9d-4695-9b5a-85b94ee24539
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=975848544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.975848544
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.2467531206
Short name T39
Test name
Test status
Simulation time 401265620 ps
CPU time 11.12 seconds
Started Feb 29 02:05:07 PM PST 24
Finished Feb 29 02:05:19 PM PST 24
Peak memory 213608 kb
Host smart-eedd07e8-8977-40fd-9988-d426e1e7fd93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2467531206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.2467531206
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.260013852
Short name T894
Test name
Test status
Simulation time 1007418860 ps
CPU time 2.51 seconds
Started Feb 29 02:05:10 PM PST 24
Finished Feb 29 02:05:15 PM PST 24
Peak memory 208952 kb
Host smart-cb06da23-c842-474b-9016-011c45b67c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260013852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.260013852
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.2076446501
Short name T817
Test name
Test status
Simulation time 479400486 ps
CPU time 4.72 seconds
Started Feb 29 02:05:12 PM PST 24
Finished Feb 29 02:05:17 PM PST 24
Peak memory 208144 kb
Host smart-9065bf24-8e8a-4754-b2c7-5ae9e51f7d23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076446501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.2076446501
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.1198496824
Short name T311
Test name
Test status
Simulation time 98826590 ps
CPU time 3.07 seconds
Started Feb 29 02:05:10 PM PST 24
Finished Feb 29 02:05:14 PM PST 24
Peak memory 219852 kb
Host smart-5ed086bc-6454-4930-b913-d48b1539e7d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1198496824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.1198496824
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.1349689316
Short name T690
Test name
Test status
Simulation time 360573466 ps
CPU time 8.21 seconds
Started Feb 29 02:05:13 PM PST 24
Finished Feb 29 02:05:22 PM PST 24
Peak memory 208868 kb
Host smart-4e22accc-def8-4684-b088-088442399857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1349689316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.1349689316
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.41032566
Short name T211
Test name
Test status
Simulation time 534838201 ps
CPU time 4.95 seconds
Started Feb 29 02:05:13 PM PST 24
Finished Feb 29 02:05:19 PM PST 24
Peak memory 205760 kb
Host smart-18215fcd-5a26-488c-9639-6d302c57e375
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41032566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.41032566
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.2478893612
Short name T741
Test name
Test status
Simulation time 8500456560 ps
CPU time 24.97 seconds
Started Feb 29 02:05:11 PM PST 24
Finished Feb 29 02:05:38 PM PST 24
Peak memory 207280 kb
Host smart-123c65d4-ae90-48fd-aeef-36c3537ff01b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478893612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.2478893612
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.3541938229
Short name T546
Test name
Test status
Simulation time 117954587 ps
CPU time 4.77 seconds
Started Feb 29 02:05:09 PM PST 24
Finished Feb 29 02:05:15 PM PST 24
Peak memory 207500 kb
Host smart-e1769292-7980-4ecc-89f0-7bb3f024a5fe
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3541938229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.3541938229
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.2115105857
Short name T744
Test name
Test status
Simulation time 1386022639 ps
CPU time 22.19 seconds
Started Feb 29 02:05:11 PM PST 24
Finished Feb 29 02:05:35 PM PST 24
Peak memory 207212 kb
Host smart-8d6a0d88-37cf-48c7-8dcb-2c1796a5ae98
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115105857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.2115105857
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.1822358927
Short name T140
Test name
Test status
Simulation time 932124326 ps
CPU time 14.18 seconds
Started Feb 29 02:05:11 PM PST 24
Finished Feb 29 02:05:27 PM PST 24
Peak memory 209028 kb
Host smart-d701a61f-a507-4227-8946-1b84599a5d55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822358927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.1822358927
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.1952539677
Short name T851
Test name
Test status
Simulation time 175366294 ps
CPU time 4.72 seconds
Started Feb 29 02:05:09 PM PST 24
Finished Feb 29 02:05:15 PM PST 24
Peak memory 207376 kb
Host smart-ce771cce-5f7f-4764-a88a-c60df53b54ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952539677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.1952539677
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.3503532207
Short name T687
Test name
Test status
Simulation time 174763019 ps
CPU time 3.01 seconds
Started Feb 29 02:05:09 PM PST 24
Finished Feb 29 02:05:13 PM PST 24
Peak memory 213588 kb
Host smart-85838565-51f1-4ce9-8e18-e57bb6ed9b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3503532207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.3503532207
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.1116493993
Short name T60
Test name
Test status
Simulation time 487727942 ps
CPU time 10.56 seconds
Started Feb 29 02:05:11 PM PST 24
Finished Feb 29 02:05:23 PM PST 24
Peak memory 210132 kb
Host smart-f5ac2338-0eaa-475c-be38-0f12cf0e9629
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116493993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.1116493993
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.3438845518
Short name T466
Test name
Test status
Simulation time 27948711 ps
CPU time 0.69 seconds
Started Feb 29 02:05:12 PM PST 24
Finished Feb 29 02:05:14 PM PST 24
Peak memory 205368 kb
Host smart-1ab159da-aea1-4da9-822a-6808a373e39c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3438845518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.3438845518
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.3542738824
Short name T34
Test name
Test status
Simulation time 103239693 ps
CPU time 3.67 seconds
Started Feb 29 02:05:09 PM PST 24
Finished Feb 29 02:05:14 PM PST 24
Peak memory 213668 kb
Host smart-d914259a-75e5-4904-870f-6bb9ebf840a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542738824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.3542738824
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.3401013997
Short name T622
Test name
Test status
Simulation time 266444153 ps
CPU time 2.43 seconds
Started Feb 29 02:05:10 PM PST 24
Finished Feb 29 02:05:13 PM PST 24
Peak memory 213712 kb
Host smart-e0bbad01-235e-4110-8e36-479b9cba8cbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401013997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.3401013997
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.2241598669
Short name T836
Test name
Test status
Simulation time 619500839 ps
CPU time 4.19 seconds
Started Feb 29 02:05:10 PM PST 24
Finished Feb 29 02:05:16 PM PST 24
Peak memory 218316 kb
Host smart-44281fe5-f756-433f-b3da-fc345d73dd50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2241598669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.2241598669
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.3878241400
Short name T323
Test name
Test status
Simulation time 57475017 ps
CPU time 3.7 seconds
Started Feb 29 02:05:11 PM PST 24
Finished Feb 29 02:05:16 PM PST 24
Peak memory 213604 kb
Host smart-7f5a50bf-98fc-432c-a27e-97fbe51830b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878241400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.3878241400
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.2009598280
Short name T246
Test name
Test status
Simulation time 54125315 ps
CPU time 2.05 seconds
Started Feb 29 02:05:09 PM PST 24
Finished Feb 29 02:05:12 PM PST 24
Peak memory 214480 kb
Host smart-5a08aa74-18b7-4f25-aa11-7d6eddc85753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2009598280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.2009598280
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.3620221087
Short name T547
Test name
Test status
Simulation time 527115489 ps
CPU time 17.69 seconds
Started Feb 29 02:05:11 PM PST 24
Finished Feb 29 02:05:30 PM PST 24
Peak memory 208412 kb
Host smart-3d4915d1-be68-4e1d-9ede-4a89f3b01610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620221087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.3620221087
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.667675423
Short name T212
Test name
Test status
Simulation time 1027814384 ps
CPU time 23.89 seconds
Started Feb 29 02:05:10 PM PST 24
Finished Feb 29 02:05:36 PM PST 24
Peak memory 207428 kb
Host smart-a2a4ed76-c880-4fa4-ba17-755102c02466
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=667675423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.667675423
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.2102894600
Short name T340
Test name
Test status
Simulation time 520880728 ps
CPU time 6.93 seconds
Started Feb 29 02:05:10 PM PST 24
Finished Feb 29 02:05:19 PM PST 24
Peak memory 207828 kb
Host smart-1312f939-f3a9-40b0-a3d2-d821a726ce68
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2102894600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.2102894600
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.2471439994
Short name T477
Test name
Test status
Simulation time 66361615 ps
CPU time 3.28 seconds
Started Feb 29 02:05:12 PM PST 24
Finished Feb 29 02:05:16 PM PST 24
Peak memory 207824 kb
Host smart-cea8c2e5-2308-4ee8-8d4a-215cc1ea01f3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2471439994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.2471439994
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.379040320
Short name T549
Test name
Test status
Simulation time 1464094373 ps
CPU time 10.9 seconds
Started Feb 29 02:05:09 PM PST 24
Finished Feb 29 02:05:21 PM PST 24
Peak memory 208060 kb
Host smart-ad5d86cd-07f9-4481-835a-98087140e161
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379040320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.379040320
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.1630300764
Short name T434
Test name
Test status
Simulation time 787567002 ps
CPU time 3.73 seconds
Started Feb 29 02:05:10 PM PST 24
Finished Feb 29 02:05:16 PM PST 24
Peak memory 213696 kb
Host smart-d3172496-2b81-401f-9aef-5425465f156b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630300764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.1630300764
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.3095284621
Short name T205
Test name
Test status
Simulation time 206123899 ps
CPU time 6.65 seconds
Started Feb 29 02:05:11 PM PST 24
Finished Feb 29 02:05:19 PM PST 24
Peak memory 206308 kb
Host smart-18c0391b-4bdd-4b15-8118-a23cc68fd935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095284621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.3095284621
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.3592490846
Short name T191
Test name
Test status
Simulation time 757142148 ps
CPU time 19.91 seconds
Started Feb 29 02:05:08 PM PST 24
Finished Feb 29 02:05:28 PM PST 24
Peak memory 215252 kb
Host smart-8d3e2a12-608c-405f-ab04-8ce7e574ef47
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592490846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.3592490846
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.3438983877
Short name T635
Test name
Test status
Simulation time 376141842 ps
CPU time 5.24 seconds
Started Feb 29 02:05:11 PM PST 24
Finished Feb 29 02:05:18 PM PST 24
Peak memory 208548 kb
Host smart-64e3a0dc-e0a6-4851-bbe4-168331d9a14f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438983877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.3438983877
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.1992420257
Short name T845
Test name
Test status
Simulation time 680680371 ps
CPU time 7.16 seconds
Started Feb 29 02:05:29 PM PST 24
Finished Feb 29 02:05:37 PM PST 24
Peak memory 210092 kb
Host smart-9b8a228e-e4e6-47b4-8a7b-7e7d01cf70ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1992420257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.1992420257
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.786959354
Short name T606
Test name
Test status
Simulation time 93626632 ps
CPU time 0.8 seconds
Started Feb 29 02:05:08 PM PST 24
Finished Feb 29 02:05:09 PM PST 24
Peak memory 205348 kb
Host smart-24bbae46-64dc-48c4-b0ee-87a7b967038c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=786959354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.786959354
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.1888188490
Short name T292
Test name
Test status
Simulation time 1009185470 ps
CPU time 13.94 seconds
Started Feb 29 02:05:08 PM PST 24
Finished Feb 29 02:05:22 PM PST 24
Peak memory 215188 kb
Host smart-0aa43def-8e33-43da-98b8-6c0ba359d4e6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1888188490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.1888188490
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.1628397489
Short name T608
Test name
Test status
Simulation time 964378820 ps
CPU time 6.95 seconds
Started Feb 29 02:05:11 PM PST 24
Finished Feb 29 02:05:20 PM PST 24
Peak memory 221420 kb
Host smart-72357ac6-7890-4439-ae7b-0d898a688682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628397489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.1628397489
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.246958457
Short name T624
Test name
Test status
Simulation time 205598219 ps
CPU time 2.88 seconds
Started Feb 29 02:05:11 PM PST 24
Finished Feb 29 02:05:16 PM PST 24
Peak memory 206604 kb
Host smart-6f44d913-43b8-4626-a35c-1620947473e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246958457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.246958457
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.4093449811
Short name T225
Test name
Test status
Simulation time 600850713 ps
CPU time 12.7 seconds
Started Feb 29 02:05:10 PM PST 24
Finished Feb 29 02:05:25 PM PST 24
Peak memory 209968 kb
Host smart-e8e21ef4-9b58-4b52-aefe-5400f54479cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093449811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.4093449811
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.3039246876
Short name T872
Test name
Test status
Simulation time 1726359000 ps
CPU time 24.61 seconds
Started Feb 29 02:05:12 PM PST 24
Finished Feb 29 02:05:38 PM PST 24
Peak memory 220732 kb
Host smart-f0450dd9-cc5d-4205-afce-3f72ac841505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3039246876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.3039246876
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.3990126728
Short name T644
Test name
Test status
Simulation time 91382598 ps
CPU time 4 seconds
Started Feb 29 02:05:07 PM PST 24
Finished Feb 29 02:05:11 PM PST 24
Peak memory 206028 kb
Host smart-3504520c-6d93-41cd-8338-57975e803e87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990126728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.3990126728
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.2068386956
Short name T84
Test name
Test status
Simulation time 981596362 ps
CPU time 3.51 seconds
Started Feb 29 02:05:10 PM PST 24
Finished Feb 29 02:05:15 PM PST 24
Peak memory 205428 kb
Host smart-5350c0e5-3d2d-4d25-8453-c12651a918ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068386956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.2068386956
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.2310794537
Short name T661
Test name
Test status
Simulation time 128086360 ps
CPU time 2.4 seconds
Started Feb 29 02:05:10 PM PST 24
Finished Feb 29 02:05:13 PM PST 24
Peak memory 205952 kb
Host smart-ba6f8a6f-9cc0-49ff-bdd1-1210df5181a6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2310794537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.2310794537
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.868761936
Short name T347
Test name
Test status
Simulation time 246012556 ps
CPU time 6.87 seconds
Started Feb 29 02:05:08 PM PST 24
Finished Feb 29 02:05:15 PM PST 24
Peak memory 207580 kb
Host smart-70fe1c41-f8a2-441a-88f6-19e42ad84a5c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868761936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.868761936
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.3791960572
Short name T139
Test name
Test status
Simulation time 283427841 ps
CPU time 4.75 seconds
Started Feb 29 02:05:11 PM PST 24
Finished Feb 29 02:05:17 PM PST 24
Peak memory 206012 kb
Host smart-7e6124aa-6091-4821-99e7-b0d1f1b22de5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791960572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.3791960572
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.2822929588
Short name T4
Test name
Test status
Simulation time 582965236 ps
CPU time 13.45 seconds
Started Feb 29 02:05:11 PM PST 24
Finished Feb 29 02:05:26 PM PST 24
Peak memory 209368 kb
Host smart-dd7a0125-290d-40ad-af35-8e13106e8d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822929588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.2822929588
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.691583321
Short name T423
Test name
Test status
Simulation time 870971044 ps
CPU time 8.22 seconds
Started Feb 29 02:05:10 PM PST 24
Finished Feb 29 02:05:21 PM PST 24
Peak memory 207672 kb
Host smart-5bbeb760-ee36-4920-b487-8272835250b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691583321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.691583321
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.295877296
Short name T802
Test name
Test status
Simulation time 541071419 ps
CPU time 18.29 seconds
Started Feb 29 02:05:10 PM PST 24
Finished Feb 29 02:05:30 PM PST 24
Peak memory 213640 kb
Host smart-1d418331-3a86-4efd-be67-01aaa5dda13a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295877296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.295877296
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.2605782043
Short name T892
Test name
Test status
Simulation time 1639414227 ps
CPU time 62.89 seconds
Started Feb 29 02:05:10 PM PST 24
Finished Feb 29 02:06:15 PM PST 24
Peak memory 209092 kb
Host smart-9a8e92c7-72d8-4707-910e-ab818bdf1823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605782043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.2605782043
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.3976154636
Short name T218
Test name
Test status
Simulation time 41165849 ps
CPU time 1.6 seconds
Started Feb 29 02:05:11 PM PST 24
Finished Feb 29 02:05:14 PM PST 24
Peak memory 208916 kb
Host smart-e197f29c-8f32-48b4-8772-34cc5e60bf20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3976154636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.3976154636
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.945947692
Short name T808
Test name
Test status
Simulation time 50386394 ps
CPU time 0.84 seconds
Started Feb 29 02:05:23 PM PST 24
Finished Feb 29 02:05:24 PM PST 24
Peak memory 205332 kb
Host smart-887a1111-3bd9-4cc5-be65-5e3a65993a32
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945947692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.945947692
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.3930142988
Short name T336
Test name
Test status
Simulation time 1315143493 ps
CPU time 16.59 seconds
Started Feb 29 02:05:19 PM PST 24
Finished Feb 29 02:05:36 PM PST 24
Peak memory 214388 kb
Host smart-3fa19917-3dd5-4287-b424-fc72f90c5d34
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3930142988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.3930142988
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.1838815876
Short name T293
Test name
Test status
Simulation time 3421292958 ps
CPU time 33.85 seconds
Started Feb 29 02:05:20 PM PST 24
Finished Feb 29 02:05:54 PM PST 24
Peak memory 213724 kb
Host smart-52f48c94-b5aa-4831-9964-cb3992f7945c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838815876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.1838815876
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.3966748033
Short name T689
Test name
Test status
Simulation time 92207736 ps
CPU time 4.33 seconds
Started Feb 29 02:05:20 PM PST 24
Finished Feb 29 02:05:25 PM PST 24
Peak memory 207908 kb
Host smart-9c1c9783-3a1c-4093-8817-6a7782798b3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966748033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.3966748033
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.3719979520
Short name T428
Test name
Test status
Simulation time 154717297 ps
CPU time 3.1 seconds
Started Feb 29 02:05:19 PM PST 24
Finished Feb 29 02:05:22 PM PST 24
Peak memory 208680 kb
Host smart-5e6e740f-1a59-43c7-9af0-56c2cd1aae02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3719979520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.3719979520
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.274551945
Short name T697
Test name
Test status
Simulation time 343191127 ps
CPU time 6.83 seconds
Started Feb 29 02:05:10 PM PST 24
Finished Feb 29 02:05:17 PM PST 24
Peak memory 208324 kb
Host smart-811df85b-ebfb-4bb7-af1d-fe261c2e9b8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274551945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.274551945
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.1758235337
Short name T556
Test name
Test status
Simulation time 3487201895 ps
CPU time 65.42 seconds
Started Feb 29 02:05:10 PM PST 24
Finished Feb 29 02:06:17 PM PST 24
Peak memory 207256 kb
Host smart-31aaecc4-af01-40ed-91fe-2c3d8a4a3607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758235337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.1758235337
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.1229526802
Short name T184
Test name
Test status
Simulation time 239979438 ps
CPU time 2.88 seconds
Started Feb 29 02:05:12 PM PST 24
Finished Feb 29 02:05:16 PM PST 24
Peak memory 206064 kb
Host smart-de9986fb-890d-4de1-8db9-e29abe492e8f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1229526802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.1229526802
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.3643358861
Short name T615
Test name
Test status
Simulation time 67156301 ps
CPU time 2.87 seconds
Started Feb 29 02:05:08 PM PST 24
Finished Feb 29 02:05:13 PM PST 24
Peak memory 207576 kb
Host smart-bd7c8e31-e70e-491e-bc20-09fd4ab08ed3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643358861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.3643358861
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.1748344052
Short name T470
Test name
Test status
Simulation time 1497628137 ps
CPU time 11.07 seconds
Started Feb 29 02:05:12 PM PST 24
Finished Feb 29 02:05:24 PM PST 24
Peak memory 207684 kb
Host smart-aa4965d8-1f6d-4c01-a175-d09d18dc729a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1748344052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.1748344052
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.2113281411
Short name T720
Test name
Test status
Simulation time 648805534 ps
CPU time 7.48 seconds
Started Feb 29 02:05:19 PM PST 24
Finished Feb 29 02:05:27 PM PST 24
Peak memory 208492 kb
Host smart-106fba9b-ae82-448a-bab0-715245c8ef0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113281411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.2113281411
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.3289943405
Short name T3
Test name
Test status
Simulation time 41685795 ps
CPU time 2.56 seconds
Started Feb 29 02:05:07 PM PST 24
Finished Feb 29 02:05:10 PM PST 24
Peak memory 207416 kb
Host smart-24faaf95-a45f-4990-8e36-ce5d383ed081
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289943405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.3289943405
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.2656931276
Short name T396
Test name
Test status
Simulation time 84763389 ps
CPU time 4.19 seconds
Started Feb 29 02:05:19 PM PST 24
Finished Feb 29 02:05:23 PM PST 24
Peak memory 221844 kb
Host smart-1ed57315-e256-4168-8df2-18a471da0df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656931276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.2656931276
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.56548049
Short name T54
Test name
Test status
Simulation time 125324445 ps
CPU time 2.95 seconds
Started Feb 29 02:05:19 PM PST 24
Finished Feb 29 02:05:23 PM PST 24
Peak memory 209464 kb
Host smart-dd58fce1-1018-4cf3-9a9c-a914c61033f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=56548049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.56548049
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.1787443524
Short name T504
Test name
Test status
Simulation time 10360611 ps
CPU time 0.72 seconds
Started Feb 29 02:05:23 PM PST 24
Finished Feb 29 02:05:24 PM PST 24
Peak memory 205192 kb
Host smart-7ee5adc9-96e3-4a95-8689-c7407afa615d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1787443524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.1787443524
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.2138233276
Short name T309
Test name
Test status
Simulation time 118444215 ps
CPU time 3.9 seconds
Started Feb 29 02:05:19 PM PST 24
Finished Feb 29 02:05:23 PM PST 24
Peak memory 214372 kb
Host smart-97b58922-eae2-44cc-9ae3-7ba7f72c4d33
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2138233276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.2138233276
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.479255805
Short name T20
Test name
Test status
Simulation time 79419030 ps
CPU time 4.17 seconds
Started Feb 29 02:05:20 PM PST 24
Finished Feb 29 02:05:24 PM PST 24
Peak memory 216980 kb
Host smart-015da687-5361-4d84-ac34-e8d6e7c2e54c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479255805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.479255805
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.1671521040
Short name T342
Test name
Test status
Simulation time 652310442 ps
CPU time 17.81 seconds
Started Feb 29 02:05:20 PM PST 24
Finished Feb 29 02:05:39 PM PST 24
Peak memory 207612 kb
Host smart-18f763b0-11e9-443d-a05d-6471b9144108
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1671521040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.1671521040
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.1290941329
Short name T405
Test name
Test status
Simulation time 162827146 ps
CPU time 2.94 seconds
Started Feb 29 02:05:17 PM PST 24
Finished Feb 29 02:05:21 PM PST 24
Peak memory 208076 kb
Host smart-31d27705-a24c-48b7-9f02-00b0d802757c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290941329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.1290941329
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.4258246491
Short name T302
Test name
Test status
Simulation time 2050984947 ps
CPU time 59.66 seconds
Started Feb 29 02:05:22 PM PST 24
Finished Feb 29 02:06:22 PM PST 24
Peak memory 221664 kb
Host smart-9b1dcf9d-86e4-4b4f-900d-945ae7f6a481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4258246491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.4258246491
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.2409997052
Short name T249
Test name
Test status
Simulation time 70645834 ps
CPU time 2.63 seconds
Started Feb 29 02:05:24 PM PST 24
Finished Feb 29 02:05:27 PM PST 24
Peak memory 221684 kb
Host smart-59780cd6-3332-479b-8119-87d6343fdeb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409997052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.2409997052
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.2326999273
Short name T769
Test name
Test status
Simulation time 150745545 ps
CPU time 3.63 seconds
Started Feb 29 02:05:22 PM PST 24
Finished Feb 29 02:05:26 PM PST 24
Peak memory 206028 kb
Host smart-017dbf78-62ab-43ba-abfd-65af6d005fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326999273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.2326999273
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.1489407149
Short name T503
Test name
Test status
Simulation time 174991724 ps
CPU time 5.2 seconds
Started Feb 29 02:05:24 PM PST 24
Finished Feb 29 02:05:30 PM PST 24
Peak memory 207536 kb
Host smart-c02d1623-4198-4235-8480-5082fc27aa95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489407149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.1489407149
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.3000588704
Short name T685
Test name
Test status
Simulation time 109335066 ps
CPU time 4.96 seconds
Started Feb 29 02:05:17 PM PST 24
Finished Feb 29 02:05:23 PM PST 24
Peak memory 208016 kb
Host smart-17ae12ab-3d6d-4987-acbb-3b1be4cd7605
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000588704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.3000588704
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.2079317910
Short name T854
Test name
Test status
Simulation time 2250814995 ps
CPU time 18.3 seconds
Started Feb 29 02:05:19 PM PST 24
Finished Feb 29 02:05:38 PM PST 24
Peak memory 207924 kb
Host smart-1942a642-fcf5-4e72-bff6-e4b51cf24ae5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079317910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.2079317910
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.1806178519
Short name T185
Test name
Test status
Simulation time 52203966 ps
CPU time 1.96 seconds
Started Feb 29 02:05:17 PM PST 24
Finished Feb 29 02:05:20 PM PST 24
Peak memory 206132 kb
Host smart-b9efdd68-3d58-42a4-a95c-816656ff990c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806178519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.1806178519
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.1669597835
Short name T214
Test name
Test status
Simulation time 374558777 ps
CPU time 2.29 seconds
Started Feb 29 02:05:19 PM PST 24
Finished Feb 29 02:05:22 PM PST 24
Peak memory 214732 kb
Host smart-45dce008-1c8e-44ae-816a-3cba97583f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1669597835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.1669597835
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.400174541
Short name T527
Test name
Test status
Simulation time 197519938 ps
CPU time 4.32 seconds
Started Feb 29 02:05:19 PM PST 24
Finished Feb 29 02:05:24 PM PST 24
Peak memory 205884 kb
Host smart-e8c6d435-4fd1-4a37-b1d8-5877ae5980ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400174541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.400174541
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.2483383549
Short name T120
Test name
Test status
Simulation time 565966066 ps
CPU time 16.81 seconds
Started Feb 29 02:05:25 PM PST 24
Finished Feb 29 02:05:42 PM PST 24
Peak memory 221976 kb
Host smart-c7284ca1-58d8-4ae3-a294-cba32fa5e302
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483383549 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.2483383549
Directory /workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.3310564990
Short name T350
Test name
Test status
Simulation time 351755649 ps
CPU time 6.94 seconds
Started Feb 29 02:05:19 PM PST 24
Finished Feb 29 02:05:26 PM PST 24
Peak memory 217468 kb
Host smart-b0c9a184-6958-49c6-95a3-0b04a49c9cc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310564990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.3310564990
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.798002649
Short name T572
Test name
Test status
Simulation time 98517207 ps
CPU time 1.91 seconds
Started Feb 29 02:05:22 PM PST 24
Finished Feb 29 02:05:24 PM PST 24
Peak memory 209168 kb
Host smart-c6f8ca57-18b1-42de-a77e-e4d5372a58aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798002649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.798002649
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.3703571828
Short name T660
Test name
Test status
Simulation time 30067897 ps
CPU time 0.95 seconds
Started Feb 29 02:05:24 PM PST 24
Finished Feb 29 02:05:26 PM PST 24
Peak memory 205420 kb
Host smart-80d42b18-91e1-4f98-ab43-df96d6e9a206
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703571828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.3703571828
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.3296471357
Short name T801
Test name
Test status
Simulation time 112723500 ps
CPU time 2.55 seconds
Started Feb 29 02:05:20 PM PST 24
Finished Feb 29 02:05:23 PM PST 24
Peak memory 213596 kb
Host smart-9ae70252-f367-466c-8e61-b1ca11ea0fbb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3296471357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.3296471357
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.1064825788
Short name T75
Test name
Test status
Simulation time 130984261 ps
CPU time 1.51 seconds
Started Feb 29 02:05:21 PM PST 24
Finished Feb 29 02:05:23 PM PST 24
Peak memory 206324 kb
Host smart-2e55a730-d7b0-4ca3-9cc3-96b94436158b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1064825788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.1064825788
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.1933599265
Short name T637
Test name
Test status
Simulation time 567492897 ps
CPU time 4.63 seconds
Started Feb 29 02:05:23 PM PST 24
Finished Feb 29 02:05:28 PM PST 24
Peak memory 217884 kb
Host smart-fdcc4e91-f74b-4dea-9ba7-8fc38710d2d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933599265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.1933599265
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.2622997245
Short name T670
Test name
Test status
Simulation time 232967291 ps
CPU time 2.44 seconds
Started Feb 29 02:05:21 PM PST 24
Finished Feb 29 02:05:24 PM PST 24
Peak memory 207552 kb
Host smart-a6ae25fe-72a7-4ac1-8f58-c0d80fe06aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622997245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.2622997245
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.2622173998
Short name T207
Test name
Test status
Simulation time 1771380840 ps
CPU time 9.16 seconds
Started Feb 29 02:05:23 PM PST 24
Finished Feb 29 02:05:32 PM PST 24
Peak memory 217656 kb
Host smart-c1632309-2477-46ec-be22-a18add1bdbf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2622173998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.2622173998
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.481522649
Short name T842
Test name
Test status
Simulation time 1638363961 ps
CPU time 39.16 seconds
Started Feb 29 02:05:17 PM PST 24
Finished Feb 29 02:05:57 PM PST 24
Peak memory 207340 kb
Host smart-0ccda456-373e-4a33-99f5-d7c6ed702d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=481522649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.481522649
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.3796387251
Short name T362
Test name
Test status
Simulation time 156859761 ps
CPU time 3.22 seconds
Started Feb 29 02:05:23 PM PST 24
Finished Feb 29 02:05:27 PM PST 24
Peak memory 207032 kb
Host smart-b39bc49b-b98d-4c30-8d62-f165ca64edc5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796387251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.3796387251
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.669011054
Short name T558
Test name
Test status
Simulation time 71535374 ps
CPU time 3.63 seconds
Started Feb 29 02:05:24 PM PST 24
Finished Feb 29 02:05:28 PM PST 24
Peak memory 206064 kb
Host smart-df63b3d9-fe33-42a2-af97-4c9e054ab677
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669011054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.669011054
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.2689436386
Short name T420
Test name
Test status
Simulation time 108120014 ps
CPU time 2.23 seconds
Started Feb 29 02:05:22 PM PST 24
Finished Feb 29 02:05:24 PM PST 24
Peak memory 207640 kb
Host smart-a8df3459-bbfe-4d14-92d3-782b2e68dd3e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2689436386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.2689436386
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.3208098341
Short name T426
Test name
Test status
Simulation time 537571151 ps
CPU time 11.35 seconds
Started Feb 29 02:05:22 PM PST 24
Finished Feb 29 02:05:34 PM PST 24
Peak memory 208888 kb
Host smart-53271e7e-449c-418b-b95d-bbef6172994f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208098341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.3208098341
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.3936484261
Short name T472
Test name
Test status
Simulation time 101280853 ps
CPU time 3.93 seconds
Started Feb 29 02:05:22 PM PST 24
Finished Feb 29 02:05:27 PM PST 24
Peak memory 205460 kb
Host smart-87367106-de3f-4712-b0e9-58b71f6f1051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936484261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.3936484261
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all_with_rand_reset.1919712382
Short name T44
Test name
Test status
Simulation time 762674768 ps
CPU time 12.69 seconds
Started Feb 29 02:05:21 PM PST 24
Finished Feb 29 02:05:35 PM PST 24
Peak memory 221980 kb
Host smart-1437ce0f-0364-49f8-8f4d-9821936d5e79
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919712382 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all_with_rand_reset.1919712382
Directory /workspace/49.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.1381582348
Short name T433
Test name
Test status
Simulation time 258370399 ps
CPU time 7.99 seconds
Started Feb 29 02:05:21 PM PST 24
Finished Feb 29 02:05:29 PM PST 24
Peak memory 207292 kb
Host smart-d044dcd7-3ecd-4ef9-9f05-631cc9f48c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381582348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.1381582348
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.1966497003
Short name T604
Test name
Test status
Simulation time 93444314 ps
CPU time 3.72 seconds
Started Feb 29 02:05:22 PM PST 24
Finished Feb 29 02:05:27 PM PST 24
Peak memory 209352 kb
Host smart-ee57df56-36a5-40c9-b2e2-769630197f12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966497003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.1966497003
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.2721058081
Short name T621
Test name
Test status
Simulation time 43025398 ps
CPU time 0.9 seconds
Started Feb 29 02:01:38 PM PST 24
Finished Feb 29 02:01:39 PM PST 24
Peak memory 205396 kb
Host smart-807831aa-9015-40db-8ecd-0e8727461f65
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721058081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.2721058081
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.1100434693
Short name T789
Test name
Test status
Simulation time 88689799 ps
CPU time 3.32 seconds
Started Feb 29 02:01:22 PM PST 24
Finished Feb 29 02:01:26 PM PST 24
Peak memory 213652 kb
Host smart-a21b7291-cebe-4492-b55a-da020433aa81
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1100434693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.1100434693
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.673836007
Short name T783
Test name
Test status
Simulation time 608119308 ps
CPU time 5.08 seconds
Started Feb 29 02:01:26 PM PST 24
Finished Feb 29 02:01:32 PM PST 24
Peak memory 214080 kb
Host smart-0b7a3995-7179-4cc2-bca9-361e01faa04e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673836007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.673836007
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.125425223
Short name T70
Test name
Test status
Simulation time 71116186 ps
CPU time 2.93 seconds
Started Feb 29 02:01:24 PM PST 24
Finished Feb 29 02:01:27 PM PST 24
Peak memory 206596 kb
Host smart-698f5822-fddd-446a-83e6-38a9d44588bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125425223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.125425223
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.2670567194
Short name T92
Test name
Test status
Simulation time 186935867 ps
CPU time 5.16 seconds
Started Feb 29 02:01:25 PM PST 24
Finished Feb 29 02:01:30 PM PST 24
Peak memory 208772 kb
Host smart-9c4215ef-c6e2-4d45-8668-dbaff5d6bbe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2670567194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.2670567194
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.3072504668
Short name T888
Test name
Test status
Simulation time 198412281 ps
CPU time 3.61 seconds
Started Feb 29 02:01:23 PM PST 24
Finished Feb 29 02:01:26 PM PST 24
Peak memory 209128 kb
Host smart-6d495d09-6484-4c09-b6bd-8be482a6439e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072504668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.3072504668
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.2089703536
Short name T796
Test name
Test status
Simulation time 500371649 ps
CPU time 2.76 seconds
Started Feb 29 02:01:25 PM PST 24
Finished Feb 29 02:01:28 PM PST 24
Peak memory 218852 kb
Host smart-3afbd988-ed07-42d9-b8d3-4faff20d97b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089703536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.2089703536
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.1213733383
Short name T568
Test name
Test status
Simulation time 503592274 ps
CPU time 4.75 seconds
Started Feb 29 02:01:25 PM PST 24
Finished Feb 29 02:01:30 PM PST 24
Peak memory 208340 kb
Host smart-56f1f4a2-d12a-4e6b-8e61-6cd64238d28e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1213733383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.1213733383
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.3013130978
Short name T343
Test name
Test status
Simulation time 22531263 ps
CPU time 1.88 seconds
Started Feb 29 02:01:22 PM PST 24
Finished Feb 29 02:01:24 PM PST 24
Peak memory 207452 kb
Host smart-ef936f36-37ab-4263-9e4e-8a8958654da2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3013130978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.3013130978
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.2448990125
Short name T754
Test name
Test status
Simulation time 84213288 ps
CPU time 4.26 seconds
Started Feb 29 02:01:23 PM PST 24
Finished Feb 29 02:01:27 PM PST 24
Peak memory 208008 kb
Host smart-fcb79875-f6d3-4456-88f7-e93bcf6a6322
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448990125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.2448990125
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.3468684864
Short name T742
Test name
Test status
Simulation time 67720731 ps
CPU time 2.56 seconds
Started Feb 29 02:01:26 PM PST 24
Finished Feb 29 02:01:28 PM PST 24
Peak memory 206096 kb
Host smart-705a1232-fd52-4869-a8a3-8d51ac0554df
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468684864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.3468684864
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.1595354887
Short name T83
Test name
Test status
Simulation time 546938005 ps
CPU time 3.76 seconds
Started Feb 29 02:01:23 PM PST 24
Finished Feb 29 02:01:26 PM PST 24
Peak memory 208332 kb
Host smart-dd6a1da2-a9c8-4a28-928c-e8a2b6538598
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1595354887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.1595354887
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.2406028565
Short name T810
Test name
Test status
Simulation time 697069125 ps
CPU time 12.19 seconds
Started Feb 29 02:01:24 PM PST 24
Finished Feb 29 02:01:36 PM PST 24
Peak memory 207976 kb
Host smart-777d1d15-ef3d-4ab0-9662-d18765f097ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406028565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.2406028565
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.2525731146
Short name T497
Test name
Test status
Simulation time 174278454 ps
CPU time 2.5 seconds
Started Feb 29 02:01:26 PM PST 24
Finished Feb 29 02:01:29 PM PST 24
Peak memory 205940 kb
Host smart-763b21ea-01d0-49ef-8f36-56510f2f4966
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525731146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.2525731146
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.3139173511
Short name T78
Test name
Test status
Simulation time 33406254315 ps
CPU time 274.31 seconds
Started Feb 29 02:01:39 PM PST 24
Finished Feb 29 02:06:13 PM PST 24
Peak memory 221860 kb
Host smart-d40996b1-eb10-4b59-a7a4-ec6fdeac8215
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139173511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.3139173511
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.776686994
Short name T613
Test name
Test status
Simulation time 684841959 ps
CPU time 7.66 seconds
Started Feb 29 02:01:24 PM PST 24
Finished Feb 29 02:01:31 PM PST 24
Peak memory 207876 kb
Host smart-34beb975-c397-47bf-87c8-7d58ca7023d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=776686994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.776686994
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.3181013047
Short name T37
Test name
Test status
Simulation time 367900458 ps
CPU time 1.6 seconds
Started Feb 29 02:01:38 PM PST 24
Finished Feb 29 02:01:40 PM PST 24
Peak memory 208844 kb
Host smart-306c65c9-222a-425d-9343-418fb64652e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3181013047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.3181013047
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.657643176
Short name T677
Test name
Test status
Simulation time 31624267 ps
CPU time 0.83 seconds
Started Feb 29 02:01:38 PM PST 24
Finished Feb 29 02:01:39 PM PST 24
Peak memory 205332 kb
Host smart-e55eba5b-b74e-4766-ab02-fd406ef43aca
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=657643176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.657643176
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.3604473097
Short name T266
Test name
Test status
Simulation time 194061998 ps
CPU time 3.88 seconds
Started Feb 29 02:01:38 PM PST 24
Finished Feb 29 02:01:42 PM PST 24
Peak memory 213696 kb
Host smart-0743d499-bab8-403d-aa9a-c81929155742
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3604473097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.3604473097
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.3319203091
Short name T356
Test name
Test status
Simulation time 354965458 ps
CPU time 2.41 seconds
Started Feb 29 02:01:37 PM PST 24
Finished Feb 29 02:01:39 PM PST 24
Peak memory 206412 kb
Host smart-2476eef0-5098-426b-95fb-d01355ceba7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3319203091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.3319203091
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.731758800
Short name T408
Test name
Test status
Simulation time 764722432 ps
CPU time 16.31 seconds
Started Feb 29 02:01:38 PM PST 24
Finished Feb 29 02:01:54 PM PST 24
Peak memory 217904 kb
Host smart-aec467db-0417-4d98-9d2f-e2851b664edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=731758800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.731758800
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.3143578036
Short name T276
Test name
Test status
Simulation time 155715538 ps
CPU time 5.87 seconds
Started Feb 29 02:01:41 PM PST 24
Finished Feb 29 02:01:47 PM PST 24
Peak memory 221784 kb
Host smart-b59387fa-7a76-433c-856d-21fbea4885da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143578036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.3143578036
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.2063466723
Short name T69
Test name
Test status
Simulation time 1353720526 ps
CPU time 7.48 seconds
Started Feb 29 02:01:38 PM PST 24
Finished Feb 29 02:01:45 PM PST 24
Peak memory 208848 kb
Host smart-9d7d2ee0-ad11-4326-86ad-a2c21691f9a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2063466723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.2063466723
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.4044357856
Short name T267
Test name
Test status
Simulation time 468089464 ps
CPU time 6.39 seconds
Started Feb 29 02:01:37 PM PST 24
Finished Feb 29 02:01:44 PM PST 24
Peak memory 209204 kb
Host smart-07ac8e5b-6328-4e6e-9fcf-79757de398ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044357856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.4044357856
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.2781296540
Short name T222
Test name
Test status
Simulation time 87888361 ps
CPU time 2.83 seconds
Started Feb 29 02:01:37 PM PST 24
Finished Feb 29 02:01:41 PM PST 24
Peak memory 206028 kb
Host smart-36b2d53b-2803-4262-92b6-7dac783e98b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781296540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.2781296540
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.79133584
Short name T832
Test name
Test status
Simulation time 177751789 ps
CPU time 3.8 seconds
Started Feb 29 02:01:45 PM PST 24
Finished Feb 29 02:01:50 PM PST 24
Peak memory 206096 kb
Host smart-5111be18-0fae-4408-a91d-8c90adb1078e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79133584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.79133584
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.2439096496
Short name T43
Test name
Test status
Simulation time 437334057 ps
CPU time 3.14 seconds
Started Feb 29 02:01:38 PM PST 24
Finished Feb 29 02:01:41 PM PST 24
Peak memory 206056 kb
Host smart-dcb426f2-3b32-4776-b198-42c5d92fd3bb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439096496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.2439096496
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.3161912156
Short name T612
Test name
Test status
Simulation time 150905875 ps
CPU time 4.87 seconds
Started Feb 29 02:01:38 PM PST 24
Finished Feb 29 02:01:43 PM PST 24
Peak memory 205940 kb
Host smart-f8273145-61ae-449d-9d12-6676ea478644
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161912156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.3161912156
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.3826796761
Short name T862
Test name
Test status
Simulation time 50017127 ps
CPU time 2.37 seconds
Started Feb 29 02:01:40 PM PST 24
Finished Feb 29 02:01:43 PM PST 24
Peak memory 208028 kb
Host smart-64cc97c6-edd5-4620-8958-a1760eb7e4cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826796761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.3826796761
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.817036434
Short name T505
Test name
Test status
Simulation time 205186200 ps
CPU time 2.87 seconds
Started Feb 29 02:01:40 PM PST 24
Finished Feb 29 02:01:43 PM PST 24
Peak memory 206168 kb
Host smart-64cdc90b-78ea-47fd-a923-31c92c27018b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817036434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.817036434
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.944309955
Short name T348
Test name
Test status
Simulation time 1393193253 ps
CPU time 14.27 seconds
Started Feb 29 02:01:41 PM PST 24
Finished Feb 29 02:01:56 PM PST 24
Peak memory 215400 kb
Host smart-30456fd3-fc99-42da-9801-1af0f86b1d66
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944309955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.944309955
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.2046965031
Short name T645
Test name
Test status
Simulation time 551304562 ps
CPU time 8.1 seconds
Started Feb 29 02:01:38 PM PST 24
Finished Feb 29 02:01:46 PM PST 24
Peak memory 207984 kb
Host smart-e3c082fc-74f2-43d0-a6d6-f37ca204c428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2046965031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.2046965031
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.3648380270
Short name T865
Test name
Test status
Simulation time 551288888 ps
CPU time 3.26 seconds
Started Feb 29 02:01:39 PM PST 24
Finished Feb 29 02:01:42 PM PST 24
Peak memory 208872 kb
Host smart-0855f1e2-6368-4909-bbe6-7a066e33a5e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648380270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.3648380270
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.2978853044
Short name T675
Test name
Test status
Simulation time 59831870 ps
CPU time 1.01 seconds
Started Feb 29 02:01:56 PM PST 24
Finished Feb 29 02:01:57 PM PST 24
Peak memory 205480 kb
Host smart-ef7b92e2-3a30-425b-b39d-b629ce84bbf1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978853044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.2978853044
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.39826916
Short name T126
Test name
Test status
Simulation time 123214898 ps
CPU time 3.98 seconds
Started Feb 29 02:01:56 PM PST 24
Finished Feb 29 02:02:00 PM PST 24
Peak memory 222092 kb
Host smart-e72992d9-057c-4a7b-9291-ceffc55b329c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=39826916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.39826916
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.2220119297
Short name T804
Test name
Test status
Simulation time 75450949 ps
CPU time 3.47 seconds
Started Feb 29 02:01:54 PM PST 24
Finished Feb 29 02:01:57 PM PST 24
Peak memory 217656 kb
Host smart-e66f4e0c-e005-4218-a198-5836ac7f6ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2220119297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.2220119297
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.3151633432
Short name T64
Test name
Test status
Simulation time 132267395 ps
CPU time 3.79 seconds
Started Feb 29 02:01:57 PM PST 24
Finished Feb 29 02:02:01 PM PST 24
Peak memory 208924 kb
Host smart-dc7e5c07-661a-486c-8a4a-ebbafeb81523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151633432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.3151633432
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.1402744053
Short name T87
Test name
Test status
Simulation time 70801853 ps
CPU time 4.44 seconds
Started Feb 29 02:01:59 PM PST 24
Finished Feb 29 02:02:04 PM PST 24
Peak memory 220776 kb
Host smart-b99d8b90-492a-487c-a98d-f3368d7c55a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402744053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.1402744053
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.3284395858
Short name T299
Test name
Test status
Simulation time 3511941604 ps
CPU time 9.4 seconds
Started Feb 29 02:01:56 PM PST 24
Finished Feb 29 02:02:05 PM PST 24
Peak memory 209760 kb
Host smart-7c8a30e3-d80e-4c13-a39e-7a4c970e3f4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284395858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.3284395858
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.1469481828
Short name T719
Test name
Test status
Simulation time 58514895 ps
CPU time 2.87 seconds
Started Feb 29 02:01:54 PM PST 24
Finished Feb 29 02:01:57 PM PST 24
Peak memory 213672 kb
Host smart-82c164f3-019a-4572-97fb-7d185f10b36e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469481828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.1469481828
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.3589901946
Short name T521
Test name
Test status
Simulation time 171004332 ps
CPU time 4.45 seconds
Started Feb 29 02:02:00 PM PST 24
Finished Feb 29 02:02:05 PM PST 24
Peak memory 209044 kb
Host smart-c8a96593-2551-4ec0-88b6-1a71fb14691b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589901946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.3589901946
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.4082869354
Short name T771
Test name
Test status
Simulation time 246857140 ps
CPU time 3.24 seconds
Started Feb 29 02:01:39 PM PST 24
Finished Feb 29 02:01:42 PM PST 24
Peak memory 205948 kb
Host smart-ec7211eb-f71c-409b-ab84-c88c15a3a0f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082869354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.4082869354
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.38173471
Short name T400
Test name
Test status
Simulation time 588362669 ps
CPU time 4.26 seconds
Started Feb 29 02:01:38 PM PST 24
Finished Feb 29 02:01:42 PM PST 24
Peak memory 206212 kb
Host smart-577216a9-95bf-42e7-b2be-262bb981b334
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38173471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.38173471
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.2623057470
Short name T459
Test name
Test status
Simulation time 169101872 ps
CPU time 2.64 seconds
Started Feb 29 02:01:39 PM PST 24
Finished Feb 29 02:01:42 PM PST 24
Peak memory 205868 kb
Host smart-b293f0a3-8db4-4987-ad28-bb6307ca1f37
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623057470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.2623057470
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.3829984938
Short name T208
Test name
Test status
Simulation time 249800416 ps
CPU time 2.9 seconds
Started Feb 29 02:01:54 PM PST 24
Finished Feb 29 02:01:57 PM PST 24
Peak memory 206052 kb
Host smart-f817671a-97f0-4275-9ec5-6941f1dfe30e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829984938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.3829984938
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.2213045049
Short name T646
Test name
Test status
Simulation time 401817176 ps
CPU time 3.54 seconds
Started Feb 29 02:02:00 PM PST 24
Finished Feb 29 02:02:03 PM PST 24
Peak memory 208444 kb
Host smart-33c58840-2976-46e7-b7a1-faf1230ee5d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2213045049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.2213045049
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.445016051
Short name T639
Test name
Test status
Simulation time 236465591 ps
CPU time 2.71 seconds
Started Feb 29 02:01:37 PM PST 24
Finished Feb 29 02:01:41 PM PST 24
Peak memory 207828 kb
Host smart-b6bd42d7-8f51-4c3e-8802-0aff7b262516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445016051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.445016051
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.638312877
Short name T58
Test name
Test status
Simulation time 709309200 ps
CPU time 8.56 seconds
Started Feb 29 02:01:56 PM PST 24
Finished Feb 29 02:02:06 PM PST 24
Peak memory 214680 kb
Host smart-53a6214e-cf32-4c28-b7c1-7d418ef90189
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638312877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.638312877
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.1313588934
Short name T280
Test name
Test status
Simulation time 565792108 ps
CPU time 9.9 seconds
Started Feb 29 02:01:57 PM PST 24
Finished Feb 29 02:02:07 PM PST 24
Peak memory 213712 kb
Host smart-cf4c9015-976c-4780-8294-73fc4c43505e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313588934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.1313588934
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.1694317870
Short name T221
Test name
Test status
Simulation time 39018576 ps
CPU time 2.02 seconds
Started Feb 29 02:01:55 PM PST 24
Finished Feb 29 02:01:57 PM PST 24
Peak memory 208840 kb
Host smart-5f7ec10d-ca04-4746-b2c1-da92ad842746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1694317870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.1694317870
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.2870492740
Short name T623
Test name
Test status
Simulation time 87336421 ps
CPU time 0.88 seconds
Started Feb 29 02:01:56 PM PST 24
Finished Feb 29 02:01:58 PM PST 24
Peak memory 205332 kb
Host smart-6ba9664a-9eb6-4504-93c8-6cacf17c346d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870492740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.2870492740
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.2288173578
Short name T860
Test name
Test status
Simulation time 124046205 ps
CPU time 3.5 seconds
Started Feb 29 02:01:55 PM PST 24
Finished Feb 29 02:01:58 PM PST 24
Peak memory 207856 kb
Host smart-6cb82225-d03c-4497-af3f-953a90e15cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288173578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.2288173578
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.1155964964
Short name T787
Test name
Test status
Simulation time 162384709 ps
CPU time 6.12 seconds
Started Feb 29 02:01:57 PM PST 24
Finished Feb 29 02:02:03 PM PST 24
Peak memory 216396 kb
Host smart-658a7634-ef54-4e3d-95ac-1b197942cb9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155964964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.1155964964
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.4055842291
Short name T257
Test name
Test status
Simulation time 222631951 ps
CPU time 10.81 seconds
Started Feb 29 02:02:02 PM PST 24
Finished Feb 29 02:02:14 PM PST 24
Peak memory 213620 kb
Host smart-82f45dd7-d1dd-4e0b-aac0-af0e773d9962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055842291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.4055842291
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.232195378
Short name T226
Test name
Test status
Simulation time 71744025 ps
CPU time 3 seconds
Started Feb 29 02:01:57 PM PST 24
Finished Feb 29 02:02:01 PM PST 24
Peak memory 217588 kb
Host smart-037cdc2d-7339-4fa7-87a0-c633eec1bf6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232195378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.232195378
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.362450356
Short name T768
Test name
Test status
Simulation time 199840677 ps
CPU time 2.89 seconds
Started Feb 29 02:01:55 PM PST 24
Finished Feb 29 02:01:58 PM PST 24
Peak memory 207792 kb
Host smart-6d680379-dcc9-4c42-b2f4-9f694a776365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=362450356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.362450356
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.3770059191
Short name T550
Test name
Test status
Simulation time 134746491 ps
CPU time 4.47 seconds
Started Feb 29 02:01:56 PM PST 24
Finished Feb 29 02:02:01 PM PST 24
Peak memory 207840 kb
Host smart-6b1639f4-3dfd-4c57-bde2-3ffbd990fde9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770059191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.3770059191
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.4263569700
Short name T782
Test name
Test status
Simulation time 412062294 ps
CPU time 2.95 seconds
Started Feb 29 02:01:56 PM PST 24
Finished Feb 29 02:02:00 PM PST 24
Peak memory 206024 kb
Host smart-0fbe294b-2dc2-411c-8240-9806c96bdb90
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263569700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.4263569700
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.140598057
Short name T703
Test name
Test status
Simulation time 515076954 ps
CPU time 5.29 seconds
Started Feb 29 02:01:56 PM PST 24
Finished Feb 29 02:02:02 PM PST 24
Peak memory 207804 kb
Host smart-ef3e0b33-dbed-4f3d-a9ac-b8b7dd50e911
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140598057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.140598057
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.889211373
Short name T737
Test name
Test status
Simulation time 58709143 ps
CPU time 2.12 seconds
Started Feb 29 02:01:57 PM PST 24
Finished Feb 29 02:01:59 PM PST 24
Peak memory 207896 kb
Host smart-0476763f-83b2-409b-9ed5-52564134ff6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=889211373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.889211373
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.3615655201
Short name T424
Test name
Test status
Simulation time 832813058 ps
CPU time 5.72 seconds
Started Feb 29 02:01:54 PM PST 24
Finished Feb 29 02:02:00 PM PST 24
Peak memory 205924 kb
Host smart-0af155b9-3673-4fdf-9777-68106a1bae64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615655201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.3615655201
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all_with_rand_reset.4265419849
Short name T316
Test name
Test status
Simulation time 2268837289 ps
CPU time 22.49 seconds
Started Feb 29 02:01:56 PM PST 24
Finished Feb 29 02:02:18 PM PST 24
Peak memory 222052 kb
Host smart-03a93cf1-aa55-407b-b337-e8356b95d638
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4265419849 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all_with_rand_reset.4265419849
Directory /workspace/8.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.1223797704
Short name T762
Test name
Test status
Simulation time 40129648 ps
CPU time 2.77 seconds
Started Feb 29 02:01:55 PM PST 24
Finished Feb 29 02:01:58 PM PST 24
Peak memory 206520 kb
Host smart-672285f6-656e-40ff-b6e2-969173889bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223797704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.1223797704
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.1727398904
Short name T617
Test name
Test status
Simulation time 102684443 ps
CPU time 1.21 seconds
Started Feb 29 02:01:55 PM PST 24
Finished Feb 29 02:01:57 PM PST 24
Peak memory 208844 kb
Host smart-ca3892f6-3740-4771-b63e-5f1bca9dbe14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727398904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.1727398904
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.1156546759
Short name T569
Test name
Test status
Simulation time 19807503 ps
CPU time 0.76 seconds
Started Feb 29 02:02:01 PM PST 24
Finished Feb 29 02:02:03 PM PST 24
Peak memory 205344 kb
Host smart-12be81ef-ab5b-4a48-a790-fa7a24dc7f40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1156546759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.1156546759
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.3025843075
Short name T411
Test name
Test status
Simulation time 41460116 ps
CPU time 3.36 seconds
Started Feb 29 02:01:56 PM PST 24
Finished Feb 29 02:02:01 PM PST 24
Peak memory 213696 kb
Host smart-ce042f26-b324-4fdf-bc12-8dee5b839686
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3025843075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.3025843075
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.3200359455
Short name T40
Test name
Test status
Simulation time 137154749 ps
CPU time 5.94 seconds
Started Feb 29 02:01:56 PM PST 24
Finished Feb 29 02:02:02 PM PST 24
Peak memory 217504 kb
Host smart-f1ed4e5e-2e97-411b-9fc0-bf8fa7739667
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3200359455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.3200359455
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.3026026554
Short name T731
Test name
Test status
Simulation time 757234623 ps
CPU time 3.81 seconds
Started Feb 29 02:01:56 PM PST 24
Finished Feb 29 02:02:01 PM PST 24
Peak memory 207684 kb
Host smart-8eba7c70-0fbd-4c93-89cc-de8c2e0b3d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026026554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.3026026554
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.2409721025
Short name T328
Test name
Test status
Simulation time 204743557 ps
CPU time 3.7 seconds
Started Feb 29 02:01:57 PM PST 24
Finished Feb 29 02:02:02 PM PST 24
Peak memory 208344 kb
Host smart-302d8c28-875e-4924-9f91-87552a507dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409721025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.2409721025
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.3880255369
Short name T553
Test name
Test status
Simulation time 1039732117 ps
CPU time 4.95 seconds
Started Feb 29 02:01:57 PM PST 24
Finished Feb 29 02:02:03 PM PST 24
Peak memory 213028 kb
Host smart-ae1e7ac0-e66e-44f3-86ad-2b6c13d19cda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880255369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.3880255369
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_random.3776934696
Short name T595
Test name
Test status
Simulation time 565962412 ps
CPU time 5.63 seconds
Started Feb 29 02:01:57 PM PST 24
Finished Feb 29 02:02:04 PM PST 24
Peak memory 207340 kb
Host smart-6f5c19e9-2090-47f5-acc1-0a4ff81fcad1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776934696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.3776934696
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.2593269506
Short name T473
Test name
Test status
Simulation time 232467064 ps
CPU time 3.12 seconds
Started Feb 29 02:01:55 PM PST 24
Finished Feb 29 02:01:59 PM PST 24
Peak memory 207904 kb
Host smart-c6d9c347-7591-4821-8c19-3308ab61c994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593269506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.2593269506
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.3662368102
Short name T605
Test name
Test status
Simulation time 1767011786 ps
CPU time 34.39 seconds
Started Feb 29 02:01:56 PM PST 24
Finished Feb 29 02:02:31 PM PST 24
Peak memory 207908 kb
Host smart-1d372940-a747-4dd4-a557-31144b220163
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662368102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.3662368102
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.426510449
Short name T837
Test name
Test status
Simulation time 255975732 ps
CPU time 4.09 seconds
Started Feb 29 02:01:56 PM PST 24
Finished Feb 29 02:02:01 PM PST 24
Peak memory 206016 kb
Host smart-fafecab5-a02c-4feb-a1f5-b00fd13615bc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=426510449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.426510449
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.2726334474
Short name T240
Test name
Test status
Simulation time 213534715 ps
CPU time 3.22 seconds
Started Feb 29 02:01:59 PM PST 24
Finished Feb 29 02:02:03 PM PST 24
Peak memory 207552 kb
Host smart-43440936-d19d-4482-be45-856a4dd76292
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726334474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.2726334474
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.2724426479
Short name T220
Test name
Test status
Simulation time 103423333 ps
CPU time 2.39 seconds
Started Feb 29 02:01:56 PM PST 24
Finished Feb 29 02:01:58 PM PST 24
Peak memory 213596 kb
Host smart-c63be8cd-c221-41a8-8a13-c467b8418423
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724426479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.2724426479
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.2808705312
Short name T603
Test name
Test status
Simulation time 13059790650 ps
CPU time 16.52 seconds
Started Feb 29 02:01:58 PM PST 24
Finished Feb 29 02:02:15 PM PST 24
Peak memory 207540 kb
Host smart-69c43207-fe4c-4243-8952-30c2027e78cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808705312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.2808705312
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.3482765731
Short name T68
Test name
Test status
Simulation time 2787270902 ps
CPU time 35.23 seconds
Started Feb 29 02:01:55 PM PST 24
Finished Feb 29 02:02:31 PM PST 24
Peak memory 215828 kb
Host smart-b1617d1a-4a48-42ae-92e6-95df3429aaa3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482765731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.3482765731
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.543380781
Short name T29
Test name
Test status
Simulation time 453098123 ps
CPU time 5.42 seconds
Started Feb 29 02:01:57 PM PST 24
Finished Feb 29 02:02:03 PM PST 24
Peak memory 209176 kb
Host smart-2724f9b9-221a-4d37-9df3-9a964161266f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543380781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.543380781
Directory /workspace/9.keymgr_sw_invalid_input/latest
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