Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
43.16	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	360	216	144	40.00

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	168	112	40.00	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11421

1

T1

11

T2

15

T3

17

auto[Attestation]

7908

1

T1

12

T2

4

T3

9

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2845	1			T1	5		T3	2		T4	3
auto[Aes]	3423	1			T1	3		T3	4		T13	16
auto[Kmac]	3493	1			T1	3		T3	5		T14	1
auto[Otbn]	3419	1			T1	3		T2	19		T3	6

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7718	1			T1	8		T2	8		T3	8
auto[OpGenId]	6149	1			T1	9		T3	9		T4	2
auto[OpGenSwOut]	6079	1			T1	5		T3	8		T4	2
auto[OpGenHwOut]	7101	1			T1	9		T2	19		T3	9
auto[OpDisable]	119	1			T44	1		T45	2		T46	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10064

1

T1

14

T2

8

T3

14

auto[OpDoneFail]

17102

1

T1

17

T2

19

T3

20

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6096	1			T1	5		T2	12		T3	1
auto[StInit]	4273	1			T1	2		T2	2		T3	5
auto[StCreatorRootKey]	3024	1			T1	4		T2	2		T3	6
auto[StOwnerIntKey]	2578	1			T1	4		T2	2		T3	5
auto[StOwnerKey]	2394	1			T1	4		T2	2		T3	1
auto[StDisabled]	7693	1			T1	12		T2	7		T3	16
auto[StInvalid]	1108	1			T189	8		T80	25		T87	25

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	168	112	40.00	168

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	315	1			T4	1		T15	2		T97	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	111	1			T15	1		T20	1		T45	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	79	1			T16	1		T45	1		T46	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	66	1			T16	1		T6	3		T47	3
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	68	1			T133	1		T45	1		T117	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	221	1			T1	1		T3	1		T133	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	33	1			T87	1		T190	2		T191	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	289	1			T4	1		T97	2		T51	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	122	1			T60	1		T51	1		T45	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	71	1			T96	1		T45	1		T108	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	73	1			T23	1		T133	1		T45	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	62	1			T24	1		T122	1		T99	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	221	1			T3	1		T96	1		T45	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	31	1			T80	1		T91	2		T192	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	336	1			T97	1		T60	3		T51	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	134	1			T20	1		T44	1		T46	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	78	1			T3	2		T33	1		T47	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	72	1			T193	1		T183	1		T194	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	57	1			T45	1		T62	1		T47	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	220	1			T1	1		T23	1		T24	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	41	1			T80	3		T87	1		T89	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	322	1			T15	1		T60	2		T45	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	116	1			T20	1		T44	1		T23	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	82	1			T60	1		T51	1		T62	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	56	1			T3	1		T51	1		T195	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	60	1			T24	1		T96	1		T6	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	193	1			T15	1		T23	1		T45	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	34	1			T80	2		T87	1		T191	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	56	1			T6	4		T47	4		T7	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	135	1			T41	1		T20	1		T133	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	77	1			T97	1		T24	1		T107	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	63	1			T96	1		T107	1		T56	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	56	1			T47	1		T125	1		T196	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	219	1			T1	1		T96	1		T45	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	34	1			T189	2		T80	1		T197	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	65	1			T7	1		T64	1		T100	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	117	1			T33	1		T20	3		T60	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	79	1			T14	1		T99	1		T54	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	71	1			T24	1		T6	1		T47	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	59	1			T108	1		T99	1		T6	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	206	1			T45	2		T6	6		T47	4
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	40	1			T89	1		T190	1		T191	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	51	1			T6	2		T47	2		T7	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	126	1			T20	2		T99	1		T21	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	67	1			T14	1		T96	1		T25	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	73	1			T3	1		T65	1		T6	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	41	1			T193	1		T175	1		T104	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	213	1			T1	1		T3	1		T133	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	39	1			T87	1		T89	1		T190	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	71	1			T6	3		T7	2		T64	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	128	1			T34	1		T33	1		T46	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	73	1			T24	1		T45	1		T107	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	48	1			T96	1		T120	1		T122	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	80	1			T60	1		T45	2		T107	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	201	1			T1	1		T3	1		T108	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	28	1			T87	1		T89	1		T190	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	250	1			T4	2		T97	2		T51	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	110	1			T3	1		T97	1		T23	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	62	1			T107	1		T108	1		T47	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	48	1			T45	1		T62	1		T65	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	64	1			T122	1		T7	2		T64	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	162	1			T45	1		T107	3		T122	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	42	1			T87	1		T190	2		T198	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	431	1			T1	1		T13	8		T15	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	129	1			T3	1		T17	1		T79	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	91	1			T13	1		T17	1		T41	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	112	1			T13	1		T16	2		T17	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	76	1			T119	1		T122	1		T47	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	264	1			T1	1		T3	1		T13	3
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	28	1			T80	1		T191	1		T91	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	476	1			T15	1		T60	1		T45	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	128	1			T199	1		T45	1		T108	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	93	1			T60	1		T199	1		T76	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	89	1			T16	1		T78	1		T199	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	83	1			T23	1		T6	1		T76	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	278	1			T78	2		T23	2		T96	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	34	1			T87	2		T192	1		T197	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	457	1			T1	2		T2	11		T4	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	131	1			T2	1		T121	1		T21	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	101	1			T3	1		T6	4		T47	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	85	1			T3	1		T16	1		T121	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	92	1			T96	1		T45	1		T62	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	285	1			T2	3		T45	1		T108	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	32	1			T80	1		T190	1		T192	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	62	1			T6	5		T47	1		T64	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	111	1			T1	1		T44	1		T122	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	69	1			T33	1		T44	1		T107	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	57	1			T1	1		T45	2		T99	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	59	1			T1	1		T54	2		T7	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	187	1			T15	1		T45	5		T61	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	29	1			T87	1		T190	1		T198	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	49	1			T6	2		T7	1		T64	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	122	1			T13	1		T14	1		T41	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	115	1			T16	1		T45	1		T200	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	82	1			T3	1		T41	1		T97	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	88	1			T13	1		T17	1		T79	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	300	1			T1	1		T13	1		T17	3
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	30	1			T80	2		T87	2		T190	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	37	1			T6	2		T7	2		T64	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	126	1			T78	1		T20	2		T108	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	100	1			T78	1		T44	1		T99	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	86	1			T16	1		T97	1		T23	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	95	1			T1	1		T78	1		T23	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	290	1			T3	1		T15	1		T78	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	30	1			T80	1		T87	2		T190	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	46	1			T6	2		T7	1		T64	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	135	1			T4	1		T41	1		T20	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	108	1			T2	1		T16	1		T121	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	81	1			T2	1		T107	1		T75	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	75	1			T2	1		T121	1		T62	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	264	1			T2	1		T3	2		T44	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	35	1			T189	1		T91	1		T197	1

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	202	1			T16	2		T133	1		T45	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	691	1			T1	1		T3	1		T4	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	192	1			T133	1		T96	1		T45	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	677	1			T3	1		T4	1		T97	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	192	1			T3	2		T33	1		T45	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	746	1			T1	1		T97	1		T20	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	186	1			T3	1		T60	1		T51	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	677	1			T15	2		T20	1		T60	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	184	1			T97	1		T24	1		T96	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	456	1			T1	1		T41	1		T20	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	200	1			T14	1		T24	1		T108	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	437	1			T33	1		T20	3		T60	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	164	1			T3	1		T14	1		T65	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	446	1			T1	1		T3	1		T20	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	178	1			T60	1		T45	3		T107	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	451	1			T1	1		T3	1		T34	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	165	1			T45	1		T107	1		T108	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	573	1			T3	1		T4	2		T97	3
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	266	1			T13	2		T16	2		T17	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	865	1			T1	2		T3	2		T13	11
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	247	1			T16	1		T78	1		T60	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	934	1			T15	1		T78	2		T60	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	261	1			T3	2		T16	1		T45	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	922	1			T1	2		T2	15		T4	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	164	1			T1	2		T33	1		T44	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	410	1			T1	1		T15	1		T44	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	270	1			T3	1		T13	1		T16	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	516	1			T1	1		T13	2		T14	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	266	1			T1	1		T16	1		T78	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	498	1			T3	1		T15	1		T78	3
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	247	1			T2	3		T16	1		T107	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	497	1			T2	1		T3	2		T4	1