Unified Coverage Report :: Group Instance : key_version

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6938

1

T1

10

T3

9

T4

1

auto[1]

248

1

T107

8

T108

2

T123

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	2903	1			T1	4		T3	5		T16	1
auto[134217728:268435455]	162	1			T45	1		T61	1		T21	1
auto[268435456:402653183]	163	1			T1	1		T96	1		T42	1
auto[402653184:536870911]	136	1			T60	1		T23	1		T65	1
auto[536870912:671088639]	153	1			T65	1		T47	2		T124	1
auto[671088640:805306367]	129	1			T65	1		T6	2		T47	2
auto[805306368:939524095]	138	1			T3	1		T16	1		T41	1
auto[939524096:1073741823]	151	1			T1	1		T41	1		T23	1
auto[1073741824:1207959551]	155	1			T44	1		T96	2		T45	1
auto[1207959552:1342177279]	126	1			T3	1		T45	1		T99	1
auto[1342177280:1476395007]	127	1			T20	1		T44	1		T23	1
auto[1476395008:1610612735]	133	1			T96	1		T108	1		T61	1
auto[1610612736:1744830463]	126	1			T3	1		T97	1		T60	1
auto[1744830464:1879048191]	130	1			T4	1		T44	1		T23	1
auto[1879048192:2013265919]	135	1			T16	1		T51	1		T50	1
auto[2013265920:2147483647]	139	1			T20	2		T44	1		T23	1
auto[2147483648:2281701375]	144	1			T1	1		T23	1		T24	1
auto[2281701376:2415919103]	119	1			T45	1		T54	1		T7	1
auto[2415919104:2550136831]	133	1			T24	1		T96	1		T45	2
auto[2550136832:2684354559]	141	1			T1	1		T23	1		T45	1
auto[2684354560:2818572287]	138	1			T60	1		T96	1		T45	1
auto[2818572288:2952790015]	147	1			T96	1		T107	1		T62	1
auto[2952790016:3087007743]	138	1			T51	1		T65	1		T21	2
auto[3087007744:3221225471]	119	1			T60	1		T23	1		T24	1
auto[3221225472:3355443199]	149	1			T20	1		T60	1		T45	1
auto[3355443200:3489660927]	143	1			T20	2		T96	1		T99	1
auto[3489660928:3623878655]	117	1			T23	1		T45	3		T107	1
auto[3623878656:3758096383]	130	1			T96	1		T45	1		T107	1
auto[3758096384:3892314111]	143	1			T1	1		T97	1		T24	1
auto[3892314112:4026531839]	115	1			T96	1		T45	1		T107	1
auto[4026531840:4160749567]	145	1			T1	1		T3	1		T60	1
auto[4160749568:4294967295]	159	1			T20	1		T60	1		T45	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	2893	1			T1	4		T3	5		T16	1
auto[0:134217727]	auto[1]	10	1			T123	1		T363	1		T333	1
auto[134217728:268435455]	auto[0]	157	1			T45	1		T61	1		T21	1
auto[134217728:268435455]	auto[1]	5	1			T124	1		T175	1		T332	1
auto[268435456:402653183]	auto[0]	150	1			T1	1		T96	1		T42	1
auto[268435456:402653183]	auto[1]	13	1			T107	1		T226	2		T346	1
auto[402653184:536870911]	auto[0]	129	1			T60	1		T23	1		T65	1
auto[402653184:536870911]	auto[1]	7	1			T389	1		T394	2		T392	1
auto[536870912:671088639]	auto[0]	144	1			T65	1		T47	2		T7	1
auto[536870912:671088639]	auto[1]	9	1			T124	1		T332	1		T333	1
auto[671088640:805306367]	auto[0]	125	1			T65	1		T6	2		T47	2
auto[671088640:805306367]	auto[1]	4	1			T363	1		T232	1		T401	1
auto[805306368:939524095]	auto[0]	131	1			T3	1		T16	1		T41	1
auto[805306368:939524095]	auto[1]	7	1			T108	1		T272	1		T376	1
auto[939524096:1073741823]	auto[0]	145	1			T1	1		T41	1		T23	1
auto[939524096:1073741823]	auto[1]	6	1			T125	2		T402	1		T403	1
auto[1073741824:1207959551]	auto[0]	152	1			T44	1		T96	2		T45	1
auto[1073741824:1207959551]	auto[1]	3	1			T226	1		T363	1		T397	1
auto[1207959552:1342177279]	auto[0]	120	1			T3	1		T45	1		T99	1
auto[1207959552:1342177279]	auto[1]	6	1			T346	1		T225	1		T393	1
auto[1342177280:1476395007]	auto[0]	118	1			T20	1		T44	1		T23	1
auto[1342177280:1476395007]	auto[1]	9	1			T226	1		T292	1		T276	1
auto[1476395008:1610612735]	auto[0]	128	1			T96	1		T108	1		T61	1
auto[1476395008:1610612735]	auto[1]	5	1			T292	1		T232	1		T389	1
auto[1610612736:1744830463]	auto[0]	118	1			T3	1		T97	1		T60	1
auto[1610612736:1744830463]	auto[1]	8	1			T124	1		T366	1		T268	1
auto[1744830464:1879048191]	auto[0]	123	1			T4	1		T44	1		T23	1
auto[1744830464:1879048191]	auto[1]	7	1			T107	2		T333	1		T359	1
auto[1879048192:2013265919]	auto[0]	130	1			T16	1		T51	1		T50	1
auto[1879048192:2013265919]	auto[1]	5	1			T366	1		T268	1		T272	1
auto[2013265920:2147483647]	auto[0]	126	1			T20	2		T44	1		T23	1
auto[2013265920:2147483647]	auto[1]	13	1			T107	2		T123	1		T125	1
auto[2147483648:2281701375]	auto[0]	139	1			T1	1		T23	1		T24	1
auto[2147483648:2281701375]	auto[1]	5	1			T226	1		T332	1		T404	1
auto[2281701376:2415919103]	auto[0]	111	1			T45	1		T54	1		T7	1
auto[2281701376:2415919103]	auto[1]	8	1			T268	1		T276	1		T272	1
auto[2415919104:2550136831]	auto[0]	125	1			T24	1		T96	1		T45	2
auto[2415919104:2550136831]	auto[1]	8	1			T124	1		T125	1		T346	1
auto[2550136832:2684354559]	auto[0]	134	1			T1	1		T23	1		T45	1
auto[2550136832:2684354559]	auto[1]	7	1			T268	1		T276	1		T359	1
auto[2684354560:2818572287]	auto[0]	129	1			T60	1		T96	1		T45	1
auto[2684354560:2818572287]	auto[1]	9	1			T232	1		T389	1		T343	1
auto[2818572288:2952790015]	auto[0]	139	1			T96	1		T62	1		T65	1
auto[2818572288:2952790015]	auto[1]	8	1			T107	1		T292	2		T363	1
auto[2952790016:3087007743]	auto[0]	129	1			T51	1		T65	1		T21	2
auto[2952790016:3087007743]	auto[1]	9	1			T124	1		T226	1		T268	1
auto[3087007744:3221225471]	auto[0]	110	1			T60	1		T23	1		T24	1
auto[3087007744:3221225471]	auto[1]	9	1			T226	1		T346	1		T332	1
auto[3221225472:3355443199]	auto[0]	134	1			T20	1		T60	1		T45	1
auto[3221225472:3355443199]	auto[1]	15	1			T107	2		T332	1		T376	1
auto[3355443200:3489660927]	auto[0]	130	1			T20	2		T96	1		T99	1
auto[3355443200:3489660927]	auto[1]	13	1			T358	1		T333	1		T225	1
auto[3489660928:3623878655]	auto[0]	113	1			T23	1		T45	3		T107	1
auto[3489660928:3623878655]	auto[1]	4	1			T124	1		T125	1		T292	1
auto[3623878656:3758096383]	auto[0]	125	1			T96	1		T45	1		T107	1
auto[3623878656:3758096383]	auto[1]	5	1			T332	1		T359	1		T232	1
auto[3758096384:3892314111]	auto[0]	133	1			T1	1		T97	1		T24	1
auto[3758096384:3892314111]	auto[1]	10	1			T124	2		T346	1		T225	1
auto[3892314112:4026531839]	auto[0]	110	1			T96	1		T45	1		T107	1
auto[3892314112:4026531839]	auto[1]	5	1			T358	1		T363	1		T232	1
auto[4026531840:4160749567]	auto[0]	136	1			T1	1		T3	1		T60	1
auto[4026531840:4160749567]	auto[1]	9	1			T108	1		T123	1		T332	1
auto[4160749568:4294967295]	auto[0]	152	1			T20	1		T60	1		T45	2
auto[4160749568:4294967295]	auto[1]	7	1			T123	1		T333	2		T403	1