Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.85 99.07 98.14 98.72 100.00 99.11 98.41 91.54


Total test records in report: 1074
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T1007 /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.1683605530 Mar 03 02:03:46 PM PST 24 Mar 03 02:03:48 PM PST 24 51499163 ps
T1008 /workspace/coverage/cover_reg_top/16.keymgr_intr_test.1643861320 Mar 03 02:03:46 PM PST 24 Mar 03 02:03:46 PM PST 24 7725124 ps
T150 /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.3224052772 Mar 03 02:03:47 PM PST 24 Mar 03 02:04:00 PM PST 24 875979306 ps
T1009 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.1537075211 Mar 03 02:03:25 PM PST 24 Mar 03 02:03:33 PM PST 24 570400958 ps
T1010 /workspace/coverage/cover_reg_top/49.keymgr_intr_test.1911051890 Mar 03 02:04:02 PM PST 24 Mar 03 02:04:04 PM PST 24 8642226 ps
T1011 /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.227514018 Mar 03 02:03:20 PM PST 24 Mar 03 02:03:23 PM PST 24 513354464 ps
T1012 /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.3398953414 Mar 03 02:03:14 PM PST 24 Mar 03 02:03:19 PM PST 24 263368314 ps
T151 /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.2980082249 Mar 03 02:02:59 PM PST 24 Mar 03 02:03:05 PM PST 24 226271164 ps
T1013 /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.2564001587 Mar 03 02:03:48 PM PST 24 Mar 03 02:03:53 PM PST 24 168616550 ps
T1014 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.2050962927 Mar 03 02:03:21 PM PST 24 Mar 03 02:03:25 PM PST 24 135968465 ps
T1015 /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.2092052447 Mar 03 02:03:21 PM PST 24 Mar 03 02:03:29 PM PST 24 960377055 ps
T1016 /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.2329093121 Mar 03 02:03:12 PM PST 24 Mar 03 02:03:15 PM PST 24 419232847 ps
T1017 /workspace/coverage/cover_reg_top/46.keymgr_intr_test.358826195 Mar 03 02:04:00 PM PST 24 Mar 03 02:04:01 PM PST 24 11431255 ps
T1018 /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.1437265497 Mar 03 02:02:58 PM PST 24 Mar 03 02:03:00 PM PST 24 75660605 ps
T1019 /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.3409629282 Mar 03 02:03:28 PM PST 24 Mar 03 02:03:30 PM PST 24 330676465 ps
T1020 /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.1588420556 Mar 03 02:03:47 PM PST 24 Mar 03 02:03:48 PM PST 24 23718109 ps
T1021 /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.3427300911 Mar 03 02:03:47 PM PST 24 Mar 03 02:03:49 PM PST 24 99611494 ps
T142 /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.3965425805 Mar 03 02:03:27 PM PST 24 Mar 03 02:03:50 PM PST 24 1220023716 ps
T1022 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.2654613366 Mar 03 02:03:27 PM PST 24 Mar 03 02:03:34 PM PST 24 637123206 ps
T1023 /workspace/coverage/cover_reg_top/11.keymgr_intr_test.2697915019 Mar 03 02:03:28 PM PST 24 Mar 03 02:03:29 PM PST 24 53754160 ps
T156 /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.1318501670 Mar 03 02:03:44 PM PST 24 Mar 03 02:03:52 PM PST 24 438808343 ps
T1024 /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.1769652377 Mar 03 02:03:28 PM PST 24 Mar 03 02:03:31 PM PST 24 228897771 ps
T1025 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.379542484 Mar 03 02:03:53 PM PST 24 Mar 03 02:04:16 PM PST 24 1063178612 ps
T1026 /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.651403293 Mar 03 02:03:47 PM PST 24 Mar 03 02:03:57 PM PST 24 1736191139 ps
T1027 /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.2086292367 Mar 03 02:03:25 PM PST 24 Mar 03 02:03:29 PM PST 24 52090049 ps
T1028 /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.4030936534 Mar 03 02:03:06 PM PST 24 Mar 03 02:03:18 PM PST 24 867988084 ps
T1029 /workspace/coverage/cover_reg_top/45.keymgr_intr_test.1902650796 Mar 03 02:04:02 PM PST 24 Mar 03 02:04:04 PM PST 24 41483563 ps
T1030 /workspace/coverage/cover_reg_top/6.keymgr_intr_test.496542470 Mar 03 02:03:18 PM PST 24 Mar 03 02:03:19 PM PST 24 13116293 ps
T1031 /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.2577078459 Mar 03 02:03:36 PM PST 24 Mar 03 02:03:43 PM PST 24 364945357 ps
T1032 /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.3336610539 Mar 03 02:03:57 PM PST 24 Mar 03 02:03:59 PM PST 24 16638692 ps
T1033 /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.195290041 Mar 03 02:03:22 PM PST 24 Mar 03 02:03:25 PM PST 24 85622777 ps
T1034 /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.3320733657 Mar 03 02:03:26 PM PST 24 Mar 03 02:03:35 PM PST 24 440569105 ps
T1035 /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.1163483250 Mar 03 02:03:05 PM PST 24 Mar 03 02:03:10 PM PST 24 68446145 ps
T1036 /workspace/coverage/cover_reg_top/29.keymgr_intr_test.3803226636 Mar 03 02:03:54 PM PST 24 Mar 03 02:03:56 PM PST 24 35989796 ps
T1037 /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.2564391696 Mar 03 02:03:28 PM PST 24 Mar 03 02:03:29 PM PST 24 35977497 ps
T1038 /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.2508909519 Mar 03 02:03:28 PM PST 24 Mar 03 02:03:32 PM PST 24 614682180 ps
T1039 /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.61564657 Mar 03 02:03:55 PM PST 24 Mar 03 02:03:59 PM PST 24 199309385 ps
T1040 /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.2927036502 Mar 03 02:03:06 PM PST 24 Mar 03 02:03:08 PM PST 24 65163660 ps
T1041 /workspace/coverage/cover_reg_top/14.keymgr_intr_test.3066197632 Mar 03 02:03:45 PM PST 24 Mar 03 02:03:46 PM PST 24 10365535 ps
T1042 /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.1957823732 Mar 03 02:03:07 PM PST 24 Mar 03 02:03:10 PM PST 24 153341285 ps
T1043 /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.3017873096 Mar 03 02:03:17 PM PST 24 Mar 03 02:03:18 PM PST 24 113331263 ps
T1044 /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.2997668970 Mar 03 02:03:15 PM PST 24 Mar 03 02:03:17 PM PST 24 14084366 ps
T1045 /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.1625453904 Mar 03 02:03:00 PM PST 24 Mar 03 02:03:07 PM PST 24 319409629 ps
T1046 /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.627573926 Mar 03 02:03:15 PM PST 24 Mar 03 02:03:16 PM PST 24 28763316 ps
T140 /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.4197605138 Mar 03 02:03:05 PM PST 24 Mar 03 02:03:10 PM PST 24 396180802 ps
T1047 /workspace/coverage/cover_reg_top/3.keymgr_intr_test.3486612771 Mar 03 02:03:07 PM PST 24 Mar 03 02:03:08 PM PST 24 10701347 ps
T155 /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.1587470831 Mar 03 02:03:07 PM PST 24 Mar 03 02:03:18 PM PST 24 767884956 ps
T1048 /workspace/coverage/cover_reg_top/26.keymgr_intr_test.1363238963 Mar 03 02:03:57 PM PST 24 Mar 03 02:03:59 PM PST 24 30015423 ps
T1049 /workspace/coverage/cover_reg_top/39.keymgr_intr_test.2705674253 Mar 03 02:03:54 PM PST 24 Mar 03 02:03:56 PM PST 24 32560903 ps
T1050 /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.759570408 Mar 03 02:03:38 PM PST 24 Mar 03 02:03:39 PM PST 24 28223865 ps
T1051 /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.566511472 Mar 03 02:03:37 PM PST 24 Mar 03 02:03:40 PM PST 24 102443442 ps
T1052 /workspace/coverage/cover_reg_top/22.keymgr_intr_test.3941068040 Mar 03 02:03:54 PM PST 24 Mar 03 02:03:56 PM PST 24 19224187 ps
T1053 /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.1612688126 Mar 03 02:03:18 PM PST 24 Mar 03 02:03:23 PM PST 24 160639052 ps
T1054 /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.2457869895 Mar 03 02:03:30 PM PST 24 Mar 03 02:03:32 PM PST 24 58953993 ps
T1055 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.709986052 Mar 03 02:03:20 PM PST 24 Mar 03 02:03:25 PM PST 24 417868695 ps
T1056 /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.4122934452 Mar 03 02:03:26 PM PST 24 Mar 03 02:03:28 PM PST 24 80884298 ps
T1057 /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.544439092 Mar 03 02:03:19 PM PST 24 Mar 03 02:03:22 PM PST 24 136258136 ps
T1058 /workspace/coverage/cover_reg_top/2.keymgr_intr_test.3678192173 Mar 03 02:03:06 PM PST 24 Mar 03 02:03:07 PM PST 24 10272172 ps
T1059 /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.3454143031 Mar 03 02:03:47 PM PST 24 Mar 03 02:03:49 PM PST 24 148076874 ps
T1060 /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.2450816035 Mar 03 02:03:28 PM PST 24 Mar 03 02:03:29 PM PST 24 53523398 ps
T1061 /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.2199418503 Mar 03 02:03:05 PM PST 24 Mar 03 02:03:13 PM PST 24 591205047 ps
T1062 /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.1102028644 Mar 03 02:03:06 PM PST 24 Mar 03 02:03:08 PM PST 24 134651104 ps
T1063 /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.2613468592 Mar 03 02:03:25 PM PST 24 Mar 03 02:03:27 PM PST 24 14880804 ps
T1064 /workspace/coverage/cover_reg_top/20.keymgr_intr_test.3880891920 Mar 03 02:03:56 PM PST 24 Mar 03 02:03:58 PM PST 24 169258778 ps
T1065 /workspace/coverage/cover_reg_top/28.keymgr_intr_test.22079013 Mar 03 02:03:53 PM PST 24 Mar 03 02:03:54 PM PST 24 32918868 ps
T1066 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.3329625489 Mar 03 02:03:20 PM PST 24 Mar 03 02:03:26 PM PST 24 268341249 ps
T1067 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.3021315624 Mar 03 02:03:46 PM PST 24 Mar 03 02:03:50 PM PST 24 157320965 ps
T1068 /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.377074136 Mar 03 02:03:47 PM PST 24 Mar 03 02:03:55 PM PST 24 191371819 ps
T1069 /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.1918502753 Mar 03 02:03:36 PM PST 24 Mar 03 02:03:38 PM PST 24 139503859 ps
T1070 /workspace/coverage/cover_reg_top/38.keymgr_intr_test.2307271547 Mar 03 02:03:54 PM PST 24 Mar 03 02:03:56 PM PST 24 21512358 ps
T1071 /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.3518105710 Mar 03 02:03:20 PM PST 24 Mar 03 02:03:28 PM PST 24 1648845450 ps
T1072 /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.1318965361 Mar 03 02:03:36 PM PST 24 Mar 03 02:03:40 PM PST 24 53462865 ps
T1073 /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.451320913 Mar 03 02:03:38 PM PST 24 Mar 03 02:03:41 PM PST 24 70111407 ps
T1074 /workspace/coverage/cover_reg_top/47.keymgr_intr_test.1043966954 Mar 03 02:04:00 PM PST 24 Mar 03 02:04:01 PM PST 24 10350544 ps

Test location /workspace/coverage/default/17.keymgr_random.2162248972
Short name T1
Test name
Test status
Simulation time 129760622 ps
CPU time 2.66 seconds
Started Mar 03 02:34:56 PM PST 24
Finished Mar 03 02:35:01 PM PST 24
Peak memory 208908 kb
Host smart-720fc92b-1f75-467c-b7e0-8f55365e21ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162248972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.2162248972
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.2505111564
Short name T6
Test name
Test status
Simulation time 3243235073 ps
CPU time 103.32 seconds
Started Mar 03 02:35:06 PM PST 24
Finished Mar 03 02:36:49 PM PST 24
Peak memory 222040 kb
Host smart-1ca71d03-f8b9-48ef-9c4b-2a66360aa192
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2505111564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.2505111564
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.1427753411
Short name T5
Test name
Test status
Simulation time 1686736148 ps
CPU time 31.34 seconds
Started Mar 03 02:33:31 PM PST 24
Finished Mar 03 02:34:03 PM PST 24
Peak memory 235852 kb
Host smart-99175997-35df-4e1d-98b0-88ca211c5998
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1427753411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.1427753411
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/39.keymgr_stress_all_with_rand_reset.3599551382
Short name T100
Test name
Test status
Simulation time 552457972 ps
CPU time 18.88 seconds
Started Mar 03 02:36:09 PM PST 24
Finished Mar 03 02:36:29 PM PST 24
Peak memory 219996 kb
Host smart-3b5fa3bc-0697-455a-af09-290c9dc6641d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3599551382 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_reset.3599551382
Directory /workspace/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.4087181760
Short name T47
Test name
Test status
Simulation time 8959128073 ps
CPU time 28.6 seconds
Started Mar 03 02:34:56 PM PST 24
Finished Mar 03 02:35:27 PM PST 24
Peak memory 215124 kb
Host smart-ae16457c-4037-45b8-963b-134ae43e9448
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087181760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.4087181760
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.954964259
Short name T60
Test name
Test status
Simulation time 49293398 ps
CPU time 3.44 seconds
Started Mar 03 02:36:10 PM PST 24
Finished Mar 03 02:36:14 PM PST 24
Peak memory 220012 kb
Host smart-704742ae-0f0c-4650-9e79-7677650be81d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954964259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.954964259
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.2328700313
Short name T8
Test name
Test status
Simulation time 124852481 ps
CPU time 2.96 seconds
Started Mar 03 02:34:17 PM PST 24
Finished Mar 03 02:34:21 PM PST 24
Peak memory 219420 kb
Host smart-5adfff0b-7720-4b85-8f91-e0c748608b21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328700313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.2328700313
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.3869537930
Short name T125
Test name
Test status
Simulation time 1069811253 ps
CPU time 13.71 seconds
Started Mar 03 02:35:51 PM PST 24
Finished Mar 03 02:36:07 PM PST 24
Peak memory 215180 kb
Host smart-74efbd46-8499-4e4d-8351-4dc54e416ed9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3869537930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.3869537930
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.727195707
Short name T202
Test name
Test status
Simulation time 2227329856 ps
CPU time 45.28 seconds
Started Mar 03 02:36:13 PM PST 24
Finished Mar 03 02:36:59 PM PST 24
Peak memory 214708 kb
Host smart-05bd8c69-949a-4bcf-a6cf-a0f6ea6021b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=727195707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.727195707
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.3706928331
Short name T20
Test name
Test status
Simulation time 178335602 ps
CPU time 5.68 seconds
Started Mar 03 02:35:44 PM PST 24
Finished Mar 03 02:35:50 PM PST 24
Peak memory 208556 kb
Host smart-fd46252b-6b5e-4a3a-a64a-165950897ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3706928331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.3706928331
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.3091592599
Short name T102
Test name
Test status
Simulation time 321311806 ps
CPU time 3.88 seconds
Started Mar 03 02:03:38 PM PST 24
Finished Mar 03 02:03:42 PM PST 24
Peak memory 214100 kb
Host smart-fbac5601-df7b-4d4f-9b3e-bbacf60b1b36
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091592599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.3091592599
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.3108914798
Short name T43
Test name
Test status
Simulation time 9249511416 ps
CPU time 58.36 seconds
Started Mar 03 02:33:45 PM PST 24
Finished Mar 03 02:34:44 PM PST 24
Peak memory 216376 kb
Host smart-934ff648-8620-4ac3-9cec-5cb7827c193b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3108914798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.3108914798
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.1666291878
Short name T346
Test name
Test status
Simulation time 6453280911 ps
CPU time 51.08 seconds
Started Mar 03 02:34:25 PM PST 24
Finished Mar 03 02:35:16 PM PST 24
Peak memory 214736 kb
Host smart-55c768bf-ed4e-456e-9000-53b79690b19a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1666291878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.1666291878
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_stress_all_with_rand_reset.537110124
Short name T104
Test name
Test status
Simulation time 1550255858 ps
CPU time 24.09 seconds
Started Mar 03 02:36:18 PM PST 24
Finished Mar 03 02:36:42 PM PST 24
Peak memory 222124 kb
Host smart-8ba4d5bc-8aa7-4e6d-84bf-47180e91e2ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=537110124 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all_with_rand_reset.537110124
Directory /workspace/41.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.1646697739
Short name T389
Test name
Test status
Simulation time 131252452 ps
CPU time 7.43 seconds
Started Mar 03 02:36:12 PM PST 24
Finished Mar 03 02:36:20 PM PST 24
Peak memory 214316 kb
Host smart-3f3bd6cf-6ed3-4664-89f4-3cfb92e5c866
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1646697739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.1646697739
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.3909480416
Short name T80
Test name
Test status
Simulation time 4712218379 ps
CPU time 63.14 seconds
Started Mar 03 02:35:10 PM PST 24
Finished Mar 03 02:36:13 PM PST 24
Peak memory 230256 kb
Host smart-379e767c-4e7d-4784-be01-dec240e2c7bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909480416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.3909480416
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.25566260
Short name T45
Test name
Test status
Simulation time 348730564 ps
CPU time 14.94 seconds
Started Mar 03 02:35:30 PM PST 24
Finished Mar 03 02:35:45 PM PST 24
Peak memory 218944 kb
Host smart-a7aa6921-e1c4-4de9-b60f-2e7b1feb9b63
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25566260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.25566260
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.2555730388
Short name T397
Test name
Test status
Simulation time 5345830254 ps
CPU time 75.96 seconds
Started Mar 03 02:34:52 PM PST 24
Finished Mar 03 02:36:09 PM PST 24
Peak memory 222108 kb
Host smart-02e3e1f9-4126-404a-a9e1-1f613bc4822a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2555730388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.2555730388
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.3451603361
Short name T134
Test name
Test status
Simulation time 1754061619 ps
CPU time 42.92 seconds
Started Mar 03 02:03:46 PM PST 24
Finished Mar 03 02:04:29 PM PST 24
Peak memory 214936 kb
Host smart-4ad34e6b-47fe-48ee-bc9c-7762a9c81184
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3451603361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.3451603361
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.966593810
Short name T333
Test name
Test status
Simulation time 4719833425 ps
CPU time 128.75 seconds
Started Mar 03 02:35:37 PM PST 24
Finished Mar 03 02:37:46 PM PST 24
Peak memory 221984 kb
Host smart-9d043b90-9d5d-45b0-a1d8-d62b358ba748
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=966593810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.966593810
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.1303329370
Short name T18
Test name
Test status
Simulation time 745026169 ps
CPU time 6.44 seconds
Started Mar 03 02:34:17 PM PST 24
Finished Mar 03 02:34:23 PM PST 24
Peak memory 220928 kb
Host smart-84dc3858-7568-46c4-8925-a65aaaf1b340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1303329370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.1303329370
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.4280487939
Short name T183
Test name
Test status
Simulation time 16543324178 ps
CPU time 69.6 seconds
Started Mar 03 02:36:01 PM PST 24
Finished Mar 03 02:37:11 PM PST 24
Peak memory 216056 kb
Host smart-fb14e3c4-b4a4-4d45-89c6-80d7d60694b0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280487939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.4280487939
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.278192433
Short name T363
Test name
Test status
Simulation time 255658979 ps
CPU time 13.55 seconds
Started Mar 03 02:34:05 PM PST 24
Finished Mar 03 02:34:20 PM PST 24
Peak memory 213876 kb
Host smart-bae91d49-f38c-4f34-a225-a7d45c4c7d9c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=278192433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.278192433
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.4154084118
Short name T22
Test name
Test status
Simulation time 1648988210 ps
CPU time 20.94 seconds
Started Mar 03 02:34:20 PM PST 24
Finished Mar 03 02:34:41 PM PST 24
Peak memory 220108 kb
Host smart-0f70d2a9-a538-4961-8cfd-42ef77edc011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154084118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.4154084118
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.3759404311
Short name T59
Test name
Test status
Simulation time 441311016 ps
CPU time 4.94 seconds
Started Mar 03 02:34:24 PM PST 24
Finished Mar 03 02:34:30 PM PST 24
Peak memory 209612 kb
Host smart-d4da8908-9e0a-4ae7-b7dd-bd2d360c27ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3759404311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.3759404311
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.2721100011
Short name T106
Test name
Test status
Simulation time 229823865 ps
CPU time 2.43 seconds
Started Mar 03 02:03:00 PM PST 24
Finished Mar 03 02:03:02 PM PST 24
Peak memory 214040 kb
Host smart-d1199469-f79f-480f-a468-40142931ea60
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2721100011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.2721100011
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.589653158
Short name T28
Test name
Test status
Simulation time 52583449 ps
CPU time 3.42 seconds
Started Mar 03 02:33:59 PM PST 24
Finished Mar 03 02:34:02 PM PST 24
Peak memory 207908 kb
Host smart-d1059917-1308-483d-8de3-f2eda1a6d059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=589653158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.589653158
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.2537405854
Short name T14
Test name
Test status
Simulation time 170115921 ps
CPU time 2.5 seconds
Started Mar 03 02:33:58 PM PST 24
Finished Mar 03 02:34:01 PM PST 24
Peak memory 209484 kb
Host smart-b7e4f06c-3442-4127-818a-80b88a65b296
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537405854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.2537405854
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.3780614066
Short name T204
Test name
Test status
Simulation time 3010051768 ps
CPU time 53.04 seconds
Started Mar 03 02:33:32 PM PST 24
Finished Mar 03 02:34:25 PM PST 24
Peak memory 215540 kb
Host smart-32c12a32-3f9b-4615-8068-0f2102b36647
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780614066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.3780614066
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.453457683
Short name T123
Test name
Test status
Simulation time 179827187 ps
CPU time 3.55 seconds
Started Mar 03 02:36:26 PM PST 24
Finished Mar 03 02:36:30 PM PST 24
Peak memory 214448 kb
Host smart-6ce3da37-bbc0-4350-a7c6-551529bc9d2f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=453457683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.453457683
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.2072241648
Short name T157
Test name
Test status
Simulation time 552706602 ps
CPU time 6.42 seconds
Started Mar 03 02:35:51 PM PST 24
Finished Mar 03 02:36:00 PM PST 24
Peak memory 217452 kb
Host smart-e60c507b-a962-48d6-9432-98a949e97149
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2072241648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.2072241648
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.355779835
Short name T197
Test name
Test status
Simulation time 1057698469 ps
CPU time 9.73 seconds
Started Mar 03 02:36:15 PM PST 24
Finished Mar 03 02:36:25 PM PST 24
Peak memory 210228 kb
Host smart-7ddd7a21-63e4-4013-833d-50c730455cd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355779835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.355779835
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.2400596795
Short name T362
Test name
Test status
Simulation time 419588511 ps
CPU time 12.1 seconds
Started Mar 03 02:35:58 PM PST 24
Finished Mar 03 02:36:11 PM PST 24
Peak memory 213876 kb
Host smart-0403669d-8d42-4e88-b002-6b7672c80ae0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2400596795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.2400596795
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_stress_all_with_rand_reset.3044783542
Short name T112
Test name
Test status
Simulation time 213558568 ps
CPU time 7.84 seconds
Started Mar 03 02:33:32 PM PST 24
Finished Mar 03 02:33:40 PM PST 24
Peak memory 222112 kb
Host smart-bec670d6-b8b4-4c7a-a455-8ba3c98928f9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044783542 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all_with_rand_reset.3044783542
Directory /workspace/0.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.2352281332
Short name T86
Test name
Test status
Simulation time 167919326 ps
CPU time 4.89 seconds
Started Mar 03 02:35:49 PM PST 24
Finished Mar 03 02:35:55 PM PST 24
Peak memory 209108 kb
Host smart-9c28b51b-499e-46b2-9dc3-543926605df8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352281332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.2352281332
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.696977995
Short name T212
Test name
Test status
Simulation time 4782131892 ps
CPU time 84.67 seconds
Started Mar 03 02:34:22 PM PST 24
Finished Mar 03 02:35:48 PM PST 24
Peak memory 216928 kb
Host smart-2a1e9fc9-088c-4dff-a9b3-96b62f1dbbdc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=696977995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.696977995
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.3694344089
Short name T65
Test name
Test status
Simulation time 1792470245 ps
CPU time 9.06 seconds
Started Mar 03 02:35:51 PM PST 24
Finished Mar 03 02:36:02 PM PST 24
Peak memory 218152 kb
Host smart-ae5f8987-f0b1-489c-9f90-853289488a62
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694344089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.3694344089
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.1258169628
Short name T424
Test name
Test status
Simulation time 25970390 ps
CPU time 0.77 seconds
Started Mar 03 02:34:41 PM PST 24
Finished Mar 03 02:34:42 PM PST 24
Peak memory 205528 kb
Host smart-942cc7ca-b764-48ea-bfd0-1b5f552f16c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258169628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.1258169628
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.572873347
Short name T124
Test name
Test status
Simulation time 447338907 ps
CPU time 6.83 seconds
Started Mar 03 02:36:14 PM PST 24
Finished Mar 03 02:36:21 PM PST 24
Peak memory 213884 kb
Host smart-dd2a50fb-973b-41d4-b71e-6f10efd6520a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=572873347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.572873347
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.1755374678
Short name T137
Test name
Test status
Simulation time 245416038 ps
CPU time 10.24 seconds
Started Mar 03 02:03:14 PM PST 24
Finished Mar 03 02:03:25 PM PST 24
Peak memory 213704 kb
Host smart-4e174d0c-b75e-41fd-982e-df7d44fe9526
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1755374678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.1755374678
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.2331933603
Short name T70
Test name
Test status
Simulation time 1090974319 ps
CPU time 16.21 seconds
Started Mar 03 02:34:10 PM PST 24
Finished Mar 03 02:34:26 PM PST 24
Peak memory 215832 kb
Host smart-3dc7284a-dcb8-47aa-83af-f8cf0a75a51f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2331933603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.2331933603
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.1329946905
Short name T89
Test name
Test status
Simulation time 163161317 ps
CPU time 3.24 seconds
Started Mar 03 02:34:42 PM PST 24
Finished Mar 03 02:34:46 PM PST 24
Peak memory 213796 kb
Host smart-dd479f71-032c-41c9-b349-b18adfa4f683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329946905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.1329946905
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.3257989226
Short name T249
Test name
Test status
Simulation time 493683406 ps
CPU time 23.96 seconds
Started Mar 03 02:35:55 PM PST 24
Finished Mar 03 02:36:19 PM PST 24
Peak memory 215776 kb
Host smart-82fa9942-5bf2-4b35-adec-8b6d8c52ba64
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257989226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.3257989226
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.2447238066
Short name T92
Test name
Test status
Simulation time 68888577 ps
CPU time 2.43 seconds
Started Mar 03 02:35:14 PM PST 24
Finished Mar 03 02:35:16 PM PST 24
Peak memory 218696 kb
Host smart-3def18ee-3af0-4cff-b582-b9e7c08f9184
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447238066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.2447238066
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.3230824132
Short name T873
Test name
Test status
Simulation time 162628340 ps
CPU time 6.73 seconds
Started Mar 03 02:33:40 PM PST 24
Finished Mar 03 02:33:47 PM PST 24
Peak memory 213744 kb
Host smart-04e8cf5e-799c-4316-91a2-82275d619feb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3230824132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.3230824132
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.1180784297
Short name T236
Test name
Test status
Simulation time 164019090 ps
CPU time 4.21 seconds
Started Mar 03 02:35:49 PM PST 24
Finished Mar 03 02:35:53 PM PST 24
Peak memory 209936 kb
Host smart-fc373ef4-63eb-4960-a362-241456078507
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180784297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.1180784297
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.40575776
Short name T141
Test name
Test status
Simulation time 1832552521 ps
CPU time 15.87 seconds
Started Mar 03 02:02:59 PM PST 24
Finished Mar 03 02:03:14 PM PST 24
Peak memory 213804 kb
Host smart-b5e8b288-2f9b-4171-9803-81ce870f8fd0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40575776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err.40575776
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.3228696793
Short name T27
Test name
Test status
Simulation time 121121385 ps
CPU time 5.71 seconds
Started Mar 03 02:35:45 PM PST 24
Finished Mar 03 02:35:51 PM PST 24
Peak memory 221056 kb
Host smart-4146aa7e-2335-4afa-bef4-10a9cf7c0122
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228696793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.3228696793
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.1234904933
Short name T163
Test name
Test status
Simulation time 56119111 ps
CPU time 2.92 seconds
Started Mar 03 02:33:40 PM PST 24
Finished Mar 03 02:33:43 PM PST 24
Peak memory 216096 kb
Host smart-c80a14fb-80ea-4abf-94f2-9cfd238403da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234904933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.1234904933
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.3232088713
Short name T50
Test name
Test status
Simulation time 199190282 ps
CPU time 3.41 seconds
Started Mar 03 02:35:05 PM PST 24
Finished Mar 03 02:35:09 PM PST 24
Peak memory 222140 kb
Host smart-126ba055-006b-4b54-adb2-c230143b8a29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3232088713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.3232088713
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.3501823081
Short name T294
Test name
Test status
Simulation time 381099309 ps
CPU time 5.31 seconds
Started Mar 03 02:34:20 PM PST 24
Finished Mar 03 02:34:26 PM PST 24
Peak memory 221964 kb
Host smart-7a4a9e3c-c4dc-439d-a865-52d0d26b4412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501823081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.3501823081
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.1724796518
Short name T168
Test name
Test status
Simulation time 445401540 ps
CPU time 13.76 seconds
Started Mar 03 02:35:24 PM PST 24
Finished Mar 03 02:35:38 PM PST 24
Peak memory 222216 kb
Host smart-d4a97e56-80fa-4604-9a22-44c82de433f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724796518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.1724796518
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.3519781820
Short name T147
Test name
Test status
Simulation time 12673864870 ps
CPU time 47.54 seconds
Started Mar 03 02:35:47 PM PST 24
Finished Mar 03 02:36:35 PM PST 24
Peak memory 219448 kb
Host smart-38c4156c-2a1f-46a8-8a81-99c108e83601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3519781820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.3519781820
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.4037203978
Short name T153
Test name
Test status
Simulation time 571744684 ps
CPU time 11.6 seconds
Started Mar 03 02:03:12 PM PST 24
Finished Mar 03 02:03:24 PM PST 24
Peak memory 208984 kb
Host smart-21e14850-af15-4526-942b-83eb74b8b968
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037203978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.4037203978
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.763236857
Short name T166
Test name
Test status
Simulation time 58283011 ps
CPU time 2.83 seconds
Started Mar 03 02:36:39 PM PST 24
Finished Mar 03 02:36:42 PM PST 24
Peak memory 216888 kb
Host smart-46aa1079-c074-40db-b241-b3464eaceae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763236857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.763236857
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.3054040482
Short name T217
Test name
Test status
Simulation time 663138688 ps
CPU time 34.81 seconds
Started Mar 03 02:34:41 PM PST 24
Finished Mar 03 02:35:16 PM PST 24
Peak memory 222012 kb
Host smart-8996c82a-815e-4084-9252-7484220a2189
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054040482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.3054040482
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.2368498150
Short name T107
Test name
Test status
Simulation time 544846695 ps
CPU time 16.23 seconds
Started Mar 03 02:35:14 PM PST 24
Finished Mar 03 02:35:30 PM PST 24
Peak memory 214700 kb
Host smart-0ab968e5-c9b0-4b91-8563-376b6f6ba47f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2368498150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.2368498150
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.187366380
Short name T344
Test name
Test status
Simulation time 163495529 ps
CPU time 3.2 seconds
Started Mar 03 02:33:58 PM PST 24
Finished Mar 03 02:34:02 PM PST 24
Peak memory 214492 kb
Host smart-68dec76d-afcb-4f4f-8eef-b9caa02eab7d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=187366380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.187366380
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.1889792848
Short name T989
Test name
Test status
Simulation time 257838061 ps
CPU time 5.48 seconds
Started Mar 03 02:03:00 PM PST 24
Finished Mar 03 02:03:05 PM PST 24
Peak memory 214088 kb
Host smart-4d9e2b4c-674e-47de-b880-95afdb8e23cd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1889792848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.1889792848
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.1818125389
Short name T161
Test name
Test status
Simulation time 409980409 ps
CPU time 11.68 seconds
Started Mar 03 02:36:28 PM PST 24
Finished Mar 03 02:36:40 PM PST 24
Peak memory 216192 kb
Host smart-afbea733-97a6-428a-875b-7305501764a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1818125389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.1818125389
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.167591547
Short name T319
Test name
Test status
Simulation time 3500189363 ps
CPU time 8.97 seconds
Started Mar 03 02:35:07 PM PST 24
Finished Mar 03 02:35:16 PM PST 24
Peak memory 213856 kb
Host smart-5d2ba3aa-5e36-440b-a9a4-8b36dd4543b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167591547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.167591547
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.2000800377
Short name T23
Test name
Test status
Simulation time 219428490 ps
CPU time 6.43 seconds
Started Mar 03 02:35:11 PM PST 24
Finished Mar 03 02:35:18 PM PST 24
Peak memory 207972 kb
Host smart-bb207770-1c15-4507-8c45-e380bb065b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000800377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.2000800377
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.3455295962
Short name T215
Test name
Test status
Simulation time 21820037039 ps
CPU time 134.49 seconds
Started Mar 03 02:36:09 PM PST 24
Finished Mar 03 02:38:23 PM PST 24
Peak memory 215588 kb
Host smart-ea5b9999-a801-460e-8ce9-2e57316e9053
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3455295962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.3455295962
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.2410268233
Short name T187
Test name
Test status
Simulation time 12570058864 ps
CPU time 76.29 seconds
Started Mar 03 02:36:31 PM PST 24
Finished Mar 03 02:37:48 PM PST 24
Peak memory 215780 kb
Host smart-464eca3c-db30-4ec5-af9e-305b24b2365f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410268233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.2410268233
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.668518096
Short name T325
Test name
Test status
Simulation time 162480968 ps
CPU time 3.06 seconds
Started Mar 03 02:36:26 PM PST 24
Finished Mar 03 02:36:30 PM PST 24
Peak memory 208768 kb
Host smart-accdd6f4-07fb-4972-84f2-65301a3a0c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668518096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.668518096
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.1287019858
Short name T361
Test name
Test status
Simulation time 1096275733 ps
CPU time 6.23 seconds
Started Mar 03 02:36:35 PM PST 24
Finished Mar 03 02:36:41 PM PST 24
Peak memory 206044 kb
Host smart-cc8ae3f6-a2e5-40c4-9a6f-954865481a62
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287019858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.1287019858
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.148138139
Short name T162
Test name
Test status
Simulation time 279149339 ps
CPU time 4.51 seconds
Started Mar 03 02:35:12 PM PST 24
Finished Mar 03 02:35:17 PM PST 24
Peak memory 222240 kb
Host smart-d8ede521-7337-4a84-8257-96f4d4f60725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148138139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.148138139
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.3193938973
Short name T152
Test name
Test status
Simulation time 2382296560 ps
CPU time 9.02 seconds
Started Mar 03 02:34:42 PM PST 24
Finished Mar 03 02:34:51 PM PST 24
Peak memory 210348 kb
Host smart-40583db8-ffa2-4496-a66b-428149a25ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193938973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.3193938973
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.1806863539
Short name T159
Test name
Test status
Simulation time 550951626 ps
CPU time 4.21 seconds
Started Mar 03 02:35:59 PM PST 24
Finished Mar 03 02:36:04 PM PST 24
Peak memory 222168 kb
Host smart-21ce1261-3fc1-42b4-8f0e-0666d4a8f573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806863539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.1806863539
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.1123412017
Short name T280
Test name
Test status
Simulation time 217900080 ps
CPU time 4.15 seconds
Started Mar 03 02:34:23 PM PST 24
Finished Mar 03 02:34:29 PM PST 24
Peak memory 213836 kb
Host smart-ed8aa838-5a97-46ea-ba9a-c937be9e931e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123412017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.1123412017
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.1491203657
Short name T394
Test name
Test status
Simulation time 1219360867 ps
CPU time 17.66 seconds
Started Mar 03 02:34:45 PM PST 24
Finished Mar 03 02:35:03 PM PST 24
Peak memory 214908 kb
Host smart-1aa00ef5-bf59-4234-be6e-1c5cd749e698
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1491203657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.1491203657
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_random.4244640391
Short name T285
Test name
Test status
Simulation time 257809801 ps
CPU time 3.8 seconds
Started Mar 03 02:34:54 PM PST 24
Finished Mar 03 02:34:59 PM PST 24
Peak memory 209280 kb
Host smart-1b2e0844-b9e3-4a74-a494-145e81d1c997
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244640391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.4244640391
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.2041559961
Short name T225
Test name
Test status
Simulation time 129344278 ps
CPU time 2.94 seconds
Started Mar 03 02:34:58 PM PST 24
Finished Mar 03 02:35:06 PM PST 24
Peak memory 214528 kb
Host smart-410d5c26-c840-4251-98c2-73578ce4c293
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2041559961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.2041559961
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.1159841909
Short name T233
Test name
Test status
Simulation time 463437565 ps
CPU time 3.94 seconds
Started Mar 03 02:35:21 PM PST 24
Finished Mar 03 02:35:25 PM PST 24
Peak memory 213872 kb
Host smart-ed22f36e-7262-41a4-a611-9d11ee0dee70
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1159841909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.1159841909
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.571221032
Short name T339
Test name
Test status
Simulation time 274369306 ps
CPU time 4.76 seconds
Started Mar 03 02:35:35 PM PST 24
Finished Mar 03 02:35:39 PM PST 24
Peak memory 221912 kb
Host smart-2c2c46b0-f83d-406e-b22a-a1f00c0a1b1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571221032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.571221032
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.2396132293
Short name T368
Test name
Test status
Simulation time 374244352 ps
CPU time 5.38 seconds
Started Mar 03 02:35:45 PM PST 24
Finished Mar 03 02:35:51 PM PST 24
Peak memory 213732 kb
Host smart-8f9daee2-f27c-4037-9210-f1157df500a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2396132293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.2396132293
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.4099515435
Short name T238
Test name
Test status
Simulation time 19031135079 ps
CPU time 89.61 seconds
Started Mar 03 02:36:15 PM PST 24
Finished Mar 03 02:37:45 PM PST 24
Peak memory 231480 kb
Host smart-bfe6d5bd-256f-4fcf-bc0e-98fd106950d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099515435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.4099515435
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.2980082249
Short name T151
Test name
Test status
Simulation time 226271164 ps
CPU time 6.33 seconds
Started Mar 03 02:02:59 PM PST 24
Finished Mar 03 02:03:05 PM PST 24
Peak memory 209108 kb
Host smart-1e369662-e3a1-4f04-a49b-5be526065e88
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980082249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err
.2980082249
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.3065557678
Short name T138
Test name
Test status
Simulation time 2554575137 ps
CPU time 59.14 seconds
Started Mar 03 02:03:27 PM PST 24
Finished Mar 03 02:04:27 PM PST 24
Peak memory 222788 kb
Host smart-8fd0f191-9b00-4501-90b3-59baacfa38f3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065557678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_er
r.3065557678
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.2770611734
Short name T148
Test name
Test status
Simulation time 382822434 ps
CPU time 12.93 seconds
Started Mar 03 02:03:37 PM PST 24
Finished Mar 03 02:03:50 PM PST 24
Peak memory 208796 kb
Host smart-b0578faa-4374-4c3d-a8c5-8488fa742eec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2770611734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er
r.2770611734
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.153296933
Short name T154
Test name
Test status
Simulation time 831397776 ps
CPU time 18.45 seconds
Started Mar 03 02:03:43 PM PST 24
Finished Mar 03 02:04:03 PM PST 24
Peak memory 208952 kb
Host smart-45141d83-c67c-4622-8bc5-744e82c4abc9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153296933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_err
.153296933
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.4197605138
Short name T140
Test name
Test status
Simulation time 396180802 ps
CPU time 5.53 seconds
Started Mar 03 02:03:05 PM PST 24
Finished Mar 03 02:03:10 PM PST 24
Peak memory 208836 kb
Host smart-d4ad818a-2d12-4f6a-b775-888f29385b15
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4197605138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err
.4197605138
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.3300578298
Short name T19
Test name
Test status
Simulation time 59243058 ps
CPU time 2.81 seconds
Started Mar 03 02:35:10 PM PST 24
Finished Mar 03 02:35:13 PM PST 24
Peak memory 222224 kb
Host smart-cc0d7f66-a22c-4e78-aa63-110b9ac04ba0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300578298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.3300578298
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.2249851514
Short name T160
Test name
Test status
Simulation time 607351789 ps
CPU time 5.41 seconds
Started Mar 03 02:35:44 PM PST 24
Finished Mar 03 02:35:50 PM PST 24
Peak memory 222092 kb
Host smart-70d919ba-2801-422e-bc8e-c8afc20f3f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2249851514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.2249851514
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.2298191380
Short name T165
Test name
Test status
Simulation time 522687590 ps
CPU time 5.44 seconds
Started Mar 03 02:36:00 PM PST 24
Finished Mar 03 02:36:07 PM PST 24
Peak memory 217336 kb
Host smart-fc4bf78a-0f10-451f-aa44-c33aed81fe74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298191380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.2298191380
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.490389379
Short name T167
Test name
Test status
Simulation time 142797101 ps
CPU time 4.01 seconds
Started Mar 03 02:36:24 PM PST 24
Finished Mar 03 02:36:28 PM PST 24
Peak memory 216544 kb
Host smart-321637da-ea9d-409d-a099-9f76a3837dda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=490389379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.490389379
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.500754871
Short name T357
Test name
Test status
Simulation time 226759397 ps
CPU time 3.31 seconds
Started Mar 03 02:34:45 PM PST 24
Finished Mar 03 02:34:48 PM PST 24
Peak memory 207768 kb
Host smart-e3664861-4fb8-4634-8303-ac445e934967
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500754871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.500754871
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.3747279035
Short name T395
Test name
Test status
Simulation time 145081523 ps
CPU time 2.92 seconds
Started Mar 03 02:34:40 PM PST 24
Finished Mar 03 02:34:43 PM PST 24
Peak memory 213880 kb
Host smart-cb3d5b94-088a-4056-bc8f-aacb1d354ec7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3747279035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.3747279035
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.3855068036
Short name T321
Test name
Test status
Simulation time 6475389263 ps
CPU time 25.17 seconds
Started Mar 03 02:34:40 PM PST 24
Finished Mar 03 02:35:06 PM PST 24
Peak memory 214036 kb
Host smart-fbad9d24-1c7b-47e8-8c7e-a220e2ed21d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855068036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.3855068036
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.859405611
Short name T51
Test name
Test status
Simulation time 98484840 ps
CPU time 3.18 seconds
Started Mar 03 02:34:43 PM PST 24
Finished Mar 03 02:34:47 PM PST 24
Peak memory 213788 kb
Host smart-e2958af3-45a6-4573-92b3-317275fc0d8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=859405611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.859405611
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.1220485435
Short name T262
Test name
Test status
Simulation time 212379604 ps
CPU time 4.44 seconds
Started Mar 03 02:34:56 PM PST 24
Finished Mar 03 02:35:03 PM PST 24
Peak memory 208352 kb
Host smart-c813d232-fcd0-41e2-be9a-fece50e76b81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1220485435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.1220485435
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.4285704430
Short name T203
Test name
Test status
Simulation time 111586075 ps
CPU time 5.64 seconds
Started Mar 03 02:34:53 PM PST 24
Finished Mar 03 02:35:00 PM PST 24
Peak memory 213832 kb
Host smart-7d545a8f-a652-4b86-86f9-3bcc22ec977e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4285704430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.4285704430
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.362791562
Short name T108
Test name
Test status
Simulation time 68241522 ps
CPU time 3.06 seconds
Started Mar 03 02:35:06 PM PST 24
Finished Mar 03 02:35:09 PM PST 24
Peak memory 213828 kb
Host smart-4ead93e7-44eb-4444-8793-2b50cf82e6b8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=362791562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.362791562
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.1316731061
Short name T257
Test name
Test status
Simulation time 194122449 ps
CPU time 3.64 seconds
Started Mar 03 02:35:00 PM PST 24
Finished Mar 03 02:35:08 PM PST 24
Peak memory 210088 kb
Host smart-4ed0aabe-b2da-409b-aca4-e18313deed95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316731061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.1316731061
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.278543977
Short name T349
Test name
Test status
Simulation time 129015056 ps
CPU time 2.94 seconds
Started Mar 03 02:35:10 PM PST 24
Finished Mar 03 02:35:13 PM PST 24
Peak memory 214828 kb
Host smart-535cbd90-c3a8-4988-9f2a-939180b729e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=278543977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.278543977
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.3974050354
Short name T186
Test name
Test status
Simulation time 14302216023 ps
CPU time 307.51 seconds
Started Mar 03 02:35:25 PM PST 24
Finished Mar 03 02:40:32 PM PST 24
Peak memory 219776 kb
Host smart-420e8785-6cbf-46dd-9502-db3578babd7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974050354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.3974050354
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.3681189938
Short name T328
Test name
Test status
Simulation time 862345251 ps
CPU time 20.44 seconds
Started Mar 03 02:35:44 PM PST 24
Finished Mar 03 02:36:05 PM PST 24
Peak memory 221896 kb
Host smart-94734cb2-8cd1-4120-81f4-ac55652def14
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681189938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.3681189938
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.1098860832
Short name T269
Test name
Test status
Simulation time 419212243 ps
CPU time 16.52 seconds
Started Mar 03 02:36:02 PM PST 24
Finished Mar 03 02:36:19 PM PST 24
Peak memory 222064 kb
Host smart-fc93e726-d923-493f-aba9-fbd78e4e5280
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098860832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.1098860832
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.3753276907
Short name T279
Test name
Test status
Simulation time 221537100 ps
CPU time 5.69 seconds
Started Mar 03 02:36:10 PM PST 24
Finished Mar 03 02:36:16 PM PST 24
Peak memory 213784 kb
Host smart-4c7fcce8-1658-4188-872f-6399b3da3a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753276907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.3753276907
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.4114977082
Short name T318
Test name
Test status
Simulation time 6978429976 ps
CPU time 38.11 seconds
Started Mar 03 02:36:22 PM PST 24
Finished Mar 03 02:37:01 PM PST 24
Peak memory 222048 kb
Host smart-282cfbc6-dfb6-4f91-a6e9-89ca441fda81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4114977082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.4114977082
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.2251137107
Short name T224
Test name
Test status
Simulation time 576305343 ps
CPU time 6.7 seconds
Started Mar 03 02:34:06 PM PST 24
Finished Mar 03 02:34:13 PM PST 24
Peak memory 213868 kb
Host smart-71038c8b-aafd-47eb-a10d-b94b5d4f11b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251137107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.2251137107
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.2738496402
Short name T158
Test name
Test status
Simulation time 68876202 ps
CPU time 3.72 seconds
Started Mar 03 02:34:55 PM PST 24
Finished Mar 03 02:35:01 PM PST 24
Peak memory 217292 kb
Host smart-2e7a7cf2-c5fd-42f5-a5b0-3d7df68587c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738496402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.2738496402
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.3068812366
Short name T169
Test name
Test status
Simulation time 680174933 ps
CPU time 4.27 seconds
Started Mar 03 02:36:05 PM PST 24
Finished Mar 03 02:36:09 PM PST 24
Peak memory 216792 kb
Host smart-e52a1121-3890-45fc-9b31-8171868019ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3068812366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.3068812366
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.1625453904
Short name T1045
Test name
Test status
Simulation time 319409629 ps
CPU time 7.25 seconds
Started Mar 03 02:03:00 PM PST 24
Finished Mar 03 02:03:07 PM PST 24
Peak memory 205692 kb
Host smart-0ee15ee7-347e-4618-8305-22ece77cc683
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625453904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.1
625453904
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.2898499358
Short name T173
Test name
Test status
Simulation time 661105941 ps
CPU time 16.69 seconds
Started Mar 03 02:02:59 PM PST 24
Finished Mar 03 02:03:16 PM PST 24
Peak memory 205680 kb
Host smart-8a6d0871-d6ec-49ba-b33a-1e92fcd36f14
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898499358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.2
898499358
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.1437265497
Short name T1018
Test name
Test status
Simulation time 75660605 ps
CPU time 1.17 seconds
Started Mar 03 02:02:58 PM PST 24
Finished Mar 03 02:03:00 PM PST 24
Peak memory 205608 kb
Host smart-396bfc55-99b3-4262-a20c-011956fee289
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1437265497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.1
437265497
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.1386140721
Short name T909
Test name
Test status
Simulation time 29510199 ps
CPU time 1.17 seconds
Started Mar 03 02:02:59 PM PST 24
Finished Mar 03 02:03:00 PM PST 24
Peak memory 213796 kb
Host smart-d1e77c66-3a14-46a1-8c74-a074ce3d61f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386140721 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.1386140721
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.1409569366
Short name T985
Test name
Test status
Simulation time 47628577 ps
CPU time 1.2 seconds
Started Mar 03 02:03:06 PM PST 24
Finished Mar 03 02:03:07 PM PST 24
Peak memory 205364 kb
Host smart-1522e1bb-981e-4cf8-ad43-b8cc49733337
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409569366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.1409569366
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.2824611892
Short name T924
Test name
Test status
Simulation time 11080851 ps
CPU time 0.88 seconds
Started Mar 03 02:03:00 PM PST 24
Finished Mar 03 02:03:01 PM PST 24
Peak memory 205344 kb
Host smart-ee4c8ad0-0896-46eb-bc39-854f61029084
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2824611892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.2824611892
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.4164880080
Short name T979
Test name
Test status
Simulation time 72703757 ps
CPU time 2.73 seconds
Started Mar 03 02:03:00 PM PST 24
Finished Mar 03 02:03:02 PM PST 24
Peak memory 205600 kb
Host smart-4e7ca73c-8615-4c23-9259-7f19db12447e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164880080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.4164880080
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.2199418503
Short name T1061
Test name
Test status
Simulation time 591205047 ps
CPU time 7.95 seconds
Started Mar 03 02:03:05 PM PST 24
Finished Mar 03 02:03:13 PM PST 24
Peak memory 213964 kb
Host smart-94a1ee8a-88af-4044-8ac7-f2be2dfd14cb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2199418503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
keymgr_shadow_reg_errors_with_csr_rw.2199418503
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.3089953618
Short name T956
Test name
Test status
Simulation time 25216570 ps
CPU time 1.46 seconds
Started Mar 03 02:02:57 PM PST 24
Finished Mar 03 02:02:58 PM PST 24
Peak memory 213872 kb
Host smart-74668f8d-6ed5-4f7e-ac16-1831978577b2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3089953618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.3089953618
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.1163483250
Short name T1035
Test name
Test status
Simulation time 68446145 ps
CPU time 4.79 seconds
Started Mar 03 02:03:05 PM PST 24
Finished Mar 03 02:03:10 PM PST 24
Peak memory 205628 kb
Host smart-0aae418a-c893-40ef-b523-818266440abe
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163483250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.1
163483250
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.4030936534
Short name T1028
Test name
Test status
Simulation time 867988084 ps
CPU time 12.53 seconds
Started Mar 03 02:03:06 PM PST 24
Finished Mar 03 02:03:18 PM PST 24
Peak memory 205488 kb
Host smart-75e1fae8-c5bd-4f1d-a544-fd99b85422ad
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030936534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.4
030936534
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.3766846246
Short name T975
Test name
Test status
Simulation time 127864234 ps
CPU time 1.24 seconds
Started Mar 03 02:02:59 PM PST 24
Finished Mar 03 02:03:00 PM PST 24
Peak memory 205580 kb
Host smart-b7bcec0d-f094-46ce-af03-21f28cee57dd
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3766846246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.3
766846246
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.1102028644
Short name T1062
Test name
Test status
Simulation time 134651104 ps
CPU time 1.28 seconds
Started Mar 03 02:03:06 PM PST 24
Finished Mar 03 02:03:08 PM PST 24
Peak memory 213928 kb
Host smart-34c2e06a-ca20-44a0-afc8-e0d261c2e467
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102028644 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.1102028644
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.3889373986
Short name T942
Test name
Test status
Simulation time 26490991 ps
CPU time 1.05 seconds
Started Mar 03 02:03:00 PM PST 24
Finished Mar 03 02:03:01 PM PST 24
Peak memory 205728 kb
Host smart-5d26e242-620a-48b6-8864-8c74a5fef9c6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889373986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.3889373986
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.1018188666
Short name T982
Test name
Test status
Simulation time 11940541 ps
CPU time 0.76 seconds
Started Mar 03 02:02:59 PM PST 24
Finished Mar 03 02:02:59 PM PST 24
Peak memory 205192 kb
Host smart-bd4e5705-ff8f-4f9d-99bc-8c703f8e6dcd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1018188666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.1018188666
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.3708150605
Short name T130
Test name
Test status
Simulation time 83708153 ps
CPU time 1.66 seconds
Started Mar 03 02:03:05 PM PST 24
Finished Mar 03 02:03:07 PM PST 24
Peak memory 205676 kb
Host smart-a707a075-1e76-4ccc-b620-d6a54adf2353
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3708150605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sa
me_csr_outstanding.3708150605
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.2709030720
Short name T966
Test name
Test status
Simulation time 543710875 ps
CPU time 9.99 seconds
Started Mar 03 02:02:59 PM PST 24
Finished Mar 03 02:03:09 PM PST 24
Peak memory 214048 kb
Host smart-bf054c82-d02f-4268-8214-f25d987cd07c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709030720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.2709030720
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.3705630072
Short name T926
Test name
Test status
Simulation time 112557065 ps
CPU time 2.33 seconds
Started Mar 03 02:02:59 PM PST 24
Finished Mar 03 02:03:01 PM PST 24
Peak memory 213792 kb
Host smart-b9b91c71-1c9f-4193-be7d-2a0dc540a974
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705630072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.3705630072
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.3409629282
Short name T1019
Test name
Test status
Simulation time 330676465 ps
CPU time 2.2 seconds
Started Mar 03 02:03:28 PM PST 24
Finished Mar 03 02:03:30 PM PST 24
Peak memory 213700 kb
Host smart-35e40e6a-4f23-4fcb-ab5b-01f74544c4cb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3409629282 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.3409629282
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.2564391696
Short name T1037
Test name
Test status
Simulation time 35977497 ps
CPU time 0.87 seconds
Started Mar 03 02:03:28 PM PST 24
Finished Mar 03 02:03:29 PM PST 24
Peak memory 205404 kb
Host smart-c7e01bcc-21f8-4f1c-a67f-ccdd81e36d41
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564391696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.2564391696
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.57708256
Short name T913
Test name
Test status
Simulation time 12730082 ps
CPU time 0.7 seconds
Started Mar 03 02:03:28 PM PST 24
Finished Mar 03 02:03:28 PM PST 24
Peak memory 205240 kb
Host smart-c1632ca3-1a8d-4ff9-927f-226870212fa7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57708256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.57708256
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.1769652377
Short name T1024
Test name
Test status
Simulation time 228897771 ps
CPU time 2.51 seconds
Started Mar 03 02:03:28 PM PST 24
Finished Mar 03 02:03:31 PM PST 24
Peak memory 205684 kb
Host smart-bd56be58-6532-4575-b38f-2a72b71dbf69
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769652377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.1769652377
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.2024555105
Short name T103
Test name
Test status
Simulation time 350228591 ps
CPU time 3.69 seconds
Started Mar 03 02:03:26 PM PST 24
Finished Mar 03 02:03:30 PM PST 24
Peak memory 214108 kb
Host smart-1ba19a33-b296-48dc-8ac0-5bf622ebdaec
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024555105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.2024555105
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.3320733657
Short name T1034
Test name
Test status
Simulation time 440569105 ps
CPU time 8.99 seconds
Started Mar 03 02:03:26 PM PST 24
Finished Mar 03 02:03:35 PM PST 24
Peak memory 219952 kb
Host smart-b77d8098-d310-4ae3-933b-e338e154f23c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320733657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.keymgr_shadow_reg_errors_with_csr_rw.3320733657
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.1492907659
Short name T919
Test name
Test status
Simulation time 504831541 ps
CPU time 4.82 seconds
Started Mar 03 02:03:27 PM PST 24
Finished Mar 03 02:03:31 PM PST 24
Peak memory 221932 kb
Host smart-fb17a509-830d-4b7a-8a6f-744e98537476
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492907659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.1492907659
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.759570408
Short name T1050
Test name
Test status
Simulation time 28223865 ps
CPU time 1.18 seconds
Started Mar 03 02:03:38 PM PST 24
Finished Mar 03 02:03:39 PM PST 24
Peak memory 213924 kb
Host smart-15b177e4-8c49-42ba-b307-68096bcc49b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759570408 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.759570408
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.1659401859
Short name T974
Test name
Test status
Simulation time 190099969 ps
CPU time 1.08 seconds
Started Mar 03 02:03:26 PM PST 24
Finished Mar 03 02:03:28 PM PST 24
Peak memory 205500 kb
Host smart-f2c3fa77-a727-40e5-8c0d-a2b4c4b46001
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659401859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.1659401859
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.2697915019
Short name T1023
Test name
Test status
Simulation time 53754160 ps
CPU time 0.91 seconds
Started Mar 03 02:03:28 PM PST 24
Finished Mar 03 02:03:29 PM PST 24
Peak memory 205520 kb
Host smart-f9f18957-750c-469b-816b-aeaaf3876ff5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697915019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.2697915019
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.1606013892
Short name T941
Test name
Test status
Simulation time 62572432 ps
CPU time 1.84 seconds
Started Mar 03 02:03:40 PM PST 24
Finished Mar 03 02:03:42 PM PST 24
Peak memory 205528 kb
Host smart-f9952003-0989-4ed5-94eb-5d64983af100
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606013892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s
ame_csr_outstanding.1606013892
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.3993282769
Short name T931
Test name
Test status
Simulation time 198742337 ps
CPU time 4.23 seconds
Started Mar 03 02:03:29 PM PST 24
Finished Mar 03 02:03:34 PM PST 24
Peak memory 214128 kb
Host smart-286d78b7-28c9-4362-a893-681a0bbd1031
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993282769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.3993282769
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.3286751189
Short name T980
Test name
Test status
Simulation time 311465854 ps
CPU time 9.14 seconds
Started Mar 03 02:03:28 PM PST 24
Finished Mar 03 02:03:38 PM PST 24
Peak memory 213988 kb
Host smart-2b859a05-06b5-46fc-b55d-26ac166af068
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286751189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.3286751189
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.2457869895
Short name T1054
Test name
Test status
Simulation time 58953993 ps
CPU time 2.14 seconds
Started Mar 03 02:03:30 PM PST 24
Finished Mar 03 02:03:32 PM PST 24
Peak memory 213896 kb
Host smart-041d8b76-bd8a-4ea2-84b9-55be14da51e1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2457869895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.2457869895
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.2508909519
Short name T1038
Test name
Test status
Simulation time 614682180 ps
CPU time 4.72 seconds
Started Mar 03 02:03:28 PM PST 24
Finished Mar 03 02:03:32 PM PST 24
Peak memory 208856 kb
Host smart-eeb232bf-3b58-4833-9fc3-ee1584ff41dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508909519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.2508909519
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.1918502753
Short name T1069
Test name
Test status
Simulation time 139503859 ps
CPU time 1.43 seconds
Started Mar 03 02:03:36 PM PST 24
Finished Mar 03 02:03:38 PM PST 24
Peak memory 213908 kb
Host smart-e1e90aa2-ce61-41ff-b642-957271f9765e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1918502753 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.1918502753
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.1998954414
Short name T127
Test name
Test status
Simulation time 44446926 ps
CPU time 1.38 seconds
Started Mar 03 02:03:41 PM PST 24
Finished Mar 03 02:03:42 PM PST 24
Peak memory 205632 kb
Host smart-b45b8853-7a2b-475b-95f5-1318c32b247a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998954414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.1998954414
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.2296932404
Short name T964
Test name
Test status
Simulation time 35930641 ps
CPU time 0.81 seconds
Started Mar 03 02:03:39 PM PST 24
Finished Mar 03 02:03:40 PM PST 24
Peak memory 205324 kb
Host smart-51d4ca07-3d4f-446a-929b-58b3d23de516
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2296932404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.2296932404
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.1318965361
Short name T1072
Test name
Test status
Simulation time 53462865 ps
CPU time 2.26 seconds
Started Mar 03 02:03:36 PM PST 24
Finished Mar 03 02:03:40 PM PST 24
Peak memory 205640 kb
Host smart-66c6f8a8-5217-4da2-a85c-3ff234a5b0f5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318965361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.1318965361
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.1938001948
Short name T987
Test name
Test status
Simulation time 472171911 ps
CPU time 4 seconds
Started Mar 03 02:03:39 PM PST 24
Finished Mar 03 02:03:43 PM PST 24
Peak memory 214124 kb
Host smart-e9535655-14fc-470e-aad5-a988313db1ff
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938001948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.1938001948
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.2577078459
Short name T1031
Test name
Test status
Simulation time 364945357 ps
CPU time 6.55 seconds
Started Mar 03 02:03:36 PM PST 24
Finished Mar 03 02:03:43 PM PST 24
Peak memory 220064 kb
Host smart-6fcb71f4-620b-492c-9c49-c8afe741b406
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2577078459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.2577078459
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.3815550111
Short name T906
Test name
Test status
Simulation time 581444445 ps
CPU time 3.97 seconds
Started Mar 03 02:03:38 PM PST 24
Finished Mar 03 02:03:42 PM PST 24
Peak memory 213840 kb
Host smart-1069f0a8-ec24-4e61-a9c6-a3a5628ca26c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815550111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.3815550111
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.4003987404
Short name T1000
Test name
Test status
Simulation time 181766530 ps
CPU time 6.07 seconds
Started Mar 03 02:03:37 PM PST 24
Finished Mar 03 02:03:44 PM PST 24
Peak memory 209104 kb
Host smart-a0ef063c-58cc-42bb-8736-6ea2c9a0d6b6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003987404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.4003987404
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.2500775341
Short name T976
Test name
Test status
Simulation time 98267840 ps
CPU time 1.16 seconds
Started Mar 03 02:03:37 PM PST 24
Finished Mar 03 02:03:39 PM PST 24
Peak memory 205592 kb
Host smart-a14d2aaf-88cc-45db-b802-c510ceabb460
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500775341 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.2500775341
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.1782974483
Short name T132
Test name
Test status
Simulation time 91693088 ps
CPU time 1.23 seconds
Started Mar 03 02:03:38 PM PST 24
Finished Mar 03 02:03:40 PM PST 24
Peak memory 205684 kb
Host smart-c6b3a1ea-fe20-426c-a050-15ee1979e712
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782974483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.1782974483
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.109409824
Short name T930
Test name
Test status
Simulation time 18991560 ps
CPU time 0.82 seconds
Started Mar 03 02:03:41 PM PST 24
Finished Mar 03 02:03:42 PM PST 24
Peak memory 205316 kb
Host smart-450e35de-7ba9-4339-8706-ed53fcd269c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109409824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.109409824
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.566511472
Short name T1051
Test name
Test status
Simulation time 102443442 ps
CPU time 2.27 seconds
Started Mar 03 02:03:37 PM PST 24
Finished Mar 03 02:03:40 PM PST 24
Peak memory 205692 kb
Host smart-e66db33f-004c-4a25-bd30-b69048945a63
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=566511472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_sa
me_csr_outstanding.566511472
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.2057271066
Short name T110
Test name
Test status
Simulation time 430308407 ps
CPU time 2.76 seconds
Started Mar 03 02:03:39 PM PST 24
Finished Mar 03 02:03:42 PM PST 24
Peak memory 214076 kb
Host smart-e0bfa9b7-daca-4501-9b59-0339e7115265
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057271066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.2057271066
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.451320913
Short name T1073
Test name
Test status
Simulation time 70111407 ps
CPU time 2.71 seconds
Started Mar 03 02:03:38 PM PST 24
Finished Mar 03 02:03:41 PM PST 24
Peak memory 215804 kb
Host smart-61d5e599-8190-46f0-80ee-5ce71c195a92
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451320913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.451320913
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.41156274
Short name T938
Test name
Test status
Simulation time 57044835 ps
CPU time 1.77 seconds
Started Mar 03 02:03:47 PM PST 24
Finished Mar 03 02:03:49 PM PST 24
Peak memory 213900 kb
Host smart-68121fc2-1717-4dbc-aa29-aa73aa4e8fa7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41156274 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.41156274
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.125782857
Short name T946
Test name
Test status
Simulation time 25931170 ps
CPU time 1.06 seconds
Started Mar 03 02:03:47 PM PST 24
Finished Mar 03 02:03:48 PM PST 24
Peak memory 205456 kb
Host smart-0ed4e80e-04ec-466a-9814-51633c195fc9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125782857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.125782857
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.3066197632
Short name T1041
Test name
Test status
Simulation time 10365535 ps
CPU time 0.82 seconds
Started Mar 03 02:03:45 PM PST 24
Finished Mar 03 02:03:46 PM PST 24
Peak memory 205240 kb
Host smart-751009eb-9c27-4e61-bbc2-396cf34a1e53
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066197632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.3066197632
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.2328025774
Short name T969
Test name
Test status
Simulation time 210764429 ps
CPU time 2.14 seconds
Started Mar 03 02:03:44 PM PST 24
Finished Mar 03 02:03:47 PM PST 24
Peak memory 205540 kb
Host smart-4dbd0ebb-8eea-4a5c-aebb-418a4eca2ba7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328025774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s
ame_csr_outstanding.2328025774
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.3021315624
Short name T1067
Test name
Test status
Simulation time 157320965 ps
CPU time 3.56 seconds
Started Mar 03 02:03:46 PM PST 24
Finished Mar 03 02:03:50 PM PST 24
Peak memory 214040 kb
Host smart-df7e32dd-9a8f-4370-8b2a-cf9be3751714
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021315624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.3021315624
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.3440512446
Short name T109
Test name
Test status
Simulation time 445829562 ps
CPU time 5.97 seconds
Started Mar 03 02:03:47 PM PST 24
Finished Mar 03 02:03:53 PM PST 24
Peak memory 219856 kb
Host smart-195d9e10-871e-4218-b42f-ee5a7b1a7dfd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440512446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.3440512446
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.3595832236
Short name T951
Test name
Test status
Simulation time 108611627 ps
CPU time 3.07 seconds
Started Mar 03 02:03:46 PM PST 24
Finished Mar 03 02:03:49 PM PST 24
Peak memory 213852 kb
Host smart-3b5bd513-42b7-4563-aef9-f7deaf12771c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3595832236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.3595832236
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.1683605530
Short name T1007
Test name
Test status
Simulation time 51499163 ps
CPU time 1.44 seconds
Started Mar 03 02:03:46 PM PST 24
Finished Mar 03 02:03:48 PM PST 24
Peak memory 213888 kb
Host smart-a392c287-4b29-4d8e-8f8e-2b4e15eb9e12
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683605530 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.1683605530
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.1861021990
Short name T1004
Test name
Test status
Simulation time 46267241 ps
CPU time 1.16 seconds
Started Mar 03 02:03:48 PM PST 24
Finished Mar 03 02:03:51 PM PST 24
Peak memory 205552 kb
Host smart-3515403d-38d2-40c1-9f3a-81fae3ff6a0f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861021990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.1861021990
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.3544465966
Short name T915
Test name
Test status
Simulation time 32934962 ps
CPU time 0.72 seconds
Started Mar 03 02:03:44 PM PST 24
Finished Mar 03 02:03:46 PM PST 24
Peak memory 205340 kb
Host smart-d9d70c93-e940-4ed0-a5df-c6f8fe2e2d9a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544465966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.3544465966
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.2165430711
Short name T965
Test name
Test status
Simulation time 35601498 ps
CPU time 2.06 seconds
Started Mar 03 02:03:48 PM PST 24
Finished Mar 03 02:03:52 PM PST 24
Peak memory 205596 kb
Host smart-9164dc1d-b57f-4bb8-9775-496d8f725c90
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165430711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.2165430711
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.3643382989
Short name T101
Test name
Test status
Simulation time 350995368 ps
CPU time 2.11 seconds
Started Mar 03 02:03:47 PM PST 24
Finished Mar 03 02:03:49 PM PST 24
Peak memory 214112 kb
Host smart-24b49d09-901f-46b3-9111-3de1eac99c12
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643382989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.3643382989
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.802659604
Short name T945
Test name
Test status
Simulation time 1097732934 ps
CPU time 10.41 seconds
Started Mar 03 02:03:45 PM PST 24
Finished Mar 03 02:03:56 PM PST 24
Peak memory 214112 kb
Host smart-35e6dd98-7cd7-4e9a-bce0-b359bbf570aa
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802659604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.
keymgr_shadow_reg_errors_with_csr_rw.802659604
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.2571500996
Short name T988
Test name
Test status
Simulation time 91525057 ps
CPU time 1.67 seconds
Started Mar 03 02:03:45 PM PST 24
Finished Mar 03 02:03:47 PM PST 24
Peak memory 213824 kb
Host smart-6da681ae-8aca-48a8-a695-2a493678ab58
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571500996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.2571500996
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.3224052772
Short name T150
Test name
Test status
Simulation time 875979306 ps
CPU time 9.81 seconds
Started Mar 03 02:03:47 PM PST 24
Finished Mar 03 02:04:00 PM PST 24
Peak memory 209176 kb
Host smart-e5752a96-aadc-494e-b9a9-f1083071bfba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224052772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.3224052772
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.3427300911
Short name T1021
Test name
Test status
Simulation time 99611494 ps
CPU time 2.03 seconds
Started Mar 03 02:03:47 PM PST 24
Finished Mar 03 02:03:49 PM PST 24
Peak memory 218480 kb
Host smart-6f2da6d8-9cdd-413c-8f2a-cd58b663c463
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427300911 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.3427300911
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.2877720521
Short name T126
Test name
Test status
Simulation time 13496087 ps
CPU time 1.27 seconds
Started Mar 03 02:03:45 PM PST 24
Finished Mar 03 02:03:46 PM PST 24
Peak memory 205696 kb
Host smart-115a37dd-8f66-4209-90e0-05f9b44a89b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877720521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.2877720521
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.1643861320
Short name T1008
Test name
Test status
Simulation time 7725124 ps
CPU time 0.71 seconds
Started Mar 03 02:03:46 PM PST 24
Finished Mar 03 02:03:46 PM PST 24
Peak memory 205260 kb
Host smart-acd1d951-7fcd-4e67-b89c-022122b5b0d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1643861320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.1643861320
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.3454143031
Short name T1059
Test name
Test status
Simulation time 148076874 ps
CPU time 2.1 seconds
Started Mar 03 02:03:47 PM PST 24
Finished Mar 03 02:03:49 PM PST 24
Peak memory 205584 kb
Host smart-52f363d9-fdea-43da-81ce-29044edcdd5a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454143031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.3454143031
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.2930260704
Short name T944
Test name
Test status
Simulation time 440280859 ps
CPU time 3.74 seconds
Started Mar 03 02:03:46 PM PST 24
Finished Mar 03 02:03:50 PM PST 24
Peak memory 214084 kb
Host smart-d62e4da2-30f6-4cba-a0b4-7abd91713ff4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930260704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.2930260704
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.377074136
Short name T1068
Test name
Test status
Simulation time 191371819 ps
CPU time 5.07 seconds
Started Mar 03 02:03:47 PM PST 24
Finished Mar 03 02:03:55 PM PST 24
Peak memory 220052 kb
Host smart-63230853-a0fb-4b40-a14d-6693049874b3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377074136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
keymgr_shadow_reg_errors_with_csr_rw.377074136
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.3099137288
Short name T172
Test name
Test status
Simulation time 75217955 ps
CPU time 2.67 seconds
Started Mar 03 02:03:45 PM PST 24
Finished Mar 03 02:03:48 PM PST 24
Peak memory 213700 kb
Host smart-a011c1d8-b2ad-4a55-a378-fb6fb545f1ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099137288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.3099137288
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.1588420556
Short name T1020
Test name
Test status
Simulation time 23718109 ps
CPU time 1.52 seconds
Started Mar 03 02:03:47 PM PST 24
Finished Mar 03 02:03:48 PM PST 24
Peak memory 213912 kb
Host smart-59de7d23-a921-439e-8104-d9bbe6090fcc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1588420556 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.1588420556
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.3745566535
Short name T128
Test name
Test status
Simulation time 41156085 ps
CPU time 0.93 seconds
Started Mar 03 02:03:45 PM PST 24
Finished Mar 03 02:03:46 PM PST 24
Peak memory 205500 kb
Host smart-c40e6a2d-2712-431f-b543-f8ea7574af60
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745566535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.3745566535
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.1443612470
Short name T986
Test name
Test status
Simulation time 11973444 ps
CPU time 0.73 seconds
Started Mar 03 02:03:48 PM PST 24
Finished Mar 03 02:03:51 PM PST 24
Peak memory 205292 kb
Host smart-8d848666-c0ea-4ba8-8d4f-09af0ec5c0af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1443612470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.1443612470
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.2564001587
Short name T1013
Test name
Test status
Simulation time 168616550 ps
CPU time 3.1 seconds
Started Mar 03 02:03:48 PM PST 24
Finished Mar 03 02:03:53 PM PST 24
Peak memory 205648 kb
Host smart-6883c4df-9448-441a-916c-442ba1fef29d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2564001587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.2564001587
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.651403293
Short name T1026
Test name
Test status
Simulation time 1736191139 ps
CPU time 10.21 seconds
Started Mar 03 02:03:47 PM PST 24
Finished Mar 03 02:03:57 PM PST 24
Peak memory 214052 kb
Host smart-da852cd0-992b-4404-852f-aa5b16093a5b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=651403293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shado
w_reg_errors.651403293
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.3166949260
Short name T111
Test name
Test status
Simulation time 713204491 ps
CPU time 7.37 seconds
Started Mar 03 02:03:47 PM PST 24
Finished Mar 03 02:03:55 PM PST 24
Peak memory 214108 kb
Host smart-d6d83569-5652-4064-b4d6-965b691c9f9d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166949260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.keymgr_shadow_reg_errors_with_csr_rw.3166949260
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.1103450519
Short name T929
Test name
Test status
Simulation time 300579803 ps
CPU time 2.8 seconds
Started Mar 03 02:03:46 PM PST 24
Finished Mar 03 02:03:49 PM PST 24
Peak memory 213864 kb
Host smart-274788ef-d0cb-43ef-a42c-b109d74bf627
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103450519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.1103450519
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.1318501670
Short name T156
Test name
Test status
Simulation time 438808343 ps
CPU time 6.49 seconds
Started Mar 03 02:03:44 PM PST 24
Finished Mar 03 02:03:52 PM PST 24
Peak memory 208724 kb
Host smart-5b77ea14-9e8d-4090-86c1-1229806823af
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318501670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.1318501670
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.1745172361
Short name T983
Test name
Test status
Simulation time 21444035 ps
CPU time 1.14 seconds
Started Mar 03 02:03:52 PM PST 24
Finished Mar 03 02:03:54 PM PST 24
Peak memory 205680 kb
Host smart-543057d8-4419-465e-922f-d70ff500dd8b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745172361 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.1745172361
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.3406206633
Short name T959
Test name
Test status
Simulation time 83297564 ps
CPU time 1.24 seconds
Started Mar 03 02:03:55 PM PST 24
Finished Mar 03 02:03:58 PM PST 24
Peak memory 205636 kb
Host smart-31a10d01-1637-4555-9f3b-2b7f95ca7a7d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406206633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.3406206633
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.4010984313
Short name T935
Test name
Test status
Simulation time 19679393 ps
CPU time 0.72 seconds
Started Mar 03 02:03:55 PM PST 24
Finished Mar 03 02:03:57 PM PST 24
Peak memory 205348 kb
Host smart-273eb2b9-d34b-44cf-905f-2cc12e775bbd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010984313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.4010984313
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.1202303259
Short name T943
Test name
Test status
Simulation time 23982145 ps
CPU time 1.44 seconds
Started Mar 03 02:03:52 PM PST 24
Finished Mar 03 02:03:54 PM PST 24
Peak memory 205608 kb
Host smart-d253f686-9448-4c9c-9be5-f47c3e644c55
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202303259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.1202303259
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.1936178709
Short name T928
Test name
Test status
Simulation time 420430975 ps
CPU time 5.51 seconds
Started Mar 03 02:03:46 PM PST 24
Finished Mar 03 02:03:52 PM PST 24
Peak memory 214132 kb
Host smart-60a6f25b-0700-41bc-a983-a12fc03adfa8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936178709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.1936178709
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.3673143375
Short name T984
Test name
Test status
Simulation time 1687135571 ps
CPU time 16.31 seconds
Started Mar 03 02:03:45 PM PST 24
Finished Mar 03 02:04:02 PM PST 24
Peak memory 214068 kb
Host smart-b89719eb-0919-46f6-9d91-87cc62bbd3e2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673143375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.3673143375
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.722012922
Short name T977
Test name
Test status
Simulation time 244462974 ps
CPU time 4.15 seconds
Started Mar 03 02:03:48 PM PST 24
Finished Mar 03 02:03:54 PM PST 24
Peak memory 213768 kb
Host smart-7ab73f47-841b-470a-987c-1f74c82ec3b0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=722012922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.722012922
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.1690704186
Short name T144
Test name
Test status
Simulation time 1020219624 ps
CPU time 9.72 seconds
Started Mar 03 02:03:46 PM PST 24
Finished Mar 03 02:03:56 PM PST 24
Peak memory 209084 kb
Host smart-98ea8c7e-a3ef-4a7a-817a-bc3110295dd8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690704186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.1690704186
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.61564657
Short name T1039
Test name
Test status
Simulation time 199309385 ps
CPU time 1.79 seconds
Started Mar 03 02:03:55 PM PST 24
Finished Mar 03 02:03:59 PM PST 24
Peak memory 213892 kb
Host smart-51c1985b-451c-45b4-a0c2-46b307cd30d7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61564657 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.61564657
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.3336610539
Short name T1032
Test name
Test status
Simulation time 16638692 ps
CPU time 1.12 seconds
Started Mar 03 02:03:57 PM PST 24
Finished Mar 03 02:03:59 PM PST 24
Peak memory 205588 kb
Host smart-ca1da773-1567-4bcc-8be8-557a058f7cdc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336610539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.3336610539
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.3866748374
Short name T968
Test name
Test status
Simulation time 74804632 ps
CPU time 0.71 seconds
Started Mar 03 02:03:55 PM PST 24
Finished Mar 03 02:03:57 PM PST 24
Peak memory 205360 kb
Host smart-98114203-be97-4df7-957f-11a1fc2f4c69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866748374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.3866748374
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.2940389983
Short name T972
Test name
Test status
Simulation time 38636016 ps
CPU time 1.92 seconds
Started Mar 03 02:03:55 PM PST 24
Finished Mar 03 02:03:58 PM PST 24
Peak memory 205656 kb
Host smart-aec9d306-1613-4097-bb16-46406f44b14e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940389983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.2940389983
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.379542484
Short name T1025
Test name
Test status
Simulation time 1063178612 ps
CPU time 22.45 seconds
Started Mar 03 02:03:53 PM PST 24
Finished Mar 03 02:04:16 PM PST 24
Peak memory 217436 kb
Host smart-8849a326-2b6b-4d76-8535-fb20cee5c15f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379542484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shado
w_reg_errors.379542484
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.2120656426
Short name T950
Test name
Test status
Simulation time 1054590000 ps
CPU time 9.25 seconds
Started Mar 03 02:03:54 PM PST 24
Finished Mar 03 02:04:04 PM PST 24
Peak memory 214152 kb
Host smart-5d32931d-8efb-4b7c-b7fd-ab58387c27d4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120656426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.2120656426
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.1246352232
Short name T1003
Test name
Test status
Simulation time 56657595 ps
CPU time 1.75 seconds
Started Mar 03 02:03:52 PM PST 24
Finished Mar 03 02:03:54 PM PST 24
Peak memory 213780 kb
Host smart-0e2eb743-1712-4fc3-926f-8fa00923f59e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1246352232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.1246352232
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.449745762
Short name T149
Test name
Test status
Simulation time 302015705 ps
CPU time 9.06 seconds
Started Mar 03 02:03:53 PM PST 24
Finished Mar 03 02:04:03 PM PST 24
Peak memory 208176 kb
Host smart-3e1ade5d-424d-4eff-b6fd-fe5bc2d74d26
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449745762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_err
.449745762
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.3183363433
Short name T953
Test name
Test status
Simulation time 310113898 ps
CPU time 4.59 seconds
Started Mar 03 02:03:05 PM PST 24
Finished Mar 03 02:03:09 PM PST 24
Peak memory 205572 kb
Host smart-e91d6f1c-0e02-4536-8252-c3273ec4dd55
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3183363433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.3
183363433
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.1502088262
Short name T948
Test name
Test status
Simulation time 12166050897 ps
CPU time 17.42 seconds
Started Mar 03 02:03:08 PM PST 24
Finished Mar 03 02:03:26 PM PST 24
Peak memory 205708 kb
Host smart-ce8138cb-264b-4abf-ad8a-46bbd810d6bb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502088262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.1
502088262
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.2927036502
Short name T1040
Test name
Test status
Simulation time 65163660 ps
CPU time 1.18 seconds
Started Mar 03 02:03:06 PM PST 24
Finished Mar 03 02:03:08 PM PST 24
Peak memory 205544 kb
Host smart-902e968e-07c8-4b53-be94-808ed50bee55
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2927036502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.2
927036502
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.2777831730
Short name T992
Test name
Test status
Simulation time 55769021 ps
CPU time 1.4 seconds
Started Mar 03 02:03:07 PM PST 24
Finished Mar 03 02:03:08 PM PST 24
Peak memory 205700 kb
Host smart-e8210b80-0f04-4d7d-b53b-0833c5d96868
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2777831730 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.2777831730
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.3410874714
Short name T937
Test name
Test status
Simulation time 60210791 ps
CPU time 1.15 seconds
Started Mar 03 02:03:04 PM PST 24
Finished Mar 03 02:03:05 PM PST 24
Peak memory 205668 kb
Host smart-918aa763-3e45-46c2-bbe8-2cdebd6c5bda
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410874714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.3410874714
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.3678192173
Short name T1058
Test name
Test status
Simulation time 10272172 ps
CPU time 0.71 seconds
Started Mar 03 02:03:06 PM PST 24
Finished Mar 03 02:03:07 PM PST 24
Peak memory 205272 kb
Host smart-ab860834-b105-4e2b-bec7-a5d08f168eee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3678192173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.3678192173
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.976335208
Short name T991
Test name
Test status
Simulation time 813195939 ps
CPU time 2.33 seconds
Started Mar 03 02:03:17 PM PST 24
Finished Mar 03 02:03:20 PM PST 24
Peak memory 205396 kb
Host smart-f7906da2-ec1a-434c-abf8-d0009c5f0bf9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976335208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sam
e_csr_outstanding.976335208
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.3767636558
Short name T963
Test name
Test status
Simulation time 915239888 ps
CPU time 6.23 seconds
Started Mar 03 02:03:06 PM PST 24
Finished Mar 03 02:03:12 PM PST 24
Peak memory 222160 kb
Host smart-633158cd-9aae-4dae-8a0c-21d8841b2f55
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767636558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.3767636558
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.1173937661
Short name T971
Test name
Test status
Simulation time 166858108 ps
CPU time 6.59 seconds
Started Mar 03 02:03:06 PM PST 24
Finished Mar 03 02:03:13 PM PST 24
Peak memory 214072 kb
Host smart-e9faa241-c6d4-4886-adc3-fe0bd486e4d9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173937661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.1173937661
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.2774489331
Short name T978
Test name
Test status
Simulation time 75774743 ps
CPU time 2.41 seconds
Started Mar 03 02:03:17 PM PST 24
Finished Mar 03 02:03:20 PM PST 24
Peak memory 213620 kb
Host smart-f8c9b559-3fde-4259-b70a-dccc0757ab0d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774489331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.2774489331
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.1587470831
Short name T155
Test name
Test status
Simulation time 767884956 ps
CPU time 10.83 seconds
Started Mar 03 02:03:07 PM PST 24
Finished Mar 03 02:03:18 PM PST 24
Peak memory 209172 kb
Host smart-1e5202cb-f04f-4afa-b538-372fa2ff1d80
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587470831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.1587470831
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.3880891920
Short name T1064
Test name
Test status
Simulation time 169258778 ps
CPU time 0.75 seconds
Started Mar 03 02:03:56 PM PST 24
Finished Mar 03 02:03:58 PM PST 24
Peak memory 205252 kb
Host smart-dc043e5b-8c23-4dc5-a12d-3cbe77cc1655
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880891920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.3880891920
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.767411949
Short name T925
Test name
Test status
Simulation time 13927016 ps
CPU time 0.8 seconds
Started Mar 03 02:03:54 PM PST 24
Finished Mar 03 02:03:56 PM PST 24
Peak memory 205380 kb
Host smart-98234d1f-1e38-435c-8d5a-1cb00cf163bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767411949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.767411949
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.3941068040
Short name T1052
Test name
Test status
Simulation time 19224187 ps
CPU time 0.7 seconds
Started Mar 03 02:03:54 PM PST 24
Finished Mar 03 02:03:56 PM PST 24
Peak memory 205348 kb
Host smart-08e7309b-4c11-44c5-ae09-c85a6d9f2132
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941068040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.3941068040
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.1534740676
Short name T910
Test name
Test status
Simulation time 49663775 ps
CPU time 0.76 seconds
Started Mar 03 02:03:54 PM PST 24
Finished Mar 03 02:03:56 PM PST 24
Peak memory 205248 kb
Host smart-2ac8fd30-7674-4dee-8d9e-30e6ff81c692
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1534740676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.1534740676
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.3689427150
Short name T952
Test name
Test status
Simulation time 28074305 ps
CPU time 0.67 seconds
Started Mar 03 02:03:55 PM PST 24
Finished Mar 03 02:03:57 PM PST 24
Peak memory 205284 kb
Host smart-2262f816-5ae1-4f57-bebb-56533ebefd3b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689427150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.3689427150
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.2583699531
Short name T922
Test name
Test status
Simulation time 53099502 ps
CPU time 0.72 seconds
Started Mar 03 02:03:55 PM PST 24
Finished Mar 03 02:03:57 PM PST 24
Peak memory 205240 kb
Host smart-4eec7476-d754-4f67-81e3-939429e6b05b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583699531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.2583699531
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.1363238963
Short name T1048
Test name
Test status
Simulation time 30015423 ps
CPU time 0.7 seconds
Started Mar 03 02:03:57 PM PST 24
Finished Mar 03 02:03:59 PM PST 24
Peak memory 205336 kb
Host smart-d2c8dbfa-7f04-4a73-9f49-1a198a8ece93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1363238963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.1363238963
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.2126982377
Short name T920
Test name
Test status
Simulation time 53939389 ps
CPU time 0.77 seconds
Started Mar 03 02:03:53 PM PST 24
Finished Mar 03 02:03:54 PM PST 24
Peak memory 205240 kb
Host smart-97ac1776-ca02-4eb9-8636-0cb5b8b0ea7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126982377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.2126982377
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.22079013
Short name T1065
Test name
Test status
Simulation time 32918868 ps
CPU time 0.73 seconds
Started Mar 03 02:03:53 PM PST 24
Finished Mar 03 02:03:54 PM PST 24
Peak memory 205208 kb
Host smart-abc76f6b-9f7d-47fb-bdf1-2a9aa1ac7572
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22079013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.22079013
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.3803226636
Short name T1036
Test name
Test status
Simulation time 35989796 ps
CPU time 0.87 seconds
Started Mar 03 02:03:54 PM PST 24
Finished Mar 03 02:03:56 PM PST 24
Peak memory 205260 kb
Host smart-42b3021e-5d18-4c54-a36c-1b9bca05185e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3803226636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.3803226636
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.3398953414
Short name T1012
Test name
Test status
Simulation time 263368314 ps
CPU time 4.9 seconds
Started Mar 03 02:03:14 PM PST 24
Finished Mar 03 02:03:19 PM PST 24
Peak memory 205600 kb
Host smart-15bb17f1-a81f-472c-8bcd-24c688aaf09b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3398953414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.3
398953414
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.1683074728
Short name T911
Test name
Test status
Simulation time 255364826 ps
CPU time 14.25 seconds
Started Mar 03 02:03:18 PM PST 24
Finished Mar 03 02:03:32 PM PST 24
Peak memory 205504 kb
Host smart-b8acfccd-1e68-4b76-988e-f5b19f812b2c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683074728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.1
683074728
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.756238004
Short name T917
Test name
Test status
Simulation time 45509338 ps
CPU time 0.92 seconds
Started Mar 03 02:03:14 PM PST 24
Finished Mar 03 02:03:15 PM PST 24
Peak memory 205372 kb
Host smart-d8f7986a-2da8-4749-831f-22e24eb93a50
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756238004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.756238004
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.3128256222
Short name T927
Test name
Test status
Simulation time 31707074 ps
CPU time 2.15 seconds
Started Mar 03 02:03:12 PM PST 24
Finished Mar 03 02:03:15 PM PST 24
Peak memory 213924 kb
Host smart-c0fa72cc-77d7-4891-b097-38a890ad201f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128256222 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.3128256222
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.2997668970
Short name T1044
Test name
Test status
Simulation time 14084366 ps
CPU time 1.08 seconds
Started Mar 03 02:03:15 PM PST 24
Finished Mar 03 02:03:17 PM PST 24
Peak memory 205632 kb
Host smart-9ac831e7-7feb-4e4e-b39f-9755b3e573c1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997668970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.2997668970
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.3486612771
Short name T1047
Test name
Test status
Simulation time 10701347 ps
CPU time 0.83 seconds
Started Mar 03 02:03:07 PM PST 24
Finished Mar 03 02:03:08 PM PST 24
Peak memory 205344 kb
Host smart-4de7de2a-2f0a-4265-863a-1471349b86d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486612771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.3486612771
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.1704944654
Short name T1002
Test name
Test status
Simulation time 116310758 ps
CPU time 2.84 seconds
Started Mar 03 02:03:14 PM PST 24
Finished Mar 03 02:03:17 PM PST 24
Peak memory 205632 kb
Host smart-83511df7-dde8-4fcc-aa01-38cac8ad0081
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704944654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.1704944654
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.1957823732
Short name T1042
Test name
Test status
Simulation time 153341285 ps
CPU time 2.8 seconds
Started Mar 03 02:03:07 PM PST 24
Finished Mar 03 02:03:10 PM PST 24
Peak memory 214056 kb
Host smart-f51e2f3f-ac9f-48b0-8448-8b71a08384ff
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957823732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.1957823732
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.2674647687
Short name T954
Test name
Test status
Simulation time 336816264 ps
CPU time 9.63 seconds
Started Mar 03 02:03:07 PM PST 24
Finished Mar 03 02:03:17 PM PST 24
Peak memory 214020 kb
Host smart-eba87b7b-963c-4688-939c-1665784b463f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674647687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.2674647687
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.4223554627
Short name T174
Test name
Test status
Simulation time 366354324 ps
CPU time 6.04 seconds
Started Mar 03 02:03:17 PM PST 24
Finished Mar 03 02:03:24 PM PST 24
Peak memory 216788 kb
Host smart-fa8460f7-27e8-4f09-951f-ab9add6506ec
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223554627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.4223554627
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.2608503537
Short name T962
Test name
Test status
Simulation time 24624298 ps
CPU time 0.74 seconds
Started Mar 03 02:03:55 PM PST 24
Finished Mar 03 02:03:57 PM PST 24
Peak memory 205272 kb
Host smart-cd751b30-9976-48f5-9ce5-db8ac41a5ebe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2608503537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.2608503537
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.846361556
Short name T907
Test name
Test status
Simulation time 15093576 ps
CPU time 0.85 seconds
Started Mar 03 02:03:55 PM PST 24
Finished Mar 03 02:03:57 PM PST 24
Peak memory 205364 kb
Host smart-33034651-4d29-4fe9-b761-83f5e2f8befd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846361556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.846361556
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.2019563469
Short name T918
Test name
Test status
Simulation time 14794333 ps
CPU time 0.91 seconds
Started Mar 03 02:03:55 PM PST 24
Finished Mar 03 02:03:57 PM PST 24
Peak memory 205500 kb
Host smart-0e60c198-b6e9-407f-bf54-e0e888e2a86c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2019563469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.2019563469
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.2843718302
Short name T999
Test name
Test status
Simulation time 39574903 ps
CPU time 0.8 seconds
Started Mar 03 02:03:55 PM PST 24
Finished Mar 03 02:03:58 PM PST 24
Peak memory 205336 kb
Host smart-baa72f80-a81d-4b7e-b08c-29a4b38f5c24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843718302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.2843718302
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.2759440827
Short name T960
Test name
Test status
Simulation time 30494103 ps
CPU time 0.81 seconds
Started Mar 03 02:03:53 PM PST 24
Finished Mar 03 02:03:54 PM PST 24
Peak memory 205348 kb
Host smart-10fdd829-190c-4dbb-b1ea-2f95b5fac333
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759440827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.2759440827
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.3636458987
Short name T923
Test name
Test status
Simulation time 10753999 ps
CPU time 0.83 seconds
Started Mar 03 02:03:56 PM PST 24
Finished Mar 03 02:03:58 PM PST 24
Peak memory 205252 kb
Host smart-bee233e4-b12d-4250-b10a-16dba3aaccc0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636458987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.3636458987
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.1179284328
Short name T973
Test name
Test status
Simulation time 113073378 ps
CPU time 0.79 seconds
Started Mar 03 02:03:54 PM PST 24
Finished Mar 03 02:03:56 PM PST 24
Peak memory 205360 kb
Host smart-6cd530fc-598a-4b7a-9ebf-85310a294986
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179284328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.1179284328
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.3148529630
Short name T933
Test name
Test status
Simulation time 24054841 ps
CPU time 0.72 seconds
Started Mar 03 02:03:54 PM PST 24
Finished Mar 03 02:03:56 PM PST 24
Peak memory 205320 kb
Host smart-fc184f7a-633c-49f1-9113-a7a89e40a026
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148529630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.3148529630
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.2307271547
Short name T1070
Test name
Test status
Simulation time 21512358 ps
CPU time 0.73 seconds
Started Mar 03 02:03:54 PM PST 24
Finished Mar 03 02:03:56 PM PST 24
Peak memory 205316 kb
Host smart-22b845db-5b16-47bf-9b85-f027648988da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307271547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.2307271547
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.2705674253
Short name T1049
Test name
Test status
Simulation time 32560903 ps
CPU time 0.74 seconds
Started Mar 03 02:03:54 PM PST 24
Finished Mar 03 02:03:56 PM PST 24
Peak memory 205348 kb
Host smart-f56caca9-7caa-48c3-9399-b80b1301a847
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2705674253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.2705674253
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.1242189935
Short name T955
Test name
Test status
Simulation time 363028718 ps
CPU time 10.35 seconds
Started Mar 03 02:03:15 PM PST 24
Finished Mar 03 02:03:25 PM PST 24
Peak memory 205712 kb
Host smart-08df7891-9f13-49ef-adb9-27f6fade2374
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242189935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.1
242189935
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.1011282823
Short name T135
Test name
Test status
Simulation time 1003226754 ps
CPU time 15.4 seconds
Started Mar 03 02:03:15 PM PST 24
Finished Mar 03 02:03:31 PM PST 24
Peak memory 205584 kb
Host smart-3bcaa557-e871-40e6-97a5-dca16840d4d7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011282823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.1
011282823
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.1726283790
Short name T996
Test name
Test status
Simulation time 57495346 ps
CPU time 1.01 seconds
Started Mar 03 02:03:13 PM PST 24
Finished Mar 03 02:03:14 PM PST 24
Peak memory 205516 kb
Host smart-c41599de-0943-4ce4-a77c-097c00930661
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726283790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.1
726283790
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.1158391581
Short name T934
Test name
Test status
Simulation time 34981048 ps
CPU time 1.8 seconds
Started Mar 03 02:03:12 PM PST 24
Finished Mar 03 02:03:14 PM PST 24
Peak memory 213808 kb
Host smart-3ccfef8f-5324-4aa3-9a68-4d507bb6abf3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158391581 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.1158391581
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.3853719210
Short name T947
Test name
Test status
Simulation time 25430042 ps
CPU time 1.52 seconds
Started Mar 03 02:03:14 PM PST 24
Finished Mar 03 02:03:16 PM PST 24
Peak memory 205560 kb
Host smart-2ec5e7aa-dee4-4844-bb40-878f238a3de1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3853719210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.3853719210
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.399050864
Short name T916
Test name
Test status
Simulation time 57653286 ps
CPU time 0.73 seconds
Started Mar 03 02:03:18 PM PST 24
Finished Mar 03 02:03:19 PM PST 24
Peak memory 205220 kb
Host smart-85af3736-edf7-42ec-89c3-506c6fcdf95d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399050864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.399050864
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.4201994493
Short name T1006
Test name
Test status
Simulation time 20249777 ps
CPU time 1.47 seconds
Started Mar 03 02:03:14 PM PST 24
Finished Mar 03 02:03:16 PM PST 24
Peak memory 205576 kb
Host smart-45222392-fbd4-4011-861f-62a61eeb437d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4201994493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.4201994493
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.1612688126
Short name T1053
Test name
Test status
Simulation time 160639052 ps
CPU time 4.91 seconds
Started Mar 03 02:03:18 PM PST 24
Finished Mar 03 02:03:23 PM PST 24
Peak memory 222152 kb
Host smart-bbddb079-30fa-4f0b-9b93-1e1d2aac5d3c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612688126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.1612688126
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.850505675
Short name T1001
Test name
Test status
Simulation time 547823166 ps
CPU time 8.04 seconds
Started Mar 03 02:03:15 PM PST 24
Finished Mar 03 02:03:24 PM PST 24
Peak memory 214012 kb
Host smart-ee9d00c5-296b-4f8a-8d8c-0069f26ea505
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850505675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.k
eymgr_shadow_reg_errors_with_csr_rw.850505675
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.1164672937
Short name T936
Test name
Test status
Simulation time 324307810 ps
CPU time 5.48 seconds
Started Mar 03 02:03:12 PM PST 24
Finished Mar 03 02:03:18 PM PST 24
Peak memory 213744 kb
Host smart-39a3aa92-c683-41ba-b9a1-15e4f995e50d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164672937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.1164672937
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.4132805962
Short name T961
Test name
Test status
Simulation time 37214196 ps
CPU time 0.84 seconds
Started Mar 03 02:04:02 PM PST 24
Finished Mar 03 02:04:03 PM PST 24
Peak memory 205232 kb
Host smart-29a0d259-ef17-4d1c-a18f-d1c32c225440
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132805962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.4132805962
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.2551843297
Short name T994
Test name
Test status
Simulation time 61750561 ps
CPU time 0.89 seconds
Started Mar 03 02:04:03 PM PST 24
Finished Mar 03 02:04:04 PM PST 24
Peak memory 205216 kb
Host smart-ff1b4945-4335-4f9f-b15d-12d5a7c21ffb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551843297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.2551843297
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.2778448383
Short name T914
Test name
Test status
Simulation time 11409379 ps
CPU time 0.78 seconds
Started Mar 03 02:04:03 PM PST 24
Finished Mar 03 02:04:04 PM PST 24
Peak memory 205228 kb
Host smart-a1fe01d3-0699-4a5d-b8ec-6b6a7030db7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2778448383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.2778448383
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.1488691611
Short name T967
Test name
Test status
Simulation time 20958783 ps
CPU time 0.77 seconds
Started Mar 03 02:04:01 PM PST 24
Finished Mar 03 02:04:02 PM PST 24
Peak memory 205388 kb
Host smart-2f76105f-5a7d-490c-80f8-9fb7d327e210
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488691611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.1488691611
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.1720700422
Short name T995
Test name
Test status
Simulation time 8802285 ps
CPU time 0.8 seconds
Started Mar 03 02:04:02 PM PST 24
Finished Mar 03 02:04:03 PM PST 24
Peak memory 205224 kb
Host smart-61677d30-8b4f-4a0a-a1a6-232a4ba10056
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720700422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.1720700422
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.1902650796
Short name T1029
Test name
Test status
Simulation time 41483563 ps
CPU time 0.87 seconds
Started Mar 03 02:04:02 PM PST 24
Finished Mar 03 02:04:04 PM PST 24
Peak memory 205248 kb
Host smart-af9d9c23-a34f-4268-9506-9c41139891c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1902650796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.1902650796
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.358826195
Short name T1017
Test name
Test status
Simulation time 11431255 ps
CPU time 0.72 seconds
Started Mar 03 02:04:00 PM PST 24
Finished Mar 03 02:04:01 PM PST 24
Peak memory 205360 kb
Host smart-1f462600-171f-49f9-bac3-d06f571d02d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=358826195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.358826195
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.1043966954
Short name T1074
Test name
Test status
Simulation time 10350544 ps
CPU time 0.67 seconds
Started Mar 03 02:04:00 PM PST 24
Finished Mar 03 02:04:01 PM PST 24
Peak memory 205340 kb
Host smart-6f0b4b89-1766-40aa-97d5-d60685be3a6b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1043966954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.1043966954
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.774233025
Short name T993
Test name
Test status
Simulation time 12843050 ps
CPU time 0.74 seconds
Started Mar 03 02:04:00 PM PST 24
Finished Mar 03 02:04:02 PM PST 24
Peak memory 205252 kb
Host smart-8132310c-f4d8-4033-b466-16ea036e5281
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774233025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.774233025
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.1911051890
Short name T1010
Test name
Test status
Simulation time 8642226 ps
CPU time 0.84 seconds
Started Mar 03 02:04:02 PM PST 24
Finished Mar 03 02:04:04 PM PST 24
Peak memory 205260 kb
Host smart-cf1c8f8b-1106-47fd-9a0a-df288f6c82a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911051890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.1911051890
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.195290041
Short name T1033
Test name
Test status
Simulation time 85622777 ps
CPU time 1.53 seconds
Started Mar 03 02:03:22 PM PST 24
Finished Mar 03 02:03:25 PM PST 24
Peak memory 213692 kb
Host smart-9b71fc4b-bb9d-4e86-97b9-f24d8f881928
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195290041 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.195290041
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.627573926
Short name T1046
Test name
Test status
Simulation time 28763316 ps
CPU time 1.15 seconds
Started Mar 03 02:03:15 PM PST 24
Finished Mar 03 02:03:16 PM PST 24
Peak memory 205712 kb
Host smart-ec75acd7-6e0f-4272-9c59-c87477563cbc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627573926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.627573926
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.1731951717
Short name T958
Test name
Test status
Simulation time 52144516 ps
CPU time 0.85 seconds
Started Mar 03 02:03:13 PM PST 24
Finished Mar 03 02:03:14 PM PST 24
Peak memory 205244 kb
Host smart-146eaee6-bbdc-45ba-80e0-caa6cf8cc0cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1731951717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.1731951717
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.2652380454
Short name T131
Test name
Test status
Simulation time 108131945 ps
CPU time 2.43 seconds
Started Mar 03 02:03:13 PM PST 24
Finished Mar 03 02:03:16 PM PST 24
Peak memory 205696 kb
Host smart-bb208d67-8074-448c-996e-758dfedda376
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2652380454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.2652380454
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.2012037071
Short name T990
Test name
Test status
Simulation time 240909984 ps
CPU time 3.91 seconds
Started Mar 03 02:03:12 PM PST 24
Finished Mar 03 02:03:16 PM PST 24
Peak memory 222344 kb
Host smart-f658e320-74e9-418c-969f-7352e498bc12
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012037071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.2012037071
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.3070796973
Short name T981
Test name
Test status
Simulation time 335614918 ps
CPU time 4.11 seconds
Started Mar 03 02:03:15 PM PST 24
Finished Mar 03 02:03:20 PM PST 24
Peak memory 214048 kb
Host smart-11098d4f-20d3-4707-b676-33abde25ff10
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070796973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
keymgr_shadow_reg_errors_with_csr_rw.3070796973
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.2329093121
Short name T1016
Test name
Test status
Simulation time 419232847 ps
CPU time 3.31 seconds
Started Mar 03 02:03:12 PM PST 24
Finished Mar 03 02:03:15 PM PST 24
Peak memory 213868 kb
Host smart-58336bf5-7c71-4016-a0b6-0a0c64b2eb42
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329093121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.2329093121
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.3017873096
Short name T1043
Test name
Test status
Simulation time 113331263 ps
CPU time 1.13 seconds
Started Mar 03 02:03:17 PM PST 24
Finished Mar 03 02:03:18 PM PST 24
Peak memory 205556 kb
Host smart-f9adddf0-e5c0-435b-a52a-87181b517067
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017873096 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.3017873096
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.2613468592
Short name T1063
Test name
Test status
Simulation time 14880804 ps
CPU time 1.11 seconds
Started Mar 03 02:03:25 PM PST 24
Finished Mar 03 02:03:27 PM PST 24
Peak memory 205608 kb
Host smart-1c107a24-e00f-43a1-9404-2f9be596f8f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2613468592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.2613468592
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.496542470
Short name T1030
Test name
Test status
Simulation time 13116293 ps
CPU time 0.77 seconds
Started Mar 03 02:03:18 PM PST 24
Finished Mar 03 02:03:19 PM PST 24
Peak memory 205336 kb
Host smart-2fcad87d-8037-4c56-b055-e7338ff5ad06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=496542470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.496542470
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.544439092
Short name T1057
Test name
Test status
Simulation time 136258136 ps
CPU time 1.99 seconds
Started Mar 03 02:03:19 PM PST 24
Finished Mar 03 02:03:22 PM PST 24
Peak memory 205544 kb
Host smart-cd378d52-d4cb-47e0-b892-df1b8321e7b2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=544439092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sam
e_csr_outstanding.544439092
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.610246674
Short name T105
Test name
Test status
Simulation time 215203223 ps
CPU time 3.9 seconds
Started Mar 03 02:03:21 PM PST 24
Finished Mar 03 02:03:25 PM PST 24
Peak memory 214048 kb
Host smart-e29f429c-f403-49aa-8068-0f607e56faf1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=610246674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shadow
_reg_errors.610246674
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.709986052
Short name T1055
Test name
Test status
Simulation time 417868695 ps
CPU time 5.32 seconds
Started Mar 03 02:03:20 PM PST 24
Finished Mar 03 02:03:25 PM PST 24
Peak memory 214104 kb
Host smart-3c38784d-29eb-49fa-8352-7cee8acf80d9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709986052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.k
eymgr_shadow_reg_errors_with_csr_rw.709986052
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.139813335
Short name T997
Test name
Test status
Simulation time 28815405 ps
CPU time 2.36 seconds
Started Mar 03 02:03:21 PM PST 24
Finished Mar 03 02:03:23 PM PST 24
Peak memory 213844 kb
Host smart-cb782c4c-fb91-4458-8db6-84630317bae8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139813335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.139813335
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.3518105710
Short name T1071
Test name
Test status
Simulation time 1648845450 ps
CPU time 7.48 seconds
Started Mar 03 02:03:20 PM PST 24
Finished Mar 03 02:03:28 PM PST 24
Peak memory 208424 kb
Host smart-3ba99546-503e-467d-a403-6468fd463e44
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518105710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.3518105710
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.2801076675
Short name T939
Test name
Test status
Simulation time 65064812 ps
CPU time 1.38 seconds
Started Mar 03 02:03:21 PM PST 24
Finished Mar 03 02:03:22 PM PST 24
Peak memory 213852 kb
Host smart-f1bc7004-f84c-458a-a3aa-5918e1c871e4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801076675 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.2801076675
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.1127211137
Short name T912
Test name
Test status
Simulation time 17704872 ps
CPU time 1.09 seconds
Started Mar 03 02:03:21 PM PST 24
Finished Mar 03 02:03:23 PM PST 24
Peak memory 205504 kb
Host smart-fe813ec1-59b4-40b6-aeff-0d36e50a2589
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1127211137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.1127211137
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.3578290852
Short name T908
Test name
Test status
Simulation time 23536523 ps
CPU time 0.92 seconds
Started Mar 03 02:03:18 PM PST 24
Finished Mar 03 02:03:19 PM PST 24
Peak memory 205344 kb
Host smart-255bc980-aa5d-46e4-8a87-1ec5a7652440
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578290852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.3578290852
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.1074470785
Short name T129
Test name
Test status
Simulation time 395783802 ps
CPU time 2.66 seconds
Started Mar 03 02:03:24 PM PST 24
Finished Mar 03 02:03:27 PM PST 24
Peak memory 205628 kb
Host smart-f12a40a5-acfe-470f-9d4b-63e2472a0932
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1074470785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.1074470785
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.1702317049
Short name T1005
Test name
Test status
Simulation time 840152437 ps
CPU time 4.09 seconds
Started Mar 03 02:03:21 PM PST 24
Finished Mar 03 02:03:26 PM PST 24
Peak memory 214004 kb
Host smart-3a59f673-bbf2-4b44-af59-d7fae24c234c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702317049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.1702317049
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.2092052447
Short name T1015
Test name
Test status
Simulation time 960377055 ps
CPU time 6.64 seconds
Started Mar 03 02:03:21 PM PST 24
Finished Mar 03 02:03:29 PM PST 24
Peak memory 219652 kb
Host smart-cb41922e-6729-4474-b9cb-22d2df9ea55f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092052447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
keymgr_shadow_reg_errors_with_csr_rw.2092052447
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.1855139091
Short name T181
Test name
Test status
Simulation time 134828059 ps
CPU time 3.11 seconds
Started Mar 03 02:03:22 PM PST 24
Finished Mar 03 02:03:26 PM PST 24
Peak memory 213548 kb
Host smart-23b435e1-c4f8-4f53-904e-50849eb516aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855139091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.1855139091
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.1341433444
Short name T921
Test name
Test status
Simulation time 410360386 ps
CPU time 5.58 seconds
Started Mar 03 02:03:20 PM PST 24
Finished Mar 03 02:03:26 PM PST 24
Peak memory 213784 kb
Host smart-136a652b-f56e-453b-973b-4fbdf0a4d2f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341433444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.1341433444
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.2086292367
Short name T1027
Test name
Test status
Simulation time 52090049 ps
CPU time 2.29 seconds
Started Mar 03 02:03:25 PM PST 24
Finished Mar 03 02:03:29 PM PST 24
Peak memory 213952 kb
Host smart-171c25d3-9475-469d-81e5-64dde93f0ef2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086292367 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.2086292367
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.546707054
Short name T949
Test name
Test status
Simulation time 26571247 ps
CPU time 1.11 seconds
Started Mar 03 02:03:18 PM PST 24
Finished Mar 03 02:03:19 PM PST 24
Peak memory 205608 kb
Host smart-c9250f4a-f223-432f-9a44-e19d6e481d7f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546707054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.546707054
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.820885074
Short name T957
Test name
Test status
Simulation time 11320935 ps
CPU time 0.86 seconds
Started Mar 03 02:03:18 PM PST 24
Finished Mar 03 02:03:19 PM PST 24
Peak memory 205324 kb
Host smart-93a97a28-6180-4025-bc7d-e3e54967385c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820885074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.820885074
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.227514018
Short name T1011
Test name
Test status
Simulation time 513354464 ps
CPU time 3.04 seconds
Started Mar 03 02:03:20 PM PST 24
Finished Mar 03 02:03:23 PM PST 24
Peak memory 205568 kb
Host smart-33dd7ecb-0003-492a-8ad7-28e535ddec82
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227514018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sam
e_csr_outstanding.227514018
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.2050962927
Short name T1014
Test name
Test status
Simulation time 135968465 ps
CPU time 2.5 seconds
Started Mar 03 02:03:21 PM PST 24
Finished Mar 03 02:03:25 PM PST 24
Peak memory 213924 kb
Host smart-a2789bb3-47e9-4fe9-9fad-b50828b9a674
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2050962927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.2050962927
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.1537075211
Short name T1009
Test name
Test status
Simulation time 570400958 ps
CPU time 6.77 seconds
Started Mar 03 02:03:25 PM PST 24
Finished Mar 03 02:03:33 PM PST 24
Peak memory 220056 kb
Host smart-84bcf4a2-978a-4ba4-9be6-0fbfec964bd9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537075211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
keymgr_shadow_reg_errors_with_csr_rw.1537075211
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.636806412
Short name T932
Test name
Test status
Simulation time 590521607 ps
CPU time 5.79 seconds
Started Mar 03 02:03:21 PM PST 24
Finished Mar 03 02:03:27 PM PST 24
Peak memory 213796 kb
Host smart-db52129a-59c9-4604-8d86-384bb21de185
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=636806412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.636806412
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.2645926093
Short name T136
Test name
Test status
Simulation time 880343248 ps
CPU time 7.4 seconds
Started Mar 03 02:03:22 PM PST 24
Finished Mar 03 02:03:30 PM PST 24
Peak memory 209000 kb
Host smart-c82d5334-9837-4afb-9ba0-ed1374b7adb8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2645926093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.2645926093
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.4122934452
Short name T1056
Test name
Test status
Simulation time 80884298 ps
CPU time 1.93 seconds
Started Mar 03 02:03:26 PM PST 24
Finished Mar 03 02:03:28 PM PST 24
Peak memory 213956 kb
Host smart-c5b9de72-090c-4c90-aba7-2c8830dbcdb4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4122934452 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.4122934452
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.2450816035
Short name T1060
Test name
Test status
Simulation time 53523398 ps
CPU time 1.06 seconds
Started Mar 03 02:03:28 PM PST 24
Finished Mar 03 02:03:29 PM PST 24
Peak memory 205624 kb
Host smart-df01a469-c809-426f-94e2-e6d90bfb1d8b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450816035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.2450816035
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.1961271042
Short name T970
Test name
Test status
Simulation time 29946722 ps
CPU time 0.69 seconds
Started Mar 03 02:03:26 PM PST 24
Finished Mar 03 02:03:27 PM PST 24
Peak memory 205256 kb
Host smart-f184a6fa-04dc-4f17-838c-c9069d31574f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961271042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.1961271042
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.4146910240
Short name T998
Test name
Test status
Simulation time 74011815 ps
CPU time 1.45 seconds
Started Mar 03 02:03:30 PM PST 24
Finished Mar 03 02:03:31 PM PST 24
Peak memory 205620 kb
Host smart-4d95ceb7-8a5b-4cc6-b313-c25a916c06d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146910240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.4146910240
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.3329625489
Short name T1066
Test name
Test status
Simulation time 268341249 ps
CPU time 5.41 seconds
Started Mar 03 02:03:20 PM PST 24
Finished Mar 03 02:03:26 PM PST 24
Peak memory 214140 kb
Host smart-eec28073-cc84-4719-bc31-d4922d2ccbbb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329625489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.3329625489
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.2654613366
Short name T1022
Test name
Test status
Simulation time 637123206 ps
CPU time 6.83 seconds
Started Mar 03 02:03:27 PM PST 24
Finished Mar 03 02:03:34 PM PST 24
Peak memory 219664 kb
Host smart-3055da38-a8a6-4b0f-a803-d094f10ba967
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2654613366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.2654613366
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.3372620949
Short name T940
Test name
Test status
Simulation time 111793099 ps
CPU time 1.96 seconds
Started Mar 03 02:03:26 PM PST 24
Finished Mar 03 02:03:28 PM PST 24
Peak memory 213904 kb
Host smart-18b24dcf-decb-4274-8b30-e0e7fb985449
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3372620949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.3372620949
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.3965425805
Short name T142
Test name
Test status
Simulation time 1220023716 ps
CPU time 23.57 seconds
Started Mar 03 02:03:27 PM PST 24
Finished Mar 03 02:03:50 PM PST 24
Peak memory 208812 kb
Host smart-ae9160d9-dc61-4582-9b42-3327e2e1553a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965425805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.3965425805
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.2911867826
Short name T572
Test name
Test status
Simulation time 51422964 ps
CPU time 0.92 seconds
Started Mar 03 02:33:36 PM PST 24
Finished Mar 03 02:33:37 PM PST 24
Peak memory 205612 kb
Host smart-0571b39a-4f8d-49a6-b1cf-e9aa8e48292b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911867826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.2911867826
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.2975492673
Short name T648
Test name
Test status
Simulation time 357160808 ps
CPU time 4.53 seconds
Started Mar 03 02:33:32 PM PST 24
Finished Mar 03 02:33:36 PM PST 24
Peak memory 217928 kb
Host smart-739ef0ed-eb0c-48d2-87a2-af27703f3d88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975492673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.2975492673
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.252479194
Short name T801
Test name
Test status
Simulation time 47359406 ps
CPU time 2.22 seconds
Started Mar 03 02:33:37 PM PST 24
Finished Mar 03 02:33:39 PM PST 24
Peak memory 207168 kb
Host smart-cca4559f-8e07-42c5-9ab0-ccec83f7d432
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=252479194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.252479194
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.3944988252
Short name T662
Test name
Test status
Simulation time 1307801591 ps
CPU time 38.38 seconds
Started Mar 03 02:33:32 PM PST 24
Finished Mar 03 02:34:11 PM PST 24
Peak memory 218300 kb
Host smart-be9ad31b-e964-4a80-b39c-fb8a61053663
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944988252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.3944988252
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.2119984933
Short name T780
Test name
Test status
Simulation time 5797562574 ps
CPU time 44.19 seconds
Started Mar 03 02:33:33 PM PST 24
Finished Mar 03 02:34:17 PM PST 24
Peak memory 222020 kb
Host smart-a0337863-b02f-4bda-b80c-445d7d55b2ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2119984933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.2119984933
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.3035138760
Short name T53
Test name
Test status
Simulation time 309284014 ps
CPU time 5.07 seconds
Started Mar 03 02:33:37 PM PST 24
Finished Mar 03 02:33:43 PM PST 24
Peak memory 209352 kb
Host smart-f74e7a61-cced-4ded-a692-d7594a17cd83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035138760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.3035138760
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.510508152
Short name T608
Test name
Test status
Simulation time 8529792895 ps
CPU time 80.76 seconds
Started Mar 03 02:33:34 PM PST 24
Finished Mar 03 02:34:55 PM PST 24
Peak memory 218072 kb
Host smart-3468c913-c2d4-4fdc-8903-70ad092741f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510508152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.510508152
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sideload.579303038
Short name T742
Test name
Test status
Simulation time 60445596 ps
CPU time 2.88 seconds
Started Mar 03 02:33:28 PM PST 24
Finished Mar 03 02:33:31 PM PST 24
Peak memory 207316 kb
Host smart-5cfa54d1-ebea-4d49-9c94-099103aa0956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579303038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.579303038
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.3583493621
Short name T315
Test name
Test status
Simulation time 77489679 ps
CPU time 2.26 seconds
Started Mar 03 02:33:28 PM PST 24
Finished Mar 03 02:33:30 PM PST 24
Peak memory 206100 kb
Host smart-d834e298-7748-4632-aff6-06b45db59ada
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583493621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.3583493621
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.371683700
Short name T520
Test name
Test status
Simulation time 118326453 ps
CPU time 5.15 seconds
Started Mar 03 02:33:29 PM PST 24
Finished Mar 03 02:33:34 PM PST 24
Peak memory 206220 kb
Host smart-3fd0b6b3-fbd5-45c1-97d2-1a06b219e3d5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=371683700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.371683700
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.3614546054
Short name T460
Test name
Test status
Simulation time 115612637 ps
CPU time 4.11 seconds
Started Mar 03 02:33:32 PM PST 24
Finished Mar 03 02:33:37 PM PST 24
Peak memory 207372 kb
Host smart-4fea7616-b986-4465-bac4-75514480f9cb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614546054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.3614546054
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.3233069892
Short name T705
Test name
Test status
Simulation time 165347486 ps
CPU time 4.56 seconds
Started Mar 03 02:33:32 PM PST 24
Finished Mar 03 02:33:37 PM PST 24
Peak memory 208676 kb
Host smart-cea42c7a-a231-4fec-be2d-7cdf42c198b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3233069892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.3233069892
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.3723833028
Short name T507
Test name
Test status
Simulation time 152177321 ps
CPU time 3.51 seconds
Started Mar 03 02:33:27 PM PST 24
Finished Mar 03 02:33:31 PM PST 24
Peak memory 206396 kb
Host smart-8cc6c110-e5c5-4d0b-9241-cc002b19a455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723833028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.3723833028
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.948717674
Short name T808
Test name
Test status
Simulation time 915537334 ps
CPU time 10.5 seconds
Started Mar 03 02:33:32 PM PST 24
Finished Mar 03 02:33:43 PM PST 24
Peak memory 208264 kb
Host smart-501d3572-8d7b-4746-b48d-bf4b8d16bcb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948717674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.948717674
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.57734611
Short name T743
Test name
Test status
Simulation time 132657584 ps
CPU time 2.22 seconds
Started Mar 03 02:33:32 PM PST 24
Finished Mar 03 02:33:35 PM PST 24
Peak memory 209284 kb
Host smart-89bd0c08-f77e-46a2-b31c-b4a3faefd4dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57734611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.57734611
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.3672991593
Short name T816
Test name
Test status
Simulation time 48255703 ps
CPU time 0.87 seconds
Started Mar 03 02:33:39 PM PST 24
Finished Mar 03 02:33:40 PM PST 24
Peak memory 205532 kb
Host smart-bc5a9028-5ab8-4528-b5ff-17108c8b6ac5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3672991593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.3672991593
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.3327818659
Short name T320
Test name
Test status
Simulation time 165829661 ps
CPU time 3.52 seconds
Started Mar 03 02:33:36 PM PST 24
Finished Mar 03 02:33:40 PM PST 24
Peak memory 214544 kb
Host smart-0edb97a2-6517-4f89-8696-66177992605d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3327818659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.3327818659
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.785145507
Short name T44
Test name
Test status
Simulation time 174887216 ps
CPU time 2.51 seconds
Started Mar 03 02:33:36 PM PST 24
Finished Mar 03 02:33:38 PM PST 24
Peak memory 213864 kb
Host smart-87a211c3-954d-48d0-9638-f87dffea690b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=785145507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.785145507
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.758283142
Short name T286
Test name
Test status
Simulation time 1113613601 ps
CPU time 5.15 seconds
Started Mar 03 02:33:40 PM PST 24
Finished Mar 03 02:33:46 PM PST 24
Peak memory 213804 kb
Host smart-71b87e4d-492d-4b93-b32f-902e5f3462f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758283142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.758283142
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.722564684
Short name T87
Test name
Test status
Simulation time 394205664 ps
CPU time 6.49 seconds
Started Mar 03 02:33:42 PM PST 24
Finished Mar 03 02:33:48 PM PST 24
Peak memory 221968 kb
Host smart-57d41d9f-8515-4a00-ac60-42681957a38b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722564684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.722564684
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.645054980
Short name T62
Test name
Test status
Simulation time 92645813 ps
CPU time 4.25 seconds
Started Mar 03 02:33:34 PM PST 24
Finished Mar 03 02:33:38 PM PST 24
Peak memory 208696 kb
Host smart-c94518fc-d477-4315-be0a-0584983fa0d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645054980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.645054980
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.3548455676
Short name T284
Test name
Test status
Simulation time 97490856 ps
CPU time 4.75 seconds
Started Mar 03 02:33:33 PM PST 24
Finished Mar 03 02:33:38 PM PST 24
Peak memory 213788 kb
Host smart-be066cd8-9883-46ac-8a0b-62f9d693fac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3548455676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.3548455676
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.1216537483
Short name T12
Test name
Test status
Simulation time 1030744415 ps
CPU time 19.06 seconds
Started Mar 03 02:33:37 PM PST 24
Finished Mar 03 02:33:56 PM PST 24
Peak memory 234604 kb
Host smart-896dd82d-cd5f-4c43-ad22-a4cf9e9dfafd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216537483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.1216537483
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload.4015445733
Short name T812
Test name
Test status
Simulation time 254983764 ps
CPU time 4.63 seconds
Started Mar 03 02:33:33 PM PST 24
Finished Mar 03 02:33:37 PM PST 24
Peak memory 207664 kb
Host smart-ed830b3c-040d-4312-beae-3fff7ea8615c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015445733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.4015445733
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.4025311412
Short name T798
Test name
Test status
Simulation time 49218326 ps
CPU time 2.9 seconds
Started Mar 03 02:33:34 PM PST 24
Finished Mar 03 02:33:37 PM PST 24
Peak memory 206908 kb
Host smart-d6520e74-af56-42fa-a04f-d27a7677a3dd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4025311412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.4025311412
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.1185012012
Short name T628
Test name
Test status
Simulation time 793136629 ps
CPU time 5.93 seconds
Started Mar 03 02:33:32 PM PST 24
Finished Mar 03 02:33:38 PM PST 24
Peak memory 208024 kb
Host smart-29ee1549-657c-4155-8194-98b43e311a8e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185012012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.1185012012
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.1965030346
Short name T470
Test name
Test status
Simulation time 190411733 ps
CPU time 4.02 seconds
Started Mar 03 02:33:34 PM PST 24
Finished Mar 03 02:33:38 PM PST 24
Peak memory 207252 kb
Host smart-3477f762-11fc-4b51-ab52-d7d3915569c1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965030346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.1965030346
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.1722817767
Short name T500
Test name
Test status
Simulation time 51914022 ps
CPU time 2.6 seconds
Started Mar 03 02:33:41 PM PST 24
Finished Mar 03 02:33:43 PM PST 24
Peak memory 208580 kb
Host smart-1eb64625-f41f-4c5c-9b18-5df8b5349fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1722817767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.1722817767
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.2501527808
Short name T133
Test name
Test status
Simulation time 72054125 ps
CPU time 3.25 seconds
Started Mar 03 02:33:37 PM PST 24
Finished Mar 03 02:33:40 PM PST 24
Peak memory 207752 kb
Host smart-9f70502c-b789-41b5-9729-0a93c796f03c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501527808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.2501527808
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.1055511316
Short name T827
Test name
Test status
Simulation time 194234961 ps
CPU time 9.85 seconds
Started Mar 03 02:33:41 PM PST 24
Finished Mar 03 02:33:51 PM PST 24
Peak memory 215580 kb
Host smart-9a9c1ecb-daf1-47cc-8d94-2a8a9bac680a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1055511316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.1055511316
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_stress_all_with_rand_reset.2056387038
Short name T48
Test name
Test status
Simulation time 232466141 ps
CPU time 10.74 seconds
Started Mar 03 02:33:42 PM PST 24
Finished Mar 03 02:33:53 PM PST 24
Peak memory 222104 kb
Host smart-bf890142-2f79-40b6-9a92-bed8a4b0cdd2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056387038 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all_with_rand_reset.2056387038
Directory /workspace/1.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.3731550869
Short name T265
Test name
Test status
Simulation time 364938559 ps
CPU time 7.96 seconds
Started Mar 03 02:33:39 PM PST 24
Finished Mar 03 02:33:47 PM PST 24
Peak memory 217844 kb
Host smart-bb1195f1-472d-441d-aed7-a062ba091c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731550869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.3731550869
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.155411755
Short name T146
Test name
Test status
Simulation time 72190935 ps
CPU time 1.26 seconds
Started Mar 03 02:33:42 PM PST 24
Finished Mar 03 02:33:43 PM PST 24
Peak memory 208948 kb
Host smart-feef32e7-dc41-4847-bd7c-ab5929b076e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155411755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.155411755
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.3320235654
Short name T590
Test name
Test status
Simulation time 16360786 ps
CPU time 0.94 seconds
Started Mar 03 02:34:22 PM PST 24
Finished Mar 03 02:34:24 PM PST 24
Peak memory 205576 kb
Host smart-f45a9b5c-2849-4d66-9125-ec6845f912ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3320235654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.3320235654
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.2084202140
Short name T407
Test name
Test status
Simulation time 115638402 ps
CPU time 4.17 seconds
Started Mar 03 02:34:23 PM PST 24
Finished Mar 03 02:34:28 PM PST 24
Peak memory 214808 kb
Host smart-04cc46d8-065f-4277-a6e3-2b4e66e61fea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2084202140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.2084202140
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.1371155308
Short name T317
Test name
Test status
Simulation time 151978789 ps
CPU time 1.81 seconds
Started Mar 03 02:34:26 PM PST 24
Finished Mar 03 02:34:28 PM PST 24
Peak memory 209124 kb
Host smart-5d0a1644-a75d-41cf-900b-f052caee41f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371155308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.1371155308
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.505138619
Short name T84
Test name
Test status
Simulation time 2445283189 ps
CPU time 9.57 seconds
Started Mar 03 02:34:24 PM PST 24
Finished Mar 03 02:34:34 PM PST 24
Peak memory 209336 kb
Host smart-5ac69f96-92b3-490a-a54c-b9f32e046f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=505138619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.505138619
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.3239751225
Short name T566
Test name
Test status
Simulation time 427308110 ps
CPU time 5.75 seconds
Started Mar 03 02:34:22 PM PST 24
Finished Mar 03 02:34:29 PM PST 24
Peak memory 213896 kb
Host smart-3e56c435-d730-4d1d-91ae-2bfa587c7683
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3239751225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.3239751225
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.2474116945
Short name T122
Test name
Test status
Simulation time 193527634 ps
CPU time 3.36 seconds
Started Mar 03 02:34:22 PM PST 24
Finished Mar 03 02:34:27 PM PST 24
Peak memory 206968 kb
Host smart-d5ac0115-5628-4d4d-8ba3-bc4ad91a119f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474116945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.2474116945
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.3561956456
Short name T844
Test name
Test status
Simulation time 2437924386 ps
CPU time 9.77 seconds
Started Mar 03 02:34:22 PM PST 24
Finished Mar 03 02:34:33 PM PST 24
Peak memory 207512 kb
Host smart-76fa6faa-b640-4e6b-a457-47fa84e9daba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561956456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.3561956456
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.2080544723
Short name T815
Test name
Test status
Simulation time 834072195 ps
CPU time 26.2 seconds
Started Mar 03 02:34:26 PM PST 24
Finished Mar 03 02:34:54 PM PST 24
Peak memory 207948 kb
Host smart-b8556586-7321-4d79-b7aa-d73fbe5ab456
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2080544723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.2080544723
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.1288468592
Short name T751
Test name
Test status
Simulation time 81409736 ps
CPU time 3.2 seconds
Started Mar 03 02:34:24 PM PST 24
Finished Mar 03 02:34:28 PM PST 24
Peak memory 206176 kb
Host smart-0c9d918b-192c-4f5d-a20f-ef0b0be5209a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288468592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.1288468592
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.3825996379
Short name T760
Test name
Test status
Simulation time 660930524 ps
CPU time 7.88 seconds
Started Mar 03 02:34:26 PM PST 24
Finished Mar 03 02:34:34 PM PST 24
Peak memory 207276 kb
Host smart-bd508baa-40c6-4b10-bb58-8f49195f28c7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825996379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.3825996379
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.2147195427
Short name T789
Test name
Test status
Simulation time 161337108 ps
CPU time 3.23 seconds
Started Mar 03 02:34:24 PM PST 24
Finished Mar 03 02:34:28 PM PST 24
Peak memory 209696 kb
Host smart-668f5905-ac5a-4ca6-b98d-90547f055372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147195427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.2147195427
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.3689180773
Short name T545
Test name
Test status
Simulation time 459404765 ps
CPU time 3.39 seconds
Started Mar 03 02:34:16 PM PST 24
Finished Mar 03 02:34:20 PM PST 24
Peak memory 206064 kb
Host smart-1ccb625d-e6aa-4c41-b58d-c9e13233a319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689180773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.3689180773
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.3217817452
Short name T809
Test name
Test status
Simulation time 5184556622 ps
CPU time 57.63 seconds
Started Mar 03 02:34:25 PM PST 24
Finished Mar 03 02:35:23 PM PST 24
Peak memory 209388 kb
Host smart-88476e1c-ce35-4714-aeab-cb517e99f378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217817452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.3217817452
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.899756582
Short name T561
Test name
Test status
Simulation time 60093045 ps
CPU time 2.29 seconds
Started Mar 03 02:34:22 PM PST 24
Finished Mar 03 02:34:26 PM PST 24
Peak memory 210044 kb
Host smart-55512356-9f94-48cf-b80e-f7f6680e0099
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899756582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.899756582
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.1226701719
Short name T622
Test name
Test status
Simulation time 78616064 ps
CPU time 0.89 seconds
Started Mar 03 02:34:42 PM PST 24
Finished Mar 03 02:34:43 PM PST 24
Peak memory 205600 kb
Host smart-d686e2de-a9ec-465c-981e-e2d690bdb96d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226701719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.1226701719
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.3166188949
Short name T822
Test name
Test status
Simulation time 168119862 ps
CPU time 2.94 seconds
Started Mar 03 02:34:42 PM PST 24
Finished Mar 03 02:34:45 PM PST 24
Peak memory 214060 kb
Host smart-df7c9405-5cee-4f6d-ba4f-5f0203d9bdee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166188949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.3166188949
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.2233958240
Short name T180
Test name
Test status
Simulation time 71919873 ps
CPU time 1.62 seconds
Started Mar 03 02:34:24 PM PST 24
Finished Mar 03 02:34:27 PM PST 24
Peak memory 207016 kb
Host smart-d1ff373e-73a6-498a-8ffb-f07eed2ea0e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233958240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.2233958240
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.1856775571
Short name T21
Test name
Test status
Simulation time 2946316115 ps
CPU time 52.51 seconds
Started Mar 03 02:34:43 PM PST 24
Finished Mar 03 02:35:35 PM PST 24
Peak memory 213804 kb
Host smart-712f7ec7-566d-4780-b245-86d1016eb51f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1856775571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.1856775571
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.604110627
Short name T820
Test name
Test status
Simulation time 2403113306 ps
CPU time 89.49 seconds
Started Mar 03 02:34:42 PM PST 24
Finished Mar 03 02:36:12 PM PST 24
Peak memory 220364 kb
Host smart-973ef734-a4e5-4b02-bd81-8308e52ee10a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604110627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.604110627
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.4014322026
Short name T478
Test name
Test status
Simulation time 164211008 ps
CPU time 3.12 seconds
Started Mar 03 02:34:25 PM PST 24
Finished Mar 03 02:34:29 PM PST 24
Peak memory 209524 kb
Host smart-d400307f-5563-4518-880a-21bfabe64294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4014322026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.4014322026
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.2192623075
Short name T570
Test name
Test status
Simulation time 9413071869 ps
CPU time 94.66 seconds
Started Mar 03 02:34:25 PM PST 24
Finished Mar 03 02:36:00 PM PST 24
Peak memory 207976 kb
Host smart-bc915fe1-844c-4652-8140-5b54bd26a113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192623075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.2192623075
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.1489973800
Short name T707
Test name
Test status
Simulation time 140492162 ps
CPU time 2.3 seconds
Started Mar 03 02:34:24 PM PST 24
Finished Mar 03 02:34:27 PM PST 24
Peak memory 207796 kb
Host smart-621815e9-e5ea-46db-b159-57e4808c6a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489973800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.1489973800
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.3768266600
Short name T79
Test name
Test status
Simulation time 207872656 ps
CPU time 2.27 seconds
Started Mar 03 02:34:24 PM PST 24
Finished Mar 03 02:34:27 PM PST 24
Peak memory 208288 kb
Host smart-0ee77456-cbe9-4e26-b0ff-6a89e270084a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3768266600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.3768266600
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.377789851
Short name T271
Test name
Test status
Simulation time 63431636 ps
CPU time 2.43 seconds
Started Mar 03 02:34:24 PM PST 24
Finished Mar 03 02:34:27 PM PST 24
Peak memory 208092 kb
Host smart-b56b630e-9f42-419c-820f-6e3ac032c76f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377789851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.377789851
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.298199733
Short name T582
Test name
Test status
Simulation time 179729616 ps
CPU time 2.63 seconds
Started Mar 03 02:34:26 PM PST 24
Finished Mar 03 02:34:31 PM PST 24
Peak memory 206212 kb
Host smart-b659ed22-f48a-4f26-9209-06c22c8a3694
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298199733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.298199733
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.2664990558
Short name T16
Test name
Test status
Simulation time 547377666 ps
CPU time 5.68 seconds
Started Mar 03 02:34:43 PM PST 24
Finished Mar 03 02:34:49 PM PST 24
Peak memory 208524 kb
Host smart-9e3ad3bc-644e-4e7b-ade0-7286d4b5d99a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664990558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.2664990558
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.2056095169
Short name T695
Test name
Test status
Simulation time 152772063 ps
CPU time 4.51 seconds
Started Mar 03 02:34:25 PM PST 24
Finished Mar 03 02:34:30 PM PST 24
Peak memory 207624 kb
Host smart-28904752-d220-4fce-9286-338653088c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056095169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.2056095169
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.2490618828
Short name T223
Test name
Test status
Simulation time 5589865453 ps
CPU time 78.77 seconds
Started Mar 03 02:34:42 PM PST 24
Finished Mar 03 02:36:01 PM PST 24
Peak memory 222132 kb
Host smart-08faf6ae-48c0-4b30-91a3-0fa8be7122d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490618828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.2490618828
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_stress_all_with_rand_reset.1764866416
Short name T170
Test name
Test status
Simulation time 1053376110 ps
CPU time 12.87 seconds
Started Mar 03 02:34:41 PM PST 24
Finished Mar 03 02:34:54 PM PST 24
Peak memory 222128 kb
Host smart-f6dee87e-0471-43e0-879b-8860abc11a2e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764866416 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all_with_rand_reset.1764866416
Directory /workspace/11.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.1380934694
Short name T429
Test name
Test status
Simulation time 179682262 ps
CPU time 4.68 seconds
Started Mar 03 02:34:28 PM PST 24
Finished Mar 03 02:34:33 PM PST 24
Peak memory 207920 kb
Host smart-adab8fe7-d939-412d-ae28-79fea979222e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380934694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.1380934694
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.101292844
Short name T670
Test name
Test status
Simulation time 12091325 ps
CPU time 0.9 seconds
Started Mar 03 02:34:45 PM PST 24
Finished Mar 03 02:34:46 PM PST 24
Peak memory 205612 kb
Host smart-be4e6d37-27ff-4ef9-ade6-70c3e2d980f3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101292844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.101292844
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.1660579718
Short name T834
Test name
Test status
Simulation time 113348822 ps
CPU time 2.79 seconds
Started Mar 03 02:34:41 PM PST 24
Finished Mar 03 02:34:43 PM PST 24
Peak memory 213864 kb
Host smart-32f42c64-d427-4ed5-a48f-499f62f71eb7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1660579718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.1660579718
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.2400844177
Short name T367
Test name
Test status
Simulation time 243989373 ps
CPU time 5.01 seconds
Started Mar 03 02:34:44 PM PST 24
Finished Mar 03 02:34:49 PM PST 24
Peak memory 220932 kb
Host smart-2da97af1-e506-47d2-8522-93d99180b491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400844177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.2400844177
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.1827680975
Short name T711
Test name
Test status
Simulation time 22978148 ps
CPU time 1.59 seconds
Started Mar 03 02:34:41 PM PST 24
Finished Mar 03 02:34:43 PM PST 24
Peak memory 206760 kb
Host smart-358043d4-6102-454a-b041-0a3305b1bd38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1827680975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.1827680975
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.365299696
Short name T490
Test name
Test status
Simulation time 5994936010 ps
CPU time 19.12 seconds
Started Mar 03 02:34:42 PM PST 24
Finished Mar 03 02:35:02 PM PST 24
Peak memory 218880 kb
Host smart-aafec991-ea55-42ab-99d7-c43b0519a852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365299696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.365299696
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.3741612276
Short name T856
Test name
Test status
Simulation time 2030721115 ps
CPU time 9.37 seconds
Started Mar 03 02:34:40 PM PST 24
Finished Mar 03 02:34:50 PM PST 24
Peak memory 213812 kb
Host smart-f90b9039-d093-4c57-acfa-39cfc82d6a37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741612276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.3741612276
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.864801671
Short name T848
Test name
Test status
Simulation time 66291890 ps
CPU time 3.22 seconds
Started Mar 03 02:34:43 PM PST 24
Finished Mar 03 02:34:46 PM PST 24
Peak memory 208432 kb
Host smart-837b310a-193e-4132-af42-0729f0492b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864801671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.864801671
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.3041591903
Short name T327
Test name
Test status
Simulation time 372251805 ps
CPU time 5.08 seconds
Started Mar 03 02:34:44 PM PST 24
Finished Mar 03 02:34:49 PM PST 24
Peak memory 206148 kb
Host smart-be9c34bd-9246-4dbe-abbc-3b174c65b368
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041591903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.3041591903
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.2067615047
Short name T663
Test name
Test status
Simulation time 924781841 ps
CPU time 4.46 seconds
Started Mar 03 02:34:42 PM PST 24
Finished Mar 03 02:34:46 PM PST 24
Peak memory 207696 kb
Host smart-f427af7e-5c7a-4003-8f60-35b28201da7d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2067615047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.2067615047
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.1532141955
Short name T574
Test name
Test status
Simulation time 127355856 ps
CPU time 2.2 seconds
Started Mar 03 02:34:41 PM PST 24
Finished Mar 03 02:34:44 PM PST 24
Peak memory 208104 kb
Host smart-32d52ef1-f945-4158-a2bf-504f31c8b0d7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532141955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.1532141955
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.3497014327
Short name T501
Test name
Test status
Simulation time 72946342 ps
CPU time 3.15 seconds
Started Mar 03 02:34:39 PM PST 24
Finished Mar 03 02:34:43 PM PST 24
Peak memory 206204 kb
Host smart-0df9bcec-829e-4e5e-952c-b18f90a12ddf
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497014327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.3497014327
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.2326885863
Short name T565
Test name
Test status
Simulation time 104303213 ps
CPU time 2.69 seconds
Started Mar 03 02:34:42 PM PST 24
Finished Mar 03 02:34:45 PM PST 24
Peak memory 213852 kb
Host smart-620cdf20-8ed4-4453-aec3-540af156672c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326885863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.2326885863
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.563959135
Short name T839
Test name
Test status
Simulation time 1025067247 ps
CPU time 2.9 seconds
Started Mar 03 02:34:42 PM PST 24
Finished Mar 03 02:34:45 PM PST 24
Peak memory 206120 kb
Host smart-986ff4c3-4a46-4521-beb5-9221c6778ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563959135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.563959135
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.2489944828
Short name T311
Test name
Test status
Simulation time 586816642 ps
CPU time 25.27 seconds
Started Mar 03 02:34:40 PM PST 24
Finished Mar 03 02:35:06 PM PST 24
Peak memory 220728 kb
Host smart-f2d428bf-dac9-4856-b419-b920402e05cf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489944828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.2489944828
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_stress_all_with_rand_reset.3373492952
Short name T773
Test name
Test status
Simulation time 324180131 ps
CPU time 11.52 seconds
Started Mar 03 02:34:45 PM PST 24
Finished Mar 03 02:34:56 PM PST 24
Peak memory 222188 kb
Host smart-0525dc54-414e-4028-abf9-38e4a657b66b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3373492952 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all_with_rand_reset.3373492952
Directory /workspace/12.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.4024070085
Short name T256
Test name
Test status
Simulation time 487744552 ps
CPU time 4.37 seconds
Started Mar 03 02:34:41 PM PST 24
Finished Mar 03 02:34:46 PM PST 24
Peak memory 206184 kb
Host smart-78d15640-0341-4d42-a976-f175c5a2801e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4024070085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.4024070085
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.2921530735
Short name T414
Test name
Test status
Simulation time 1111765927 ps
CPU time 14.48 seconds
Started Mar 03 02:34:40 PM PST 24
Finished Mar 03 02:34:55 PM PST 24
Peak memory 210464 kb
Host smart-a2ec36d2-434d-4bf8-8d97-76532ade2de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921530735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.2921530735
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.3918844430
Short name T25
Test name
Test status
Simulation time 89401870 ps
CPU time 3.23 seconds
Started Mar 03 02:34:42 PM PST 24
Finished Mar 03 02:34:46 PM PST 24
Peak memory 220924 kb
Host smart-574a1321-6ff8-4e9d-a554-6d53f462b695
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3918844430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.3918844430
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.2423211825
Short name T584
Test name
Test status
Simulation time 59952161 ps
CPU time 3.16 seconds
Started Mar 03 02:34:41 PM PST 24
Finished Mar 03 02:34:44 PM PST 24
Peak memory 209424 kb
Host smart-c95991fb-42f6-41fc-8cfa-c54f6e58184d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2423211825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.2423211825
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.1944188992
Short name T322
Test name
Test status
Simulation time 394831522 ps
CPU time 3.86 seconds
Started Mar 03 02:34:45 PM PST 24
Finished Mar 03 02:34:49 PM PST 24
Peak memory 208044 kb
Host smart-5f14c1fd-47b5-48ab-bfc2-ce9443e881fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944188992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.1944188992
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.2656810557
Short name T764
Test name
Test status
Simulation time 77719461 ps
CPU time 3.02 seconds
Started Mar 03 02:34:38 PM PST 24
Finished Mar 03 02:34:41 PM PST 24
Peak memory 209544 kb
Host smart-3c7c29fe-7e9f-4f64-91e6-b9c817e5e385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656810557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.2656810557
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.548760228
Short name T657
Test name
Test status
Simulation time 93611982 ps
CPU time 2.96 seconds
Started Mar 03 02:34:42 PM PST 24
Finished Mar 03 02:34:45 PM PST 24
Peak memory 206880 kb
Host smart-40e819e8-43eb-4a75-8518-4c4f099a4d06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=548760228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.548760228
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.531498394
Short name T378
Test name
Test status
Simulation time 232903454 ps
CPU time 6.73 seconds
Started Mar 03 02:34:39 PM PST 24
Finished Mar 03 02:34:46 PM PST 24
Peak memory 207632 kb
Host smart-5fad40ed-cd55-4e0a-a91a-44badb0beefb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531498394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.531498394
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.2678770205
Short name T636
Test name
Test status
Simulation time 537933627 ps
CPU time 7.6 seconds
Started Mar 03 02:34:42 PM PST 24
Finished Mar 03 02:34:50 PM PST 24
Peak memory 205888 kb
Host smart-2615f985-0c6e-43be-8285-7ab8562fe120
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2678770205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.2678770205
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.2380440452
Short name T464
Test name
Test status
Simulation time 180011942 ps
CPU time 6.86 seconds
Started Mar 03 02:34:41 PM PST 24
Finished Mar 03 02:34:48 PM PST 24
Peak memory 207872 kb
Host smart-9923094e-ba0d-495d-b1bc-6e4dfa329159
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2380440452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.2380440452
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.2750213137
Short name T829
Test name
Test status
Simulation time 51380487 ps
CPU time 2.61 seconds
Started Mar 03 02:34:40 PM PST 24
Finished Mar 03 02:34:43 PM PST 24
Peak memory 208768 kb
Host smart-a7c8be54-6943-4f5e-a9bd-c2b5c9bcaf4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2750213137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.2750213137
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.3192238767
Short name T445
Test name
Test status
Simulation time 1036672938 ps
CPU time 7.21 seconds
Started Mar 03 02:34:39 PM PST 24
Finished Mar 03 02:34:46 PM PST 24
Peak memory 205956 kb
Host smart-f85bbc38-c505-4925-a999-8f9ae4680fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192238767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.3192238767
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all_with_rand_reset.2395404508
Short name T859
Test name
Test status
Simulation time 622719233 ps
CPU time 14.23 seconds
Started Mar 03 02:34:40 PM PST 24
Finished Mar 03 02:34:55 PM PST 24
Peak memory 222200 kb
Host smart-9df7a9ed-d45b-4f95-8384-0d4d0abc4237
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2395404508 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all_with_rand_reset.2395404508
Directory /workspace/13.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.2909317572
Short name T889
Test name
Test status
Simulation time 112150321 ps
CPU time 4.95 seconds
Started Mar 03 02:34:43 PM PST 24
Finished Mar 03 02:34:48 PM PST 24
Peak memory 218004 kb
Host smart-dd6eca91-8275-4fc6-8a96-0ec608ddbb79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909317572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.2909317572
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.544838112
Short name T753
Test name
Test status
Simulation time 1239370888 ps
CPU time 8.68 seconds
Started Mar 03 02:34:40 PM PST 24
Finished Mar 03 02:34:49 PM PST 24
Peak memory 209432 kb
Host smart-6bc3151f-f337-4ed7-a79d-9782af3b42de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=544838112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.544838112
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.43936311
Short name T569
Test name
Test status
Simulation time 24073248 ps
CPU time 0.73 seconds
Started Mar 03 02:34:43 PM PST 24
Finished Mar 03 02:34:44 PM PST 24
Peak memory 205616 kb
Host smart-818daaf9-7181-4a96-9091-6dbd651b81d1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43936311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.43936311
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.4022385042
Short name T10
Test name
Test status
Simulation time 118978264 ps
CPU time 4.11 seconds
Started Mar 03 02:34:43 PM PST 24
Finished Mar 03 02:34:48 PM PST 24
Peak memory 214020 kb
Host smart-7cd9b572-237f-44c8-94cd-87c3e959b4fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022385042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.4022385042
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.3931415472
Short name T626
Test name
Test status
Simulation time 87159368 ps
CPU time 2.26 seconds
Started Mar 03 02:34:42 PM PST 24
Finished Mar 03 02:34:45 PM PST 24
Peak memory 208304 kb
Host smart-ec3f77e2-ad3d-4383-bba4-f85dd90ef562
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3931415472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.3931415472
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.2794150636
Short name T352
Test name
Test status
Simulation time 56172186 ps
CPU time 3.58 seconds
Started Mar 03 02:34:41 PM PST 24
Finished Mar 03 02:34:45 PM PST 24
Peak memory 210360 kb
Host smart-7dcaf803-ff97-42df-ba05-ef77a16584aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2794150636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.2794150636
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.524270598
Short name T508
Test name
Test status
Simulation time 99296068 ps
CPU time 4.74 seconds
Started Mar 03 02:34:38 PM PST 24
Finished Mar 03 02:34:43 PM PST 24
Peak memory 214360 kb
Host smart-7ae20a0e-f914-4e63-8fb5-20bf1b34eb8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524270598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.524270598
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.2531928805
Short name T290
Test name
Test status
Simulation time 327395096 ps
CPU time 3.68 seconds
Started Mar 03 02:34:41 PM PST 24
Finished Mar 03 02:34:45 PM PST 24
Peak memory 209120 kb
Host smart-c5036700-f30a-41ac-8c13-f9bdbcafa318
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531928805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.2531928805
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.540852398
Short name T15
Test name
Test status
Simulation time 1042451533 ps
CPU time 8.18 seconds
Started Mar 03 02:34:39 PM PST 24
Finished Mar 03 02:34:47 PM PST 24
Peak memory 207600 kb
Host smart-2df325f8-b83c-450e-9f5e-7437bf398315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540852398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.540852398
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.2859897868
Short name T439
Test name
Test status
Simulation time 539342521 ps
CPU time 14.1 seconds
Started Mar 03 02:34:40 PM PST 24
Finished Mar 03 02:34:54 PM PST 24
Peak memory 207240 kb
Host smart-43d4d6c1-04f8-47c6-95bb-d86841c18aab
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2859897868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.2859897868
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.1832581441
Short name T380
Test name
Test status
Simulation time 153367892 ps
CPU time 3.83 seconds
Started Mar 03 02:34:40 PM PST 24
Finished Mar 03 02:34:44 PM PST 24
Peak memory 208156 kb
Host smart-5c32a6a4-e56f-4751-bc6b-b3a0c60ebd37
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832581441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.1832581441
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.2436589077
Short name T616
Test name
Test status
Simulation time 214231929 ps
CPU time 3.13 seconds
Started Mar 03 02:34:45 PM PST 24
Finished Mar 03 02:34:48 PM PST 24
Peak memory 207052 kb
Host smart-7bb3be33-2f20-4f72-ad9d-9f3175e57221
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436589077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.2436589077
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.163260653
Short name T553
Test name
Test status
Simulation time 262360195 ps
CPU time 3.47 seconds
Started Mar 03 02:34:39 PM PST 24
Finished Mar 03 02:34:43 PM PST 24
Peak memory 207200 kb
Host smart-771b7a7e-b59d-45e4-a102-a962b36c7b71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163260653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.163260653
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.3400048567
Short name T473
Test name
Test status
Simulation time 184176020 ps
CPU time 5.03 seconds
Started Mar 03 02:34:41 PM PST 24
Finished Mar 03 02:34:46 PM PST 24
Peak memory 208244 kb
Host smart-1115a5e8-5561-4c7d-b76a-f3646314c46e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3400048567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.3400048567
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.3293746431
Short name T227
Test name
Test status
Simulation time 131537754 ps
CPU time 4.98 seconds
Started Mar 03 02:34:44 PM PST 24
Finished Mar 03 02:34:49 PM PST 24
Peak memory 208924 kb
Host smart-09a37c0f-0d02-4cc3-b29e-99c9119dbaa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3293746431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.3293746431
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.3584034122
Short name T618
Test name
Test status
Simulation time 487957727 ps
CPU time 5.59 seconds
Started Mar 03 02:34:39 PM PST 24
Finished Mar 03 02:34:45 PM PST 24
Peak memory 210312 kb
Host smart-73fef8c7-c7fb-49d8-94bf-db5d723ce0dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584034122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.3584034122
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.1202465562
Short name T850
Test name
Test status
Simulation time 17904317 ps
CPU time 0.97 seconds
Started Mar 03 02:34:50 PM PST 24
Finished Mar 03 02:34:51 PM PST 24
Peak memory 205600 kb
Host smart-d30f922e-af7a-4b53-bda4-18f535a7f1ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1202465562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.1202465562
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.1714763578
Short name T175
Test name
Test status
Simulation time 35195368 ps
CPU time 2.71 seconds
Started Mar 03 02:34:48 PM PST 24
Finished Mar 03 02:34:51 PM PST 24
Peak memory 213816 kb
Host smart-3b3ba6d3-e975-4f19-9cbd-a1fcc3e08f12
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1714763578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.1714763578
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.3606240202
Short name T619
Test name
Test status
Simulation time 264215387 ps
CPU time 9.13 seconds
Started Mar 03 02:34:54 PM PST 24
Finished Mar 03 02:35:05 PM PST 24
Peak memory 213792 kb
Host smart-df2e029d-bd74-4f9e-8fd1-26df30d51214
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606240202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.3606240202
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.1273443440
Short name T68
Test name
Test status
Simulation time 54265206 ps
CPU time 3.08 seconds
Started Mar 03 02:34:45 PM PST 24
Finished Mar 03 02:34:48 PM PST 24
Peak memory 209320 kb
Host smart-08ca4b78-dd91-45f0-8139-6fa0c0a29696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273443440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.1273443440
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.1486741256
Short name T323
Test name
Test status
Simulation time 291064900 ps
CPU time 3.98 seconds
Started Mar 03 02:34:43 PM PST 24
Finished Mar 03 02:34:47 PM PST 24
Peak memory 208580 kb
Host smart-c1a2e887-f9b9-4b3c-88d3-9abacac44c81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486741256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.1486741256
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.3227778186
Short name T842
Test name
Test status
Simulation time 366288805 ps
CPU time 5.74 seconds
Started Mar 03 02:34:47 PM PST 24
Finished Mar 03 02:34:54 PM PST 24
Peak memory 209540 kb
Host smart-9b96e175-5953-4bbb-ac34-5d35b0f254ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227778186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.3227778186
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.1876564712
Short name T697
Test name
Test status
Simulation time 87080701 ps
CPU time 3.59 seconds
Started Mar 03 02:34:44 PM PST 24
Finished Mar 03 02:34:48 PM PST 24
Peak memory 208608 kb
Host smart-ef01b909-11b0-4ad6-adef-a08cae1cac61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876564712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.1876564712
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.862820675
Short name T862
Test name
Test status
Simulation time 76880134 ps
CPU time 3.86 seconds
Started Mar 03 02:34:43 PM PST 24
Finished Mar 03 02:34:47 PM PST 24
Peak memory 213872 kb
Host smart-7fca7ccd-cf50-488e-9504-adac467f7540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862820675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.862820675
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.1449131990
Short name T302
Test name
Test status
Simulation time 97669156 ps
CPU time 2.14 seconds
Started Mar 03 02:34:44 PM PST 24
Finished Mar 03 02:34:46 PM PST 24
Peak memory 208048 kb
Host smart-006c2197-93a6-4082-932b-331925dd2646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1449131990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.1449131990
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.2309271438
Short name T499
Test name
Test status
Simulation time 162650169 ps
CPU time 2.44 seconds
Started Mar 03 02:34:44 PM PST 24
Finished Mar 03 02:34:47 PM PST 24
Peak memory 206228 kb
Host smart-ae10177b-4e49-4922-a5e6-2ba44c4726b3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2309271438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.2309271438
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.463653717
Short name T293
Test name
Test status
Simulation time 64507185 ps
CPU time 3.21 seconds
Started Mar 03 02:34:47 PM PST 24
Finished Mar 03 02:34:52 PM PST 24
Peak memory 206212 kb
Host smart-c126613d-f262-407b-a2b5-b2a829dbef01
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463653717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.463653717
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.978899480
Short name T456
Test name
Test status
Simulation time 2324715782 ps
CPU time 23.66 seconds
Started Mar 03 02:34:44 PM PST 24
Finished Mar 03 02:35:08 PM PST 24
Peak memory 207392 kb
Host smart-16786521-b8ee-4cad-911a-34a7a4808eaa
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=978899480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.978899480
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.1036163533
Short name T481
Test name
Test status
Simulation time 72603804 ps
CPU time 2.2 seconds
Started Mar 03 02:34:53 PM PST 24
Finished Mar 03 02:34:57 PM PST 24
Peak memory 207248 kb
Host smart-a0d12b63-ac59-415d-a789-9c9083b15f31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1036163533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.1036163533
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.3336739432
Short name T484
Test name
Test status
Simulation time 138616944 ps
CPU time 4.3 seconds
Started Mar 03 02:34:45 PM PST 24
Finished Mar 03 02:34:49 PM PST 24
Peak memory 207148 kb
Host smart-288b9356-3e86-4890-8081-32e5b3424981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336739432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.3336739432
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.2732227418
Short name T811
Test name
Test status
Simulation time 2286034974 ps
CPU time 29.81 seconds
Started Mar 03 02:34:59 PM PST 24
Finished Mar 03 02:35:34 PM PST 24
Peak memory 220488 kb
Host smart-727c3400-362f-4ea2-938d-186733cdd2d0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732227418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.2732227418
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.1484786058
Short name T891
Test name
Test status
Simulation time 190575820 ps
CPU time 7.32 seconds
Started Mar 03 02:34:55 PM PST 24
Finished Mar 03 02:35:03 PM PST 24
Peak memory 219692 kb
Host smart-afbad621-8625-478f-8cf5-bad2a364d0cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484786058 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.1484786058
Directory /workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.2305258725
Short name T522
Test name
Test status
Simulation time 900250004 ps
CPU time 22.94 seconds
Started Mar 03 02:34:42 PM PST 24
Finished Mar 03 02:35:06 PM PST 24
Peak memory 213864 kb
Host smart-b2e2c5a0-0c31-4102-8d83-256450e1b426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305258725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.2305258725
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.585119093
Short name T646
Test name
Test status
Simulation time 201245000 ps
CPU time 3.15 seconds
Started Mar 03 02:34:52 PM PST 24
Finished Mar 03 02:34:56 PM PST 24
Peak memory 209636 kb
Host smart-e5e30b25-4a25-49b5-8bc6-dfbb33d7fd42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=585119093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.585119093
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.1660228248
Short name T770
Test name
Test status
Simulation time 16915326 ps
CPU time 0.83 seconds
Started Mar 03 02:35:00 PM PST 24
Finished Mar 03 02:35:05 PM PST 24
Peak memory 205452 kb
Host smart-939943b7-c3d4-4307-bef6-a5916d98c231
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660228248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.1660228248
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.1522218720
Short name T32
Test name
Test status
Simulation time 1690320141 ps
CPU time 4.82 seconds
Started Mar 03 02:34:53 PM PST 24
Finished Mar 03 02:34:58 PM PST 24
Peak memory 222488 kb
Host smart-466cf359-3267-4d48-99b5-b21767452a4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522218720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.1522218720
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.2383886917
Short name T71
Test name
Test status
Simulation time 415662122 ps
CPU time 3.55 seconds
Started Mar 03 02:34:55 PM PST 24
Finished Mar 03 02:35:00 PM PST 24
Peak memory 213724 kb
Host smart-20157c75-0153-433b-83c3-e900df288ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383886917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.2383886917
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.3134404962
Short name T604
Test name
Test status
Simulation time 10742860561 ps
CPU time 59.63 seconds
Started Mar 03 02:34:52 PM PST 24
Finished Mar 03 02:35:53 PM PST 24
Peak memory 219340 kb
Host smart-764447a0-64b1-4be7-94f1-bff6928b8008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3134404962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.3134404962
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.3202397449
Short name T201
Test name
Test status
Simulation time 72287081 ps
CPU time 3.65 seconds
Started Mar 03 02:34:53 PM PST 24
Finished Mar 03 02:34:58 PM PST 24
Peak memory 215380 kb
Host smart-c0200cbf-ef0a-4ea6-a506-fa6678e303c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202397449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.3202397449
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_sideload.2332158086
Short name T454
Test name
Test status
Simulation time 122747310 ps
CPU time 2.2 seconds
Started Mar 03 02:34:53 PM PST 24
Finished Mar 03 02:34:56 PM PST 24
Peak memory 206012 kb
Host smart-da3516df-edd6-402e-97f3-af5fddeb662c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332158086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.2332158086
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.1832557362
Short name T802
Test name
Test status
Simulation time 342666328 ps
CPU time 6.81 seconds
Started Mar 03 02:34:56 PM PST 24
Finished Mar 03 02:35:05 PM PST 24
Peak memory 207856 kb
Host smart-5174c8bb-03c3-4176-bbaa-d9c0f575dfba
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832557362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.1832557362
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.572851236
Short name T601
Test name
Test status
Simulation time 248759014 ps
CPU time 3.14 seconds
Started Mar 03 02:34:53 PM PST 24
Finished Mar 03 02:34:57 PM PST 24
Peak memory 206192 kb
Host smart-a3972adc-026c-4869-abaf-253878b4d333
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572851236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.572851236
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.3970232656
Short name T632
Test name
Test status
Simulation time 378502999 ps
CPU time 4.8 seconds
Started Mar 03 02:34:52 PM PST 24
Finished Mar 03 02:34:58 PM PST 24
Peak memory 206184 kb
Host smart-6751e1e7-dc4d-432a-9432-e48e3d63f4be
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970232656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.3970232656
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.129360293
Short name T544
Test name
Test status
Simulation time 128292631 ps
CPU time 2.42 seconds
Started Mar 03 02:34:55 PM PST 24
Finished Mar 03 02:34:59 PM PST 24
Peak memory 208392 kb
Host smart-c4fbd8b0-0253-4732-bdd1-8308b7c7707f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=129360293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.129360293
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.1596625645
Short name T694
Test name
Test status
Simulation time 312827886 ps
CPU time 2.71 seconds
Started Mar 03 02:34:52 PM PST 24
Finished Mar 03 02:34:56 PM PST 24
Peak memory 206168 kb
Host smart-50306f9e-ed49-4fe4-9443-b95b94c81145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596625645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.1596625645
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.2617572568
Short name T96
Test name
Test status
Simulation time 1093458357 ps
CPU time 6.78 seconds
Started Mar 03 02:34:55 PM PST 24
Finished Mar 03 02:35:02 PM PST 24
Peak memory 207508 kb
Host smart-54a3e3be-e33c-4c3f-a761-c394a9f9a0cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617572568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.2617572568
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.244440737
Short name T381
Test name
Test status
Simulation time 89789735 ps
CPU time 3.53 seconds
Started Mar 03 02:34:54 PM PST 24
Finished Mar 03 02:34:59 PM PST 24
Peak memory 209220 kb
Host smart-22a688ce-eac9-4d3e-ae86-13c3f6c76e22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244440737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.244440737
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.3489553913
Short name T537
Test name
Test status
Simulation time 57417272 ps
CPU time 0.76 seconds
Started Mar 03 02:34:59 PM PST 24
Finished Mar 03 02:35:05 PM PST 24
Peak memory 205528 kb
Host smart-f67ba53d-9e40-4e91-a3bf-1718904f9ed4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489553913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.3489553913
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.1504274306
Short name T393
Test name
Test status
Simulation time 95942510 ps
CPU time 3.84 seconds
Started Mar 03 02:34:55 PM PST 24
Finished Mar 03 02:35:01 PM PST 24
Peak memory 215136 kb
Host smart-a6e2fd78-9561-46a2-b3d2-8c9d0c2018da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1504274306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.1504274306
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.1849686516
Short name T177
Test name
Test status
Simulation time 1246561042 ps
CPU time 26.37 seconds
Started Mar 03 02:34:57 PM PST 24
Finished Mar 03 02:35:29 PM PST 24
Peak memory 213804 kb
Host smart-a7ff686d-7a07-4ab6-bcf8-a590d1a0d9fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849686516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.1849686516
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.4150047935
Short name T740
Test name
Test status
Simulation time 822889836 ps
CPU time 6.06 seconds
Started Mar 03 02:34:55 PM PST 24
Finished Mar 03 02:35:02 PM PST 24
Peak memory 213664 kb
Host smart-7e7e13d6-c67b-4c56-9a28-028948c4f5ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150047935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.4150047935
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.3112237641
Short name T190
Test name
Test status
Simulation time 880294596 ps
CPU time 4.77 seconds
Started Mar 03 02:34:54 PM PST 24
Finished Mar 03 02:35:01 PM PST 24
Peak memory 210268 kb
Host smart-61387991-3907-48d0-a30a-bb5f3f96a8cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3112237641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.3112237641
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_sideload.2382610646
Short name T667
Test name
Test status
Simulation time 111661181 ps
CPU time 3.65 seconds
Started Mar 03 02:34:54 PM PST 24
Finished Mar 03 02:34:59 PM PST 24
Peak memory 207852 kb
Host smart-3187bfcd-120d-43a7-a6e3-968e0a9633c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382610646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.2382610646
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.1823592832
Short name T324
Test name
Test status
Simulation time 597054877 ps
CPU time 6.69 seconds
Started Mar 03 02:34:57 PM PST 24
Finished Mar 03 02:35:10 PM PST 24
Peak memory 208380 kb
Host smart-532f0d25-44ee-4591-85a5-c3bd7b6e8f2c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1823592832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.1823592832
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.4123025666
Short name T538
Test name
Test status
Simulation time 238602251 ps
CPU time 6.87 seconds
Started Mar 03 02:34:54 PM PST 24
Finished Mar 03 02:35:02 PM PST 24
Peak memory 207216 kb
Host smart-e11b77ba-29f5-4eab-9f26-0efaa54fd335
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123025666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.4123025666
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.1614251924
Short name T432
Test name
Test status
Simulation time 224083973 ps
CPU time 4.87 seconds
Started Mar 03 02:34:55 PM PST 24
Finished Mar 03 02:35:01 PM PST 24
Peak memory 208324 kb
Host smart-dd7824bf-70dc-493f-8b1f-97d3952cbfc3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1614251924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.1614251924
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.1112881348
Short name T303
Test name
Test status
Simulation time 47168578 ps
CPU time 3.04 seconds
Started Mar 03 02:34:52 PM PST 24
Finished Mar 03 02:34:56 PM PST 24
Peak memory 208836 kb
Host smart-53b51938-cfdd-48c1-a5c9-59bc7e2f3ee0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1112881348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.1112881348
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.2349525915
Short name T861
Test name
Test status
Simulation time 105039124 ps
CPU time 4.58 seconds
Started Mar 03 02:34:56 PM PST 24
Finished Mar 03 02:35:01 PM PST 24
Peak memory 207852 kb
Host smart-0f8b1263-74e8-46ff-b17b-160a8cc94acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349525915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.2349525915
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.628707194
Short name T298
Test name
Test status
Simulation time 3471647350 ps
CPU time 67.93 seconds
Started Mar 03 02:34:55 PM PST 24
Finished Mar 03 02:36:04 PM PST 24
Peak memory 208228 kb
Host smart-02ea20e6-f1c1-4c50-ade9-0d44e99b2c51
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628707194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.628707194
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.3568678824
Short name T234
Test name
Test status
Simulation time 94597772 ps
CPU time 4.87 seconds
Started Mar 03 02:34:57 PM PST 24
Finished Mar 03 02:35:06 PM PST 24
Peak memory 213828 kb
Host smart-6ad6a7b6-b78f-4502-a6de-52b0144323f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3568678824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.3568678824
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.1124271933
Short name T485
Test name
Test status
Simulation time 230674600 ps
CPU time 2.22 seconds
Started Mar 03 02:34:55 PM PST 24
Finished Mar 03 02:34:58 PM PST 24
Peak memory 209836 kb
Host smart-26ba7caa-faa8-42a8-8845-ddc619d792ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124271933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.1124271933
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.2301787299
Short name T541
Test name
Test status
Simulation time 25098082 ps
CPU time 0.87 seconds
Started Mar 03 02:35:02 PM PST 24
Finished Mar 03 02:35:05 PM PST 24
Peak memory 205600 kb
Host smart-782a5200-f80a-4a19-b819-d9fc77346f0e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2301787299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.2301787299
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.3244907585
Short name T29
Test name
Test status
Simulation time 231733819 ps
CPU time 2.63 seconds
Started Mar 03 02:35:08 PM PST 24
Finished Mar 03 02:35:10 PM PST 24
Peak memory 209080 kb
Host smart-14570394-eefe-4629-ba50-8d8bfe42d77d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244907585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.3244907585
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.632361942
Short name T573
Test name
Test status
Simulation time 73910607 ps
CPU time 2.93 seconds
Started Mar 03 02:35:08 PM PST 24
Finished Mar 03 02:35:11 PM PST 24
Peak memory 208064 kb
Host smart-2fd1cfca-fbf7-4f4c-ba25-3bb0a8ecc5fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=632361942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.632361942
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.2773283760
Short name T679
Test name
Test status
Simulation time 139541541 ps
CPU time 5.05 seconds
Started Mar 03 02:35:00 PM PST 24
Finished Mar 03 02:35:09 PM PST 24
Peak memory 208904 kb
Host smart-88518be2-339c-487e-830f-d315a134064b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773283760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.2773283760
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.3486706624
Short name T510
Test name
Test status
Simulation time 189979454 ps
CPU time 2.6 seconds
Started Mar 03 02:35:07 PM PST 24
Finished Mar 03 02:35:09 PM PST 24
Peak memory 220172 kb
Host smart-ce1a848e-0ea7-4f8d-9e24-c8626c4b41f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486706624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.3486706624
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.559228081
Short name T593
Test name
Test status
Simulation time 188816637 ps
CPU time 5.1 seconds
Started Mar 03 02:34:58 PM PST 24
Finished Mar 03 02:35:08 PM PST 24
Peak memory 209628 kb
Host smart-2bbbf66a-87c2-43ba-aad2-6fe366625c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=559228081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.559228081
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.4240840344
Short name T661
Test name
Test status
Simulation time 878740225 ps
CPU time 3.8 seconds
Started Mar 03 02:34:59 PM PST 24
Finished Mar 03 02:35:08 PM PST 24
Peak memory 206124 kb
Host smart-67688d2e-107b-40bd-a3c2-fa53494ecfd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4240840344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.4240840344
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.4040880853
Short name T673
Test name
Test status
Simulation time 478873209 ps
CPU time 5.75 seconds
Started Mar 03 02:35:09 PM PST 24
Finished Mar 03 02:35:15 PM PST 24
Peak memory 207440 kb
Host smart-9ca408b7-8bb1-422f-a940-b58527db364a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040880853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.4040880853
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.311615438
Short name T78
Test name
Test status
Simulation time 356674483 ps
CPU time 3.06 seconds
Started Mar 03 02:34:59 PM PST 24
Finished Mar 03 02:35:08 PM PST 24
Peak memory 206124 kb
Host smart-54f2045b-0def-4eeb-95e9-56fb44b922c0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=311615438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.311615438
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.1641290757
Short name T766
Test name
Test status
Simulation time 33207468 ps
CPU time 2.44 seconds
Started Mar 03 02:34:59 PM PST 24
Finished Mar 03 02:35:06 PM PST 24
Peak memory 206736 kb
Host smart-21d42251-2b6a-4fd4-b58c-02a21f08cd79
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641290757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.1641290757
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.3937322700
Short name T621
Test name
Test status
Simulation time 116414057 ps
CPU time 3.04 seconds
Started Mar 03 02:35:08 PM PST 24
Finished Mar 03 02:35:11 PM PST 24
Peak memory 207824 kb
Host smart-68cb738c-0870-4a53-9cbb-8da535be1e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937322700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.3937322700
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.3898812422
Short name T775
Test name
Test status
Simulation time 68612608 ps
CPU time 1.76 seconds
Started Mar 03 02:34:55 PM PST 24
Finished Mar 03 02:34:57 PM PST 24
Peak memory 206200 kb
Host smart-9adef8e0-a2da-46d5-b1df-96b26f6133a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898812422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.3898812422
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.4079386173
Short name T301
Test name
Test status
Simulation time 5704058766 ps
CPU time 69.41 seconds
Started Mar 03 02:35:06 PM PST 24
Finished Mar 03 02:36:15 PM PST 24
Peak memory 222096 kb
Host smart-efbb5a8f-b82c-463b-9cee-a7059611bd99
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079386173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.4079386173
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.3258205474
Short name T254
Test name
Test status
Simulation time 116481172 ps
CPU time 4.09 seconds
Started Mar 03 02:35:10 PM PST 24
Finished Mar 03 02:35:14 PM PST 24
Peak memory 209364 kb
Host smart-945f05bd-6000-4ad9-9d37-b8d359812f75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3258205474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.3258205474
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.2788692736
Short name T685
Test name
Test status
Simulation time 110169244 ps
CPU time 2.62 seconds
Started Mar 03 02:35:00 PM PST 24
Finished Mar 03 02:35:07 PM PST 24
Peak memory 209772 kb
Host smart-f7812add-ce35-4928-b0c4-52165c05fd17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788692736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.2788692736
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.3664076697
Short name T732
Test name
Test status
Simulation time 14078960 ps
CPU time 0.79 seconds
Started Mar 03 02:35:02 PM PST 24
Finished Mar 03 02:35:06 PM PST 24
Peak memory 205596 kb
Host smart-10c2b7c2-f5e7-4597-9ffd-228bb21057e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664076697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.3664076697
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.3474405957
Short name T716
Test name
Test status
Simulation time 159317764 ps
CPU time 6.92 seconds
Started Mar 03 02:35:08 PM PST 24
Finished Mar 03 02:35:15 PM PST 24
Peak memory 209572 kb
Host smart-2379c668-5496-4d01-bccb-928063bdafa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3474405957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.3474405957
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.3805463688
Short name T66
Test name
Test status
Simulation time 139805202 ps
CPU time 3 seconds
Started Mar 03 02:35:10 PM PST 24
Finished Mar 03 02:35:13 PM PST 24
Peak memory 209352 kb
Host smart-f80ab0f8-496b-4752-8834-48cdfbbdf767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805463688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.3805463688
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.444041419
Short name T722
Test name
Test status
Simulation time 1170952548 ps
CPU time 9.2 seconds
Started Mar 03 02:35:07 PM PST 24
Finished Mar 03 02:35:17 PM PST 24
Peak memory 218732 kb
Host smart-f1347bb4-7fce-4972-ad03-77ecc44c5fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444041419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.444041419
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.3005154189
Short name T222
Test name
Test status
Simulation time 163681514 ps
CPU time 4.63 seconds
Started Mar 03 02:35:06 PM PST 24
Finished Mar 03 02:35:11 PM PST 24
Peak memory 219772 kb
Host smart-0e77f58b-d11b-4e4a-be0d-8240a2a48673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005154189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.3005154189
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.3940024397
Short name T242
Test name
Test status
Simulation time 180385037 ps
CPU time 3.2 seconds
Started Mar 03 02:35:08 PM PST 24
Finished Mar 03 02:35:11 PM PST 24
Peak memory 217688 kb
Host smart-e75f68b6-f9ad-435a-9522-87fce28b993b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940024397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.3940024397
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.2801364642
Short name T525
Test name
Test status
Simulation time 67644705 ps
CPU time 2.78 seconds
Started Mar 03 02:35:02 PM PST 24
Finished Mar 03 02:35:09 PM PST 24
Peak memory 206260 kb
Host smart-5dff64ac-8f7f-40a2-8ef5-5f6e88a21aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801364642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.2801364642
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.2366450018
Short name T524
Test name
Test status
Simulation time 43138714 ps
CPU time 1.81 seconds
Started Mar 03 02:35:08 PM PST 24
Finished Mar 03 02:35:10 PM PST 24
Peak memory 206188 kb
Host smart-7b79406a-68b8-4d2d-953d-1ffeee741460
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366450018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.2366450018
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.603313081
Short name T178
Test name
Test status
Simulation time 182165021 ps
CPU time 2.76 seconds
Started Mar 03 02:35:07 PM PST 24
Finished Mar 03 02:35:10 PM PST 24
Peak memory 206096 kb
Host smart-2ea233e9-5f71-4373-b28d-12b5cfc67596
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=603313081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.603313081
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.2807232247
Short name T691
Test name
Test status
Simulation time 112061318 ps
CPU time 1.94 seconds
Started Mar 03 02:35:00 PM PST 24
Finished Mar 03 02:35:06 PM PST 24
Peak memory 206188 kb
Host smart-91e16708-831d-41fd-afd7-158ccafb6ebc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2807232247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.2807232247
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.1554663931
Short name T899
Test name
Test status
Simulation time 243775928 ps
CPU time 4.16 seconds
Started Mar 03 02:35:00 PM PST 24
Finished Mar 03 02:35:09 PM PST 24
Peak memory 209076 kb
Host smart-8956096b-ec27-4d12-bede-b37fc7ae149b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554663931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.1554663931
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.3412112540
Short name T74
Test name
Test status
Simulation time 141402693 ps
CPU time 2.29 seconds
Started Mar 03 02:35:11 PM PST 24
Finished Mar 03 02:35:14 PM PST 24
Peak memory 206092 kb
Host smart-5f801ac3-35f7-4018-8e75-00ac803d6d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412112540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.3412112540
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.4105633570
Short name T710
Test name
Test status
Simulation time 104662778 ps
CPU time 2.51 seconds
Started Mar 03 02:35:01 PM PST 24
Finished Mar 03 02:35:07 PM PST 24
Peak memory 209496 kb
Host smart-62cf77a8-27b7-4484-9fb8-5051b37609ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105633570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.4105633570
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.2379018180
Short name T441
Test name
Test status
Simulation time 21242534 ps
CPU time 0.9 seconds
Started Mar 03 02:33:50 PM PST 24
Finished Mar 03 02:33:51 PM PST 24
Peak memory 205600 kb
Host smart-6fdb1ebc-99e2-4008-8230-9fbd09cc523f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379018180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.2379018180
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.2152244244
Short name T404
Test name
Test status
Simulation time 50160421 ps
CPU time 3.87 seconds
Started Mar 03 02:33:37 PM PST 24
Finished Mar 03 02:33:41 PM PST 24
Peak memory 213868 kb
Host smart-a20bf859-246b-488c-9db3-d322115a4de3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2152244244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.2152244244
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.2829623045
Short name T36
Test name
Test status
Simulation time 77072158 ps
CPU time 2.93 seconds
Started Mar 03 02:33:45 PM PST 24
Finished Mar 03 02:33:48 PM PST 24
Peak memory 213740 kb
Host smart-2b1c91ef-0a2e-4f75-8106-f37605657fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829623045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.2829623045
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.1641350502
Short name T427
Test name
Test status
Simulation time 164536611 ps
CPU time 5.09 seconds
Started Mar 03 02:33:39 PM PST 24
Finished Mar 03 02:33:44 PM PST 24
Peak memory 207472 kb
Host smart-34e6cf02-c3ca-4761-9246-eb29e5176f47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641350502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.1641350502
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.4116846856
Short name T588
Test name
Test status
Simulation time 1018864498 ps
CPU time 14.16 seconds
Started Mar 03 02:33:38 PM PST 24
Finished Mar 03 02:33:53 PM PST 24
Peak memory 213820 kb
Host smart-9886e6a6-6d76-4b02-851f-ee11709e7204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116846856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.4116846856
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.1709386295
Short name T836
Test name
Test status
Simulation time 268729597 ps
CPU time 5.63 seconds
Started Mar 03 02:33:41 PM PST 24
Finished Mar 03 02:33:47 PM PST 24
Peak memory 209984 kb
Host smart-cea5a1fa-133f-4532-b7df-e9baf551bae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1709386295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.1709386295
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.3588703312
Short name T220
Test name
Test status
Simulation time 214667508 ps
CPU time 7.77 seconds
Started Mar 03 02:33:42 PM PST 24
Finished Mar 03 02:33:50 PM PST 24
Peak memory 208596 kb
Host smart-473b3443-4405-42c3-80ae-b3d73009600c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588703312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.3588703312
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.4245280742
Short name T310
Test name
Test status
Simulation time 110949832 ps
CPU time 3.64 seconds
Started Mar 03 02:33:40 PM PST 24
Finished Mar 03 02:33:43 PM PST 24
Peak memory 213888 kb
Host smart-80ba7b15-adeb-40c0-a9cb-da9b5591be4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245280742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.4245280742
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.3723326192
Short name T98
Test name
Test status
Simulation time 779866982 ps
CPU time 25.34 seconds
Started Mar 03 02:33:48 PM PST 24
Finished Mar 03 02:34:13 PM PST 24
Peak memory 234948 kb
Host smart-43b1990a-2e59-4044-9b4d-9d629353ba11
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723326192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.3723326192
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.2462028626
Short name T377
Test name
Test status
Simulation time 574636401 ps
CPU time 5.09 seconds
Started Mar 03 02:33:40 PM PST 24
Finished Mar 03 02:33:45 PM PST 24
Peak memory 207868 kb
Host smart-cdac010c-a6bb-43a4-8d76-e5c2290acad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462028626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.2462028626
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.1986060971
Short name T443
Test name
Test status
Simulation time 74167658 ps
CPU time 2.95 seconds
Started Mar 03 02:33:40 PM PST 24
Finished Mar 03 02:33:43 PM PST 24
Peak memory 206220 kb
Host smart-59b2c58c-786d-4078-9e9e-6841b61fe080
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1986060971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.1986060971
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.4227225610
Short name T727
Test name
Test status
Simulation time 880631235 ps
CPU time 7.72 seconds
Started Mar 03 02:33:39 PM PST 24
Finished Mar 03 02:33:47 PM PST 24
Peak memory 207732 kb
Host smart-a6161d92-eda0-4ce6-90ed-8f3d798809b2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4227225610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.4227225610
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.1752274917
Short name T708
Test name
Test status
Simulation time 4915366675 ps
CPU time 45.16 seconds
Started Mar 03 02:33:37 PM PST 24
Finished Mar 03 02:34:24 PM PST 24
Peak memory 207160 kb
Host smart-a38aeab5-eda5-4ea2-be64-7a07b0654ce0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752274917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.1752274917
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.3915003331
Short name T824
Test name
Test status
Simulation time 1166392632 ps
CPU time 34.97 seconds
Started Mar 03 02:33:49 PM PST 24
Finished Mar 03 02:34:24 PM PST 24
Peak memory 213860 kb
Host smart-5cebb8d7-99e5-4409-a899-3418bcc2f6c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3915003331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.3915003331
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.3240077063
Short name T550
Test name
Test status
Simulation time 389128277 ps
CPU time 3.41 seconds
Started Mar 03 02:33:41 PM PST 24
Finished Mar 03 02:33:44 PM PST 24
Peak memory 206240 kb
Host smart-3b206278-a0b1-408d-8dea-f012e1f2a95c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3240077063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.3240077063
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.3716022668
Short name T494
Test name
Test status
Simulation time 1276299755 ps
CPU time 4.28 seconds
Started Mar 03 02:33:43 PM PST 24
Finished Mar 03 02:33:48 PM PST 24
Peak memory 213868 kb
Host smart-cffc4751-b05c-4630-bb2b-3f04861c8f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3716022668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.3716022668
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.2762189707
Short name T33
Test name
Test status
Simulation time 66761516 ps
CPU time 2.38 seconds
Started Mar 03 02:33:50 PM PST 24
Finished Mar 03 02:33:52 PM PST 24
Peak memory 209104 kb
Host smart-b8d963a6-e41f-44a5-85e6-d599ac66f7ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762189707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.2762189707
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.250698795
Short name T660
Test name
Test status
Simulation time 65711238 ps
CPU time 0.73 seconds
Started Mar 03 02:35:09 PM PST 24
Finished Mar 03 02:35:10 PM PST 24
Peak memory 205528 kb
Host smart-5b3ba1a7-0f61-48c3-ae25-016799a33ffe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=250698795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.250698795
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.125158241
Short name T272
Test name
Test status
Simulation time 159625541 ps
CPU time 3.3 seconds
Started Mar 03 02:35:10 PM PST 24
Finished Mar 03 02:35:14 PM PST 24
Peak memory 213744 kb
Host smart-a50c80e6-ec6d-4df1-b01c-5794bda3bb4d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=125158241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.125158241
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.171389016
Short name T830
Test name
Test status
Simulation time 120546301 ps
CPU time 3.65 seconds
Started Mar 03 02:35:09 PM PST 24
Finished Mar 03 02:35:13 PM PST 24
Peak memory 217664 kb
Host smart-2a95d59b-68ff-4791-96e6-5bb047c42b59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=171389016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.171389016
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.1713046245
Short name T82
Test name
Test status
Simulation time 73274785 ps
CPU time 3.6 seconds
Started Mar 03 02:35:13 PM PST 24
Finished Mar 03 02:35:17 PM PST 24
Peak memory 208872 kb
Host smart-4f5c6c51-8db5-4f35-bab9-ef800bfceecf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713046245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.1713046245
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.2318791780
Short name T350
Test name
Test status
Simulation time 89906007 ps
CPU time 4.74 seconds
Started Mar 03 02:35:11 PM PST 24
Finished Mar 03 02:35:17 PM PST 24
Peak memory 216352 kb
Host smart-49e0bae1-a81b-43cc-93ef-02f250823e3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318791780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.2318791780
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.1364227129
Short name T894
Test name
Test status
Simulation time 353576764 ps
CPU time 4.54 seconds
Started Mar 03 02:35:10 PM PST 24
Finished Mar 03 02:35:14 PM PST 24
Peak memory 207740 kb
Host smart-cae658bb-5b8a-4da8-af60-649f17c483b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1364227129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.1364227129
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.620412472
Short name T596
Test name
Test status
Simulation time 623584326 ps
CPU time 5.13 seconds
Started Mar 03 02:35:05 PM PST 24
Finished Mar 03 02:35:11 PM PST 24
Peak memory 206172 kb
Host smart-3ea66c7b-ab8b-4434-b49a-1e04853622c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620412472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.620412472
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.2056024085
Short name T425
Test name
Test status
Simulation time 198550442 ps
CPU time 7.2 seconds
Started Mar 03 02:35:11 PM PST 24
Finished Mar 03 02:35:19 PM PST 24
Peak memory 207132 kb
Host smart-8899937b-9f26-4f12-9f26-ec5dbf84fb9e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2056024085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.2056024085
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.2416272294
Short name T517
Test name
Test status
Simulation time 217067445 ps
CPU time 3.1 seconds
Started Mar 03 02:35:09 PM PST 24
Finished Mar 03 02:35:12 PM PST 24
Peak memory 207976 kb
Host smart-0376d010-b529-4f2c-b889-0e3ccaa11aa4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416272294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.2416272294
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.2794742453
Short name T680
Test name
Test status
Simulation time 891651388 ps
CPU time 6.99 seconds
Started Mar 03 02:35:09 PM PST 24
Finished Mar 03 02:35:16 PM PST 24
Peak memory 207372 kb
Host smart-e083f63a-f648-4501-bead-7d52074931de
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794742453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.2794742453
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.2231715480
Short name T625
Test name
Test status
Simulation time 44645588 ps
CPU time 2.82 seconds
Started Mar 03 02:35:11 PM PST 24
Finished Mar 03 02:35:15 PM PST 24
Peak memory 209184 kb
Host smart-21a04bed-71be-475b-95c3-aac822f79fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231715480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.2231715480
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.754955740
Short name T529
Test name
Test status
Simulation time 9210262901 ps
CPU time 73.33 seconds
Started Mar 03 02:35:09 PM PST 24
Finished Mar 03 02:36:22 PM PST 24
Peak memory 208412 kb
Host smart-8ddd8208-71fa-4152-a22e-5aa9ca615ee2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754955740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.754955740
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.3913944746
Short name T209
Test name
Test status
Simulation time 1838844325 ps
CPU time 42.55 seconds
Started Mar 03 02:35:07 PM PST 24
Finished Mar 03 02:35:49 PM PST 24
Peak memory 215836 kb
Host smart-38983289-340f-4829-a480-20e44ec5c4a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3913944746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.3913944746
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.2514655671
Short name T275
Test name
Test status
Simulation time 264598101 ps
CPU time 9.38 seconds
Started Mar 03 02:35:11 PM PST 24
Finished Mar 03 02:35:21 PM PST 24
Peak memory 213900 kb
Host smart-f6baba8d-076e-45a0-9643-7c3e81c429a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514655671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.2514655671
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.2254663576
Short name T575
Test name
Test status
Simulation time 1047810893 ps
CPU time 10.66 seconds
Started Mar 03 02:35:07 PM PST 24
Finished Mar 03 02:35:18 PM PST 24
Peak memory 210384 kb
Host smart-60f6b5bb-3cad-45d1-91ee-236c0b066057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254663576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.2254663576
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.697381841
Short name T666
Test name
Test status
Simulation time 47185072 ps
CPU time 0.77 seconds
Started Mar 03 02:35:10 PM PST 24
Finished Mar 03 02:35:10 PM PST 24
Peak memory 205536 kb
Host smart-2e1eb26d-6217-4eeb-81ad-307a3382c05e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=697381841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.697381841
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.2039109475
Short name T246
Test name
Test status
Simulation time 375047828 ps
CPU time 4.69 seconds
Started Mar 03 02:35:06 PM PST 24
Finished Mar 03 02:35:11 PM PST 24
Peak memory 209068 kb
Host smart-d2ca08f1-232f-477c-a536-79eec33dc85b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039109475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.2039109475
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.1417430632
Short name T514
Test name
Test status
Simulation time 181855804 ps
CPU time 3.34 seconds
Started Mar 03 02:35:12 PM PST 24
Finished Mar 03 02:35:15 PM PST 24
Peak memory 208328 kb
Host smart-aaf33707-3038-459b-b13e-2ef6a18ff803
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417430632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.1417430632
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.2953243115
Short name T189
Test name
Test status
Simulation time 153090424 ps
CPU time 3.1 seconds
Started Mar 03 02:35:13 PM PST 24
Finished Mar 03 02:35:17 PM PST 24
Peak memory 211016 kb
Host smart-b4dc40bd-76cd-4afc-8170-100ab061ec42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953243115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.2953243115
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.4036429185
Short name T42
Test name
Test status
Simulation time 133127035 ps
CPU time 5.6 seconds
Started Mar 03 02:35:09 PM PST 24
Finished Mar 03 02:35:15 PM PST 24
Peak memory 205732 kb
Host smart-ea56c338-c93f-4673-8c8a-42e903a83a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036429185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.4036429185
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.3308373130
Short name T638
Test name
Test status
Simulation time 887698380 ps
CPU time 7.12 seconds
Started Mar 03 02:35:10 PM PST 24
Finished Mar 03 02:35:17 PM PST 24
Peak memory 213872 kb
Host smart-91866864-ec28-4bb8-81d2-23ea03b34417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3308373130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.3308373130
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.2373177655
Short name T884
Test name
Test status
Simulation time 999673156 ps
CPU time 21.7 seconds
Started Mar 03 02:35:08 PM PST 24
Finished Mar 03 02:35:29 PM PST 24
Peak memory 208000 kb
Host smart-9bd85319-35df-4026-a001-c7900c6e286f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373177655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.2373177655
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.459461425
Short name T13
Test name
Test status
Simulation time 59908672 ps
CPU time 3.34 seconds
Started Mar 03 02:35:10 PM PST 24
Finished Mar 03 02:35:13 PM PST 24
Peak memory 208128 kb
Host smart-92fc85a5-23ff-4485-878b-d18bde1a57dc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=459461425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.459461425
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.868607958
Short name T869
Test name
Test status
Simulation time 988992238 ps
CPU time 5.67 seconds
Started Mar 03 02:35:09 PM PST 24
Finished Mar 03 02:35:14 PM PST 24
Peak memory 207916 kb
Host smart-0f3d4cb2-04b6-4669-8dd8-cb572e51731e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868607958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.868607958
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.3619404363
Short name T672
Test name
Test status
Simulation time 162524077 ps
CPU time 3.62 seconds
Started Mar 03 02:35:08 PM PST 24
Finished Mar 03 02:35:12 PM PST 24
Peak memory 207936 kb
Host smart-792771d5-70b5-48b5-a1fd-674558f9f014
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619404363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.3619404363
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.299617946
Short name T658
Test name
Test status
Simulation time 87029206 ps
CPU time 3.84 seconds
Started Mar 03 02:35:08 PM PST 24
Finished Mar 03 02:35:12 PM PST 24
Peak memory 217864 kb
Host smart-65914d9c-5019-4a03-aafe-1bbe3ed1b73b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299617946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.299617946
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.3494451099
Short name T435
Test name
Test status
Simulation time 97457494 ps
CPU time 2.7 seconds
Started Mar 03 02:35:09 PM PST 24
Finished Mar 03 02:35:11 PM PST 24
Peak memory 205972 kb
Host smart-9a1a1ac9-7c75-4309-9140-f43a5870553f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494451099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.3494451099
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.2064558365
Short name T433
Test name
Test status
Simulation time 23938237 ps
CPU time 0.8 seconds
Started Mar 03 02:35:12 PM PST 24
Finished Mar 03 02:35:13 PM PST 24
Peak memory 205520 kb
Host smart-b5da5560-2f6e-4ee1-963a-e5cb97c2dff0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2064558365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.2064558365
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.4094915437
Short name T631
Test name
Test status
Simulation time 7489657601 ps
CPU time 42.65 seconds
Started Mar 03 02:35:09 PM PST 24
Finished Mar 03 02:35:52 PM PST 24
Peak memory 208760 kb
Host smart-31c41bd9-dff4-462f-97dd-5cd5849bc03d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094915437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.4094915437
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.1356276858
Short name T139
Test name
Test status
Simulation time 984066382 ps
CPU time 3.6 seconds
Started Mar 03 02:35:12 PM PST 24
Finished Mar 03 02:35:16 PM PST 24
Peak memory 209804 kb
Host smart-60986ffb-d946-4a26-8afa-3b11708c56d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356276858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.1356276858
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.2973311320
Short name T519
Test name
Test status
Simulation time 47708897 ps
CPU time 0.98 seconds
Started Mar 03 02:35:21 PM PST 24
Finished Mar 03 02:35:22 PM PST 24
Peak memory 205680 kb
Host smart-e032d406-fd65-4a68-9ac9-759527dfce92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973311320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.2973311320
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.562684578
Short name T728
Test name
Test status
Simulation time 517634362 ps
CPU time 4.12 seconds
Started Mar 03 02:35:12 PM PST 24
Finished Mar 03 02:35:16 PM PST 24
Peak memory 208448 kb
Host smart-eb6bb27b-5b3e-48f3-980f-a29b4e018bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=562684578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.562684578
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.74314463
Short name T281
Test name
Test status
Simulation time 905497078 ps
CPU time 10.59 seconds
Started Mar 03 02:35:15 PM PST 24
Finished Mar 03 02:35:26 PM PST 24
Peak memory 222024 kb
Host smart-9b40a6fa-9817-423e-96dc-99c0997de1da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74314463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.74314463
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.888995349
Short name T531
Test name
Test status
Simulation time 193463790 ps
CPU time 2.88 seconds
Started Mar 03 02:35:14 PM PST 24
Finished Mar 03 02:35:17 PM PST 24
Peak memory 213880 kb
Host smart-7822be34-0bda-4fc7-913c-c12ba07476d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888995349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.888995349
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.4050445460
Short name T448
Test name
Test status
Simulation time 328851617 ps
CPU time 9.27 seconds
Started Mar 03 02:35:14 PM PST 24
Finished Mar 03 02:35:23 PM PST 24
Peak memory 213800 kb
Host smart-0bb9fc8d-cde6-4029-be8c-52fdbddfeb33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050445460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.4050445460
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.3900330007
Short name T696
Test name
Test status
Simulation time 389902541 ps
CPU time 5.89 seconds
Started Mar 03 02:35:07 PM PST 24
Finished Mar 03 02:35:13 PM PST 24
Peak memory 207788 kb
Host smart-8a228264-f265-4853-aa78-b3817e8537da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900330007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.3900330007
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.2791753282
Short name T687
Test name
Test status
Simulation time 33822377 ps
CPU time 2.52 seconds
Started Mar 03 02:35:12 PM PST 24
Finished Mar 03 02:35:14 PM PST 24
Peak memory 206072 kb
Host smart-d4a32876-4c38-4d52-af3e-af752b3b0e3b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791753282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.2791753282
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.3999126840
Short name T898
Test name
Test status
Simulation time 4193774858 ps
CPU time 13.22 seconds
Started Mar 03 02:35:12 PM PST 24
Finished Mar 03 02:35:25 PM PST 24
Peak memory 208176 kb
Host smart-8f64daa2-8876-4e35-b0b6-eb7641dc5e18
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999126840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.3999126840
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.12023275
Short name T693
Test name
Test status
Simulation time 50643382 ps
CPU time 2.76 seconds
Started Mar 03 02:35:13 PM PST 24
Finished Mar 03 02:35:17 PM PST 24
Peak memory 206224 kb
Host smart-5fc51ab7-ba59-46db-8890-2c4d418bf22e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12023275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.12023275
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.3675293809
Short name T778
Test name
Test status
Simulation time 4840461868 ps
CPU time 30.16 seconds
Started Mar 03 02:35:14 PM PST 24
Finished Mar 03 02:35:44 PM PST 24
Peak memory 208460 kb
Host smart-dd331d57-57ee-444a-8b26-cd4436e4e633
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675293809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.3675293809
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.1871478643
Short name T512
Test name
Test status
Simulation time 252673863 ps
CPU time 5.91 seconds
Started Mar 03 02:35:10 PM PST 24
Finished Mar 03 02:35:16 PM PST 24
Peak memory 207532 kb
Host smart-0ea92726-81e4-49fe-9523-1344145312ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871478643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.1871478643
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.391759089
Short name T578
Test name
Test status
Simulation time 362199242 ps
CPU time 5.31 seconds
Started Mar 03 02:35:11 PM PST 24
Finished Mar 03 02:35:17 PM PST 24
Peak memory 213928 kb
Host smart-d28f521d-30d4-4d2f-8153-7e66ecd034ed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391759089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.391759089
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_stress_all_with_rand_reset.2394592655
Short name T767
Test name
Test status
Simulation time 368594745 ps
CPU time 11.87 seconds
Started Mar 03 02:35:11 PM PST 24
Finished Mar 03 02:35:24 PM PST 24
Peak memory 222200 kb
Host smart-63357e00-8969-4feb-8304-0d0225064281
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2394592655 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all_with_rand_reset.2394592655
Directory /workspace/22.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.4126902880
Short name T266
Test name
Test status
Simulation time 59447544 ps
CPU time 3.65 seconds
Started Mar 03 02:35:15 PM PST 24
Finished Mar 03 02:35:18 PM PST 24
Peak memory 206660 kb
Host smart-a1923322-43e2-453d-b4cf-83c63691dd1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4126902880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.4126902880
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.3452926365
Short name T794
Test name
Test status
Simulation time 309739969 ps
CPU time 4.2 seconds
Started Mar 03 02:35:15 PM PST 24
Finished Mar 03 02:35:20 PM PST 24
Peak memory 209416 kb
Host smart-996ae757-7c4c-42ed-8cf2-a5143e9b134e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452926365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.3452926365
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.3473803979
Short name T423
Test name
Test status
Simulation time 12522863 ps
CPU time 0.88 seconds
Started Mar 03 02:35:22 PM PST 24
Finished Mar 03 02:35:23 PM PST 24
Peak memory 205616 kb
Host smart-5a3c3e3c-c7cc-4671-ab3c-0b66375887aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3473803979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.3473803979
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.3245313552
Short name T292
Test name
Test status
Simulation time 164095172 ps
CPU time 4.93 seconds
Started Mar 03 02:35:23 PM PST 24
Finished Mar 03 02:35:28 PM PST 24
Peak memory 214580 kb
Host smart-6d7a97ff-14c2-497f-8c78-4363cb9cac71
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3245313552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.3245313552
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.1703946243
Short name T63
Test name
Test status
Simulation time 234923772 ps
CPU time 2.4 seconds
Started Mar 03 02:35:21 PM PST 24
Finished Mar 03 02:35:24 PM PST 24
Peak memory 221796 kb
Host smart-d4e52f8e-d3b1-47c3-b456-a421f98712f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1703946243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.1703946243
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.2385012892
Short name T684
Test name
Test status
Simulation time 29410045 ps
CPU time 2.44 seconds
Started Mar 03 02:35:19 PM PST 24
Finished Mar 03 02:35:21 PM PST 24
Peak memory 222028 kb
Host smart-5fd43333-8f36-4623-8487-976a115c2bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385012892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.2385012892
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.3389042418
Short name T704
Test name
Test status
Simulation time 489038902 ps
CPU time 6.29 seconds
Started Mar 03 02:35:22 PM PST 24
Finished Mar 03 02:35:28 PM PST 24
Peak memory 213008 kb
Host smart-bc9f258f-c909-4e77-b5e3-971fa4e72e0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3389042418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.3389042418
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.2286221534
Short name T857
Test name
Test status
Simulation time 880851561 ps
CPU time 4.2 seconds
Started Mar 03 02:35:19 PM PST 24
Finished Mar 03 02:35:24 PM PST 24
Peak memory 210908 kb
Host smart-99c66a4c-1745-4342-afd5-6e4d4f0d9a18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286221534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.2286221534
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.231489672
Short name T206
Test name
Test status
Simulation time 74338200 ps
CPU time 2.56 seconds
Started Mar 03 02:35:22 PM PST 24
Finished Mar 03 02:35:24 PM PST 24
Peak memory 219968 kb
Host smart-be23999a-e84b-40d8-9419-8f755c639fd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231489672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.231489672
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.1047321271
Short name T765
Test name
Test status
Simulation time 340205154 ps
CPU time 7.98 seconds
Started Mar 03 02:35:20 PM PST 24
Finished Mar 03 02:35:28 PM PST 24
Peak memory 209552 kb
Host smart-98d14c81-c477-4949-8790-1ab742c01ef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1047321271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.1047321271
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.1790480735
Short name T837
Test name
Test status
Simulation time 98720056 ps
CPU time 2.16 seconds
Started Mar 03 02:35:20 PM PST 24
Finished Mar 03 02:35:22 PM PST 24
Peak memory 207820 kb
Host smart-e27c1cde-21e3-46e7-bef6-71253b0a7be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790480735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.1790480735
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.4001392257
Short name T483
Test name
Test status
Simulation time 125056897 ps
CPU time 2.38 seconds
Started Mar 03 02:35:20 PM PST 24
Finished Mar 03 02:35:23 PM PST 24
Peak memory 208488 kb
Host smart-bd469811-dfc4-4d96-ac34-df1d8f3d2664
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001392257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.4001392257
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.1204212992
Short name T874
Test name
Test status
Simulation time 487301389 ps
CPU time 4.58 seconds
Started Mar 03 02:35:22 PM PST 24
Finished Mar 03 02:35:27 PM PST 24
Peak memory 207472 kb
Host smart-583ee039-524c-450d-8b4a-e7712daa98e8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204212992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.1204212992
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.1289641450
Short name T788
Test name
Test status
Simulation time 115463809 ps
CPU time 2.34 seconds
Started Mar 03 02:35:22 PM PST 24
Finished Mar 03 02:35:25 PM PST 24
Peak memory 206052 kb
Host smart-d6184659-75fb-4000-90ac-1e9bf516145f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1289641450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.1289641450
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.712221253
Short name T405
Test name
Test status
Simulation time 444556235 ps
CPU time 3.59 seconds
Started Mar 03 02:35:21 PM PST 24
Finished Mar 03 02:35:25 PM PST 24
Peak memory 206732 kb
Host smart-dd369600-a2b6-4143-845f-279fbbea17fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712221253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.712221253
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.1912798488
Short name T491
Test name
Test status
Simulation time 155425149 ps
CPU time 4.8 seconds
Started Mar 03 02:35:22 PM PST 24
Finished Mar 03 02:35:27 PM PST 24
Peak memory 206116 kb
Host smart-21c366b3-edf7-4376-9ca5-7fb7cc365c78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912798488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.1912798488
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.480350787
Short name T185
Test name
Test status
Simulation time 2213325651 ps
CPU time 43.42 seconds
Started Mar 03 02:35:22 PM PST 24
Finished Mar 03 02:36:05 PM PST 24
Peak memory 220148 kb
Host smart-d96ed36e-ce8d-4cf3-9e37-add5c22fa540
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480350787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.480350787
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.127173361
Short name T562
Test name
Test status
Simulation time 44162878 ps
CPU time 3.21 seconds
Started Mar 03 02:35:21 PM PST 24
Finished Mar 03 02:35:25 PM PST 24
Peak memory 208748 kb
Host smart-3703b8bb-36f8-4fb6-8ec9-3b36b51dbd10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127173361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.127173361
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.727460718
Short name T712
Test name
Test status
Simulation time 330787478 ps
CPU time 3.65 seconds
Started Mar 03 02:35:19 PM PST 24
Finished Mar 03 02:35:23 PM PST 24
Peak memory 209500 kb
Host smart-a94e56e9-c390-45a9-9bbb-7e92e7395b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=727460718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.727460718
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.3144098513
Short name T592
Test name
Test status
Simulation time 14436961 ps
CPU time 0.75 seconds
Started Mar 03 02:35:29 PM PST 24
Finished Mar 03 02:35:30 PM PST 24
Peak memory 205608 kb
Host smart-f283d60f-1c69-4f5d-b734-5c67b03c7258
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144098513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.3144098513
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.4150922656
Short name T867
Test name
Test status
Simulation time 115460051 ps
CPU time 5.27 seconds
Started Mar 03 02:35:26 PM PST 24
Finished Mar 03 02:35:31 PM PST 24
Peak memory 209556 kb
Host smart-d9a4872f-8c7c-4b79-a540-60602c6904f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150922656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.4150922656
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.595703826
Short name T338
Test name
Test status
Simulation time 17180890 ps
CPU time 1.4 seconds
Started Mar 03 02:35:24 PM PST 24
Finished Mar 03 02:35:26 PM PST 24
Peak memory 206892 kb
Host smart-c35a18ce-88aa-44d0-948a-ff08ffdbb952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595703826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.595703826
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.2823539203
Short name T846
Test name
Test status
Simulation time 2887904749 ps
CPU time 11.35 seconds
Started Mar 03 02:35:22 PM PST 24
Finished Mar 03 02:35:33 PM PST 24
Peak memory 214076 kb
Host smart-297176e2-f673-4778-ae03-fbcbfbb7e4f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823539203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.2823539203
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.983406688
Short name T282
Test name
Test status
Simulation time 224233381 ps
CPU time 7.57 seconds
Started Mar 03 02:35:23 PM PST 24
Finished Mar 03 02:35:31 PM PST 24
Peak memory 213796 kb
Host smart-499c6188-1c82-4d5d-8b2c-86dd26315b40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983406688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.983406688
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.2363564480
Short name T758
Test name
Test status
Simulation time 82706506 ps
CPU time 1.48 seconds
Started Mar 03 02:35:21 PM PST 24
Finished Mar 03 02:35:23 PM PST 24
Peak memory 205664 kb
Host smart-436d774b-5d91-456c-9146-49783d9f725e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363564480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.2363564480
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.4281727025
Short name T382
Test name
Test status
Simulation time 1403292797 ps
CPU time 9.4 seconds
Started Mar 03 02:35:22 PM PST 24
Finished Mar 03 02:35:31 PM PST 24
Peak memory 208716 kb
Host smart-7450d103-210b-4ec6-be0a-007e09600d48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281727025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.4281727025
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.85736255
Short name T854
Test name
Test status
Simulation time 1435691571 ps
CPU time 6.43 seconds
Started Mar 03 02:35:20 PM PST 24
Finished Mar 03 02:35:27 PM PST 24
Peak memory 207964 kb
Host smart-d09d1458-3822-4352-a466-8bf10208fc35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85736255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.85736255
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.3336312973
Short name T642
Test name
Test status
Simulation time 1166101085 ps
CPU time 28.03 seconds
Started Mar 03 02:35:19 PM PST 24
Finished Mar 03 02:35:47 PM PST 24
Peak memory 207260 kb
Host smart-52e42477-6fbb-4f29-b8df-65c466d70629
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336312973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.3336312973
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.2121790960
Short name T611
Test name
Test status
Simulation time 104523666 ps
CPU time 3.05 seconds
Started Mar 03 02:35:21 PM PST 24
Finished Mar 03 02:35:24 PM PST 24
Peak memory 206244 kb
Host smart-7f426904-9082-4e68-af37-41056bfee114
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121790960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.2121790960
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.4241119056
Short name T563
Test name
Test status
Simulation time 1445725681 ps
CPU time 9.63 seconds
Started Mar 03 02:35:21 PM PST 24
Finished Mar 03 02:35:31 PM PST 24
Peak memory 208320 kb
Host smart-d6b8924a-42b4-48e6-a929-64aa39586b5c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4241119056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.4241119056
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.3860383584
Short name T434
Test name
Test status
Simulation time 340241753 ps
CPU time 6.78 seconds
Started Mar 03 02:35:21 PM PST 24
Finished Mar 03 02:35:28 PM PST 24
Peak memory 208252 kb
Host smart-4321f74d-c40b-45cc-a59e-306602877068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860383584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.3860383584
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.3662099578
Short name T567
Test name
Test status
Simulation time 248283534 ps
CPU time 3.18 seconds
Started Mar 03 02:35:23 PM PST 24
Finished Mar 03 02:35:27 PM PST 24
Peak memory 206120 kb
Host smart-e5877b58-8995-4864-bb35-8da990acc5be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662099578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.3662099578
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.3100365296
Short name T385
Test name
Test status
Simulation time 873209624 ps
CPU time 12.12 seconds
Started Mar 03 02:35:24 PM PST 24
Finished Mar 03 02:35:36 PM PST 24
Peak memory 215208 kb
Host smart-9d92b658-5d40-48aa-8cb4-2054cb7e75c6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100365296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.3100365296
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.1358012299
Short name T689
Test name
Test status
Simulation time 87734680 ps
CPU time 4.7 seconds
Started Mar 03 02:35:22 PM PST 24
Finished Mar 03 02:35:27 PM PST 24
Peak memory 213816 kb
Host smart-8afa719d-fc78-40ea-84da-9bd2cc416c66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358012299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.1358012299
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.3310776326
Short name T463
Test name
Test status
Simulation time 15034096071 ps
CPU time 32.62 seconds
Started Mar 03 02:35:23 PM PST 24
Finished Mar 03 02:35:56 PM PST 24
Peak memory 222052 kb
Host smart-6e388cb7-9ff5-4d60-a4e0-e17e3f28adfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310776326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.3310776326
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.3463260281
Short name T94
Test name
Test status
Simulation time 10880145 ps
CPU time 0.83 seconds
Started Mar 03 02:35:24 PM PST 24
Finished Mar 03 02:35:25 PM PST 24
Peak memory 205608 kb
Host smart-c540d1d3-cf25-40a9-b8cd-e5d252d45d1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463260281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.3463260281
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.1608726678
Short name T408
Test name
Test status
Simulation time 136974109 ps
CPU time 2.71 seconds
Started Mar 03 02:35:23 PM PST 24
Finished Mar 03 02:35:26 PM PST 24
Peak memory 213884 kb
Host smart-279b1b09-aedf-42ac-a552-3a0d5f6bc06e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1608726678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.1608726678
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.249682232
Short name T263
Test name
Test status
Simulation time 1297113200 ps
CPU time 3.58 seconds
Started Mar 03 02:35:26 PM PST 24
Finished Mar 03 02:35:29 PM PST 24
Peak memory 213840 kb
Host smart-857e8791-84f3-46e7-b510-2aff6b1396f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249682232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.249682232
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.1475532552
Short name T300
Test name
Test status
Simulation time 104141228 ps
CPU time 3.52 seconds
Started Mar 03 02:35:23 PM PST 24
Finished Mar 03 02:35:27 PM PST 24
Peak memory 208712 kb
Host smart-feb37225-6dd7-43cb-b451-23cb5b4d8293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475532552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.1475532552
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.3821947364
Short name T259
Test name
Test status
Simulation time 126648266 ps
CPU time 2.8 seconds
Started Mar 03 02:35:23 PM PST 24
Finished Mar 03 02:35:26 PM PST 24
Peak memory 210848 kb
Host smart-b0de7302-7922-4084-a510-52037a61f927
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821947364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.3821947364
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.2951790280
Short name T208
Test name
Test status
Simulation time 107290847 ps
CPU time 2.76 seconds
Started Mar 03 02:35:24 PM PST 24
Finished Mar 03 02:35:26 PM PST 24
Peak memory 208844 kb
Host smart-72384ca7-8b40-404a-a8c7-598288b5e962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951790280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.2951790280
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.4185861154
Short name T502
Test name
Test status
Simulation time 454973293 ps
CPU time 5.2 seconds
Started Mar 03 02:35:28 PM PST 24
Finished Mar 03 02:35:33 PM PST 24
Peak memory 207276 kb
Host smart-d0cf3b95-9045-40d9-bd0b-c00258a187b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185861154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.4185861154
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.638913715
Short name T340
Test name
Test status
Simulation time 1371569303 ps
CPU time 25.94 seconds
Started Mar 03 02:35:23 PM PST 24
Finished Mar 03 02:35:49 PM PST 24
Peak memory 208084 kb
Host smart-f10f141a-e488-4864-aa45-707dbd426c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638913715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.638913715
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.2812039456
Short name T479
Test name
Test status
Simulation time 80843668 ps
CPU time 4.28 seconds
Started Mar 03 02:35:22 PM PST 24
Finished Mar 03 02:35:27 PM PST 24
Peak memory 208152 kb
Host smart-60385a6b-c022-461b-98e1-74cdb2ea6e81
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2812039456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.2812039456
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.4234454521
Short name T277
Test name
Test status
Simulation time 122095977 ps
CPU time 2.35 seconds
Started Mar 03 02:35:24 PM PST 24
Finished Mar 03 02:35:27 PM PST 24
Peak memory 206168 kb
Host smart-148b6948-24cc-4c85-8c9d-27a0b355d915
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4234454521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.4234454521
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.1396140569
Short name T516
Test name
Test status
Simulation time 259245621 ps
CPU time 7.58 seconds
Started Mar 03 02:35:26 PM PST 24
Finished Mar 03 02:35:33 PM PST 24
Peak memory 208016 kb
Host smart-12102083-1a54-48c8-8fa9-638c9e0a696c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396140569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.1396140569
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.2671571727
Short name T492
Test name
Test status
Simulation time 250978185 ps
CPU time 3.17 seconds
Started Mar 03 02:35:24 PM PST 24
Finished Mar 03 02:35:28 PM PST 24
Peak memory 214380 kb
Host smart-b8e95545-85d6-4c2d-9d55-0fa759168f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671571727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.2671571727
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.654982019
Short name T487
Test name
Test status
Simulation time 759322272 ps
CPU time 7.79 seconds
Started Mar 03 02:35:26 PM PST 24
Finished Mar 03 02:35:34 PM PST 24
Peak memory 206248 kb
Host smart-27cbb185-5730-4055-b88c-d0ded80fe0c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654982019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.654982019
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.3113382299
Short name T840
Test name
Test status
Simulation time 570766031 ps
CPU time 14.9 seconds
Started Mar 03 02:35:24 PM PST 24
Finished Mar 03 02:35:39 PM PST 24
Peak memory 208552 kb
Host smart-710db71d-c720-4bd2-b7e2-e11ea7d9b1e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113382299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.3113382299
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.1810875822
Short name T475
Test name
Test status
Simulation time 680556497 ps
CPU time 6.35 seconds
Started Mar 03 02:35:26 PM PST 24
Finished Mar 03 02:35:33 PM PST 24
Peak memory 209704 kb
Host smart-fa7a5923-c2cc-4577-895c-ccdf2f0782aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810875822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.1810875822
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.831844002
Short name T600
Test name
Test status
Simulation time 46024372 ps
CPU time 0.76 seconds
Started Mar 03 02:35:31 PM PST 24
Finished Mar 03 02:35:32 PM PST 24
Peak memory 205612 kb
Host smart-1b667c3b-c7ce-4c5f-a00f-830c8f51453c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=831844002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.831844002
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.3494375318
Short name T359
Test name
Test status
Simulation time 140143859 ps
CPU time 3.21 seconds
Started Mar 03 02:35:29 PM PST 24
Finished Mar 03 02:35:32 PM PST 24
Peak memory 214576 kb
Host smart-83447a98-391e-4286-af1b-f4556ba11996
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3494375318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.3494375318
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.3805532434
Short name T645
Test name
Test status
Simulation time 75906585 ps
CPU time 3.72 seconds
Started Mar 03 02:35:31 PM PST 24
Finished Mar 03 02:35:35 PM PST 24
Peak memory 208976 kb
Host smart-41929294-7260-4bfc-af18-8fc4e89d9ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3805532434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.3805532434
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.775499941
Short name T466
Test name
Test status
Simulation time 185073422 ps
CPU time 3.18 seconds
Started Mar 03 02:35:29 PM PST 24
Finished Mar 03 02:35:32 PM PST 24
Peak memory 217772 kb
Host smart-e3696e57-5eda-4908-98f3-8617c02106a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775499941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.775499941
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.3506024247
Short name T833
Test name
Test status
Simulation time 316799054 ps
CPU time 3.38 seconds
Started Mar 03 02:35:23 PM PST 24
Finished Mar 03 02:35:26 PM PST 24
Peak memory 208556 kb
Host smart-8c04fe56-68ee-4a8b-b8c3-1b9916db1ea9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506024247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.3506024247
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.2898066717
Short name T296
Test name
Test status
Simulation time 4362096270 ps
CPU time 31.58 seconds
Started Mar 03 02:35:24 PM PST 24
Finished Mar 03 02:35:56 PM PST 24
Peak memory 210732 kb
Host smart-85e725b9-c56e-4ec1-abc4-fe01c4965b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2898066717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.2898066717
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.2662017350
Short name T210
Test name
Test status
Simulation time 40298417 ps
CPU time 3.4 seconds
Started Mar 03 02:35:25 PM PST 24
Finished Mar 03 02:35:28 PM PST 24
Peak memory 219636 kb
Host smart-a932a38a-8408-4f55-b4fd-e48e004940d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662017350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.2662017350
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.3345594869
Short name T752
Test name
Test status
Simulation time 499721915 ps
CPU time 12.68 seconds
Started Mar 03 02:35:26 PM PST 24
Finished Mar 03 02:35:39 PM PST 24
Peak memory 208700 kb
Host smart-dcd8130d-189d-4a06-8932-328bbe418287
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3345594869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.3345594869
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.3374915031
Short name T305
Test name
Test status
Simulation time 90280753 ps
CPU time 2.57 seconds
Started Mar 03 02:35:27 PM PST 24
Finished Mar 03 02:35:30 PM PST 24
Peak memory 206144 kb
Host smart-ea6b037d-b767-4ff5-a7e0-7b89e6608df0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3374915031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.3374915031
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.1472463526
Short name T637
Test name
Test status
Simulation time 23155819 ps
CPU time 1.83 seconds
Started Mar 03 02:35:22 PM PST 24
Finished Mar 03 02:35:24 PM PST 24
Peak memory 206060 kb
Host smart-96b4586f-a5f3-44a7-a088-02fc7aaf2d0a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1472463526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.1472463526
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.563587545
Short name T714
Test name
Test status
Simulation time 136571136 ps
CPU time 4.87 seconds
Started Mar 03 02:35:26 PM PST 24
Finished Mar 03 02:35:31 PM PST 24
Peak memory 207572 kb
Host smart-90db3d82-ee9b-4054-acc0-ff41662fd87d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=563587545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.563587545
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.1335163967
Short name T581
Test name
Test status
Simulation time 310238053 ps
CPU time 3.82 seconds
Started Mar 03 02:35:25 PM PST 24
Finished Mar 03 02:35:29 PM PST 24
Peak memory 208284 kb
Host smart-97a4a245-7570-4b84-ad22-042618417b58
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335163967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.1335163967
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.3747517740
Short name T453
Test name
Test status
Simulation time 109421743 ps
CPU time 3.12 seconds
Started Mar 03 02:35:34 PM PST 24
Finished Mar 03 02:35:37 PM PST 24
Peak memory 207972 kb
Host smart-283419ab-e3cb-4b4d-acf4-9d254a0efb90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747517740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.3747517740
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.2824618720
Short name T734
Test name
Test status
Simulation time 42162286 ps
CPU time 1.81 seconds
Started Mar 03 02:35:24 PM PST 24
Finished Mar 03 02:35:26 PM PST 24
Peak memory 205944 kb
Host smart-0bb9ba19-71d7-4a07-b243-80715d4c9c23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824618720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.2824618720
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.1207073764
Short name T291
Test name
Test status
Simulation time 1023283231 ps
CPU time 11.59 seconds
Started Mar 03 02:35:26 PM PST 24
Finished Mar 03 02:35:38 PM PST 24
Peak memory 208948 kb
Host smart-267afd83-0bbe-4cb5-858b-74550c5da0f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207073764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.1207073764
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.2029213839
Short name T369
Test name
Test status
Simulation time 65286808 ps
CPU time 2.27 seconds
Started Mar 03 02:35:32 PM PST 24
Finished Mar 03 02:35:34 PM PST 24
Peak memory 209760 kb
Host smart-bea122fb-ff49-4eba-a09e-46afce401246
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029213839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.2029213839
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.403474247
Short name T634
Test name
Test status
Simulation time 51941298 ps
CPU time 0.77 seconds
Started Mar 03 02:35:38 PM PST 24
Finished Mar 03 02:35:39 PM PST 24
Peak memory 205468 kb
Host smart-b0ed6dc0-fe04-4da4-ad1b-6b3538a991e1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=403474247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.403474247
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.4219994404
Short name T329
Test name
Test status
Simulation time 263672416 ps
CPU time 4.71 seconds
Started Mar 03 02:35:32 PM PST 24
Finished Mar 03 02:35:36 PM PST 24
Peak memory 215116 kb
Host smart-222d55a3-03fc-4dfa-8a34-c8879d2d84c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4219994404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.4219994404
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.2390040843
Short name T38
Test name
Test status
Simulation time 495854372 ps
CPU time 3.3 seconds
Started Mar 03 02:35:37 PM PST 24
Finished Mar 03 02:35:41 PM PST 24
Peak memory 209208 kb
Host smart-51793a14-8494-495e-8fa9-54fcac699f99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390040843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.2390040843
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.3696239888
Short name T635
Test name
Test status
Simulation time 165358632 ps
CPU time 2.64 seconds
Started Mar 03 02:35:31 PM PST 24
Finished Mar 03 02:35:33 PM PST 24
Peak memory 213864 kb
Host smart-6bc4f4dd-8ab8-4b8d-a050-88b5d2824df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3696239888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.3696239888
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.3406195691
Short name T643
Test name
Test status
Simulation time 1042366537 ps
CPU time 36.1 seconds
Started Mar 03 02:35:36 PM PST 24
Finished Mar 03 02:36:12 PM PST 24
Peak memory 219676 kb
Host smart-3b4c0f2f-7ba4-4c0e-b8f9-a757eb38f94d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3406195691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.3406195691
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.382560120
Short name T295
Test name
Test status
Simulation time 11327727942 ps
CPU time 49.19 seconds
Started Mar 03 02:35:39 PM PST 24
Finished Mar 03 02:36:28 PM PST 24
Peak memory 221888 kb
Host smart-32eb679b-9f16-478e-b8e9-639086b55d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382560120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.382560120
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.2136873026
Short name T41
Test name
Test status
Simulation time 850747984 ps
CPU time 3.43 seconds
Started Mar 03 02:35:36 PM PST 24
Finished Mar 03 02:35:40 PM PST 24
Peak memory 208532 kb
Host smart-2fa2a01c-cb92-44fd-aa7b-829ec79f5d69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136873026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.2136873026
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.2406935283
Short name T835
Test name
Test status
Simulation time 209309099 ps
CPU time 3.74 seconds
Started Mar 03 02:35:31 PM PST 24
Finished Mar 03 02:35:35 PM PST 24
Peak memory 208484 kb
Host smart-cb3fcf1f-2389-46a2-90c1-d7a4c5dcc2dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406935283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.2406935283
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.2923132026
Short name T521
Test name
Test status
Simulation time 286572006 ps
CPU time 8.36 seconds
Started Mar 03 02:35:30 PM PST 24
Finished Mar 03 02:35:38 PM PST 24
Peak memory 207904 kb
Host smart-3acfc62f-78d9-4f15-8f61-11e7dcc9544f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923132026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.2923132026
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.3922411207
Short name T73
Test name
Test status
Simulation time 2692653060 ps
CPU time 27.64 seconds
Started Mar 03 02:35:32 PM PST 24
Finished Mar 03 02:36:00 PM PST 24
Peak memory 207968 kb
Host smart-2bce2292-b243-4b33-92b4-41a794fad2c4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3922411207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.3922411207
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.754915484
Short name T446
Test name
Test status
Simulation time 44524322 ps
CPU time 2.31 seconds
Started Mar 03 02:35:30 PM PST 24
Finished Mar 03 02:35:33 PM PST 24
Peak memory 206132 kb
Host smart-35ba5c61-cb64-4acd-9d69-cc79cf03cb50
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754915484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.754915484
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.926202832
Short name T615
Test name
Test status
Simulation time 40819600 ps
CPU time 1.8 seconds
Started Mar 03 02:35:31 PM PST 24
Finished Mar 03 02:35:33 PM PST 24
Peak memory 206192 kb
Host smart-4b570a48-2eb7-438b-979c-b8db8f6c7b06
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926202832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.926202832
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.1584919491
Short name T690
Test name
Test status
Simulation time 124996947 ps
CPU time 3.73 seconds
Started Mar 03 02:35:35 PM PST 24
Finished Mar 03 02:35:39 PM PST 24
Peak memory 208128 kb
Host smart-aeeee81d-f612-4e55-bda3-82e074319d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584919491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.1584919491
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.3282887848
Short name T703
Test name
Test status
Simulation time 500192743 ps
CPU time 3.66 seconds
Started Mar 03 02:35:30 PM PST 24
Finished Mar 03 02:35:33 PM PST 24
Peak memory 206060 kb
Host smart-578ec673-1bd3-41fc-b145-0af8ec34af9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282887848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.3282887848
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.1670553327
Short name T715
Test name
Test status
Simulation time 53549989 ps
CPU time 3.33 seconds
Started Mar 03 02:35:34 PM PST 24
Finished Mar 03 02:35:38 PM PST 24
Peak memory 206712 kb
Host smart-016d9f9d-2807-4c26-b7ca-685bbfdf0977
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1670553327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.1670553327
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.898532669
Short name T893
Test name
Test status
Simulation time 2272815966 ps
CPU time 56.51 seconds
Started Mar 03 02:35:38 PM PST 24
Finished Mar 03 02:36:34 PM PST 24
Peak memory 209624 kb
Host smart-f4f2b94a-f3d9-4c09-a7a2-e3aaa5a012b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898532669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.898532669
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.1257088827
Short name T731
Test name
Test status
Simulation time 60454811 ps
CPU time 2.12 seconds
Started Mar 03 02:35:36 PM PST 24
Finished Mar 03 02:35:38 PM PST 24
Peak memory 209484 kb
Host smart-3c3c8f6d-3b7b-49cd-b0f1-a1c5a0ee6285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257088827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.1257088827
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.2461762004
Short name T431
Test name
Test status
Simulation time 9809865 ps
CPU time 0.8 seconds
Started Mar 03 02:35:34 PM PST 24
Finished Mar 03 02:35:35 PM PST 24
Peak memory 205528 kb
Host smart-d80e01e3-adc6-4d4c-8847-dc4767b469fd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461762004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.2461762004
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.1477789856
Short name T30
Test name
Test status
Simulation time 901867313 ps
CPU time 2.97 seconds
Started Mar 03 02:35:39 PM PST 24
Finished Mar 03 02:35:42 PM PST 24
Peak memory 217624 kb
Host smart-88b114d0-1f09-495e-8713-6d76c972119f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477789856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.1477789856
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.1782917910
Short name T46
Test name
Test status
Simulation time 143491626 ps
CPU time 3.12 seconds
Started Mar 03 02:35:37 PM PST 24
Finished Mar 03 02:35:40 PM PST 24
Peak memory 206984 kb
Host smart-a879bc19-f5d6-4370-b131-60c9ffb5cf87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782917910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.1782917910
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.433038212
Short name T81
Test name
Test status
Simulation time 3970213583 ps
CPU time 34.11 seconds
Started Mar 03 02:35:36 PM PST 24
Finished Mar 03 02:36:10 PM PST 24
Peak memory 222140 kb
Host smart-148238a9-d778-4b71-860b-65942c77588e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433038212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.433038212
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.1644021647
Short name T465
Test name
Test status
Simulation time 32959130 ps
CPU time 1.49 seconds
Started Mar 03 02:35:38 PM PST 24
Finished Mar 03 02:35:39 PM PST 24
Peak memory 205484 kb
Host smart-595f8ba2-fd0b-45a7-9b12-e464f0b1e22b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644021647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.1644021647
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.4143310913
Short name T228
Test name
Test status
Simulation time 207687877 ps
CPU time 2.53 seconds
Started Mar 03 02:35:37 PM PST 24
Finished Mar 03 02:35:40 PM PST 24
Peak memory 207532 kb
Host smart-b8e59975-448c-47bc-81e1-bc461532ac07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143310913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.4143310913
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.519970282
Short name T306
Test name
Test status
Simulation time 1215351746 ps
CPU time 4.52 seconds
Started Mar 03 02:35:37 PM PST 24
Finished Mar 03 02:35:42 PM PST 24
Peak memory 207548 kb
Host smart-06824449-a7c7-48c9-9d17-35dc7f647d6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=519970282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.519970282
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.3435368558
Short name T471
Test name
Test status
Simulation time 654907865 ps
CPU time 4.09 seconds
Started Mar 03 02:35:39 PM PST 24
Finished Mar 03 02:35:43 PM PST 24
Peak memory 207936 kb
Host smart-55aea624-3f34-477a-9157-d8a6553f8c3e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435368558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.3435368558
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.735424121
Short name T415
Test name
Test status
Simulation time 1876167237 ps
CPU time 59.87 seconds
Started Mar 03 02:35:40 PM PST 24
Finished Mar 03 02:36:40 PM PST 24
Peak memory 207704 kb
Host smart-d9097582-8d8b-4e87-a10e-091f813e12e3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735424121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.735424121
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.1138734515
Short name T613
Test name
Test status
Simulation time 133845136 ps
CPU time 2.52 seconds
Started Mar 03 02:35:37 PM PST 24
Finished Mar 03 02:35:39 PM PST 24
Peak memory 206176 kb
Host smart-239958b2-00ba-489a-900d-e1a75c225bd4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138734515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.1138734515
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.3440949929
Short name T759
Test name
Test status
Simulation time 22646397 ps
CPU time 1.6 seconds
Started Mar 03 02:35:38 PM PST 24
Finished Mar 03 02:35:40 PM PST 24
Peak memory 206976 kb
Host smart-9efda973-9d34-4550-98e6-1e0b79a5e1f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440949929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.3440949929
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.449813056
Short name T195
Test name
Test status
Simulation time 156651231 ps
CPU time 2.56 seconds
Started Mar 03 02:35:37 PM PST 24
Finished Mar 03 02:35:40 PM PST 24
Peak memory 207756 kb
Host smart-ad72febb-40ef-4f71-9fdf-d7c342ff9e03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=449813056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.449813056
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.3390323674
Short name T683
Test name
Test status
Simulation time 3833257372 ps
CPU time 48.54 seconds
Started Mar 03 02:35:40 PM PST 24
Finished Mar 03 02:36:28 PM PST 24
Peak memory 215548 kb
Host smart-753d99e0-139f-426f-a203-3aa8b230cad9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3390323674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.3390323674
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_stress_all_with_rand_reset.814267921
Short name T213
Test name
Test status
Simulation time 3508876772 ps
CPU time 23.04 seconds
Started Mar 03 02:35:37 PM PST 24
Finished Mar 03 02:36:01 PM PST 24
Peak memory 221092 kb
Host smart-397835a2-4f6f-45e4-8911-1c321704d347
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814267921 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all_with_rand_reset.814267921
Directory /workspace/28.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.35426980
Short name T372
Test name
Test status
Simulation time 89324823 ps
CPU time 2.27 seconds
Started Mar 03 02:35:36 PM PST 24
Finished Mar 03 02:35:39 PM PST 24
Peak memory 209452 kb
Host smart-20dba4af-e3f4-4bfc-b95b-e1224345f077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=35426980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.35426980
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.1186544652
Short name T883
Test name
Test status
Simulation time 120791875 ps
CPU time 0.87 seconds
Started Mar 03 02:35:46 PM PST 24
Finished Mar 03 02:35:47 PM PST 24
Peak memory 205552 kb
Host smart-3e0d2919-dbda-4bbf-a6d2-da37216b8a42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186544652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.1186544652
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.3030543635
Short name T401
Test name
Test status
Simulation time 236756890 ps
CPU time 6.92 seconds
Started Mar 03 02:35:43 PM PST 24
Finished Mar 03 02:35:50 PM PST 24
Peak memory 214920 kb
Host smart-95e8e541-2da4-45cb-bcaa-6f75a788037a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3030543635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.3030543635
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.1555412367
Short name T784
Test name
Test status
Simulation time 51393835 ps
CPU time 3.48 seconds
Started Mar 03 02:35:44 PM PST 24
Finished Mar 03 02:35:48 PM PST 24
Peak memory 209740 kb
Host smart-2088c72d-f234-4e40-b0f5-4b3af5da1c27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555412367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.1555412367
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.764552985
Short name T91
Test name
Test status
Simulation time 184912486 ps
CPU time 4.65 seconds
Started Mar 03 02:35:45 PM PST 24
Finished Mar 03 02:35:49 PM PST 24
Peak memory 210032 kb
Host smart-561035d7-81fa-47a7-bf96-2eeeb552a4c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764552985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.764552985
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.2302541309
Short name T763
Test name
Test status
Simulation time 407854361 ps
CPU time 3.15 seconds
Started Mar 03 02:35:41 PM PST 24
Finished Mar 03 02:35:44 PM PST 24
Peak memory 214508 kb
Host smart-9584d348-1693-4eca-8083-5deaf616a240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302541309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.2302541309
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.2205907899
Short name T633
Test name
Test status
Simulation time 240238454 ps
CPU time 4.49 seconds
Started Mar 03 02:35:43 PM PST 24
Finished Mar 03 02:35:48 PM PST 24
Peak memory 208520 kb
Host smart-d293f880-8752-48db-9276-2b2060156603
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205907899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.2205907899
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.3511670413
Short name T640
Test name
Test status
Simulation time 267053624 ps
CPU time 4.61 seconds
Started Mar 03 02:35:36 PM PST 24
Finished Mar 03 02:35:41 PM PST 24
Peak memory 207856 kb
Host smart-c8de7195-05d0-4778-bef8-1e96e01dbf0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3511670413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.3511670413
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.2037655376
Short name T255
Test name
Test status
Simulation time 156233210 ps
CPU time 3.27 seconds
Started Mar 03 02:35:47 PM PST 24
Finished Mar 03 02:35:52 PM PST 24
Peak memory 206216 kb
Host smart-e56dc669-7e70-4929-b304-487c69acfb8d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037655376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.2037655376
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.3946850269
Short name T474
Test name
Test status
Simulation time 79882772 ps
CPU time 3.87 seconds
Started Mar 03 02:35:49 PM PST 24
Finished Mar 03 02:35:53 PM PST 24
Peak memory 208004 kb
Host smart-8e3d3d20-7b35-4010-9d22-b89216debe05
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946850269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.3946850269
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.3015126625
Short name T312
Test name
Test status
Simulation time 1002595037 ps
CPU time 13.59 seconds
Started Mar 03 02:35:44 PM PST 24
Finished Mar 03 02:35:57 PM PST 24
Peak memory 207144 kb
Host smart-eeb78998-0adf-4a98-acc6-5859708fa8ad
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015126625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.3015126625
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.2918708492
Short name T270
Test name
Test status
Simulation time 644447867 ps
CPU time 5 seconds
Started Mar 03 02:35:44 PM PST 24
Finished Mar 03 02:35:49 PM PST 24
Peak memory 209204 kb
Host smart-64ae74a5-f559-4039-b01f-005db975467f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918708492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.2918708492
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.4220621194
Short name T558
Test name
Test status
Simulation time 243953979 ps
CPU time 6.14 seconds
Started Mar 03 02:35:37 PM PST 24
Finished Mar 03 02:35:43 PM PST 24
Peak memory 207152 kb
Host smart-79d08f34-72ec-465e-91a4-69e154d3dc20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220621194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.4220621194
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.728347097
Short name T506
Test name
Test status
Simulation time 457494606 ps
CPU time 4.58 seconds
Started Mar 03 02:35:44 PM PST 24
Finished Mar 03 02:35:48 PM PST 24
Peak memory 207248 kb
Host smart-29ac204b-a6a1-45ca-883c-d3361ae4a609
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728347097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.728347097
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.4155438038
Short name T35
Test name
Test status
Simulation time 108232218 ps
CPU time 1.75 seconds
Started Mar 03 02:35:45 PM PST 24
Finished Mar 03 02:35:47 PM PST 24
Peak memory 209124 kb
Host smart-2068bb58-4f1e-40e7-ace7-1318122a777c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155438038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.4155438038
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.2871191073
Short name T668
Test name
Test status
Simulation time 39299025 ps
CPU time 0.86 seconds
Started Mar 03 02:33:51 PM PST 24
Finished Mar 03 02:33:52 PM PST 24
Peak memory 205608 kb
Host smart-a44a7708-1afd-4205-b631-74157b83ce80
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2871191073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.2871191073
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.3328639683
Short name T396
Test name
Test status
Simulation time 234131193 ps
CPU time 10.17 seconds
Started Mar 03 02:33:49 PM PST 24
Finished Mar 03 02:33:59 PM PST 24
Peak memory 214508 kb
Host smart-e2cea2c0-1460-4a8f-89fc-f9b98f8615b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3328639683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.3328639683
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.3966415940
Short name T207
Test name
Test status
Simulation time 1592649642 ps
CPU time 6.65 seconds
Started Mar 03 02:33:49 PM PST 24
Finished Mar 03 02:33:56 PM PST 24
Peak memory 220372 kb
Host smart-f6054789-83ca-4aa8-a55d-d06e945bcb94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966415940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.3966415940
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.1113240626
Short name T400
Test name
Test status
Simulation time 261262316 ps
CPU time 2.33 seconds
Started Mar 03 02:33:45 PM PST 24
Finished Mar 03 02:33:47 PM PST 24
Peak memory 207812 kb
Host smart-81ab771a-c16d-45f9-a88b-fdcc89eb5971
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113240626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.1113240626
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.1828229759
Short name T607
Test name
Test status
Simulation time 102012933 ps
CPU time 3.42 seconds
Started Mar 03 02:33:45 PM PST 24
Finished Mar 03 02:33:49 PM PST 24
Peak memory 208360 kb
Host smart-bf27586d-75a3-45fe-9ad4-e0c8a12cd4c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828229759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.1828229759
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.2102281006
Short name T237
Test name
Test status
Simulation time 23167836774 ps
CPU time 84.62 seconds
Started Mar 03 02:33:43 PM PST 24
Finished Mar 03 02:35:08 PM PST 24
Peak memory 226544 kb
Host smart-88a5c440-2911-48cf-a38a-1b98b5cd25dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102281006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.2102281006
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.2918120830
Short name T863
Test name
Test status
Simulation time 96060101 ps
CPU time 3.37 seconds
Started Mar 03 02:33:44 PM PST 24
Finished Mar 03 02:33:47 PM PST 24
Peak memory 215860 kb
Host smart-5a69371d-b722-4970-88df-27bf350cab8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918120830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.2918120830
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.1094239615
Short name T248
Test name
Test status
Simulation time 679162769 ps
CPU time 6.77 seconds
Started Mar 03 02:33:45 PM PST 24
Finished Mar 03 02:33:52 PM PST 24
Peak memory 209132 kb
Host smart-ef15018b-4a67-4acb-bc51-69b0825b36dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094239615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.1094239615
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.2321883863
Short name T11
Test name
Test status
Simulation time 990755401 ps
CPU time 10.71 seconds
Started Mar 03 02:33:46 PM PST 24
Finished Mar 03 02:33:57 PM PST 24
Peak memory 230176 kb
Host smart-0708e534-cc5a-4f9f-978f-5d7841a43f02
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321883863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.2321883863
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sideload.1230840121
Short name T117
Test name
Test status
Simulation time 92846682 ps
CPU time 3.99 seconds
Started Mar 03 02:33:47 PM PST 24
Finished Mar 03 02:33:51 PM PST 24
Peak memory 207924 kb
Host smart-cd662b5b-2961-469d-b6b2-5fd88286f216
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230840121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.1230840121
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.2233597256
Short name T119
Test name
Test status
Simulation time 432788084 ps
CPU time 4.43 seconds
Started Mar 03 02:33:42 PM PST 24
Finished Mar 03 02:33:47 PM PST 24
Peak memory 208116 kb
Host smart-f902890b-aca4-4781-b634-d9c3c5e954fb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233597256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.2233597256
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.1194808397
Short name T379
Test name
Test status
Simulation time 167120413 ps
CPU time 4.06 seconds
Started Mar 03 02:33:46 PM PST 24
Finished Mar 03 02:33:50 PM PST 24
Peak memory 208480 kb
Host smart-411622e8-b516-4fbb-ab24-19da631ba83d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194808397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.1194808397
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.3633429623
Short name T599
Test name
Test status
Simulation time 571717817 ps
CPU time 14.64 seconds
Started Mar 03 02:33:44 PM PST 24
Finished Mar 03 02:33:58 PM PST 24
Peak memory 207316 kb
Host smart-898b8362-01a8-4f03-95fe-a56a0c91d9de
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3633429623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.3633429623
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.4187076592
Short name T261
Test name
Test status
Simulation time 426954781 ps
CPU time 7.68 seconds
Started Mar 03 02:33:45 PM PST 24
Finished Mar 03 02:33:53 PM PST 24
Peak memory 219800 kb
Host smart-fa59ec98-dd72-4225-918c-2e7289fdf2ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187076592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.4187076592
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.2439484692
Short name T120
Test name
Test status
Simulation time 71493234 ps
CPU time 3.11 seconds
Started Mar 03 02:33:44 PM PST 24
Finished Mar 03 02:33:47 PM PST 24
Peak memory 207972 kb
Host smart-11b4daa7-18cf-4153-8106-2277d27518e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439484692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.2439484692
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.707617335
Short name T211
Test name
Test status
Simulation time 662391517 ps
CPU time 24.19 seconds
Started Mar 03 02:33:48 PM PST 24
Finished Mar 03 02:34:13 PM PST 24
Peak memory 214576 kb
Host smart-6572a8af-e989-41a1-9dc2-bccca30d9d90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707617335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.707617335
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_stress_all_with_rand_reset.90459049
Short name T143
Test name
Test status
Simulation time 1147295631 ps
CPU time 14.2 seconds
Started Mar 03 02:33:44 PM PST 24
Finished Mar 03 02:33:59 PM PST 24
Peak memory 219800 kb
Host smart-ab080a6e-e438-4033-9246-8a09b79f001c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90459049 -assert nopostp
roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all_with_rand_reset.90459049
Directory /workspace/3.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.1431091906
Short name T882
Test name
Test status
Simulation time 208205745 ps
CPU time 5.64 seconds
Started Mar 03 02:33:45 PM PST 24
Finished Mar 03 02:33:51 PM PST 24
Peak memory 207188 kb
Host smart-b3be044e-9366-4dfb-9588-ecc7a805808c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1431091906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.1431091906
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.2652817334
Short name T371
Test name
Test status
Simulation time 201515900 ps
CPU time 2.23 seconds
Started Mar 03 02:33:45 PM PST 24
Finished Mar 03 02:33:48 PM PST 24
Peak memory 209304 kb
Host smart-897dde09-5994-4795-b70d-cff0247f59f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2652817334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.2652817334
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.3818804602
Short name T412
Test name
Test status
Simulation time 73747688 ps
CPU time 1.07 seconds
Started Mar 03 02:35:46 PM PST 24
Finished Mar 03 02:35:47 PM PST 24
Peak memory 205608 kb
Host smart-67051427-aa00-4925-a726-3bc020b5147a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818804602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.3818804602
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.682460602
Short name T343
Test name
Test status
Simulation time 73473351 ps
CPU time 4.67 seconds
Started Mar 03 02:35:44 PM PST 24
Finished Mar 03 02:35:49 PM PST 24
Peak memory 222008 kb
Host smart-1f2dfa3e-959f-45b7-9031-02d557a0240e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=682460602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.682460602
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.1973879635
Short name T755
Test name
Test status
Simulation time 1915533409 ps
CPU time 26.25 seconds
Started Mar 03 02:35:46 PM PST 24
Finished Mar 03 02:36:13 PM PST 24
Peak memory 207924 kb
Host smart-c5dfb593-c70a-4e85-9b3b-a6da55c96f8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1973879635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.1973879635
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.1418837301
Short name T192
Test name
Test status
Simulation time 3501814209 ps
CPU time 28.27 seconds
Started Mar 03 02:35:41 PM PST 24
Finished Mar 03 02:36:09 PM PST 24
Peak memory 230292 kb
Host smart-5752a90c-e0d7-465e-9879-6d07b3e94ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418837301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.1418837301
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.3744425573
Short name T57
Test name
Test status
Simulation time 83346366 ps
CPU time 4.23 seconds
Started Mar 03 02:35:43 PM PST 24
Finished Mar 03 02:35:47 PM PST 24
Peak memory 216212 kb
Host smart-dbd07e5c-682c-4bb5-8eb1-18b23b87771d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744425573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.3744425573
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.1127274817
Short name T903
Test name
Test status
Simulation time 466214339 ps
CPU time 3.97 seconds
Started Mar 03 02:35:46 PM PST 24
Finished Mar 03 02:35:50 PM PST 24
Peak memory 207264 kb
Host smart-b797b716-235d-4fa3-a57f-3e1a8ae78710
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127274817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.1127274817
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.986299649
Short name T877
Test name
Test status
Simulation time 114784398 ps
CPU time 3.63 seconds
Started Mar 03 02:35:45 PM PST 24
Finished Mar 03 02:35:48 PM PST 24
Peak memory 208000 kb
Host smart-ca2657b2-dcf2-45dc-90e5-65494950ba0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986299649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.986299649
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.4154439050
Short name T823
Test name
Test status
Simulation time 1601391684 ps
CPU time 11.34 seconds
Started Mar 03 02:35:44 PM PST 24
Finished Mar 03 02:35:55 PM PST 24
Peak memory 207580 kb
Host smart-90c78a57-f328-4809-ab22-9826896d75d0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4154439050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.4154439050
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.2049387573
Short name T885
Test name
Test status
Simulation time 37149677 ps
CPU time 2.4 seconds
Started Mar 03 02:35:44 PM PST 24
Finished Mar 03 02:35:47 PM PST 24
Peak memory 206296 kb
Host smart-56879dd6-f6b6-4f6a-9ed1-4c544bec5412
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049387573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.2049387573
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.1369170826
Short name T791
Test name
Test status
Simulation time 195784967 ps
CPU time 7.35 seconds
Started Mar 03 02:35:46 PM PST 24
Finished Mar 03 02:35:53 PM PST 24
Peak memory 207116 kb
Host smart-1f5cbc01-72c3-4bbd-a1d8-4c3afa2a1571
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369170826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.1369170826
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.3095192621
Short name T799
Test name
Test status
Simulation time 125106650 ps
CPU time 1.87 seconds
Started Mar 03 02:35:45 PM PST 24
Finished Mar 03 02:35:47 PM PST 24
Peak memory 207520 kb
Host smart-1a4a3e9c-a41a-407b-b2d6-1e610eca4cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095192621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.3095192621
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.3252038665
Short name T853
Test name
Test status
Simulation time 215044588 ps
CPU time 7.89 seconds
Started Mar 03 02:35:42 PM PST 24
Finished Mar 03 02:35:50 PM PST 24
Peak memory 206120 kb
Host smart-614315b6-bbb3-4c0a-b8fd-6f93d617bbcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252038665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.3252038665
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.1130173927
Short name T718
Test name
Test status
Simulation time 591374680 ps
CPU time 18.18 seconds
Started Mar 03 02:35:49 PM PST 24
Finished Mar 03 02:36:07 PM PST 24
Peak memory 215340 kb
Host smart-f37b74ed-8787-4984-b3bc-b1182d423557
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1130173927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.1130173927
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_stress_all_with_rand_reset.1785107626
Short name T116
Test name
Test status
Simulation time 448331558 ps
CPU time 16.66 seconds
Started Mar 03 02:35:46 PM PST 24
Finished Mar 03 02:36:03 PM PST 24
Peak memory 222188 kb
Host smart-a7cf808e-6103-4e70-b562-eeb45dc0da1f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785107626 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all_with_rand_reset.1785107626
Directory /workspace/30.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.1398334610
Short name T629
Test name
Test status
Simulation time 686049153 ps
CPU time 5.39 seconds
Started Mar 03 02:35:45 PM PST 24
Finished Mar 03 02:35:51 PM PST 24
Peak memory 209136 kb
Host smart-aef48c70-f1c4-453e-a623-6929aad90f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398334610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.1398334610
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.623519860
Short name T469
Test name
Test status
Simulation time 22719074 ps
CPU time 1.02 seconds
Started Mar 03 02:35:51 PM PST 24
Finished Mar 03 02:35:54 PM PST 24
Peak memory 205548 kb
Host smart-96154455-7069-4844-b0ff-54345667d35a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623519860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.623519860
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.1893475394
Short name T392
Test name
Test status
Simulation time 130089298 ps
CPU time 4.82 seconds
Started Mar 03 02:35:42 PM PST 24
Finished Mar 03 02:35:47 PM PST 24
Peak memory 214940 kb
Host smart-7ffcb173-db13-4095-959d-25092344b8d8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1893475394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.1893475394
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.729303375
Short name T630
Test name
Test status
Simulation time 710767701 ps
CPU time 4.63 seconds
Started Mar 03 02:35:46 PM PST 24
Finished Mar 03 02:35:50 PM PST 24
Peak memory 207536 kb
Host smart-063b8fc9-432c-4cde-b385-449e5b2faa9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729303375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.729303375
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.1066939532
Short name T757
Test name
Test status
Simulation time 147270663 ps
CPU time 4.49 seconds
Started Mar 03 02:35:48 PM PST 24
Finished Mar 03 02:35:53 PM PST 24
Peak memory 209744 kb
Host smart-15ded1bc-0243-4430-b92d-b7c67962205f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066939532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.1066939532
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.1953116357
Short name T586
Test name
Test status
Simulation time 116120757 ps
CPU time 3.73 seconds
Started Mar 03 02:35:47 PM PST 24
Finished Mar 03 02:35:52 PM PST 24
Peak memory 207756 kb
Host smart-848608da-fb0e-4822-a16d-4bb244280207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1953116357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.1953116357
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.3265854492
Short name T785
Test name
Test status
Simulation time 41817636 ps
CPU time 3.17 seconds
Started Mar 03 02:35:46 PM PST 24
Finished Mar 03 02:35:49 PM PST 24
Peak memory 207388 kb
Host smart-bfeb7605-031d-4ef3-97d4-a0c4609ba26a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3265854492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.3265854492
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.3558265656
Short name T688
Test name
Test status
Simulation time 115670145 ps
CPU time 2.33 seconds
Started Mar 03 02:35:48 PM PST 24
Finished Mar 03 02:35:51 PM PST 24
Peak memory 205588 kb
Host smart-0408a80f-e257-4b2a-8ed4-b6661c644404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3558265656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.3558265656
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.2984502011
Short name T533
Test name
Test status
Simulation time 38455903 ps
CPU time 2.52 seconds
Started Mar 03 02:35:44 PM PST 24
Finished Mar 03 02:35:47 PM PST 24
Peak memory 207972 kb
Host smart-0e61cb50-ff1e-434a-8bbf-4a4fc8e0e81c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984502011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.2984502011
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.875100924
Short name T342
Test name
Test status
Simulation time 35446680 ps
CPU time 2.61 seconds
Started Mar 03 02:35:43 PM PST 24
Finished Mar 03 02:35:45 PM PST 24
Peak memory 207960 kb
Host smart-56631526-fa26-4ad7-a5d0-4548b9a29829
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875100924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.875100924
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.3865463771
Short name T609
Test name
Test status
Simulation time 186388726 ps
CPU time 5.89 seconds
Started Mar 03 02:35:46 PM PST 24
Finished Mar 03 02:35:52 PM PST 24
Peak memory 207772 kb
Host smart-abdb0e4a-f505-4099-ad8b-56cbd0aa0daa
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3865463771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.3865463771
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.626112525
Short name T787
Test name
Test status
Simulation time 432991798 ps
CPU time 3.63 seconds
Started Mar 03 02:35:49 PM PST 24
Finished Mar 03 02:35:52 PM PST 24
Peak memory 209212 kb
Host smart-fb488bc2-f36d-46bd-80b4-4c41fd79745d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626112525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.626112525
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.497438544
Short name T676
Test name
Test status
Simulation time 605471373 ps
CPU time 3.22 seconds
Started Mar 03 02:35:43 PM PST 24
Finished Mar 03 02:35:47 PM PST 24
Peak memory 205968 kb
Host smart-9418bd50-d1fc-4225-9827-47530a8bbac2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497438544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.497438544
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.2724771253
Short name T196
Test name
Test status
Simulation time 56259691 ps
CPU time 3.65 seconds
Started Mar 03 02:35:49 PM PST 24
Finished Mar 03 02:35:53 PM PST 24
Peak memory 208524 kb
Host smart-d9a0cc67-cdb7-42ae-a9de-165bde4a5eac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724771253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.2724771253
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.2463904149
Short name T790
Test name
Test status
Simulation time 73046628 ps
CPU time 1.4 seconds
Started Mar 03 02:35:51 PM PST 24
Finished Mar 03 02:35:55 PM PST 24
Peak memory 208096 kb
Host smart-892e7a3c-cf11-4703-9078-88ba15ddb61d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463904149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.2463904149
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.255159800
Short name T419
Test name
Test status
Simulation time 28033851 ps
CPU time 0.83 seconds
Started Mar 03 02:35:52 PM PST 24
Finished Mar 03 02:35:54 PM PST 24
Peak memory 205520 kb
Host smart-00d36dd8-0578-4bf3-ad13-bee74fa0d1e3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=255159800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.255159800
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.266616468
Short name T31
Test name
Test status
Simulation time 509024224 ps
CPU time 5.67 seconds
Started Mar 03 02:35:45 PM PST 24
Finished Mar 03 02:35:51 PM PST 24
Peak memory 209648 kb
Host smart-7c24abb6-a28d-4633-b3d8-674c2ba3c697
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266616468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.266616468
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.1136170496
Short name T651
Test name
Test status
Simulation time 96238180 ps
CPU time 1.48 seconds
Started Mar 03 02:35:50 PM PST 24
Finished Mar 03 02:35:51 PM PST 24
Peak memory 206656 kb
Host smart-9a7c9869-4755-4e58-93cd-25e3aa762bc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1136170496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.1136170496
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.704835103
Short name T750
Test name
Test status
Simulation time 80371573 ps
CPU time 3.61 seconds
Started Mar 03 02:35:56 PM PST 24
Finished Mar 03 02:36:02 PM PST 24
Peak memory 213160 kb
Host smart-07924763-3ac1-4be9-b2e6-8c2e84d2cfe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704835103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.704835103
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.1214259689
Short name T235
Test name
Test status
Simulation time 149783026 ps
CPU time 6.87 seconds
Started Mar 03 02:35:48 PM PST 24
Finished Mar 03 02:35:55 PM PST 24
Peak memory 209324 kb
Host smart-7b7e4a0b-64b7-420d-a1c7-6b315614cafd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1214259689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.1214259689
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.4048533450
Short name T383
Test name
Test status
Simulation time 116402539 ps
CPU time 1.87 seconds
Started Mar 03 02:35:47 PM PST 24
Finished Mar 03 02:35:50 PM PST 24
Peak memory 208920 kb
Host smart-92bc3d25-8e5e-450a-ae53-f76c08415196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048533450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.4048533450
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.3409828771
Short name T386
Test name
Test status
Simulation time 313819358 ps
CPU time 4.04 seconds
Started Mar 03 02:35:53 PM PST 24
Finished Mar 03 02:35:58 PM PST 24
Peak memory 209252 kb
Host smart-51c45735-9d2f-4f43-90ee-93ba53a1b16d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409828771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.3409828771
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.2464071700
Short name T871
Test name
Test status
Simulation time 416822111 ps
CPU time 6.37 seconds
Started Mar 03 02:35:54 PM PST 24
Finished Mar 03 02:36:00 PM PST 24
Peak memory 207008 kb
Host smart-ac835bfb-3b1f-41a2-8e97-6d272fe87999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464071700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.2464071700
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.559024967
Short name T351
Test name
Test status
Simulation time 33632964 ps
CPU time 2.04 seconds
Started Mar 03 02:35:51 PM PST 24
Finished Mar 03 02:35:55 PM PST 24
Peak memory 207868 kb
Host smart-38f6141f-a2bc-40ef-a5ac-9b75815c52d6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559024967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.559024967
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.88050034
Short name T546
Test name
Test status
Simulation time 211352582 ps
CPU time 2.92 seconds
Started Mar 03 02:35:52 PM PST 24
Finished Mar 03 02:35:56 PM PST 24
Peak memory 206088 kb
Host smart-a7379356-132c-4c1e-ad6b-e682cd2ec730
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88050034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.88050034
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.97578057
Short name T2
Test name
Test status
Simulation time 65818961 ps
CPU time 3.41 seconds
Started Mar 03 02:35:47 PM PST 24
Finished Mar 03 02:35:52 PM PST 24
Peak memory 208268 kb
Host smart-43286f4a-9f75-4f86-9973-54753f545541
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97578057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.97578057
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.1166366833
Short name T251
Test name
Test status
Simulation time 65643917 ps
CPU time 2.53 seconds
Started Mar 03 02:35:48 PM PST 24
Finished Mar 03 02:35:51 PM PST 24
Peak memory 207536 kb
Host smart-4f0235c9-b231-411a-ba36-f84329598cd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166366833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.1166366833
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.1552641859
Short name T430
Test name
Test status
Simulation time 99871679 ps
CPU time 3.34 seconds
Started Mar 03 02:35:48 PM PST 24
Finished Mar 03 02:35:52 PM PST 24
Peak memory 205928 kb
Host smart-28b8199b-556f-4c1e-874b-bc519e25d856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552641859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.1552641859
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.3869391874
Short name T639
Test name
Test status
Simulation time 54997366172 ps
CPU time 162.91 seconds
Started Mar 03 02:35:50 PM PST 24
Finished Mar 03 02:38:36 PM PST 24
Peak memory 222100 kb
Host smart-29bf8f54-559e-4500-b712-4c1f09caeebe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869391874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.3869391874
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.2991985085
Short name T892
Test name
Test status
Simulation time 1660823463 ps
CPU time 7 seconds
Started Mar 03 02:35:50 PM PST 24
Finished Mar 03 02:36:00 PM PST 24
Peak memory 207512 kb
Host smart-9c795a9c-b654-4033-9380-6ae91bb62e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991985085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.2991985085
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.3344055267
Short name T374
Test name
Test status
Simulation time 74468688 ps
CPU time 2.23 seconds
Started Mar 03 02:35:50 PM PST 24
Finished Mar 03 02:35:56 PM PST 24
Peak memory 209448 kb
Host smart-1410ccdd-9e50-41ce-8598-8e87ca3d8e25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3344055267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.3344055267
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.3113803347
Short name T476
Test name
Test status
Simulation time 14928214 ps
CPU time 0.94 seconds
Started Mar 03 02:35:50 PM PST 24
Finished Mar 03 02:35:54 PM PST 24
Peak memory 205580 kb
Host smart-f61ed36f-e5bb-4503-89e9-e3260239281e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113803347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.3113803347
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.930782039
Short name T332
Test name
Test status
Simulation time 217877690 ps
CPU time 4.06 seconds
Started Mar 03 02:35:52 PM PST 24
Finished Mar 03 02:35:58 PM PST 24
Peak memory 214872 kb
Host smart-0d2f1bbd-f520-49a6-a59c-694604cb77a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=930782039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.930782039
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.3861052531
Short name T659
Test name
Test status
Simulation time 116194123 ps
CPU time 3.31 seconds
Started Mar 03 02:35:52 PM PST 24
Finished Mar 03 02:35:57 PM PST 24
Peak memory 208696 kb
Host smart-eccfee93-e4bd-4820-ad97-68f41f8a1573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3861052531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.3861052531
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.2387640112
Short name T55
Test name
Test status
Simulation time 345245394 ps
CPU time 5.16 seconds
Started Mar 03 02:35:52 PM PST 24
Finished Mar 03 02:35:59 PM PST 24
Peak memory 217772 kb
Host smart-ecc1ce7a-4d54-4292-8693-1ea810664619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2387640112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.2387640112
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.2781963849
Short name T515
Test name
Test status
Simulation time 759810137 ps
CPU time 12.2 seconds
Started Mar 03 02:36:01 PM PST 24
Finished Mar 03 02:36:14 PM PST 24
Peak memory 220156 kb
Host smart-de997a03-cf0e-4581-ba1f-9e77d3d9e339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781963849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.2781963849
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.3730278318
Short name T221
Test name
Test status
Simulation time 66287204 ps
CPU time 3.83 seconds
Started Mar 03 02:35:50 PM PST 24
Finished Mar 03 02:35:57 PM PST 24
Peak memory 208808 kb
Host smart-b0b71c5e-92a8-451c-a086-9901d5e0cffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730278318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.3730278318
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.3209237901
Short name T595
Test name
Test status
Simulation time 94451278 ps
CPU time 4.69 seconds
Started Mar 03 02:35:56 PM PST 24
Finished Mar 03 02:36:03 PM PST 24
Peak memory 206040 kb
Host smart-13b1b5c5-8e2b-49d3-b390-7a391d33aa5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3209237901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.3209237901
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.4245055778
Short name T526
Test name
Test status
Simulation time 1546846244 ps
CPU time 43.67 seconds
Started Mar 03 02:35:51 PM PST 24
Finished Mar 03 02:36:37 PM PST 24
Peak memory 207284 kb
Host smart-cea4c041-38fb-40d2-9361-e5dbff5972da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245055778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.4245055778
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.1110007239
Short name T555
Test name
Test status
Simulation time 825056590 ps
CPU time 6.61 seconds
Started Mar 03 02:35:49 PM PST 24
Finished Mar 03 02:35:56 PM PST 24
Peak memory 208220 kb
Host smart-492152e6-c745-4718-9d46-6c60f3400ef8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110007239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.1110007239
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.3350213039
Short name T653
Test name
Test status
Simulation time 469540261 ps
CPU time 16.13 seconds
Started Mar 03 02:35:49 PM PST 24
Finished Mar 03 02:36:06 PM PST 24
Peak memory 207836 kb
Host smart-6255452f-a5a1-4674-9ff2-d8df25a8b3ea
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350213039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.3350213039
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.3338791486
Short name T818
Test name
Test status
Simulation time 559654836 ps
CPU time 7.87 seconds
Started Mar 03 02:35:49 PM PST 24
Finished Mar 03 02:35:57 PM PST 24
Peak memory 206320 kb
Host smart-6314e2c9-0f77-461c-b725-78a90a390969
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3338791486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.3338791486
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.872170702
Short name T97
Test name
Test status
Simulation time 218368419 ps
CPU time 2.66 seconds
Started Mar 03 02:35:56 PM PST 24
Finished Mar 03 02:36:01 PM PST 24
Peak memory 208624 kb
Host smart-ad7b04d6-a970-4899-9ad1-7a73a8b7e3f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872170702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.872170702
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.2469938471
Short name T416
Test name
Test status
Simulation time 292760825 ps
CPU time 3.06 seconds
Started Mar 03 02:35:50 PM PST 24
Finished Mar 03 02:35:56 PM PST 24
Peak memory 206616 kb
Host smart-82335b7e-192b-4f23-bee5-ad207c92005b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469938471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.2469938471
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all_with_rand_reset.153791612
Short name T726
Test name
Test status
Simulation time 4884504857 ps
CPU time 26.14 seconds
Started Mar 03 02:36:00 PM PST 24
Finished Mar 03 02:36:28 PM PST 24
Peak memory 221156 kb
Host smart-68b2dedd-d0a0-484e-9406-b798629b77f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153791612 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all_with_rand_reset.153791612
Directory /workspace/33.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.2738262594
Short name T24
Test name
Test status
Simulation time 116313730 ps
CPU time 3.12 seconds
Started Mar 03 02:35:47 PM PST 24
Finished Mar 03 02:35:50 PM PST 24
Peak memory 206648 kb
Host smart-a62da13a-e0a6-4bd9-867d-c8be18e0c5c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738262594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.2738262594
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.3936944963
Short name T39
Test name
Test status
Simulation time 488185968 ps
CPU time 8.24 seconds
Started Mar 03 02:35:54 PM PST 24
Finished Mar 03 02:36:03 PM PST 24
Peak memory 210352 kb
Host smart-f9488e2f-058c-4a07-8d56-d9e5ba477db4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936944963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.3936944963
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.2609700458
Short name T409
Test name
Test status
Simulation time 22613575 ps
CPU time 0.76 seconds
Started Mar 03 02:35:55 PM PST 24
Finished Mar 03 02:35:56 PM PST 24
Peak memory 205540 kb
Host smart-a34b7fb4-4ce1-44aa-9852-f3da98f49f40
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2609700458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.2609700458
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.1799793142
Short name T376
Test name
Test status
Simulation time 35775631 ps
CPU time 2.79 seconds
Started Mar 03 02:35:48 PM PST 24
Finished Mar 03 02:35:51 PM PST 24
Peak memory 213804 kb
Host smart-ee9f8989-0b37-4453-824e-19486b999380
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1799793142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.1799793142
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.195767610
Short name T564
Test name
Test status
Simulation time 447002584 ps
CPU time 3.26 seconds
Started Mar 03 02:36:01 PM PST 24
Finished Mar 03 02:36:04 PM PST 24
Peak memory 207416 kb
Host smart-8389aedc-aa2c-40cd-94d6-b1ad35df04fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195767610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.195767610
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.475398651
Short name T455
Test name
Test status
Simulation time 33566338 ps
CPU time 2.27 seconds
Started Mar 03 02:35:57 PM PST 24
Finished Mar 03 02:36:00 PM PST 24
Peak memory 208120 kb
Host smart-ecd7c438-59a7-4982-a3ed-ef1c2b13ea4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=475398651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.475398651
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.4185724952
Short name T198
Test name
Test status
Simulation time 104012876 ps
CPU time 4.92 seconds
Started Mar 03 02:35:58 PM PST 24
Finished Mar 03 02:36:04 PM PST 24
Peak memory 213812 kb
Host smart-9d45b6db-9c4c-491f-bade-00ee3f62619d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4185724952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.4185724952
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.395422088
Short name T244
Test name
Test status
Simulation time 118586235 ps
CPU time 4.08 seconds
Started Mar 03 02:36:00 PM PST 24
Finished Mar 03 02:36:06 PM PST 24
Peak memory 209260 kb
Host smart-acc57991-4d47-4c04-a0c6-2cac930f850a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395422088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.395422088
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.2762032934
Short name T289
Test name
Test status
Simulation time 117036415 ps
CPU time 5.28 seconds
Started Mar 03 02:35:52 PM PST 24
Finished Mar 03 02:35:59 PM PST 24
Peak memory 213840 kb
Host smart-8c4e47cc-8ae2-4838-ad52-5b9d54d8424f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762032934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.2762032934
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.2463275549
Short name T865
Test name
Test status
Simulation time 647488968 ps
CPU time 2.65 seconds
Started Mar 03 02:36:00 PM PST 24
Finished Mar 03 02:36:04 PM PST 24
Peak memory 206100 kb
Host smart-ee35180e-0d53-435c-b133-38b35a952062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463275549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.2463275549
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.2000057213
Short name T793
Test name
Test status
Simulation time 33840373 ps
CPU time 2.56 seconds
Started Mar 03 02:35:49 PM PST 24
Finished Mar 03 02:35:52 PM PST 24
Peak memory 206268 kb
Host smart-6762323b-4d58-40d4-b947-da324161f1e2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000057213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.2000057213
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.3996567429
Short name T709
Test name
Test status
Simulation time 2027169854 ps
CPU time 21.26 seconds
Started Mar 03 02:36:00 PM PST 24
Finished Mar 03 02:36:23 PM PST 24
Peak memory 208120 kb
Host smart-d4c2e73c-4410-45e5-a97c-6a84e1b1109a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3996567429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.3996567429
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.3252878620
Short name T551
Test name
Test status
Simulation time 385881200 ps
CPU time 5.04 seconds
Started Mar 03 02:35:56 PM PST 24
Finished Mar 03 02:36:03 PM PST 24
Peak memory 208136 kb
Host smart-fcf82853-87ce-465a-89c6-b4a445f2b2f8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3252878620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.3252878620
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.2716897784
Short name T756
Test name
Test status
Simulation time 965997753 ps
CPU time 4.74 seconds
Started Mar 03 02:35:59 PM PST 24
Finished Mar 03 02:36:04 PM PST 24
Peak memory 208440 kb
Host smart-0c794255-e02e-449a-9bfc-833163a7a11b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716897784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.2716897784
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.136905930
Short name T597
Test name
Test status
Simulation time 104278329 ps
CPU time 3.3 seconds
Started Mar 03 02:35:51 PM PST 24
Finished Mar 03 02:35:57 PM PST 24
Peak memory 207708 kb
Host smart-8323feb2-9fa6-4af7-b71d-3f0ff3ac295b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=136905930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.136905930
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.2360883681
Short name T69
Test name
Test status
Simulation time 19124621478 ps
CPU time 70.76 seconds
Started Mar 03 02:35:55 PM PST 24
Finished Mar 03 02:37:06 PM PST 24
Peak memory 217328 kb
Host smart-bff43efd-d301-4acc-86e5-5e707cf4596b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360883681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.2360883681
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.3178487337
Short name T274
Test name
Test status
Simulation time 1530998884 ps
CPU time 5.12 seconds
Started Mar 03 02:35:54 PM PST 24
Finished Mar 03 02:36:00 PM PST 24
Peak memory 206928 kb
Host smart-3f6a7913-e866-45e5-83fe-643aecb86e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178487337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.3178487337
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.1354548792
Short name T52
Test name
Test status
Simulation time 198489273 ps
CPU time 1.72 seconds
Started Mar 03 02:35:58 PM PST 24
Finished Mar 03 02:36:01 PM PST 24
Peak memory 209260 kb
Host smart-333e022b-1afe-4d24-ba89-5697a1bf3360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354548792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.1354548792
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.2572745587
Short name T438
Test name
Test status
Simulation time 17909687 ps
CPU time 0.72 seconds
Started Mar 03 02:36:04 PM PST 24
Finished Mar 03 02:36:05 PM PST 24
Peak memory 205476 kb
Host smart-db9d7c0a-fea2-4eea-8d9c-12b80fdedac1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572745587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.2572745587
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.2101930014
Short name T297
Test name
Test status
Simulation time 30498848 ps
CPU time 2.22 seconds
Started Mar 03 02:35:55 PM PST 24
Finished Mar 03 02:35:58 PM PST 24
Peak memory 217716 kb
Host smart-e1c50c7d-0a12-46de-ac13-0a7f48fc220c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2101930014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.2101930014
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.399645147
Short name T388
Test name
Test status
Simulation time 2604771838 ps
CPU time 69.61 seconds
Started Mar 03 02:35:54 PM PST 24
Finished Mar 03 02:37:04 PM PST 24
Peak memory 213936 kb
Host smart-6a3cfb34-2196-4f3c-8efe-0ed79fdc64d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399645147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.399645147
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.1398392179
Short name T191
Test name
Test status
Simulation time 90622927 ps
CPU time 4.65 seconds
Started Mar 03 02:35:54 PM PST 24
Finished Mar 03 02:35:59 PM PST 24
Peak memory 209856 kb
Host smart-9157e3fd-5f0b-4d0f-aab6-b380d87595ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398392179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.1398392179
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.3825981031
Short name T61
Test name
Test status
Simulation time 58801868 ps
CPU time 3.68 seconds
Started Mar 03 02:35:56 PM PST 24
Finished Mar 03 02:36:00 PM PST 24
Peak memory 219996 kb
Host smart-4393bd8a-05f3-4760-a890-83fd85b7b7f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3825981031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.3825981031
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.1997360931
Short name T229
Test name
Test status
Simulation time 1307488876 ps
CPU time 9.93 seconds
Started Mar 03 02:35:55 PM PST 24
Finished Mar 03 02:36:06 PM PST 24
Peak memory 209064 kb
Host smart-4ca7c783-b402-438b-9641-00428f3b9591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997360931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.1997360931
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.1138013525
Short name T819
Test name
Test status
Simulation time 338634750 ps
CPU time 3.31 seconds
Started Mar 03 02:35:59 PM PST 24
Finished Mar 03 02:36:03 PM PST 24
Peak memory 206176 kb
Host smart-15b3d405-bb50-4af1-b263-d200f786e5b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1138013525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.1138013525
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.586704256
Short name T851
Test name
Test status
Simulation time 55635753 ps
CPU time 3.13 seconds
Started Mar 03 02:35:58 PM PST 24
Finished Mar 03 02:36:02 PM PST 24
Peak memory 207900 kb
Host smart-c48ec81c-e132-4a23-8720-ded13fa3a8e3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586704256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.586704256
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.1488101902
Short name T231
Test name
Test status
Simulation time 567739648 ps
CPU time 8.03 seconds
Started Mar 03 02:35:58 PM PST 24
Finished Mar 03 02:36:06 PM PST 24
Peak memory 207836 kb
Host smart-0b713174-c76a-4c7a-b426-7f0965ad22e2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488101902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.1488101902
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.1453400339
Short name T449
Test name
Test status
Simulation time 181971878 ps
CPU time 2.78 seconds
Started Mar 03 02:35:56 PM PST 24
Finished Mar 03 02:36:01 PM PST 24
Peak memory 206140 kb
Host smart-07cdb86c-fd23-433f-ab9b-b25c9024aff8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453400339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.1453400339
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.839302650
Short name T585
Test name
Test status
Simulation time 126761110 ps
CPU time 2.81 seconds
Started Mar 03 02:36:04 PM PST 24
Finished Mar 03 02:36:07 PM PST 24
Peak memory 208488 kb
Host smart-c0910fe3-458b-4ff4-90ba-a920939e30ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839302650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.839302650
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.2632955741
Short name T652
Test name
Test status
Simulation time 89474340 ps
CPU time 1.93 seconds
Started Mar 03 02:35:56 PM PST 24
Finished Mar 03 02:35:59 PM PST 24
Peak memory 206084 kb
Host smart-ca6ea5f8-4a0a-4e8f-aa41-a99610cf08d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632955741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.2632955741
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.3759959838
Short name T872
Test name
Test status
Simulation time 11220116018 ps
CPU time 77.3 seconds
Started Mar 03 02:36:02 PM PST 24
Finished Mar 03 02:37:20 PM PST 24
Peak memory 215648 kb
Host smart-10551646-21cf-497f-8b83-d77ad5eda8fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3759959838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.3759959838
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.3840207793
Short name T341
Test name
Test status
Simulation time 177230215 ps
CPU time 4.77 seconds
Started Mar 03 02:35:56 PM PST 24
Finished Mar 03 02:36:02 PM PST 24
Peak memory 213864 kb
Host smart-a75185b6-a340-45d5-8b9f-da310344a411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840207793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.3840207793
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.2115366684
Short name T375
Test name
Test status
Simulation time 61550911 ps
CPU time 2.43 seconds
Started Mar 03 02:36:06 PM PST 24
Finished Mar 03 02:36:08 PM PST 24
Peak memory 208984 kb
Host smart-1cee3daa-e3b8-49ef-bc50-2754bcd9a88b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115366684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.2115366684
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.2222553744
Short name T93
Test name
Test status
Simulation time 35362954 ps
CPU time 0.79 seconds
Started Mar 03 02:36:03 PM PST 24
Finished Mar 03 02:36:04 PM PST 24
Peak memory 205612 kb
Host smart-01a847ab-37dd-4be6-92bf-e24b586ed3f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2222553744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.2222553744
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.105533465
Short name T390
Test name
Test status
Simulation time 228008826 ps
CPU time 4.65 seconds
Started Mar 03 02:36:02 PM PST 24
Finished Mar 03 02:36:07 PM PST 24
Peak memory 214784 kb
Host smart-a35cecde-9e46-47b7-a3a5-6ec0389e485a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=105533465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.105533465
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.297698980
Short name T702
Test name
Test status
Simulation time 119331793 ps
CPU time 4.17 seconds
Started Mar 03 02:36:04 PM PST 24
Finished Mar 03 02:36:09 PM PST 24
Peak memory 209344 kb
Host smart-95ad2437-a8ae-4bd7-9850-42a84c9fef7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=297698980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.297698980
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.330757648
Short name T72
Test name
Test status
Simulation time 80208631 ps
CPU time 3.93 seconds
Started Mar 03 02:36:02 PM PST 24
Finished Mar 03 02:36:06 PM PST 24
Peak memory 209352 kb
Host smart-7be87f9e-8661-4c60-8a98-ec7fa8722322
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330757648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.330757648
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.28156927
Short name T83
Test name
Test status
Simulation time 3455879899 ps
CPU time 33.29 seconds
Started Mar 03 02:36:04 PM PST 24
Finished Mar 03 02:36:38 PM PST 24
Peak memory 213932 kb
Host smart-b995cdbc-aab0-491e-ab32-5ef0799bdfeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28156927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.28156927
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.368799180
Short name T647
Test name
Test status
Simulation time 153401533 ps
CPU time 7.55 seconds
Started Mar 03 02:36:03 PM PST 24
Finished Mar 03 02:36:11 PM PST 24
Peak memory 219848 kb
Host smart-9eaa93a3-a453-44b3-96f7-735d59bc909c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368799180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.368799180
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.3458350594
Short name T230
Test name
Test status
Simulation time 228805053 ps
CPU time 5.07 seconds
Started Mar 03 02:36:05 PM PST 24
Finished Mar 03 02:36:10 PM PST 24
Peak memory 209076 kb
Host smart-d7dcffb3-5f98-489c-82e5-d22c6a52b138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458350594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.3458350594
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.3756632545
Short name T748
Test name
Test status
Simulation time 210197062 ps
CPU time 7.67 seconds
Started Mar 03 02:36:03 PM PST 24
Finished Mar 03 02:36:11 PM PST 24
Peak memory 207812 kb
Host smart-724ded99-eef5-4a64-8726-15ea3c27dcaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756632545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.3756632545
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.2345464268
Short name T806
Test name
Test status
Simulation time 230986725 ps
CPU time 3.18 seconds
Started Mar 03 02:36:03 PM PST 24
Finished Mar 03 02:36:07 PM PST 24
Peak memory 206256 kb
Host smart-1c99ba1a-d2c9-4c81-8529-6e097b95a866
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345464268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.2345464268
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.1966590052
Short name T875
Test name
Test status
Simulation time 263831384 ps
CPU time 3.65 seconds
Started Mar 03 02:36:05 PM PST 24
Finished Mar 03 02:36:08 PM PST 24
Peak memory 207956 kb
Host smart-7e19e71a-dba0-4f29-be6f-f21242742fcf
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966590052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.1966590052
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.3479273529
Short name T814
Test name
Test status
Simulation time 106508322 ps
CPU time 2.98 seconds
Started Mar 03 02:36:05 PM PST 24
Finished Mar 03 02:36:08 PM PST 24
Peak memory 206176 kb
Host smart-78096cde-1bef-4d82-b058-fd899d4d2578
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3479273529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.3479273529
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.3798364087
Short name T75
Test name
Test status
Simulation time 38359024 ps
CPU time 2.11 seconds
Started Mar 03 02:36:02 PM PST 24
Finished Mar 03 02:36:04 PM PST 24
Peak memory 214896 kb
Host smart-da2888ff-0eef-4eb7-9906-791a6856766a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3798364087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.3798364087
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.786281486
Short name T527
Test name
Test status
Simulation time 188823248 ps
CPU time 2.62 seconds
Started Mar 03 02:36:05 PM PST 24
Finished Mar 03 02:36:08 PM PST 24
Peak memory 206092 kb
Host smart-5b704026-f31b-409b-a531-17c9fbb2b52c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786281486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.786281486
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.2628963275
Short name T888
Test name
Test status
Simulation time 206350088 ps
CPU time 3.65 seconds
Started Mar 03 02:36:03 PM PST 24
Finished Mar 03 02:36:07 PM PST 24
Peak memory 207104 kb
Host smart-e5dd5220-968b-433c-9024-bc3dca260132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628963275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.2628963275
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.4286205710
Short name T182
Test name
Test status
Simulation time 293552043 ps
CPU time 3.34 seconds
Started Mar 03 02:36:02 PM PST 24
Finished Mar 03 02:36:06 PM PST 24
Peak memory 209264 kb
Host smart-aae753e4-8bcb-4a5f-9288-7f01d4764995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286205710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.4286205710
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.3943830308
Short name T902
Test name
Test status
Simulation time 36984349 ps
CPU time 1.02 seconds
Started Mar 03 02:36:06 PM PST 24
Finished Mar 03 02:36:07 PM PST 24
Peak memory 205676 kb
Host smart-ff965ea9-b6c5-49d6-ad13-909d53cead18
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943830308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.3943830308
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.1703779700
Short name T398
Test name
Test status
Simulation time 195344055 ps
CPU time 3.7 seconds
Started Mar 03 02:36:03 PM PST 24
Finished Mar 03 02:36:07 PM PST 24
Peak memory 213948 kb
Host smart-16a98b91-92e2-4d4f-b033-c3cf2cddd25e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1703779700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.1703779700
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.2357628393
Short name T686
Test name
Test status
Simulation time 220360291 ps
CPU time 5.69 seconds
Started Mar 03 02:36:05 PM PST 24
Finished Mar 03 02:36:10 PM PST 24
Peak memory 209176 kb
Host smart-633d7d54-cd75-418b-a01b-1c41f9c8b47d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357628393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.2357628393
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.3201001181
Short name T804
Test name
Test status
Simulation time 899867448 ps
CPU time 4.47 seconds
Started Mar 03 02:36:02 PM PST 24
Finished Mar 03 02:36:07 PM PST 24
Peak memory 222028 kb
Host smart-7b923a75-c545-439c-8bb9-f4cd0cde83be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201001181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.3201001181
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.2330909709
Short name T828
Test name
Test status
Simulation time 112378238 ps
CPU time 3.88 seconds
Started Mar 03 02:36:03 PM PST 24
Finished Mar 03 02:36:08 PM PST 24
Peak memory 210028 kb
Host smart-7d72bd5c-844a-4e52-aad3-bf46a9773341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2330909709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.2330909709
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.2483740587
Short name T58
Test name
Test status
Simulation time 376411839 ps
CPU time 4.86 seconds
Started Mar 03 02:36:03 PM PST 24
Finished Mar 03 02:36:08 PM PST 24
Peak memory 217752 kb
Host smart-c872cd06-86f9-4dd5-b414-a184d944c369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483740587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.2483740587
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.3390918456
Short name T3
Test name
Test status
Simulation time 215710084 ps
CPU time 3.89 seconds
Started Mar 03 02:36:02 PM PST 24
Finished Mar 03 02:36:07 PM PST 24
Peak memory 207232 kb
Host smart-f6f55d31-2ab1-4e13-a9b0-d08bd65736bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3390918456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.3390918456
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.393111232
Short name T901
Test name
Test status
Simulation time 461733925 ps
CPU time 5.09 seconds
Started Mar 03 02:36:05 PM PST 24
Finished Mar 03 02:36:11 PM PST 24
Peak memory 206244 kb
Host smart-d8add8d3-e59b-459c-865c-931f0a3477ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393111232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.393111232
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.1707669605
Short name T17
Test name
Test status
Simulation time 65218998 ps
CPU time 2.97 seconds
Started Mar 03 02:36:04 PM PST 24
Finished Mar 03 02:36:07 PM PST 24
Peak memory 206112 kb
Host smart-8bdc7add-5681-4e88-9a97-5e42b0dea753
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1707669605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.1707669605
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.2248355465
Short name T576
Test name
Test status
Simulation time 337934887 ps
CPU time 7.2 seconds
Started Mar 03 02:36:03 PM PST 24
Finished Mar 03 02:36:11 PM PST 24
Peak memory 208208 kb
Host smart-74a363fc-2d48-4abf-9f33-c69b40780829
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248355465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.2248355465
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.3224525609
Short name T335
Test name
Test status
Simulation time 64845207 ps
CPU time 3.08 seconds
Started Mar 03 02:36:03 PM PST 24
Finished Mar 03 02:36:07 PM PST 24
Peak memory 207932 kb
Host smart-0f119c38-c592-404f-8934-0f817bdd7bb2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224525609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.3224525609
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.1488066895
Short name T644
Test name
Test status
Simulation time 41889318 ps
CPU time 1.73 seconds
Started Mar 03 02:36:03 PM PST 24
Finished Mar 03 02:36:05 PM PST 24
Peak memory 215384 kb
Host smart-dc470b7c-9bb0-409b-ae08-10d4d5da81a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1488066895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.1488066895
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.2927063564
Short name T769
Test name
Test status
Simulation time 112407356 ps
CPU time 3.2 seconds
Started Mar 03 02:36:02 PM PST 24
Finished Mar 03 02:36:06 PM PST 24
Peak memory 207900 kb
Host smart-4f3714c1-4121-433d-b6d3-50dc5799c80b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927063564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.2927063564
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all_with_rand_reset.994952504
Short name T171
Test name
Test status
Simulation time 384985111 ps
CPU time 13.74 seconds
Started Mar 03 02:36:01 PM PST 24
Finished Mar 03 02:36:15 PM PST 24
Peak memory 221652 kb
Host smart-a22bdbfb-e13b-4a3a-8d95-8efe0578164c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=994952504 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all_with_rand_reset.994952504
Directory /workspace/37.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.2770349995
Short name T713
Test name
Test status
Simulation time 4617757458 ps
CPU time 33.44 seconds
Started Mar 03 02:36:04 PM PST 24
Finished Mar 03 02:36:38 PM PST 24
Peak memory 217860 kb
Host smart-6d7078d9-94b2-47d9-9d16-5cf2014ba5ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770349995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.2770349995
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.2582570145
Short name T34
Test name
Test status
Simulation time 138422793 ps
CPU time 1.63 seconds
Started Mar 03 02:36:03 PM PST 24
Finished Mar 03 02:36:05 PM PST 24
Peak memory 209220 kb
Host smart-90fc9bc0-4f58-43a4-adb0-b43283c95419
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582570145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.2582570145
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.1302049755
Short name T95
Test name
Test status
Simulation time 12965096 ps
CPU time 0.78 seconds
Started Mar 03 02:36:11 PM PST 24
Finished Mar 03 02:36:12 PM PST 24
Peak memory 205532 kb
Host smart-e94c3581-35e5-45a9-a500-8894acc9719d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302049755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.1302049755
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.1249372719
Short name T399
Test name
Test status
Simulation time 151870815 ps
CPU time 3.38 seconds
Started Mar 03 02:36:12 PM PST 24
Finished Mar 03 02:36:16 PM PST 24
Peak memory 213884 kb
Host smart-55317f41-6866-4861-b5b7-32ee1c5c0126
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1249372719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.1249372719
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.3452497840
Short name T614
Test name
Test status
Simulation time 394782140 ps
CPU time 8.22 seconds
Started Mar 03 02:36:14 PM PST 24
Finished Mar 03 02:36:22 PM PST 24
Peak memory 214120 kb
Host smart-1445f9ac-1e64-4b9f-948a-c299582710f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3452497840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.3452497840
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.706488679
Short name T422
Test name
Test status
Simulation time 33889961 ps
CPU time 2.3 seconds
Started Mar 03 02:36:10 PM PST 24
Finished Mar 03 02:36:12 PM PST 24
Peak memory 207668 kb
Host smart-1f97053c-c1a6-4572-a3c3-4a19f631ebb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706488679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.706488679
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.1243114635
Short name T904
Test name
Test status
Simulation time 472623276 ps
CPU time 4.44 seconds
Started Mar 03 02:36:12 PM PST 24
Finished Mar 03 02:36:17 PM PST 24
Peak memory 208448 kb
Host smart-5e10111c-fc9d-483e-b7e3-0647a376c4df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243114635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.1243114635
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.986054613
Short name T239
Test name
Test status
Simulation time 201071522 ps
CPU time 7.16 seconds
Started Mar 03 02:36:15 PM PST 24
Finished Mar 03 02:36:22 PM PST 24
Peak memory 211048 kb
Host smart-f85c7b88-afc3-4910-b71b-4fbe4eb8ca8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=986054613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.986054613
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_random.270605040
Short name T530
Test name
Test status
Simulation time 135552325 ps
CPU time 4.82 seconds
Started Mar 03 02:36:12 PM PST 24
Finished Mar 03 02:36:17 PM PST 24
Peak memory 213864 kb
Host smart-8eb4d69f-7236-4615-8579-71b10a78833a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270605040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.270605040
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.2093631828
Short name T841
Test name
Test status
Simulation time 489353552 ps
CPU time 2.47 seconds
Started Mar 03 02:36:01 PM PST 24
Finished Mar 03 02:36:05 PM PST 24
Peak memory 206156 kb
Host smart-1608d94f-0a15-4655-afcc-a81f39a61158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093631828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.2093631828
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.1287291543
Short name T866
Test name
Test status
Simulation time 96926293 ps
CPU time 3 seconds
Started Mar 03 02:36:10 PM PST 24
Finished Mar 03 02:36:13 PM PST 24
Peak memory 206236 kb
Host smart-7cc37c6e-3486-4675-a6a9-79374019b47c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1287291543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.1287291543
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.1587657324
Short name T831
Test name
Test status
Simulation time 502537732 ps
CPU time 6 seconds
Started Mar 03 02:36:02 PM PST 24
Finished Mar 03 02:36:09 PM PST 24
Peak memory 207644 kb
Host smart-784ce37a-3a22-46f1-96d6-5b29eb64f339
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587657324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.1587657324
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.185713051
Short name T654
Test name
Test status
Simulation time 51223579 ps
CPU time 2.66 seconds
Started Mar 03 02:36:11 PM PST 24
Finished Mar 03 02:36:14 PM PST 24
Peak memory 208048 kb
Host smart-02ecc8a5-85d2-4af5-b6fa-32947d0a645a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185713051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.185713051
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.2711197027
Short name T650
Test name
Test status
Simulation time 56442953 ps
CPU time 2.02 seconds
Started Mar 03 02:36:16 PM PST 24
Finished Mar 03 02:36:18 PM PST 24
Peak memory 208416 kb
Host smart-25353e9d-a05a-4ee6-b1d0-774837940d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711197027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.2711197027
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.3486551591
Short name T495
Test name
Test status
Simulation time 57646438 ps
CPU time 2.86 seconds
Started Mar 03 02:36:03 PM PST 24
Finished Mar 03 02:36:06 PM PST 24
Peak memory 207604 kb
Host smart-db6e5a6f-a3c4-45ed-a6a1-04b54448cdf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486551591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.3486551591
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all_with_rand_reset.777008207
Short name T115
Test name
Test status
Simulation time 220469992 ps
CPU time 8.74 seconds
Started Mar 03 02:36:15 PM PST 24
Finished Mar 03 02:36:24 PM PST 24
Peak memory 219800 kb
Host smart-7812cecf-bcab-438f-9470-aa43c19ceb90
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777008207 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all_with_rand_reset.777008207
Directory /workspace/38.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.742060187
Short name T761
Test name
Test status
Simulation time 349479815 ps
CPU time 3.74 seconds
Started Mar 03 02:36:10 PM PST 24
Finished Mar 03 02:36:14 PM PST 24
Peak memory 206720 kb
Host smart-7c5e9624-8789-41e4-9027-2a64d44fa178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=742060187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.742060187
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.3458046336
Short name T188
Test name
Test status
Simulation time 142562149 ps
CPU time 2.99 seconds
Started Mar 03 02:36:08 PM PST 24
Finished Mar 03 02:36:12 PM PST 24
Peak memory 209692 kb
Host smart-ad25eb70-b29d-4b77-ac40-766ae54da856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3458046336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.3458046336
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.1114669032
Short name T547
Test name
Test status
Simulation time 22346507 ps
CPU time 1.02 seconds
Started Mar 03 02:36:18 PM PST 24
Finished Mar 03 02:36:19 PM PST 24
Peak memory 205536 kb
Host smart-f7e59904-2c30-4330-82c9-fa2953906219
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114669032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.1114669032
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.573469736
Short name T800
Test name
Test status
Simulation time 121629341 ps
CPU time 2.55 seconds
Started Mar 03 02:36:10 PM PST 24
Finished Mar 03 02:36:13 PM PST 24
Peak memory 208720 kb
Host smart-d4bdc853-0d35-4540-92a1-0af527fc9f8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573469736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.573469736
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.1829067048
Short name T54
Test name
Test status
Simulation time 320168012 ps
CPU time 6.35 seconds
Started Mar 03 02:36:12 PM PST 24
Finished Mar 03 02:36:19 PM PST 24
Peak memory 209280 kb
Host smart-23ba43ce-9593-4460-b7ac-b42df6d4cbe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829067048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.1829067048
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.3641823616
Short name T577
Test name
Test status
Simulation time 626261308 ps
CPU time 11.44 seconds
Started Mar 03 02:36:13 PM PST 24
Finished Mar 03 02:36:26 PM PST 24
Peak memory 209208 kb
Host smart-f1524788-5d74-4bc0-8860-bec74f7de95e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641823616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.3641823616
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.2326971046
Short name T725
Test name
Test status
Simulation time 771316988 ps
CPU time 3.8 seconds
Started Mar 03 02:36:14 PM PST 24
Finished Mar 03 02:36:18 PM PST 24
Peak memory 213796 kb
Host smart-c72f3ac5-7fbd-4d57-ad26-f7341d041354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2326971046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.2326971046
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.3939565938
Short name T345
Test name
Test status
Simulation time 240695539 ps
CPU time 6.89 seconds
Started Mar 03 02:36:14 PM PST 24
Finished Mar 03 02:36:21 PM PST 24
Peak memory 213800 kb
Host smart-8bf77620-413c-4c21-aa4d-12c1148c2efb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939565938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.3939565938
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.2702903057
Short name T444
Test name
Test status
Simulation time 78443548 ps
CPU time 3.43 seconds
Started Mar 03 02:36:16 PM PST 24
Finished Mar 03 02:36:19 PM PST 24
Peak memory 205996 kb
Host smart-e12d7ce2-7b28-4bb8-9ba1-af81349341ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702903057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.2702903057
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.3883615708
Short name T252
Test name
Test status
Simulation time 94796749 ps
CPU time 2.78 seconds
Started Mar 03 02:36:11 PM PST 24
Finished Mar 03 02:36:14 PM PST 24
Peak memory 206080 kb
Host smart-81ffffc7-4873-4618-87fd-7066583aeffb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3883615708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.3883615708
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.2029996976
Short name T199
Test name
Test status
Simulation time 482272827 ps
CPU time 2.76 seconds
Started Mar 03 02:36:10 PM PST 24
Finished Mar 03 02:36:13 PM PST 24
Peak memory 206140 kb
Host smart-5cbbfdaf-f149-40f2-8074-1bdbe97eafd7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029996976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.2029996976
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.850185305
Short name T387
Test name
Test status
Simulation time 68213201 ps
CPU time 3.56 seconds
Started Mar 03 02:36:18 PM PST 24
Finished Mar 03 02:36:21 PM PST 24
Peak memory 207968 kb
Host smart-3df0846d-d32f-47fe-b757-b5fa8e6f8708
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850185305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.850185305
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.798540080
Short name T896
Test name
Test status
Simulation time 4314294992 ps
CPU time 6 seconds
Started Mar 03 02:36:10 PM PST 24
Finished Mar 03 02:36:16 PM PST 24
Peak memory 209340 kb
Host smart-104ea033-64a1-4e3d-9b26-e8f2ac9a5bb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798540080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.798540080
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.2004253833
Short name T783
Test name
Test status
Simulation time 35675528 ps
CPU time 2.29 seconds
Started Mar 03 02:36:10 PM PST 24
Finished Mar 03 02:36:13 PM PST 24
Peak memory 206016 kb
Host smart-69a78fdf-f7cc-4930-b4fe-48b7dc734b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2004253833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.2004253833
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.1981044932
Short name T744
Test name
Test status
Simulation time 284160112 ps
CPU time 3.98 seconds
Started Mar 03 02:36:13 PM PST 24
Finished Mar 03 02:36:17 PM PST 24
Peak memory 206748 kb
Host smart-c1663409-356b-46a1-9845-fb08fafc2b73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981044932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.1981044932
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.2930702613
Short name T552
Test name
Test status
Simulation time 94615116 ps
CPU time 2.49 seconds
Started Mar 03 02:36:11 PM PST 24
Finished Mar 03 02:36:14 PM PST 24
Peak memory 209560 kb
Host smart-607b3c66-6e43-438c-9476-329cc289cbb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930702613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.2930702613
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.1242225022
Short name T457
Test name
Test status
Simulation time 179180128 ps
CPU time 0.82 seconds
Started Mar 03 02:33:59 PM PST 24
Finished Mar 03 02:34:00 PM PST 24
Peak memory 205612 kb
Host smart-dae8c379-fbbb-470a-ada2-115e24e367f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1242225022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.1242225022
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.909165436
Short name T406
Test name
Test status
Simulation time 310061598 ps
CPU time 2.61 seconds
Started Mar 03 02:33:52 PM PST 24
Finished Mar 03 02:33:54 PM PST 24
Peak memory 213872 kb
Host smart-42ea98b6-c06d-47cf-a7d4-2bbb80270c05
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=909165436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.909165436
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.3489380041
Short name T852
Test name
Test status
Simulation time 56623915 ps
CPU time 3.05 seconds
Started Mar 03 02:33:49 PM PST 24
Finished Mar 03 02:33:52 PM PST 24
Peak memory 208892 kb
Host smart-aa745131-888a-4af1-9b43-bc358d0afc66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489380041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.3489380041
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.1350176278
Short name T796
Test name
Test status
Simulation time 751214803 ps
CPU time 3.6 seconds
Started Mar 03 02:33:53 PM PST 24
Finished Mar 03 02:33:57 PM PST 24
Peak memory 207408 kb
Host smart-dd45cc1b-89cc-459b-ae8a-57ba1a50a4bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350176278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.1350176278
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.416629117
Short name T287
Test name
Test status
Simulation time 144081495 ps
CPU time 3.61 seconds
Started Mar 03 02:33:51 PM PST 24
Finished Mar 03 02:33:55 PM PST 24
Peak memory 207948 kb
Host smart-293f721c-4f61-48ce-9e77-27e45ee69c04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=416629117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.416629117
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.3656604015
Short name T730
Test name
Test status
Simulation time 325083009 ps
CPU time 10.59 seconds
Started Mar 03 02:33:52 PM PST 24
Finished Mar 03 02:34:03 PM PST 24
Peak memory 210900 kb
Host smart-64089d01-2ccf-4bb2-a047-1bfa6edc2eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3656604015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.3656604015
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.825210700
Short name T253
Test name
Test status
Simulation time 54102513 ps
CPU time 2.91 seconds
Started Mar 03 02:33:52 PM PST 24
Finished Mar 03 02:33:55 PM PST 24
Peak memory 209404 kb
Host smart-8e06fdc2-0e0c-4f39-87dd-07a819bacca0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=825210700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.825210700
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.2416315882
Short name T817
Test name
Test status
Simulation time 161622486 ps
CPU time 6.42 seconds
Started Mar 03 02:33:50 PM PST 24
Finished Mar 03 02:33:56 PM PST 24
Peak memory 208392 kb
Host smart-260fb971-378d-4951-8f59-04dc535328b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416315882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.2416315882
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.1865001187
Short name T40
Test name
Test status
Simulation time 33570721744 ps
CPU time 186.62 seconds
Started Mar 03 02:33:59 PM PST 24
Finished Mar 03 02:37:05 PM PST 24
Peak memory 289988 kb
Host smart-2f3565f6-a8f5-49f7-84f4-57bfc51c643b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865001187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.1865001187
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.435916691
Short name T692
Test name
Test status
Simulation time 330667695 ps
CPU time 4.89 seconds
Started Mar 03 02:33:51 PM PST 24
Finished Mar 03 02:33:56 PM PST 24
Peak memory 207764 kb
Host smart-655caa88-d787-484e-b81b-2ec2b3065a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435916691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.435916691
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.931005855
Short name T436
Test name
Test status
Simulation time 65792895 ps
CPU time 2.28 seconds
Started Mar 03 02:33:53 PM PST 24
Finished Mar 03 02:33:55 PM PST 24
Peak memory 208052 kb
Host smart-53caf11e-32f3-49c9-a9c0-90746b3d743c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=931005855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.931005855
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.2908954822
Short name T843
Test name
Test status
Simulation time 72109899 ps
CPU time 2.96 seconds
Started Mar 03 02:33:52 PM PST 24
Finished Mar 03 02:33:55 PM PST 24
Peak memory 206176 kb
Host smart-8c519e87-1db7-4126-a71d-be77073b9ada
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2908954822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.2908954822
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.556360299
Short name T337
Test name
Test status
Simulation time 26235805 ps
CPU time 2.11 seconds
Started Mar 03 02:33:51 PM PST 24
Finished Mar 03 02:33:53 PM PST 24
Peak memory 207956 kb
Host smart-547d7963-c99f-4b53-ad6a-78c93c759064
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556360299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.556360299
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.3318734267
Short name T745
Test name
Test status
Simulation time 116770056 ps
CPU time 3.81 seconds
Started Mar 03 02:33:53 PM PST 24
Finished Mar 03 02:33:57 PM PST 24
Peak memory 215396 kb
Host smart-190cc453-9399-40cc-b717-dd295080754e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318734267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.3318734267
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.321495622
Short name T532
Test name
Test status
Simulation time 60369030 ps
CPU time 2.74 seconds
Started Mar 03 02:33:51 PM PST 24
Finished Mar 03 02:33:53 PM PST 24
Peak memory 207832 kb
Host smart-19938b22-0498-486c-be67-285f3c412c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=321495622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.321495622
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.2115982308
Short name T7
Test name
Test status
Simulation time 3444339014 ps
CPU time 24.63 seconds
Started Mar 03 02:33:58 PM PST 24
Finished Mar 03 02:34:23 PM PST 24
Peak memory 219332 kb
Host smart-b48c059a-d240-4256-9830-d0c42633515c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2115982308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.2115982308
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.1227493848
Short name T720
Test name
Test status
Simulation time 133307055 ps
CPU time 6.09 seconds
Started Mar 03 02:33:52 PM PST 24
Finished Mar 03 02:33:58 PM PST 24
Peak memory 217928 kb
Host smart-35c3a1a9-1896-48e2-a635-64d040dda745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1227493848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.1227493848
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.3743357359
Short name T879
Test name
Test status
Simulation time 27130388 ps
CPU time 0.92 seconds
Started Mar 03 02:36:14 PM PST 24
Finished Mar 03 02:36:16 PM PST 24
Peak memory 205600 kb
Host smart-f78431dd-569d-46f4-adb8-fb2417a10e2e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743357359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.3743357359
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.458356405
Short name T587
Test name
Test status
Simulation time 144108845 ps
CPU time 2.06 seconds
Started Mar 03 02:36:18 PM PST 24
Finished Mar 03 02:36:21 PM PST 24
Peak memory 207924 kb
Host smart-c69a6102-a19f-4f58-bc3a-dfd07487f8bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458356405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.458356405
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.3166566257
Short name T480
Test name
Test status
Simulation time 37171421 ps
CPU time 1.69 seconds
Started Mar 03 02:36:16 PM PST 24
Finished Mar 03 02:36:18 PM PST 24
Peak memory 207472 kb
Host smart-ff081eb1-1136-4c53-ad25-ae6ccce75414
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166566257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.3166566257
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.22588240
Short name T721
Test name
Test status
Simulation time 203189843 ps
CPU time 7.47 seconds
Started Mar 03 02:36:18 PM PST 24
Finished Mar 03 02:36:26 PM PST 24
Peak memory 221972 kb
Host smart-4eae51ec-d5dc-4036-a3fe-dc5c25581a38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22588240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.22588240
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.968682208
Short name T674
Test name
Test status
Simulation time 235069250 ps
CPU time 4.6 seconds
Started Mar 03 02:36:16 PM PST 24
Finished Mar 03 02:36:21 PM PST 24
Peak memory 213928 kb
Host smart-a705058d-7306-4fdf-b161-43dc406e4cd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968682208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.968682208
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.1565032760
Short name T194
Test name
Test status
Simulation time 74019227 ps
CPU time 3.63 seconds
Started Mar 03 02:36:15 PM PST 24
Finished Mar 03 02:36:19 PM PST 24
Peak memory 209132 kb
Host smart-bcfc7dd5-9825-4e50-9ae2-a0a64b0c382a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565032760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.1565032760
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.3525992299
Short name T838
Test name
Test status
Simulation time 170929690 ps
CPU time 2.68 seconds
Started Mar 03 02:36:14 PM PST 24
Finished Mar 03 02:36:18 PM PST 24
Peak memory 207816 kb
Host smart-3093eba4-2272-4288-a8bd-1d919f7d8949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3525992299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.3525992299
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.1821341013
Short name T782
Test name
Test status
Simulation time 77340994 ps
CPU time 1.72 seconds
Started Mar 03 02:36:10 PM PST 24
Finished Mar 03 02:36:12 PM PST 24
Peak memory 206184 kb
Host smart-bb0f4106-78d1-4ea2-b1c3-655b0e37384f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821341013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.1821341013
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.4188183917
Short name T675
Test name
Test status
Simulation time 3130369626 ps
CPU time 42.46 seconds
Started Mar 03 02:36:13 PM PST 24
Finished Mar 03 02:36:55 PM PST 24
Peak memory 208288 kb
Host smart-a29f2cd1-d547-4e5d-89e6-0b063a980c6f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188183917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.4188183917
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.2185910472
Short name T477
Test name
Test status
Simulation time 53215871 ps
CPU time 2.86 seconds
Started Mar 03 02:36:10 PM PST 24
Finished Mar 03 02:36:13 PM PST 24
Peak memory 206172 kb
Host smart-d358a73e-5ac4-439a-bdba-c098f3de401a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2185910472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.2185910472
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.3365475273
Short name T442
Test name
Test status
Simulation time 183956598 ps
CPU time 3.86 seconds
Started Mar 03 02:36:17 PM PST 24
Finished Mar 03 02:36:21 PM PST 24
Peak memory 214960 kb
Host smart-7808b57d-a7f5-4042-9c78-6cba6923ae4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365475273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.3365475273
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.2762423227
Short name T540
Test name
Test status
Simulation time 340313887 ps
CPU time 3.48 seconds
Started Mar 03 02:36:12 PM PST 24
Finished Mar 03 02:36:16 PM PST 24
Peak memory 207632 kb
Host smart-7fbd4178-a30b-4301-952d-f60ef4e37bbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762423227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.2762423227
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.1997175547
Short name T219
Test name
Test status
Simulation time 937809187 ps
CPU time 26.82 seconds
Started Mar 03 02:36:14 PM PST 24
Finished Mar 03 02:36:41 PM PST 24
Peak memory 220376 kb
Host smart-cfb59fd1-d943-4987-8058-f0063132b0f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997175547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.1997175547
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.1699860494
Short name T627
Test name
Test status
Simulation time 57145277 ps
CPU time 3.73 seconds
Started Mar 03 02:36:14 PM PST 24
Finished Mar 03 02:36:18 PM PST 24
Peak memory 217896 kb
Host smart-fcb21d21-c1ef-46e4-a99d-fa7f2eb1dad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699860494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.1699860494
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.2346052028
Short name T699
Test name
Test status
Simulation time 502808749 ps
CPU time 3.29 seconds
Started Mar 03 02:36:18 PM PST 24
Finished Mar 03 02:36:21 PM PST 24
Peak memory 209456 kb
Host smart-3a08f034-ce46-49f9-bf0f-42168eea8156
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346052028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.2346052028
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.1444249001
Short name T451
Test name
Test status
Simulation time 17371487 ps
CPU time 0.97 seconds
Started Mar 03 02:36:14 PM PST 24
Finished Mar 03 02:36:15 PM PST 24
Peak memory 205532 kb
Host smart-045f2271-5203-4906-86d3-50436a873f8a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444249001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.1444249001
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.4023340916
Short name T402
Test name
Test status
Simulation time 282969370 ps
CPU time 7.16 seconds
Started Mar 03 02:36:17 PM PST 24
Finished Mar 03 02:36:24 PM PST 24
Peak memory 222056 kb
Host smart-89d118a9-0a82-43ba-a26b-4e3836c9236b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4023340916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.4023340916
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.8228316
Short name T37
Test name
Test status
Simulation time 255442918 ps
CPU time 3.74 seconds
Started Mar 03 02:36:15 PM PST 24
Finished Mar 03 02:36:19 PM PST 24
Peak memory 217372 kb
Host smart-4a4f4119-95d0-489e-9215-9305336e473a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8228316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.8228316
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.1696056303
Short name T795
Test name
Test status
Simulation time 186770395 ps
CPU time 3.67 seconds
Started Mar 03 02:36:16 PM PST 24
Finished Mar 03 02:36:20 PM PST 24
Peak memory 209412 kb
Host smart-4a93f62d-7049-4c28-893d-b2d26764274e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696056303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.1696056303
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.2510250044
Short name T864
Test name
Test status
Simulation time 530862222 ps
CPU time 4.64 seconds
Started Mar 03 02:36:18 PM PST 24
Finished Mar 03 02:36:22 PM PST 24
Peak memory 219176 kb
Host smart-a964fba7-e8ce-467a-a81f-592aa221b5e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510250044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.2510250044
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.2014543897
Short name T858
Test name
Test status
Simulation time 57251972 ps
CPU time 3.01 seconds
Started Mar 03 02:36:16 PM PST 24
Finished Mar 03 02:36:19 PM PST 24
Peak memory 207992 kb
Host smart-17bd5d3a-d430-4671-a492-38f62e0957f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014543897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.2014543897
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.3090096903
Short name T886
Test name
Test status
Simulation time 164563637 ps
CPU time 3.59 seconds
Started Mar 03 02:36:15 PM PST 24
Finished Mar 03 02:36:19 PM PST 24
Peak memory 209184 kb
Host smart-b281ea76-20d3-445d-9c99-4cfae4d8bd5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090096903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.3090096903
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.3839179975
Short name T482
Test name
Test status
Simulation time 1577909616 ps
CPU time 20.01 seconds
Started Mar 03 02:36:16 PM PST 24
Finished Mar 03 02:36:36 PM PST 24
Peak memory 207768 kb
Host smart-6bb03db9-56eb-481e-b9e8-2a0326ea082a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3839179975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.3839179975
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.433871062
Short name T461
Test name
Test status
Simulation time 442099834 ps
CPU time 2.65 seconds
Started Mar 03 02:36:16 PM PST 24
Finished Mar 03 02:36:19 PM PST 24
Peak memory 206120 kb
Host smart-c81c4dca-3b5c-4406-abbd-6e44c9cffea1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433871062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.433871062
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.2863525809
Short name T701
Test name
Test status
Simulation time 141156057 ps
CPU time 5.23 seconds
Started Mar 03 02:36:15 PM PST 24
Finished Mar 03 02:36:20 PM PST 24
Peak memory 207268 kb
Host smart-8afd4966-fd9a-4748-b95d-600c1796b9cf
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863525809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.2863525809
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.3892157139
Short name T176
Test name
Test status
Simulation time 880366754 ps
CPU time 9.84 seconds
Started Mar 03 02:36:19 PM PST 24
Finished Mar 03 02:36:29 PM PST 24
Peak memory 208000 kb
Host smart-1247fcb5-d443-4bba-83d7-c456bbb5178e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892157139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.3892157139
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.3204848377
Short name T905
Test name
Test status
Simulation time 50851946 ps
CPU time 1.64 seconds
Started Mar 03 02:36:18 PM PST 24
Finished Mar 03 02:36:20 PM PST 24
Peak memory 209196 kb
Host smart-7a5ff3c8-1aaf-405d-813a-fb32ae6279b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204848377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.3204848377
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.130675703
Short name T411
Test name
Test status
Simulation time 642833117 ps
CPU time 7.41 seconds
Started Mar 03 02:36:14 PM PST 24
Finished Mar 03 02:36:22 PM PST 24
Peak memory 206040 kb
Host smart-9e79a679-5987-45c7-b000-fded05331a83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=130675703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.130675703
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.3480049154
Short name T797
Test name
Test status
Simulation time 8293655933 ps
CPU time 64.48 seconds
Started Mar 03 02:36:18 PM PST 24
Finished Mar 03 02:37:22 PM PST 24
Peak memory 222044 kb
Host smart-7812060f-8406-4f73-802f-62b48da8f45a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3480049154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.3480049154
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.3735315140
Short name T656
Test name
Test status
Simulation time 300319938 ps
CPU time 3.63 seconds
Started Mar 03 02:36:18 PM PST 24
Finished Mar 03 02:36:22 PM PST 24
Peak memory 206224 kb
Host smart-6a9449fe-286f-4e15-bf5e-e9233963c8dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3735315140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.3735315140
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.1147483993
Short name T56
Test name
Test status
Simulation time 1594792578 ps
CPU time 27.92 seconds
Started Mar 03 02:36:16 PM PST 24
Finished Mar 03 02:36:44 PM PST 24
Peak memory 209832 kb
Host smart-9a52c3d2-b07b-4706-a9b6-8f495fa72c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147483993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.1147483993
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.1940263123
Short name T557
Test name
Test status
Simulation time 10661112 ps
CPU time 0.75 seconds
Started Mar 03 02:36:21 PM PST 24
Finished Mar 03 02:36:23 PM PST 24
Peak memory 205608 kb
Host smart-2612a46d-cecc-4e12-9703-611f90c4ef5f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1940263123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.1940263123
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.3465607183
Short name T391
Test name
Test status
Simulation time 60055289 ps
CPU time 4.34 seconds
Started Mar 03 02:36:20 PM PST 24
Finished Mar 03 02:36:25 PM PST 24
Peak memory 214456 kb
Host smart-583cffcc-d604-4096-a4f3-a0836cb86342
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3465607183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.3465607183
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.4201086323
Short name T9
Test name
Test status
Simulation time 92336415 ps
CPU time 2.05 seconds
Started Mar 03 02:36:21 PM PST 24
Finished Mar 03 02:36:24 PM PST 24
Peak memory 207884 kb
Host smart-2a0b3863-3bcf-41a3-a270-40fa61248b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201086323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.4201086323
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.2417812100
Short name T881
Test name
Test status
Simulation time 72742307 ps
CPU time 1.69 seconds
Started Mar 03 02:36:21 PM PST 24
Finished Mar 03 02:36:24 PM PST 24
Peak memory 208284 kb
Host smart-9c2624ae-9dd1-4f70-a9e4-6aae0437fbd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417812100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.2417812100
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.3849048985
Short name T355
Test name
Test status
Simulation time 124080269 ps
CPU time 3.53 seconds
Started Mar 03 02:36:22 PM PST 24
Finished Mar 03 02:36:26 PM PST 24
Peak memory 221692 kb
Host smart-fd361fb9-e953-4aab-a5a8-f28fe3237077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849048985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.3849048985
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.4060787727
Short name T216
Test name
Test status
Simulation time 502862623 ps
CPU time 25.94 seconds
Started Mar 03 02:36:23 PM PST 24
Finished Mar 03 02:36:49 PM PST 24
Peak memory 209316 kb
Host smart-f9a2d330-62c9-4240-a138-a8a734c8c260
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060787727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.4060787727
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.1353247802
Short name T493
Test name
Test status
Simulation time 976214963 ps
CPU time 8.33 seconds
Started Mar 03 02:36:23 PM PST 24
Finished Mar 03 02:36:31 PM PST 24
Peak memory 208400 kb
Host smart-bb209e8c-066c-417b-88de-fd50f2f8f360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353247802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.1353247802
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.1675982299
Short name T421
Test name
Test status
Simulation time 47800562 ps
CPU time 2.62 seconds
Started Mar 03 02:36:16 PM PST 24
Finished Mar 03 02:36:19 PM PST 24
Peak memory 206100 kb
Host smart-4a6bf28f-fe46-439c-8502-42b2b510e42c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1675982299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.1675982299
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.2212832522
Short name T845
Test name
Test status
Simulation time 63192210 ps
CPU time 2.32 seconds
Started Mar 03 02:36:16 PM PST 24
Finished Mar 03 02:36:18 PM PST 24
Peak memory 206692 kb
Host smart-8927e011-91d0-4071-a6c9-2919f6dacbd7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2212832522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.2212832522
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.2834937002
Short name T76
Test name
Test status
Simulation time 27271299 ps
CPU time 2.07 seconds
Started Mar 03 02:36:19 PM PST 24
Finished Mar 03 02:36:21 PM PST 24
Peak memory 207780 kb
Host smart-dfc9527e-bdb0-4884-a504-38f818651c99
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834937002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.2834937002
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.282611603
Short name T677
Test name
Test status
Simulation time 32123070 ps
CPU time 2.12 seconds
Started Mar 03 02:36:14 PM PST 24
Finished Mar 03 02:36:16 PM PST 24
Peak memory 208108 kb
Host smart-24351feb-66b1-4a48-b616-2aed14bc5605
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282611603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.282611603
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.526738073
Short name T805
Test name
Test status
Simulation time 106399605 ps
CPU time 3.34 seconds
Started Mar 03 02:36:20 PM PST 24
Finished Mar 03 02:36:24 PM PST 24
Peak memory 208028 kb
Host smart-6361f969-bc5b-49e0-abef-fdd06d6a765f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526738073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.526738073
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.3381959546
Short name T534
Test name
Test status
Simulation time 591248216 ps
CPU time 7.21 seconds
Started Mar 03 02:36:19 PM PST 24
Finished Mar 03 02:36:27 PM PST 24
Peak memory 207780 kb
Host smart-668f4536-85c9-4d99-9927-a5ac4eaa208d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381959546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.3381959546
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.1056467105
Short name T365
Test name
Test status
Simulation time 205365742 ps
CPU time 3.46 seconds
Started Mar 03 02:36:22 PM PST 24
Finished Mar 03 02:36:26 PM PST 24
Peak memory 219948 kb
Host smart-78720ebc-0340-4bab-98a7-70aceddc1bfd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1056467105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.1056467105
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.3351035740
Short name T807
Test name
Test status
Simulation time 223887309 ps
CPU time 7.21 seconds
Started Mar 03 02:36:24 PM PST 24
Finished Mar 03 02:36:32 PM PST 24
Peak memory 217756 kb
Host smart-91527501-cfa0-47b4-bd18-c7e2654dfcd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3351035740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.3351035740
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.4023046873
Short name T897
Test name
Test status
Simulation time 873457316 ps
CPU time 2.52 seconds
Started Mar 03 02:36:22 PM PST 24
Finished Mar 03 02:36:25 PM PST 24
Peak memory 209312 kb
Host smart-be99c5f8-d03d-471f-899c-f07091c957a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023046873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.4023046873
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.578071971
Short name T887
Test name
Test status
Simulation time 25729717 ps
CPU time 0.89 seconds
Started Mar 03 02:36:31 PM PST 24
Finished Mar 03 02:36:33 PM PST 24
Peak memory 205664 kb
Host smart-d23ddc98-09bb-419a-8d02-f84b57754384
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=578071971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.578071971
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.1381304824
Short name T348
Test name
Test status
Simulation time 65222201 ps
CPU time 2.69 seconds
Started Mar 03 02:36:23 PM PST 24
Finished Mar 03 02:36:26 PM PST 24
Peak memory 213812 kb
Host smart-87ecd721-c04e-4156-bc8e-4ba089e3ebd5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1381304824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.1381304824
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.2928852121
Short name T776
Test name
Test status
Simulation time 25385683 ps
CPU time 1.24 seconds
Started Mar 03 02:36:26 PM PST 24
Finished Mar 03 02:36:28 PM PST 24
Peak memory 206256 kb
Host smart-44326922-2c75-4ba8-87cf-bcbab070454e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2928852121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.2928852121
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.3034766428
Short name T462
Test name
Test status
Simulation time 380756752 ps
CPU time 5.21 seconds
Started Mar 03 02:36:28 PM PST 24
Finished Mar 03 02:36:34 PM PST 24
Peak memory 209564 kb
Host smart-a38c9b7b-8cde-477e-9739-865106021f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3034766428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.3034766428
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.1756622282
Short name T260
Test name
Test status
Simulation time 1279573456 ps
CPU time 11.34 seconds
Started Mar 03 02:36:26 PM PST 24
Finished Mar 03 02:36:38 PM PST 24
Peak memory 221948 kb
Host smart-4ef81d5c-1073-4b9a-afa1-87ee5c6d0947
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756622282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.1756622282
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.3840410852
Short name T498
Test name
Test status
Simulation time 142358927 ps
CPU time 3 seconds
Started Mar 03 02:36:24 PM PST 24
Finished Mar 03 02:36:27 PM PST 24
Peak memory 208504 kb
Host smart-e6fceec3-dfbe-4d96-9a9a-4c81970c38bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3840410852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.3840410852
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.3380334886
Short name T250
Test name
Test status
Simulation time 84647435 ps
CPU time 3.51 seconds
Started Mar 03 02:36:22 PM PST 24
Finished Mar 03 02:36:26 PM PST 24
Peak memory 213872 kb
Host smart-2a13c52f-ca6f-4097-9945-82cd13480a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380334886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.3380334886
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.1639910729
Short name T717
Test name
Test status
Simulation time 187159996 ps
CPU time 2.91 seconds
Started Mar 03 02:36:22 PM PST 24
Finished Mar 03 02:36:25 PM PST 24
Peak memory 208264 kb
Host smart-f3ec8465-4788-49f7-ac11-9e1709963555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639910729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.1639910729
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.1272226529
Short name T664
Test name
Test status
Simulation time 173844038 ps
CPU time 2.6 seconds
Started Mar 03 02:36:22 PM PST 24
Finished Mar 03 02:36:25 PM PST 24
Peak memory 206380 kb
Host smart-8e7b201d-1f02-40da-b80c-e1b5dbe2ca0b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272226529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.1272226529
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.2554073099
Short name T878
Test name
Test status
Simulation time 497717554 ps
CPU time 3.75 seconds
Started Mar 03 02:36:20 PM PST 24
Finished Mar 03 02:36:24 PM PST 24
Peak memory 206900 kb
Host smart-b26f471e-d4cf-4aa6-ab38-21c5263e0189
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554073099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.2554073099
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.2549812612
Short name T754
Test name
Test status
Simulation time 119849819 ps
CPU time 3.28 seconds
Started Mar 03 02:36:22 PM PST 24
Finished Mar 03 02:36:26 PM PST 24
Peak memory 207900 kb
Host smart-ec200947-b023-47f4-8989-b6da3df9c9d6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549812612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.2549812612
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.4013974895
Short name T247
Test name
Test status
Simulation time 164723871 ps
CPU time 3.89 seconds
Started Mar 03 02:36:26 PM PST 24
Finished Mar 03 02:36:30 PM PST 24
Peak memory 213856 kb
Host smart-7696e6c9-e8f8-4f81-a9fc-1bb939ffe0e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013974895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.4013974895
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.1947670021
Short name T384
Test name
Test status
Simulation time 80846432 ps
CPU time 2.33 seconds
Started Mar 03 02:36:23 PM PST 24
Finished Mar 03 02:36:26 PM PST 24
Peak memory 206140 kb
Host smart-a4c31c4f-b616-4698-8dcd-89716190ae2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1947670021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.1947670021
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.27607368
Short name T706
Test name
Test status
Simulation time 205018150 ps
CPU time 5.2 seconds
Started Mar 03 02:36:27 PM PST 24
Finished Mar 03 02:36:33 PM PST 24
Peak memory 217960 kb
Host smart-8790129e-16f6-42de-aa65-50bc58fc8dcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27607368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.27607368
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.2453646942
Short name T821
Test name
Test status
Simulation time 17411863 ps
CPU time 0.82 seconds
Started Mar 03 02:36:30 PM PST 24
Finished Mar 03 02:36:32 PM PST 24
Peak memory 205484 kb
Host smart-c4c42913-13cc-45be-a238-8d83d73ff97d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453646942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.2453646942
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.1625073331
Short name T232
Test name
Test status
Simulation time 1369590802 ps
CPU time 19.18 seconds
Started Mar 03 02:36:26 PM PST 24
Finished Mar 03 02:36:46 PM PST 24
Peak memory 222016 kb
Host smart-2827d2f2-9e98-43f0-8967-1311f494eea1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1625073331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.1625073331
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.1903663444
Short name T205
Test name
Test status
Simulation time 96039417 ps
CPU time 4.17 seconds
Started Mar 03 02:36:25 PM PST 24
Finished Mar 03 02:36:30 PM PST 24
Peak memory 214088 kb
Host smart-e7e232d3-e57e-4b13-92be-4be7f8ec6282
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903663444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.1903663444
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.4273177043
Short name T472
Test name
Test status
Simulation time 196772002 ps
CPU time 2.31 seconds
Started Mar 03 02:36:26 PM PST 24
Finished Mar 03 02:36:29 PM PST 24
Peak memory 208856 kb
Host smart-c89804e3-ed90-4666-b0a0-e5fbe6b9b70b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273177043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.4273177043
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.2911686805
Short name T85
Test name
Test status
Simulation time 404745092 ps
CPU time 5.39 seconds
Started Mar 03 02:36:27 PM PST 24
Finished Mar 03 02:36:33 PM PST 24
Peak memory 208784 kb
Host smart-eab3b923-bced-4f78-900e-f936298f9a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911686805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.2911686805
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.3015521059
Short name T868
Test name
Test status
Simulation time 303923762 ps
CPU time 4.56 seconds
Started Mar 03 02:36:29 PM PST 24
Finished Mar 03 02:36:36 PM PST 24
Peak memory 219680 kb
Host smart-882e6715-1e01-498f-8d50-d56f9cc32664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3015521059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.3015521059
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.643061280
Short name T528
Test name
Test status
Simulation time 129049650 ps
CPU time 5.63 seconds
Started Mar 03 02:36:25 PM PST 24
Finished Mar 03 02:36:32 PM PST 24
Peak memory 217792 kb
Host smart-ff6c5e6d-5760-4382-937d-b007aa95e755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=643061280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.643061280
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.2601284234
Short name T314
Test name
Test status
Simulation time 57589385 ps
CPU time 2.76 seconds
Started Mar 03 02:36:26 PM PST 24
Finished Mar 03 02:36:29 PM PST 24
Peak memory 206172 kb
Host smart-8c101273-44bf-487e-a7af-a01905456662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601284234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.2601284234
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.3946376065
Short name T458
Test name
Test status
Simulation time 1642996398 ps
CPU time 11.54 seconds
Started Mar 03 02:36:29 PM PST 24
Finished Mar 03 02:36:42 PM PST 24
Peak memory 207400 kb
Host smart-409079d7-9ba5-4b7c-b339-eecde9f6c46e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946376065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.3946376065
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.548191765
Short name T426
Test name
Test status
Simulation time 452665473 ps
CPU time 4.99 seconds
Started Mar 03 02:36:27 PM PST 24
Finished Mar 03 02:36:33 PM PST 24
Peak memory 206244 kb
Host smart-35cef32d-d9c8-4e9a-b601-12a3390a4e96
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=548191765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.548191765
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.2133376598
Short name T418
Test name
Test status
Simulation time 107002347 ps
CPU time 4.71 seconds
Started Mar 03 02:36:31 PM PST 24
Finished Mar 03 02:36:36 PM PST 24
Peak memory 208320 kb
Host smart-1828b6d4-498d-4cdc-8180-747b299a3dcc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133376598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.2133376598
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.2141558301
Short name T503
Test name
Test status
Simulation time 672309016 ps
CPU time 2.79 seconds
Started Mar 03 02:36:28 PM PST 24
Finished Mar 03 02:36:31 PM PST 24
Peak memory 207072 kb
Host smart-d8c8fade-e164-43da-a004-9fbe60189cea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141558301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.2141558301
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.1425538621
Short name T467
Test name
Test status
Simulation time 143845738 ps
CPU time 3.06 seconds
Started Mar 03 02:36:27 PM PST 24
Finished Mar 03 02:36:31 PM PST 24
Peak memory 206464 kb
Host smart-764f77c0-9f51-462a-9e14-aa5e9037acd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425538621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.1425538621
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.4271946928
Short name T610
Test name
Test status
Simulation time 10309460369 ps
CPU time 23.75 seconds
Started Mar 03 02:36:30 PM PST 24
Finished Mar 03 02:36:55 PM PST 24
Peak memory 216016 kb
Host smart-ea581878-6f44-493e-8310-b417001c7046
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271946928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.4271946928
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_stress_all_with_rand_reset.1253696745
Short name T64
Test name
Test status
Simulation time 249026807 ps
CPU time 16.7 seconds
Started Mar 03 02:36:31 PM PST 24
Finished Mar 03 02:36:49 PM PST 24
Peak memory 220576 kb
Host smart-da0b7d9b-b6ac-4224-968f-2514e38cffbc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1253696745 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all_with_rand_reset.1253696745
Directory /workspace/44.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.774176934
Short name T620
Test name
Test status
Simulation time 821334135 ps
CPU time 15.25 seconds
Started Mar 03 02:36:24 PM PST 24
Finished Mar 03 02:36:40 PM PST 24
Peak memory 207496 kb
Host smart-7f55b41d-197a-4f1f-b25f-9573ad550a39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774176934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.774176934
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.770635551
Short name T583
Test name
Test status
Simulation time 130288860 ps
CPU time 3.44 seconds
Started Mar 03 02:36:30 PM PST 24
Finished Mar 03 02:36:34 PM PST 24
Peak memory 209716 kb
Host smart-7e7e0709-1396-4bf0-94be-9c4179470ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770635551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.770635551
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.2114591207
Short name T598
Test name
Test status
Simulation time 117011687 ps
CPU time 0.79 seconds
Started Mar 03 02:36:30 PM PST 24
Finished Mar 03 02:36:32 PM PST 24
Peak memory 205472 kb
Host smart-44186bcb-57ab-47c5-941d-5244c44189c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114591207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.2114591207
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.1248897691
Short name T413
Test name
Test status
Simulation time 304813305 ps
CPU time 4.08 seconds
Started Mar 03 02:36:25 PM PST 24
Finished Mar 03 02:36:29 PM PST 24
Peak memory 207688 kb
Host smart-99efbb20-7562-4592-a8d3-cc381a914f55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248897691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.1248897691
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.4268704986
Short name T786
Test name
Test status
Simulation time 6996440318 ps
CPU time 54.99 seconds
Started Mar 03 02:36:30 PM PST 24
Finished Mar 03 02:37:26 PM PST 24
Peak memory 221952 kb
Host smart-5de5833f-4272-4dad-8179-d7688e4de6f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268704986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.4268704986
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.3385089122
Short name T214
Test name
Test status
Simulation time 160045085 ps
CPU time 4.62 seconds
Started Mar 03 02:36:24 PM PST 24
Finished Mar 03 02:36:28 PM PST 24
Peak memory 219628 kb
Host smart-78c287ff-a7a6-4e84-ae88-de2147280dc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385089122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.3385089122
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.2539758824
Short name T741
Test name
Test status
Simulation time 46799596 ps
CPU time 3.19 seconds
Started Mar 03 02:36:25 PM PST 24
Finished Mar 03 02:36:29 PM PST 24
Peak memory 206488 kb
Host smart-245c90f8-d485-41d1-9b0c-2fd9739dea93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539758824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.2539758824
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.249795597
Short name T813
Test name
Test status
Simulation time 86062078 ps
CPU time 2.64 seconds
Started Mar 03 02:36:26 PM PST 24
Finished Mar 03 02:36:29 PM PST 24
Peak memory 206100 kb
Host smart-81093e2f-d23c-41be-8845-83c5673141da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249795597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.249795597
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.2843504282
Short name T832
Test name
Test status
Simulation time 152211596 ps
CPU time 2.99 seconds
Started Mar 03 02:36:32 PM PST 24
Finished Mar 03 02:36:35 PM PST 24
Peak memory 207604 kb
Host smart-1fee12e8-fe2b-4c71-8c58-620950398216
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2843504282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.2843504282
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.72978592
Short name T489
Test name
Test status
Simulation time 81742030 ps
CPU time 1.84 seconds
Started Mar 03 02:36:28 PM PST 24
Finished Mar 03 02:36:30 PM PST 24
Peak memory 206164 kb
Host smart-80d4fff2-cf6e-44f5-a15e-a8d1d5e881f3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72978592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.72978592
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.2005295402
Short name T179
Test name
Test status
Simulation time 136715302 ps
CPU time 4.31 seconds
Started Mar 03 02:36:25 PM PST 24
Finished Mar 03 02:36:29 PM PST 24
Peak memory 206400 kb
Host smart-b51ab0ed-ebda-4548-b696-8be783a2dc18
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005295402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.2005295402
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.2820799351
Short name T810
Test name
Test status
Simulation time 2100970891 ps
CPU time 11.81 seconds
Started Mar 03 02:36:30 PM PST 24
Finished Mar 03 02:36:43 PM PST 24
Peak memory 208848 kb
Host smart-30347dc8-122a-44e5-be67-ea79f770da35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2820799351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.2820799351
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.3189738432
Short name T549
Test name
Test status
Simulation time 620323831 ps
CPU time 6.87 seconds
Started Mar 03 02:36:29 PM PST 24
Finished Mar 03 02:36:37 PM PST 24
Peak memory 207908 kb
Host smart-13685dc0-bcd8-4cd0-818f-1884214afc01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189738432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.3189738432
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.2887366066
Short name T671
Test name
Test status
Simulation time 2152101917 ps
CPU time 26.97 seconds
Started Mar 03 02:36:30 PM PST 24
Finished Mar 03 02:36:58 PM PST 24
Peak memory 216608 kb
Host smart-e563b804-8fe5-4ae9-9249-ae969ae724d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2887366066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.2887366066
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_stress_all_with_rand_reset.1372202735
Short name T99
Test name
Test status
Simulation time 2646404403 ps
CPU time 12.68 seconds
Started Mar 03 02:36:27 PM PST 24
Finished Mar 03 02:36:41 PM PST 24
Peak memory 222080 kb
Host smart-35f717d2-1f81-42b2-9f01-93715560c130
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372202735 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all_with_rand_reset.1372202735
Directory /workspace/45.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.2261072052
Short name T698
Test name
Test status
Simulation time 283004300 ps
CPU time 7.77 seconds
Started Mar 03 02:36:31 PM PST 24
Finished Mar 03 02:36:40 PM PST 24
Peak memory 209188 kb
Host smart-4e3aec9f-bd17-41df-87f0-7d95dad4b3be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261072052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.2261072052
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.1476569241
Short name T825
Test name
Test status
Simulation time 30413280 ps
CPU time 1.5 seconds
Started Mar 03 02:36:29 PM PST 24
Finished Mar 03 02:36:32 PM PST 24
Peak memory 209612 kb
Host smart-3ea887fe-2546-46bc-8438-48429ee922ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476569241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.1476569241
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.4120161667
Short name T606
Test name
Test status
Simulation time 8065985 ps
CPU time 0.81 seconds
Started Mar 03 02:36:36 PM PST 24
Finished Mar 03 02:36:37 PM PST 24
Peak memory 205596 kb
Host smart-5325da02-91d1-47dc-a952-0404b31d4e0b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120161667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.4120161667
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.836490423
Short name T276
Test name
Test status
Simulation time 5248311641 ps
CPU time 15 seconds
Started Mar 03 02:36:32 PM PST 24
Finished Mar 03 02:36:47 PM PST 24
Peak memory 213936 kb
Host smart-57941260-2434-49ff-88f0-e9d177aeed3d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=836490423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.836490423
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.2685170156
Short name T26
Test name
Test status
Simulation time 233531980 ps
CPU time 6.12 seconds
Started Mar 03 02:36:32 PM PST 24
Finished Mar 03 02:36:39 PM PST 24
Peak memory 214076 kb
Host smart-b58279e0-f7dd-4832-9fdd-701cf2043d7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2685170156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.2685170156
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.23992210
Short name T855
Test name
Test status
Simulation time 1866166457 ps
CPU time 39.91 seconds
Started Mar 03 02:36:32 PM PST 24
Finished Mar 03 02:37:13 PM PST 24
Peak memory 208228 kb
Host smart-700b5de8-2310-4cc1-a4b4-ec45686f374b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23992210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.23992210
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.2615776236
Short name T612
Test name
Test status
Simulation time 351805562 ps
CPU time 4.36 seconds
Started Mar 03 02:36:34 PM PST 24
Finished Mar 03 02:36:39 PM PST 24
Peak memory 208672 kb
Host smart-5676e882-3d5e-4f13-8060-d2d03cad2b69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615776236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.2615776236
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.1401538068
Short name T90
Test name
Test status
Simulation time 3748339079 ps
CPU time 27.21 seconds
Started Mar 03 02:36:34 PM PST 24
Finished Mar 03 02:37:02 PM PST 24
Peak memory 222044 kb
Host smart-f34b91de-0c0b-4e49-8359-e83f25d55b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401538068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.1401538068
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.1842256450
Short name T4
Test name
Test status
Simulation time 565375726 ps
CPU time 3.13 seconds
Started Mar 03 02:36:32 PM PST 24
Finished Mar 03 02:36:36 PM PST 24
Peak memory 220180 kb
Host smart-d60562d5-963c-4c2f-8fe5-614a85e3b24c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1842256450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.1842256450
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.1721928938
Short name T497
Test name
Test status
Simulation time 89120402 ps
CPU time 4.51 seconds
Started Mar 03 02:36:32 PM PST 24
Finished Mar 03 02:36:37 PM PST 24
Peak memory 213860 kb
Host smart-32fbfc7e-9dce-4b8b-ab13-db2633a72bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721928938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.1721928938
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.1088478808
Short name T77
Test name
Test status
Simulation time 678810841 ps
CPU time 14.25 seconds
Started Mar 03 02:36:33 PM PST 24
Finished Mar 03 02:36:48 PM PST 24
Peak memory 207212 kb
Host smart-5ae1035a-b95a-4374-9b7e-c603dda890ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1088478808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.1088478808
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.3900849462
Short name T777
Test name
Test status
Simulation time 307682856 ps
CPU time 2.02 seconds
Started Mar 03 02:36:34 PM PST 24
Finished Mar 03 02:36:37 PM PST 24
Peak memory 206272 kb
Host smart-e7752bca-91b2-4870-806d-02593159e931
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3900849462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.3900849462
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.3469006230
Short name T288
Test name
Test status
Simulation time 182116746 ps
CPU time 2.26 seconds
Started Mar 03 02:36:35 PM PST 24
Finished Mar 03 02:36:38 PM PST 24
Peak memory 207996 kb
Host smart-63bc5a19-83fb-444a-b4b8-1e161ab476cd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3469006230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.3469006230
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.2686340447
Short name T781
Test name
Test status
Simulation time 26952911 ps
CPU time 2.13 seconds
Started Mar 03 02:36:36 PM PST 24
Finished Mar 03 02:36:38 PM PST 24
Peak memory 209760 kb
Host smart-05696bb0-4c04-4e97-8d59-2da45bd3a541
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2686340447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.2686340447
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.1859573450
Short name T539
Test name
Test status
Simulation time 885758996 ps
CPU time 19.88 seconds
Started Mar 03 02:36:32 PM PST 24
Finished Mar 03 02:36:53 PM PST 24
Peak memory 207476 kb
Host smart-b5cf8c3b-ee3d-495c-8fe8-a2cedabc1a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1859573450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.1859573450
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.1400566766
Short name T184
Test name
Test status
Simulation time 1591855601 ps
CPU time 31.78 seconds
Started Mar 03 02:36:33 PM PST 24
Finished Mar 03 02:37:05 PM PST 24
Peak memory 221996 kb
Host smart-f81d22af-bd0f-466e-9d45-f17ef22121df
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400566766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.1400566766
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.433454449
Short name T749
Test name
Test status
Simulation time 1766355917 ps
CPU time 8.74 seconds
Started Mar 03 02:36:33 PM PST 24
Finished Mar 03 02:36:42 PM PST 24
Peak memory 207944 kb
Host smart-5b9712db-bcd7-488d-b786-e7209c851c93
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=433454449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.433454449
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.2099225819
Short name T145
Test name
Test status
Simulation time 270683208 ps
CPU time 1.79 seconds
Started Mar 03 02:36:33 PM PST 24
Finished Mar 03 02:36:35 PM PST 24
Peak memory 209436 kb
Host smart-325d0ac6-d7de-4535-a71e-90a5f2fe3315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099225819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.2099225819
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.3251415564
Short name T736
Test name
Test status
Simulation time 98560299 ps
CPU time 0.75 seconds
Started Mar 03 02:36:43 PM PST 24
Finished Mar 03 02:36:44 PM PST 24
Peak memory 205524 kb
Host smart-111a3a1c-b8b1-4597-aaf6-1733db70708e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251415564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.3251415564
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.3792154226
Short name T403
Test name
Test status
Simulation time 128665174 ps
CPU time 4.88 seconds
Started Mar 03 02:36:32 PM PST 24
Finished Mar 03 02:36:38 PM PST 24
Peak memory 215028 kb
Host smart-7f01fd91-fa88-4f30-a6a0-99b9f8160e4f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3792154226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.3792154226
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.3148751716
Short name T164
Test name
Test status
Simulation time 130003342 ps
CPU time 7.06 seconds
Started Mar 03 02:36:42 PM PST 24
Finished Mar 03 02:36:51 PM PST 24
Peak memory 222088 kb
Host smart-57fbedb9-79ea-438b-ba2a-e4a2e5913b63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3148751716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.3148751716
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.2811086613
Short name T67
Test name
Test status
Simulation time 43602323 ps
CPU time 1.91 seconds
Started Mar 03 02:36:32 PM PST 24
Finished Mar 03 02:36:35 PM PST 24
Peak memory 207332 kb
Host smart-53ab6a8d-9916-46a0-9ea4-ab72b69e32cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811086613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.2811086613
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.3096670400
Short name T88
Test name
Test status
Simulation time 99951260 ps
CPU time 3.06 seconds
Started Mar 03 02:36:42 PM PST 24
Finished Mar 03 02:36:47 PM PST 24
Peak memory 208212 kb
Host smart-472d660a-d9aa-481d-91eb-ee95b4c3e580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096670400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.3096670400
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.4097487834
Short name T240
Test name
Test status
Simulation time 960699971 ps
CPU time 8.05 seconds
Started Mar 03 02:36:40 PM PST 24
Finished Mar 03 02:36:49 PM PST 24
Peak memory 221984 kb
Host smart-453e5436-c787-4f8a-8465-eb14dfa2fd02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4097487834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.4097487834
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.1089159883
Short name T49
Test name
Test status
Simulation time 213761461 ps
CPU time 3.5 seconds
Started Mar 03 02:36:34 PM PST 24
Finished Mar 03 02:36:39 PM PST 24
Peak memory 209284 kb
Host smart-cb1eab96-8678-42c8-acd9-615e5b8171ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089159883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.1089159883
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.853216640
Short name T241
Test name
Test status
Simulation time 358616565 ps
CPU time 5.44 seconds
Started Mar 03 02:36:34 PM PST 24
Finished Mar 03 02:36:40 PM PST 24
Peak memory 213808 kb
Host smart-1f84f4da-f79d-4592-9de1-15b70cd472e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853216640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.853216640
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.3274794946
Short name T309
Test name
Test status
Simulation time 275783657 ps
CPU time 4.48 seconds
Started Mar 03 02:36:32 PM PST 24
Finished Mar 03 02:36:37 PM PST 24
Peak memory 207980 kb
Host smart-8eee81f3-3f87-473d-88f9-9098c00b2634
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3274794946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.3274794946
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.442180343
Short name T336
Test name
Test status
Simulation time 256835268 ps
CPU time 7.68 seconds
Started Mar 03 02:36:32 PM PST 24
Finished Mar 03 02:36:40 PM PST 24
Peak memory 207076 kb
Host smart-13377464-4303-4d1d-b713-9e57c0c207ff
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=442180343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.442180343
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.3563073178
Short name T278
Test name
Test status
Simulation time 27110522603 ps
CPU time 65.57 seconds
Started Mar 03 02:36:33 PM PST 24
Finished Mar 03 02:37:40 PM PST 24
Peak memory 207316 kb
Host smart-9b652aec-367c-46a3-bcc7-3241e7056b85
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563073178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.3563073178
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.1541245968
Short name T264
Test name
Test status
Simulation time 779947207 ps
CPU time 7.18 seconds
Started Mar 03 02:36:33 PM PST 24
Finished Mar 03 02:36:41 PM PST 24
Peak memory 208060 kb
Host smart-a5794eb1-580b-46db-a061-a5d3d87d15fd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1541245968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.1541245968
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.3310599792
Short name T440
Test name
Test status
Simulation time 210567076 ps
CPU time 4.45 seconds
Started Mar 03 02:36:42 PM PST 24
Finished Mar 03 02:36:48 PM PST 24
Peak memory 213872 kb
Host smart-5e30310c-427f-45d1-b829-a04802c4cd22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310599792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.3310599792
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.3588015758
Short name T410
Test name
Test status
Simulation time 59098419 ps
CPU time 2.8 seconds
Started Mar 03 02:36:34 PM PST 24
Finished Mar 03 02:36:38 PM PST 24
Peak memory 207604 kb
Host smart-fbb31d6b-79a2-4ccc-99aa-a9f5eb426278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588015758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.3588015758
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.161773413
Short name T304
Test name
Test status
Simulation time 1396909760 ps
CPU time 15.1 seconds
Started Mar 03 02:36:41 PM PST 24
Finished Mar 03 02:36:58 PM PST 24
Peak memory 221512 kb
Host smart-bcac9d90-1b36-49a2-8ae3-37f06b745695
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161773413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.161773413
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.2052210684
Short name T193
Test name
Test status
Simulation time 391147780 ps
CPU time 9.79 seconds
Started Mar 03 02:36:41 PM PST 24
Finished Mar 03 02:36:53 PM PST 24
Peak memory 207536 kb
Host smart-bc817112-a03c-4d86-b682-6ca787617528
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052210684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.2052210684
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.1922958535
Short name T373
Test name
Test status
Simulation time 912687289 ps
CPU time 8.1 seconds
Started Mar 03 02:36:41 PM PST 24
Finished Mar 03 02:36:51 PM PST 24
Peak memory 210340 kb
Host smart-06f3ba4e-75f8-43ef-a131-6d848ff476f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922958535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.1922958535
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.2623016639
Short name T447
Test name
Test status
Simulation time 73013548 ps
CPU time 0.74 seconds
Started Mar 03 02:36:42 PM PST 24
Finished Mar 03 02:36:44 PM PST 24
Peak memory 205616 kb
Host smart-9b64b67a-4058-4d0e-8bad-4ad7b39b65a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623016639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.2623016639
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.956334988
Short name T366
Test name
Test status
Simulation time 108476824 ps
CPU time 4.19 seconds
Started Mar 03 02:36:42 PM PST 24
Finished Mar 03 02:36:48 PM PST 24
Peak memory 213984 kb
Host smart-939db0e3-b6ad-4d48-b5c7-e14da4f652d3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=956334988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.956334988
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.2310145421
Short name T723
Test name
Test status
Simulation time 21584492 ps
CPU time 1.81 seconds
Started Mar 03 02:36:43 PM PST 24
Finished Mar 03 02:36:45 PM PST 24
Peak memory 206592 kb
Host smart-a1cfdfd5-ec23-42ba-acbe-4b6b658920d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310145421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.2310145421
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.728195187
Short name T774
Test name
Test status
Simulation time 1432132806 ps
CPU time 7.84 seconds
Started Mar 03 02:36:41 PM PST 24
Finished Mar 03 02:36:49 PM PST 24
Peak memory 218644 kb
Host smart-11d84ca6-a06f-45ed-950f-39400db44540
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728195187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.728195187
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.2775995643
Short name T258
Test name
Test status
Simulation time 1539895854 ps
CPU time 9.24 seconds
Started Mar 03 02:36:42 PM PST 24
Finished Mar 03 02:36:53 PM PST 24
Peak memory 210084 kb
Host smart-4a1203c4-9a83-4aec-bb45-3b7b732c8cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775995643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.2775995643
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.1030177769
Short name T283
Test name
Test status
Simulation time 731713330 ps
CPU time 5.09 seconds
Started Mar 03 02:36:46 PM PST 24
Finished Mar 03 02:36:51 PM PST 24
Peak memory 215088 kb
Host smart-1df45669-eda6-4340-b5f4-ece22f1b98b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1030177769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.1030177769
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.3311530813
Short name T316
Test name
Test status
Simulation time 510114284 ps
CPU time 11.06 seconds
Started Mar 03 02:36:48 PM PST 24
Finished Mar 03 02:37:00 PM PST 24
Peak memory 208604 kb
Host smart-9375b951-3a26-48b3-8fba-6efb59a1c6c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311530813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.3311530813
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.3006551911
Short name T452
Test name
Test status
Simulation time 1392882939 ps
CPU time 8.56 seconds
Started Mar 03 02:36:40 PM PST 24
Finished Mar 03 02:36:49 PM PST 24
Peak memory 207456 kb
Host smart-9d6eab6c-5ea0-46a9-91d4-beb1820f0cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006551911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.3006551911
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.2346004584
Short name T360
Test name
Test status
Simulation time 39144722 ps
CPU time 2.39 seconds
Started Mar 03 02:36:42 PM PST 24
Finished Mar 03 02:36:46 PM PST 24
Peak memory 206192 kb
Host smart-d4a55348-4e07-4462-ad15-1e6ed156e3f3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346004584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.2346004584
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.2178818935
Short name T669
Test name
Test status
Simulation time 656974056 ps
CPU time 5.18 seconds
Started Mar 03 02:36:42 PM PST 24
Finished Mar 03 02:36:49 PM PST 24
Peak memory 207788 kb
Host smart-31daf826-4bc9-481e-8580-a03af882554d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178818935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.2178818935
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.3046754713
Short name T505
Test name
Test status
Simulation time 289129096 ps
CPU time 2.75 seconds
Started Mar 03 02:36:42 PM PST 24
Finished Mar 03 02:36:46 PM PST 24
Peak memory 206228 kb
Host smart-3474c5e1-ba30-4541-8ac5-d9a5f86f9306
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046754713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.3046754713
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.952048929
Short name T655
Test name
Test status
Simulation time 826969653 ps
CPU time 11.49 seconds
Started Mar 03 02:36:40 PM PST 24
Finished Mar 03 02:36:52 PM PST 24
Peak memory 209304 kb
Host smart-5f693343-6221-4975-b6c2-1844c04f9ee6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952048929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.952048929
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.2191734822
Short name T900
Test name
Test status
Simulation time 281657599 ps
CPU time 3.28 seconds
Started Mar 03 02:36:42 PM PST 24
Finished Mar 03 02:36:47 PM PST 24
Peak memory 207740 kb
Host smart-71b290ec-aa20-4369-bef2-ad60314d6240
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2191734822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.2191734822
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.3393584172
Short name T273
Test name
Test status
Simulation time 6877818319 ps
CPU time 17.22 seconds
Started Mar 03 02:36:48 PM PST 24
Finished Mar 03 02:37:05 PM PST 24
Peak memory 215784 kb
Host smart-c05288d2-27bc-4971-a355-31ae54bc1820
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393584172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.3393584172
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.1652565452
Short name T571
Test name
Test status
Simulation time 174459295 ps
CPU time 6.17 seconds
Started Mar 03 02:36:46 PM PST 24
Finished Mar 03 02:36:53 PM PST 24
Peak memory 221932 kb
Host smart-a24c5886-ca8e-4e0f-96b3-2caff4a94e82
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652565452 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.1652565452
Directory /workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.2927364676
Short name T330
Test name
Test status
Simulation time 492910474 ps
CPU time 5.07 seconds
Started Mar 03 02:36:42 PM PST 24
Finished Mar 03 02:36:49 PM PST 24
Peak memory 213868 kb
Host smart-8bf55b49-102e-4427-96e3-5f1c9db1ca3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927364676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.2927364676
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.2406974858
Short name T459
Test name
Test status
Simulation time 526445402 ps
CPU time 10.57 seconds
Started Mar 03 02:36:48 PM PST 24
Finished Mar 03 02:36:59 PM PST 24
Peak memory 210204 kb
Host smart-b561e2db-6ca1-4506-b55b-980977db1313
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2406974858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.2406974858
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.3429413414
Short name T437
Test name
Test status
Simulation time 9744868 ps
CPU time 0.86 seconds
Started Mar 03 02:36:46 PM PST 24
Finished Mar 03 02:36:47 PM PST 24
Peak memory 205532 kb
Host smart-a69c4b25-a6d2-4636-b0c7-27b8451fbc1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3429413414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.3429413414
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.2951964379
Short name T268
Test name
Test status
Simulation time 219252312 ps
CPU time 4.36 seconds
Started Mar 03 02:36:42 PM PST 24
Finished Mar 03 02:36:48 PM PST 24
Peak memory 222036 kb
Host smart-9ee2cbca-1d58-4efe-859d-e3ed39661dfd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2951964379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.2951964379
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.2910393090
Short name T554
Test name
Test status
Simulation time 2829014609 ps
CPU time 20.14 seconds
Started Mar 03 02:36:43 PM PST 24
Finished Mar 03 02:37:04 PM PST 24
Peak memory 208484 kb
Host smart-1ada2917-2792-40b0-bc2d-a0155edc3817
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910393090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.2910393090
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.437195913
Short name T200
Test name
Test status
Simulation time 117195448 ps
CPU time 3.37 seconds
Started Mar 03 02:36:43 PM PST 24
Finished Mar 03 02:36:47 PM PST 24
Peak memory 207748 kb
Host smart-7f574551-6de8-4335-87fd-1f3c847b4209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437195913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.437195913
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.1083228351
Short name T356
Test name
Test status
Simulation time 2958028522 ps
CPU time 10.17 seconds
Started Mar 03 02:36:42 PM PST 24
Finished Mar 03 02:36:54 PM PST 24
Peak memory 213928 kb
Host smart-19012880-0a00-40c5-84b3-f32ce64af1d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083228351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.1083228351
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.1445692162
Short name T299
Test name
Test status
Simulation time 773159568 ps
CPU time 21.62 seconds
Started Mar 03 02:36:46 PM PST 24
Finished Mar 03 02:37:08 PM PST 24
Peak memory 221960 kb
Host smart-03951615-cf8d-499d-a44c-0fa43dae5385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445692162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.1445692162
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.4144453493
Short name T724
Test name
Test status
Simulation time 435282914 ps
CPU time 2.43 seconds
Started Mar 03 02:36:42 PM PST 24
Finished Mar 03 02:36:46 PM PST 24
Peak memory 214888 kb
Host smart-3301508d-eb63-49b7-882d-978eb8504c79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144453493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.4144453493
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.2693894950
Short name T649
Test name
Test status
Simulation time 237251162 ps
CPU time 6.71 seconds
Started Mar 03 02:36:44 PM PST 24
Finished Mar 03 02:36:51 PM PST 24
Peak memory 208572 kb
Host smart-6fb6fc85-8f23-40e9-b528-c2c5807789e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2693894950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.2693894950
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.3268973860
Short name T364
Test name
Test status
Simulation time 3371383315 ps
CPU time 32.96 seconds
Started Mar 03 02:36:43 PM PST 24
Finished Mar 03 02:37:17 PM PST 24
Peak memory 207752 kb
Host smart-6ce6805c-bec2-456e-a954-f29099a88dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3268973860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.3268973860
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.2198254835
Short name T580
Test name
Test status
Simulation time 169305618 ps
CPU time 2.94 seconds
Started Mar 03 02:36:42 PM PST 24
Finished Mar 03 02:36:46 PM PST 24
Peak memory 208048 kb
Host smart-213a3e88-71a3-49e5-b57e-5fc5dded8dad
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198254835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.2198254835
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.782294488
Short name T589
Test name
Test status
Simulation time 95103382 ps
CPU time 4.27 seconds
Started Mar 03 02:36:41 PM PST 24
Finished Mar 03 02:36:47 PM PST 24
Peak memory 208292 kb
Host smart-7aa37518-031d-4a66-abd7-90a5fd746fe6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782294488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.782294488
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.53351631
Short name T535
Test name
Test status
Simulation time 794238556 ps
CPU time 5.31 seconds
Started Mar 03 02:36:42 PM PST 24
Finished Mar 03 02:36:49 PM PST 24
Peak memory 206164 kb
Host smart-1dc2a341-5a28-4dc1-ba98-c6850f10d76c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53351631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.53351631
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.1954066544
Short name T417
Test name
Test status
Simulation time 310015727 ps
CPU time 3.61 seconds
Started Mar 03 02:36:46 PM PST 24
Finished Mar 03 02:36:50 PM PST 24
Peak memory 214452 kb
Host smart-2ff35d82-b7d8-42ca-862b-34a89b6cf932
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954066544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.1954066544
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.1806613127
Short name T739
Test name
Test status
Simulation time 28275888 ps
CPU time 2.05 seconds
Started Mar 03 02:36:41 PM PST 24
Finished Mar 03 02:36:43 PM PST 24
Peak memory 207740 kb
Host smart-6222aabd-b38a-4544-830e-f63f22ae3b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806613127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.1806613127
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.3106944165
Short name T513
Test name
Test status
Simulation time 28998738 ps
CPU time 0.75 seconds
Started Mar 03 02:36:42 PM PST 24
Finished Mar 03 02:36:44 PM PST 24
Peak memory 205392 kb
Host smart-79488728-5084-4099-91ec-8d892472838f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106944165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.3106944165
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.2851413065
Short name T568
Test name
Test status
Simulation time 128745427 ps
CPU time 2.76 seconds
Started Mar 03 02:36:42 PM PST 24
Finished Mar 03 02:36:46 PM PST 24
Peak memory 206260 kb
Host smart-afa0c9b6-a0b1-45fa-92b3-e1af6e3e3984
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851413065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.2851413065
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.4201076425
Short name T762
Test name
Test status
Simulation time 147643962 ps
CPU time 2.54 seconds
Started Mar 03 02:36:43 PM PST 24
Finished Mar 03 02:36:46 PM PST 24
Peak memory 209280 kb
Host smart-7dd9aa7a-5d15-436c-acb4-f41eb88dbc05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4201076425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.4201076425
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.3137304814
Short name T420
Test name
Test status
Simulation time 29050993 ps
CPU time 0.76 seconds
Started Mar 03 02:34:05 PM PST 24
Finished Mar 03 02:34:07 PM PST 24
Peak memory 205552 kb
Host smart-23e1fb7e-bc9a-47d3-9249-938ecfd6653d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137304814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.3137304814
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.258061456
Short name T876
Test name
Test status
Simulation time 106770804 ps
CPU time 2.21 seconds
Started Mar 03 02:33:57 PM PST 24
Finished Mar 03 02:33:59 PM PST 24
Peak memory 207512 kb
Host smart-a89d3336-1e85-4d78-ba8a-7ec6f0061b41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258061456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.258061456
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.1325447262
Short name T331
Test name
Test status
Simulation time 370058348 ps
CPU time 8.38 seconds
Started Mar 03 02:33:58 PM PST 24
Finished Mar 03 02:34:06 PM PST 24
Peak memory 213804 kb
Host smart-f199ea76-f465-4e16-a6cd-cb8dc40ba0ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325447262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.1325447262
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.4279154201
Short name T353
Test name
Test status
Simulation time 511433251 ps
CPU time 6.21 seconds
Started Mar 03 02:33:58 PM PST 24
Finished Mar 03 02:34:04 PM PST 24
Peak memory 222024 kb
Host smart-be922aeb-521a-4521-ae07-65666caec191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279154201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.4279154201
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.3413032320
Short name T733
Test name
Test status
Simulation time 76821315 ps
CPU time 3.45 seconds
Started Mar 03 02:33:58 PM PST 24
Finished Mar 03 02:34:02 PM PST 24
Peak memory 209224 kb
Host smart-2ca7c351-e1c4-4ee7-a7d5-db879eb2255c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3413032320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.3413032320
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.3670811234
Short name T267
Test name
Test status
Simulation time 426955539 ps
CPU time 9.47 seconds
Started Mar 03 02:33:57 PM PST 24
Finished Mar 03 02:34:07 PM PST 24
Peak memory 208680 kb
Host smart-5ed2e834-4f47-40aa-a42f-25a092842c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670811234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.3670811234
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.4270188197
Short name T450
Test name
Test status
Simulation time 401195986 ps
CPU time 4.42 seconds
Started Mar 03 02:33:56 PM PST 24
Finished Mar 03 02:34:01 PM PST 24
Peak memory 206644 kb
Host smart-35439ab3-8c95-4e84-a4b0-999498ff2b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270188197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.4270188197
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.3756715696
Short name T849
Test name
Test status
Simulation time 307286197 ps
CPU time 3.75 seconds
Started Mar 03 02:33:58 PM PST 24
Finished Mar 03 02:34:02 PM PST 24
Peak memory 208280 kb
Host smart-bd759ccd-2414-4016-9e32-0b3ced2bc4c1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756715696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.3756715696
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.2839822163
Short name T624
Test name
Test status
Simulation time 830211574 ps
CPU time 6.3 seconds
Started Mar 03 02:33:58 PM PST 24
Finished Mar 03 02:34:05 PM PST 24
Peak memory 208048 kb
Host smart-a39ea752-69e1-4c98-b78d-6d8ea060d7df
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839822163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.2839822163
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.2145598157
Short name T559
Test name
Test status
Simulation time 175779903 ps
CPU time 5.68 seconds
Started Mar 03 02:33:57 PM PST 24
Finished Mar 03 02:34:03 PM PST 24
Peak memory 207732 kb
Host smart-02518673-4e2b-4067-b76d-74d1b987eecc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145598157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.2145598157
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.2415348746
Short name T738
Test name
Test status
Simulation time 65933713 ps
CPU time 2.06 seconds
Started Mar 03 02:34:03 PM PST 24
Finished Mar 03 02:34:05 PM PST 24
Peak memory 207356 kb
Host smart-4c070539-0bae-45e2-b1af-ebee3a5f5c63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2415348746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.2415348746
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.1026937128
Short name T579
Test name
Test status
Simulation time 55574760 ps
CPU time 2.91 seconds
Started Mar 03 02:33:58 PM PST 24
Finished Mar 03 02:34:01 PM PST 24
Peak memory 205980 kb
Host smart-b4d45240-57ba-4942-96c4-fad62d64b9f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026937128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.1026937128
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.3369126283
Short name T737
Test name
Test status
Simulation time 5603772555 ps
CPU time 67.36 seconds
Started Mar 03 02:34:03 PM PST 24
Finished Mar 03 02:35:10 PM PST 24
Peak memory 216004 kb
Host smart-7767f3f0-7d47-4ad2-b267-13639494a3cb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3369126283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.3369126283
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.1752535069
Short name T313
Test name
Test status
Simulation time 200108375 ps
CPU time 6.17 seconds
Started Mar 03 02:33:58 PM PST 24
Finished Mar 03 02:34:04 PM PST 24
Peak memory 207312 kb
Host smart-4ce647d3-1280-40c9-b6c1-6d598253c55c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1752535069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.1752535069
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.1866311045
Short name T536
Test name
Test status
Simulation time 279273154 ps
CPU time 3.14 seconds
Started Mar 03 02:34:06 PM PST 24
Finished Mar 03 02:34:09 PM PST 24
Peak memory 209696 kb
Host smart-492a8e0b-aa9f-49c4-a6f1-a5bdb75a1053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866311045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.1866311045
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.2027047683
Short name T735
Test name
Test status
Simulation time 15477099 ps
CPU time 0.77 seconds
Started Mar 03 02:34:13 PM PST 24
Finished Mar 03 02:34:14 PM PST 24
Peak memory 205552 kb
Host smart-cd850154-7a29-45ee-8fa6-4be24959b663
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027047683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.2027047683
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.2307154544
Short name T847
Test name
Test status
Simulation time 60021887 ps
CPU time 2.18 seconds
Started Mar 03 02:34:03 PM PST 24
Finished Mar 03 02:34:06 PM PST 24
Peak memory 208116 kb
Host smart-3e2ed47f-7729-41fc-b776-fad670e5671e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2307154544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.2307154544
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.2300118298
Short name T895
Test name
Test status
Simulation time 382319365 ps
CPU time 4.67 seconds
Started Mar 03 02:34:06 PM PST 24
Finished Mar 03 02:34:11 PM PST 24
Peak memory 209288 kb
Host smart-cd4a752a-75b5-425c-9ece-0c60d773d765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300118298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.2300118298
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.2155467820
Short name T245
Test name
Test status
Simulation time 198364951 ps
CPU time 4.88 seconds
Started Mar 03 02:34:05 PM PST 24
Finished Mar 03 02:34:11 PM PST 24
Peak memory 213852 kb
Host smart-729364fc-a16a-4c04-91c9-3b9acd12a2cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155467820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.2155467820
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.3188696004
Short name T729
Test name
Test status
Simulation time 258195003 ps
CPU time 5.42 seconds
Started Mar 03 02:34:06 PM PST 24
Finished Mar 03 02:34:12 PM PST 24
Peak memory 213676 kb
Host smart-d4fb464d-3193-4f67-ad8a-b811a0c29098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188696004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.3188696004
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_random.3231740748
Short name T308
Test name
Test status
Simulation time 304187789 ps
CPU time 6.21 seconds
Started Mar 03 02:34:03 PM PST 24
Finished Mar 03 02:34:09 PM PST 24
Peak memory 213892 kb
Host smart-90d90c2e-c2d0-461a-a435-8a65e945b6eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3231740748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.3231740748
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.3018332207
Short name T682
Test name
Test status
Simulation time 1278786619 ps
CPU time 5.95 seconds
Started Mar 03 02:34:09 PM PST 24
Finished Mar 03 02:34:15 PM PST 24
Peak memory 206516 kb
Host smart-9758e8d4-4f5a-43c4-bb9c-8d5359e7ace6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018332207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.3018332207
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.3126580327
Short name T560
Test name
Test status
Simulation time 134814087 ps
CPU time 3.5 seconds
Started Mar 03 02:34:04 PM PST 24
Finished Mar 03 02:34:08 PM PST 24
Peak memory 208112 kb
Host smart-53149432-7680-4e4c-8c02-51112deba820
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126580327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.3126580327
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.2200363098
Short name T792
Test name
Test status
Simulation time 213434537 ps
CPU time 2.85 seconds
Started Mar 03 02:34:04 PM PST 24
Finished Mar 03 02:34:09 PM PST 24
Peak memory 206180 kb
Host smart-13e4daf0-2574-4e28-870d-634d9288ec1b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2200363098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.2200363098
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.4113914724
Short name T121
Test name
Test status
Simulation time 390127377 ps
CPU time 7.68 seconds
Started Mar 03 02:34:08 PM PST 24
Finished Mar 03 02:34:16 PM PST 24
Peak memory 206044 kb
Host smart-d44441c9-d291-4901-b185-7ab190be8ba5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113914724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.4113914724
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.2704763055
Short name T665
Test name
Test status
Simulation time 227621849 ps
CPU time 2.95 seconds
Started Mar 03 02:34:04 PM PST 24
Finished Mar 03 02:34:09 PM PST 24
Peak memory 209440 kb
Host smart-c418fa36-deaf-4fbe-ae23-f396cc11270e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704763055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.2704763055
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.3416809615
Short name T511
Test name
Test status
Simulation time 71874027 ps
CPU time 2.57 seconds
Started Mar 03 02:34:04 PM PST 24
Finished Mar 03 02:34:09 PM PST 24
Peak memory 207960 kb
Host smart-57ec527f-c54f-4916-af1f-e6eac5bceed6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416809615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.3416809615
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.3849876524
Short name T518
Test name
Test status
Simulation time 226933328 ps
CPU time 3.45 seconds
Started Mar 03 02:34:05 PM PST 24
Finished Mar 03 02:34:10 PM PST 24
Peak memory 206740 kb
Host smart-ea508239-cec9-4a4d-8e99-581d98c25e2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849876524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.3849876524
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.3936782571
Short name T118
Test name
Test status
Simulation time 403582109 ps
CPU time 3.02 seconds
Started Mar 03 02:34:07 PM PST 24
Finished Mar 03 02:34:10 PM PST 24
Peak memory 209332 kb
Host smart-67dacce0-f9e4-4925-a440-8eea89850e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936782571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.3936782571
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.286499741
Short name T488
Test name
Test status
Simulation time 57040012 ps
CPU time 0.94 seconds
Started Mar 03 02:34:16 PM PST 24
Finished Mar 03 02:34:17 PM PST 24
Peak memory 205648 kb
Host smart-855b87f1-f3e6-4566-b522-c6523297bdd6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286499741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.286499741
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.1305585597
Short name T326
Test name
Test status
Simulation time 35789695 ps
CPU time 2.76 seconds
Started Mar 03 02:34:11 PM PST 24
Finished Mar 03 02:34:14 PM PST 24
Peak memory 213860 kb
Host smart-66f59061-4812-4754-9dca-9486d788f070
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1305585597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.1305585597
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.2861304207
Short name T771
Test name
Test status
Simulation time 5910610038 ps
CPU time 18.72 seconds
Started Mar 03 02:34:11 PM PST 24
Finished Mar 03 02:34:29 PM PST 24
Peak memory 217132 kb
Host smart-d5da1486-e0d0-4149-8c2a-b0771d2d0dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2861304207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.2861304207
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.533200463
Short name T496
Test name
Test status
Simulation time 176889694 ps
CPU time 3.73 seconds
Started Mar 03 02:34:09 PM PST 24
Finished Mar 03 02:34:13 PM PST 24
Peak memory 207924 kb
Host smart-4a4a6117-9249-4d86-8612-fc150f92d1ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=533200463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.533200463
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.2096641217
Short name T880
Test name
Test status
Simulation time 217065750 ps
CPU time 6.15 seconds
Started Mar 03 02:34:11 PM PST 24
Finished Mar 03 02:34:18 PM PST 24
Peak memory 207788 kb
Host smart-b811d0f9-4ea5-4868-88d7-475a0c99aff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2096641217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.2096641217
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.627181373
Short name T354
Test name
Test status
Simulation time 96538456 ps
CPU time 2.45 seconds
Started Mar 03 02:34:12 PM PST 24
Finished Mar 03 02:34:14 PM PST 24
Peak memory 208460 kb
Host smart-8b6cdb80-877a-4efa-a2fd-6652d6c9f90c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627181373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.627181373
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.2488825719
Short name T678
Test name
Test status
Simulation time 105372113 ps
CPU time 4.67 seconds
Started Mar 03 02:34:10 PM PST 24
Finished Mar 03 02:34:15 PM PST 24
Peak memory 209400 kb
Host smart-47be3f4a-6fad-46df-b3a9-601cec1e24f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488825719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.2488825719
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.1402668721
Short name T779
Test name
Test status
Simulation time 119309284 ps
CPU time 5.29 seconds
Started Mar 03 02:34:12 PM PST 24
Finished Mar 03 02:34:17 PM PST 24
Peak memory 213884 kb
Host smart-37ae7b00-a79f-4192-b76e-5b9286ac11cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402668721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.1402668721
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.1733468060
Short name T870
Test name
Test status
Simulation time 57620623 ps
CPU time 2.83 seconds
Started Mar 03 02:34:09 PM PST 24
Finished Mar 03 02:34:12 PM PST 24
Peak memory 206216 kb
Host smart-3f190e03-d7ee-4990-8249-fbfb9e34d9b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733468060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.1733468060
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.1048782365
Short name T307
Test name
Test status
Simulation time 66894794 ps
CPU time 3.24 seconds
Started Mar 03 02:34:09 PM PST 24
Finished Mar 03 02:34:13 PM PST 24
Peak memory 208196 kb
Host smart-d256ffe4-aed4-4b90-be6f-8c0f6363ffaf
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048782365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.1048782365
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.3984508383
Short name T641
Test name
Test status
Simulation time 230473975 ps
CPU time 3.18 seconds
Started Mar 03 02:34:13 PM PST 24
Finished Mar 03 02:34:17 PM PST 24
Peak memory 207296 kb
Host smart-63eb42cb-8265-4b60-b458-56d4d0527c56
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984508383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.3984508383
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.2165414948
Short name T803
Test name
Test status
Simulation time 135653808 ps
CPU time 2.68 seconds
Started Mar 03 02:34:09 PM PST 24
Finished Mar 03 02:34:12 PM PST 24
Peak memory 208024 kb
Host smart-071cfaba-0a59-4dba-9484-6cb5b0fdc53a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165414948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.2165414948
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.3076971276
Short name T768
Test name
Test status
Simulation time 233206743 ps
CPU time 2.91 seconds
Started Mar 03 02:34:10 PM PST 24
Finished Mar 03 02:34:13 PM PST 24
Peak memory 213808 kb
Host smart-d8eb5d9b-44fd-4713-8892-aa3071a23708
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076971276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.3076971276
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.1361696128
Short name T860
Test name
Test status
Simulation time 98905058 ps
CPU time 4.09 seconds
Started Mar 03 02:34:10 PM PST 24
Finished Mar 03 02:34:14 PM PST 24
Peak memory 208428 kb
Host smart-db3f7089-070c-4dd8-a599-22eb1d95d963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361696128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.1361696128
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.2172226597
Short name T591
Test name
Test status
Simulation time 1299296268 ps
CPU time 33 seconds
Started Mar 03 02:34:10 PM PST 24
Finished Mar 03 02:34:43 PM PST 24
Peak memory 218812 kb
Host smart-69bb5251-d0c9-477c-8a69-b4bda15477a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2172226597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.2172226597
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_stress_all_with_rand_reset.1719960682
Short name T113
Test name
Test status
Simulation time 2268892087 ps
CPU time 12.9 seconds
Started Mar 03 02:34:16 PM PST 24
Finished Mar 03 02:34:29 PM PST 24
Peak memory 222260 kb
Host smart-b9dc92d2-fb1d-49b7-a185-2c41ff7e4152
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719960682 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all_with_rand_reset.1719960682
Directory /workspace/7.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.2970312167
Short name T468
Test name
Test status
Simulation time 329122298 ps
CPU time 4.44 seconds
Started Mar 03 02:34:10 PM PST 24
Finished Mar 03 02:34:15 PM PST 24
Peak memory 222016 kb
Host smart-872c2e59-6ba9-4328-a733-9c1a88dadf82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970312167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.2970312167
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.3963382848
Short name T681
Test name
Test status
Simulation time 42307581 ps
CPU time 2.21 seconds
Started Mar 03 02:34:10 PM PST 24
Finished Mar 03 02:34:12 PM PST 24
Peak memory 209284 kb
Host smart-0d34a6a0-90fb-41a3-a2b8-31c69164e3ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3963382848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.3963382848
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.2240858211
Short name T623
Test name
Test status
Simulation time 9953495 ps
CPU time 0.73 seconds
Started Mar 03 02:34:16 PM PST 24
Finished Mar 03 02:34:17 PM PST 24
Peak memory 205556 kb
Host smart-d4d54b9b-a9a7-44f8-9a08-61ea79697dd1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2240858211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.2240858211
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.3290255760
Short name T226
Test name
Test status
Simulation time 209769651 ps
CPU time 4.27 seconds
Started Mar 03 02:34:15 PM PST 24
Finished Mar 03 02:34:19 PM PST 24
Peak memory 213804 kb
Host smart-f679481d-31aa-457b-b303-bdc71f4e3e8d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3290255760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.3290255760
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.352462397
Short name T594
Test name
Test status
Simulation time 75470874 ps
CPU time 3.55 seconds
Started Mar 03 02:34:24 PM PST 24
Finished Mar 03 02:34:28 PM PST 24
Peak memory 206636 kb
Host smart-9afb939e-185c-46a0-b7c5-809c40cce1ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=352462397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.352462397
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.1595619261
Short name T218
Test name
Test status
Simulation time 46118377 ps
CPU time 3.35 seconds
Started Mar 03 02:34:18 PM PST 24
Finished Mar 03 02:34:21 PM PST 24
Peak memory 207828 kb
Host smart-6dd2e83c-1142-4aec-98a4-d6040fd297ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1595619261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.1595619261
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.3925201593
Short name T504
Test name
Test status
Simulation time 245118884 ps
CPU time 6.16 seconds
Started Mar 03 02:34:16 PM PST 24
Finished Mar 03 02:34:23 PM PST 24
Peak memory 217856 kb
Host smart-8eec046b-5757-44dd-b5eb-3b21c37e232b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3925201593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.3925201593
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.1556491269
Short name T542
Test name
Test status
Simulation time 409759089 ps
CPU time 4.02 seconds
Started Mar 03 02:34:17 PM PST 24
Finished Mar 03 02:34:21 PM PST 24
Peak memory 208096 kb
Host smart-7be12391-46ac-4c01-a10d-db3cbf6d6ca6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556491269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.1556491269
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.2863263738
Short name T826
Test name
Test status
Simulation time 342937511 ps
CPU time 1.82 seconds
Started Mar 03 02:34:20 PM PST 24
Finished Mar 03 02:34:23 PM PST 24
Peak memory 205448 kb
Host smart-9f4e2ad8-a9ce-4658-aab7-4adc5b213266
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863263738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.2863263738
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.3664565085
Short name T543
Test name
Test status
Simulation time 64534994 ps
CPU time 2.58 seconds
Started Mar 03 02:34:18 PM PST 24
Finished Mar 03 02:34:22 PM PST 24
Peak memory 206076 kb
Host smart-402aea89-394d-4bbf-bf30-654a8c995793
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664565085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.3664565085
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.1161014557
Short name T602
Test name
Test status
Simulation time 125546938 ps
CPU time 3.62 seconds
Started Mar 03 02:34:17 PM PST 24
Finished Mar 03 02:34:21 PM PST 24
Peak memory 207132 kb
Host smart-13cb7390-223f-48f3-8d12-d2c90df6cbd8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161014557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.1161014557
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.1342683233
Short name T347
Test name
Test status
Simulation time 43567073 ps
CPU time 2.51 seconds
Started Mar 03 02:34:16 PM PST 24
Finished Mar 03 02:34:19 PM PST 24
Peak memory 208104 kb
Host smart-5903f4aa-8dc5-4d0f-b54b-f913de589070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1342683233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.1342683233
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.3549609
Short name T509
Test name
Test status
Simulation time 90325301 ps
CPU time 2.1 seconds
Started Mar 03 02:34:16 PM PST 24
Finished Mar 03 02:34:18 PM PST 24
Peak memory 207848 kb
Host smart-27d045ff-f007-4f03-b00d-8f8f5607b7f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3549609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.3549609
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.2717563360
Short name T605
Test name
Test status
Simulation time 9267969671 ps
CPU time 27.54 seconds
Started Mar 03 02:34:17 PM PST 24
Finished Mar 03 02:34:45 PM PST 24
Peak memory 216344 kb
Host smart-e314bd0e-18d1-4b51-8792-818fc7797b0d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717563360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.2717563360
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_stress_all_with_rand_reset.3048618691
Short name T114
Test name
Test status
Simulation time 982006448 ps
CPU time 10.73 seconds
Started Mar 03 02:34:23 PM PST 24
Finished Mar 03 02:34:35 PM PST 24
Peak memory 222088 kb
Host smart-495a92d0-cba7-4ac6-a118-e7983c830625
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3048618691 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all_with_rand_reset.3048618691
Directory /workspace/8.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.572339053
Short name T719
Test name
Test status
Simulation time 2782015977 ps
CPU time 69.11 seconds
Started Mar 03 02:34:24 PM PST 24
Finished Mar 03 02:35:34 PM PST 24
Peak memory 221448 kb
Host smart-a62a1723-a258-4349-bc59-7684bdec8350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=572339053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.572339053
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.2993191624
Short name T890
Test name
Test status
Simulation time 123299441 ps
CPU time 2.1 seconds
Started Mar 03 02:34:17 PM PST 24
Finished Mar 03 02:34:20 PM PST 24
Peak memory 209204 kb
Host smart-a43a29e1-0b78-4681-8030-f449769b8c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993191624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.2993191624
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.1860224132
Short name T746
Test name
Test status
Simulation time 28226862 ps
CPU time 0.73 seconds
Started Mar 03 02:34:15 PM PST 24
Finished Mar 03 02:34:16 PM PST 24
Peak memory 205784 kb
Host smart-bf915c52-58fe-4a82-922a-8cba28e2eb07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860224132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.1860224132
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.2497642551
Short name T358
Test name
Test status
Simulation time 63406765 ps
CPU time 2.73 seconds
Started Mar 03 02:34:16 PM PST 24
Finished Mar 03 02:34:19 PM PST 24
Peak memory 213780 kb
Host smart-e2f102e0-4859-4b35-b800-ec17089da742
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2497642551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.2497642551
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.953708997
Short name T334
Test name
Test status
Simulation time 63725166 ps
CPU time 1.96 seconds
Started Mar 03 02:34:16 PM PST 24
Finished Mar 03 02:34:18 PM PST 24
Peak memory 207056 kb
Host smart-31c26cb0-c69b-4cb1-af42-91a44c728fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953708997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.953708997
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.2131414633
Short name T523
Test name
Test status
Simulation time 2182814606 ps
CPU time 36.35 seconds
Started Mar 03 02:34:16 PM PST 24
Finished Mar 03 02:34:53 PM PST 24
Peak memory 208612 kb
Host smart-065100c0-27df-44dc-96a7-f14bab03ed82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131414633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.2131414633
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.3820478600
Short name T747
Test name
Test status
Simulation time 110681510 ps
CPU time 3.71 seconds
Started Mar 03 02:34:24 PM PST 24
Finished Mar 03 02:34:29 PM PST 24
Peak memory 209068 kb
Host smart-b26606ad-c672-4c61-86f7-a540c1fc29c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820478600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.3820478600
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.2337832207
Short name T556
Test name
Test status
Simulation time 335423099 ps
CPU time 9.42 seconds
Started Mar 03 02:34:16 PM PST 24
Finished Mar 03 02:34:26 PM PST 24
Peak memory 209004 kb
Host smart-7844fae4-8562-4516-a5cc-45dffaf6ed2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337832207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.2337832207
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.2414896798
Short name T243
Test name
Test status
Simulation time 64773584 ps
CPU time 3.6 seconds
Started Mar 03 02:34:16 PM PST 24
Finished Mar 03 02:34:19 PM PST 24
Peak memory 208016 kb
Host smart-72548706-3642-4632-b4b6-7ada1536899e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2414896798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.2414896798
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.1022354809
Short name T617
Test name
Test status
Simulation time 3530280312 ps
CPU time 8.29 seconds
Started Mar 03 02:34:23 PM PST 24
Finished Mar 03 02:34:33 PM PST 24
Peak memory 208028 kb
Host smart-9a2dd176-4bd0-4961-bfb2-3f04d99b6ed0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1022354809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.1022354809
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.3533326052
Short name T700
Test name
Test status
Simulation time 310610331 ps
CPU time 3.28 seconds
Started Mar 03 02:34:17 PM PST 24
Finished Mar 03 02:34:21 PM PST 24
Peak memory 206316 kb
Host smart-a6a54907-d884-4eb7-8bfd-b578d15ed0b2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533326052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.3533326052
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.3486183740
Short name T772
Test name
Test status
Simulation time 3690054576 ps
CPU time 28.71 seconds
Started Mar 03 02:34:16 PM PST 24
Finished Mar 03 02:34:45 PM PST 24
Peak memory 208380 kb
Host smart-771b0026-55bf-430b-9025-39a870ec5191
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486183740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.3486183740
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.1962445428
Short name T603
Test name
Test status
Simulation time 396152116 ps
CPU time 9.93 seconds
Started Mar 03 02:34:17 PM PST 24
Finished Mar 03 02:34:27 PM PST 24
Peak memory 213816 kb
Host smart-3ddf5ac7-7ff5-4ad3-89ff-acbeae1cdc83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962445428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.1962445428
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.2529653307
Short name T428
Test name
Test status
Simulation time 67588762 ps
CPU time 3.12 seconds
Started Mar 03 02:34:20 PM PST 24
Finished Mar 03 02:34:24 PM PST 24
Peak memory 207272 kb
Host smart-345a2bdc-e7f7-41ff-ac2b-b867505c8c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529653307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.2529653307
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.3521678208
Short name T486
Test name
Test status
Simulation time 375750896 ps
CPU time 2.26 seconds
Started Mar 03 02:34:20 PM PST 24
Finished Mar 03 02:34:23 PM PST 24
Peak memory 213896 kb
Host smart-cd6b9916-6d82-4095-ba0f-a5a8e19266f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521678208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.3521678208
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.2142160168
Short name T548
Test name
Test status
Simulation time 261697799 ps
CPU time 8.49 seconds
Started Mar 03 02:34:23 PM PST 24
Finished Mar 03 02:34:33 PM PST 24
Peak memory 207824 kb
Host smart-46ef3d9b-05c4-4b51-80fa-2fd3651829eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2142160168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.2142160168
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.868831986
Short name T370
Test name
Test status
Simulation time 258188193 ps
CPU time 5.07 seconds
Started Mar 03 02:34:20 PM PST 24
Finished Mar 03 02:34:26 PM PST 24
Peak memory 209180 kb
Host smart-7c6c9a9a-6726-4129-a364-d5ed63685369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868831986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.868831986
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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