Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
43.16	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	360	216	144	40.00

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	168	112	40.00	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11555

1

T1

4

T2

11

T3

5

auto[Attestation]

8302

1

T2

9

T3

3

T4

5

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2889	1			T1	1		T2	4		T15	5
auto[Aes]	3511	1			T3	8		T4	2		T13	18
auto[Kmac]	3638	1			T2	2		T4	2		T14	2
auto[Otbn]	3693	1			T1	1		T2	5		T4	6

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7815	1			T1	1		T2	8		T3	8
auto[OpGenId]	6126	1			T1	2		T2	9		T4	3
auto[OpGenSwOut]	6256	1			T1	1		T2	7		T4	3
auto[OpGenHwOut]	7475	1			T1	1		T2	4		T3	8
auto[OpDisable]	138	1			T45	1		T46	1		T47	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10408

1

T1

1

T2

10

T3

8

auto[OpDoneFail]

17402

1

T1

4

T2

18

T3

8

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6396	1			T1	1		T2	1		T3	1
auto[StInit]	4318	1			T1	4		T2	3		T3	2
auto[StCreatorRootKey]	3078	1			T2	5		T3	2		T13	2
auto[StOwnerIntKey]	2769	1			T2	5		T3	2		T13	2
auto[StOwnerKey]	2453	1			T2	1		T3	2		T13	2
auto[StDisabled]	7747	1			T2	13		T3	7		T13	7
auto[StInvalid]	1049	1			T4	18		T100	22		T38	10

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	168	112	40.00	168

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	296	1			T126	1		T22	1		T127	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	119	1			T126	1		T46	1		T23	3
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	66	1			T41	1		T101	1		T104	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	77	1			T2	1		T46	2		T41	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	65	1			T68	1		T46	2		T183	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	213	1			T15	1		T85	1		T86	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	31	1			T184	1		T185	1		T92	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	310	1			T22	1		T186	1		T54	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	105	1			T26	1		T22	1		T46	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	78	1			T15	1		T26	1		T85	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	66	1			T39	1		T127	1		T68	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	63	1			T33	1		T6	1		T101	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	213	1			T46	1		T47	1		T67	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	24	1			T100	1		T187	1		T188	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	326	1			T22	2		T127	1		T80	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	109	1			T85	1		T22	1		T54	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	83	1			T56	1		T41	1		T6	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	66	1			T23	1		T37	1		T189	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	69	1			T85	1		T37	1		T6	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	233	1			T2	1		T39	1		T85	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	42	1			T4	1		T38	1		T187	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	302	1			T22	1		T80	1		T56	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	129	1			T1	1		T14	1		T17	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	73	1			T2	1		T23	1		T190	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	80	1			T2	1		T15	2		T26	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	68	1			T37	1		T186	1		T6	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	226	1			T2	1		T26	1		T68	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	37	1			T187	1		T188	1		T184	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	90	1			T46	3		T41	2		T6	3
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	131	1			T55	1		T22	2		T127	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	95	1			T190	1		T54	1		T41	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	58	1			T39	1		T85	1		T173	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	55	1			T68	1		T101	1		T175	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	209	1			T2	1		T40	1		T46	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	35	1			T188	1		T184	2		T191	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	79	1			T46	4		T41	2		T6	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	127	1			T17	1		T22	2		T127	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	97	1			T15	1		T46	1		T60	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	72	1			T186	1		T41	1		T6	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	67	1			T190	1		T186	1		T41	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	221	1			T26	2		T40	1		T39	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	30	1			T184	2		T185	1		T92	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	74	1			T46	6		T6	3		T101	5
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	118	1			T2	1		T17	1		T55	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	66	1			T41	2		T121	1		T192	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	93	1			T26	1		T127	1		T183	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	62	1			T40	1		T33	1		T6	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	213	1			T46	1		T190	1		T80	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	27	1			T4	1		T38	1		T187	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	77	1			T46	4		T41	5		T6	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	118	1			T22	1		T18	1		T33	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	84	1			T126	1		T45	1		T18	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	77	1			T41	1		T28	1		T6	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	69	1			T193	1		T101	1		T194	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	206	1			T15	1		T26	1		T86	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	37	1			T4	1		T100	1		T188	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	276	1			T16	1		T22	1		T127	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	118	1			T1	1		T39	1		T55	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	60	1			T183	1		T54	1		T41	3
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	61	1			T15	1		T46	1		T59	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	37	1			T46	1		T80	1		T101	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	179	1			T2	1		T15	2		T39	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	28	1			T187	1		T94	2		T195	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	482	1			T13	10		T48	5		T126	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	137	1			T3	1		T4	1		T13	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	96	1			T3	1		T13	1		T14	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	93	1			T3	1		T13	1		T48	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	81	1			T48	1		T39	1		T46	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	273	1			T3	2		T13	1		T15	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	35	1			T4	1		T187	1		T188	4
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	508	1			T126	1		T22	2		T37	4
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	143	1			T126	1		T22	1		T18	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	101	1			T14	1		T16	1		T39	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	107	1			T126	2		T33	1		T82	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	95	1			T127	1		T183	2		T82	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	261	1			T39	1		T86	1		T46	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	27	1			T187	1		T184	1		T94	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	517	1			T127	1		T99	2		T196	3
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	137	1			T18	2		T127	1		T99	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	106	1			T14	1		T16	1		T45	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	99	1			T45	1		T196	1		T60	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	99	1			T196	1		T67	1		T79	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	275	1			T46	2		T196	1		T190	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	38	1			T4	2		T100	1		T184	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	70	1			T46	1		T41	3		T58	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	119	1			T2	1		T86	1		T22	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	71	1			T15	1		T39	1		T126	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	54	1			T54	1		T128	1		T197	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	60	1			T41	2		T128	1		T101	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	183	1			T39	1		T46	3		T190	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	33	1			T184	1		T198	1		T92	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	50	1			T41	3		T101	3		T104	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	119	1			T17	1		T48	1		T22	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	108	1			T14	1		T17	1		T48	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	93	1			T86	1		T60	1		T128	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	86	1			T3	1		T13	1		T86	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	281	1			T3	2		T13	3		T48	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	25	1			T188	1		T94	1		T198	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	74	1			T46	2		T41	3		T101	5
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	149	1			T14	1		T26	1		T33	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	111	1			T16	1		T17	2		T126	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	91	1			T46	2		T183	1		T37	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	75	1			T15	1		T127	1		T101	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	278	1			T26	2		T40	1		T39	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	37	1			T100	1		T38	2		T184	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	62	1			T46	1		T41	1		T6	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	140	1			T14	1		T26	1		T39	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	114	1			T14	1		T15	1		T16	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	107	1			T2	1		T26	1		T99	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	103	1			T39	1		T99	1		T46	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	283	1			T2	1		T99	4		T196	3
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	30	1			T4	3		T100	3		T184	2

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	183	1			T68	1		T46	2		T183	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	684	1			T2	1		T15	1		T85	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	198	1			T15	1		T26	1		T39	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	661	1			T26	1		T22	2		T46	4
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	198	1			T85	1		T37	2		T56	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	730	1			T2	1		T4	1		T39	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	209	1			T2	1		T15	2		T26	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	706	1			T1	1		T2	2		T14	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	190	1			T39	1		T85	1		T68	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	483	1			T2	1		T40	1		T55	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	224	1			T15	1		T46	1		T190	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	469	1			T17	1		T26	2		T40	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	209	1			T40	1		T127	1		T33	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	444	1			T2	1		T4	1		T17	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	207	1			T126	1		T45	1		T18	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	461	1			T4	1		T15	1		T26	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	152	1			T15	1		T46	2		T183	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	607	1			T1	1		T2	1		T15	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	257	1			T3	2		T13	2		T14	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	940	1			T3	3		T4	2		T13	12
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	287	1			T14	1		T16	1		T39	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	955	1			T39	1		T126	2		T86	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	284	1			T14	1		T16	1		T45	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	987	1			T4	2		T18	2		T127	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	165	1			T15	1		T39	1		T126	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	425	1			T2	1		T39	1		T86	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	273	1			T3	1		T13	1		T14	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	489	1			T3	2		T13	3		T17	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	256	1			T15	1		T16	1		T17	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	559	1			T14	1		T26	3		T40	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	306	1			T14	1		T15	1		T16	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	533	1			T2	2		T4	3		T14	1