Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31802

1

T1

5

T2

34

T3

20

auto[1]

262

1

T15

3

T80

3

T121

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	31814	1			T1	5		T2	34		T3	20
auto[134217728:268435455]	12	1			T300	1		T301	1		T408	2
auto[268435456:402653183]	5	1			T80	1		T129	1		T387	1
auto[402653184:536870911]	9	1			T285	2		T301	1		T254	1
auto[536870912:671088639]	6	1			T129	1		T273	1		T243	1
auto[671088640:805306367]	8	1			T121	1		T285	1		T408	1
auto[805306368:939524095]	9	1			T273	1		T131	1		T286	1
auto[939524096:1073741823]	5	1			T128	1		T254	1		T299	1
auto[1073741824:1207959551]	9	1			T129	1		T273	1		T286	1
auto[1207959552:1342177279]	2	1			T408	1		T387	1		-	-
auto[1342177280:1476395007]	5	1			T123	1		T128	1		T254	1
auto[1476395008:1610612735]	13	1			T80	1		T285	1		T254	1
auto[1610612736:1744830463]	6	1			T128	1		T129	1		T408	1
auto[1744830464:1879048191]	5	1			T285	1		T327	1		T387	2
auto[1879048192:2013265919]	4	1			T285	1		T325	1		T409	1
auto[2013265920:2147483647]	8	1			T15	1		T307	1		T285	1
auto[2147483648:2281701375]	11	1			T269	2		T223	1		T408	1
auto[2281701376:2415919103]	9	1			T121	1		T128	2		T300	1
auto[2415919104:2550136831]	8	1			T300	1		T223	1		T327	2
auto[2550136832:2684354559]	12	1			T129	1		T273	1		T285	2
auto[2684354560:2818572287]	7	1			T131	2		T223	1		T408	2
auto[2818572288:2952790015]	3	1			T128	1		T229	1		T387	1
auto[2952790016:3087007743]	6	1			T128	3		T254	1		T325	1
auto[3087007744:3221225471]	13	1			T121	1		T307	2		T285	2
auto[3221225472:3355443199]	8	1			T131	1		T285	1		T301	1
auto[3355443200:3489660927]	8	1			T15	1		T273	1		T285	2
auto[3489660928:3623878655]	12	1			T128	1		T129	2		T273	1
auto[3623878656:3758096383]	10	1			T128	1		T307	1		T301	1
auto[3758096384:3892314111]	7	1			T121	1		T128	1		T387	1
auto[3892314112:4026531839]	10	1			T15	1		T80	1		T269	1
auto[4026531840:4160749567]	10	1			T285	2		T299	1		T410	1
auto[4160749568:4294967295]	10	1			T128	1		T129	1		T300	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	31802	1			T1	5		T2	34		T3	20
auto[0:134217727]	auto[1]	12	1			T123	1		T128	1		T131	2
auto[134217728:268435455]	auto[1]	12	1			T300	1		T301	1		T408	2
auto[268435456:402653183]	auto[1]	5	1			T80	1		T129	1		T387	1
auto[402653184:536870911]	auto[1]	9	1			T285	2		T301	1		T254	1
auto[536870912:671088639]	auto[1]	6	1			T129	1		T273	1		T243	1
auto[671088640:805306367]	auto[1]	8	1			T121	1		T285	1		T408	1
auto[805306368:939524095]	auto[1]	9	1			T273	1		T131	1		T286	1
auto[939524096:1073741823]	auto[1]	5	1			T128	1		T254	1		T299	1
auto[1073741824:1207959551]	auto[1]	9	1			T129	1		T273	1		T286	1
auto[1207959552:1342177279]	auto[1]	2	1			T408	1		T387	1		-	-
auto[1342177280:1476395007]	auto[1]	5	1			T123	1		T128	1		T254	1
auto[1476395008:1610612735]	auto[1]	13	1			T80	1		T285	1		T254	1
auto[1610612736:1744830463]	auto[1]	6	1			T128	1		T129	1		T408	1
auto[1744830464:1879048191]	auto[1]	5	1			T285	1		T327	1		T387	2
auto[1879048192:2013265919]	auto[1]	4	1			T285	1		T325	1		T409	1
auto[2013265920:2147483647]	auto[1]	8	1			T15	1		T307	1		T285	1
auto[2147483648:2281701375]	auto[1]	11	1			T269	2		T223	1		T408	1
auto[2281701376:2415919103]	auto[1]	9	1			T121	1		T128	2		T300	1
auto[2415919104:2550136831]	auto[1]	8	1			T300	1		T223	1		T327	2
auto[2550136832:2684354559]	auto[1]	12	1			T129	1		T273	1		T285	2
auto[2684354560:2818572287]	auto[1]	7	1			T131	2		T223	1		T408	2
auto[2818572288:2952790015]	auto[1]	3	1			T128	1		T229	1		T387	1
auto[2952790016:3087007743]	auto[1]	6	1			T128	3		T254	1		T325	1
auto[3087007744:3221225471]	auto[1]	13	1			T121	1		T307	2		T285	2
auto[3221225472:3355443199]	auto[1]	8	1			T131	1		T285	1		T301	1
auto[3355443200:3489660927]	auto[1]	8	1			T15	1		T273	1		T285	2
auto[3489660928:3623878655]	auto[1]	12	1			T128	1		T129	2		T273	1
auto[3623878656:3758096383]	auto[1]	10	1			T128	1		T307	1		T301	1
auto[3758096384:3892314111]	auto[1]	7	1			T121	1		T128	1		T387	1
auto[3892314112:4026531839]	auto[1]	10	1			T15	1		T80	1		T269	1
auto[4026531840:4160749567]	auto[1]	10	1			T285	2		T299	1		T410	1
auto[4160749568:4294967295]	auto[1]	10	1			T128	1		T129	1		T300	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1631

1

T2

2

T4

4

T14

1

auto[1]

1794

1

T2

1

T14

1

T15

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	110	1			T16	1		T17	1		T39	1
auto[134217728:268435455]	107	1			T14	1		T41	1		T6	1
auto[268435456:402653183]	110	1			T15	1		T55	2		T45	1
auto[402653184:536870911]	98	1			T26	1		T55	1		T190	1
auto[536870912:671088639]	98	1			T23	1		T54	1		T41	1
auto[671088640:805306367]	122	1			T186	1		T41	4		T189	1
auto[805306368:939524095]	95	1			T127	1		T47	1		T67	1
auto[939524096:1073741823]	119	1			T4	1		T46	1		T67	1
auto[1073741824:1207959551]	91	1			T46	1		T41	1		T6	1
auto[1207959552:1342177279]	100	1			T22	1		T46	1		T186	1
auto[1342177280:1476395007]	115	1			T27	1		T190	1		T47	1
auto[1476395008:1610612735]	126	1			T4	1		T39	1		T126	1
auto[1610612736:1744830463]	101	1			T46	1		T190	1		T80	1
auto[1744830464:1879048191]	91	1			T68	1		T41	2		T121	1
auto[1879048192:2013265919]	113	1			T4	1		T47	1		T41	1
auto[2013265920:2147483647]	112	1			T26	1		T55	1		T22	1
auto[2147483648:2281701375]	102	1			T23	1		T80	1		T41	1
auto[2281701376:2415919103]	111	1			T22	1		T183	1		T41	1
auto[2415919104:2550136831]	101	1			T18	1		T52	2		T68	1
auto[2550136832:2684354559]	118	1			T53	1		T46	1		T183	1
auto[2684354560:2818572287]	97	1			T22	1		T46	1		T183	1
auto[2818572288:2952790015]	101	1			T14	1		T18	1		T6	2
auto[2952790016:3087007743]	92	1			T53	1		T68	1		T41	1
auto[3087007744:3221225471]	103	1			T4	1		T26	1		T39	1
auto[3221225472:3355443199]	104	1			T2	1		T68	1		T46	1
auto[3355443200:3489660927]	116	1			T22	1		T80	1		T41	3
auto[3489660928:3623878655]	115	1			T2	2		T126	1		T127	1
auto[3623878656:3758096383]	126	1			T15	1		T52	1		T68	1
auto[3758096384:3892314111]	98	1			T18	1		T67	1		T60	1
auto[3892314112:4026531839]	116	1			T55	1		T186	1		T54	1
auto[4026531840:4160749567]	115	1			T46	1		T183	1		T80	1
auto[4160749568:4294967295]	102	1			T55	1		T126	1		T22	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	48	1			T16	1		T52	1		T46	1
auto[0:134217727]	auto[1]	62	1			T17	1		T39	1		T24	1
auto[134217728:268435455]	auto[0]	58	1			T173	1		T58	1		T265	2
auto[134217728:268435455]	auto[1]	49	1			T14	1		T41	1		T6	1
auto[268435456:402653183]	auto[0]	58	1			T55	1		T22	2		T53	1
auto[268435456:402653183]	auto[1]	52	1			T15	1		T55	1		T45	1
auto[402653184:536870911]	auto[0]	48	1			T26	1		T41	1		T100	1
auto[402653184:536870911]	auto[1]	50	1			T55	1		T190	1		T41	1
auto[536870912:671088639]	auto[0]	61	1			T23	1		T41	1		T25	1
auto[536870912:671088639]	auto[1]	37	1			T54	1		T101	1		T44	1
auto[671088640:805306367]	auto[0]	59	1			T275	1		T258	1		T323	1
auto[671088640:805306367]	auto[1]	63	1			T186	1		T41	4		T189	1
auto[805306368:939524095]	auto[0]	35	1			T127	1		T67	1		T187	1
auto[805306368:939524095]	auto[1]	60	1			T47	1		T41	1		T24	1
auto[939524096:1073741823]	auto[0]	49	1			T4	1		T41	1		T6	1
auto[939524096:1073741823]	auto[1]	70	1			T46	1		T67	1		T41	2
auto[1073741824:1207959551]	auto[0]	41	1			T46	1		T101	2		T42	1
auto[1073741824:1207959551]	auto[1]	50	1			T41	1		T6	1		T34	1
auto[1207959552:1342177279]	auto[0]	48	1			T22	1		T41	1		T226	1
auto[1207959552:1342177279]	auto[1]	52	1			T46	1		T186	1		T89	1
auto[1342177280:1476395007]	auto[0]	52	1			T27	1		T197	1		T42	1
auto[1342177280:1476395007]	auto[1]	63	1			T190	1		T47	1		T80	1
auto[1476395008:1610612735]	auto[0]	54	1			T4	1		T39	1		T126	1
auto[1476395008:1610612735]	auto[1]	72	1			T81	1		T41	1		T101	1
auto[1610612736:1744830463]	auto[0]	47	1			T41	1		T101	1		T58	1
auto[1610612736:1744830463]	auto[1]	54	1			T46	1		T190	1		T80	1
auto[1744830464:1879048191]	auto[0]	47	1			T121	1		T173	1		T104	1
auto[1744830464:1879048191]	auto[1]	44	1			T68	1		T41	2		T28	1
auto[1879048192:2013265919]	auto[0]	39	1			T4	1		T226	1		T101	1
auto[1879048192:2013265919]	auto[1]	74	1			T47	1		T41	1		T24	1
auto[2013265920:2147483647]	auto[0]	68	1			T26	1		T22	1		T68	1
auto[2013265920:2147483647]	auto[1]	44	1			T55	1		T53	1		T121	1
auto[2147483648:2281701375]	auto[0]	50	1			T23	1		T6	1		T189	2
auto[2147483648:2281701375]	auto[1]	52	1			T80	1		T41	1		T101	1
auto[2281701376:2415919103]	auto[0]	57	1			T22	1		T41	1		T123	1
auto[2281701376:2415919103]	auto[1]	54	1			T183	1		T89	2		T71	1
auto[2415919104:2550136831]	auto[0]	55	1			T18	1		T52	2		T6	1
auto[2415919104:2550136831]	auto[1]	46	1			T68	1		T88	1		T72	1
auto[2550136832:2684354559]	auto[0]	56	1			T53	1		T46	1		T183	1
auto[2550136832:2684354559]	auto[1]	62	1			T58	1		T114	1		T72	1
auto[2684354560:2818572287]	auto[0]	47	1			T22	1		T72	1		T355	1
auto[2684354560:2818572287]	auto[1]	50	1			T46	1		T183	1		T41	1
auto[2818572288:2952790015]	auto[0]	46	1			T14	1		T6	1		T189	1
auto[2818572288:2952790015]	auto[1]	55	1			T18	1		T6	1		T101	1
auto[2952790016:3087007743]	auto[0]	43	1			T68	1		T121	1		T101	1
auto[2952790016:3087007743]	auto[1]	49	1			T53	1		T41	1		T71	1
auto[3087007744:3221225471]	auto[0]	50	1			T4	1		T54	1		T173	1
auto[3087007744:3221225471]	auto[1]	53	1			T26	1		T39	1		T46	3
auto[3221225472:3355443199]	auto[0]	42	1			T2	1		T41	3		T197	1
auto[3221225472:3355443199]	auto[1]	62	1			T68	1		T46	1		T186	1
auto[3355443200:3489660927]	auto[0]	58	1			T22	1		T41	1		T6	1
auto[3355443200:3489660927]	auto[1]	58	1			T80	1		T41	2		T101	1
auto[3489660928:3623878655]	auto[0]	57	1			T2	1		T126	1		T183	1
auto[3489660928:3623878655]	auto[1]	58	1			T2	1		T127	1		T23	1
auto[3623878656:3758096383]	auto[0]	60	1			T52	1		T186	1		T101	1
auto[3623878656:3758096383]	auto[1]	66	1			T15	1		T68	1		T101	1
auto[3758096384:3892314111]	auto[0]	55	1			T18	1		T25	1		T226	1
auto[3758096384:3892314111]	auto[1]	43	1			T67	1		T60	1		T54	1
auto[3892314112:4026531839]	auto[0]	43	1			T186	1		T41	1		T226	1
auto[3892314112:4026531839]	auto[1]	73	1			T55	1		T54	1		T41	2
auto[4026531840:4160749567]	auto[0]	47	1			T41	2		T25	1		T101	1
auto[4026531840:4160749567]	auto[1]	68	1			T46	1		T183	1		T80	1
auto[4160749568:4294967295]	auto[0]	53	1			T22	1		T60	1		T173	1
auto[4160749568:4294967295]	auto[1]	49	1			T55	1		T126	1		T46	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1644

1

T2

2

T4

4

T14

2

auto[1]

1783

1

T2

1

T15

2

T17

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	102	1			T14	2		T126	1		T41	1
auto[134217728:268435455]	116	1			T4	1		T22	1		T80	1
auto[268435456:402653183]	105	1			T127	1		T52	1		T46	1
auto[402653184:536870911]	117	1			T2	1		T15	1		T55	1
auto[536870912:671088639]	93	1			T22	1		T46	1		T41	2
auto[671088640:805306367]	111	1			T22	1		T68	2		T80	1
auto[805306368:939524095]	94	1			T2	1		T39	1		T52	1
auto[939524096:1073741823]	123	1			T4	1		T47	1		T54	1
auto[1073741824:1207959551]	92	1			T68	1		T186	1		T54	1
auto[1207959552:1342177279]	99	1			T39	1		T47	1		T183	1
auto[1342177280:1476395007]	100	1			T55	1		T18	2		T53	1
auto[1476395008:1610612735]	87	1			T183	1		T41	1		T100	1
auto[1610612736:1744830463]	107	1			T4	1		T52	1		T190	1
auto[1744830464:1879048191]	106	1			T26	1		T67	1		T41	1
auto[1879048192:2013265919]	113	1			T55	1		T186	1		T41	1
auto[2013265920:2147483647]	98	1			T55	1		T53	1		T46	1
auto[2147483648:2281701375]	108	1			T59	1		T54	1		T41	2
auto[2281701376:2415919103]	106	1			T15	1		T126	1		T22	1
auto[2415919104:2550136831]	89	1			T45	1		T127	1		T46	2
auto[2550136832:2684354559]	119	1			T26	1		T22	1		T81	1
auto[2684354560:2818572287]	117	1			T22	1		T46	2		T41	1
auto[2818572288:2952790015]	107	1			T55	1		T46	1		T80	1
auto[2952790016:3087007743]	113	1			T55	1		T68	1		T46	1
auto[3087007744:3221225471]	99	1			T17	1		T126	1		T68	1
auto[3221225472:3355443199]	101	1			T2	1		T60	1		T89	1
auto[3355443200:3489660927]	136	1			T26	1		T27	1		T54	1
auto[3489660928:3623878655]	101	1			T4	1		T22	1		T23	1
auto[3623878656:3758096383]	114	1			T16	1		T52	1		T183	1
auto[3758096384:3892314111]	114	1			T22	1		T18	1		T23	1
auto[3892314112:4026531839]	116	1			T46	1		T41	4		T6	1
auto[4026531840:4160749567]	97	1			T53	1		T46	1		T47	1
auto[4160749568:4294967295]	127	1			T39	1		T53	1		T46	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	60	1			T14	2		T41	1		T173	2
auto[0:134217727]	auto[1]	42	1			T126	1		T121	1		T101	1
auto[134217728:268435455]	auto[0]	58	1			T4	1		T22	1		T6	1
auto[134217728:268435455]	auto[1]	58	1			T80	1		T186	1		T41	1
auto[268435456:402653183]	auto[0]	50	1			T127	1		T52	1		T128	1
auto[268435456:402653183]	auto[1]	55	1			T46	1		T128	1		T245	1
auto[402653184:536870911]	auto[0]	54	1			T2	1		T67	1		T101	1
auto[402653184:536870911]	auto[1]	63	1			T15	1		T55	1		T46	1
auto[536870912:671088639]	auto[0]	40	1			T22	1		T101	1		T245	1
auto[536870912:671088639]	auto[1]	53	1			T46	1		T41	2		T71	1
auto[671088640:805306367]	auto[0]	50	1			T22	1		T68	1		T226	1
auto[671088640:805306367]	auto[1]	61	1			T68	1		T80	1		T101	1
auto[805306368:939524095]	auto[0]	46	1			T52	1		T6	1		T58	1
auto[805306368:939524095]	auto[1]	48	1			T2	1		T39	1		T23	1
auto[939524096:1073741823]	auto[0]	62	1			T4	1		T54	1		T226	1
auto[939524096:1073741823]	auto[1]	61	1			T47	1		T101	1		T88	1
auto[1073741824:1207959551]	auto[0]	37	1			T68	1		T41	1		T187	1
auto[1073741824:1207959551]	auto[1]	55	1			T186	1		T54	1		T24	1
auto[1207959552:1342177279]	auto[0]	38	1			T183	1		T6	1		T173	1
auto[1207959552:1342177279]	auto[1]	61	1			T39	1		T47	1		T186	1
auto[1342177280:1476395007]	auto[0]	42	1			T18	1		T53	1		T38	1
auto[1342177280:1476395007]	auto[1]	58	1			T55	1		T18	1		T54	1
auto[1476395008:1610612735]	auto[0]	49	1			T41	1		T100	1		T173	1
auto[1476395008:1610612735]	auto[1]	38	1			T183	1		T34	1		T58	1
auto[1610612736:1744830463]	auto[0]	56	1			T4	1		T52	1		T41	1
auto[1610612736:1744830463]	auto[1]	51	1			T190	1		T183	1		T80	1
auto[1744830464:1879048191]	auto[0]	49	1			T411	1		T195	1		T130	1
auto[1744830464:1879048191]	auto[1]	57	1			T26	1		T67	1		T41	1
auto[1879048192:2013265919]	auto[0]	45	1			T186	1		T58	1		T61	2
auto[1879048192:2013265919]	auto[1]	68	1			T55	1		T41	1		T71	1
auto[2013265920:2147483647]	auto[0]	44	1			T53	1		T226	2		T88	1
auto[2013265920:2147483647]	auto[1]	54	1			T55	1		T46	1		T6	1
auto[2147483648:2281701375]	auto[0]	57	1			T59	1		T54	1		T25	1
auto[2147483648:2281701375]	auto[1]	51	1			T41	2		T88	1		T42	1
auto[2281701376:2415919103]	auto[0]	39	1			T22	1		T68	1		T46	1
auto[2281701376:2415919103]	auto[1]	67	1			T15	1		T126	1		T54	1
auto[2415919104:2550136831]	auto[0]	42	1			T46	1		T41	3		T6	1
auto[2415919104:2550136831]	auto[1]	47	1			T45	1		T127	1		T46	1
auto[2550136832:2684354559]	auto[0]	63	1			T26	1		T41	1		T58	1
auto[2550136832:2684354559]	auto[1]	56	1			T22	1		T81	1		T41	2
auto[2684354560:2818572287]	auto[0]	54	1			T22	1		T41	1		T121	1
auto[2684354560:2818572287]	auto[1]	63	1			T46	2		T101	1		T104	1
auto[2818572288:2952790015]	auto[0]	56	1			T55	1		T80	1		T186	1
auto[2818572288:2952790015]	auto[1]	51	1			T46	1		T41	1		T121	1
auto[2952790016:3087007743]	auto[0]	60	1			T46	1		T41	1		T25	1
auto[2952790016:3087007743]	auto[1]	53	1			T55	1		T68	1		T190	1
auto[3087007744:3221225471]	auto[0]	40	1			T126	1		T41	1		T258	1
auto[3087007744:3221225471]	auto[1]	59	1			T17	1		T68	1		T190	1
auto[3221225472:3355443199]	auto[0]	38	1			T2	1		T123	1		T192	1
auto[3221225472:3355443199]	auto[1]	63	1			T60	1		T89	1		T101	1
auto[3355443200:3489660927]	auto[0]	64	1			T26	1		T27	1		T226	1
auto[3355443200:3489660927]	auto[1]	72	1			T54	1		T41	1		T89	1
auto[3489660928:3623878655]	auto[0]	49	1			T4	1		T22	1		T23	1
auto[3489660928:3623878655]	auto[1]	52	1			T67	1		T123	1		T101	2
auto[3623878656:3758096383]	auto[0]	60	1			T16	1		T52	1		T183	1
auto[3623878656:3758096383]	auto[1]	54	1			T226	1		T100	1		T173	1
auto[3758096384:3892314111]	auto[0]	56	1			T22	1		T23	1		T41	1
auto[3758096384:3892314111]	auto[1]	58	1			T18	1		T60	1		T226	1
auto[3892314112:4026531839]	auto[0]	58	1			T46	1		T41	1		T6	1
auto[3892314112:4026531839]	auto[1]	58	1			T41	3		T101	1		T265	1
auto[4026531840:4160749567]	auto[0]	50	1			T128	1		T101	1		T100	1
auto[4026531840:4160749567]	auto[1]	47	1			T53	1		T46	1		T47	1
auto[4160749568:4294967295]	auto[0]	78	1			T39	1		T53	1		T54	1
auto[4160749568:4294967295]	auto[1]	49	1			T46	1		T183	1		T61	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1663

1

T2

2

T4

4

T14

2

auto[1]

1764

1

T2

1

T15

2

T17

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	93	1			T55	1		T22	1		T121	1
auto[134217728:268435455]	116	1			T55	1		T22	1		T46	1
auto[268435456:402653183]	127	1			T4	1		T16	1		T26	1
auto[402653184:536870911]	102	1			T14	1		T17	1		T52	1
auto[536870912:671088639]	104	1			T22	1		T27	1		T186	1
auto[671088640:805306367]	103	1			T18	1		T52	1		T183	1
auto[805306368:939524095]	109	1			T2	1		T47	1		T183	1
auto[939524096:1073741823]	108	1			T41	1		T123	1		T389	1
auto[1073741824:1207959551]	104	1			T46	2		T23	1		T41	2
auto[1207959552:1342177279]	100	1			T55	1		T60	1		T88	1
auto[1342177280:1476395007]	108	1			T53	1		T68	1		T54	1
auto[1476395008:1610612735]	105	1			T39	1		T46	2		T81	1
auto[1610612736:1744830463]	103	1			T89	1		T101	1		T88	1
auto[1744830464:1879048191]	108	1			T126	1		T53	1		T41	2
auto[1879048192:2013265919]	116	1			T2	1		T55	1		T67	1
auto[2013265920:2147483647]	121	1			T53	2		T46	1		T41	4
auto[2147483648:2281701375]	107	1			T22	1		T46	1		T101	1
auto[2281701376:2415919103]	102	1			T14	1		T68	2		T190	1
auto[2415919104:2550136831]	99	1			T15	1		T52	1		T190	1
auto[2550136832:2684354559]	123	1			T54	3		T41	1		T101	2
auto[2684354560:2818572287]	100	1			T4	1		T22	1		T46	1
auto[2818572288:2952790015]	125	1			T22	1		T68	1		T46	1
auto[2952790016:3087007743]	85	1			T15	1		T127	1		T54	1
auto[3087007744:3221225471]	97	1			T26	1		T22	1		T41	1
auto[3221225472:3355443199]	114	1			T26	1		T55	1		T68	1
auto[3355443200:3489660927]	113	1			T22	1		T46	1		T183	1
auto[3489660928:3623878655]	104	1			T4	1		T127	1		T68	1
auto[3623878656:3758096383]	102	1			T2	1		T55	1		T45	1
auto[3758096384:3892314111]	99	1			T126	1		T52	1		T46	1
auto[3892314112:4026531839]	108	1			T39	1		T101	1		T245	1
auto[4026531840:4160749567]	113	1			T46	1		T80	1		T186	1
auto[4160749568:4294967295]	109	1			T4	1		T18	1		T23	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	45	1			T22	1		T226	1		T6	1
auto[0:134217727]	auto[1]	48	1			T55	1		T121	1		T411	1
auto[134217728:268435455]	auto[0]	52	1			T22	1		T25	1		T6	1
auto[134217728:268435455]	auto[1]	64	1			T55	1		T46	1		T59	1
auto[268435456:402653183]	auto[0]	64	1			T4	1		T16	1		T39	1
auto[268435456:402653183]	auto[1]	63	1			T26	1		T46	1		T41	2
auto[402653184:536870911]	auto[0]	62	1			T14	1		T52	1		T6	1
auto[402653184:536870911]	auto[1]	40	1			T17	1		T67	1		T41	1
auto[536870912:671088639]	auto[0]	45	1			T22	1		T186	1		T101	1
auto[536870912:671088639]	auto[1]	59	1			T27	1		T89	1		T71	2
auto[671088640:805306367]	auto[0]	49	1			T52	1		T186	1		T101	1
auto[671088640:805306367]	auto[1]	54	1			T18	1		T183	1		T41	1
auto[805306368:939524095]	auto[0]	46	1			T226	1		T58	2		T61	1
auto[805306368:939524095]	auto[1]	63	1			T2	1		T47	1		T183	1
auto[939524096:1073741823]	auto[0]	52	1			T62	1		T43	1		T195	1
auto[939524096:1073741823]	auto[1]	56	1			T41	1		T123	1		T389	1
auto[1073741824:1207959551]	auto[0]	57	1			T46	1		T23	1		T41	2
auto[1073741824:1207959551]	auto[1]	47	1			T46	1		T24	1		T6	1
auto[1207959552:1342177279]	auto[0]	47	1			T55	1		T245	1		T265	1
auto[1207959552:1342177279]	auto[1]	53	1			T60	1		T88	1		T34	1
auto[1342177280:1476395007]	auto[0]	51	1			T41	1		T101	1		T7	1
auto[1342177280:1476395007]	auto[1]	57	1			T53	1		T68	1		T54	1
auto[1476395008:1610612735]	auto[0]	44	1			T101	1		T173	1		T197	1
auto[1476395008:1610612735]	auto[1]	61	1			T39	1		T46	2		T81	1
auto[1610612736:1744830463]	auto[0]	52	1			T88	1		T189	1		T114	1
auto[1610612736:1744830463]	auto[1]	51	1			T89	1		T101	1		T100	1
auto[1744830464:1879048191]	auto[0]	57	1			T126	1		T245	1		T187	1
auto[1744830464:1879048191]	auto[1]	51	1			T53	1		T41	2		T71	1
auto[1879048192:2013265919]	auto[0]	49	1			T2	1		T192	1		T42	1
auto[1879048192:2013265919]	auto[1]	67	1			T55	1		T67	1		T24	2
auto[2013265920:2147483647]	auto[0]	60	1			T53	2		T41	1		T121	1
auto[2013265920:2147483647]	auto[1]	61	1			T46	1		T41	3		T226	1
auto[2147483648:2281701375]	auto[0]	42	1			T22	1		T46	1		T173	1
auto[2147483648:2281701375]	auto[1]	65	1			T101	1		T104	1		T197	1
auto[2281701376:2415919103]	auto[0]	53	1			T14	1		T68	2		T60	1
auto[2281701376:2415919103]	auto[1]	49	1			T190	1		T54	1		T244	1
auto[2415919104:2550136831]	auto[0]	48	1			T52	1		T226	1		T173	1
auto[2415919104:2550136831]	auto[1]	51	1			T15	1		T190	1		T41	1
auto[2550136832:2684354559]	auto[0]	58	1			T54	2		T101	1		T42	1
auto[2550136832:2684354559]	auto[1]	65	1			T54	1		T41	1		T101	1
auto[2684354560:2818572287]	auto[0]	52	1			T4	1		T22	1		T80	1
auto[2684354560:2818572287]	auto[1]	48	1			T46	1		T54	1		T88	1
auto[2818572288:2952790015]	auto[0]	61	1			T22	1		T68	1		T46	1
auto[2818572288:2952790015]	auto[1]	64	1			T190	1		T47	2		T81	1
auto[2952790016:3087007743]	auto[0]	28	1			T25	1		T197	1		T187	1
auto[2952790016:3087007743]	auto[1]	57	1			T15	1		T127	1		T54	1
auto[3087007744:3221225471]	auto[0]	60	1			T26	1		T22	1		T41	1
auto[3087007744:3221225471]	auto[1]	37	1			T71	1		T128	1		T58	1
auto[3221225472:3355443199]	auto[0]	59	1			T68	1		T186	1		T25	1
auto[3221225472:3355443199]	auto[1]	55	1			T26	1		T55	1		T101	1
auto[3355443200:3489660927]	auto[0]	53	1			T22	1		T183	1		T80	1
auto[3355443200:3489660927]	auto[1]	60	1			T46	1		T41	1		T24	1
auto[3489660928:3623878655]	auto[0]	57	1			T4	1		T127	1		T67	1
auto[3489660928:3623878655]	auto[1]	47	1			T68	1		T41	4		T128	1
auto[3623878656:3758096383]	auto[0]	56	1			T2	1		T41	1		T6	3
auto[3623878656:3758096383]	auto[1]	46	1			T55	1		T45	1		T46	1
auto[3758096384:3892314111]	auto[0]	44	1			T126	1		T52	1		T41	1
auto[3758096384:3892314111]	auto[1]	55	1			T46	1		T183	1		T41	3
auto[3892314112:4026531839]	auto[0]	48	1			T411	1		T116	1		T261	1
auto[3892314112:4026531839]	auto[1]	60	1			T39	1		T101	1		T245	1
auto[4026531840:4160749567]	auto[0]	54	1			T128	1		T6	1		T100	1
auto[4026531840:4160749567]	auto[1]	59	1			T46	1		T80	1		T186	1
auto[4160749568:4294967295]	auto[0]	58	1			T4	1		T23	1		T41	2
auto[4160749568:4294967295]	auto[1]	51	1			T18	1		T80	1		T186	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1670

1

T2

2

T4

4

T14

1

auto[1]

1756

1

T2

1

T14

1

T15

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	104	1			T4	1		T26	1		T127	1
auto[134217728:268435455]	97	1			T2	1		T126	1		T46	1
auto[268435456:402653183]	122	1			T45	1		T127	1		T53	1
auto[402653184:536870911]	108	1			T186	1		T41	1		T197	1
auto[536870912:671088639]	118	1			T47	1		T183	1		T59	1
auto[671088640:805306367]	114	1			T4	1		T52	1		T46	1
auto[805306368:939524095]	99	1			T22	1		T46	1		T81	1
auto[939524096:1073741823]	104	1			T22	1		T41	1		T101	3
auto[1073741824:1207959551]	87	1			T22	1		T53	1		T190	1
auto[1207959552:1342177279]	100	1			T22	1		T23	1		T60	1
auto[1342177280:1476395007]	95	1			T14	1		T17	1		T41	3
auto[1476395008:1610612735]	100	1			T68	1		T41	1		T25	1
auto[1610612736:1744830463]	100	1			T80	1		T54	1		T41	2
auto[1744830464:1879048191]	102	1			T55	1		T126	1		T18	1
auto[1879048192:2013265919]	91	1			T4	1		T55	1		T186	1
auto[2013265920:2147483647]	104	1			T46	1		T41	3		T25	1
auto[2147483648:2281701375]	95	1			T22	1		T52	1		T46	1
auto[2281701376:2415919103]	126	1			T2	1		T55	1		T46	1
auto[2415919104:2550136831]	112	1			T15	1		T26	1		T39	1
auto[2550136832:2684354559]	119	1			T4	1		T18	1		T52	1
auto[2684354560:2818572287]	113	1			T68	1		T80	1		T41	2
auto[2818572288:2952790015]	127	1			T27	1		T52	1		T68	1
auto[2952790016:3087007743]	104	1			T18	1		T6	1		T101	1
auto[3087007744:3221225471]	117	1			T14	1		T46	1		T60	1
auto[3221225472:3355443199]	110	1			T55	2		T22	1		T53	1
auto[3355443200:3489660927]	109	1			T55	1		T126	1		T22	1
auto[3489660928:3623878655]	99	1			T22	1		T80	1		T186	1
auto[3623878656:3758096383]	108	1			T16	1		T26	1		T39	1
auto[3758096384:3892314111]	109	1			T2	1		T15	1		T46	1
auto[3892314112:4026531839]	108	1			T46	1		T183	1		T6	1
auto[4026531840:4160749567]	114	1			T23	1		T226	2		T28	1
auto[4160749568:4294967295]	111	1			T39	1		T41	2		T128	1