Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.78 99.07 98.03 98.29 100.00 99.11 98.41 91.56


Total test records in report: 1075
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html
T1005 /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.2803866479 Mar 05 01:44:14 PM PST 24 Mar 05 01:44:15 PM PST 24 13647733 ps
T1006 /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.1197004778 Mar 05 01:44:05 PM PST 24 Mar 05 01:44:19 PM PST 24 3598026172 ps
T156 /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.3134970863 Mar 05 01:44:06 PM PST 24 Mar 05 01:44:18 PM PST 24 509761612 ps
T1007 /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.2924934103 Mar 05 01:44:01 PM PST 24 Mar 05 01:44:03 PM PST 24 103502093 ps
T1008 /workspace/coverage/cover_reg_top/43.keymgr_intr_test.2491893053 Mar 05 01:44:30 PM PST 24 Mar 05 01:44:30 PM PST 24 7457429 ps
T1009 /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.591922159 Mar 05 01:44:13 PM PST 24 Mar 05 01:44:14 PM PST 24 24128088 ps
T1010 /workspace/coverage/cover_reg_top/27.keymgr_intr_test.2384405224 Mar 05 01:44:29 PM PST 24 Mar 05 01:44:30 PM PST 24 11216547 ps
T1011 /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.1260972717 Mar 05 01:44:32 PM PST 24 Mar 05 01:44:39 PM PST 24 163365238 ps
T1012 /workspace/coverage/cover_reg_top/24.keymgr_intr_test.1419197439 Mar 05 01:44:31 PM PST 24 Mar 05 01:44:31 PM PST 24 11789745 ps
T1013 /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.207649514 Mar 05 01:44:23 PM PST 24 Mar 05 01:44:30 PM PST 24 155847061 ps
T1014 /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.1571498801 Mar 05 01:44:20 PM PST 24 Mar 05 01:44:23 PM PST 24 45808258 ps
T1015 /workspace/coverage/cover_reg_top/23.keymgr_intr_test.3030665638 Mar 05 01:44:35 PM PST 24 Mar 05 01:44:36 PM PST 24 22391560 ps
T1016 /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.1344088624 Mar 05 01:43:59 PM PST 24 Mar 05 01:44:00 PM PST 24 15743781 ps
T1017 /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.2005483185 Mar 05 01:44:27 PM PST 24 Mar 05 01:44:29 PM PST 24 36424065 ps
T1018 /workspace/coverage/cover_reg_top/12.keymgr_intr_test.2640572406 Mar 05 01:44:24 PM PST 24 Mar 05 01:44:25 PM PST 24 30467731 ps
T1019 /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.592982232 Mar 05 01:44:04 PM PST 24 Mar 05 01:44:20 PM PST 24 251359844 ps
T1020 /workspace/coverage/cover_reg_top/26.keymgr_intr_test.4278094864 Mar 05 01:44:34 PM PST 24 Mar 05 01:44:36 PM PST 24 23633617 ps
T1021 /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.2681600772 Mar 05 01:44:06 PM PST 24 Mar 05 01:44:15 PM PST 24 371984867 ps
T152 /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.417193951 Mar 05 01:44:31 PM PST 24 Mar 05 01:44:49 PM PST 24 5772480591 ps
T1022 /workspace/coverage/cover_reg_top/11.keymgr_intr_test.1652993333 Mar 05 01:44:21 PM PST 24 Mar 05 01:44:22 PM PST 24 16849469 ps
T1023 /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.3895530159 Mar 05 01:44:21 PM PST 24 Mar 05 01:44:23 PM PST 24 179236565 ps
T1024 /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.461244478 Mar 05 01:44:20 PM PST 24 Mar 05 01:44:22 PM PST 24 65155784 ps
T1025 /workspace/coverage/cover_reg_top/20.keymgr_intr_test.681006531 Mar 05 01:44:33 PM PST 24 Mar 05 01:44:34 PM PST 24 42420357 ps
T140 /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.2135793852 Mar 05 01:44:26 PM PST 24 Mar 05 01:44:35 PM PST 24 335825391 ps
T1026 /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.2252666333 Mar 05 01:44:12 PM PST 24 Mar 05 01:44:17 PM PST 24 718280201 ps
T1027 /workspace/coverage/cover_reg_top/31.keymgr_intr_test.720396248 Mar 05 01:44:36 PM PST 24 Mar 05 01:44:37 PM PST 24 15607748 ps
T1028 /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.2746249105 Mar 05 01:44:22 PM PST 24 Mar 05 01:44:26 PM PST 24 180203530 ps
T1029 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.3426587177 Mar 05 01:44:14 PM PST 24 Mar 05 01:44:18 PM PST 24 94948068 ps
T1030 /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.419616726 Mar 05 01:44:12 PM PST 24 Mar 05 01:44:13 PM PST 24 41404846 ps
T1031 /workspace/coverage/cover_reg_top/10.keymgr_intr_test.2679505849 Mar 05 01:44:18 PM PST 24 Mar 05 01:44:19 PM PST 24 39966139 ps
T161 /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.2702993535 Mar 05 01:44:22 PM PST 24 Mar 05 01:44:28 PM PST 24 232072018 ps
T1032 /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.3851413623 Mar 05 01:44:22 PM PST 24 Mar 05 01:44:24 PM PST 24 164257313 ps
T1033 /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.787379802 Mar 05 01:44:06 PM PST 24 Mar 05 01:44:07 PM PST 24 44571577 ps
T1034 /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.3891459573 Mar 05 01:44:12 PM PST 24 Mar 05 01:44:14 PM PST 24 24840169 ps
T1035 /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.2416899187 Mar 05 01:44:27 PM PST 24 Mar 05 01:44:29 PM PST 24 24007930 ps
T1036 /workspace/coverage/cover_reg_top/3.keymgr_intr_test.960933610 Mar 05 01:44:05 PM PST 24 Mar 05 01:44:06 PM PST 24 125979314 ps
T1037 /workspace/coverage/cover_reg_top/37.keymgr_intr_test.2931889053 Mar 05 01:44:33 PM PST 24 Mar 05 01:44:35 PM PST 24 29663438 ps
T1038 /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.1337003147 Mar 05 01:44:03 PM PST 24 Mar 05 01:44:05 PM PST 24 74168796 ps
T1039 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.2909505033 Mar 05 01:44:24 PM PST 24 Mar 05 01:44:29 PM PST 24 171845835 ps
T1040 /workspace/coverage/cover_reg_top/35.keymgr_intr_test.1068797705 Mar 05 01:44:33 PM PST 24 Mar 05 01:44:35 PM PST 24 29568217 ps
T1041 /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.4187961972 Mar 05 01:44:14 PM PST 24 Mar 05 01:44:16 PM PST 24 23389438 ps
T1042 /workspace/coverage/cover_reg_top/21.keymgr_intr_test.1031531927 Mar 05 01:44:27 PM PST 24 Mar 05 01:44:28 PM PST 24 155808088 ps
T1043 /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.2781049599 Mar 05 01:44:22 PM PST 24 Mar 05 01:44:25 PM PST 24 171379647 ps
T1044 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.2650569958 Mar 05 01:44:25 PM PST 24 Mar 05 01:44:30 PM PST 24 192376706 ps
T1045 /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.304756318 Mar 05 01:44:14 PM PST 24 Mar 05 01:44:16 PM PST 24 51433065 ps
T1046 /workspace/coverage/cover_reg_top/45.keymgr_intr_test.1816869590 Mar 05 01:44:39 PM PST 24 Mar 05 01:44:41 PM PST 24 80211827 ps
T1047 /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.2854157620 Mar 05 01:44:01 PM PST 24 Mar 05 01:44:03 PM PST 24 30267448 ps
T1048 /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.1718269549 Mar 05 01:44:23 PM PST 24 Mar 05 01:44:25 PM PST 24 112347850 ps
T1049 /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.2752525373 Mar 05 01:44:15 PM PST 24 Mar 05 01:44:16 PM PST 24 17489950 ps
T1050 /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.2152062460 Mar 05 01:44:33 PM PST 24 Mar 05 01:44:34 PM PST 24 57649668 ps
T1051 /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.1977962349 Mar 05 01:44:22 PM PST 24 Mar 05 01:44:25 PM PST 24 169462762 ps
T1052 /workspace/coverage/cover_reg_top/39.keymgr_intr_test.2279539423 Mar 05 01:44:39 PM PST 24 Mar 05 01:44:41 PM PST 24 10343973 ps
T1053 /workspace/coverage/cover_reg_top/1.keymgr_intr_test.1301216168 Mar 05 01:44:03 PM PST 24 Mar 05 01:44:04 PM PST 24 11397558 ps
T1054 /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.3297820568 Mar 05 01:44:25 PM PST 24 Mar 05 01:44:29 PM PST 24 93248440 ps
T1055 /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.2536857331 Mar 05 01:44:24 PM PST 24 Mar 05 01:44:26 PM PST 24 69244792 ps
T1056 /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.708346963 Mar 05 01:44:00 PM PST 24 Mar 05 01:44:02 PM PST 24 232417114 ps
T1057 /workspace/coverage/cover_reg_top/13.keymgr_intr_test.1380702041 Mar 05 01:44:24 PM PST 24 Mar 05 01:44:25 PM PST 24 10374234 ps
T1058 /workspace/coverage/cover_reg_top/33.keymgr_intr_test.2405131738 Mar 05 01:44:33 PM PST 24 Mar 05 01:44:34 PM PST 24 23382523 ps
T1059 /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.2248129504 Mar 05 01:44:30 PM PST 24 Mar 05 01:44:34 PM PST 24 150962458 ps
T1060 /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.500016599 Mar 05 01:44:22 PM PST 24 Mar 05 01:44:24 PM PST 24 29059923 ps
T1061 /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.3468281732 Mar 05 01:44:12 PM PST 24 Mar 05 01:44:14 PM PST 24 99899604 ps
T1062 /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.2759158475 Mar 05 01:44:22 PM PST 24 Mar 05 01:44:23 PM PST 24 73915546 ps
T1063 /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.2049983058 Mar 05 01:44:22 PM PST 24 Mar 05 01:44:25 PM PST 24 35557171 ps
T1064 /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.282286053 Mar 05 01:44:06 PM PST 24 Mar 05 01:44:16 PM PST 24 1502575898 ps
T1065 /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.3821772004 Mar 05 01:44:01 PM PST 24 Mar 05 01:44:05 PM PST 24 365376025 ps
T1066 /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.745633210 Mar 05 01:44:20 PM PST 24 Mar 05 01:44:21 PM PST 24 18568554 ps
T1067 /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.4007589662 Mar 05 01:44:10 PM PST 24 Mar 05 01:44:11 PM PST 24 100896633 ps
T1068 /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.3584917133 Mar 05 01:44:15 PM PST 24 Mar 05 01:44:18 PM PST 24 161105166 ps
T1069 /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.385661789 Mar 05 01:44:19 PM PST 24 Mar 05 01:44:23 PM PST 24 326649549 ps
T1070 /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.1004807101 Mar 05 01:44:32 PM PST 24 Mar 05 01:44:34 PM PST 24 36183363 ps
T1071 /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.3978105195 Mar 05 01:44:27 PM PST 24 Mar 05 01:44:33 PM PST 24 207346558 ps
T1072 /workspace/coverage/cover_reg_top/16.keymgr_intr_test.2632946734 Mar 05 01:44:29 PM PST 24 Mar 05 01:44:30 PM PST 24 64870546 ps
T1073 /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.3456179601 Mar 05 01:44:03 PM PST 24 Mar 05 01:44:05 PM PST 24 895593528 ps
T1074 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.1144330057 Mar 05 01:44:28 PM PST 24 Mar 05 01:44:33 PM PST 24 106259277 ps
T1075 /workspace/coverage/cover_reg_top/44.keymgr_intr_test.2362274913 Mar 05 01:44:39 PM PST 24 Mar 05 01:44:41 PM PST 24 9736423 ps

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.364999293
Short name T4
Test name
Test status
Simulation time 262037562 ps
CPU time 7.62 seconds
Started Mar 05 01:21:06 PM PST 24
Finished Mar 05 01:21:14 PM PST 24
Peak memory 214060 kb
Host smart-44a3ffd4-0db9-4c92-9d0f-af0bec53a2a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364999293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.364999293
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.2041213935
Short name T41
Test name
Test status
Simulation time 1651248342 ps
CPU time 24.44 seconds
Started Mar 05 01:19:26 PM PST 24
Finished Mar 05 01:19:51 PM PST 24
Peak memory 214596 kb
Host smart-73476cf6-d9e1-4585-a28c-0ba5e40dd0d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041213935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.2041213935
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.1293098110
Short name T15
Test name
Test status
Simulation time 47386935 ps
CPU time 3.52 seconds
Started Mar 05 01:19:39 PM PST 24
Finished Mar 05 01:19:43 PM PST 24
Peak memory 214252 kb
Host smart-3021fe6c-8b49-4c8d-b90b-b57b6929d769
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1293098110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.1293098110
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.968140957
Short name T6
Test name
Test status
Simulation time 5300013982 ps
CPU time 28.97 seconds
Started Mar 05 01:19:53 PM PST 24
Finished Mar 05 01:20:23 PM PST 24
Peak memory 222516 kb
Host smart-d0114393-b692-4d81-bafd-eda85c8287b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=968140957 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.968140957
Directory /workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.497131775
Short name T5
Test name
Test status
Simulation time 87819804726 ps
CPU time 215.73 seconds
Started Mar 05 01:19:16 PM PST 24
Finished Mar 05 01:22:53 PM PST 24
Peak memory 272764 kb
Host smart-ebadebd8-96bd-48da-93dc-183613510ff6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497131775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.497131775
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.3523283307
Short name T101
Test name
Test status
Simulation time 438695692 ps
CPU time 19.74 seconds
Started Mar 05 01:21:27 PM PST 24
Finished Mar 05 01:21:47 PM PST 24
Peak memory 215296 kb
Host smart-52ac6f97-aca6-41f2-9756-330ff9c50b7a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3523283307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.3523283307
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.1184789360
Short name T8
Test name
Test status
Simulation time 63000362 ps
CPU time 4.13 seconds
Started Mar 05 01:19:32 PM PST 24
Finished Mar 05 01:19:38 PM PST 24
Peak memory 209600 kb
Host smart-b28fef2f-9d00-40c1-935c-a02f3e85849c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1184789360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.1184789360
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.2893668987
Short name T42
Test name
Test status
Simulation time 10106310054 ps
CPU time 52.06 seconds
Started Mar 05 01:20:46 PM PST 24
Finished Mar 05 01:21:39 PM PST 24
Peak memory 214792 kb
Host smart-6326ae70-33dc-43a3-92c8-b546dd0418a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893668987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.2893668987
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.1308050271
Short name T130
Test name
Test status
Simulation time 1760235518 ps
CPU time 33.88 seconds
Started Mar 05 01:19:59 PM PST 24
Finished Mar 05 01:20:33 PM PST 24
Peak memory 217236 kb
Host smart-6783fc4b-4289-43a0-88d9-ef6dc1f9eb96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1308050271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.1308050271
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.1660817328
Short name T105
Test name
Test status
Simulation time 234215724 ps
CPU time 5.51 seconds
Started Mar 05 01:44:09 PM PST 24
Finished Mar 05 01:44:15 PM PST 24
Peak memory 214548 kb
Host smart-f94d1bd7-2eea-4c8d-a81b-e819fb6faecb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1660817328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.1660817328
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.275807691
Short name T22
Test name
Test status
Simulation time 2344334650 ps
CPU time 53.5 seconds
Started Mar 05 01:19:46 PM PST 24
Finished Mar 05 01:20:40 PM PST 24
Peak memory 220548 kb
Host smart-fc949772-78a9-48d0-8442-ac1926408cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=275807691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.275807691
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.2806568216
Short name T49
Test name
Test status
Simulation time 10379941447 ps
CPU time 137.68 seconds
Started Mar 05 01:21:00 PM PST 24
Finished Mar 05 01:23:18 PM PST 24
Peak memory 222332 kb
Host smart-69b7c1cb-6fc9-47e4-a36c-4359add8da09
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2806568216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.2806568216
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.338905998
Short name T128
Test name
Test status
Simulation time 303234932 ps
CPU time 16.41 seconds
Started Mar 05 01:20:08 PM PST 24
Finished Mar 05 01:20:25 PM PST 24
Peak memory 214788 kb
Host smart-fcb3d666-e788-4f9d-9b8a-b286a2149c0f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=338905998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.338905998
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.1377842908
Short name T285
Test name
Test status
Simulation time 4720715033 ps
CPU time 43.45 seconds
Started Mar 05 01:20:07 PM PST 24
Finished Mar 05 01:20:51 PM PST 24
Peak memory 222312 kb
Host smart-9fcf665c-69f4-4e7e-a8d9-526b1a46aa89
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1377842908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.1377842908
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.1551613107
Short name T46
Test name
Test status
Simulation time 2823898260 ps
CPU time 28.75 seconds
Started Mar 05 01:20:52 PM PST 24
Finished Mar 05 01:21:21 PM PST 24
Peak memory 217000 kb
Host smart-5213b563-fecc-4e50-b0cd-cf1687fb0bf5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551613107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.1551613107
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.1302918638
Short name T299
Test name
Test status
Simulation time 4082090102 ps
CPU time 49.25 seconds
Started Mar 05 01:20:06 PM PST 24
Finished Mar 05 01:20:55 PM PST 24
Peak memory 216416 kb
Host smart-667dd2f1-dd9f-4ab7-a543-044de65bfe95
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1302918638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.1302918638
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_stress_all_with_rand_reset.120910706
Short name T58
Test name
Test status
Simulation time 279564245 ps
CPU time 16.22 seconds
Started Mar 05 01:19:16 PM PST 24
Finished Mar 05 01:19:33 PM PST 24
Peak memory 222424 kb
Host smart-ce30b3d6-27b0-47bb-9ad9-a80aea945d37
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120910706 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all_with_rand_reset.120910706
Directory /workspace/3.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.2308727935
Short name T27
Test name
Test status
Simulation time 653082073 ps
CPU time 3.72 seconds
Started Mar 05 01:20:43 PM PST 24
Finished Mar 05 01:20:48 PM PST 24
Peak memory 219676 kb
Host smart-183609cf-9c61-45a9-9bee-9ea9fd11cd1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2308727935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.2308727935
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.978924656
Short name T409
Test name
Test status
Simulation time 1095340617 ps
CPU time 48.99 seconds
Started Mar 05 01:20:56 PM PST 24
Finished Mar 05 01:21:46 PM PST 24
Peak memory 214148 kb
Host smart-c1e430fa-8c1b-46b9-b329-6281f625e42d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=978924656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.978924656
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.1089330782
Short name T110
Test name
Test status
Simulation time 917213693 ps
CPU time 4.04 seconds
Started Mar 05 01:44:09 PM PST 24
Finished Mar 05 01:44:13 PM PST 24
Peak memory 214448 kb
Host smart-1a1c20c4-9c17-4abf-9156-f668cf2d0006
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1089330782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.1089330782
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.1553932452
Short name T72
Test name
Test status
Simulation time 670811431 ps
CPU time 30.56 seconds
Started Mar 05 01:20:46 PM PST 24
Finished Mar 05 01:21:17 PM PST 24
Peak memory 216248 kb
Host smart-ccb2702f-5709-413f-8254-942e1147170e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1553932452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.1553932452
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.4046863556
Short name T131
Test name
Test status
Simulation time 1011750754 ps
CPU time 55.38 seconds
Started Mar 05 01:19:54 PM PST 24
Finished Mar 05 01:20:50 PM PST 24
Peak memory 215068 kb
Host smart-e6f5d9c6-f121-4104-af15-f82c227ab6e2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4046863556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.4046863556
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.1620648172
Short name T425
Test name
Test status
Simulation time 4445561462 ps
CPU time 54.46 seconds
Started Mar 05 01:19:20 PM PST 24
Finished Mar 05 01:20:15 PM PST 24
Peak memory 214092 kb
Host smart-2a2c7cff-1c99-47c6-b0b9-732c5c1b8090
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1620648172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.1620648172
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.3288098264
Short name T36
Test name
Test status
Simulation time 225388449 ps
CPU time 3.61 seconds
Started Mar 05 01:19:52 PM PST 24
Finished Mar 05 01:19:57 PM PST 24
Peak memory 214140 kb
Host smart-c3b2139f-2a32-43e1-bbb5-06135497465f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288098264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.3288098264
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.1263338553
Short name T219
Test name
Test status
Simulation time 761355345 ps
CPU time 20.93 seconds
Started Mar 05 01:20:39 PM PST 24
Finished Mar 05 01:21:00 PM PST 24
Peak memory 222272 kb
Host smart-85037456-afbb-4a31-87ea-7a90b3b2314a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263338553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.1263338553
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.408869060
Short name T20
Test name
Test status
Simulation time 211250388 ps
CPU time 7.68 seconds
Started Mar 05 01:19:58 PM PST 24
Finished Mar 05 01:20:06 PM PST 24
Peak memory 214152 kb
Host smart-10bd48f3-e226-44e3-afad-dbdce03bed4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408869060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.408869060
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.933309535
Short name T430
Test name
Test status
Simulation time 60889180 ps
CPU time 0.95 seconds
Started Mar 05 01:19:14 PM PST 24
Finished Mar 05 01:19:15 PM PST 24
Peak memory 205896 kb
Host smart-f4aca97d-6d83-4bee-890a-c3a6a7fffc1d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=933309535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.933309535
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.4220568241
Short name T211
Test name
Test status
Simulation time 1308706343 ps
CPU time 51.63 seconds
Started Mar 05 01:20:52 PM PST 24
Finished Mar 05 01:21:44 PM PST 24
Peak memory 216248 kb
Host smart-a43432dd-54a7-4a9f-a752-e7401974ba3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4220568241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.4220568241
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.2724730505
Short name T33
Test name
Test status
Simulation time 57262777 ps
CPU time 2.12 seconds
Started Mar 05 01:19:49 PM PST 24
Finished Mar 05 01:19:52 PM PST 24
Peak memory 209880 kb
Host smart-b80b4fd0-c8ae-463b-99f6-a7c754743eaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724730505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.2724730505
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.952350266
Short name T184
Test name
Test status
Simulation time 79083845 ps
CPU time 2.91 seconds
Started Mar 05 01:19:49 PM PST 24
Finished Mar 05 01:19:52 PM PST 24
Peak memory 222284 kb
Host smart-cd2457b0-8ca4-4ee4-ab50-79e05c3b6c0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952350266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.952350266
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.156266511
Short name T121
Test name
Test status
Simulation time 392530966 ps
CPU time 3.66 seconds
Started Mar 05 01:20:50 PM PST 24
Finished Mar 05 01:20:54 PM PST 24
Peak memory 214076 kb
Host smart-395a728b-436a-417f-ba2a-f7ab905d8c52
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=156266511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.156266511
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.2342427653
Short name T178
Test name
Test status
Simulation time 7588931951 ps
CPU time 58.02 seconds
Started Mar 05 01:19:15 PM PST 24
Finished Mar 05 01:20:13 PM PST 24
Peak memory 215960 kb
Host smart-db03b061-d86a-44ff-b89a-0532efcffdb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342427653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.2342427653
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.2465872377
Short name T301
Test name
Test status
Simulation time 468884088 ps
CPU time 6.63 seconds
Started Mar 05 01:19:44 PM PST 24
Finished Mar 05 01:19:51 PM PST 24
Peak memory 214668 kb
Host smart-7fe15216-a7fb-4714-9d8d-eab5fbf5fe80
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2465872377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.2465872377
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.584566087
Short name T67
Test name
Test status
Simulation time 100419786 ps
CPU time 4.75 seconds
Started Mar 05 01:21:09 PM PST 24
Finished Mar 05 01:21:14 PM PST 24
Peak memory 218008 kb
Host smart-89edb016-0bad-447b-bdf3-fd2c2f22318f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584566087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.584566087
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.3947132809
Short name T19
Test name
Test status
Simulation time 75503515 ps
CPU time 2.88 seconds
Started Mar 05 01:20:13 PM PST 24
Finished Mar 05 01:20:16 PM PST 24
Peak memory 218600 kb
Host smart-e9942217-2bc7-43c1-b1e2-db11552424b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3947132809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.3947132809
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_stress_all_with_rand_reset.1686197466
Short name T115
Test name
Test status
Simulation time 255081756 ps
CPU time 7.92 seconds
Started Mar 05 01:19:15 PM PST 24
Finished Mar 05 01:19:23 PM PST 24
Peak memory 219828 kb
Host smart-45f7faf3-2774-4316-8be1-ec3660ccb2b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1686197466 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all_with_rand_reset.1686197466
Directory /workspace/4.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.4148761217
Short name T77
Test name
Test status
Simulation time 3220955348 ps
CPU time 61.65 seconds
Started Mar 05 01:21:23 PM PST 24
Finished Mar 05 01:22:25 PM PST 24
Peak memory 222276 kb
Host smart-8c9bcfeb-bcae-4005-b44c-17d5a4bee4dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148761217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.4148761217
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.2183250559
Short name T151
Test name
Test status
Simulation time 3097616349 ps
CPU time 34.34 seconds
Started Mar 05 01:44:12 PM PST 24
Finished Mar 05 01:44:47 PM PST 24
Peak memory 212840 kb
Host smart-c0419798-0cc8-46ea-a444-964e044e0ccd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183250559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err
.2183250559
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.1624499885
Short name T408
Test name
Test status
Simulation time 214866564 ps
CPU time 10.71 seconds
Started Mar 05 01:20:53 PM PST 24
Finished Mar 05 01:21:04 PM PST 24
Peak memory 215124 kb
Host smart-4921862e-f857-42bb-b10c-7ec708d8f75c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1624499885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.1624499885
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.3548018436
Short name T145
Test name
Test status
Simulation time 400335268 ps
CPU time 6.22 seconds
Started Mar 05 01:44:05 PM PST 24
Finished Mar 05 01:44:12 PM PST 24
Peak memory 209604 kb
Host smart-64e0b76e-627d-4830-b590-cedf3959d779
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548018436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.3548018436
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.560022249
Short name T221
Test name
Test status
Simulation time 41914384497 ps
CPU time 245.27 seconds
Started Mar 05 01:20:10 PM PST 24
Finished Mar 05 01:24:15 PM PST 24
Peak memory 222400 kb
Host smart-0da987bd-6641-4ca2-b796-46a9363ec852
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560022249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.560022249
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.1467373358
Short name T208
Test name
Test status
Simulation time 3720628299 ps
CPU time 37.15 seconds
Started Mar 05 01:19:18 PM PST 24
Finished Mar 05 01:19:56 PM PST 24
Peak memory 215960 kb
Host smart-5dbcbf3c-d941-48b9-8a4a-7a6a98ddb8db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467373358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.1467373358
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.3262361491
Short name T44
Test name
Test status
Simulation time 768004765 ps
CPU time 26.87 seconds
Started Mar 05 01:19:52 PM PST 24
Finished Mar 05 01:20:19 PM PST 24
Peak memory 216340 kb
Host smart-bcead318-32cc-492c-9941-b90b92da2f0f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3262361491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.3262361491
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.643829978
Short name T325
Test name
Test status
Simulation time 265452679 ps
CPU time 14.29 seconds
Started Mar 05 01:20:54 PM PST 24
Finished Mar 05 01:21:08 PM PST 24
Peak memory 215208 kb
Host smart-de62d610-d8c0-45ae-aa24-7be0426d05ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=643829978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.643829978
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.2036212185
Short name T238
Test name
Test status
Simulation time 1013992922 ps
CPU time 5.66 seconds
Started Mar 05 01:20:04 PM PST 24
Finished Mar 05 01:20:10 PM PST 24
Peak memory 214080 kb
Host smart-260b6b34-6dd3-47a2-aa98-1f9b7d12f3bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036212185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.2036212185
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.3294892987
Short name T108
Test name
Test status
Simulation time 1476417635 ps
CPU time 5.76 seconds
Started Mar 05 01:44:20 PM PST 24
Finished Mar 05 01:44:26 PM PST 24
Peak memory 214524 kb
Host smart-455eba50-72e6-48e1-bbd2-328e2cfd8590
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294892987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.3294892987
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.1031725526
Short name T3
Test name
Test status
Simulation time 64487676 ps
CPU time 3.16 seconds
Started Mar 05 01:19:49 PM PST 24
Finished Mar 05 01:19:52 PM PST 24
Peak memory 206552 kb
Host smart-fd3e9dd9-9571-4568-a235-d758a7b07898
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031725526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.1031725526
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.2957622272
Short name T232
Test name
Test status
Simulation time 1347526202 ps
CPU time 16.65 seconds
Started Mar 05 01:20:04 PM PST 24
Finished Mar 05 01:20:20 PM PST 24
Peak memory 222180 kb
Host smart-a78a81f7-9bd8-45e0-9de6-551929e2a935
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2957622272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.2957622272
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.435382838
Short name T322
Test name
Test status
Simulation time 65384757 ps
CPU time 4.13 seconds
Started Mar 05 01:20:30 PM PST 24
Finished Mar 05 01:20:34 PM PST 24
Peak memory 222180 kb
Host smart-1a9143fa-8135-4bed-8e0d-11c297f27043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435382838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.435382838
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.913349538
Short name T224
Test name
Test status
Simulation time 52553038 ps
CPU time 4 seconds
Started Mar 05 01:21:05 PM PST 24
Finished Mar 05 01:21:09 PM PST 24
Peak memory 214148 kb
Host smart-92ca9a68-0ce5-4e5d-80c7-ea966a267fb7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=913349538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.913349538
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.2135793852
Short name T140
Test name
Test status
Simulation time 335825391 ps
CPU time 8.38 seconds
Started Mar 05 01:44:26 PM PST 24
Finished Mar 05 01:44:35 PM PST 24
Peak memory 209604 kb
Host smart-71078b12-4e3b-4b67-9903-f9021b80a09c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2135793852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.2135793852
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.1515058782
Short name T160
Test name
Test status
Simulation time 146880046 ps
CPU time 2.09 seconds
Started Mar 05 01:19:59 PM PST 24
Finished Mar 05 01:20:01 PM PST 24
Peak memory 209528 kb
Host smart-7d99cf3f-2d9f-45a6-bb12-0a58ffe3d8dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515058782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.1515058782
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.3482752864
Short name T162
Test name
Test status
Simulation time 93496587 ps
CPU time 4.38 seconds
Started Mar 05 01:19:51 PM PST 24
Finished Mar 05 01:19:56 PM PST 24
Peak memory 217760 kb
Host smart-8e303677-570d-4441-9170-4b62e9989a48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482752864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.3482752864
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.1369459139
Short name T237
Test name
Test status
Simulation time 616145929 ps
CPU time 5.97 seconds
Started Mar 05 01:19:42 PM PST 24
Finished Mar 05 01:19:48 PM PST 24
Peak memory 213940 kb
Host smart-db84f312-0400-4975-a48d-0cce0e5e4302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369459139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.1369459139
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.2297388733
Short name T61
Test name
Test status
Simulation time 600049062 ps
CPU time 14.88 seconds
Started Mar 05 01:20:33 PM PST 24
Finished Mar 05 01:20:48 PM PST 24
Peak memory 220256 kb
Host smart-dae38f11-0e91-4dee-a5dc-fc26de7e310d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297388733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.2297388733
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.3481423034
Short name T344
Test name
Test status
Simulation time 304869768 ps
CPU time 6.36 seconds
Started Mar 05 01:20:54 PM PST 24
Finished Mar 05 01:21:00 PM PST 24
Peak memory 220416 kb
Host smart-54ce9948-d483-4f37-bb2c-73516acb04fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481423034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.3481423034
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.781479597
Short name T89
Test name
Test status
Simulation time 566891267 ps
CPU time 4.89 seconds
Started Mar 05 01:21:04 PM PST 24
Finished Mar 05 01:21:09 PM PST 24
Peak memory 220976 kb
Host smart-8d29c9c7-5d3f-4c55-862b-eb19e2008fb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781479597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.781479597
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.852973676
Short name T327
Test name
Test status
Simulation time 1770765336 ps
CPU time 8.1 seconds
Started Mar 05 01:19:15 PM PST 24
Finished Mar 05 01:19:23 PM PST 24
Peak memory 214228 kb
Host smart-81ae35e3-20e2-4334-a10a-f92870f23c22
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=852973676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.852973676
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.935372433
Short name T163
Test name
Test status
Simulation time 130739499 ps
CPU time 6.56 seconds
Started Mar 05 01:20:55 PM PST 24
Finished Mar 05 01:21:02 PM PST 24
Peak memory 217516 kb
Host smart-0029bc77-10f9-4bfc-ba57-daa0f4e4463d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935372433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.935372433
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.3661619653
Short name T147
Test name
Test status
Simulation time 320251941 ps
CPU time 8.03 seconds
Started Mar 05 01:44:24 PM PST 24
Finished Mar 05 01:44:32 PM PST 24
Peak memory 209264 kb
Host smart-c2a9877d-cbe4-469b-8eec-fbc19ecfb92b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3661619653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.3661619653
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.3495509907
Short name T141
Test name
Test status
Simulation time 198760812 ps
CPU time 6.2 seconds
Started Mar 05 01:44:28 PM PST 24
Finished Mar 05 01:44:35 PM PST 24
Peak memory 214208 kb
Host smart-e2b462e3-d1b4-4d26-b9c5-09718d06adc7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495509907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.3495509907
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.417193951
Short name T152
Test name
Test status
Simulation time 5772480591 ps
CPU time 17.98 seconds
Started Mar 05 01:44:31 PM PST 24
Finished Mar 05 01:44:49 PM PST 24
Peak memory 214400 kb
Host smart-13f87336-d906-443b-8b1a-f9494437f885
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=417193951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_err
.417193951
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.3568063254
Short name T827
Test name
Test status
Simulation time 3811040729 ps
CPU time 44.75 seconds
Started Mar 05 01:19:10 PM PST 24
Finished Mar 05 01:19:55 PM PST 24
Peak memory 216124 kb
Host smart-5902f4ec-89b4-4a31-a5d0-c80aaa260ca2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568063254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.3568063254
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.823499385
Short name T278
Test name
Test status
Simulation time 680425541 ps
CPU time 6.9 seconds
Started Mar 05 01:19:56 PM PST 24
Finished Mar 05 01:20:03 PM PST 24
Peak memory 222252 kb
Host smart-960bd9ed-f1c0-42f2-8404-ed15cf61e3f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=823499385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.823499385
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.3896766482
Short name T263
Test name
Test status
Simulation time 143089598 ps
CPU time 3.4 seconds
Started Mar 05 01:19:58 PM PST 24
Finished Mar 05 01:20:02 PM PST 24
Peak memory 208108 kb
Host smart-4de38500-0bfa-4f54-8ed4-4e75e3653770
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3896766482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.3896766482
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.693481655
Short name T336
Test name
Test status
Simulation time 503890700 ps
CPU time 6.48 seconds
Started Mar 05 01:20:15 PM PST 24
Finished Mar 05 01:20:22 PM PST 24
Peak memory 214100 kb
Host smart-5898e092-5929-477e-8050-d12c13bce967
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=693481655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.693481655
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.754079617
Short name T396
Test name
Test status
Simulation time 78027481 ps
CPU time 2.91 seconds
Started Mar 05 01:20:25 PM PST 24
Finished Mar 05 01:20:28 PM PST 24
Peak memory 209704 kb
Host smart-8714c204-9bdb-4f78-8fac-b51a03eaccf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754079617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.754079617
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.3382534132
Short name T268
Test name
Test status
Simulation time 6519077743 ps
CPU time 44.39 seconds
Started Mar 05 01:21:06 PM PST 24
Finished Mar 05 01:21:51 PM PST 24
Peak memory 210228 kb
Host smart-bc8801b8-b538-4a06-8e34-047d1caba9dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3382534132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.3382534132
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_stress_all_with_rand_reset.3956652685
Short name T125
Test name
Test status
Simulation time 365645360 ps
CPU time 14.89 seconds
Started Mar 05 01:21:01 PM PST 24
Finished Mar 05 01:21:16 PM PST 24
Peak memory 219940 kb
Host smart-605d58b3-522f-49ac-91c9-a4fd86b7639f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3956652685 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all_with_rand_reset.3956652685
Directory /workspace/42.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.2539425545
Short name T164
Test name
Test status
Simulation time 424419661 ps
CPU time 4.43 seconds
Started Mar 05 01:20:00 PM PST 24
Finished Mar 05 01:20:04 PM PST 24
Peak memory 217492 kb
Host smart-7ba49375-92b9-4c78-9973-bb8ddf8b530f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539425545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.2539425545
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.3124639482
Short name T317
Test name
Test status
Simulation time 160168300 ps
CPU time 6.91 seconds
Started Mar 05 01:20:18 PM PST 24
Finished Mar 05 01:20:25 PM PST 24
Peak memory 222232 kb
Host smart-e6065700-3cf7-4e10-87fe-6a4937331902
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124639482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.3124639482
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.2073099755
Short name T419
Test name
Test status
Simulation time 88052096 ps
CPU time 4.95 seconds
Started Mar 05 01:20:29 PM PST 24
Finished Mar 05 01:20:34 PM PST 24
Peak memory 214216 kb
Host smart-8ce18afc-a364-4295-876a-b02a13fa9a68
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2073099755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.2073099755
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.888265278
Short name T421
Test name
Test status
Simulation time 48105223 ps
CPU time 3.6 seconds
Started Mar 05 01:20:35 PM PST 24
Finished Mar 05 01:20:39 PM PST 24
Peak memory 214148 kb
Host smart-7d186e22-a31c-46b3-8669-8a4f7016fc1a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=888265278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.888265278
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.1395215373
Short name T95
Test name
Test status
Simulation time 173626284 ps
CPU time 2.97 seconds
Started Mar 05 01:20:44 PM PST 24
Finished Mar 05 01:20:48 PM PST 24
Peak memory 208776 kb
Host smart-f0d10582-c0c3-4297-b045-4d3d1aa57b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395215373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.1395215373
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.725644541
Short name T2
Test name
Test status
Simulation time 336505073 ps
CPU time 4.71 seconds
Started Mar 05 01:19:20 PM PST 24
Finished Mar 05 01:19:26 PM PST 24
Peak memory 207124 kb
Host smart-48e57224-02a5-4f3d-85f6-8bf8019addb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725644541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.725644541
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.1018515571
Short name T354
Test name
Test status
Simulation time 5381852142 ps
CPU time 71.19 seconds
Started Mar 05 01:19:42 PM PST 24
Finished Mar 05 01:20:53 PM PST 24
Peak memory 223760 kb
Host smart-18601aff-3b24-4148-8e45-8766d77f8bf3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018515571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.1018515571
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.2044025213
Short name T148
Test name
Test status
Simulation time 624810193 ps
CPU time 8.82 seconds
Started Mar 05 01:44:24 PM PST 24
Finished Mar 05 01:44:33 PM PST 24
Peak memory 209192 kb
Host smart-d046a7a2-6459-4dcb-9ed1-4603ec5128c6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044025213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er
r.2044025213
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.207649514
Short name T1013
Test name
Test status
Simulation time 155847061 ps
CPU time 6.66 seconds
Started Mar 05 01:44:23 PM PST 24
Finished Mar 05 01:44:30 PM PST 24
Peak memory 209304 kb
Host smart-2973b75b-574d-4d17-9993-28e0c352bd4f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207649514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_err
.207649514
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.2425946141
Short name T165
Test name
Test status
Simulation time 154449178 ps
CPU time 5.6 seconds
Started Mar 05 01:20:46 PM PST 24
Finished Mar 05 01:20:52 PM PST 24
Peak memory 222472 kb
Host smart-c3b6f49c-a374-45e9-94f1-25ef20e188a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425946141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.2425946141
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.782069700
Short name T758
Test name
Test status
Simulation time 1059783331 ps
CPU time 6.62 seconds
Started Mar 05 01:19:12 PM PST 24
Finished Mar 05 01:19:19 PM PST 24
Peak memory 214052 kb
Host smart-0b67da96-6a5d-4974-903f-052c078f60b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782069700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.782069700
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.243867217
Short name T363
Test name
Test status
Simulation time 301046958 ps
CPU time 15.21 seconds
Started Mar 05 01:19:16 PM PST 24
Finished Mar 05 01:19:32 PM PST 24
Peak memory 214436 kb
Host smart-b54d3ebc-028f-4188-a1c6-3a3181682714
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243867217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.243867217
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.1710509985
Short name T699
Test name
Test status
Simulation time 33129538 ps
CPU time 2.06 seconds
Started Mar 05 01:19:02 PM PST 24
Finished Mar 05 01:19:06 PM PST 24
Peak memory 209792 kb
Host smart-70623a8f-391f-4192-a7b1-19b6595997cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1710509985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.1710509985
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.2154451089
Short name T255
Test name
Test status
Simulation time 1655253608 ps
CPU time 28.48 seconds
Started Mar 05 01:19:48 PM PST 24
Finished Mar 05 01:20:17 PM PST 24
Peak memory 213956 kb
Host smart-1fbe713b-8d55-44f0-b60d-4e750d7e7cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154451089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.2154451089
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.1641754622
Short name T73
Test name
Test status
Simulation time 46223457 ps
CPU time 2.85 seconds
Started Mar 05 01:19:40 PM PST 24
Finished Mar 05 01:19:44 PM PST 24
Peak memory 210156 kb
Host smart-15b5b79c-5c26-4a3b-9ce0-9b0bc3df9c9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641754622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.1641754622
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.4077446979
Short name T457
Test name
Test status
Simulation time 400505193 ps
CPU time 5.62 seconds
Started Mar 05 01:19:49 PM PST 24
Finished Mar 05 01:19:54 PM PST 24
Peak memory 207400 kb
Host smart-621298ef-0f30-4a9b-8a4c-419c3598b486
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077446979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.4077446979
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.1262248129
Short name T369
Test name
Test status
Simulation time 885626430 ps
CPU time 9.33 seconds
Started Mar 05 01:19:58 PM PST 24
Finished Mar 05 01:20:08 PM PST 24
Peak memory 211116 kb
Host smart-3e20e494-796f-4db9-ae5d-bde8cc75c5e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1262248129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.1262248129
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.840713278
Short name T179
Test name
Test status
Simulation time 963455549 ps
CPU time 23.16 seconds
Started Mar 05 01:19:55 PM PST 24
Finished Mar 05 01:20:18 PM PST 24
Peak memory 222376 kb
Host smart-022120e9-11fd-40e7-898f-17ed88abc45c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840713278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.840713278
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.3663300433
Short name T199
Test name
Test status
Simulation time 210256095 ps
CPU time 2.45 seconds
Started Mar 05 01:19:53 PM PST 24
Finished Mar 05 01:19:56 PM PST 24
Peak memory 209448 kb
Host smart-f2461440-3083-469b-a883-85a8800b7100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663300433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.3663300433
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.4047699824
Short name T371
Test name
Test status
Simulation time 179075688 ps
CPU time 4.61 seconds
Started Mar 05 01:20:12 PM PST 24
Finished Mar 05 01:20:17 PM PST 24
Peak memory 222224 kb
Host smart-a6e109ff-8fe6-4510-83b5-7a7474ed3920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047699824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.4047699824
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.947058939
Short name T258
Test name
Test status
Simulation time 49029542 ps
CPU time 3.24 seconds
Started Mar 05 01:19:55 PM PST 24
Finished Mar 05 01:19:59 PM PST 24
Peak memory 209628 kb
Host smart-49f33bee-f69f-40e9-bbce-edb7391bef36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947058939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.947058939
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.1533923997
Short name T48
Test name
Test status
Simulation time 75863593 ps
CPU time 3.12 seconds
Started Mar 05 01:19:13 PM PST 24
Finished Mar 05 01:19:17 PM PST 24
Peak memory 208396 kb
Host smart-a27569f0-873e-4d2c-b766-c7801029dc6b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1533923997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.1533923997
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.4104895434
Short name T65
Test name
Test status
Simulation time 454287901 ps
CPU time 5.05 seconds
Started Mar 05 01:20:03 PM PST 24
Finished Mar 05 01:20:08 PM PST 24
Peak memory 209308 kb
Host smart-84e10d69-c368-4191-b611-d576146f0bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104895434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.4104895434
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.3924016734
Short name T415
Test name
Test status
Simulation time 82284474 ps
CPU time 3.36 seconds
Started Mar 05 01:20:03 PM PST 24
Finished Mar 05 01:20:07 PM PST 24
Peak memory 215316 kb
Host smart-91f583fb-83fc-47e1-9faf-f61605b9b66b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3924016734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.3924016734
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_sideload.609889087
Short name T40
Test name
Test status
Simulation time 252021947 ps
CPU time 7.06 seconds
Started Mar 05 01:20:12 PM PST 24
Finished Mar 05 01:20:19 PM PST 24
Peak memory 206340 kb
Host smart-c8c9b841-2551-4a87-91b0-6893cd8ff84c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=609889087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.609889087
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.375292329
Short name T80
Test name
Test status
Simulation time 238225404 ps
CPU time 3.22 seconds
Started Mar 05 01:21:05 PM PST 24
Finished Mar 05 01:21:09 PM PST 24
Peak memory 214760 kb
Host smart-9646307b-c981-49c3-bed2-50b4b85f2d08
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=375292329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.375292329
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.270291438
Short name T313
Test name
Test status
Simulation time 48604827 ps
CPU time 3.35 seconds
Started Mar 05 01:21:14 PM PST 24
Finished Mar 05 01:21:17 PM PST 24
Peak memory 214148 kb
Host smart-874b6bf9-30a6-484c-8b0d-c9647c7af667
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=270291438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.270291438
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.3563888468
Short name T166
Test name
Test status
Simulation time 250981185 ps
CPU time 8.11 seconds
Started Mar 05 01:20:36 PM PST 24
Finished Mar 05 01:20:44 PM PST 24
Peak memory 216800 kb
Host smart-f690ac82-a749-403d-9200-5d969d56d1ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563888468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.3563888468
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.119567514
Short name T988
Test name
Test status
Simulation time 1435617576 ps
CPU time 9.15 seconds
Started Mar 05 01:44:05 PM PST 24
Finished Mar 05 01:44:14 PM PST 24
Peak memory 205968 kb
Host smart-707b2922-a62a-4fdc-8bf4-65e5a4715a81
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119567514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.119567514
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.592982232
Short name T1019
Test name
Test status
Simulation time 251359844 ps
CPU time 15.26 seconds
Started Mar 05 01:44:04 PM PST 24
Finished Mar 05 01:44:20 PM PST 24
Peak memory 205868 kb
Host smart-e5df69c1-f7c5-44bc-b26d-8b95bcbdcb02
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592982232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.592982232
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.2802924402
Short name T139
Test name
Test status
Simulation time 111541321 ps
CPU time 1.17 seconds
Started Mar 05 01:44:05 PM PST 24
Finished Mar 05 01:44:06 PM PST 24
Peak memory 205984 kb
Host smart-bd120644-3125-4a20-875d-d49aabc13329
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802924402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.2
802924402
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.2924934103
Short name T1007
Test name
Test status
Simulation time 103502093 ps
CPU time 1.94 seconds
Started Mar 05 01:44:01 PM PST 24
Finished Mar 05 01:44:03 PM PST 24
Peak memory 214184 kb
Host smart-61d35d95-6fcf-48db-892e-8e0ca016286a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924934103 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.2924934103
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.2854157620
Short name T1047
Test name
Test status
Simulation time 30267448 ps
CPU time 1.13 seconds
Started Mar 05 01:44:01 PM PST 24
Finished Mar 05 01:44:03 PM PST 24
Peak memory 205984 kb
Host smart-185f6526-41e0-4fce-950f-65c4e8519307
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854157620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.2854157620
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.3001664473
Short name T951
Test name
Test status
Simulation time 24687097 ps
CPU time 0.7 seconds
Started Mar 05 01:44:01 PM PST 24
Finished Mar 05 01:44:02 PM PST 24
Peak memory 205636 kb
Host smart-8ddfe716-5d2b-46ec-af52-cca9e01e17e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001664473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.3001664473
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.3456179601
Short name T1073
Test name
Test status
Simulation time 895593528 ps
CPU time 1.89 seconds
Started Mar 05 01:44:03 PM PST 24
Finished Mar 05 01:44:05 PM PST 24
Peak memory 205956 kb
Host smart-a5d1ce15-e04b-4d16-9839-89a1646b4b83
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3456179601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.3456179601
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.1485652869
Short name T952
Test name
Test status
Simulation time 58879537 ps
CPU time 1.56 seconds
Started Mar 05 01:44:25 PM PST 24
Finished Mar 05 01:44:26 PM PST 24
Peak memory 214528 kb
Host smart-170facc3-dcc9-4a3a-9d07-2da86a63649b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1485652869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.1485652869
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.2089788672
Short name T961
Test name
Test status
Simulation time 1534241588 ps
CPU time 13.58 seconds
Started Mar 05 01:44:05 PM PST 24
Finished Mar 05 01:44:19 PM PST 24
Peak memory 220436 kb
Host smart-c5fd476b-149b-4d07-9731-f2250571c574
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2089788672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
keymgr_shadow_reg_errors_with_csr_rw.2089788672
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.3069091223
Short name T914
Test name
Test status
Simulation time 126667283 ps
CPU time 3.23 seconds
Started Mar 05 01:44:06 PM PST 24
Finished Mar 05 01:44:10 PM PST 24
Peak memory 214304 kb
Host smart-1ebf5257-56eb-4435-8d4a-8ec1d3a47fda
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069091223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.3069091223
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.595853966
Short name T941
Test name
Test status
Simulation time 518991275 ps
CPU time 7.87 seconds
Started Mar 05 01:44:04 PM PST 24
Finished Mar 05 01:44:12 PM PST 24
Peak memory 206064 kb
Host smart-e4e3c537-c23f-4aaf-8f71-bebc4f6406f3
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=595853966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.595853966
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.1197004778
Short name T1006
Test name
Test status
Simulation time 3598026172 ps
CPU time 14.43 seconds
Started Mar 05 01:44:05 PM PST 24
Finished Mar 05 01:44:19 PM PST 24
Peak memory 206068 kb
Host smart-a865b81a-5f07-4f28-9e17-d3ddf57ee08a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197004778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.1
197004778
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.761734321
Short name T970
Test name
Test status
Simulation time 26434677 ps
CPU time 0.91 seconds
Started Mar 05 01:43:59 PM PST 24
Finished Mar 05 01:44:00 PM PST 24
Peak memory 205856 kb
Host smart-b8e4ed6e-db8a-4056-98fd-630f6a673c9e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=761734321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.761734321
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.1337003147
Short name T1038
Test name
Test status
Simulation time 74168796 ps
CPU time 1.73 seconds
Started Mar 05 01:44:03 PM PST 24
Finished Mar 05 01:44:05 PM PST 24
Peak memory 214176 kb
Host smart-a99fdaad-3b29-4688-8aef-167887c874c3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1337003147 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.1337003147
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.591922159
Short name T1009
Test name
Test status
Simulation time 24128088 ps
CPU time 1.15 seconds
Started Mar 05 01:44:13 PM PST 24
Finished Mar 05 01:44:14 PM PST 24
Peak memory 205956 kb
Host smart-06f43b64-5026-42d5-a3d8-260f06e69cdd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591922159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.591922159
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.1301216168
Short name T1053
Test name
Test status
Simulation time 11397558 ps
CPU time 0.69 seconds
Started Mar 05 01:44:03 PM PST 24
Finished Mar 05 01:44:04 PM PST 24
Peak memory 205660 kb
Host smart-db2fea89-6c44-43cf-bf81-8a228888f63c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1301216168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.1301216168
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.2904463187
Short name T973
Test name
Test status
Simulation time 132476283 ps
CPU time 2.46 seconds
Started Mar 05 01:44:03 PM PST 24
Finished Mar 05 01:44:06 PM PST 24
Peak memory 205984 kb
Host smart-f664801d-9f90-4e39-924a-8e1638d50363
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904463187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sa
me_csr_outstanding.2904463187
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.867900278
Short name T960
Test name
Test status
Simulation time 180793180 ps
CPU time 2.6 seconds
Started Mar 05 01:44:05 PM PST 24
Finished Mar 05 01:44:08 PM PST 24
Peak memory 214472 kb
Host smart-69509d0a-c8c0-420b-91aa-2b3c8942fd95
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867900278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shadow
_reg_errors.867900278
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.1236807433
Short name T929
Test name
Test status
Simulation time 1343265388 ps
CPU time 8.52 seconds
Started Mar 05 01:44:04 PM PST 24
Finished Mar 05 01:44:13 PM PST 24
Peak memory 214440 kb
Host smart-86873e83-ca65-4020-b2b0-1099b9905bb7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236807433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.1236807433
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.389730247
Short name T1000
Test name
Test status
Simulation time 573378375 ps
CPU time 3.86 seconds
Started Mar 05 01:44:01 PM PST 24
Finished Mar 05 01:44:05 PM PST 24
Peak memory 214320 kb
Host smart-e49e6814-2025-4b30-b27a-dd12668cc38d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389730247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.389730247
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.1571498801
Short name T1014
Test name
Test status
Simulation time 45808258 ps
CPU time 1.61 seconds
Started Mar 05 01:44:20 PM PST 24
Finished Mar 05 01:44:23 PM PST 24
Peak memory 214268 kb
Host smart-8f97313a-9a8b-4b09-83eb-111ec5d7c11a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571498801 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.1571498801
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.177198929
Short name T943
Test name
Test status
Simulation time 56383019 ps
CPU time 1.27 seconds
Started Mar 05 01:44:22 PM PST 24
Finished Mar 05 01:44:23 PM PST 24
Peak memory 205896 kb
Host smart-ffd0f924-95d3-4d90-a08d-d38f41053532
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177198929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.177198929
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.2679505849
Short name T1031
Test name
Test status
Simulation time 39966139 ps
CPU time 0.83 seconds
Started Mar 05 01:44:18 PM PST 24
Finished Mar 05 01:44:19 PM PST 24
Peak memory 205692 kb
Host smart-b6a1c8ba-09c4-4672-a813-96a4b92e518d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2679505849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.2679505849
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.2781049599
Short name T1043
Test name
Test status
Simulation time 171379647 ps
CPU time 3.23 seconds
Started Mar 05 01:44:22 PM PST 24
Finished Mar 05 01:44:25 PM PST 24
Peak memory 205956 kb
Host smart-d1e1d3d3-4c9e-4836-837b-d9c08cb1185b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781049599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.2781049599
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.385661789
Short name T1069
Test name
Test status
Simulation time 326649549 ps
CPU time 4.49 seconds
Started Mar 05 01:44:19 PM PST 24
Finished Mar 05 01:44:23 PM PST 24
Peak memory 220288 kb
Host smart-ab4caad0-7791-40bb-af3f-86710b6e5035
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385661789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
keymgr_shadow_reg_errors_with_csr_rw.385661789
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.1977962349
Short name T1051
Test name
Test status
Simulation time 169462762 ps
CPU time 2.64 seconds
Started Mar 05 01:44:22 PM PST 24
Finished Mar 05 01:44:25 PM PST 24
Peak memory 215144 kb
Host smart-9beab684-6d4b-44e4-ae7a-314aaeaba5ae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977962349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.1977962349
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.3942985409
Short name T146
Test name
Test status
Simulation time 1032673509 ps
CPU time 23.08 seconds
Started Mar 05 01:44:21 PM PST 24
Finished Mar 05 01:44:44 PM PST 24
Peak memory 209532 kb
Host smart-d0167f17-dc32-4a69-8e54-31e40b19aaac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942985409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_er
r.3942985409
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.3462422206
Short name T938
Test name
Test status
Simulation time 63172290 ps
CPU time 1.23 seconds
Started Mar 05 01:44:20 PM PST 24
Finished Mar 05 01:44:21 PM PST 24
Peak memory 214248 kb
Host smart-1dd942b2-d343-4a99-9044-a3392670e0a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462422206 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.3462422206
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.3895530159
Short name T1023
Test name
Test status
Simulation time 179236565 ps
CPU time 1.41 seconds
Started Mar 05 01:44:21 PM PST 24
Finished Mar 05 01:44:23 PM PST 24
Peak memory 205932 kb
Host smart-254a8b81-6348-4c7e-a81f-faa8a11ddd33
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895530159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.3895530159
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.1652993333
Short name T1022
Test name
Test status
Simulation time 16849469 ps
CPU time 0.81 seconds
Started Mar 05 01:44:21 PM PST 24
Finished Mar 05 01:44:22 PM PST 24
Peak memory 205756 kb
Host smart-952184e7-1295-47e2-afc5-10ef84697de4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652993333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.1652993333
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.2769117769
Short name T980
Test name
Test status
Simulation time 33301538 ps
CPU time 2.65 seconds
Started Mar 05 01:44:23 PM PST 24
Finished Mar 05 01:44:26 PM PST 24
Peak memory 205988 kb
Host smart-aa64e431-ecef-45a7-8668-38eb8c0d0564
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769117769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s
ame_csr_outstanding.2769117769
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.383471001
Short name T109
Test name
Test status
Simulation time 114477482 ps
CPU time 3.35 seconds
Started Mar 05 01:44:21 PM PST 24
Finished Mar 05 01:44:24 PM PST 24
Peak memory 214556 kb
Host smart-bd39b6c9-f1bb-4fbb-a728-09ccb2b7550d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=383471001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shado
w_reg_errors.383471001
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.3780563061
Short name T958
Test name
Test status
Simulation time 139822909 ps
CPU time 4.45 seconds
Started Mar 05 01:44:20 PM PST 24
Finished Mar 05 01:44:24 PM PST 24
Peak memory 214468 kb
Host smart-fca21f80-8c41-4513-a365-8b266a521301
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3780563061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.3780563061
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.461244478
Short name T1024
Test name
Test status
Simulation time 65155784 ps
CPU time 2.26 seconds
Started Mar 05 01:44:20 PM PST 24
Finished Mar 05 01:44:22 PM PST 24
Peak memory 215364 kb
Host smart-f179e459-d91e-4e1c-9d04-e80822f831ea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=461244478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.461244478
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.2702993535
Short name T161
Test name
Test status
Simulation time 232072018 ps
CPU time 4.91 seconds
Started Mar 05 01:44:22 PM PST 24
Finished Mar 05 01:44:28 PM PST 24
Peak memory 209044 kb
Host smart-20a22cb8-2483-485a-bf11-d85aeff62401
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702993535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.2702993535
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.1752857367
Short name T939
Test name
Test status
Simulation time 32219378 ps
CPU time 1.91 seconds
Started Mar 05 01:44:20 PM PST 24
Finished Mar 05 01:44:22 PM PST 24
Peak memory 214280 kb
Host smart-1fbc51d8-1c79-4e62-a68b-0d526b695f03
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1752857367 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.1752857367
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.2759158475
Short name T1062
Test name
Test status
Simulation time 73915546 ps
CPU time 1.4 seconds
Started Mar 05 01:44:22 PM PST 24
Finished Mar 05 01:44:23 PM PST 24
Peak memory 205976 kb
Host smart-d0dcee72-cd08-4f25-8980-9a35170d5e4e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2759158475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.2759158475
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.2640572406
Short name T1018
Test name
Test status
Simulation time 30467731 ps
CPU time 0.82 seconds
Started Mar 05 01:44:24 PM PST 24
Finished Mar 05 01:44:25 PM PST 24
Peak memory 205628 kb
Host smart-f335163f-95f3-4ca6-9c47-c76084ca950d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2640572406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.2640572406
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.2049983058
Short name T1063
Test name
Test status
Simulation time 35557171 ps
CPU time 2.23 seconds
Started Mar 05 01:44:22 PM PST 24
Finished Mar 05 01:44:25 PM PST 24
Peak memory 206108 kb
Host smart-1735c420-8a24-4a66-ac9c-73afa5e318d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049983058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.2049983058
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.3521052694
Short name T975
Test name
Test status
Simulation time 357991030 ps
CPU time 3.63 seconds
Started Mar 05 01:44:25 PM PST 24
Finished Mar 05 01:44:29 PM PST 24
Peak memory 214476 kb
Host smart-d24e0906-d6a2-4b4c-a1e1-81b1d6aacda4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521052694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.3521052694
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.2688567084
Short name T107
Test name
Test status
Simulation time 356016656 ps
CPU time 5.22 seconds
Started Mar 05 01:44:23 PM PST 24
Finished Mar 05 01:44:28 PM PST 24
Peak memory 214528 kb
Host smart-0afe5825-58d4-4084-bf51-6c0daa898a08
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688567084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.2688567084
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.3060139078
Short name T976
Test name
Test status
Simulation time 109036424 ps
CPU time 2.02 seconds
Started Mar 05 01:44:25 PM PST 24
Finished Mar 05 01:44:27 PM PST 24
Peak memory 206088 kb
Host smart-88af22ca-ec6f-4697-a547-11ce1ea4c0a8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060139078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.3060139078
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.165444992
Short name T142
Test name
Test status
Simulation time 219556660 ps
CPU time 5.45 seconds
Started Mar 05 01:44:20 PM PST 24
Finished Mar 05 01:44:26 PM PST 24
Peak memory 209072 kb
Host smart-fd5cfea2-0a83-4dc1-a909-1ba2462b4efd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165444992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_err
.165444992
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.1369362934
Short name T916
Test name
Test status
Simulation time 43202607 ps
CPU time 2.04 seconds
Started Mar 05 01:44:25 PM PST 24
Finished Mar 05 01:44:27 PM PST 24
Peak memory 214388 kb
Host smart-74026171-c34d-4891-8d10-0c25f1a80f59
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1369362934 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.1369362934
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.3315865614
Short name T946
Test name
Test status
Simulation time 59958632 ps
CPU time 0.94 seconds
Started Mar 05 01:44:24 PM PST 24
Finished Mar 05 01:44:25 PM PST 24
Peak memory 205744 kb
Host smart-447bfd41-f9c7-40ce-998d-bd990a13e9b0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315865614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.3315865614
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.1380702041
Short name T1057
Test name
Test status
Simulation time 10374234 ps
CPU time 0.79 seconds
Started Mar 05 01:44:24 PM PST 24
Finished Mar 05 01:44:25 PM PST 24
Peak memory 205636 kb
Host smart-8501b0b9-a747-43aa-a5da-564c04aa2fca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380702041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.1380702041
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.2005483185
Short name T1017
Test name
Test status
Simulation time 36424065 ps
CPU time 2.51 seconds
Started Mar 05 01:44:27 PM PST 24
Finished Mar 05 01:44:29 PM PST 24
Peak memory 206036 kb
Host smart-1ba33ff3-1361-45f6-a0bf-4341cbac14d1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2005483185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.2005483185
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.3503817568
Short name T978
Test name
Test status
Simulation time 755430442 ps
CPU time 3.65 seconds
Started Mar 05 01:44:24 PM PST 24
Finished Mar 05 01:44:27 PM PST 24
Peak memory 214352 kb
Host smart-8d5eb4a5-5a6a-42d7-9b3c-e035bc185659
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503817568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.3503817568
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.2909505033
Short name T1039
Test name
Test status
Simulation time 171845835 ps
CPU time 4.49 seconds
Started Mar 05 01:44:24 PM PST 24
Finished Mar 05 01:44:29 PM PST 24
Peak memory 220428 kb
Host smart-cb64d3f4-e562-4c90-8a73-f0589c1aac89
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909505033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.2909505033
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.2472160551
Short name T974
Test name
Test status
Simulation time 891265244 ps
CPU time 1.97 seconds
Started Mar 05 01:44:27 PM PST 24
Finished Mar 05 01:44:29 PM PST 24
Peak memory 216364 kb
Host smart-2c72df7b-c78c-4bcc-a3aa-7ebfdfe7ab5e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2472160551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.2472160551
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.399304740
Short name T170
Test name
Test status
Simulation time 385973862 ps
CPU time 1.6 seconds
Started Mar 05 01:44:24 PM PST 24
Finished Mar 05 01:44:25 PM PST 24
Peak memory 214332 kb
Host smart-df4b824f-0e5a-4795-9029-81113ef69bb7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399304740 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.399304740
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.2398511558
Short name T927
Test name
Test status
Simulation time 15760733 ps
CPU time 1.05 seconds
Started Mar 05 01:44:25 PM PST 24
Finished Mar 05 01:44:26 PM PST 24
Peak memory 206056 kb
Host smart-a6d3a743-34b7-4b20-8b9a-0cf6b58f437c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398511558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.2398511558
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.1352209713
Short name T928
Test name
Test status
Simulation time 10786984 ps
CPU time 0.79 seconds
Started Mar 05 01:44:22 PM PST 24
Finished Mar 05 01:44:23 PM PST 24
Peak memory 205660 kb
Host smart-8753c67f-56a4-4dbe-ac16-97db3fb7412e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1352209713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.1352209713
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.2536857331
Short name T1055
Test name
Test status
Simulation time 69244792 ps
CPU time 2.37 seconds
Started Mar 05 01:44:24 PM PST 24
Finished Mar 05 01:44:26 PM PST 24
Peak memory 205960 kb
Host smart-61b60bfa-1aca-4533-b65f-6e37799cdaa3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536857331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s
ame_csr_outstanding.2536857331
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.4164053460
Short name T106
Test name
Test status
Simulation time 135716552 ps
CPU time 3.23 seconds
Started Mar 05 01:44:24 PM PST 24
Finished Mar 05 01:44:27 PM PST 24
Peak memory 214492 kb
Host smart-0c762335-be10-4c18-92fe-77b351e2bcee
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164053460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.4164053460
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.2650569958
Short name T1044
Test name
Test status
Simulation time 192376706 ps
CPU time 5.63 seconds
Started Mar 05 01:44:25 PM PST 24
Finished Mar 05 01:44:30 PM PST 24
Peak memory 220380 kb
Host smart-2d0cdfda-80d4-46b3-b048-d2d0f432bad4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650569958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.2650569958
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.2746249105
Short name T1028
Test name
Test status
Simulation time 180203530 ps
CPU time 3.7 seconds
Started Mar 05 01:44:22 PM PST 24
Finished Mar 05 01:44:26 PM PST 24
Peak memory 214224 kb
Host smart-c2daeacf-d164-4f9d-9173-a61019d10b7a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2746249105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.2746249105
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.2416899187
Short name T1035
Test name
Test status
Simulation time 24007930 ps
CPU time 1.94 seconds
Started Mar 05 01:44:27 PM PST 24
Finished Mar 05 01:44:29 PM PST 24
Peak memory 214228 kb
Host smart-c817c3af-cb83-430d-b7c9-fbd51d768692
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416899187 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.2416899187
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.1963229207
Short name T136
Test name
Test status
Simulation time 19882318 ps
CPU time 1.25 seconds
Started Mar 05 01:44:24 PM PST 24
Finished Mar 05 01:44:26 PM PST 24
Peak memory 206004 kb
Host smart-4d39b7af-387f-49e6-a4a1-0bd00645cec9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963229207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.1963229207
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.794605984
Short name T935
Test name
Test status
Simulation time 15000327 ps
CPU time 0.92 seconds
Started Mar 05 01:44:32 PM PST 24
Finished Mar 05 01:44:34 PM PST 24
Peak memory 205836 kb
Host smart-4b434d7c-35d9-4800-adf4-9742e6a7b192
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794605984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.794605984
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.766759926
Short name T924
Test name
Test status
Simulation time 532581310 ps
CPU time 3.58 seconds
Started Mar 05 01:44:27 PM PST 24
Finished Mar 05 01:44:31 PM PST 24
Peak memory 205980 kb
Host smart-f2be1ad6-c784-464b-927a-668c39f0be8c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=766759926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_sa
me_csr_outstanding.766759926
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.3978105195
Short name T1071
Test name
Test status
Simulation time 207346558 ps
CPU time 5.25 seconds
Started Mar 05 01:44:27 PM PST 24
Finished Mar 05 01:44:33 PM PST 24
Peak memory 214500 kb
Host smart-be0670cb-5233-4aab-b7f3-097c640d66bb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3978105195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.3978105195
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.1260972717
Short name T1011
Test name
Test status
Simulation time 163365238 ps
CPU time 5.49 seconds
Started Mar 05 01:44:32 PM PST 24
Finished Mar 05 01:44:39 PM PST 24
Peak memory 214408 kb
Host smart-a3250f73-91fc-47a6-91c3-9e239930e88d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1260972717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.1260972717
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.3297820568
Short name T1054
Test name
Test status
Simulation time 93248440 ps
CPU time 3.74 seconds
Started Mar 05 01:44:25 PM PST 24
Finished Mar 05 01:44:29 PM PST 24
Peak memory 216284 kb
Host smart-bf4384da-a04a-4699-b044-23af7ca0bcba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297820568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.3297820568
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.1284508742
Short name T143
Test name
Test status
Simulation time 505367293 ps
CPU time 11.08 seconds
Started Mar 05 01:44:23 PM PST 24
Finished Mar 05 01:44:34 PM PST 24
Peak memory 209456 kb
Host smart-9cf3e4f5-0bcc-44e3-bf07-f9976bfe4a95
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1284508742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.1284508742
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.2416396673
Short name T983
Test name
Test status
Simulation time 60509735 ps
CPU time 1.67 seconds
Started Mar 05 01:44:28 PM PST 24
Finished Mar 05 01:44:30 PM PST 24
Peak memory 214376 kb
Host smart-6dac75ab-002f-4d2b-9751-baaeaaa1a957
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416396673 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.2416396673
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.1004807101
Short name T1070
Test name
Test status
Simulation time 36183363 ps
CPU time 0.93 seconds
Started Mar 05 01:44:32 PM PST 24
Finished Mar 05 01:44:34 PM PST 24
Peak memory 205824 kb
Host smart-c2aa156c-0693-46eb-bbb8-0c735581adf3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004807101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.1004807101
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.2632946734
Short name T1072
Test name
Test status
Simulation time 64870546 ps
CPU time 0.88 seconds
Started Mar 05 01:44:29 PM PST 24
Finished Mar 05 01:44:30 PM PST 24
Peak memory 205648 kb
Host smart-e02d7780-4566-44ec-b82c-2b31c600cdb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632946734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.2632946734
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.965891482
Short name T977
Test name
Test status
Simulation time 1107913478 ps
CPU time 3.15 seconds
Started Mar 05 01:44:30 PM PST 24
Finished Mar 05 01:44:33 PM PST 24
Peak memory 205952 kb
Host smart-0ec6f91c-5fb7-4918-b9bd-2aaba57ec2d0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965891482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_sa
me_csr_outstanding.965891482
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.2625571739
Short name T996
Test name
Test status
Simulation time 722999767 ps
CPU time 6.69 seconds
Started Mar 05 01:44:29 PM PST 24
Finished Mar 05 01:44:36 PM PST 24
Peak memory 214524 kb
Host smart-be6f6bd8-f599-4a01-a118-df32253b989d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625571739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.2625571739
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.1997528096
Short name T948
Test name
Test status
Simulation time 334604039 ps
CPU time 4.25 seconds
Started Mar 05 01:44:27 PM PST 24
Finished Mar 05 01:44:32 PM PST 24
Peak memory 214588 kb
Host smart-9581c4ef-8ebe-4218-a0ec-bdd48bfbc2f3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997528096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.1997528096
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.3773111024
Short name T913
Test name
Test status
Simulation time 56254802 ps
CPU time 2.92 seconds
Started Mar 05 01:44:32 PM PST 24
Finished Mar 05 01:44:36 PM PST 24
Peak memory 216340 kb
Host smart-bb69d0c5-822d-4c72-be79-c9dc56d1046e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773111024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.3773111024
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.3851413623
Short name T1032
Test name
Test status
Simulation time 164257313 ps
CPU time 1.8 seconds
Started Mar 05 01:44:22 PM PST 24
Finished Mar 05 01:44:24 PM PST 24
Peak memory 214288 kb
Host smart-0dd6f226-1b22-40b9-8f6a-96b6cc37cc5d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3851413623 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.3851413623
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.2781302991
Short name T134
Test name
Test status
Simulation time 38862982 ps
CPU time 1.16 seconds
Started Mar 05 01:44:23 PM PST 24
Finished Mar 05 01:44:24 PM PST 24
Peak memory 206004 kb
Host smart-6de692a5-7d5f-4f1a-9a3a-ad4804309f21
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2781302991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.2781302991
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.3077084523
Short name T953
Test name
Test status
Simulation time 16892387 ps
CPU time 0.94 seconds
Started Mar 05 01:44:26 PM PST 24
Finished Mar 05 01:44:27 PM PST 24
Peak memory 205812 kb
Host smart-689721b2-0582-4d95-b6d2-e7597d9d6adb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3077084523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.3077084523
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.1718269549
Short name T1048
Test name
Test status
Simulation time 112347850 ps
CPU time 1.86 seconds
Started Mar 05 01:44:23 PM PST 24
Finished Mar 05 01:44:25 PM PST 24
Peak memory 206048 kb
Host smart-89ee4680-38eb-4c20-bb36-737acfb183aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1718269549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.1718269549
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.2165917799
Short name T922
Test name
Test status
Simulation time 145372281 ps
CPU time 2.68 seconds
Started Mar 05 01:44:29 PM PST 24
Finished Mar 05 01:44:32 PM PST 24
Peak memory 214528 kb
Host smart-3c65cad5-cdf1-41a8-8878-80fb8aa0e58b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2165917799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.2165917799
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.463640512
Short name T959
Test name
Test status
Simulation time 92180389 ps
CPU time 4.63 seconds
Started Mar 05 01:44:30 PM PST 24
Finished Mar 05 01:44:35 PM PST 24
Peak memory 214536 kb
Host smart-f528f1e3-dc4c-4a63-96bc-0917d7062c5e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=463640512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
keymgr_shadow_reg_errors_with_csr_rw.463640512
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.3046607447
Short name T989
Test name
Test status
Simulation time 495487102 ps
CPU time 4.43 seconds
Started Mar 05 01:44:21 PM PST 24
Finished Mar 05 01:44:26 PM PST 24
Peak memory 214212 kb
Host smart-9d7bff04-79ec-4cb5-835f-06cd26fe8dae
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3046607447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.3046607447
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.2429514377
Short name T990
Test name
Test status
Simulation time 40964875 ps
CPU time 1.59 seconds
Started Mar 05 01:44:31 PM PST 24
Finished Mar 05 01:44:33 PM PST 24
Peak memory 214360 kb
Host smart-fd84a3f8-e006-40ec-b719-1d3ff14c7551
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2429514377 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.2429514377
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.1621753553
Short name T971
Test name
Test status
Simulation time 21586463 ps
CPU time 1.4 seconds
Started Mar 05 01:44:29 PM PST 24
Finished Mar 05 01:44:31 PM PST 24
Peak memory 206012 kb
Host smart-0bbb3c4d-6592-4a0c-af95-762344ccd5f0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621753553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.1621753553
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.3649320326
Short name T936
Test name
Test status
Simulation time 9555071 ps
CPU time 0.73 seconds
Started Mar 05 01:44:39 PM PST 24
Finished Mar 05 01:44:41 PM PST 24
Peak memory 205732 kb
Host smart-e389e79f-d37b-493f-b5dc-a59f3378e940
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649320326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.3649320326
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.2949526885
Short name T972
Test name
Test status
Simulation time 20558432 ps
CPU time 1.62 seconds
Started Mar 05 01:44:30 PM PST 24
Finished Mar 05 01:44:32 PM PST 24
Peak memory 206032 kb
Host smart-8d84c2ee-b35d-45f9-bef1-1df605592dc0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949526885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.2949526885
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.1598100051
Short name T956
Test name
Test status
Simulation time 529411271 ps
CPU time 5.61 seconds
Started Mar 05 01:44:30 PM PST 24
Finished Mar 05 01:44:36 PM PST 24
Peak memory 214468 kb
Host smart-72b439f0-431a-4076-aa6c-4d8745c4f46d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598100051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.1598100051
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.1114254269
Short name T997
Test name
Test status
Simulation time 3904456531 ps
CPU time 15.57 seconds
Started Mar 05 01:44:35 PM PST 24
Finished Mar 05 01:44:51 PM PST 24
Peak memory 214676 kb
Host smart-fef88c4e-03e7-48c5-b02e-31e5dba92f94
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114254269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.1114254269
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.2248129504
Short name T1059
Test name
Test status
Simulation time 150962458 ps
CPU time 3.35 seconds
Started Mar 05 01:44:30 PM PST 24
Finished Mar 05 01:44:34 PM PST 24
Peak memory 214280 kb
Host smart-2a31a64d-0c69-4669-9f79-3f64106af3bb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248129504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.2248129504
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.265290048
Short name T954
Test name
Test status
Simulation time 567943188 ps
CPU time 2.05 seconds
Started Mar 05 01:44:30 PM PST 24
Finished Mar 05 01:44:32 PM PST 24
Peak memory 214268 kb
Host smart-261dd22c-3fb2-435d-9bbc-45e08bb41d3a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=265290048 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.265290048
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.2152062460
Short name T1050
Test name
Test status
Simulation time 57649668 ps
CPU time 1 seconds
Started Mar 05 01:44:33 PM PST 24
Finished Mar 05 01:44:34 PM PST 24
Peak memory 205908 kb
Host smart-86ea3872-9bd7-4221-b9e0-66f95224028d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152062460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.2152062460
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.3518360835
Short name T912
Test name
Test status
Simulation time 19199345 ps
CPU time 0.86 seconds
Started Mar 05 01:44:33 PM PST 24
Finished Mar 05 01:44:34 PM PST 24
Peak memory 205788 kb
Host smart-3e80a8b2-1cdc-405e-b9db-d625043cc6a8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518360835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.3518360835
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.2401610641
Short name T964
Test name
Test status
Simulation time 23479629 ps
CPU time 1.69 seconds
Started Mar 05 01:44:31 PM PST 24
Finished Mar 05 01:44:32 PM PST 24
Peak memory 206036 kb
Host smart-04862cd1-fb2c-4f0c-8f36-11383e6fb8bc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2401610641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.2401610641
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.1144330057
Short name T1074
Test name
Test status
Simulation time 106259277 ps
CPU time 3.43 seconds
Started Mar 05 01:44:28 PM PST 24
Finished Mar 05 01:44:33 PM PST 24
Peak memory 214408 kb
Host smart-daaf5fb2-c0b7-4dec-ba3c-9b8157e61706
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1144330057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.1144330057
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.2579833586
Short name T1002
Test name
Test status
Simulation time 718065625 ps
CPU time 9.29 seconds
Started Mar 05 01:44:31 PM PST 24
Finished Mar 05 01:44:40 PM PST 24
Peak memory 220244 kb
Host smart-dc64bac7-4a94-4927-a84b-c8f98d98ff6a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579833586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.2579833586
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.1051758897
Short name T991
Test name
Test status
Simulation time 124702757 ps
CPU time 3.08 seconds
Started Mar 05 01:44:30 PM PST 24
Finished Mar 05 01:44:33 PM PST 24
Peak memory 214144 kb
Host smart-962cd79e-b122-4123-bbe7-c6439392fb79
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1051758897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.1051758897
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.282286053
Short name T1064
Test name
Test status
Simulation time 1502575898 ps
CPU time 9.4 seconds
Started Mar 05 01:44:06 PM PST 24
Finished Mar 05 01:44:16 PM PST 24
Peak memory 205956 kb
Host smart-d041acb1-f3e2-425f-adbf-5e40a1e77a9c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282286053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.282286053
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.2541864650
Short name T994
Test name
Test status
Simulation time 562527821 ps
CPU time 8.37 seconds
Started Mar 05 01:44:13 PM PST 24
Finished Mar 05 01:44:21 PM PST 24
Peak memory 206028 kb
Host smart-52ef525b-d7a0-499c-80c2-6ce814422a08
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541864650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.2
541864650
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.3786247239
Short name T932
Test name
Test status
Simulation time 79468918 ps
CPU time 1.1 seconds
Started Mar 05 01:43:59 PM PST 24
Finished Mar 05 01:44:00 PM PST 24
Peak memory 206052 kb
Host smart-6a949c49-4550-4eb9-9794-3846939dbf46
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3786247239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.3
786247239
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.63772012
Short name T930
Test name
Test status
Simulation time 66918182 ps
CPU time 1.17 seconds
Started Mar 05 01:44:03 PM PST 24
Finished Mar 05 01:44:04 PM PST 24
Peak memory 206004 kb
Host smart-f0bdef4a-8a29-433f-b900-51332886d548
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63772012 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.63772012
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.787379802
Short name T1033
Test name
Test status
Simulation time 44571577 ps
CPU time 1.08 seconds
Started Mar 05 01:44:06 PM PST 24
Finished Mar 05 01:44:07 PM PST 24
Peak memory 206016 kb
Host smart-74ae7050-6f9f-43c7-bf36-6988c6c52c95
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=787379802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.787379802
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.319597124
Short name T921
Test name
Test status
Simulation time 27666531 ps
CPU time 0.76 seconds
Started Mar 05 01:44:01 PM PST 24
Finished Mar 05 01:44:02 PM PST 24
Peak memory 205748 kb
Host smart-6277a4f4-bc19-4ee6-9f3d-34a9712623a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319597124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.319597124
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.801602664
Short name T133
Test name
Test status
Simulation time 172056427 ps
CPU time 2.08 seconds
Started Mar 05 01:44:02 PM PST 24
Finished Mar 05 01:44:05 PM PST 24
Peak memory 205992 kb
Host smart-b83b0ecd-4b24-4d9b-9510-82252d5f1a26
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=801602664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sam
e_csr_outstanding.801602664
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.2096326415
Short name T923
Test name
Test status
Simulation time 163564933 ps
CPU time 2.27 seconds
Started Mar 05 01:44:04 PM PST 24
Finished Mar 05 01:44:06 PM PST 24
Peak memory 214384 kb
Host smart-57f6c726-c281-43a5-8b09-9fcf880d2955
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096326415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.2096326415
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.3885531986
Short name T111
Test name
Test status
Simulation time 1122702199 ps
CPU time 12.83 seconds
Started Mar 05 01:44:12 PM PST 24
Finished Mar 05 01:44:25 PM PST 24
Peak memory 214512 kb
Host smart-64174bf9-9ec9-4af5-8a83-22335ebdd978
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3885531986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.3885531986
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.3761268045
Short name T979
Test name
Test status
Simulation time 567620509 ps
CPU time 1.66 seconds
Started Mar 05 01:44:06 PM PST 24
Finished Mar 05 01:44:08 PM PST 24
Peak memory 214120 kb
Host smart-fc1636ed-b5d1-4e20-a414-d3f6e058a216
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761268045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.3761268045
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.3134970863
Short name T156
Test name
Test status
Simulation time 509761612 ps
CPU time 10.88 seconds
Started Mar 05 01:44:06 PM PST 24
Finished Mar 05 01:44:18 PM PST 24
Peak memory 209700 kb
Host smart-f3fed851-6cad-4f3b-be0d-63ba80b2c26c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134970863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.3134970863
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.681006531
Short name T1025
Test name
Test status
Simulation time 42420357 ps
CPU time 0.71 seconds
Started Mar 05 01:44:33 PM PST 24
Finished Mar 05 01:44:34 PM PST 24
Peak memory 205776 kb
Host smart-b477464f-779f-4c75-a4f4-c4354cefe8a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681006531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.681006531
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.1031531927
Short name T1042
Test name
Test status
Simulation time 155808088 ps
CPU time 0.86 seconds
Started Mar 05 01:44:27 PM PST 24
Finished Mar 05 01:44:28 PM PST 24
Peak memory 205692 kb
Host smart-ae4643c5-3227-4247-8f64-f37ec3bea115
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1031531927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.1031531927
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.339122369
Short name T925
Test name
Test status
Simulation time 43370835 ps
CPU time 0.78 seconds
Started Mar 05 01:44:31 PM PST 24
Finished Mar 05 01:44:32 PM PST 24
Peak memory 205752 kb
Host smart-dea65296-839b-4ba8-a6fc-0ab0eeea4283
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339122369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.339122369
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.3030665638
Short name T1015
Test name
Test status
Simulation time 22391560 ps
CPU time 0.71 seconds
Started Mar 05 01:44:35 PM PST 24
Finished Mar 05 01:44:36 PM PST 24
Peak memory 205648 kb
Host smart-e508c1a4-0b23-4655-be5a-0583cc239a7a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030665638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.3030665638
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.1419197439
Short name T1012
Test name
Test status
Simulation time 11789745 ps
CPU time 0.7 seconds
Started Mar 05 01:44:31 PM PST 24
Finished Mar 05 01:44:31 PM PST 24
Peak memory 205696 kb
Host smart-99077918-6685-4765-b9b4-8568151f53ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419197439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.1419197439
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.4105199898
Short name T968
Test name
Test status
Simulation time 9549176 ps
CPU time 0.82 seconds
Started Mar 05 01:44:36 PM PST 24
Finished Mar 05 01:44:37 PM PST 24
Peak memory 205648 kb
Host smart-424a62c0-5d04-4771-98e7-6a48915d5cea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4105199898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.4105199898
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.4278094864
Short name T1020
Test name
Test status
Simulation time 23633617 ps
CPU time 0.85 seconds
Started Mar 05 01:44:34 PM PST 24
Finished Mar 05 01:44:36 PM PST 24
Peak memory 205724 kb
Host smart-1fa4755d-8989-4a2d-98b7-7bb7266f4c25
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278094864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.4278094864
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.2384405224
Short name T1010
Test name
Test status
Simulation time 11216547 ps
CPU time 0.87 seconds
Started Mar 05 01:44:29 PM PST 24
Finished Mar 05 01:44:30 PM PST 24
Peak memory 205720 kb
Host smart-ede7c1ed-6f75-4658-ae4e-69fa2d3325c3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2384405224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.2384405224
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.2702498015
Short name T949
Test name
Test status
Simulation time 12619157 ps
CPU time 0.73 seconds
Started Mar 05 01:44:31 PM PST 24
Finished Mar 05 01:44:32 PM PST 24
Peak memory 205696 kb
Host smart-2407ea47-d3d0-4c2c-b78b-d91dc662d27f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702498015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.2702498015
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.4008083657
Short name T1003
Test name
Test status
Simulation time 17906801 ps
CPU time 0.93 seconds
Started Mar 05 01:44:36 PM PST 24
Finished Mar 05 01:44:38 PM PST 24
Peak memory 205828 kb
Host smart-26347389-3b1d-4873-a8f2-fd137f0c0e7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008083657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.4008083657
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.2545212640
Short name T982
Test name
Test status
Simulation time 238106824 ps
CPU time 5.8 seconds
Started Mar 05 01:44:05 PM PST 24
Finished Mar 05 01:44:11 PM PST 24
Peak memory 205920 kb
Host smart-ffd13ba8-2601-44da-9c69-e3cc841ada95
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545212640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.2
545212640
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.3511808898
Short name T915
Test name
Test status
Simulation time 501818355 ps
CPU time 7.74 seconds
Started Mar 05 01:44:13 PM PST 24
Finished Mar 05 01:44:20 PM PST 24
Peak memory 206100 kb
Host smart-38df6e74-c18b-4820-8132-d6e9be4147e2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511808898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.3
511808898
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.770041648
Short name T957
Test name
Test status
Simulation time 77371890 ps
CPU time 1.36 seconds
Started Mar 05 01:44:04 PM PST 24
Finished Mar 05 01:44:06 PM PST 24
Peak memory 205936 kb
Host smart-fec0c34a-968f-4270-b694-6ad89deed35f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770041648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.770041648
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.1344088624
Short name T1016
Test name
Test status
Simulation time 15743781 ps
CPU time 1.17 seconds
Started Mar 05 01:43:59 PM PST 24
Finished Mar 05 01:44:00 PM PST 24
Peak memory 206064 kb
Host smart-9b3ec020-8065-4cfe-9468-1694f92e9ddf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344088624 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.1344088624
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.3891459573
Short name T1034
Test name
Test status
Simulation time 24840169 ps
CPU time 1.16 seconds
Started Mar 05 01:44:12 PM PST 24
Finished Mar 05 01:44:14 PM PST 24
Peak memory 206064 kb
Host smart-ff5eab89-75c0-4525-b36f-492c30f211d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891459573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.3891459573
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.960933610
Short name T1036
Test name
Test status
Simulation time 125979314 ps
CPU time 0.85 seconds
Started Mar 05 01:44:05 PM PST 24
Finished Mar 05 01:44:06 PM PST 24
Peak memory 205680 kb
Host smart-9ca3f19b-e452-4e21-b861-0a0158b77c60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=960933610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.960933610
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.2565604766
Short name T944
Test name
Test status
Simulation time 161938548 ps
CPU time 2.29 seconds
Started Mar 05 01:44:06 PM PST 24
Finished Mar 05 01:44:08 PM PST 24
Peak memory 206028 kb
Host smart-971f50c7-1c09-4417-a99b-005c3309c48d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2565604766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.2565604766
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.3821772004
Short name T1065
Test name
Test status
Simulation time 365376025 ps
CPU time 3.82 seconds
Started Mar 05 01:44:01 PM PST 24
Finished Mar 05 01:44:05 PM PST 24
Peak memory 214508 kb
Host smart-1dd3e355-d144-46c4-9580-7f0a2ec81dff
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3821772004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.3821772004
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.2681600772
Short name T1021
Test name
Test status
Simulation time 371984867 ps
CPU time 8.77 seconds
Started Mar 05 01:44:06 PM PST 24
Finished Mar 05 01:44:15 PM PST 24
Peak memory 214516 kb
Host smart-aed90db8-b32d-40d0-a6d0-b9e60df7ffa9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681600772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.2681600772
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.708346963
Short name T1056
Test name
Test status
Simulation time 232417114 ps
CPU time 1.82 seconds
Started Mar 05 01:44:00 PM PST 24
Finished Mar 05 01:44:02 PM PST 24
Peak memory 206104 kb
Host smart-72a093e8-5d09-476c-9758-eac6426379fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=708346963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.708346963
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.843691918
Short name T155
Test name
Test status
Simulation time 250131480 ps
CPU time 3.75 seconds
Started Mar 05 01:44:02 PM PST 24
Finished Mar 05 01:44:06 PM PST 24
Peak memory 209256 kb
Host smart-9b232ee2-7c1f-4a3c-8f91-0c094c745903
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843691918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err.
843691918
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.3513345133
Short name T1001
Test name
Test status
Simulation time 23048765 ps
CPU time 0.71 seconds
Started Mar 05 01:44:35 PM PST 24
Finished Mar 05 01:44:36 PM PST 24
Peak memory 205724 kb
Host smart-70b2e611-2d32-4957-b22b-039cc06dee1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3513345133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.3513345133
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.720396248
Short name T1027
Test name
Test status
Simulation time 15607748 ps
CPU time 0.71 seconds
Started Mar 05 01:44:36 PM PST 24
Finished Mar 05 01:44:37 PM PST 24
Peak memory 205640 kb
Host smart-e295ea70-a428-47a0-9870-4f1f2aeced06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720396248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.720396248
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.3255567414
Short name T984
Test name
Test status
Simulation time 61886286 ps
CPU time 0.72 seconds
Started Mar 05 01:44:39 PM PST 24
Finished Mar 05 01:44:41 PM PST 24
Peak memory 205656 kb
Host smart-3706f183-cf95-4b30-908b-88622717de72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255567414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.3255567414
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.2405131738
Short name T1058
Test name
Test status
Simulation time 23382523 ps
CPU time 0.81 seconds
Started Mar 05 01:44:33 PM PST 24
Finished Mar 05 01:44:34 PM PST 24
Peak memory 205788 kb
Host smart-0f037f26-dfc0-4a50-a740-95b7cad90677
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405131738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.2405131738
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.1934348274
Short name T947
Test name
Test status
Simulation time 50419892 ps
CPU time 0.76 seconds
Started Mar 05 01:44:31 PM PST 24
Finished Mar 05 01:44:32 PM PST 24
Peak memory 205696 kb
Host smart-215d4f19-08fa-48dc-884e-d7da353f3602
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934348274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.1934348274
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.1068797705
Short name T1040
Test name
Test status
Simulation time 29568217 ps
CPU time 0.8 seconds
Started Mar 05 01:44:33 PM PST 24
Finished Mar 05 01:44:35 PM PST 24
Peak memory 205696 kb
Host smart-1995e0d3-2444-40c0-a294-1132dea948d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1068797705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.1068797705
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.640860894
Short name T969
Test name
Test status
Simulation time 21957227 ps
CPU time 1.04 seconds
Started Mar 05 01:44:36 PM PST 24
Finished Mar 05 01:44:37 PM PST 24
Peak memory 205916 kb
Host smart-16838b9b-9807-4bd9-9607-2a8c0931c56e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640860894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.640860894
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.2931889053
Short name T1037
Test name
Test status
Simulation time 29663438 ps
CPU time 0.83 seconds
Started Mar 05 01:44:33 PM PST 24
Finished Mar 05 01:44:35 PM PST 24
Peak memory 205644 kb
Host smart-e0180a88-e5d4-45f6-9deb-2d019604a14b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931889053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.2931889053
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.237031240
Short name T966
Test name
Test status
Simulation time 9929830 ps
CPU time 0.79 seconds
Started Mar 05 01:44:36 PM PST 24
Finished Mar 05 01:44:38 PM PST 24
Peak memory 205668 kb
Host smart-5c42c7d1-555f-4679-ae94-277af0a3a1ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237031240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.237031240
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.2279539423
Short name T1052
Test name
Test status
Simulation time 10343973 ps
CPU time 0.8 seconds
Started Mar 05 01:44:39 PM PST 24
Finished Mar 05 01:44:41 PM PST 24
Peak memory 205604 kb
Host smart-e6bcc635-bcdf-44ea-b138-347670912827
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2279539423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.2279539423
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.4037537457
Short name T945
Test name
Test status
Simulation time 127521426 ps
CPU time 8.77 seconds
Started Mar 05 01:44:11 PM PST 24
Finished Mar 05 01:44:20 PM PST 24
Peak memory 206068 kb
Host smart-2968ff0d-d597-45bf-a86f-f57f24057567
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4037537457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.4
037537457
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.1801215221
Short name T995
Test name
Test status
Simulation time 920261670 ps
CPU time 8.02 seconds
Started Mar 05 01:44:09 PM PST 24
Finished Mar 05 01:44:17 PM PST 24
Peak memory 205960 kb
Host smart-42447d9d-30b6-4fe1-af6a-fefb53911fac
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1801215221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.1
801215221
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.2562838219
Short name T171
Test name
Test status
Simulation time 78852141 ps
CPU time 0.94 seconds
Started Mar 05 01:44:16 PM PST 24
Finished Mar 05 01:44:17 PM PST 24
Peak memory 205856 kb
Host smart-ffb6121b-3db9-4f15-969e-ae71fe2308dc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562838219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.2
562838219
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.3662377815
Short name T144
Test name
Test status
Simulation time 148766529 ps
CPU time 1.5 seconds
Started Mar 05 01:44:12 PM PST 24
Finished Mar 05 01:44:13 PM PST 24
Peak memory 206028 kb
Host smart-444596a8-e69c-467d-a3cc-8a90cbe2c280
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662377815 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.3662377815
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.2992505318
Short name T135
Test name
Test status
Simulation time 16112260 ps
CPU time 1.06 seconds
Started Mar 05 01:44:11 PM PST 24
Finished Mar 05 01:44:12 PM PST 24
Peak memory 205952 kb
Host smart-653b5ca2-d120-4d3d-9f74-1be31fed0d28
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2992505318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.2992505318
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.2528266645
Short name T986
Test name
Test status
Simulation time 10710679 ps
CPU time 0.71 seconds
Started Mar 05 01:44:13 PM PST 24
Finished Mar 05 01:44:14 PM PST 24
Peak memory 205736 kb
Host smart-be14939e-bf2d-45b4-864a-f877a1e86ac9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528266645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.2528266645
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.3174485531
Short name T993
Test name
Test status
Simulation time 45313682 ps
CPU time 2.15 seconds
Started Mar 05 01:44:12 PM PST 24
Finished Mar 05 01:44:14 PM PST 24
Peak memory 205968 kb
Host smart-62af1d20-47b6-40ed-ac51-fb7bc5d827c2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174485531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.3174485531
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.1589289253
Short name T926
Test name
Test status
Simulation time 674235251 ps
CPU time 2.17 seconds
Started Mar 05 01:44:11 PM PST 24
Finished Mar 05 01:44:14 PM PST 24
Peak memory 214424 kb
Host smart-d83ea7a6-7fa3-4546-b741-42b1073b3aa3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1589289253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.1589289253
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.2225504302
Short name T138
Test name
Test status
Simulation time 3848439062 ps
CPU time 9.69 seconds
Started Mar 05 01:44:06 PM PST 24
Finished Mar 05 01:44:16 PM PST 24
Peak memory 221492 kb
Host smart-63a973b4-1c47-43e6-8ded-5d4674744de0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225504302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.2225504302
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.2468596485
Short name T962
Test name
Test status
Simulation time 215179884 ps
CPU time 3.57 seconds
Started Mar 05 01:44:06 PM PST 24
Finished Mar 05 01:44:09 PM PST 24
Peak memory 214084 kb
Host smart-47cfc712-aaaa-44ad-a208-f9401b230062
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2468596485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.2468596485
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.1615630630
Short name T153
Test name
Test status
Simulation time 111686961 ps
CPU time 3.23 seconds
Started Mar 05 01:44:15 PM PST 24
Finished Mar 05 01:44:19 PM PST 24
Peak memory 209792 kb
Host smart-cf3aeca0-0a89-4184-9fbe-9ac50f4fe084
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615630630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.1615630630
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.1059701931
Short name T910
Test name
Test status
Simulation time 8391831 ps
CPU time 0.7 seconds
Started Mar 05 01:44:36 PM PST 24
Finished Mar 05 01:44:37 PM PST 24
Peak memory 205672 kb
Host smart-3789f149-34f2-4265-89b2-9fdf692c278b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1059701931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.1059701931
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.2656626886
Short name T911
Test name
Test status
Simulation time 46423517 ps
CPU time 0.76 seconds
Started Mar 05 01:44:31 PM PST 24
Finished Mar 05 01:44:32 PM PST 24
Peak memory 205700 kb
Host smart-b8b7e706-7a3f-44b0-a336-a789fad5e3cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656626886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.2656626886
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.2261448124
Short name T965
Test name
Test status
Simulation time 39814080 ps
CPU time 0.76 seconds
Started Mar 05 01:44:34 PM PST 24
Finished Mar 05 01:44:35 PM PST 24
Peak memory 205608 kb
Host smart-193e7922-16be-4311-82e4-106984b407ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261448124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.2261448124
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.2491893053
Short name T1008
Test name
Test status
Simulation time 7457429 ps
CPU time 0.85 seconds
Started Mar 05 01:44:30 PM PST 24
Finished Mar 05 01:44:30 PM PST 24
Peak memory 205740 kb
Host smart-f2da7887-8f41-4f2c-a3b0-7460508fb8f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491893053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.2491893053
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.2362274913
Short name T1075
Test name
Test status
Simulation time 9736423 ps
CPU time 0.81 seconds
Started Mar 05 01:44:39 PM PST 24
Finished Mar 05 01:44:41 PM PST 24
Peak memory 205656 kb
Host smart-05271443-c08b-42b7-af9d-e652712ac403
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2362274913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.2362274913
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.1816869590
Short name T1046
Test name
Test status
Simulation time 80211827 ps
CPU time 0.8 seconds
Started Mar 05 01:44:39 PM PST 24
Finished Mar 05 01:44:41 PM PST 24
Peak memory 205656 kb
Host smart-90907271-53f7-47eb-a1a3-7aebee138ae0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816869590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.1816869590
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.2141228349
Short name T937
Test name
Test status
Simulation time 16127480 ps
CPU time 0.74 seconds
Started Mar 05 01:44:34 PM PST 24
Finished Mar 05 01:44:35 PM PST 24
Peak memory 205720 kb
Host smart-e69a0e5b-ee4d-45af-8b1b-91a4ca63e4c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141228349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.2141228349
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.3594678227
Short name T933
Test name
Test status
Simulation time 24448336 ps
CPU time 0.86 seconds
Started Mar 05 01:44:33 PM PST 24
Finished Mar 05 01:44:34 PM PST 24
Peak memory 205732 kb
Host smart-209263e2-6be7-41e3-991d-3241d70f1b81
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3594678227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.3594678227
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.3561761395
Short name T942
Test name
Test status
Simulation time 14095485 ps
CPU time 0.79 seconds
Started Mar 05 01:44:34 PM PST 24
Finished Mar 05 01:44:35 PM PST 24
Peak memory 205520 kb
Host smart-f7add697-6401-4738-87b8-7f99574b8efe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3561761395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.3561761395
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.588875475
Short name T999
Test name
Test status
Simulation time 60707312 ps
CPU time 0.77 seconds
Started Mar 05 01:44:39 PM PST 24
Finished Mar 05 01:44:41 PM PST 24
Peak memory 205568 kb
Host smart-f51b9dba-e668-4748-b065-049bb2f8b023
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588875475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.588875475
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.2803866479
Short name T1005
Test name
Test status
Simulation time 13647733 ps
CPU time 0.98 seconds
Started Mar 05 01:44:14 PM PST 24
Finished Mar 05 01:44:15 PM PST 24
Peak memory 205932 kb
Host smart-6dca1f2c-ff56-4dce-9082-be33cef377a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2803866479 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.2803866479
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.597336339
Short name T967
Test name
Test status
Simulation time 13476717 ps
CPU time 1.11 seconds
Started Mar 05 01:44:11 PM PST 24
Finished Mar 05 01:44:12 PM PST 24
Peak memory 206100 kb
Host smart-c455da0d-6be0-44f0-8a80-0a0fba68d8f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597336339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.597336339
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.3639078357
Short name T987
Test name
Test status
Simulation time 9562749 ps
CPU time 0.75 seconds
Started Mar 05 01:44:12 PM PST 24
Finished Mar 05 01:44:13 PM PST 24
Peak memory 205672 kb
Host smart-f0153bf4-e3a0-4876-aa31-bdcc25b72f62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639078357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.3639078357
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.3584917133
Short name T1068
Test name
Test status
Simulation time 161105166 ps
CPU time 2.24 seconds
Started Mar 05 01:44:15 PM PST 24
Finished Mar 05 01:44:18 PM PST 24
Peak memory 206064 kb
Host smart-55a2291f-b078-4254-bcb0-6ccfdb187ecb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3584917133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.3584917133
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.2252666333
Short name T1026
Test name
Test status
Simulation time 718280201 ps
CPU time 5.61 seconds
Started Mar 05 01:44:12 PM PST 24
Finished Mar 05 01:44:17 PM PST 24
Peak memory 214504 kb
Host smart-8da19e44-7a60-4e06-8ca6-03c1b5dac9ad
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2252666333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.2252666333
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.4036134736
Short name T998
Test name
Test status
Simulation time 124387006 ps
CPU time 3.68 seconds
Started Mar 05 01:44:12 PM PST 24
Finished Mar 05 01:44:15 PM PST 24
Peak memory 214492 kb
Host smart-e46be2e4-dd37-460f-89bc-316fdc9bd60a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4036134736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
keymgr_shadow_reg_errors_with_csr_rw.4036134736
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.819804866
Short name T934
Test name
Test status
Simulation time 339682234 ps
CPU time 1.64 seconds
Started Mar 05 01:44:14 PM PST 24
Finished Mar 05 01:44:16 PM PST 24
Peak memory 222240 kb
Host smart-5b896fec-8678-493e-a8bd-5dcfdfe15be3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819804866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.819804866
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.2255244848
Short name T154
Test name
Test status
Simulation time 610412219 ps
CPU time 8.78 seconds
Started Mar 05 01:44:10 PM PST 24
Finished Mar 05 01:44:20 PM PST 24
Peak memory 209460 kb
Host smart-49e3648f-f73e-40c9-9588-6a54f0ea689d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255244848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.2255244848
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.2126584434
Short name T386
Test name
Test status
Simulation time 409892204 ps
CPU time 1.69 seconds
Started Mar 05 01:44:14 PM PST 24
Finished Mar 05 01:44:16 PM PST 24
Peak memory 214284 kb
Host smart-a57e040f-4b48-4d5d-b254-6792cff8afdf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2126584434 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.2126584434
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.4007589662
Short name T1067
Test name
Test status
Simulation time 100896633 ps
CPU time 1.12 seconds
Started Mar 05 01:44:10 PM PST 24
Finished Mar 05 01:44:11 PM PST 24
Peak memory 206004 kb
Host smart-b15bdaf7-72dc-4f23-828b-98ecbce5bab2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4007589662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.4007589662
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.2763474529
Short name T963
Test name
Test status
Simulation time 36216482 ps
CPU time 0.7 seconds
Started Mar 05 01:44:13 PM PST 24
Finished Mar 05 01:44:14 PM PST 24
Peak memory 205712 kb
Host smart-74da10cc-da74-4e9e-8a37-365394719d3e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763474529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.2763474529
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.1264923043
Short name T137
Test name
Test status
Simulation time 435160596 ps
CPU time 2.85 seconds
Started Mar 05 01:44:14 PM PST 24
Finished Mar 05 01:44:18 PM PST 24
Peak memory 206160 kb
Host smart-f32773c5-a179-47c3-9a34-8a447196c161
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1264923043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.1264923043
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.3837370359
Short name T955
Test name
Test status
Simulation time 439432232 ps
CPU time 2.6 seconds
Started Mar 05 01:44:14 PM PST 24
Finished Mar 05 01:44:17 PM PST 24
Peak memory 214480 kb
Host smart-82a53033-f0bc-4942-8fdc-962953587fe4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837370359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.3837370359
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.374787807
Short name T931
Test name
Test status
Simulation time 150167124 ps
CPU time 8.3 seconds
Started Mar 05 01:44:16 PM PST 24
Finished Mar 05 01:44:24 PM PST 24
Peak memory 220384 kb
Host smart-e61ba9ee-5591-4759-a176-f00b644db7e8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374787807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.k
eymgr_shadow_reg_errors_with_csr_rw.374787807
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.3340512036
Short name T920
Test name
Test status
Simulation time 215814255 ps
CPU time 4.23 seconds
Started Mar 05 01:44:14 PM PST 24
Finished Mar 05 01:44:18 PM PST 24
Peak memory 214256 kb
Host smart-e1917228-d002-4e77-bd5c-a023663bf83f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340512036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.3340512036
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.2612739833
Short name T918
Test name
Test status
Simulation time 506239287 ps
CPU time 5.04 seconds
Started Mar 05 01:44:15 PM PST 24
Finished Mar 05 01:44:20 PM PST 24
Peak memory 209188 kb
Host smart-331c19c1-173b-44e4-ae0f-5dfc5f96a654
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612739833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.2612739833
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.1590688491
Short name T169
Test name
Test status
Simulation time 89842537 ps
CPU time 1.52 seconds
Started Mar 05 01:44:09 PM PST 24
Finished Mar 05 01:44:11 PM PST 24
Peak memory 214332 kb
Host smart-98bbdbd1-4685-4ae7-9714-8d4a4d39ea3c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590688491 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.1590688491
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.2752525373
Short name T1049
Test name
Test status
Simulation time 17489950 ps
CPU time 0.89 seconds
Started Mar 05 01:44:15 PM PST 24
Finished Mar 05 01:44:16 PM PST 24
Peak memory 205816 kb
Host smart-92140986-0020-4efe-9c6a-6b1e5dd702b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752525373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.2752525373
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.3003544073
Short name T950
Test name
Test status
Simulation time 14071244 ps
CPU time 0.74 seconds
Started Mar 05 01:44:12 PM PST 24
Finished Mar 05 01:44:13 PM PST 24
Peak memory 205740 kb
Host smart-75feea2b-f2af-45fc-a1cc-91877a643bdb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003544073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.3003544073
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.304756318
Short name T1045
Test name
Test status
Simulation time 51433065 ps
CPU time 1.58 seconds
Started Mar 05 01:44:14 PM PST 24
Finished Mar 05 01:44:16 PM PST 24
Peak memory 206024 kb
Host smart-420e50cc-17b2-4337-8cdf-628d53a2ebe1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=304756318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sam
e_csr_outstanding.304756318
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.3311957235
Short name T1004
Test name
Test status
Simulation time 375830362 ps
CPU time 13.29 seconds
Started Mar 05 01:44:13 PM PST 24
Finished Mar 05 01:44:26 PM PST 24
Peak memory 214604 kb
Host smart-cf31db83-7dce-42b5-a9f5-4589e98b47bf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3311957235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
keymgr_shadow_reg_errors_with_csr_rw.3311957235
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.3804733109
Short name T917
Test name
Test status
Simulation time 1778445097 ps
CPU time 3.25 seconds
Started Mar 05 01:44:11 PM PST 24
Finished Mar 05 01:44:14 PM PST 24
Peak memory 215364 kb
Host smart-bfba43cc-2038-475b-a2b5-211bd60bc87e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3804733109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.3804733109
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.640338631
Short name T159
Test name
Test status
Simulation time 299846696 ps
CPU time 8.66 seconds
Started Mar 05 01:44:12 PM PST 24
Finished Mar 05 01:44:21 PM PST 24
Peak memory 209600 kb
Host smart-95f6a071-0bc2-44fa-b8a2-a3e1cf199ba1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=640338631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err.
640338631
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.4187961972
Short name T1041
Test name
Test status
Simulation time 23389438 ps
CPU time 1.32 seconds
Started Mar 05 01:44:14 PM PST 24
Finished Mar 05 01:44:16 PM PST 24
Peak memory 214332 kb
Host smart-f16c021a-93ab-4c5a-a421-727fe47d7217
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187961972 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.4187961972
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.419616726
Short name T1030
Test name
Test status
Simulation time 41404846 ps
CPU time 0.9 seconds
Started Mar 05 01:44:12 PM PST 24
Finished Mar 05 01:44:13 PM PST 24
Peak memory 205848 kb
Host smart-2a3f95f7-b616-427f-a4a8-bfc538063b56
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419616726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.419616726
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.2214854122
Short name T985
Test name
Test status
Simulation time 26309526 ps
CPU time 0.75 seconds
Started Mar 05 01:44:10 PM PST 24
Finished Mar 05 01:44:11 PM PST 24
Peak memory 205740 kb
Host smart-9c785cd1-a8a1-4559-9d07-882d14788561
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2214854122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.2214854122
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.65872322
Short name T132
Test name
Test status
Simulation time 185224143 ps
CPU time 2.2 seconds
Started Mar 05 01:44:12 PM PST 24
Finished Mar 05 01:44:14 PM PST 24
Peak memory 205996 kb
Host smart-5ecf72c0-2ee5-4627-ac95-74c57328e8f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65872322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_same
_csr_outstanding.65872322
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.2249241765
Short name T112
Test name
Test status
Simulation time 956829832 ps
CPU time 10.54 seconds
Started Mar 05 01:44:15 PM PST 24
Finished Mar 05 01:44:25 PM PST 24
Peak memory 214480 kb
Host smart-db92e126-4a30-42c2-81bc-a361897b8f8e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249241765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.2249241765
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.3426587177
Short name T1029
Test name
Test status
Simulation time 94948068 ps
CPU time 4.13 seconds
Started Mar 05 01:44:14 PM PST 24
Finished Mar 05 01:44:18 PM PST 24
Peak memory 214584 kb
Host smart-25b79b34-9a62-4415-a8ca-0187bbbdd7ad
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3426587177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
keymgr_shadow_reg_errors_with_csr_rw.3426587177
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.3468281732
Short name T1061
Test name
Test status
Simulation time 99899604 ps
CPU time 2.21 seconds
Started Mar 05 01:44:12 PM PST 24
Finished Mar 05 01:44:14 PM PST 24
Peak memory 214232 kb
Host smart-779b1bb0-0e8b-485b-a1fc-52e4f197c6c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468281732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.3468281732
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.3522366038
Short name T940
Test name
Test status
Simulation time 530928186 ps
CPU time 7.33 seconds
Started Mar 05 01:44:15 PM PST 24
Finished Mar 05 01:44:23 PM PST 24
Peak memory 209620 kb
Host smart-8c5f3acb-c3ed-44db-8612-88b39817fd76
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522366038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.3522366038
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.500016599
Short name T1060
Test name
Test status
Simulation time 29059923 ps
CPU time 1.56 seconds
Started Mar 05 01:44:22 PM PST 24
Finished Mar 05 01:44:24 PM PST 24
Peak memory 214248 kb
Host smart-1157d47c-9785-4136-8a56-6f0770156cd1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=500016599 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.500016599
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.745633210
Short name T1066
Test name
Test status
Simulation time 18568554 ps
CPU time 0.93 seconds
Started Mar 05 01:44:20 PM PST 24
Finished Mar 05 01:44:21 PM PST 24
Peak memory 205780 kb
Host smart-83f259b4-fc88-4d4a-bd87-9c3ef5419bc5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745633210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.745633210
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.2752350993
Short name T981
Test name
Test status
Simulation time 10749806 ps
CPU time 0.71 seconds
Started Mar 05 01:44:23 PM PST 24
Finished Mar 05 01:44:24 PM PST 24
Peak memory 205716 kb
Host smart-bd9d8c7b-a459-4c4d-a050-ae5a36d44711
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752350993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.2752350993
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.2514715134
Short name T992
Test name
Test status
Simulation time 119738063 ps
CPU time 2.07 seconds
Started Mar 05 01:44:22 PM PST 24
Finished Mar 05 01:44:25 PM PST 24
Peak memory 206028 kb
Host smart-11e4b54c-5c86-47a0-ae80-f20a92a0035b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2514715134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.2514715134
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.453969044
Short name T113
Test name
Test status
Simulation time 192650144 ps
CPU time 3.28 seconds
Started Mar 05 01:44:10 PM PST 24
Finished Mar 05 01:44:13 PM PST 24
Peak memory 222532 kb
Host smart-6ff131ec-ea1a-4fcb-9a0a-d0c8a7c04665
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453969044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shadow
_reg_errors.453969044
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.4074150568
Short name T919
Test name
Test status
Simulation time 553624897 ps
CPU time 3.99 seconds
Started Mar 05 01:44:21 PM PST 24
Finished Mar 05 01:44:25 PM PST 24
Peak memory 214180 kb
Host smart-90a7252e-58aa-4634-b822-94c37d9c7d11
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074150568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.4074150568
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.2266410142
Short name T150
Test name
Test status
Simulation time 273860872 ps
CPU time 5.56 seconds
Started Mar 05 01:44:21 PM PST 24
Finished Mar 05 01:44:27 PM PST 24
Peak memory 209360 kb
Host smart-83f6bbd4-2d8d-46f4-b8cb-10731f281bd2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2266410142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.2266410142
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.548904589
Short name T799
Test name
Test status
Simulation time 51882346 ps
CPU time 3.67 seconds
Started Mar 05 01:19:06 PM PST 24
Finished Mar 05 01:19:10 PM PST 24
Peak memory 215020 kb
Host smart-16c6924b-8188-4fa6-a8bb-c7b3205f2e59
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=548904589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.548904589
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.2808934906
Short name T751
Test name
Test status
Simulation time 152711461 ps
CPU time 2.45 seconds
Started Mar 05 01:19:15 PM PST 24
Finished Mar 05 01:19:19 PM PST 24
Peak memory 215300 kb
Host smart-77a16635-0393-41ae-b84e-3b52b7816af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2808934906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.2808934906
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.4082789551
Short name T792
Test name
Test status
Simulation time 910345794 ps
CPU time 8.88 seconds
Started Mar 05 01:19:07 PM PST 24
Finished Mar 05 01:19:16 PM PST 24
Peak memory 209404 kb
Host smart-0cacee4a-7e37-44a5-b714-e24d0181e69f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082789551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.4082789551
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.1823215633
Short name T767
Test name
Test status
Simulation time 798996796 ps
CPU time 9.33 seconds
Started Mar 05 01:19:05 PM PST 24
Finished Mar 05 01:19:16 PM PST 24
Peak memory 209044 kb
Host smart-c5742e36-fed9-46ee-bf93-2d88a64052e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823215633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.1823215633
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.1290862232
Short name T352
Test name
Test status
Simulation time 173828447 ps
CPU time 6.7 seconds
Started Mar 05 01:19:16 PM PST 24
Finished Mar 05 01:19:23 PM PST 24
Peak memory 222272 kb
Host smart-aa4e292d-947e-4fe7-a0d7-1a21c73f04e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1290862232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.1290862232
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_random.2118124206
Short name T228
Test name
Test status
Simulation time 998260345 ps
CPU time 3.97 seconds
Started Mar 05 01:19:11 PM PST 24
Finished Mar 05 01:19:17 PM PST 24
Peak memory 207232 kb
Host smart-51fc975a-6f76-4f12-b7fc-49c500482cdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2118124206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.2118124206
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.4193777697
Short name T102
Test name
Test status
Simulation time 1449735259 ps
CPU time 10.84 seconds
Started Mar 05 01:19:07 PM PST 24
Finished Mar 05 01:19:19 PM PST 24
Peak memory 230032 kb
Host smart-ff5104bf-5ab6-409b-b47c-eee65b72ca60
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4193777697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.4193777697
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload.2542390078
Short name T780
Test name
Test status
Simulation time 80852215 ps
CPU time 3.14 seconds
Started Mar 05 01:19:08 PM PST 24
Finished Mar 05 01:19:12 PM PST 24
Peak memory 206304 kb
Host smart-662b3944-3ea4-4f9d-967e-0c3fa7413178
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542390078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.2542390078
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.2173725237
Short name T538
Test name
Test status
Simulation time 191303245 ps
CPU time 2.38 seconds
Started Mar 05 01:19:12 PM PST 24
Finished Mar 05 01:19:15 PM PST 24
Peak memory 206420 kb
Host smart-cfbe399f-1fc3-4bcf-9f9f-984689a0af6b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2173725237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.2173725237
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.2658355049
Short name T562
Test name
Test status
Simulation time 146626301 ps
CPU time 6.15 seconds
Started Mar 05 01:19:04 PM PST 24
Finished Mar 05 01:19:11 PM PST 24
Peak memory 208228 kb
Host smart-bb092aa4-c066-4797-8fcf-c0b399d78068
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2658355049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.2658355049
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.2137112390
Short name T266
Test name
Test status
Simulation time 258788564 ps
CPU time 3.01 seconds
Started Mar 05 01:19:03 PM PST 24
Finished Mar 05 01:19:07 PM PST 24
Peak memory 208264 kb
Host smart-e1f08b88-e1cf-41ff-94a0-3fc3295d0f05
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137112390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.2137112390
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.2678892691
Short name T528
Test name
Test status
Simulation time 335508423 ps
CPU time 4.47 seconds
Started Mar 05 01:19:06 PM PST 24
Finished Mar 05 01:19:11 PM PST 24
Peak memory 209672 kb
Host smart-f0030d1c-99be-4f33-b55b-5cd140f72681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678892691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.2678892691
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.1398728210
Short name T719
Test name
Test status
Simulation time 132613244 ps
CPU time 3.23 seconds
Started Mar 05 01:19:07 PM PST 24
Finished Mar 05 01:19:11 PM PST 24
Peak memory 206376 kb
Host smart-4c6ba20f-9fec-4638-91a0-6322c0d7e08b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1398728210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.1398728210
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.4288894733
Short name T302
Test name
Test status
Simulation time 342946334 ps
CPU time 4.83 seconds
Started Mar 05 01:19:07 PM PST 24
Finished Mar 05 01:19:12 PM PST 24
Peak memory 209472 kb
Host smart-4ee5fbd9-eb6a-4203-8047-852b87770ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288894733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.4288894733
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.1927678480
Short name T830
Test name
Test status
Simulation time 612256728 ps
CPU time 3 seconds
Started Mar 05 01:19:15 PM PST 24
Finished Mar 05 01:19:18 PM PST 24
Peak memory 209528 kb
Host smart-3df6843c-b496-4d95-b5ce-87b290d3ed18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1927678480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.1927678480
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.3889099577
Short name T535
Test name
Test status
Simulation time 37392052 ps
CPU time 0.8 seconds
Started Mar 05 01:19:07 PM PST 24
Finished Mar 05 01:19:08 PM PST 24
Peak memory 205764 kb
Host smart-2a011406-6a52-4c20-90ea-abff35e2869e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889099577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.3889099577
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.1247255879
Short name T223
Test name
Test status
Simulation time 134541441 ps
CPU time 4.91 seconds
Started Mar 05 01:19:05 PM PST 24
Finished Mar 05 01:19:11 PM PST 24
Peak memory 215208 kb
Host smart-fa12f465-60ff-4db4-8ef5-0acbf479b730
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1247255879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.1247255879
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.1645367493
Short name T587
Test name
Test status
Simulation time 119859147 ps
CPU time 4.94 seconds
Started Mar 05 01:19:04 PM PST 24
Finished Mar 05 01:19:10 PM PST 24
Peak memory 214172 kb
Host smart-fe6efbd5-324a-42f2-a409-81689b96aadb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645367493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.1645367493
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.1853577108
Short name T480
Test name
Test status
Simulation time 334489886 ps
CPU time 4.12 seconds
Started Mar 05 01:19:05 PM PST 24
Finished Mar 05 01:19:11 PM PST 24
Peak memory 209696 kb
Host smart-99df52b4-87e3-4a68-abe6-1fc744b01f09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853577108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.1853577108
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.2357705788
Short name T326
Test name
Test status
Simulation time 651065944 ps
CPU time 4.87 seconds
Started Mar 05 01:19:14 PM PST 24
Finished Mar 05 01:19:19 PM PST 24
Peak memory 218928 kb
Host smart-8f8528f6-89a3-4d0d-86a4-4ed6713134df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357705788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.2357705788
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.3648220147
Short name T310
Test name
Test status
Simulation time 452081231 ps
CPU time 5.32 seconds
Started Mar 05 01:19:11 PM PST 24
Finished Mar 05 01:19:17 PM PST 24
Peak memory 210076 kb
Host smart-fb188e0e-a76e-4b55-9e2c-c26713410682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3648220147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.3648220147
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.2195522603
Short name T739
Test name
Test status
Simulation time 8805096344 ps
CPU time 58.99 seconds
Started Mar 05 01:19:17 PM PST 24
Finished Mar 05 01:20:17 PM PST 24
Peak memory 219280 kb
Host smart-65e1cf21-bb1d-49c0-a349-cd828cbccca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2195522603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.2195522603
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.970412650
Short name T12
Test name
Test status
Simulation time 574703709 ps
CPU time 17.48 seconds
Started Mar 05 01:19:06 PM PST 24
Finished Mar 05 01:19:24 PM PST 24
Peak memory 229196 kb
Host smart-4e2d8ff8-f920-4b41-b83b-801ca81e8c07
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970412650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.970412650
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload.2519318219
Short name T252
Test name
Test status
Simulation time 515437245 ps
CPU time 4.86 seconds
Started Mar 05 01:19:05 PM PST 24
Finished Mar 05 01:19:11 PM PST 24
Peak memory 207000 kb
Host smart-e269c892-960b-4bc8-bb6b-5649d50cbc7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519318219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.2519318219
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.2431284468
Short name T13
Test name
Test status
Simulation time 92380836 ps
CPU time 3.97 seconds
Started Mar 05 01:19:06 PM PST 24
Finished Mar 05 01:19:11 PM PST 24
Peak memory 208132 kb
Host smart-93f580a3-73ce-4eef-b146-20b86d5d116a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431284468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.2431284468
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.2834517133
Short name T698
Test name
Test status
Simulation time 197610934 ps
CPU time 6.4 seconds
Started Mar 05 01:19:11 PM PST 24
Finished Mar 05 01:19:18 PM PST 24
Peak memory 207584 kb
Host smart-6247a56e-9d62-4a27-ac29-4c558d176256
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834517133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.2834517133
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.1271593844
Short name T797
Test name
Test status
Simulation time 2857563864 ps
CPU time 55.64 seconds
Started Mar 05 01:19:23 PM PST 24
Finished Mar 05 01:20:24 PM PST 24
Peak memory 208100 kb
Host smart-7b7132a0-c783-4c7e-aaf8-372842d28d7e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1271593844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.1271593844
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.1787066087
Short name T541
Test name
Test status
Simulation time 103717322 ps
CPU time 3.13 seconds
Started Mar 05 01:19:07 PM PST 24
Finished Mar 05 01:19:11 PM PST 24
Peak memory 208040 kb
Host smart-fe873ff5-604e-4af4-8846-dbbfdb46acee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787066087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.1787066087
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.617071532
Short name T505
Test name
Test status
Simulation time 77358461 ps
CPU time 2.29 seconds
Started Mar 05 01:19:08 PM PST 24
Finished Mar 05 01:19:11 PM PST 24
Peak memory 206420 kb
Host smart-4069031c-c748-40a2-b0dd-f038d412e46f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617071532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.617071532
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.3083199464
Short name T847
Test name
Test status
Simulation time 7735940495 ps
CPU time 72.32 seconds
Started Mar 05 01:19:14 PM PST 24
Finished Mar 05 01:20:27 PM PST 24
Peak memory 208616 kb
Host smart-1171be66-f91d-41cb-a2d3-353e34e3c95a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083199464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.3083199464
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.3824888569
Short name T616
Test name
Test status
Simulation time 25595043 ps
CPU time 0.71 seconds
Started Mar 05 01:19:45 PM PST 24
Finished Mar 05 01:19:46 PM PST 24
Peak memory 205880 kb
Host smart-7e716fec-bd33-4d1d-ac0c-f8ad82c45b42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3824888569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.3824888569
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.1004705486
Short name T330
Test name
Test status
Simulation time 623712617 ps
CPU time 3.22 seconds
Started Mar 05 01:19:37 PM PST 24
Finished Mar 05 01:19:41 PM PST 24
Peak memory 214960 kb
Host smart-4e6dd53f-0402-4cb4-8017-8fe530bcf702
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1004705486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.1004705486
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.291722068
Short name T501
Test name
Test status
Simulation time 374495084 ps
CPU time 3.46 seconds
Started Mar 05 01:19:53 PM PST 24
Finished Mar 05 01:19:57 PM PST 24
Peak memory 217884 kb
Host smart-259f5dc2-f54b-4ca2-87f8-7e69040bc3a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291722068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.291722068
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.4222919859
Short name T71
Test name
Test status
Simulation time 100753526 ps
CPU time 3.61 seconds
Started Mar 05 01:19:44 PM PST 24
Finished Mar 05 01:19:48 PM PST 24
Peak memory 210076 kb
Host smart-adf3d140-509f-4bae-aa97-3eea81586209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4222919859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.4222919859
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.2632506870
Short name T261
Test name
Test status
Simulation time 206682812 ps
CPU time 5.13 seconds
Started Mar 05 01:19:41 PM PST 24
Finished Mar 05 01:19:47 PM PST 24
Peak memory 213952 kb
Host smart-e47599d5-476a-48f3-9cac-eaec73730dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632506870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.2632506870
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.3357203964
Short name T100
Test name
Test status
Simulation time 43375056919 ps
CPU time 69.57 seconds
Started Mar 05 01:19:33 PM PST 24
Finished Mar 05 01:20:44 PM PST 24
Peak memory 231208 kb
Host smart-5a741807-348e-4136-8ac6-5ed72dc07027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357203964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.3357203964
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.2244075547
Short name T484
Test name
Test status
Simulation time 115622340 ps
CPU time 3.81 seconds
Started Mar 05 01:19:42 PM PST 24
Finished Mar 05 01:19:46 PM PST 24
Peak memory 214040 kb
Host smart-3e9b2ea0-b213-490c-a06b-c4c54fabd2e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2244075547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.2244075547
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.3253887449
Short name T825
Test name
Test status
Simulation time 494697884 ps
CPU time 5.85 seconds
Started Mar 05 01:19:51 PM PST 24
Finished Mar 05 01:19:57 PM PST 24
Peak memory 209348 kb
Host smart-3677dd24-3e68-434c-bd87-320f6e95ed69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3253887449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.3253887449
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.431602131
Short name T740
Test name
Test status
Simulation time 103259229 ps
CPU time 2.84 seconds
Started Mar 05 01:19:42 PM PST 24
Finished Mar 05 01:19:45 PM PST 24
Peak memory 206364 kb
Host smart-7642f8d1-2547-4cad-ad79-e888e2c4decc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=431602131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.431602131
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.1330200355
Short name T862
Test name
Test status
Simulation time 428149511 ps
CPU time 6.84 seconds
Started Mar 05 01:19:38 PM PST 24
Finished Mar 05 01:19:46 PM PST 24
Peak memory 207500 kb
Host smart-8e3dd441-af84-4dfb-bb29-febead6cb397
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1330200355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.1330200355
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.1760064731
Short name T603
Test name
Test status
Simulation time 75116267 ps
CPU time 3.19 seconds
Started Mar 05 01:19:43 PM PST 24
Finished Mar 05 01:19:46 PM PST 24
Peak memory 206772 kb
Host smart-d7398ff6-f933-4d3c-83e9-8fcf97bce176
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760064731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.1760064731
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.827552600
Short name T287
Test name
Test status
Simulation time 92276545 ps
CPU time 2.76 seconds
Started Mar 05 01:19:37 PM PST 24
Finished Mar 05 01:19:40 PM PST 24
Peak memory 208308 kb
Host smart-ac98bf53-92af-4598-b76f-89fa97306703
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827552600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.827552600
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.2288655085
Short name T667
Test name
Test status
Simulation time 75247698 ps
CPU time 3.42 seconds
Started Mar 05 01:19:40 PM PST 24
Finished Mar 05 01:19:45 PM PST 24
Peak memory 209520 kb
Host smart-e0b8aac0-e10c-4908-a937-fd431cbff777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288655085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.2288655085
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.2694665551
Short name T518
Test name
Test status
Simulation time 2218722830 ps
CPU time 40.01 seconds
Started Mar 05 01:19:43 PM PST 24
Finished Mar 05 01:20:24 PM PST 24
Peak memory 208152 kb
Host smart-d08a4559-7ed4-4336-9e17-52b38d8d082e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694665551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.2694665551
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.2137009512
Short name T756
Test name
Test status
Simulation time 377185131 ps
CPU time 4.67 seconds
Started Mar 05 01:19:36 PM PST 24
Finished Mar 05 01:19:42 PM PST 24
Peak memory 207272 kb
Host smart-1aaa4acc-34af-4722-befd-ad42e7dd4995
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137009512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.2137009512
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.853169847
Short name T380
Test name
Test status
Simulation time 308759554 ps
CPU time 2.93 seconds
Started Mar 05 01:19:51 PM PST 24
Finished Mar 05 01:19:54 PM PST 24
Peak memory 210080 kb
Host smart-93783788-b371-42fc-8d65-26463df7c02d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853169847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.853169847
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.3550296514
Short name T503
Test name
Test status
Simulation time 19085720 ps
CPU time 0.83 seconds
Started Mar 05 01:19:41 PM PST 24
Finished Mar 05 01:19:42 PM PST 24
Peak memory 205780 kb
Host smart-35877a88-a2fc-4ebb-a637-6566e4d83e7b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550296514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.3550296514
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.462091033
Short name T35
Test name
Test status
Simulation time 98707839 ps
CPU time 1.83 seconds
Started Mar 05 01:19:39 PM PST 24
Finished Mar 05 01:19:42 PM PST 24
Peak memory 208600 kb
Host smart-b62d75df-4cc0-411b-86bc-54d618662fa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462091033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.462091033
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.3257219801
Short name T630
Test name
Test status
Simulation time 186033536 ps
CPU time 2.56 seconds
Started Mar 05 01:19:42 PM PST 24
Finished Mar 05 01:19:44 PM PST 24
Peak memory 206448 kb
Host smart-e876c9e3-a901-45a6-be95-008f58bf34c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257219801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.3257219801
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.4224922349
Short name T357
Test name
Test status
Simulation time 140573508 ps
CPU time 4.63 seconds
Started Mar 05 01:20:10 PM PST 24
Finished Mar 05 01:20:15 PM PST 24
Peak memory 214236 kb
Host smart-2ffb2389-6e18-4ec1-906d-f4c74de28bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224922349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.4224922349
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.2888785302
Short name T51
Test name
Test status
Simulation time 492273117 ps
CPU time 3.04 seconds
Started Mar 05 01:19:51 PM PST 24
Finished Mar 05 01:19:55 PM PST 24
Peak memory 215648 kb
Host smart-2e3ce991-1341-4909-b5d7-a1e806da8119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2888785302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.2888785302
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.760441498
Short name T39
Test name
Test status
Simulation time 295815282 ps
CPU time 4.84 seconds
Started Mar 05 01:19:45 PM PST 24
Finished Mar 05 01:19:50 PM PST 24
Peak memory 206632 kb
Host smart-e23596b2-2c2c-488c-a32a-84c001d9d7ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760441498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.760441498
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.1995677607
Short name T360
Test name
Test status
Simulation time 231466177 ps
CPU time 7.51 seconds
Started Mar 05 01:19:51 PM PST 24
Finished Mar 05 01:19:59 PM PST 24
Peak memory 208508 kb
Host smart-f12eade5-59d8-4841-8b65-b8105037d632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995677607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.1995677607
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.654743974
Short name T496
Test name
Test status
Simulation time 248684262 ps
CPU time 6.81 seconds
Started Mar 05 01:19:47 PM PST 24
Finished Mar 05 01:19:54 PM PST 24
Peak memory 208384 kb
Host smart-d83a2409-efa9-4991-8f6a-f3ecfae6fd82
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654743974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.654743974
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.881366527
Short name T647
Test name
Test status
Simulation time 365919766 ps
CPU time 4.33 seconds
Started Mar 05 01:19:44 PM PST 24
Finished Mar 05 01:19:48 PM PST 24
Peak memory 208476 kb
Host smart-26171a28-abe1-48e1-9247-00a9f5e54a83
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=881366527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.881366527
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.139149976
Short name T234
Test name
Test status
Simulation time 666708260 ps
CPU time 5.67 seconds
Started Mar 05 01:19:41 PM PST 24
Finished Mar 05 01:19:47 PM PST 24
Peak memory 207456 kb
Host smart-52bca66d-0005-48cc-863f-bbfc074e5102
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139149976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.139149976
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.137288405
Short name T126
Test name
Test status
Simulation time 64517920 ps
CPU time 3.43 seconds
Started Mar 05 01:19:44 PM PST 24
Finished Mar 05 01:19:47 PM PST 24
Peak memory 209724 kb
Host smart-72d036de-3742-4fd4-966e-3d55a8595670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137288405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.137288405
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.39551341
Short name T687
Test name
Test status
Simulation time 19309657 ps
CPU time 1.77 seconds
Started Mar 05 01:19:44 PM PST 24
Finished Mar 05 01:19:47 PM PST 24
Peak memory 206448 kb
Host smart-434bf135-0a87-4a5e-ac48-4155db1a58d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39551341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.39551341
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.2914071717
Short name T215
Test name
Test status
Simulation time 608002131 ps
CPU time 27.17 seconds
Started Mar 05 01:19:48 PM PST 24
Finished Mar 05 01:20:16 PM PST 24
Peak memory 216280 kb
Host smart-0a0662bc-93b7-4073-9ce3-57f1b22e04d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914071717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.2914071717
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.3446611193
Short name T864
Test name
Test status
Simulation time 1033882299 ps
CPU time 3.64 seconds
Started Mar 05 01:19:50 PM PST 24
Finished Mar 05 01:19:54 PM PST 24
Peak memory 209004 kb
Host smart-491031d5-d41e-4390-a6a4-74095e1e5b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446611193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.3446611193
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.1830612920
Short name T385
Test name
Test status
Simulation time 104566419 ps
CPU time 3.93 seconds
Started Mar 05 01:19:50 PM PST 24
Finished Mar 05 01:19:55 PM PST 24
Peak memory 209744 kb
Host smart-0fef4e0b-ba29-400a-8dd6-c78d528859a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830612920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.1830612920
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.630349355
Short name T428
Test name
Test status
Simulation time 48921542 ps
CPU time 0.86 seconds
Started Mar 05 01:19:38 PM PST 24
Finished Mar 05 01:19:39 PM PST 24
Peak memory 205880 kb
Host smart-a3ef3a63-3d93-41e0-819c-1bd154bf3a19
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630349355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.630349355
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.3962232327
Short name T28
Test name
Test status
Simulation time 212736640 ps
CPU time 2.56 seconds
Started Mar 05 01:19:42 PM PST 24
Finished Mar 05 01:19:45 PM PST 24
Peak memory 208048 kb
Host smart-6d461ab5-987a-4e32-8f90-379939ed8a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962232327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.3962232327
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.1509891967
Short name T572
Test name
Test status
Simulation time 393503648 ps
CPU time 2.2 seconds
Started Mar 05 01:19:49 PM PST 24
Finished Mar 05 01:19:52 PM PST 24
Peak memory 209444 kb
Host smart-91175851-8b99-4b96-98bd-6a4130cfb660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509891967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.1509891967
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.3569480959
Short name T904
Test name
Test status
Simulation time 232945308 ps
CPU time 3.03 seconds
Started Mar 05 01:19:48 PM PST 24
Finished Mar 05 01:19:52 PM PST 24
Peak memory 208052 kb
Host smart-e3aafc95-aff6-44c4-b016-7af578642e84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3569480959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.3569480959
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.3592523068
Short name T520
Test name
Test status
Simulation time 234116044 ps
CPU time 3.43 seconds
Started Mar 05 01:19:45 PM PST 24
Finished Mar 05 01:19:49 PM PST 24
Peak memory 209504 kb
Host smart-3937dcd6-d657-4dce-be17-ea492ec9b2d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592523068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.3592523068
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.158278330
Short name T247
Test name
Test status
Simulation time 737153872 ps
CPU time 6.77 seconds
Started Mar 05 01:19:48 PM PST 24
Finished Mar 05 01:19:55 PM PST 24
Peak memory 218088 kb
Host smart-3ca03809-44b1-430c-b87e-3ac43be47f48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158278330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.158278330
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.1416477647
Short name T514
Test name
Test status
Simulation time 130865512 ps
CPU time 4.11 seconds
Started Mar 05 01:19:46 PM PST 24
Finished Mar 05 01:19:50 PM PST 24
Peak memory 208012 kb
Host smart-1b375267-6824-48fc-9f00-18012ed51ac6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416477647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.1416477647
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.2163270063
Short name T519
Test name
Test status
Simulation time 1964565487 ps
CPU time 20.18 seconds
Started Mar 05 01:19:51 PM PST 24
Finished Mar 05 01:20:12 PM PST 24
Peak memory 208668 kb
Host smart-d87fa0b6-bcc1-4428-93ea-33b6d9f72dd3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163270063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.2163270063
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.3757870561
Short name T812
Test name
Test status
Simulation time 309106268 ps
CPU time 5 seconds
Started Mar 05 01:19:45 PM PST 24
Finished Mar 05 01:19:50 PM PST 24
Peak memory 208336 kb
Host smart-42d4e05d-4567-4b8c-920a-8d3639700cbd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757870561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.3757870561
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.367425898
Short name T688
Test name
Test status
Simulation time 114431297 ps
CPU time 3.13 seconds
Started Mar 05 01:19:55 PM PST 24
Finished Mar 05 01:19:59 PM PST 24
Peak memory 208404 kb
Host smart-28a9fb41-60dc-4d2d-9ba9-fefa140429fc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367425898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.367425898
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.653604315
Short name T433
Test name
Test status
Simulation time 479849423 ps
CPU time 2.19 seconds
Started Mar 05 01:19:46 PM PST 24
Finished Mar 05 01:19:49 PM PST 24
Peak memory 206532 kb
Host smart-c650a2b7-b9b8-4a71-abd8-b2b9afe043e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653604315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.653604315
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.2979437485
Short name T493
Test name
Test status
Simulation time 149985858 ps
CPU time 2.36 seconds
Started Mar 05 01:19:45 PM PST 24
Finished Mar 05 01:19:48 PM PST 24
Peak memory 205936 kb
Host smart-b02c45c0-aa86-4b87-a757-ef3c6bed410a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979437485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.2979437485
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all_with_rand_reset.560002773
Short name T78
Test name
Test status
Simulation time 285862974 ps
CPU time 15.48 seconds
Started Mar 05 01:19:42 PM PST 24
Finished Mar 05 01:19:58 PM PST 24
Peak memory 221412 kb
Host smart-ee35d43c-0688-40c6-aaee-1ffc5611018c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560002773 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all_with_rand_reset.560002773
Directory /workspace/12.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.3565741389
Short name T521
Test name
Test status
Simulation time 345256984 ps
CPU time 4.4 seconds
Started Mar 05 01:19:46 PM PST 24
Finished Mar 05 01:19:50 PM PST 24
Peak memory 209144 kb
Host smart-d7f17a11-abb7-4b5f-8a4f-ac4f5efd88db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565741389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.3565741389
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.256038571
Short name T846
Test name
Test status
Simulation time 50542419 ps
CPU time 0.94 seconds
Started Mar 05 01:19:42 PM PST 24
Finished Mar 05 01:19:43 PM PST 24
Peak memory 205780 kb
Host smart-34c85209-287e-4ff5-b0f7-c0159c122e15
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=256038571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.256038571
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.4136619423
Short name T410
Test name
Test status
Simulation time 119733157 ps
CPU time 4.43 seconds
Started Mar 05 01:19:47 PM PST 24
Finished Mar 05 01:19:51 PM PST 24
Peak memory 215040 kb
Host smart-05f1f142-a69d-4c9a-bd32-f4527dc13dd6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4136619423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.4136619423
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.285448816
Short name T32
Test name
Test status
Simulation time 324220242 ps
CPU time 5.73 seconds
Started Mar 05 01:19:51 PM PST 24
Finished Mar 05 01:19:57 PM PST 24
Peak memory 218628 kb
Host smart-9d82600e-5d83-42c7-b870-d44efb7d33f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285448816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.285448816
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.2248377690
Short name T778
Test name
Test status
Simulation time 122651855 ps
CPU time 3.9 seconds
Started Mar 05 01:19:51 PM PST 24
Finished Mar 05 01:19:55 PM PST 24
Peak memory 209020 kb
Host smart-56129795-c336-47a0-90c4-59d194e6a7e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248377690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.2248377690
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.1437203873
Short name T726
Test name
Test status
Simulation time 340178878 ps
CPU time 4 seconds
Started Mar 05 01:19:51 PM PST 24
Finished Mar 05 01:19:56 PM PST 24
Peak memory 207732 kb
Host smart-ac147874-3ce2-4064-9d7f-3881a1fd1a7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437203873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.1437203873
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.2298766369
Short name T407
Test name
Test status
Simulation time 172332395 ps
CPU time 4.55 seconds
Started Mar 05 01:19:52 PM PST 24
Finished Mar 05 01:19:57 PM PST 24
Peak memory 206380 kb
Host smart-29f33481-695e-44f8-a616-718cb4bb398a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2298766369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.2298766369
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.3370664194
Short name T790
Test name
Test status
Simulation time 87691721 ps
CPU time 3.48 seconds
Started Mar 05 01:19:45 PM PST 24
Finished Mar 05 01:19:49 PM PST 24
Peak memory 208328 kb
Host smart-ab2254ee-ef25-49e8-86ad-794051f30037
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3370664194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.3370664194
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.3152623192
Short name T626
Test name
Test status
Simulation time 227808769 ps
CPU time 3.13 seconds
Started Mar 05 01:19:50 PM PST 24
Finished Mar 05 01:19:53 PM PST 24
Peak memory 206440 kb
Host smart-148b3b72-ba1b-46a9-8726-7fe9a2b392c7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152623192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.3152623192
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.3615420829
Short name T489
Test name
Test status
Simulation time 90891187 ps
CPU time 2.27 seconds
Started Mar 05 01:19:51 PM PST 24
Finished Mar 05 01:19:54 PM PST 24
Peak memory 208844 kb
Host smart-fc7ed6c6-2990-4342-b97d-6d24c4756f22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615420829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.3615420829
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.2730221718
Short name T849
Test name
Test status
Simulation time 238724437 ps
CPU time 3.15 seconds
Started Mar 05 01:19:49 PM PST 24
Finished Mar 05 01:19:53 PM PST 24
Peak memory 208212 kb
Host smart-4344ba12-0742-4501-830d-c77ee907fdca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730221718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.2730221718
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.2687815933
Short name T509
Test name
Test status
Simulation time 995747717 ps
CPU time 8.56 seconds
Started Mar 05 01:19:47 PM PST 24
Finished Mar 05 01:19:56 PM PST 24
Peak memory 208908 kb
Host smart-4678b2b8-0e30-4087-9bdb-ce03bdf27f40
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2687815933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.2687815933
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_stress_all_with_rand_reset.3822958018
Short name T895
Test name
Test status
Simulation time 114865763 ps
CPU time 4.69 seconds
Started Mar 05 01:19:50 PM PST 24
Finished Mar 05 01:19:55 PM PST 24
Peak memory 217456 kb
Host smart-bed14a88-1260-4be0-b8f5-ca7331bbde77
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3822958018 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all_with_rand_reset.3822958018
Directory /workspace/13.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.1622916975
Short name T613
Test name
Test status
Simulation time 136230366 ps
CPU time 5.31 seconds
Started Mar 05 01:19:52 PM PST 24
Finished Mar 05 01:19:58 PM PST 24
Peak memory 209052 kb
Host smart-c619b2fc-e83d-48d7-970f-4ac7233b018e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622916975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.1622916975
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.270597212
Short name T609
Test name
Test status
Simulation time 97694989 ps
CPU time 1.84 seconds
Started Mar 05 01:19:47 PM PST 24
Finished Mar 05 01:19:49 PM PST 24
Peak memory 209484 kb
Host smart-ed8a9396-ef9e-4acf-b829-ce3c89fdf88b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=270597212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.270597212
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.3636026683
Short name T873
Test name
Test status
Simulation time 14438783 ps
CPU time 0.77 seconds
Started Mar 05 01:20:01 PM PST 24
Finished Mar 05 01:20:02 PM PST 24
Peak memory 205876 kb
Host smart-18ea769d-9f77-4ae4-9782-88faf4e72c4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636026683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.3636026683
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.691000606
Short name T772
Test name
Test status
Simulation time 131743350 ps
CPU time 3.65 seconds
Started Mar 05 01:20:00 PM PST 24
Finished Mar 05 01:20:03 PM PST 24
Peak memory 209800 kb
Host smart-fdb340a6-28b3-4bdc-b65f-122f3ba5b046
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691000606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.691000606
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.1769865390
Short name T262
Test name
Test status
Simulation time 123630723 ps
CPU time 3.18 seconds
Started Mar 05 01:19:57 PM PST 24
Finished Mar 05 01:20:00 PM PST 24
Peak memory 214096 kb
Host smart-11f02a04-5c1b-47ef-84de-c340b2b72dda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1769865390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.1769865390
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.1095852834
Short name T355
Test name
Test status
Simulation time 255908648 ps
CPU time 5.66 seconds
Started Mar 05 01:19:54 PM PST 24
Finished Mar 05 01:20:00 PM PST 24
Peak memory 219816 kb
Host smart-6e7299e3-382f-4086-898f-5b11baf2bd16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095852834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.1095852834
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.1265990764
Short name T757
Test name
Test status
Simulation time 86598988 ps
CPU time 4.67 seconds
Started Mar 05 01:19:53 PM PST 24
Finished Mar 05 01:19:58 PM PST 24
Peak memory 207128 kb
Host smart-e16fd56a-204d-4c54-8f17-251b644b560f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1265990764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.1265990764
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.1180094420
Short name T789
Test name
Test status
Simulation time 829324508 ps
CPU time 25.67 seconds
Started Mar 05 01:19:55 PM PST 24
Finished Mar 05 01:20:21 PM PST 24
Peak memory 208576 kb
Host smart-f7b113a5-8cae-4143-b4fe-ea18bf0579db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180094420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.1180094420
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.711453854
Short name T293
Test name
Test status
Simulation time 354544862 ps
CPU time 3.35 seconds
Started Mar 05 01:20:10 PM PST 24
Finished Mar 05 01:20:13 PM PST 24
Peak memory 208360 kb
Host smart-c6fed7a6-585c-40cb-b402-199fc12664bd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711453854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.711453854
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.504646891
Short name T715
Test name
Test status
Simulation time 457372377 ps
CPU time 8.39 seconds
Started Mar 05 01:19:56 PM PST 24
Finished Mar 05 01:20:05 PM PST 24
Peak memory 207752 kb
Host smart-5ca6b82d-6a21-4ac8-9d05-485cd5ccb875
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504646891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.504646891
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.2511909067
Short name T84
Test name
Test status
Simulation time 311676783 ps
CPU time 3.8 seconds
Started Mar 05 01:19:57 PM PST 24
Finished Mar 05 01:20:01 PM PST 24
Peak memory 208048 kb
Host smart-a087636c-f1c6-46ca-b236-67e2327619a0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2511909067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.2511909067
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.3721930583
Short name T227
Test name
Test status
Simulation time 176364553 ps
CPU time 4.79 seconds
Started Mar 05 01:19:51 PM PST 24
Finished Mar 05 01:19:56 PM PST 24
Peak memory 207692 kb
Host smart-dcdb1175-e54f-402f-9bfd-6415fb8be734
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721930583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.3721930583
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.2841585535
Short name T656
Test name
Test status
Simulation time 155070250 ps
CPU time 3.02 seconds
Started Mar 05 01:19:44 PM PST 24
Finished Mar 05 01:19:47 PM PST 24
Peak memory 206244 kb
Host smart-61fcf49b-866a-4a5f-b77f-b68035cb161b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841585535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.2841585535
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.3355245691
Short name T251
Test name
Test status
Simulation time 406178972 ps
CPU time 5.89 seconds
Started Mar 05 01:20:03 PM PST 24
Finished Mar 05 01:20:09 PM PST 24
Peak memory 217808 kb
Host smart-259657d6-3918-45a2-bf89-3999dbf527f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3355245691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.3355245691
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.3437211959
Short name T686
Test name
Test status
Simulation time 156968160 ps
CPU time 3.71 seconds
Started Mar 05 01:19:53 PM PST 24
Finished Mar 05 01:19:57 PM PST 24
Peak memory 208840 kb
Host smart-839db626-c696-47dd-be37-0396a70c6037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437211959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.3437211959
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.306800108
Short name T589
Test name
Test status
Simulation time 62100977 ps
CPU time 2.67 seconds
Started Mar 05 01:20:06 PM PST 24
Finished Mar 05 01:20:08 PM PST 24
Peak memory 209592 kb
Host smart-aca202b3-14cc-4e1d-8d37-cb17a9dcc912
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306800108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.306800108
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.802867088
Short name T604
Test name
Test status
Simulation time 48498196 ps
CPU time 0.76 seconds
Started Mar 05 01:19:52 PM PST 24
Finished Mar 05 01:19:53 PM PST 24
Peak memory 205872 kb
Host smart-fc1b0329-9399-4431-a110-0e4c5d8b6217
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=802867088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.802867088
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.3344469475
Short name T387
Test name
Test status
Simulation time 513320372 ps
CPU time 7.82 seconds
Started Mar 05 01:19:50 PM PST 24
Finished Mar 05 01:19:58 PM PST 24
Peak memory 214000 kb
Host smart-ccf00718-7b22-44b4-99b6-0581061cc5c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3344469475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.3344469475
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.1704022255
Short name T908
Test name
Test status
Simulation time 211317287 ps
CPU time 4.57 seconds
Started Mar 05 01:20:03 PM PST 24
Finished Mar 05 01:20:08 PM PST 24
Peak memory 206832 kb
Host smart-31b3a931-2745-40d3-b29e-d6a69750d6cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704022255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.1704022255
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.2045693521
Short name T88
Test name
Test status
Simulation time 701979209 ps
CPU time 5.38 seconds
Started Mar 05 01:19:49 PM PST 24
Finished Mar 05 01:19:55 PM PST 24
Peak memory 214144 kb
Host smart-0d44ac0c-b61a-4ebc-87ab-9fdb281f11e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045693521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.2045693521
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.3813286629
Short name T64
Test name
Test status
Simulation time 131870069 ps
CPU time 7.24 seconds
Started Mar 05 01:19:51 PM PST 24
Finished Mar 05 01:19:59 PM PST 24
Peak memory 219964 kb
Host smart-066dcb53-0b00-4c78-96d9-f8bfd937129c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813286629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.3813286629
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.3423614807
Short name T359
Test name
Test status
Simulation time 1206891732 ps
CPU time 35.53 seconds
Started Mar 05 01:19:50 PM PST 24
Finished Mar 05 01:20:26 PM PST 24
Peak memory 214064 kb
Host smart-fe9db3e4-bef3-4e1a-b04e-8f5231ab0909
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423614807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.3423614807
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.1182056513
Short name T884
Test name
Test status
Simulation time 7524841655 ps
CPU time 47.63 seconds
Started Mar 05 01:19:56 PM PST 24
Finished Mar 05 01:20:44 PM PST 24
Peak memory 208664 kb
Host smart-75b7d90a-290c-4a6f-a918-1d3b9ac7e6ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182056513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.1182056513
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.2299616644
Short name T878
Test name
Test status
Simulation time 532542122 ps
CPU time 4.6 seconds
Started Mar 05 01:19:57 PM PST 24
Finished Mar 05 01:20:02 PM PST 24
Peak memory 206880 kb
Host smart-e3d90304-ad15-48ab-ba6e-27f84a0b2bcc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2299616644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.2299616644
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.3733075175
Short name T486
Test name
Test status
Simulation time 591519853 ps
CPU time 5.08 seconds
Started Mar 05 01:19:53 PM PST 24
Finished Mar 05 01:19:58 PM PST 24
Peak memory 207420 kb
Host smart-97c5daa5-27b3-4df0-a947-e785512ff315
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733075175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.3733075175
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.409429390
Short name T546
Test name
Test status
Simulation time 58938186 ps
CPU time 2.43 seconds
Started Mar 05 01:19:51 PM PST 24
Finished Mar 05 01:19:54 PM PST 24
Peak memory 215084 kb
Host smart-5bf0e144-3af9-462b-a9bf-b6d073d3879b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409429390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.409429390
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.2023727584
Short name T504
Test name
Test status
Simulation time 1883207354 ps
CPU time 18.62 seconds
Started Mar 05 01:19:57 PM PST 24
Finished Mar 05 01:20:16 PM PST 24
Peak memory 208260 kb
Host smart-5a91470f-c9f3-42a0-b1f3-3317874a9bc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023727584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.2023727584
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.2962557637
Short name T735
Test name
Test status
Simulation time 127405792 ps
CPU time 3.67 seconds
Started Mar 05 01:20:03 PM PST 24
Finished Mar 05 01:20:07 PM PST 24
Peak memory 213908 kb
Host smart-21beb18a-becf-4c34-9ed6-b08fceb1704b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962557637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.2962557637
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.2606502560
Short name T736
Test name
Test status
Simulation time 78330824 ps
CPU time 2.23 seconds
Started Mar 05 01:19:50 PM PST 24
Finished Mar 05 01:19:53 PM PST 24
Peak memory 209292 kb
Host smart-709f7d2c-0be9-4cd5-8882-6a4b8693c500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606502560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.2606502560
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.1134096520
Short name T762
Test name
Test status
Simulation time 34865953 ps
CPU time 0.75 seconds
Started Mar 05 01:20:01 PM PST 24
Finished Mar 05 01:20:02 PM PST 24
Peak memory 205848 kb
Host smart-3cb77aab-5a95-4956-8de2-2cba85968667
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134096520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.1134096520
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.2880117055
Short name T269
Test name
Test status
Simulation time 37653545 ps
CPU time 3 seconds
Started Mar 05 01:19:52 PM PST 24
Finished Mar 05 01:19:55 PM PST 24
Peak memory 215052 kb
Host smart-8038972f-cc3b-4084-92cf-132750045289
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2880117055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.2880117055
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.208607129
Short name T897
Test name
Test status
Simulation time 1770131600 ps
CPU time 4.36 seconds
Started Mar 05 01:19:53 PM PST 24
Finished Mar 05 01:19:58 PM PST 24
Peak memory 209812 kb
Host smart-1757f216-bbd8-4ad8-b33f-f3e4450365e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208607129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.208607129
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.3340968283
Short name T329
Test name
Test status
Simulation time 142374544 ps
CPU time 4.94 seconds
Started Mar 05 01:19:55 PM PST 24
Finished Mar 05 01:20:00 PM PST 24
Peak memory 219152 kb
Host smart-82f08291-6e9b-4c1b-8992-75363e661336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3340968283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.3340968283
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.2690464757
Short name T713
Test name
Test status
Simulation time 98914894 ps
CPU time 3.27 seconds
Started Mar 05 01:19:49 PM PST 24
Finished Mar 05 01:19:52 PM PST 24
Peak memory 219964 kb
Host smart-407fe5f2-fccd-441b-8fd5-153ef32c2dd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2690464757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.2690464757
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.3611389801
Short name T244
Test name
Test status
Simulation time 272229992 ps
CPU time 5.29 seconds
Started Mar 05 01:19:50 PM PST 24
Finished Mar 05 01:19:56 PM PST 24
Peak memory 209408 kb
Host smart-551c4a9c-f95c-41fb-996d-b914d121d64f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611389801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.3611389801
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.1741879463
Short name T577
Test name
Test status
Simulation time 76850326 ps
CPU time 2.31 seconds
Started Mar 05 01:19:57 PM PST 24
Finished Mar 05 01:19:59 PM PST 24
Peak memory 206240 kb
Host smart-6e26a77b-de3b-4f4a-8768-21ae62db268d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741879463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.1741879463
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.2847155720
Short name T267
Test name
Test status
Simulation time 60372349 ps
CPU time 3.07 seconds
Started Mar 05 01:19:49 PM PST 24
Finished Mar 05 01:19:53 PM PST 24
Peak memory 208568 kb
Host smart-def0be62-33a9-492d-a223-de800d4e2308
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847155720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.2847155720
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.2906760471
Short name T458
Test name
Test status
Simulation time 82945376 ps
CPU time 1.74 seconds
Started Mar 05 01:19:54 PM PST 24
Finished Mar 05 01:19:56 PM PST 24
Peak memory 206464 kb
Host smart-b2b6147a-7e71-4c1c-89da-f2df9ccd01fe
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906760471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.2906760471
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.1610073820
Short name T600
Test name
Test status
Simulation time 523343875 ps
CPU time 4.53 seconds
Started Mar 05 01:20:13 PM PST 24
Finished Mar 05 01:20:18 PM PST 24
Peak memory 208076 kb
Host smart-355007a1-b530-4506-993d-8fb59bb341de
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610073820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.1610073820
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.4080030322
Short name T781
Test name
Test status
Simulation time 43637391 ps
CPU time 2.49 seconds
Started Mar 05 01:19:52 PM PST 24
Finished Mar 05 01:19:56 PM PST 24
Peak memory 208712 kb
Host smart-f298e4d9-8867-4fa5-9b7a-51672a96453f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4080030322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.4080030322
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.1144507301
Short name T516
Test name
Test status
Simulation time 25169700 ps
CPU time 1.77 seconds
Started Mar 05 01:19:51 PM PST 24
Finished Mar 05 01:19:52 PM PST 24
Peak memory 206252 kb
Host smart-e6e7e407-d70c-42ef-9d98-3c7cb6aa2602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144507301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.1144507301
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.1952359845
Short name T805
Test name
Test status
Simulation time 1020585909 ps
CPU time 4.09 seconds
Started Mar 05 01:19:56 PM PST 24
Finished Mar 05 01:20:00 PM PST 24
Peak memory 209320 kb
Host smart-80b1d12d-80d7-477e-bb9b-87880e754f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952359845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.1952359845
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.3560806012
Short name T182
Test name
Test status
Simulation time 187978525 ps
CPU time 1.61 seconds
Started Mar 05 01:19:58 PM PST 24
Finished Mar 05 01:20:00 PM PST 24
Peak memory 209116 kb
Host smart-4e79cc47-ec49-4c40-bce4-eb9ee8e193d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560806012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.3560806012
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.2665188714
Short name T573
Test name
Test status
Simulation time 25606440 ps
CPU time 0.89 seconds
Started Mar 05 01:19:49 PM PST 24
Finished Mar 05 01:19:50 PM PST 24
Peak memory 206036 kb
Host smart-2348fe49-f4fe-46ff-ba0e-462457d82180
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665188714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.2665188714
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.2150153945
Short name T388
Test name
Test status
Simulation time 56249599 ps
CPU time 2.39 seconds
Started Mar 05 01:19:53 PM PST 24
Finished Mar 05 01:19:56 PM PST 24
Peak memory 214184 kb
Host smart-acafb1e3-4459-48eb-8d7e-ed6351d154a4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2150153945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.2150153945
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.1021240651
Short name T413
Test name
Test status
Simulation time 384520982 ps
CPU time 3.54 seconds
Started Mar 05 01:19:49 PM PST 24
Finished Mar 05 01:19:52 PM PST 24
Peak memory 218280 kb
Host smart-c5fd899b-4106-4fcf-a757-907c64559992
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021240651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.1021240651
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.2094982854
Short name T284
Test name
Test status
Simulation time 309231976 ps
CPU time 7.05 seconds
Started Mar 05 01:19:52 PM PST 24
Finished Mar 05 01:19:59 PM PST 24
Peak memory 208596 kb
Host smart-8d63080e-ae5b-4833-b9e5-bb27254db54b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2094982854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.2094982854
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.1785957012
Short name T399
Test name
Test status
Simulation time 453331135 ps
CPU time 3.35 seconds
Started Mar 05 01:19:49 PM PST 24
Finished Mar 05 01:19:52 PM PST 24
Peak memory 205924 kb
Host smart-9b563245-9166-4105-940d-a9b27e8c9d1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785957012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.1785957012
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.2001688140
Short name T412
Test name
Test status
Simulation time 193941332 ps
CPU time 2.8 seconds
Started Mar 05 01:20:00 PM PST 24
Finished Mar 05 01:20:03 PM PST 24
Peak memory 207760 kb
Host smart-a3dbd4c6-b3ba-4e46-a412-5438c3de73c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2001688140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.2001688140
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.266184585
Short name T240
Test name
Test status
Simulation time 144935886 ps
CPU time 2.77 seconds
Started Mar 05 01:19:59 PM PST 24
Finished Mar 05 01:20:02 PM PST 24
Peak memory 208288 kb
Host smart-6280f0bc-dd05-47e6-b47b-6a565adf2ba8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266184585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.266184585
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.3777449743
Short name T568
Test name
Test status
Simulation time 332409964 ps
CPU time 2.51 seconds
Started Mar 05 01:20:01 PM PST 24
Finished Mar 05 01:20:04 PM PST 24
Peak memory 206488 kb
Host smart-ce51255e-fff5-4b59-ab71-76b088518f2c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777449743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.3777449743
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.2848903813
Short name T498
Test name
Test status
Simulation time 334836573 ps
CPU time 3.57 seconds
Started Mar 05 01:20:00 PM PST 24
Finished Mar 05 01:20:03 PM PST 24
Peak memory 206228 kb
Host smart-4e8eeb8f-c8bd-432c-b4ea-1987fc6b9ede
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848903813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.2848903813
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.988243437
Short name T242
Test name
Test status
Simulation time 162915869 ps
CPU time 6.08 seconds
Started Mar 05 01:19:50 PM PST 24
Finished Mar 05 01:19:56 PM PST 24
Peak memory 208480 kb
Host smart-5fdc9713-de5e-4770-ab75-7a43e797e2e1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=988243437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.988243437
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.1661972584
Short name T555
Test name
Test status
Simulation time 102465210 ps
CPU time 2.1 seconds
Started Mar 05 01:19:57 PM PST 24
Finished Mar 05 01:19:59 PM PST 24
Peak memory 206348 kb
Host smart-5601fd93-f07f-45ac-9cfb-f9153352fd7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661972584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.1661972584
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.518612672
Short name T397
Test name
Test status
Simulation time 90240037 ps
CPU time 2.56 seconds
Started Mar 05 01:19:58 PM PST 24
Finished Mar 05 01:20:01 PM PST 24
Peak memory 206312 kb
Host smart-43258d91-3f97-4f09-ab31-b2456cca94d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=518612672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.518612672
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.2076050128
Short name T190
Test name
Test status
Simulation time 738442645 ps
CPU time 17.25 seconds
Started Mar 05 01:19:53 PM PST 24
Finished Mar 05 01:20:10 PM PST 24
Peak memory 208572 kb
Host smart-73e4512f-8c9b-4c14-8d6a-12569af5c84a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2076050128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.2076050128
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_stress_all_with_rand_reset.2048560930
Short name T901
Test name
Test status
Simulation time 1244866690 ps
CPU time 9.45 seconds
Started Mar 05 01:20:07 PM PST 24
Finished Mar 05 01:20:17 PM PST 24
Peak memory 218588 kb
Host smart-7f29ec29-462b-4aa3-98fb-c23f33cafa0a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048560930 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all_with_rand_reset.2048560930
Directory /workspace/17.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.3388239194
Short name T599
Test name
Test status
Simulation time 61660543 ps
CPU time 3.45 seconds
Started Mar 05 01:19:59 PM PST 24
Finished Mar 05 01:20:02 PM PST 24
Peak memory 209024 kb
Host smart-be4dc735-3f35-43d0-9c5b-749c607bd713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3388239194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.3388239194
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.93663134
Short name T826
Test name
Test status
Simulation time 50380435 ps
CPU time 0.75 seconds
Started Mar 05 01:19:59 PM PST 24
Finished Mar 05 01:20:00 PM PST 24
Peak memory 205776 kb
Host smart-571f5e3a-a8f3-4cae-896c-9963692e3677
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93663134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.93663134
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.2780242949
Short name T31
Test name
Test status
Simulation time 126457758 ps
CPU time 3.26 seconds
Started Mar 05 01:20:03 PM PST 24
Finished Mar 05 01:20:06 PM PST 24
Peak memory 217244 kb
Host smart-7194feb5-3c55-48d2-8690-8b386f843a8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780242949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.2780242949
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.3256086206
Short name T679
Test name
Test status
Simulation time 58221342 ps
CPU time 1.92 seconds
Started Mar 05 01:20:02 PM PST 24
Finished Mar 05 01:20:04 PM PST 24
Peak memory 206700 kb
Host smart-4dc848f9-d330-47de-a652-7313fbde885d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3256086206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.3256086206
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.2163327880
Short name T693
Test name
Test status
Simulation time 1103316593 ps
CPU time 8.38 seconds
Started Mar 05 01:20:05 PM PST 24
Finished Mar 05 01:20:13 PM PST 24
Peak memory 214028 kb
Host smart-b655344d-ea6f-485d-80ff-3d011c264060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163327880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.2163327880
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.3841943786
Short name T200
Test name
Test status
Simulation time 36712495 ps
CPU time 2.23 seconds
Started Mar 05 01:19:58 PM PST 24
Finished Mar 05 01:20:00 PM PST 24
Peak memory 218740 kb
Host smart-b9ec71f6-180c-4d94-82f1-d6aaf07a6a5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841943786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.3841943786
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.150469823
Short name T231
Test name
Test status
Simulation time 110994041 ps
CPU time 4.94 seconds
Started Mar 05 01:20:29 PM PST 24
Finished Mar 05 01:20:34 PM PST 24
Peak memory 206692 kb
Host smart-3d8032d4-1f37-4a42-b559-d07c7d8d0a52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150469823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.150469823
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.593042751
Short name T683
Test name
Test status
Simulation time 55569996 ps
CPU time 3.1 seconds
Started Mar 05 01:20:01 PM PST 24
Finished Mar 05 01:20:05 PM PST 24
Peak memory 208576 kb
Host smart-8282df5c-d817-4252-84cb-f1b6a9a54bad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593042751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.593042751
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.1729632554
Short name T551
Test name
Test status
Simulation time 185754172 ps
CPU time 2.7 seconds
Started Mar 05 01:20:08 PM PST 24
Finished Mar 05 01:20:11 PM PST 24
Peak memory 206372 kb
Host smart-bc41f7fb-373c-4320-8f56-5db26e56fbad
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1729632554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.1729632554
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.315860853
Short name T515
Test name
Test status
Simulation time 267033918 ps
CPU time 6.39 seconds
Started Mar 05 01:19:58 PM PST 24
Finished Mar 05 01:20:05 PM PST 24
Peak memory 208408 kb
Host smart-b61aafc8-473c-4b77-9fcd-8d2fdd15f580
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315860853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.315860853
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.3477591897
Short name T522
Test name
Test status
Simulation time 3668372455 ps
CPU time 10.66 seconds
Started Mar 05 01:20:08 PM PST 24
Finished Mar 05 01:20:24 PM PST 24
Peak memory 208196 kb
Host smart-6fa61578-6b06-4509-9178-9dbbae310f56
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477591897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.3477591897
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.648681685
Short name T245
Test name
Test status
Simulation time 69859002 ps
CPU time 3.22 seconds
Started Mar 05 01:19:54 PM PST 24
Finished Mar 05 01:19:58 PM PST 24
Peak memory 214064 kb
Host smart-e121fd5a-19ad-4d1e-b7aa-f0f064809f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=648681685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.648681685
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.89701449
Short name T482
Test name
Test status
Simulation time 23879338 ps
CPU time 1.82 seconds
Started Mar 05 01:19:54 PM PST 24
Finished Mar 05 01:19:57 PM PST 24
Peak memory 206408 kb
Host smart-510b8d9a-3bf1-48a7-8412-15da01eb6e8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89701449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.89701449
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.3203945708
Short name T50
Test name
Test status
Simulation time 912266318 ps
CPU time 34.51 seconds
Started Mar 05 01:20:06 PM PST 24
Finished Mar 05 01:20:40 PM PST 24
Peak memory 215828 kb
Host smart-ec0463cd-3bf9-42c4-989d-057b88bc3c76
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3203945708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.3203945708
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_stress_all_with_rand_reset.3065963684
Short name T116
Test name
Test status
Simulation time 116946435 ps
CPU time 7.95 seconds
Started Mar 05 01:20:06 PM PST 24
Finished Mar 05 01:20:14 PM PST 24
Peak memory 222456 kb
Host smart-b8901bfd-1d56-4151-b5b6-210859d2cb54
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3065963684 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all_with_rand_reset.3065963684
Directory /workspace/18.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.3893199819
Short name T787
Test name
Test status
Simulation time 80278597 ps
CPU time 3.91 seconds
Started Mar 05 01:19:58 PM PST 24
Finished Mar 05 01:20:02 PM PST 24
Peak memory 215248 kb
Host smart-8420e252-278b-4470-8ec5-3ba85316b10d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893199819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.3893199819
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.3746197403
Short name T624
Test name
Test status
Simulation time 1217123129 ps
CPU time 3.17 seconds
Started Mar 05 01:19:55 PM PST 24
Finished Mar 05 01:19:59 PM PST 24
Peak memory 209956 kb
Host smart-eef0ced3-f356-423f-83ff-8b6161a8b44a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746197403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.3746197403
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.435940497
Short name T122
Test name
Test status
Simulation time 25768422 ps
CPU time 0.82 seconds
Started Mar 05 01:20:03 PM PST 24
Finished Mar 05 01:20:04 PM PST 24
Peak memory 205780 kb
Host smart-f185c6e8-bc93-4053-be6b-3cb9e6408a7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=435940497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.435940497
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.3507987422
Short name T129
Test name
Test status
Simulation time 285517209 ps
CPU time 8.7 seconds
Started Mar 05 01:20:02 PM PST 24
Finished Mar 05 01:20:10 PM PST 24
Peak memory 214968 kb
Host smart-05ec1a15-458f-42b3-83e8-651c36077853
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3507987422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.3507987422
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.1630897374
Short name T809
Test name
Test status
Simulation time 373152103 ps
CPU time 3.82 seconds
Started Mar 05 01:20:00 PM PST 24
Finished Mar 05 01:20:04 PM PST 24
Peak memory 208676 kb
Host smart-748c0bc1-d5fa-4103-976f-f0bc431efb97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1630897374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.1630897374
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.304850158
Short name T346
Test name
Test status
Simulation time 117339469 ps
CPU time 2.39 seconds
Started Mar 05 01:20:00 PM PST 24
Finished Mar 05 01:20:02 PM PST 24
Peak memory 213952 kb
Host smart-79ebe297-8d31-4a34-a6c6-624c82c1fea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304850158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.304850158
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.3391149683
Short name T692
Test name
Test status
Simulation time 1214213405 ps
CPU time 4.66 seconds
Started Mar 05 01:19:59 PM PST 24
Finished Mar 05 01:20:04 PM PST 24
Peak memory 208976 kb
Host smart-280bf181-0fb3-4a6c-a60e-4d137a70246b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391149683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.3391149683
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.1877527725
Short name T94
Test name
Test status
Simulation time 146633921 ps
CPU time 6.38 seconds
Started Mar 05 01:20:00 PM PST 24
Finished Mar 05 01:20:06 PM PST 24
Peak memory 222080 kb
Host smart-e3263c94-b255-4006-9295-07ec7f136e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877527725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.1877527725
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.510024908
Short name T69
Test name
Test status
Simulation time 78913054 ps
CPU time 3.94 seconds
Started Mar 05 01:20:04 PM PST 24
Finished Mar 05 01:20:08 PM PST 24
Peak memory 217656 kb
Host smart-fb4392ce-5f66-4dd0-8098-8b3e09e4ca40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510024908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.510024908
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.1347705286
Short name T467
Test name
Test status
Simulation time 1273716279 ps
CPU time 9.07 seconds
Started Mar 05 01:20:02 PM PST 24
Finished Mar 05 01:20:11 PM PST 24
Peak memory 207520 kb
Host smart-307a96b8-cd35-446f-acee-7c81b41cfc64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347705286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.1347705286
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.822458163
Short name T472
Test name
Test status
Simulation time 224362689 ps
CPU time 2.78 seconds
Started Mar 05 01:19:59 PM PST 24
Finished Mar 05 01:20:02 PM PST 24
Peak memory 206416 kb
Host smart-6884fe85-b2c0-4f2f-8a4c-e4b9d894c0c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=822458163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.822458163
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.2990968402
Short name T749
Test name
Test status
Simulation time 4470613271 ps
CPU time 37.16 seconds
Started Mar 05 01:20:10 PM PST 24
Finished Mar 05 01:20:47 PM PST 24
Peak memory 208600 kb
Host smart-f70fb05b-8b5d-4d35-b673-713e406e15a5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2990968402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.2990968402
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.1516129778
Short name T495
Test name
Test status
Simulation time 327887857 ps
CPU time 5.35 seconds
Started Mar 05 01:20:20 PM PST 24
Finished Mar 05 01:20:25 PM PST 24
Peak memory 208100 kb
Host smart-c9f2871c-da88-44b4-ae4d-1b8e59c8cc75
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516129778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.1516129778
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.1850980394
Short name T585
Test name
Test status
Simulation time 176664200 ps
CPU time 2.87 seconds
Started Mar 05 01:20:19 PM PST 24
Finished Mar 05 01:20:21 PM PST 24
Peak memory 206456 kb
Host smart-032f0d43-6fda-4d37-a716-d6c9c5d17624
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850980394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.1850980394
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.1050055586
Short name T771
Test name
Test status
Simulation time 54419246 ps
CPU time 2.87 seconds
Started Mar 05 01:20:15 PM PST 24
Finished Mar 05 01:20:18 PM PST 24
Peak memory 208944 kb
Host smart-9e7cef3e-4fd8-4943-b68c-ac5c6abd9696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050055586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.1050055586
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.1465585150
Short name T463
Test name
Test status
Simulation time 348612168 ps
CPU time 7.97 seconds
Started Mar 05 01:20:08 PM PST 24
Finished Mar 05 01:20:16 PM PST 24
Peak memory 206104 kb
Host smart-b2c6f82f-6165-41e7-bbc9-3657f4ff6197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1465585150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.1465585150
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.63006750
Short name T57
Test name
Test status
Simulation time 93407877 ps
CPU time 2.38 seconds
Started Mar 05 01:20:17 PM PST 24
Finished Mar 05 01:20:20 PM PST 24
Peak memory 209788 kb
Host smart-7913692e-02b1-4b81-b792-a7499c7987d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63006750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.63006750
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.2000776863
Short name T748
Test name
Test status
Simulation time 11114843 ps
CPU time 0.9 seconds
Started Mar 05 01:19:01 PM PST 24
Finished Mar 05 01:19:03 PM PST 24
Peak memory 205692 kb
Host smart-6af2c7c0-2234-43c4-894b-50d8aa418f2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000776863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.2000776863
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.3630136831
Short name T123
Test name
Test status
Simulation time 118250418 ps
CPU time 2.63 seconds
Started Mar 05 01:19:05 PM PST 24
Finished Mar 05 01:19:09 PM PST 24
Peak memory 214056 kb
Host smart-d26ba311-ecf1-4f43-9a8e-e288ef707483
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3630136831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.3630136831
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.4260005503
Short name T334
Test name
Test status
Simulation time 61498180 ps
CPU time 2.41 seconds
Started Mar 05 01:19:11 PM PST 24
Finished Mar 05 01:19:14 PM PST 24
Peak memory 209796 kb
Host smart-9a6d7bc5-8ae7-4031-bd66-fa1e48c6456a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260005503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.4260005503
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.1635285751
Short name T291
Test name
Test status
Simulation time 295205063 ps
CPU time 4.44 seconds
Started Mar 05 01:19:17 PM PST 24
Finished Mar 05 01:19:23 PM PST 24
Peak memory 208884 kb
Host smart-0fdfddc6-d1fc-4010-8b53-6b6115d8a01c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635285751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.1635285751
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.2882434939
Short name T709
Test name
Test status
Simulation time 441718024 ps
CPU time 4.81 seconds
Started Mar 05 01:19:09 PM PST 24
Finished Mar 05 01:19:14 PM PST 24
Peak memory 208844 kb
Host smart-5471adb8-fa96-417c-ab09-ba25c9851592
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2882434939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.2882434939
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.2901832177
Short name T279
Test name
Test status
Simulation time 7587514402 ps
CPU time 50.47 seconds
Started Mar 05 01:19:19 PM PST 24
Finished Mar 05 01:20:10 PM PST 24
Peak memory 214144 kb
Host smart-c58cb24c-44fb-4297-aeb0-3614de9f6884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901832177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.2901832177
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.1486467271
Short name T598
Test name
Test status
Simulation time 172743559 ps
CPU time 3.53 seconds
Started Mar 05 01:19:03 PM PST 24
Finished Mar 05 01:19:07 PM PST 24
Peak memory 209636 kb
Host smart-58deb486-f17a-4efa-b9bf-5ee7cbc2a88c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486467271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.1486467271
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.1773770929
Short name T226
Test name
Test status
Simulation time 249226754 ps
CPU time 3.34 seconds
Started Mar 05 01:19:23 PM PST 24
Finished Mar 05 01:19:27 PM PST 24
Peak memory 218004 kb
Host smart-f34a48af-e0f2-4ca5-ae64-ffb45500f6c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1773770929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.1773770929
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sideload.442063701
Short name T341
Test name
Test status
Simulation time 311024250 ps
CPU time 1.97 seconds
Started Mar 05 01:19:01 PM PST 24
Finished Mar 05 01:19:05 PM PST 24
Peak memory 207964 kb
Host smart-047830c4-c446-4ef3-acfb-3f79c3de54bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442063701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.442063701
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.1539475538
Short name T575
Test name
Test status
Simulation time 1672386254 ps
CPU time 54.61 seconds
Started Mar 05 01:19:09 PM PST 24
Finished Mar 05 01:20:04 PM PST 24
Peak memory 208168 kb
Host smart-22637f23-1d3d-49bc-8168-2551248c4ba9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1539475538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.1539475538
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.4107814729
Short name T671
Test name
Test status
Simulation time 22192794 ps
CPU time 1.95 seconds
Started Mar 05 01:19:27 PM PST 24
Finished Mar 05 01:19:29 PM PST 24
Peak memory 207012 kb
Host smart-f28f498b-04be-4a2e-b9c7-54b52c2fa801
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107814729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.4107814729
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.3660380429
Short name T754
Test name
Test status
Simulation time 2778535055 ps
CPU time 19.06 seconds
Started Mar 05 01:19:03 PM PST 24
Finished Mar 05 01:19:23 PM PST 24
Peak memory 208708 kb
Host smart-bc54298e-94d1-4cb5-8c9b-ca3c2b0673f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660380429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.3660380429
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.2758818699
Short name T442
Test name
Test status
Simulation time 5936368959 ps
CPU time 54.17 seconds
Started Mar 05 01:19:19 PM PST 24
Finished Mar 05 01:20:18 PM PST 24
Peak memory 208312 kb
Host smart-10c39efa-7c1d-494d-8c0e-361231e36c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758818699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.2758818699
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.4240695932
Short name T531
Test name
Test status
Simulation time 5096752673 ps
CPU time 43.26 seconds
Started Mar 05 01:19:07 PM PST 24
Finished Mar 05 01:19:51 PM PST 24
Peak memory 220480 kb
Host smart-b49c850f-df2a-4699-ba49-5a144d749816
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240695932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.4240695932
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.3886647694
Short name T659
Test name
Test status
Simulation time 167393442 ps
CPU time 2.46 seconds
Started Mar 05 01:19:13 PM PST 24
Finished Mar 05 01:19:16 PM PST 24
Peak memory 206996 kb
Host smart-3e92bb30-01b2-45ef-9fb1-49104ff85b36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886647694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.3886647694
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.1995212610
Short name T393
Test name
Test status
Simulation time 352458556 ps
CPU time 3.52 seconds
Started Mar 05 01:19:14 PM PST 24
Finished Mar 05 01:19:18 PM PST 24
Peak memory 209584 kb
Host smart-6e88b294-210b-4a26-a4f0-8b4b9bed9232
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995212610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.1995212610
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.2499775992
Short name T597
Test name
Test status
Simulation time 13435922 ps
CPU time 0.77 seconds
Started Mar 05 01:20:17 PM PST 24
Finished Mar 05 01:20:17 PM PST 24
Peak memory 205840 kb
Host smart-a3886a50-5044-413c-b5ee-5c036657fc14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499775992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.2499775992
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.3704882647
Short name T307
Test name
Test status
Simulation time 91301966 ps
CPU time 3.45 seconds
Started Mar 05 01:20:04 PM PST 24
Finished Mar 05 01:20:08 PM PST 24
Peak memory 214180 kb
Host smart-0d31f172-b81b-49e3-ad7a-add35dadc583
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3704882647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.3704882647
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.3627723859
Short name T45
Test name
Test status
Simulation time 1521966048 ps
CPU time 16.36 seconds
Started Mar 05 01:20:14 PM PST 24
Finished Mar 05 01:20:30 PM PST 24
Peak memory 207680 kb
Host smart-8fb0d3da-ef0c-44d0-8067-d38c2d8f75cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627723859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.3627723859
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.2499251814
Short name T281
Test name
Test status
Simulation time 61766168 ps
CPU time 3.81 seconds
Started Mar 05 01:20:14 PM PST 24
Finished Mar 05 01:20:17 PM PST 24
Peak memory 222216 kb
Host smart-c31de523-39b5-4563-917e-574449400413
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499251814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.2499251814
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.3270243328
Short name T475
Test name
Test status
Simulation time 263754427 ps
CPU time 3.52 seconds
Started Mar 05 01:20:02 PM PST 24
Finished Mar 05 01:20:05 PM PST 24
Peak memory 208296 kb
Host smart-eab80e06-a903-4b1e-991e-1feb446dbe56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3270243328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.3270243328
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.2597309525
Short name T623
Test name
Test status
Simulation time 125199614 ps
CPU time 4.56 seconds
Started Mar 05 01:20:10 PM PST 24
Finished Mar 05 01:20:15 PM PST 24
Peak memory 214140 kb
Host smart-3a55eb28-54e0-4627-82a1-9262489b4f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2597309525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.2597309525
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.1674139525
Short name T803
Test name
Test status
Simulation time 439771524 ps
CPU time 8.46 seconds
Started Mar 05 01:19:59 PM PST 24
Finished Mar 05 01:20:07 PM PST 24
Peak memory 207768 kb
Host smart-ecab6353-3ec7-4144-8590-2abce571d3bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1674139525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.1674139525
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.940477527
Short name T696
Test name
Test status
Simulation time 3854445037 ps
CPU time 68.85 seconds
Started Mar 05 01:19:55 PM PST 24
Finished Mar 05 01:21:04 PM PST 24
Peak memory 207600 kb
Host smart-76ac01cb-55c8-43bf-8f31-726e203a1b3c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940477527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.940477527
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.3200277344
Short name T257
Test name
Test status
Simulation time 236202107 ps
CPU time 3.49 seconds
Started Mar 05 01:19:57 PM PST 24
Finished Mar 05 01:20:01 PM PST 24
Peak memory 208036 kb
Host smart-4a914e3d-b29f-4dd7-9156-1427f70b502c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3200277344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.3200277344
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.3904947600
Short name T539
Test name
Test status
Simulation time 139842271 ps
CPU time 3.54 seconds
Started Mar 05 01:20:00 PM PST 24
Finished Mar 05 01:20:03 PM PST 24
Peak memory 207956 kb
Host smart-41803664-0f46-4b04-bb07-3c64b0b50f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3904947600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.3904947600
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.3513159660
Short name T685
Test name
Test status
Simulation time 61096113 ps
CPU time 2.44 seconds
Started Mar 05 01:19:57 PM PST 24
Finished Mar 05 01:20:00 PM PST 24
Peak memory 208224 kb
Host smart-03615136-02bb-4d66-bb2d-265b3d11fa57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513159660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.3513159660
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.1327884072
Short name T230
Test name
Test status
Simulation time 286837549 ps
CPU time 13.52 seconds
Started Mar 05 01:20:12 PM PST 24
Finished Mar 05 01:20:25 PM PST 24
Peak memory 220036 kb
Host smart-7a77777f-4d54-4b9a-a1ec-b3ddf32a1bda
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1327884072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.1327884072
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.2780072232
Short name T246
Test name
Test status
Simulation time 115917903 ps
CPU time 5.09 seconds
Started Mar 05 01:19:53 PM PST 24
Finished Mar 05 01:19:59 PM PST 24
Peak memory 208412 kb
Host smart-26a7625d-f780-465b-ab5b-cdeedba4882a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780072232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.2780072232
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.668969593
Short name T378
Test name
Test status
Simulation time 202815979 ps
CPU time 1.63 seconds
Started Mar 05 01:20:06 PM PST 24
Finished Mar 05 01:20:08 PM PST 24
Peak memory 209516 kb
Host smart-5257f6ed-3202-4c96-a880-a77f0a739f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=668969593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.668969593
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.1368437130
Short name T512
Test name
Test status
Simulation time 11006110 ps
CPU time 0.72 seconds
Started Mar 05 01:20:07 PM PST 24
Finished Mar 05 01:20:08 PM PST 24
Peak memory 205876 kb
Host smart-1a4992f3-d56c-4852-86be-fe746d4414b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1368437130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.1368437130
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.3136840029
Short name T286
Test name
Test status
Simulation time 61426731 ps
CPU time 2.57 seconds
Started Mar 05 01:20:06 PM PST 24
Finished Mar 05 01:20:08 PM PST 24
Peak memory 215276 kb
Host smart-dd112e0f-9a87-4d09-bfec-9ac385493eda
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3136840029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.3136840029
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.4034038962
Short name T673
Test name
Test status
Simulation time 924580915 ps
CPU time 6.81 seconds
Started Mar 05 01:20:02 PM PST 24
Finished Mar 05 01:20:08 PM PST 24
Peak memory 209732 kb
Host smart-105084e6-10ec-412d-85d2-739bc26f75a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4034038962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.4034038962
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.4143536710
Short name T903
Test name
Test status
Simulation time 3469812101 ps
CPU time 51 seconds
Started Mar 05 01:20:01 PM PST 24
Finished Mar 05 01:20:52 PM PST 24
Peak memory 209712 kb
Host smart-cbd72314-f2b3-4cf9-a827-fee6dde0e2af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143536710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.4143536710
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.1897395043
Short name T706
Test name
Test status
Simulation time 269996118 ps
CPU time 7.69 seconds
Started Mar 05 01:20:03 PM PST 24
Finished Mar 05 01:20:10 PM PST 24
Peak memory 208800 kb
Host smart-44415644-c27d-4430-aa99-a053a116f06a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897395043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.1897395043
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.1416965944
Short name T370
Test name
Test status
Simulation time 106571476 ps
CPU time 5.3 seconds
Started Mar 05 01:20:03 PM PST 24
Finished Mar 05 01:20:08 PM PST 24
Peak memory 210172 kb
Host smart-4187b1b5-f3be-49c0-a320-782ec6db1128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416965944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.1416965944
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.2936373714
Short name T55
Test name
Test status
Simulation time 40321192 ps
CPU time 2.99 seconds
Started Mar 05 01:20:02 PM PST 24
Finished Mar 05 01:20:05 PM PST 24
Peak memory 218056 kb
Host smart-09d73f83-acd6-45e3-8851-f3481d0ccf3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936373714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.2936373714
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.1158853017
Short name T534
Test name
Test status
Simulation time 546510285 ps
CPU time 7.47 seconds
Started Mar 05 01:20:19 PM PST 24
Finished Mar 05 01:20:27 PM PST 24
Peak memory 206864 kb
Host smart-c509c43a-58ff-477b-8b7d-6e313d51a03e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158853017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.1158853017
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.3674479099
Short name T870
Test name
Test status
Simulation time 52055525 ps
CPU time 2.81 seconds
Started Mar 05 01:20:03 PM PST 24
Finished Mar 05 01:20:06 PM PST 24
Peak memory 206536 kb
Host smart-811fb0d4-e835-46a4-ad0c-280392d99412
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3674479099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.3674479099
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.4240646850
Short name T367
Test name
Test status
Simulation time 90609770 ps
CPU time 1.95 seconds
Started Mar 05 01:20:13 PM PST 24
Finished Mar 05 01:20:15 PM PST 24
Peak memory 208316 kb
Host smart-e85088e1-35f0-4dce-94e4-28ab769b8cb5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4240646850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.4240646850
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.2079824677
Short name T689
Test name
Test status
Simulation time 996114874 ps
CPU time 6.62 seconds
Started Mar 05 01:20:01 PM PST 24
Finished Mar 05 01:20:08 PM PST 24
Peak memory 208340 kb
Host smart-a68de122-03bb-4453-a727-37209e80fd43
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2079824677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.2079824677
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.3536610013
Short name T669
Test name
Test status
Simulation time 978739191 ps
CPU time 7.12 seconds
Started Mar 05 01:20:10 PM PST 24
Finished Mar 05 01:20:17 PM PST 24
Peak memory 207448 kb
Host smart-9a0fdb81-2122-466a-b1eb-3049841dd4f8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536610013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.3536610013
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.2991684183
Short name T192
Test name
Test status
Simulation time 792949418 ps
CPU time 9.58 seconds
Started Mar 05 01:20:01 PM PST 24
Finished Mar 05 01:20:11 PM PST 24
Peak memory 209508 kb
Host smart-69a25645-afa0-415a-8412-27e5aa3185c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991684183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.2991684183
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.1512407045
Short name T621
Test name
Test status
Simulation time 3781408880 ps
CPU time 45.23 seconds
Started Mar 05 01:20:02 PM PST 24
Finished Mar 05 01:20:47 PM PST 24
Peak memory 207472 kb
Host smart-f52add87-c3dc-4884-956a-ce8fd8b079ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512407045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.1512407045
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.2895765011
Short name T319
Test name
Test status
Simulation time 637399779 ps
CPU time 21.61 seconds
Started Mar 05 01:20:03 PM PST 24
Finished Mar 05 01:20:25 PM PST 24
Peak memory 215824 kb
Host smart-7ae2bc6a-4229-49f2-b1b7-a72816a84797
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2895765011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.2895765011
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.759595045
Short name T902
Test name
Test status
Simulation time 169547851 ps
CPU time 5.3 seconds
Started Mar 05 01:20:17 PM PST 24
Finished Mar 05 01:20:22 PM PST 24
Peak memory 209332 kb
Host smart-43ef2e52-5238-4b28-82ff-ed498da739c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759595045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.759595045
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.2448105550
Short name T383
Test name
Test status
Simulation time 113220631 ps
CPU time 1.64 seconds
Started Mar 05 01:20:14 PM PST 24
Finished Mar 05 01:20:16 PM PST 24
Peak memory 209644 kb
Host smart-ca04d63f-34c8-471a-8997-89eb88ae2336
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448105550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.2448105550
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.1208591866
Short name T800
Test name
Test status
Simulation time 96075694 ps
CPU time 0.86 seconds
Started Mar 05 01:20:10 PM PST 24
Finished Mar 05 01:20:10 PM PST 24
Peak memory 205880 kb
Host smart-7ce57cd1-4123-4e5c-825e-7915279736de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208591866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.1208591866
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.2844172662
Short name T204
Test name
Test status
Simulation time 4481027308 ps
CPU time 15.58 seconds
Started Mar 05 01:19:59 PM PST 24
Finished Mar 05 01:20:14 PM PST 24
Peak memory 222632 kb
Host smart-696159d4-fc48-4411-a8e8-82f033a0ded6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844172662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.2844172662
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.961238953
Short name T655
Test name
Test status
Simulation time 107427060 ps
CPU time 4.11 seconds
Started Mar 05 01:20:04 PM PST 24
Finished Mar 05 01:20:08 PM PST 24
Peak memory 215928 kb
Host smart-07487c0a-abb3-47d1-8e4a-640c591a315d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961238953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.961238953
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.237595332
Short name T253
Test name
Test status
Simulation time 385367433 ps
CPU time 3.94 seconds
Started Mar 05 01:20:09 PM PST 24
Finished Mar 05 01:20:13 PM PST 24
Peak memory 219640 kb
Host smart-f4310c6b-d9dc-45d2-9dce-cd49d69b5c0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237595332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.237595332
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.2248542847
Short name T906
Test name
Test status
Simulation time 217528795 ps
CPU time 6.91 seconds
Started Mar 05 01:20:04 PM PST 24
Finished Mar 05 01:20:11 PM PST 24
Peak memory 210272 kb
Host smart-f70e9b1b-d521-4e58-a9db-4bbf28db5696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248542847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.2248542847
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.3833008838
Short name T658
Test name
Test status
Simulation time 366881970 ps
CPU time 3.4 seconds
Started Mar 05 01:20:09 PM PST 24
Finished Mar 05 01:20:12 PM PST 24
Peak memory 207240 kb
Host smart-aad5f7af-1da3-414e-91ac-c03964c0c377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3833008838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.3833008838
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.1242027724
Short name T725
Test name
Test status
Simulation time 269711488 ps
CPU time 5.92 seconds
Started Mar 05 01:20:16 PM PST 24
Finished Mar 05 01:20:22 PM PST 24
Peak memory 206980 kb
Host smart-9affd710-ad32-4402-996a-a2a13dcd8485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242027724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.1242027724
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.2548722854
Short name T712
Test name
Test status
Simulation time 3308874708 ps
CPU time 44.38 seconds
Started Mar 05 01:20:07 PM PST 24
Finished Mar 05 01:20:52 PM PST 24
Peak memory 207924 kb
Host smart-79e70451-cd72-4d65-93c2-8fe9e184f746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548722854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.2548722854
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.3015777870
Short name T552
Test name
Test status
Simulation time 94996591 ps
CPU time 2.73 seconds
Started Mar 05 01:20:18 PM PST 24
Finished Mar 05 01:20:21 PM PST 24
Peak memory 208436 kb
Host smart-8bb229ae-bac2-4d5e-82bf-63062cdb1940
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015777870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.3015777870
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.3654311470
Short name T796
Test name
Test status
Simulation time 116572585 ps
CPU time 5.06 seconds
Started Mar 05 01:19:56 PM PST 24
Finished Mar 05 01:20:01 PM PST 24
Peak memory 207140 kb
Host smart-4dbf679d-4c7e-4844-af6c-097480880899
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3654311470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.3654311470
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.3800856256
Short name T646
Test name
Test status
Simulation time 642131224 ps
CPU time 3.94 seconds
Started Mar 05 01:20:00 PM PST 24
Finished Mar 05 01:20:04 PM PST 24
Peak memory 207996 kb
Host smart-213f7ffa-95f9-41c4-9ccb-c8635daa9822
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800856256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.3800856256
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.3838394723
Short name T335
Test name
Test status
Simulation time 3128903242 ps
CPU time 21.63 seconds
Started Mar 05 01:20:02 PM PST 24
Finished Mar 05 01:20:23 PM PST 24
Peak memory 209680 kb
Host smart-749b2b2a-d798-4aa3-8a98-7c965cbb96d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838394723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.3838394723
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.1646281473
Short name T391
Test name
Test status
Simulation time 135482440 ps
CPU time 2.56 seconds
Started Mar 05 01:20:00 PM PST 24
Finished Mar 05 01:20:02 PM PST 24
Peak memory 208176 kb
Host smart-f4aedb16-26ef-4ef0-8927-a93581d4a63b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1646281473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.1646281473
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all_with_rand_reset.3549549456
Short name T856
Test name
Test status
Simulation time 179509838 ps
CPU time 5.06 seconds
Started Mar 05 01:19:53 PM PST 24
Finished Mar 05 01:19:59 PM PST 24
Peak memory 222424 kb
Host smart-339f7773-1608-43b2-b1eb-f0aec9a97d43
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3549549456 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all_with_rand_reset.3549549456
Directory /workspace/22.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.139419323
Short name T741
Test name
Test status
Simulation time 5741699288 ps
CPU time 84.76 seconds
Started Mar 05 01:20:08 PM PST 24
Finished Mar 05 01:21:33 PM PST 24
Peak memory 210236 kb
Host smart-b63eae5b-d5d0-444c-9c85-d621990ab9ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139419323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.139419323
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.2644550297
Short name T488
Test name
Test status
Simulation time 46914168 ps
CPU time 1.91 seconds
Started Mar 05 01:20:02 PM PST 24
Finished Mar 05 01:20:04 PM PST 24
Peak memory 209644 kb
Host smart-33a095a9-70a3-4a35-b829-f92e0e94c7dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644550297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.2644550297
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.3165893229
Short name T813
Test name
Test status
Simulation time 12025476 ps
CPU time 0.73 seconds
Started Mar 05 01:20:13 PM PST 24
Finished Mar 05 01:20:14 PM PST 24
Peak memory 205848 kb
Host smart-40fcd618-1681-4411-a826-faa695b93d78
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165893229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.3165893229
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.2914668704
Short name T21
Test name
Test status
Simulation time 486728192 ps
CPU time 2.06 seconds
Started Mar 05 01:19:59 PM PST 24
Finished Mar 05 01:20:01 PM PST 24
Peak memory 216636 kb
Host smart-e8228aab-ba05-4aad-a09b-9b9afb0516c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914668704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.2914668704
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.3646897575
Short name T561
Test name
Test status
Simulation time 2369917539 ps
CPU time 24.46 seconds
Started Mar 05 01:20:18 PM PST 24
Finished Mar 05 01:20:43 PM PST 24
Peak memory 209564 kb
Host smart-0c7f382c-c922-4946-a2ba-6ba1b3a65091
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646897575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.3646897575
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.1098362449
Short name T260
Test name
Test status
Simulation time 134373275 ps
CPU time 5.4 seconds
Started Mar 05 01:20:03 PM PST 24
Finished Mar 05 01:20:08 PM PST 24
Peak memory 220832 kb
Host smart-5986eb84-0dff-4334-86f0-a5e7d4247160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098362449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.1098362449
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.2397277502
Short name T188
Test name
Test status
Simulation time 2502341125 ps
CPU time 17.97 seconds
Started Mar 05 01:20:04 PM PST 24
Finished Mar 05 01:20:22 PM PST 24
Peak memory 213920 kb
Host smart-0772b30a-b532-4e00-bd46-096a784a7aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397277502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.2397277502
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_random.3796890918
Short name T536
Test name
Test status
Simulation time 308285662 ps
CPU time 4.12 seconds
Started Mar 05 01:20:13 PM PST 24
Finished Mar 05 01:20:18 PM PST 24
Peak memory 214064 kb
Host smart-9b3690aa-3fbb-4659-9dcd-1926e8c2dd16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796890918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.3796890918
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.33276119
Short name T633
Test name
Test status
Simulation time 142552398 ps
CPU time 3.94 seconds
Started Mar 05 01:20:10 PM PST 24
Finished Mar 05 01:20:14 PM PST 24
Peak memory 206316 kb
Host smart-08a605b3-110e-406f-869c-8377641bbfbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33276119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.33276119
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.1545336290
Short name T764
Test name
Test status
Simulation time 224464465 ps
CPU time 7.96 seconds
Started Mar 05 01:20:00 PM PST 24
Finished Mar 05 01:20:08 PM PST 24
Peak memory 208356 kb
Host smart-efeba189-fcea-426f-920e-658e9f426968
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1545336290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.1545336290
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.3560469108
Short name T82
Test name
Test status
Simulation time 133866941 ps
CPU time 2.53 seconds
Started Mar 05 01:20:03 PM PST 24
Finished Mar 05 01:20:06 PM PST 24
Peak memory 208192 kb
Host smart-a9ba755b-d44a-40e8-adaa-e51de022fffd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3560469108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.3560469108
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.3898672214
Short name T766
Test name
Test status
Simulation time 55256970 ps
CPU time 2.31 seconds
Started Mar 05 01:20:13 PM PST 24
Finished Mar 05 01:20:16 PM PST 24
Peak memory 208252 kb
Host smart-d33cbb39-005e-4199-bd68-d384541a68aa
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3898672214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.3898672214
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.1567862907
Short name T571
Test name
Test status
Simulation time 72093167 ps
CPU time 2.58 seconds
Started Mar 05 01:20:09 PM PST 24
Finished Mar 05 01:20:12 PM PST 24
Peak memory 218016 kb
Host smart-3baef8b0-823f-4fce-a55b-6042a17f7f9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1567862907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.1567862907
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.1600833724
Short name T885
Test name
Test status
Simulation time 593650762 ps
CPU time 7.52 seconds
Started Mar 05 01:20:01 PM PST 24
Finished Mar 05 01:20:09 PM PST 24
Peak memory 206448 kb
Host smart-b4a66d6d-6e2d-407a-aacc-81b2a4356f73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600833724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.1600833724
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.2311583256
Short name T218
Test name
Test status
Simulation time 620679462 ps
CPU time 30.28 seconds
Started Mar 05 01:20:00 PM PST 24
Finished Mar 05 01:20:31 PM PST 24
Peak memory 220316 kb
Host smart-aaf4938d-8a45-4174-891c-c3432bce888a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311583256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.2311583256
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.3821472574
Short name T349
Test name
Test status
Simulation time 1247927324 ps
CPU time 8.55 seconds
Started Mar 05 01:20:20 PM PST 24
Finished Mar 05 01:20:29 PM PST 24
Peak memory 209636 kb
Host smart-811ae2e2-1f55-404a-87e9-9cf4e024e8e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821472574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.3821472574
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.880466651
Short name T379
Test name
Test status
Simulation time 639955125 ps
CPU time 4.15 seconds
Started Mar 05 01:20:26 PM PST 24
Finished Mar 05 01:20:30 PM PST 24
Peak memory 210524 kb
Host smart-f7d97b65-08b6-41b6-958b-e97dabb908d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880466651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.880466651
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.2937716947
Short name T435
Test name
Test status
Simulation time 9715983 ps
CPU time 0.84 seconds
Started Mar 05 01:20:10 PM PST 24
Finished Mar 05 01:20:11 PM PST 24
Peak memory 205576 kb
Host smart-d178f1b4-e1c6-4e10-80cc-346966660671
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937716947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.2937716947
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.1654002122
Short name T10
Test name
Test status
Simulation time 614192702 ps
CPU time 4.72 seconds
Started Mar 05 01:20:09 PM PST 24
Finished Mar 05 01:20:13 PM PST 24
Peak memory 208816 kb
Host smart-870304ab-0789-45e3-a5d0-7aca29f3d28d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1654002122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.1654002122
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.57081370
Short name T321
Test name
Test status
Simulation time 4927973687 ps
CPU time 28.8 seconds
Started Mar 05 01:20:02 PM PST 24
Finished Mar 05 01:20:31 PM PST 24
Peak memory 218244 kb
Host smart-105e0af3-9f46-4553-a9ba-d3ac7eca58b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=57081370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.57081370
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.2113604190
Short name T87
Test name
Test status
Simulation time 1364774589 ps
CPU time 11.89 seconds
Started Mar 05 01:20:08 PM PST 24
Finished Mar 05 01:20:20 PM PST 24
Peak memory 209568 kb
Host smart-73a39d76-cdf7-4b3e-b1dd-f8cacd7222fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2113604190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.2113604190
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.1389353366
Short name T280
Test name
Test status
Simulation time 125766984 ps
CPU time 6.03 seconds
Started Mar 05 01:20:10 PM PST 24
Finished Mar 05 01:20:17 PM PST 24
Peak memory 209152 kb
Host smart-de2b6eb0-019f-46d1-8fa0-0c6b55817561
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389353366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.1389353366
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.3038224171
Short name T483
Test name
Test status
Simulation time 67723207 ps
CPU time 3.68 seconds
Started Mar 05 01:20:23 PM PST 24
Finished Mar 05 01:20:27 PM PST 24
Peak memory 209236 kb
Host smart-5080f146-4bb2-403b-8f00-a598e30a1809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3038224171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.3038224171
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.2936554563
Short name T729
Test name
Test status
Simulation time 989879620 ps
CPU time 7.89 seconds
Started Mar 05 01:20:02 PM PST 24
Finished Mar 05 01:20:10 PM PST 24
Peak memory 208264 kb
Host smart-2b79f1c0-640e-45a8-ae90-108843b6acaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2936554563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.2936554563
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.2358847897
Short name T309
Test name
Test status
Simulation time 364637789 ps
CPU time 7.4 seconds
Started Mar 05 01:20:07 PM PST 24
Finished Mar 05 01:20:14 PM PST 24
Peak memory 208156 kb
Host smart-ae102e91-1905-4a81-9743-0644164af9c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358847897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.2358847897
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.421938500
Short name T487
Test name
Test status
Simulation time 2978265286 ps
CPU time 36.54 seconds
Started Mar 05 01:20:03 PM PST 24
Finished Mar 05 01:20:40 PM PST 24
Peak memory 207704 kb
Host smart-50d6458b-cb71-483c-b731-fa5780c3c5db
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=421938500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.421938500
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.1386336909
Short name T596
Test name
Test status
Simulation time 424151188 ps
CPU time 2.51 seconds
Started Mar 05 01:20:03 PM PST 24
Finished Mar 05 01:20:05 PM PST 24
Peak memory 208328 kb
Host smart-579443e2-8bd5-43d6-9877-7cdd8bb248e1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386336909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.1386336909
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.4018884247
Short name T676
Test name
Test status
Simulation time 594177850 ps
CPU time 5.08 seconds
Started Mar 05 01:20:02 PM PST 24
Finished Mar 05 01:20:07 PM PST 24
Peak memory 206444 kb
Host smart-b4dbe6cd-54f7-4cf3-ac7b-eeb0a10ae35b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018884247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.4018884247
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.688364457
Short name T782
Test name
Test status
Simulation time 64447887 ps
CPU time 2.69 seconds
Started Mar 05 01:20:07 PM PST 24
Finished Mar 05 01:20:10 PM PST 24
Peak memory 208952 kb
Host smart-889366a0-d6eb-4664-af6d-ff5bd565c1ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688364457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.688364457
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.3055014188
Short name T175
Test name
Test status
Simulation time 134519579 ps
CPU time 2.69 seconds
Started Mar 05 01:19:59 PM PST 24
Finished Mar 05 01:20:02 PM PST 24
Peak memory 206224 kb
Host smart-c39076f7-42b0-4f5d-8f96-d66377faa6e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055014188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.3055014188
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.3981206586
Short name T868
Test name
Test status
Simulation time 9444644435 ps
CPU time 62.29 seconds
Started Mar 05 01:20:12 PM PST 24
Finished Mar 05 01:21:15 PM PST 24
Peak memory 215508 kb
Host smart-927e056e-2886-478e-8b48-26cc7f9af173
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981206586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.3981206586
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.2626148591
Short name T265
Test name
Test status
Simulation time 6329120779 ps
CPU time 66.89 seconds
Started Mar 05 01:20:12 PM PST 24
Finished Mar 05 01:21:19 PM PST 24
Peak memory 208180 kb
Host smart-c34fa2a8-755e-40b2-9cdf-f97dd55be874
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626148591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.2626148591
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.3862497163
Short name T172
Test name
Test status
Simulation time 21086355 ps
CPU time 0.79 seconds
Started Mar 05 01:20:07 PM PST 24
Finished Mar 05 01:20:08 PM PST 24
Peak memory 205772 kb
Host smart-92add004-aedf-42d9-a0bf-7fba607621e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862497163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.3862497163
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.2175660034
Short name T209
Test name
Test status
Simulation time 199037469 ps
CPU time 4.82 seconds
Started Mar 05 01:20:29 PM PST 24
Finished Mar 05 01:20:34 PM PST 24
Peak memory 208112 kb
Host smart-1c47bd4a-2e9f-478a-b6c7-bbae7a5e278e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2175660034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.2175660034
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.4243987849
Short name T294
Test name
Test status
Simulation time 203183159 ps
CPU time 5.69 seconds
Started Mar 05 01:20:17 PM PST 24
Finished Mar 05 01:20:23 PM PST 24
Peak memory 209616 kb
Host smart-864c9871-3b9c-4603-a7f7-16825b5de007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243987849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.4243987849
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.3542509667
Short name T753
Test name
Test status
Simulation time 413024279 ps
CPU time 9.67 seconds
Started Mar 05 01:20:15 PM PST 24
Finished Mar 05 01:20:24 PM PST 24
Peak memory 213996 kb
Host smart-f5e03c0f-97df-4498-ae27-c3143f382f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3542509667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.3542509667
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.3935512731
Short name T53
Test name
Test status
Simulation time 93346542 ps
CPU time 4.39 seconds
Started Mar 05 01:20:21 PM PST 24
Finished Mar 05 01:20:25 PM PST 24
Peak memory 207652 kb
Host smart-1f5bfd13-e7ec-4b81-863a-e321485e2fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935512731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.3935512731
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.2811167702
Short name T684
Test name
Test status
Simulation time 41577619 ps
CPU time 2.85 seconds
Started Mar 05 01:20:16 PM PST 24
Finished Mar 05 01:20:19 PM PST 24
Peak memory 214136 kb
Host smart-4ce2ee14-a6df-4376-ad6b-e07ad08bde77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2811167702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.2811167702
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.3551999280
Short name T547
Test name
Test status
Simulation time 1815119793 ps
CPU time 8.35 seconds
Started Mar 05 01:20:13 PM PST 24
Finished Mar 05 01:20:22 PM PST 24
Peak memory 206404 kb
Host smart-28738577-1895-4384-8cdb-a2929fee58b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551999280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.3551999280
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.4002304662
Short name T468
Test name
Test status
Simulation time 993691538 ps
CPU time 25.25 seconds
Started Mar 05 01:20:14 PM PST 24
Finished Mar 05 01:20:39 PM PST 24
Peak memory 207548 kb
Host smart-0c0f6b30-4629-45cc-bacc-50d5f781ee46
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002304662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.4002304662
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.2681580811
Short name T680
Test name
Test status
Simulation time 123253432 ps
CPU time 3.08 seconds
Started Mar 05 01:20:03 PM PST 24
Finished Mar 05 01:20:06 PM PST 24
Peak memory 208248 kb
Host smart-38452eeb-a985-4592-bd14-d51e9845fb0d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681580811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.2681580811
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.745410739
Short name T358
Test name
Test status
Simulation time 691288122 ps
CPU time 23.45 seconds
Started Mar 05 01:20:09 PM PST 24
Finished Mar 05 01:20:33 PM PST 24
Peak memory 208168 kb
Host smart-2b42272c-d51e-42db-8377-fdcf3d6123cb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745410739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.745410739
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.1617988986
Short name T643
Test name
Test status
Simulation time 207273003 ps
CPU time 3 seconds
Started Mar 05 01:20:31 PM PST 24
Finished Mar 05 01:20:34 PM PST 24
Peak memory 209408 kb
Host smart-80f8b159-0f35-4f55-a942-a73c1b4fbdca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617988986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.1617988986
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.587841356
Short name T545
Test name
Test status
Simulation time 231752486 ps
CPU time 2.92 seconds
Started Mar 05 01:20:10 PM PST 24
Finished Mar 05 01:20:13 PM PST 24
Peak memory 208008 kb
Host smart-b23f689f-96f1-4320-be6a-dad04ea20d2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587841356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.587841356
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.1266391818
Short name T366
Test name
Test status
Simulation time 1082769045 ps
CPU time 16.28 seconds
Started Mar 05 01:20:26 PM PST 24
Finished Mar 05 01:20:43 PM PST 24
Peak memory 208124 kb
Host smart-2db457fc-4ec7-4ccf-9cf5-9af898d4fdc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1266391818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.1266391818
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_stress_all_with_rand_reset.3895364702
Short name T114
Test name
Test status
Simulation time 176154965 ps
CPU time 7.44 seconds
Started Mar 05 01:20:05 PM PST 24
Finished Mar 05 01:20:13 PM PST 24
Peak memory 222280 kb
Host smart-0ad944c3-c0ec-440d-a239-74fe86c2e60f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895364702 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all_with_rand_reset.3895364702
Directory /workspace/25.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.887386577
Short name T769
Test name
Test status
Simulation time 343879387 ps
CPU time 11.81 seconds
Started Mar 05 01:20:11 PM PST 24
Finished Mar 05 01:20:23 PM PST 24
Peak memory 208260 kb
Host smart-67f12ccd-ff3b-46b6-bc59-2da00dbe9f0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=887386577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.887386577
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.2958784310
Short name T471
Test name
Test status
Simulation time 100488275 ps
CPU time 1.35 seconds
Started Mar 05 01:20:10 PM PST 24
Finished Mar 05 01:20:11 PM PST 24
Peak memory 209372 kb
Host smart-d168bde2-d510-4990-aa1a-f7f2a997c3ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958784310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.2958784310
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.3931202386
Short name T759
Test name
Test status
Simulation time 77032944 ps
CPU time 0.95 seconds
Started Mar 05 01:20:07 PM PST 24
Finished Mar 05 01:20:08 PM PST 24
Peak memory 205828 kb
Host smart-4396904d-98dd-4d22-addb-df7f0257f7c3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931202386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.3931202386
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.2821966001
Short name T273
Test name
Test status
Simulation time 758106821 ps
CPU time 27.81 seconds
Started Mar 05 01:20:09 PM PST 24
Finished Mar 05 01:20:37 PM PST 24
Peak memory 214976 kb
Host smart-dd8dec99-4707-4e4a-afe6-0919dcb2a12a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2821966001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.2821966001
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.2703819542
Short name T205
Test name
Test status
Simulation time 1002845633 ps
CPU time 11.49 seconds
Started Mar 05 01:20:12 PM PST 24
Finished Mar 05 01:20:24 PM PST 24
Peak memory 219932 kb
Host smart-d8e5b78d-a28e-4aaa-8ac3-5a38359a2ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2703819542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.2703819542
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.1472239529
Short name T454
Test name
Test status
Simulation time 636753620 ps
CPU time 4.8 seconds
Started Mar 05 01:20:19 PM PST 24
Finished Mar 05 01:20:24 PM PST 24
Peak memory 214040 kb
Host smart-047e90a3-b967-4696-9b60-e796371f6fb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472239529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.1472239529
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.651985099
Short name T91
Test name
Test status
Simulation time 162807480 ps
CPU time 4.08 seconds
Started Mar 05 01:20:29 PM PST 24
Finished Mar 05 01:20:33 PM PST 24
Peak memory 208960 kb
Host smart-18a7b539-e55e-42f9-9840-e07e6e40a100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651985099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.651985099
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.262596175
Short name T195
Test name
Test status
Simulation time 107723731 ps
CPU time 5.41 seconds
Started Mar 05 01:20:09 PM PST 24
Finished Mar 05 01:20:14 PM PST 24
Peak memory 222320 kb
Host smart-bdc5b539-73c7-47c8-8ff8-424736ab79a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262596175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.262596175
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.1593205911
Short name T216
Test name
Test status
Simulation time 151295838 ps
CPU time 5.99 seconds
Started Mar 05 01:20:08 PM PST 24
Finished Mar 05 01:20:14 PM PST 24
Peak memory 220004 kb
Host smart-7c389002-c5e4-4e8f-8d26-b9f2bb418c10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1593205911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.1593205911
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.3524579089
Short name T661
Test name
Test status
Simulation time 139514607 ps
CPU time 5.03 seconds
Started Mar 05 01:20:12 PM PST 24
Finished Mar 05 01:20:17 PM PST 24
Peak memory 207568 kb
Host smart-6526ee44-9270-4c71-8ebf-538b967024c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524579089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.3524579089
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.2078265353
Short name T86
Test name
Test status
Simulation time 6079128212 ps
CPU time 64.79 seconds
Started Mar 05 01:20:25 PM PST 24
Finished Mar 05 01:21:29 PM PST 24
Peak memory 208168 kb
Host smart-f322e12c-2ccf-4b9a-ba92-9ab0382de779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078265353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.2078265353
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.3028099244
Short name T893
Test name
Test status
Simulation time 225565438 ps
CPU time 7.73 seconds
Started Mar 05 01:20:08 PM PST 24
Finished Mar 05 01:20:15 PM PST 24
Peak memory 208572 kb
Host smart-905961e6-9594-4447-9d38-aad491c68a35
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028099244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.3028099244
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.3090963733
Short name T818
Test name
Test status
Simulation time 39231894 ps
CPU time 2.59 seconds
Started Mar 05 01:20:25 PM PST 24
Finished Mar 05 01:20:28 PM PST 24
Peak memory 208152 kb
Host smart-b8237629-0b72-4d39-a14d-1d01a61a3b47
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090963733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.3090963733
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.2012508860
Short name T786
Test name
Test status
Simulation time 58303657 ps
CPU time 2.69 seconds
Started Mar 05 01:20:07 PM PST 24
Finished Mar 05 01:20:10 PM PST 24
Peak memory 206356 kb
Host smart-eb49ec97-0912-40b6-8c1b-85e27e139436
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012508860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.2012508860
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.3243452746
Short name T418
Test name
Test status
Simulation time 422275141 ps
CPU time 4.57 seconds
Started Mar 05 01:20:12 PM PST 24
Finished Mar 05 01:20:17 PM PST 24
Peak memory 217788 kb
Host smart-249018d7-04b6-4e0d-a8a2-0776320354e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243452746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.3243452746
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.1026825002
Short name T443
Test name
Test status
Simulation time 73555726 ps
CPU time 2.16 seconds
Started Mar 05 01:20:11 PM PST 24
Finished Mar 05 01:20:13 PM PST 24
Peak memory 206528 kb
Host smart-4868d8e3-f93b-4b37-92c3-a962e0334cba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1026825002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.1026825002
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.2865361552
Short name T801
Test name
Test status
Simulation time 27986195888 ps
CPU time 45.07 seconds
Started Mar 05 01:20:29 PM PST 24
Finished Mar 05 01:21:14 PM PST 24
Peak memory 215968 kb
Host smart-7d05d6d3-2bde-4e00-8bd8-73fc563921c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2865361552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.2865361552
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.1212954581
Short name T882
Test name
Test status
Simulation time 41486429 ps
CPU time 2.72 seconds
Started Mar 05 01:20:09 PM PST 24
Finished Mar 05 01:20:12 PM PST 24
Peak memory 209000 kb
Host smart-2aac426c-fee4-4d25-afde-871f040101d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1212954581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.1212954581
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.2476197547
Short name T56
Test name
Test status
Simulation time 298552501 ps
CPU time 8.1 seconds
Started Mar 05 01:20:15 PM PST 24
Finished Mar 05 01:20:23 PM PST 24
Peak memory 210440 kb
Host smart-dc186017-0be9-430c-b399-c11e0493cc9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476197547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.2476197547
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.2473040262
Short name T662
Test name
Test status
Simulation time 29044516 ps
CPU time 0.99 seconds
Started Mar 05 01:20:40 PM PST 24
Finished Mar 05 01:20:41 PM PST 24
Peak memory 205868 kb
Host smart-057939d6-ab35-419d-9d45-8b1d8a0abe66
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473040262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.2473040262
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.1146877150
Short name T423
Test name
Test status
Simulation time 59029533 ps
CPU time 4.14 seconds
Started Mar 05 01:20:24 PM PST 24
Finished Mar 05 01:20:29 PM PST 24
Peak memory 214208 kb
Host smart-71439c43-dc70-4caf-8c3b-69fb0c84d549
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1146877150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.1146877150
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.285194881
Short name T220
Test name
Test status
Simulation time 121259025 ps
CPU time 3.89 seconds
Started Mar 05 01:20:26 PM PST 24
Finished Mar 05 01:20:30 PM PST 24
Peak memory 209680 kb
Host smart-e1c21ff4-5749-4b6e-ac3c-c697f3d83d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=285194881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.285194881
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.134417010
Short name T892
Test name
Test status
Simulation time 110497401 ps
CPU time 3.43 seconds
Started Mar 05 01:20:32 PM PST 24
Finished Mar 05 01:20:36 PM PST 24
Peak memory 210316 kb
Host smart-bc18d1b6-85c4-4353-b6b0-f4ce4eea401e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134417010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.134417010
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.1224818225
Short name T374
Test name
Test status
Simulation time 336488195 ps
CPU time 4.38 seconds
Started Mar 05 01:20:11 PM PST 24
Finished Mar 05 01:20:16 PM PST 24
Peak memory 208868 kb
Host smart-f6a107ed-2f5f-4843-a816-3f61cada6ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1224818225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.1224818225
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.1067794850
Short name T239
Test name
Test status
Simulation time 310489011 ps
CPU time 4.34 seconds
Started Mar 05 01:20:10 PM PST 24
Finished Mar 05 01:20:14 PM PST 24
Peak memory 209408 kb
Host smart-326f62e3-76d8-4522-b112-c162569b74be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067794850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.1067794850
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.2392285720
Short name T52
Test name
Test status
Simulation time 43642185 ps
CPU time 2.58 seconds
Started Mar 05 01:20:28 PM PST 24
Finished Mar 05 01:20:31 PM PST 24
Peak memory 214296 kb
Host smart-d10ef459-5f06-401b-9d4e-66f7a8e66eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392285720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.2392285720
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.3667428877
Short name T880
Test name
Test status
Simulation time 272426063 ps
CPU time 10.47 seconds
Started Mar 05 01:20:31 PM PST 24
Finished Mar 05 01:20:42 PM PST 24
Peak memory 214152 kb
Host smart-9af25eaa-ae20-4072-9e8a-92a5172c18e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667428877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.3667428877
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.4143655
Short name T834
Test name
Test status
Simulation time 183827030 ps
CPU time 2.85 seconds
Started Mar 05 01:20:22 PM PST 24
Finished Mar 05 01:20:25 PM PST 24
Peak memory 206420 kb
Host smart-a7930e4b-40c3-4363-8c57-a96a88dbd09f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4143655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.4143655
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.1763921341
Short name T836
Test name
Test status
Simulation time 74488842 ps
CPU time 3.18 seconds
Started Mar 05 01:20:09 PM PST 24
Finished Mar 05 01:20:13 PM PST 24
Peak memory 208256 kb
Host smart-1aba5057-b361-4888-9b61-4a1b4a1dec55
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1763921341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.1763921341
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.2242112751
Short name T807
Test name
Test status
Simulation time 883319456 ps
CPU time 21.69 seconds
Started Mar 05 01:20:28 PM PST 24
Finished Mar 05 01:20:50 PM PST 24
Peak memory 208244 kb
Host smart-598e14e9-e25a-43c6-9eed-f04ca27bfa5c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242112751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.2242112751
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.848353897
Short name T867
Test name
Test status
Simulation time 289831495 ps
CPU time 3.31 seconds
Started Mar 05 01:20:34 PM PST 24
Finished Mar 05 01:20:38 PM PST 24
Peak memory 215556 kb
Host smart-254391e7-c88e-4af7-a500-22b7b5afcccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848353897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.848353897
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.610547864
Short name T738
Test name
Test status
Simulation time 96928977 ps
CPU time 1.84 seconds
Started Mar 05 01:20:17 PM PST 24
Finished Mar 05 01:20:19 PM PST 24
Peak memory 207076 kb
Host smart-96457126-d44b-44ca-813e-004c3f8bde9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=610547864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.610547864
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.1683877073
Short name T497
Test name
Test status
Simulation time 643309791 ps
CPU time 10.02 seconds
Started Mar 05 01:20:08 PM PST 24
Finished Mar 05 01:20:18 PM PST 24
Peak memory 216808 kb
Host smart-5a3ce5ef-a725-4d2d-88af-672f4239b6ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1683877073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.1683877073
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_stress_all_with_rand_reset.2940933865
Short name T368
Test name
Test status
Simulation time 159380563 ps
CPU time 9.11 seconds
Started Mar 05 01:20:10 PM PST 24
Finished Mar 05 01:20:19 PM PST 24
Peak memory 222456 kb
Host smart-74d0a761-eaeb-4f03-a371-f6745170cb78
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940933865 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all_with_rand_reset.2940933865
Directory /workspace/27.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.2179873766
Short name T777
Test name
Test status
Simulation time 2153018312 ps
CPU time 32.09 seconds
Started Mar 05 01:20:23 PM PST 24
Finished Mar 05 01:20:55 PM PST 24
Peak memory 208652 kb
Host smart-bef8ad17-26b6-425a-a2fb-8ff2373f167d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2179873766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.2179873766
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.1683740042
Short name T580
Test name
Test status
Simulation time 97448485 ps
CPU time 2.94 seconds
Started Mar 05 01:20:09 PM PST 24
Finished Mar 05 01:20:12 PM PST 24
Peak memory 209572 kb
Host smart-a47ab31a-3f5a-41cf-9f6a-cc5702197673
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1683740042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.1683740042
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.2046862010
Short name T835
Test name
Test status
Simulation time 9851462 ps
CPU time 0.86 seconds
Started Mar 05 01:20:29 PM PST 24
Finished Mar 05 01:20:30 PM PST 24
Peak memory 205884 kb
Host smart-a36c4a41-f968-487e-93ec-8b730a73a941
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046862010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.2046862010
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.3150860360
Short name T300
Test name
Test status
Simulation time 215847586 ps
CPU time 4.42 seconds
Started Mar 05 01:20:12 PM PST 24
Finished Mar 05 01:20:16 PM PST 24
Peak memory 214152 kb
Host smart-29f2ec3c-0c2d-4a69-903d-ca1cc19f8fa4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3150860360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.3150860360
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.2860249716
Short name T804
Test name
Test status
Simulation time 160460106 ps
CPU time 6.89 seconds
Started Mar 05 01:20:33 PM PST 24
Finished Mar 05 01:20:40 PM PST 24
Peak memory 210188 kb
Host smart-58eb6009-f79f-4a49-9cb5-3fe3bf5b1dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2860249716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.2860249716
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.3557504776
Short name T295
Test name
Test status
Simulation time 118385704 ps
CPU time 2.62 seconds
Started Mar 05 01:20:13 PM PST 24
Finished Mar 05 01:20:16 PM PST 24
Peak memory 214220 kb
Host smart-40da6dbb-04c3-4ab0-b0d6-5cf1a5518052
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557504776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.3557504776
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.3128687227
Short name T851
Test name
Test status
Simulation time 517083637 ps
CPU time 5.46 seconds
Started Mar 05 01:20:29 PM PST 24
Finished Mar 05 01:20:34 PM PST 24
Peak memory 219272 kb
Host smart-48cd9a7e-b16e-4622-ad04-ea03e1cf50a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3128687227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.3128687227
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.439556629
Short name T43
Test name
Test status
Simulation time 56624509 ps
CPU time 2.98 seconds
Started Mar 05 01:20:32 PM PST 24
Finished Mar 05 01:20:35 PM PST 24
Peak memory 209884 kb
Host smart-2b370052-08d7-4b08-af8d-75ce236e7959
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439556629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.439556629
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.3577617906
Short name T663
Test name
Test status
Simulation time 68051475 ps
CPU time 3.39 seconds
Started Mar 05 01:20:10 PM PST 24
Finished Mar 05 01:20:13 PM PST 24
Peak memory 207000 kb
Host smart-b400e4ab-8648-459d-9665-da923cd59250
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577617906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.3577617906
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.974006988
Short name T432
Test name
Test status
Simulation time 1595467371 ps
CPU time 15.82 seconds
Started Mar 05 01:20:29 PM PST 24
Finished Mar 05 01:20:45 PM PST 24
Peak memory 208388 kb
Host smart-ee948a70-407b-4f05-ba40-d6a81bcd9872
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974006988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.974006988
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.1272648491
Short name T479
Test name
Test status
Simulation time 53468388 ps
CPU time 2.13 seconds
Started Mar 05 01:20:07 PM PST 24
Finished Mar 05 01:20:09 PM PST 24
Peak memory 208220 kb
Host smart-4b62916f-ebeb-41c5-bbf3-5643b031dba1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272648491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.1272648491
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.3919737560
Short name T450
Test name
Test status
Simulation time 455758891 ps
CPU time 8.81 seconds
Started Mar 05 01:20:12 PM PST 24
Finished Mar 05 01:20:21 PM PST 24
Peak memory 207608 kb
Host smart-fa2de04f-5f4b-4b7e-b7a5-2bec433ac667
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3919737560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.3919737560
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.3967389102
Short name T500
Test name
Test status
Simulation time 121668332 ps
CPU time 3.28 seconds
Started Mar 05 01:20:11 PM PST 24
Finished Mar 05 01:20:15 PM PST 24
Peak memory 208268 kb
Host smart-905dc6eb-558c-47bb-b368-484f3c9e0932
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967389102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.3967389102
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.626721283
Short name T449
Test name
Test status
Simulation time 65397279 ps
CPU time 1.65 seconds
Started Mar 05 01:20:34 PM PST 24
Finished Mar 05 01:20:36 PM PST 24
Peak memory 207720 kb
Host smart-3a51000c-7d83-4a04-91aa-dfb5835031ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626721283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.626721283
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.2619087215
Short name T733
Test name
Test status
Simulation time 151940785 ps
CPU time 2.48 seconds
Started Mar 05 01:20:10 PM PST 24
Finished Mar 05 01:20:12 PM PST 24
Peak memory 205936 kb
Host smart-e62b2d7f-222c-4ace-8431-015fb5df2fae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619087215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.2619087215
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all_with_rand_reset.2264377990
Short name T54
Test name
Test status
Simulation time 626391335 ps
CPU time 8.25 seconds
Started Mar 05 01:20:20 PM PST 24
Finished Mar 05 01:20:28 PM PST 24
Peak memory 222120 kb
Host smart-0799b6db-aa44-4b69-8223-ee0810966348
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264377990 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all_with_rand_reset.2264377990
Directory /workspace/28.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.386467195
Short name T881
Test name
Test status
Simulation time 40764010 ps
CPU time 3.12 seconds
Started Mar 05 01:20:31 PM PST 24
Finished Mar 05 01:20:34 PM PST 24
Peak memory 209600 kb
Host smart-41b11b75-0897-4325-b51b-10ec1baa4c08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386467195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.386467195
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.143804487
Short name T149
Test name
Test status
Simulation time 113825689 ps
CPU time 1.38 seconds
Started Mar 05 01:20:37 PM PST 24
Finished Mar 05 01:20:39 PM PST 24
Peak memory 209452 kb
Host smart-5da60f72-2f3a-4951-a46f-fe047b454196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143804487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.143804487
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.3629535275
Short name T703
Test name
Test status
Simulation time 31024735 ps
CPU time 0.83 seconds
Started Mar 05 01:20:24 PM PST 24
Finished Mar 05 01:20:25 PM PST 24
Peak memory 205804 kb
Host smart-7c722e40-f201-4a3a-861b-74da3587fe72
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3629535275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.3629535275
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.2774900823
Short name T76
Test name
Test status
Simulation time 329015278 ps
CPU time 2.84 seconds
Started Mar 05 01:20:32 PM PST 24
Finished Mar 05 01:20:35 PM PST 24
Peak memory 208748 kb
Host smart-6b6e55c0-b541-4f1c-90dd-abf79ef3e8cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774900823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.2774900823
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.3797647400
Short name T90
Test name
Test status
Simulation time 852023470 ps
CPU time 6.9 seconds
Started Mar 05 01:20:29 PM PST 24
Finished Mar 05 01:20:36 PM PST 24
Peak memory 209108 kb
Host smart-a42ec0d1-c8d0-4164-8c41-0f4e240f4841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3797647400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.3797647400
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.3227291676
Short name T235
Test name
Test status
Simulation time 333684520 ps
CPU time 3.43 seconds
Started Mar 05 01:20:32 PM PST 24
Finished Mar 05 01:20:36 PM PST 24
Peak memory 214084 kb
Host smart-c5c87d80-1aa4-4517-948c-9a8607d93c3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3227291676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.3227291676
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.2761316108
Short name T324
Test name
Test status
Simulation time 610452924 ps
CPU time 5.13 seconds
Started Mar 05 01:20:16 PM PST 24
Finished Mar 05 01:20:21 PM PST 24
Peak memory 215240 kb
Host smart-3fdca5b1-f081-4be7-9390-9360615b5b56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761316108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.2761316108
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.251534578
Short name T288
Test name
Test status
Simulation time 50325673 ps
CPU time 3.34 seconds
Started Mar 05 01:20:22 PM PST 24
Finished Mar 05 01:20:26 PM PST 24
Peak memory 206828 kb
Host smart-60b5e7d7-e725-4e1e-9b5d-38ddab9f42cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251534578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.251534578
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.1218955223
Short name T815
Test name
Test status
Simulation time 65638391 ps
CPU time 2.76 seconds
Started Mar 05 01:20:18 PM PST 24
Finished Mar 05 01:20:21 PM PST 24
Peak memory 208232 kb
Host smart-4b9402f2-2b5a-4b08-a3be-72d55e9de910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218955223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.1218955223
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.233743323
Short name T402
Test name
Test status
Simulation time 88646916 ps
CPU time 4 seconds
Started Mar 05 01:20:30 PM PST 24
Finished Mar 05 01:20:34 PM PST 24
Peak memory 208240 kb
Host smart-ccbfb7b5-b6d1-4623-a9a9-e6aab1efd125
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=233743323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.233743323
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.741637226
Short name T811
Test name
Test status
Simulation time 199135143 ps
CPU time 2.87 seconds
Started Mar 05 01:20:32 PM PST 24
Finished Mar 05 01:20:36 PM PST 24
Peak memory 206484 kb
Host smart-7bfe72bc-1b99-42fe-94ad-dc6bbe75e5d2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=741637226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.741637226
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.2638700347
Short name T857
Test name
Test status
Simulation time 493290211 ps
CPU time 6.73 seconds
Started Mar 05 01:20:15 PM PST 24
Finished Mar 05 01:20:22 PM PST 24
Peak memory 207288 kb
Host smart-afcfc9e2-e621-4a1c-ac5c-c63de5844af1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2638700347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.2638700347
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.2822949288
Short name T16
Test name
Test status
Simulation time 271398969 ps
CPU time 9.2 seconds
Started Mar 05 01:20:32 PM PST 24
Finished Mar 05 01:20:42 PM PST 24
Peak memory 214112 kb
Host smart-c61aca39-16e4-4f98-96bf-9c34e55e46eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822949288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.2822949288
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.3972807606
Short name T752
Test name
Test status
Simulation time 268977013 ps
CPU time 3.94 seconds
Started Mar 05 01:20:23 PM PST 24
Finished Mar 05 01:20:27 PM PST 24
Peak memory 208064 kb
Host smart-1a53b24a-6057-4fc0-936b-adf99d7a4fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972807606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.3972807606
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.3303438126
Short name T348
Test name
Test status
Simulation time 50220956967 ps
CPU time 494.43 seconds
Started Mar 05 01:20:29 PM PST 24
Finished Mar 05 01:28:43 PM PST 24
Peak memory 219608 kb
Host smart-28cb2fe3-34aa-4414-98cf-a908d4f1d16d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303438126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.3303438126
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.1608922067
Short name T476
Test name
Test status
Simulation time 840329529 ps
CPU time 3.66 seconds
Started Mar 05 01:20:40 PM PST 24
Finished Mar 05 01:20:44 PM PST 24
Peak memory 208196 kb
Host smart-1a55f935-0867-4bc6-abf4-1da6f7a51e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1608922067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.1608922067
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.2288535147
Short name T181
Test name
Test status
Simulation time 496728450 ps
CPU time 3.87 seconds
Started Mar 05 01:20:32 PM PST 24
Finished Mar 05 01:20:37 PM PST 24
Peak memory 210088 kb
Host smart-6fe6d31c-e54f-4f5a-8825-661a12eed455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288535147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.2288535147
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.1695355178
Short name T429
Test name
Test status
Simulation time 193580931 ps
CPU time 0.94 seconds
Started Mar 05 01:19:30 PM PST 24
Finished Mar 05 01:19:31 PM PST 24
Peak memory 205844 kb
Host smart-17ce0178-cbf4-4745-9d50-96cfbd52c520
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695355178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.1695355178
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.3920722200
Short name T229
Test name
Test status
Simulation time 207788006 ps
CPU time 7.88 seconds
Started Mar 05 01:19:07 PM PST 24
Finished Mar 05 01:19:16 PM PST 24
Peak memory 214204 kb
Host smart-546a1e16-ecab-4eaa-90d4-8833597cb51a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3920722200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.3920722200
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.3635760010
Short name T650
Test name
Test status
Simulation time 149050833 ps
CPU time 5.82 seconds
Started Mar 05 01:19:09 PM PST 24
Finished Mar 05 01:19:15 PM PST 24
Peak memory 216472 kb
Host smart-8f785fa5-c51b-4ab8-ae5d-5b10cbb42990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635760010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.3635760010
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.989151240
Short name T666
Test name
Test status
Simulation time 2690848043 ps
CPU time 23.27 seconds
Started Mar 05 01:19:16 PM PST 24
Finished Mar 05 01:19:41 PM PST 24
Peak memory 208676 kb
Host smart-4e66d05b-523c-44e5-994b-9cc085ad3be9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989151240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.989151240
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.3124663374
Short name T548
Test name
Test status
Simulation time 256668926 ps
CPU time 3.52 seconds
Started Mar 05 01:19:15 PM PST 24
Finished Mar 05 01:19:19 PM PST 24
Peak memory 208976 kb
Host smart-c76add8d-e2a5-4069-8c4c-f16ec74fc3ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124663374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.3124663374
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.2855492548
Short name T276
Test name
Test status
Simulation time 293839977 ps
CPU time 4.25 seconds
Started Mar 05 01:19:36 PM PST 24
Finished Mar 05 01:19:41 PM PST 24
Peak memory 210104 kb
Host smart-4f304658-cfe2-42d2-be65-d1366700e622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855492548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.2855492548
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.3723373972
Short name T697
Test name
Test status
Simulation time 263455539 ps
CPU time 4.18 seconds
Started Mar 05 01:19:10 PM PST 24
Finished Mar 05 01:19:15 PM PST 24
Peak memory 219668 kb
Host smart-c94f05c5-a091-4df7-8a56-480f1e6a87f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723373972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.3723373972
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.778708214
Short name T843
Test name
Test status
Simulation time 65221589 ps
CPU time 3.65 seconds
Started Mar 05 01:19:27 PM PST 24
Finished Mar 05 01:19:30 PM PST 24
Peak memory 206620 kb
Host smart-4d1cfa5a-d767-40e5-a72a-4629f6480c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778708214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.778708214
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.2734917210
Short name T103
Test name
Test status
Simulation time 5329860257 ps
CPU time 130.8 seconds
Started Mar 05 01:19:14 PM PST 24
Finished Mar 05 01:21:25 PM PST 24
Peak memory 273072 kb
Host smart-b1af42dc-334f-4344-9d0f-83971503e93e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734917210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.2734917210
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sideload.962909336
Short name T233
Test name
Test status
Simulation time 74230937 ps
CPU time 1.91 seconds
Started Mar 05 01:19:07 PM PST 24
Finished Mar 05 01:19:09 PM PST 24
Peak memory 206380 kb
Host smart-c4b5a9f7-914e-43b9-b42b-6112307a0086
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962909336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.962909336
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.623778958
Short name T850
Test name
Test status
Simulation time 114620087 ps
CPU time 3.17 seconds
Started Mar 05 01:19:14 PM PST 24
Finished Mar 05 01:19:18 PM PST 24
Peak memory 208324 kb
Host smart-59c14ffa-039c-45ac-96bd-55e5735cfd0e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623778958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.623778958
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.1665926622
Short name T765
Test name
Test status
Simulation time 336537966 ps
CPU time 2.79 seconds
Started Mar 05 01:19:11 PM PST 24
Finished Mar 05 01:19:14 PM PST 24
Peak memory 206448 kb
Host smart-76d8a551-f65a-4244-b2bd-e472a42f496c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1665926622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.1665926622
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.1618697220
Short name T720
Test name
Test status
Simulation time 160538041 ps
CPU time 4.62 seconds
Started Mar 05 01:19:14 PM PST 24
Finished Mar 05 01:19:19 PM PST 24
Peak memory 208076 kb
Host smart-4750da49-0176-4ed9-b061-64323d7ed7f4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1618697220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.1618697220
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.2541892331
Short name T17
Test name
Test status
Simulation time 1277254093 ps
CPU time 20.47 seconds
Started Mar 05 01:19:24 PM PST 24
Finished Mar 05 01:19:45 PM PST 24
Peak memory 208572 kb
Host smart-14a42328-2731-43d6-8813-062c844dd920
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541892331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.2541892331
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.541070895
Short name T563
Test name
Test status
Simulation time 505008009 ps
CPU time 4.21 seconds
Started Mar 05 01:19:20 PM PST 24
Finished Mar 05 01:19:25 PM PST 24
Peak memory 206352 kb
Host smart-5e8ff142-0b18-4e98-859b-b3251ddf76e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541070895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.541070895
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.4199687742
Short name T342
Test name
Test status
Simulation time 5882391753 ps
CPU time 192.64 seconds
Started Mar 05 01:19:10 PM PST 24
Finished Mar 05 01:22:23 PM PST 24
Peak memory 216684 kb
Host smart-b2c741ba-7c13-4c4f-89ae-bc6848def3d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4199687742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.4199687742
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.1330739253
Short name T891
Test name
Test status
Simulation time 166243635 ps
CPU time 4 seconds
Started Mar 05 01:19:13 PM PST 24
Finished Mar 05 01:19:17 PM PST 24
Peak memory 206948 kb
Host smart-957f5f78-770d-401e-8c2d-d505d897a923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330739253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.1330739253
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.3349302761
Short name T118
Test name
Test status
Simulation time 333681622 ps
CPU time 3.43 seconds
Started Mar 05 01:19:09 PM PST 24
Finished Mar 05 01:19:12 PM PST 24
Peak memory 209772 kb
Host smart-6a4489dc-44ad-45e0-a36d-d3eed33faea8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3349302761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.3349302761
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.2004842615
Short name T543
Test name
Test status
Simulation time 62013141 ps
CPU time 0.77 seconds
Started Mar 05 01:20:37 PM PST 24
Finished Mar 05 01:20:38 PM PST 24
Peak memory 205740 kb
Host smart-e512fca0-a338-4795-81e1-968b1a208c17
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2004842615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.2004842615
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.2989569083
Short name T755
Test name
Test status
Simulation time 433305391 ps
CPU time 12.79 seconds
Started Mar 05 01:20:38 PM PST 24
Finished Mar 05 01:20:51 PM PST 24
Peak memory 214484 kb
Host smart-2d2c2fea-2cd5-4ee4-a87f-a8c06a8c5dd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989569083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.2989569083
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.21682516
Short name T831
Test name
Test status
Simulation time 140881332 ps
CPU time 4.14 seconds
Started Mar 05 01:20:46 PM PST 24
Finished Mar 05 01:20:51 PM PST 24
Peak memory 208040 kb
Host smart-d0f5931f-cc80-4373-8a77-ecd3216fe152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21682516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.21682516
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.2297554376
Short name T406
Test name
Test status
Simulation time 434271138 ps
CPU time 5.19 seconds
Started Mar 05 01:20:23 PM PST 24
Finished Mar 05 01:20:28 PM PST 24
Peak memory 214000 kb
Host smart-14751299-1b3a-4dca-8d8d-69da766ef863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2297554376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.2297554376
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.4038330012
Short name T874
Test name
Test status
Simulation time 222220205 ps
CPU time 4.02 seconds
Started Mar 05 01:20:49 PM PST 24
Finished Mar 05 01:20:53 PM PST 24
Peak memory 211592 kb
Host smart-503ef999-28c1-48e9-b117-3ce44f2518f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038330012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.4038330012
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.3662728137
Short name T785
Test name
Test status
Simulation time 256953779 ps
CPU time 7.27 seconds
Started Mar 05 01:20:24 PM PST 24
Finished Mar 05 01:20:37 PM PST 24
Peak memory 209392 kb
Host smart-f31e7284-f932-4c9c-a24e-7b69f1865c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662728137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.3662728137
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.1637048071
Short name T695
Test name
Test status
Simulation time 8067975953 ps
CPU time 51.25 seconds
Started Mar 05 01:20:37 PM PST 24
Finished Mar 05 01:21:28 PM PST 24
Peak memory 208068 kb
Host smart-1d39dacb-d0ea-4468-a529-a7b96d0c9d81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637048071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.1637048071
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.246648332
Short name T364
Test name
Test status
Simulation time 7875326701 ps
CPU time 55.32 seconds
Started Mar 05 01:20:33 PM PST 24
Finished Mar 05 01:21:29 PM PST 24
Peak memory 208756 kb
Host smart-a4631bc0-42ce-469b-b3ba-0af3b90e5476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246648332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.246648332
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.3751507478
Short name T390
Test name
Test status
Simulation time 113475208 ps
CPU time 4.03 seconds
Started Mar 05 01:20:29 PM PST 24
Finished Mar 05 01:20:33 PM PST 24
Peak memory 207580 kb
Host smart-50587172-b6dd-42a5-ad34-b3c78eda9609
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751507478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.3751507478
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.355235566
Short name T682
Test name
Test status
Simulation time 46633954 ps
CPU time 2.52 seconds
Started Mar 05 01:20:36 PM PST 24
Finished Mar 05 01:20:38 PM PST 24
Peak memory 206500 kb
Host smart-5b0496ac-8e6d-4799-af4c-79830f69d3c7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=355235566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.355235566
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.3774523698
Short name T196
Test name
Test status
Simulation time 56019461 ps
CPU time 2.9 seconds
Started Mar 05 01:20:40 PM PST 24
Finished Mar 05 01:20:44 PM PST 24
Peak memory 208344 kb
Host smart-fd3abc07-3e53-4679-a4de-3b7f74ecdc9f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774523698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.3774523698
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.1139810235
Short name T838
Test name
Test status
Simulation time 263128750 ps
CPU time 3.03 seconds
Started Mar 05 01:20:33 PM PST 24
Finished Mar 05 01:20:36 PM PST 24
Peak memory 209544 kb
Host smart-21015cef-b805-4435-bcd6-64974984d838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1139810235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.1139810235
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.3460360410
Short name T405
Test name
Test status
Simulation time 100825147 ps
CPU time 2.29 seconds
Started Mar 05 01:20:35 PM PST 24
Finished Mar 05 01:20:38 PM PST 24
Peak memory 206416 kb
Host smart-8304470c-31ea-4645-9f5f-75e901f2a664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3460360410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.3460360410
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.3517449097
Short name T250
Test name
Test status
Simulation time 103656604 ps
CPU time 3.75 seconds
Started Mar 05 01:20:17 PM PST 24
Finished Mar 05 01:20:21 PM PST 24
Peak memory 214148 kb
Host smart-b0203b98-5cb1-4ffb-ad94-21bbfb5fe114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517449097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.3517449097
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.4226078102
Short name T537
Test name
Test status
Simulation time 455970499 ps
CPU time 2.05 seconds
Started Mar 05 01:20:28 PM PST 24
Finished Mar 05 01:20:31 PM PST 24
Peak memory 209372 kb
Host smart-e991bc48-3d9f-47c3-a2b4-c5236b6a0e50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4226078102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.4226078102
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.3019390582
Short name T96
Test name
Test status
Simulation time 38206335 ps
CPU time 0.77 seconds
Started Mar 05 01:20:39 PM PST 24
Finished Mar 05 01:20:40 PM PST 24
Peak memory 205880 kb
Host smart-3fc730e1-3d4c-4107-9df6-ebe7e465d433
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019390582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.3019390582
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.4244887851
Short name T794
Test name
Test status
Simulation time 372528335 ps
CPU time 3.78 seconds
Started Mar 05 01:20:45 PM PST 24
Finished Mar 05 01:20:49 PM PST 24
Peak memory 209052 kb
Host smart-f0ff4715-d09d-4261-9fb5-307a96363b55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4244887851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.4244887851
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.3923847486
Short name T861
Test name
Test status
Simulation time 290275351 ps
CPU time 3.35 seconds
Started Mar 05 01:20:41 PM PST 24
Finished Mar 05 01:20:44 PM PST 24
Peak memory 209568 kb
Host smart-831cebaa-327b-4c1c-ab9a-994917866ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923847486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.3923847486
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.2786038421
Short name T691
Test name
Test status
Simulation time 255644711 ps
CPU time 3.05 seconds
Started Mar 05 01:20:39 PM PST 24
Finished Mar 05 01:20:42 PM PST 24
Peak memory 207828 kb
Host smart-bb635351-0578-4e0b-a914-a20beb1dfb77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786038421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.2786038421
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.3489854556
Short name T353
Test name
Test status
Simulation time 195472299 ps
CPU time 3.61 seconds
Started Mar 05 01:20:35 PM PST 24
Finished Mar 05 01:20:39 PM PST 24
Peak memory 211088 kb
Host smart-3237e468-4111-4141-bfea-baf0fef8ba2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489854556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.3489854556
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.187839806
Short name T214
Test name
Test status
Simulation time 80858943 ps
CPU time 3.95 seconds
Started Mar 05 01:20:37 PM PST 24
Finished Mar 05 01:20:41 PM PST 24
Peak memory 219484 kb
Host smart-7a1fb60b-d473-4a53-badb-6047d4a93c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=187839806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.187839806
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.3776313391
Short name T747
Test name
Test status
Simulation time 322977980 ps
CPU time 9.26 seconds
Started Mar 05 01:20:47 PM PST 24
Finished Mar 05 01:20:57 PM PST 24
Peak memory 209472 kb
Host smart-e0d7671d-1410-415a-b320-1cc1ac404e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3776313391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.3776313391
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.3031891117
Short name T282
Test name
Test status
Simulation time 100143715 ps
CPU time 4.47 seconds
Started Mar 05 01:20:33 PM PST 24
Finished Mar 05 01:20:37 PM PST 24
Peak memory 208516 kb
Host smart-d7e39a29-99b0-42e0-8402-af7bf203a913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3031891117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.3031891117
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.449160793
Short name T549
Test name
Test status
Simulation time 84601967 ps
CPU time 3.09 seconds
Started Mar 05 01:20:43 PM PST 24
Finished Mar 05 01:20:46 PM PST 24
Peak memory 206364 kb
Host smart-1fa37ce1-aae6-4abd-828c-a8b2445bb325
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449160793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.449160793
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.1561262281
Short name T174
Test name
Test status
Simulation time 607292100 ps
CPU time 4.96 seconds
Started Mar 05 01:20:39 PM PST 24
Finished Mar 05 01:20:44 PM PST 24
Peak memory 206300 kb
Host smart-8d77aa99-8f5a-4de0-8516-066475b55473
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1561262281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.1561262281
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.2789895175
Short name T896
Test name
Test status
Simulation time 37514696 ps
CPU time 2.39 seconds
Started Mar 05 01:20:35 PM PST 24
Finished Mar 05 01:20:37 PM PST 24
Peak memory 206392 kb
Host smart-db7ac197-dd74-4a61-b04c-ac7ea5f0c553
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789895175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.2789895175
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.2398594643
Short name T395
Test name
Test status
Simulation time 387249749 ps
CPU time 3.49 seconds
Started Mar 05 01:20:35 PM PST 24
Finished Mar 05 01:20:38 PM PST 24
Peak memory 209568 kb
Host smart-55e4dc2f-7c25-4472-825f-b89f08c56431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398594643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.2398594643
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.2610788979
Short name T85
Test name
Test status
Simulation time 517747205 ps
CPU time 2.99 seconds
Started Mar 05 01:20:34 PM PST 24
Finished Mar 05 01:20:37 PM PST 24
Peak memory 208004 kb
Host smart-94add834-4d2c-49a4-863a-fea7ccb0bf73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610788979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.2610788979
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.3693893456
Short name T308
Test name
Test status
Simulation time 241557193 ps
CPU time 7.23 seconds
Started Mar 05 01:20:44 PM PST 24
Finished Mar 05 01:20:52 PM PST 24
Peak memory 218040 kb
Host smart-36d85a56-2c0d-45b0-b596-72f42c8ce93f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693893456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.3693893456
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.3733215163
Short name T607
Test name
Test status
Simulation time 277023424 ps
CPU time 7.16 seconds
Started Mar 05 01:20:46 PM PST 24
Finished Mar 05 01:20:54 PM PST 24
Peak memory 210080 kb
Host smart-5a27f012-603f-48f6-bf8b-3334db483dfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733215163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.3733215163
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.4104477187
Short name T97
Test name
Test status
Simulation time 59511413 ps
CPU time 0.79 seconds
Started Mar 05 01:20:44 PM PST 24
Finished Mar 05 01:20:46 PM PST 24
Peak memory 205804 kb
Host smart-41abd368-5500-43da-b3f4-3a141550024c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104477187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.4104477187
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.868540684
Short name T424
Test name
Test status
Simulation time 42619526 ps
CPU time 3.25 seconds
Started Mar 05 01:20:37 PM PST 24
Finished Mar 05 01:20:41 PM PST 24
Peak memory 215088 kb
Host smart-bff1f9b0-aa6a-48e7-9004-ac79a32398e9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=868540684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.868540684
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.3336722705
Short name T523
Test name
Test status
Simulation time 158776538 ps
CPU time 2.61 seconds
Started Mar 05 01:20:41 PM PST 24
Finished Mar 05 01:20:44 PM PST 24
Peak memory 218036 kb
Host smart-7298cc19-665d-47dc-821b-a9cf74dbb573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336722705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.3336722705
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.884083090
Short name T610
Test name
Test status
Simulation time 12728933404 ps
CPU time 22.38 seconds
Started Mar 05 01:20:44 PM PST 24
Finished Mar 05 01:21:07 PM PST 24
Peak memory 214164 kb
Host smart-f6614250-02ad-4b0c-8232-3af47376c165
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884083090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.884083090
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.1426051584
Short name T236
Test name
Test status
Simulation time 712170914 ps
CPU time 10.97 seconds
Started Mar 05 01:20:39 PM PST 24
Finished Mar 05 01:20:50 PM PST 24
Peak memory 222092 kb
Host smart-1699ced4-d394-427f-9327-27a16998915d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426051584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.1426051584
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.1909874619
Short name T554
Test name
Test status
Simulation time 91367905 ps
CPU time 1.96 seconds
Started Mar 05 01:20:36 PM PST 24
Finished Mar 05 01:20:38 PM PST 24
Peak memory 206288 kb
Host smart-a4034363-5196-4690-9cfb-7e319a3c3b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1909874619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.1909874619
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.3386091815
Short name T275
Test name
Test status
Simulation time 238427162 ps
CPU time 9.28 seconds
Started Mar 05 01:20:38 PM PST 24
Finished Mar 05 01:20:48 PM PST 24
Peak memory 218144 kb
Host smart-8a33a00c-7049-4799-949b-8057e4d12e8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386091815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.3386091815
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.2657327792
Short name T441
Test name
Test status
Simulation time 251008951 ps
CPU time 2.72 seconds
Started Mar 05 01:20:39 PM PST 24
Finished Mar 05 01:20:42 PM PST 24
Peak memory 206508 kb
Host smart-4290cb8b-f8fd-441b-914b-292c2131bf60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2657327792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.2657327792
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.3174939351
Short name T436
Test name
Test status
Simulation time 229112054 ps
CPU time 7.47 seconds
Started Mar 05 01:20:52 PM PST 24
Finished Mar 05 01:20:59 PM PST 24
Peak memory 208232 kb
Host smart-05d0899a-275b-4586-9465-2f65033e6183
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3174939351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.3174939351
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.2124489826
Short name T612
Test name
Test status
Simulation time 128585902 ps
CPU time 3.77 seconds
Started Mar 05 01:20:35 PM PST 24
Finished Mar 05 01:20:39 PM PST 24
Peak memory 208416 kb
Host smart-720a5256-5141-4731-87cd-fb54c85055c4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124489826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.2124489826
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.4255617120
Short name T638
Test name
Test status
Simulation time 138277133 ps
CPU time 5.49 seconds
Started Mar 05 01:20:52 PM PST 24
Finished Mar 05 01:20:58 PM PST 24
Peak memory 207884 kb
Host smart-b43e214a-ab98-4a3f-bae3-21e718d81b82
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255617120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.4255617120
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.3580412683
Short name T529
Test name
Test status
Simulation time 84524003 ps
CPU time 2.35 seconds
Started Mar 05 01:20:47 PM PST 24
Finished Mar 05 01:20:50 PM PST 24
Peak memory 208308 kb
Host smart-05d3dd68-9643-4117-9cae-8166ec0b65eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580412683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.3580412683
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.3067831874
Short name T770
Test name
Test status
Simulation time 1123697106 ps
CPU time 2.91 seconds
Started Mar 05 01:20:40 PM PST 24
Finished Mar 05 01:20:43 PM PST 24
Peak memory 206080 kb
Host smart-3c90d90d-615a-49ac-a889-ebf8b1b658af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067831874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.3067831874
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.1977600408
Short name T645
Test name
Test status
Simulation time 2227494188 ps
CPU time 11.06 seconds
Started Mar 05 01:20:47 PM PST 24
Finished Mar 05 01:20:59 PM PST 24
Peak memory 207432 kb
Host smart-0ecd7234-e2b2-4e01-be4a-8bf09333220f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977600408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.1977600408
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.2581372400
Short name T586
Test name
Test status
Simulation time 123528902 ps
CPU time 2.93 seconds
Started Mar 05 01:20:47 PM PST 24
Finished Mar 05 01:20:50 PM PST 24
Peak memory 209960 kb
Host smart-540f14a0-9b70-4426-9222-0310216e4f26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581372400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.2581372400
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.4285625530
Short name T526
Test name
Test status
Simulation time 40521466 ps
CPU time 0.84 seconds
Started Mar 05 01:20:40 PM PST 24
Finished Mar 05 01:20:41 PM PST 24
Peak memory 205880 kb
Host smart-c0cec91b-e596-4b1b-a2b1-f6c0e52ca12a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4285625530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.4285625530
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.1984093680
Short name T312
Test name
Test status
Simulation time 285790532 ps
CPU time 5.26 seconds
Started Mar 05 01:20:44 PM PST 24
Finished Mar 05 01:20:50 PM PST 24
Peak memory 215348 kb
Host smart-b96c2cad-0fa8-421b-a47b-407adf80a8a2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1984093680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.1984093680
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.1170834131
Short name T478
Test name
Test status
Simulation time 83286941 ps
CPU time 1.77 seconds
Started Mar 05 01:20:46 PM PST 24
Finished Mar 05 01:20:48 PM PST 24
Peak memory 207652 kb
Host smart-9d69e9a9-d51d-493e-9f4f-ffa4996ee57a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170834131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.1170834131
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.1223835195
Short name T271
Test name
Test status
Simulation time 357814489 ps
CPU time 6.25 seconds
Started Mar 05 01:20:46 PM PST 24
Finished Mar 05 01:20:53 PM PST 24
Peak memory 211644 kb
Host smart-44472940-9e4e-494c-b177-1d3eef1a7b0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223835195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.1223835195
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.2346568588
Short name T560
Test name
Test status
Simulation time 134892303 ps
CPU time 5.38 seconds
Started Mar 05 01:20:43 PM PST 24
Finished Mar 05 01:20:50 PM PST 24
Peak memory 210164 kb
Host smart-8e2f8572-2e51-4586-a5a6-1c050bbea37f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346568588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.2346568588
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.2023626635
Short name T619
Test name
Test status
Simulation time 292616296 ps
CPU time 2.57 seconds
Started Mar 05 01:20:41 PM PST 24
Finished Mar 05 01:20:43 PM PST 24
Peak memory 214124 kb
Host smart-b85c7cb7-da0a-43ae-9ea3-e2d6ee48ff67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023626635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.2023626635
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.2997090143
Short name T823
Test name
Test status
Simulation time 897234759 ps
CPU time 6.97 seconds
Started Mar 05 01:20:49 PM PST 24
Finished Mar 05 01:20:56 PM PST 24
Peak memory 208052 kb
Host smart-8069c837-d6d8-41a7-89ca-a4818c08815f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997090143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.2997090143
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.574985881
Short name T822
Test name
Test status
Simulation time 712340745 ps
CPU time 5.39 seconds
Started Mar 05 01:20:43 PM PST 24
Finished Mar 05 01:20:48 PM PST 24
Peak memory 207472 kb
Host smart-599ad440-2e76-4c66-aa15-3df338673101
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574985881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.574985881
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.125552025
Short name T316
Test name
Test status
Simulation time 280908337 ps
CPU time 4.73 seconds
Started Mar 05 01:20:43 PM PST 24
Finished Mar 05 01:20:48 PM PST 24
Peak memory 208112 kb
Host smart-9b7241be-a19c-4b1d-9e52-7636823ab627
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125552025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.125552025
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.2822593228
Short name T264
Test name
Test status
Simulation time 149266303 ps
CPU time 3.65 seconds
Started Mar 05 01:20:40 PM PST 24
Finished Mar 05 01:20:44 PM PST 24
Peak memory 208428 kb
Host smart-34e0d107-1cb3-44fb-9b98-a444809a97f0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822593228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.2822593228
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.2236646515
Short name T127
Test name
Test status
Simulation time 40537851 ps
CPU time 2.9 seconds
Started Mar 05 01:20:37 PM PST 24
Finished Mar 05 01:20:41 PM PST 24
Peak memory 210036 kb
Host smart-0afc06aa-13f9-40db-bb66-46080d2503dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236646515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.2236646515
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.435592218
Short name T453
Test name
Test status
Simulation time 88620368 ps
CPU time 2.47 seconds
Started Mar 05 01:20:45 PM PST 24
Finished Mar 05 01:20:48 PM PST 24
Peak memory 206380 kb
Host smart-7d38f0de-8164-4a8b-8805-bfb908a9933c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435592218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.435592218
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.4235150655
Short name T588
Test name
Test status
Simulation time 122407328 ps
CPU time 3.78 seconds
Started Mar 05 01:20:50 PM PST 24
Finished Mar 05 01:20:54 PM PST 24
Peak memory 215380 kb
Host smart-5826c321-9c8f-40d5-9e1b-165e63a548d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235150655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.4235150655
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_stress_all_with_rand_reset.1269144308
Short name T168
Test name
Test status
Simulation time 2673921669 ps
CPU time 10.72 seconds
Started Mar 05 01:20:37 PM PST 24
Finished Mar 05 01:20:49 PM PST 24
Peak memory 222560 kb
Host smart-dfaf6991-458f-47ca-b32f-0416502ff6a1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269144308 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all_with_rand_reset.1269144308
Directory /workspace/33.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.2737322675
Short name T394
Test name
Test status
Simulation time 774005956 ps
CPU time 9.88 seconds
Started Mar 05 01:20:46 PM PST 24
Finished Mar 05 01:20:56 PM PST 24
Peak memory 207820 kb
Host smart-22f1e255-497c-4ccc-b86a-c0c3ea4848de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737322675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.2737322675
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.3023213549
Short name T707
Test name
Test status
Simulation time 27452851 ps
CPU time 1.68 seconds
Started Mar 05 01:20:42 PM PST 24
Finished Mar 05 01:20:45 PM PST 24
Peak memory 209664 kb
Host smart-59fd3526-2761-4f35-adca-10d842818372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3023213549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.3023213549
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.2630540677
Short name T887
Test name
Test status
Simulation time 11937986 ps
CPU time 0.87 seconds
Started Mar 05 01:21:09 PM PST 24
Finished Mar 05 01:21:10 PM PST 24
Peak memory 205872 kb
Host smart-d2f25b50-887b-4616-9ac9-5a72b3be225d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2630540677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.2630540677
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.3692464238
Short name T417
Test name
Test status
Simulation time 55643522 ps
CPU time 3.88 seconds
Started Mar 05 01:20:47 PM PST 24
Finished Mar 05 01:20:51 PM PST 24
Peak memory 214252 kb
Host smart-b6e0f9ca-176d-4b2c-8144-e36490034ead
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3692464238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.3692464238
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.893366062
Short name T70
Test name
Test status
Simulation time 148929950 ps
CPU time 4.2 seconds
Started Mar 05 01:20:47 PM PST 24
Finished Mar 05 01:20:51 PM PST 24
Peak memory 214284 kb
Host smart-5f3cfc5f-d136-4bab-abd5-d4f5e811fb47
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893366062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.893366062
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.4095692054
Short name T296
Test name
Test status
Simulation time 28125709 ps
CPU time 1.96 seconds
Started Mar 05 01:20:45 PM PST 24
Finished Mar 05 01:20:47 PM PST 24
Peak memory 214116 kb
Host smart-1ebb535c-12bc-4520-9c2d-138897ebc286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095692054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.4095692054
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.3010370186
Short name T727
Test name
Test status
Simulation time 1477668453 ps
CPU time 7.07 seconds
Started Mar 05 01:21:06 PM PST 24
Finished Mar 05 01:21:13 PM PST 24
Peak memory 214116 kb
Host smart-3b546ea9-3984-431b-845b-2854034108e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010370186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.3010370186
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.812490707
Short name T185
Test name
Test status
Simulation time 543236740 ps
CPU time 21.45 seconds
Started Mar 05 01:20:48 PM PST 24
Finished Mar 05 01:21:10 PM PST 24
Peak memory 210404 kb
Host smart-a2744bac-d018-45bd-9ae4-3a300518d4db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=812490707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.812490707
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.313103418
Short name T852
Test name
Test status
Simulation time 88470884 ps
CPU time 4.32 seconds
Started Mar 05 01:20:47 PM PST 24
Finished Mar 05 01:20:51 PM PST 24
Peak memory 208820 kb
Host smart-d1b4bb64-159c-4b1f-b7df-9a4f961cb5ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313103418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.313103418
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.1000274880
Short name T173
Test name
Test status
Simulation time 223403027 ps
CPU time 3.78 seconds
Started Mar 05 01:20:41 PM PST 24
Finished Mar 05 01:20:45 PM PST 24
Peak memory 209532 kb
Host smart-10a9c62e-d604-4bb7-895f-4ee497894598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1000274880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.1000274880
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.2658744402
Short name T788
Test name
Test status
Simulation time 94043150 ps
CPU time 2.78 seconds
Started Mar 05 01:20:43 PM PST 24
Finished Mar 05 01:20:47 PM PST 24
Peak memory 206428 kb
Host smart-4ae3811a-4476-444f-b6ba-d8feefa16d54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658744402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.2658744402
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.4004959678
Short name T445
Test name
Test status
Simulation time 1081150664 ps
CPU time 34 seconds
Started Mar 05 01:20:37 PM PST 24
Finished Mar 05 01:21:11 PM PST 24
Peak memory 207940 kb
Host smart-5edf80b4-205d-40e2-adf4-07dde2ead5ef
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004959678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.4004959678
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.842899812
Short name T605
Test name
Test status
Simulation time 216344654 ps
CPU time 6.07 seconds
Started Mar 05 01:20:38 PM PST 24
Finished Mar 05 01:20:45 PM PST 24
Peak memory 208380 kb
Host smart-5b37ff00-0b27-4b33-ba91-dc536748bc2c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842899812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.842899812
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.2246986605
Short name T576
Test name
Test status
Simulation time 133254163 ps
CPU time 4.16 seconds
Started Mar 05 01:20:48 PM PST 24
Finished Mar 05 01:20:53 PM PST 24
Peak memory 206528 kb
Host smart-7362ffc1-d8a8-4e2c-9a22-f62da1f04721
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246986605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.2246986605
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.2761698512
Short name T821
Test name
Test status
Simulation time 123365917 ps
CPU time 4.82 seconds
Started Mar 05 01:20:52 PM PST 24
Finished Mar 05 01:20:57 PM PST 24
Peak memory 218368 kb
Host smart-be1d6be7-32ea-4cf1-8885-4d9a8be7fd5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761698512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.2761698512
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.2242598438
Short name T533
Test name
Test status
Simulation time 370673045 ps
CPU time 3.57 seconds
Started Mar 05 01:20:43 PM PST 24
Finished Mar 05 01:20:47 PM PST 24
Peak memory 208168 kb
Host smart-e7917170-3746-4ffe-b4d4-72fba09450a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2242598438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.2242598438
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all_with_rand_reset.1118631166
Short name T104
Test name
Test status
Simulation time 232537082 ps
CPU time 8.73 seconds
Started Mar 05 01:20:55 PM PST 24
Finished Mar 05 01:21:04 PM PST 24
Peak memory 219180 kb
Host smart-63c396b9-3634-4cde-97b2-b3981f1661ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1118631166 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all_with_rand_reset.1118631166
Directory /workspace/34.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.2510451834
Short name T392
Test name
Test status
Simulation time 986932491 ps
CPU time 10.51 seconds
Started Mar 05 01:20:43 PM PST 24
Finished Mar 05 01:20:54 PM PST 24
Peak memory 206932 kb
Host smart-eba4bb1c-3a5c-446e-b354-0426d40073f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2510451834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.2510451834
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.3662397207
Short name T876
Test name
Test status
Simulation time 1065174687 ps
CPU time 8.78 seconds
Started Mar 05 01:21:04 PM PST 24
Finished Mar 05 01:21:14 PM PST 24
Peak memory 210192 kb
Host smart-37ca6c74-4337-4c98-a745-34aa9083c45f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3662397207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.3662397207
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.3332899462
Short name T427
Test name
Test status
Simulation time 11606097 ps
CPU time 0.73 seconds
Started Mar 05 01:20:54 PM PST 24
Finished Mar 05 01:20:55 PM PST 24
Peak memory 205884 kb
Host smart-f4a7bcf3-18c7-4c45-a7cc-0be10709926b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332899462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.3332899462
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.1050907586
Short name T30
Test name
Test status
Simulation time 207932469 ps
CPU time 3.36 seconds
Started Mar 05 01:20:46 PM PST 24
Finished Mar 05 01:20:50 PM PST 24
Peak memory 218492 kb
Host smart-f638d60d-868b-4239-82d9-8aad61836598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050907586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.1050907586
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.3827366019
Short name T74
Test name
Test status
Simulation time 312803473 ps
CPU time 3.02 seconds
Started Mar 05 01:20:53 PM PST 24
Finished Mar 05 01:20:57 PM PST 24
Peak memory 207176 kb
Host smart-e70d4d98-d993-408e-9d98-bb6f74b087ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3827366019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.3827366019
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.215492704
Short name T256
Test name
Test status
Simulation time 124598249 ps
CPU time 4.46 seconds
Started Mar 05 01:20:43 PM PST 24
Finished Mar 05 01:20:48 PM PST 24
Peak memory 210172 kb
Host smart-016af01b-4431-4349-8005-a468eb820c98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=215492704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.215492704
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.3819011061
Short name T447
Test name
Test status
Simulation time 139109543 ps
CPU time 1.77 seconds
Started Mar 05 01:20:51 PM PST 24
Finished Mar 05 01:20:53 PM PST 24
Peak memory 205928 kb
Host smart-a808b6f4-17b8-482d-af0b-01bd2731986b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819011061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.3819011061
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.104078744
Short name T283
Test name
Test status
Simulation time 323149630 ps
CPU time 7.79 seconds
Started Mar 05 01:21:07 PM PST 24
Finished Mar 05 01:21:15 PM PST 24
Peak memory 218112 kb
Host smart-afbb6a06-9ab3-461d-bc04-2ad056db731e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104078744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.104078744
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.2121904972
Short name T448
Test name
Test status
Simulation time 39822991 ps
CPU time 2.34 seconds
Started Mar 05 01:20:51 PM PST 24
Finished Mar 05 01:20:54 PM PST 24
Peak memory 206556 kb
Host smart-36effce4-5709-447d-81fc-9892cd31466b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121904972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.2121904972
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.1347420911
Short name T306
Test name
Test status
Simulation time 204012961 ps
CPU time 6.03 seconds
Started Mar 05 01:20:55 PM PST 24
Finished Mar 05 01:21:01 PM PST 24
Peak memory 208380 kb
Host smart-32f0ec49-92f2-480e-9adb-5304ff2f8e70
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1347420911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.1347420911
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.3664436285
Short name T728
Test name
Test status
Simulation time 3384514295 ps
CPU time 22.77 seconds
Started Mar 05 01:20:40 PM PST 24
Finished Mar 05 01:21:03 PM PST 24
Peak memory 207976 kb
Host smart-92180796-47c2-4850-a88c-5a01885c36f9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664436285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.3664436285
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.2718114457
Short name T875
Test name
Test status
Simulation time 443013929 ps
CPU time 7.69 seconds
Started Mar 05 01:20:51 PM PST 24
Finished Mar 05 01:20:59 PM PST 24
Peak memory 207536 kb
Host smart-2ffa2b6b-0289-4e90-8e3d-d9a37fd910f3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2718114457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.2718114457
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.4011597993
Short name T356
Test name
Test status
Simulation time 210745835 ps
CPU time 3.39 seconds
Started Mar 05 01:20:50 PM PST 24
Finished Mar 05 01:20:53 PM PST 24
Peak memory 209440 kb
Host smart-ce1202ef-9a09-47b5-98db-6c07c81fd624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011597993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.4011597993
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.2737642432
Short name T444
Test name
Test status
Simulation time 1330951776 ps
CPU time 7.21 seconds
Started Mar 05 01:20:48 PM PST 24
Finished Mar 05 01:20:55 PM PST 24
Peak memory 207184 kb
Host smart-f7ae80d8-e614-42e7-a170-3042a8eb3bef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737642432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.2737642432
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.2991608971
Short name T292
Test name
Test status
Simulation time 2822478615 ps
CPU time 23.25 seconds
Started Mar 05 01:20:55 PM PST 24
Finished Mar 05 01:21:19 PM PST 24
Peak memory 216756 kb
Host smart-2af423f4-c1db-4bf5-b54c-6322053e569a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991608971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.2991608971
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.760724770
Short name T345
Test name
Test status
Simulation time 2609665766 ps
CPU time 31.37 seconds
Started Mar 05 01:21:15 PM PST 24
Finished Mar 05 01:21:47 PM PST 24
Peak memory 208948 kb
Host smart-3d1a7027-cc7d-404f-b476-4df4418e7a32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760724770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.760724770
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.3530676130
Short name T635
Test name
Test status
Simulation time 97356060 ps
CPU time 2.61 seconds
Started Mar 05 01:20:49 PM PST 24
Finished Mar 05 01:20:52 PM PST 24
Peak memory 210204 kb
Host smart-130ee90d-b819-4c85-a15d-c87a4b4d0350
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3530676130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.3530676130
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.2278374135
Short name T865
Test name
Test status
Simulation time 14273433 ps
CPU time 0.73 seconds
Started Mar 05 01:20:48 PM PST 24
Finished Mar 05 01:20:49 PM PST 24
Peak memory 205820 kb
Host smart-2a4545d6-7f6d-4e24-b427-043a2904db7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278374135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.2278374135
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.2712025870
Short name T416
Test name
Test status
Simulation time 63000299 ps
CPU time 3.32 seconds
Started Mar 05 01:21:12 PM PST 24
Finished Mar 05 01:21:15 PM PST 24
Peak memory 214964 kb
Host smart-8f64f32a-0545-4f47-a711-38ea1b5a02f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2712025870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.2712025870
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.6928000
Short name T18
Test name
Test status
Simulation time 145110715 ps
CPU time 3.79 seconds
Started Mar 05 01:20:48 PM PST 24
Finished Mar 05 01:20:53 PM PST 24
Peak memory 217588 kb
Host smart-580ef0d6-a5a7-4d3a-96f5-dc10479b2fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6928000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.6928000
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.3202564156
Short name T60
Test name
Test status
Simulation time 161894716 ps
CPU time 4.93 seconds
Started Mar 05 01:21:02 PM PST 24
Finished Mar 05 01:21:08 PM PST 24
Peak memory 208620 kb
Host smart-0eab40eb-995f-4f4a-9f1f-57d9636f2d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202564156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.3202564156
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.4072420196
Short name T25
Test name
Test status
Simulation time 268103370 ps
CPU time 9.65 seconds
Started Mar 05 01:20:52 PM PST 24
Finished Mar 05 01:21:02 PM PST 24
Peak memory 209588 kb
Host smart-23d9df50-ff2e-4312-ae76-e82409fd9df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072420196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.4072420196
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.3675431562
Short name T277
Test name
Test status
Simulation time 567353524 ps
CPU time 6.89 seconds
Started Mar 05 01:20:49 PM PST 24
Finished Mar 05 01:20:57 PM PST 24
Peak memory 222220 kb
Host smart-f7cd44b3-87e1-4bcd-806c-a73f9ac7c0b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3675431562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.3675431562
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.2602926260
Short name T212
Test name
Test status
Simulation time 70637146 ps
CPU time 3.39 seconds
Started Mar 05 01:20:49 PM PST 24
Finished Mar 05 01:20:53 PM PST 24
Peak memory 219300 kb
Host smart-6817e4e4-7a4a-47a4-8cd7-3c80c6fa29cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602926260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.2602926260
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.425482374
Short name T183
Test name
Test status
Simulation time 130674205 ps
CPU time 2.65 seconds
Started Mar 05 01:20:47 PM PST 24
Finished Mar 05 01:20:51 PM PST 24
Peak memory 207332 kb
Host smart-7f8f9bf0-50f2-41e4-a189-7fdf659f69f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425482374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.425482374
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.890635435
Short name T814
Test name
Test status
Simulation time 1171900836 ps
CPU time 8.48 seconds
Started Mar 05 01:20:45 PM PST 24
Finished Mar 05 01:20:54 PM PST 24
Peak memory 206532 kb
Host smart-fc64493a-5a6c-4c2d-ab1b-6dfdefe7a314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890635435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.890635435
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.3552038872
Short name T401
Test name
Test status
Simulation time 78997616 ps
CPU time 3.65 seconds
Started Mar 05 01:20:53 PM PST 24
Finished Mar 05 01:20:57 PM PST 24
Peak memory 206596 kb
Host smart-ff5ec0c2-1faf-4d4c-8e34-5317eabe7bc5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3552038872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.3552038872
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.935898878
Short name T853
Test name
Test status
Simulation time 33865694 ps
CPU time 2.43 seconds
Started Mar 05 01:20:50 PM PST 24
Finished Mar 05 01:20:52 PM PST 24
Peak memory 206444 kb
Host smart-20269da5-2074-449d-bf62-675481e47306
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935898878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.935898878
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.1806920704
Short name T837
Test name
Test status
Simulation time 158700282 ps
CPU time 2.03 seconds
Started Mar 05 01:20:48 PM PST 24
Finished Mar 05 01:20:50 PM PST 24
Peak memory 208380 kb
Host smart-eecea080-bed7-4b04-b903-7b216db74221
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1806920704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.1806920704
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.3722874990
Short name T641
Test name
Test status
Simulation time 44239328 ps
CPU time 1.89 seconds
Started Mar 05 01:20:52 PM PST 24
Finished Mar 05 01:20:54 PM PST 24
Peak memory 208344 kb
Host smart-6a11e3ad-45d2-4354-88ca-90d47c09c207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722874990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.3722874990
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.1286647302
Short name T553
Test name
Test status
Simulation time 275906052 ps
CPU time 3.29 seconds
Started Mar 05 01:21:12 PM PST 24
Finished Mar 05 01:21:15 PM PST 24
Peak memory 208140 kb
Host smart-aa151221-0713-4abb-a16c-1703491bb723
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1286647302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.1286647302
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.768065070
Short name T210
Test name
Test status
Simulation time 6020830046 ps
CPU time 78.05 seconds
Started Mar 05 01:20:51 PM PST 24
Finished Mar 05 01:22:09 PM PST 24
Peak memory 217132 kb
Host smart-117834f7-bbeb-4eef-8684-cf9220310e89
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768065070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.768065070
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.2917806990
Short name T795
Test name
Test status
Simulation time 372217304 ps
CPU time 12.93 seconds
Started Mar 05 01:20:45 PM PST 24
Finished Mar 05 01:20:59 PM PST 24
Peak memory 208832 kb
Host smart-db14a4a6-7ee3-4da2-8d7a-c43c645aa169
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2917806990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.2917806990
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.2628535999
Short name T722
Test name
Test status
Simulation time 105228491 ps
CPU time 2.38 seconds
Started Mar 05 01:20:48 PM PST 24
Finished Mar 05 01:20:51 PM PST 24
Peak memory 209244 kb
Host smart-647193d5-de5e-456e-9150-5ec200d34ab3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628535999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.2628535999
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.515941195
Short name T730
Test name
Test status
Simulation time 20064116 ps
CPU time 0.74 seconds
Started Mar 05 01:20:54 PM PST 24
Finished Mar 05 01:20:55 PM PST 24
Peak memory 205880 kb
Host smart-6137bbf0-e058-4dad-adca-ff8f3d429520
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515941195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.515941195
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.1006496941
Short name T243
Test name
Test status
Simulation time 47527894 ps
CPU time 3.44 seconds
Started Mar 05 01:20:48 PM PST 24
Finished Mar 05 01:20:51 PM PST 24
Peak memory 214948 kb
Host smart-43ff0e1e-b0cf-490a-b3ff-d2a0a1247f02
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1006496941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.1006496941
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.2799629859
Short name T848
Test name
Test status
Simulation time 72703106 ps
CPU time 3.07 seconds
Started Mar 05 01:20:50 PM PST 24
Finished Mar 05 01:20:54 PM PST 24
Peak memory 210524 kb
Host smart-e1aeb1e2-7bcc-4e68-ae7f-b404c5812e6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799629859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.2799629859
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.1197625204
Short name T66
Test name
Test status
Simulation time 1583779788 ps
CPU time 4.61 seconds
Started Mar 05 01:21:09 PM PST 24
Finished Mar 05 01:21:14 PM PST 24
Peak memory 208192 kb
Host smart-843bac79-c0ba-4980-a6f5-97684c02ffb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1197625204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.1197625204
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.410785491
Short name T259
Test name
Test status
Simulation time 148287703 ps
CPU time 5.85 seconds
Started Mar 05 01:20:57 PM PST 24
Finished Mar 05 01:21:03 PM PST 24
Peak memory 214132 kb
Host smart-b5488b06-f780-47fe-914f-0c0f8be608c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410785491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.410785491
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.3434807017
Short name T187
Test name
Test status
Simulation time 81203498 ps
CPU time 3.16 seconds
Started Mar 05 01:20:57 PM PST 24
Finished Mar 05 01:21:01 PM PST 24
Peak memory 209648 kb
Host smart-18abc7f1-8156-4d56-af7d-79a3ea0169ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3434807017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.3434807017
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.3476630852
Short name T404
Test name
Test status
Simulation time 1067366156 ps
CPU time 4.65 seconds
Started Mar 05 01:20:53 PM PST 24
Finished Mar 05 01:20:58 PM PST 24
Peak memory 208928 kb
Host smart-89141ee0-d9b6-49b3-bc7f-3f811cb8a664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476630852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.3476630852
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.869453191
Short name T332
Test name
Test status
Simulation time 10022476713 ps
CPU time 78.48 seconds
Started Mar 05 01:20:52 PM PST 24
Finished Mar 05 01:22:11 PM PST 24
Peak memory 218392 kb
Host smart-9d07fc86-9930-4dc3-a12b-fc191c45cea3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869453191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.869453191
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.2437943693
Short name T675
Test name
Test status
Simulation time 114690813 ps
CPU time 2.35 seconds
Started Mar 05 01:20:54 PM PST 24
Finished Mar 05 01:20:56 PM PST 24
Peak memory 206476 kb
Host smart-5c7bed85-74e3-4321-89ea-3fa61dcbcc67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437943693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.2437943693
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.3255745776
Short name T502
Test name
Test status
Simulation time 844336996 ps
CPU time 16.43 seconds
Started Mar 05 01:20:54 PM PST 24
Finished Mar 05 01:21:11 PM PST 24
Peak memory 207904 kb
Host smart-2d5ee141-d24b-4ba5-a083-2b06df46fe5c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255745776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.3255745776
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.2340508753
Short name T618
Test name
Test status
Simulation time 957312518 ps
CPU time 7.3 seconds
Started Mar 05 01:20:51 PM PST 24
Finished Mar 05 01:20:58 PM PST 24
Peak memory 208380 kb
Host smart-a8b6ad92-f38d-49a7-8a06-1c60288ed894
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2340508753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.2340508753
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.3603651392
Short name T644
Test name
Test status
Simulation time 51619020 ps
CPU time 2.78 seconds
Started Mar 05 01:20:57 PM PST 24
Finished Mar 05 01:21:00 PM PST 24
Peak memory 206860 kb
Host smart-56f3d7b0-ea67-42e9-aad3-986422ec1c7f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603651392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.3603651392
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.253102
Short name T640
Test name
Test status
Simulation time 236106081 ps
CPU time 2.63 seconds
Started Mar 05 01:20:56 PM PST 24
Finished Mar 05 01:20:59 PM PST 24
Peak memory 209752 kb
Host smart-f6c3fd1a-3a11-49c3-9ba9-803d832dfc04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.253102
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.1389689985
Short name T434
Test name
Test status
Simulation time 140007139 ps
CPU time 2.12 seconds
Started Mar 05 01:20:48 PM PST 24
Finished Mar 05 01:20:51 PM PST 24
Peak memory 206260 kb
Host smart-5d5c86a5-3127-4bca-a978-796b88255e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389689985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.1389689985
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.2717170647
Short name T550
Test name
Test status
Simulation time 1625937115 ps
CPU time 20.43 seconds
Started Mar 05 01:20:45 PM PST 24
Finished Mar 05 01:21:06 PM PST 24
Peak memory 222312 kb
Host smart-da4f3fa6-b999-440b-8f81-b787cf19db3f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717170647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.2717170647
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.1415239241
Short name T508
Test name
Test status
Simulation time 1741837949 ps
CPU time 41.12 seconds
Started Mar 05 01:20:57 PM PST 24
Finished Mar 05 01:21:39 PM PST 24
Peak memory 218168 kb
Host smart-5f1c1897-bb58-4e88-adb4-27ec5fd7d767
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415239241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.1415239241
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.3812915242
Short name T1
Test name
Test status
Simulation time 30623929 ps
CPU time 1.57 seconds
Started Mar 05 01:20:59 PM PST 24
Finished Mar 05 01:21:01 PM PST 24
Peak memory 209068 kb
Host smart-45e6b7ec-b3e4-4096-b4be-1aca87c6f58d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3812915242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.3812915242
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.485471515
Short name T524
Test name
Test status
Simulation time 26286079 ps
CPU time 0.71 seconds
Started Mar 05 01:20:59 PM PST 24
Finished Mar 05 01:21:00 PM PST 24
Peak memory 205864 kb
Host smart-3af4084c-f4fb-4bad-bb6d-3d79db91bc50
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485471515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.485471515
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.1954374721
Short name T839
Test name
Test status
Simulation time 1457011159 ps
CPU time 12.38 seconds
Started Mar 05 01:20:58 PM PST 24
Finished Mar 05 01:21:11 PM PST 24
Peak memory 214152 kb
Host smart-8481b98e-2d95-4e0a-b4fe-71c040e1522a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954374721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.1954374721
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.868761582
Short name T569
Test name
Test status
Simulation time 110667654 ps
CPU time 2.09 seconds
Started Mar 05 01:20:56 PM PST 24
Finished Mar 05 01:20:58 PM PST 24
Peak memory 206488 kb
Host smart-8472a7e6-1d91-454b-9455-d1abca77fa73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868761582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.868761582
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.1076482549
Short name T343
Test name
Test status
Simulation time 128855396 ps
CPU time 2.39 seconds
Started Mar 05 01:20:53 PM PST 24
Finished Mar 05 01:20:56 PM PST 24
Peak memory 208176 kb
Host smart-e12f0f2a-6bcd-404d-95a6-7c20836f4436
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076482549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.1076482549
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.4015224429
Short name T654
Test name
Test status
Simulation time 260509293 ps
CPU time 3.77 seconds
Started Mar 05 01:21:02 PM PST 24
Finished Mar 05 01:21:07 PM PST 24
Peak memory 210704 kb
Host smart-c6a4a81c-15ad-45c5-aa18-07ae9f0156e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015224429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.4015224429
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.3852506587
Short name T202
Test name
Test status
Simulation time 66593212 ps
CPU time 3.47 seconds
Started Mar 05 01:21:05 PM PST 24
Finished Mar 05 01:21:09 PM PST 24
Peak memory 208780 kb
Host smart-9e751a27-9b6a-4ba1-a638-c87c8761049a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3852506587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.3852506587
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.628245983
Short name T690
Test name
Test status
Simulation time 87503815 ps
CPU time 2.84 seconds
Started Mar 05 01:21:01 PM PST 24
Finished Mar 05 01:21:05 PM PST 24
Peak memory 209872 kb
Host smart-5e5b6495-b929-47f4-8cf5-67e4a4c40c73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=628245983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.628245983
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.4015338313
Short name T460
Test name
Test status
Simulation time 4392160203 ps
CPU time 32.02 seconds
Started Mar 05 01:20:49 PM PST 24
Finished Mar 05 01:21:21 PM PST 24
Peak memory 208596 kb
Host smart-3b9174b8-52c9-4792-95c6-9821978d0c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015338313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.4015338313
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.3441943924
Short name T732
Test name
Test status
Simulation time 56441457 ps
CPU time 3.27 seconds
Started Mar 05 01:21:02 PM PST 24
Finished Mar 05 01:21:06 PM PST 24
Peak memory 208276 kb
Host smart-84b7acb5-7211-486f-9055-3bfe787117dc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3441943924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.3441943924
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.4155910448
Short name T403
Test name
Test status
Simulation time 26142732 ps
CPU time 1.79 seconds
Started Mar 05 01:20:49 PM PST 24
Finished Mar 05 01:20:51 PM PST 24
Peak memory 206488 kb
Host smart-8ec89594-55cb-46e2-8e91-0d7428b9d909
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155910448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.4155910448
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.73616102
Short name T540
Test name
Test status
Simulation time 28015061 ps
CPU time 2.15 seconds
Started Mar 05 01:20:55 PM PST 24
Finished Mar 05 01:20:58 PM PST 24
Peak memory 208480 kb
Host smart-2ae74fda-9df7-4395-9f7e-f61a38f636da
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73616102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.73616102
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.916985266
Short name T197
Test name
Test status
Simulation time 181919582 ps
CPU time 5.53 seconds
Started Mar 05 01:21:02 PM PST 24
Finished Mar 05 01:21:09 PM PST 24
Peak memory 209464 kb
Host smart-46e5258f-f5bb-41c4-ad46-250941a1b6de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916985266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.916985266
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.486932879
Short name T702
Test name
Test status
Simulation time 45994180 ps
CPU time 2.53 seconds
Started Mar 05 01:21:03 PM PST 24
Finished Mar 05 01:21:06 PM PST 24
Peak memory 206140 kb
Host smart-4ec21392-cbed-433f-9c24-98032ddf99f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486932879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.486932879
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.3647296125
Short name T323
Test name
Test status
Simulation time 18164021547 ps
CPU time 44.34 seconds
Started Mar 05 01:20:55 PM PST 24
Finished Mar 05 01:21:39 PM PST 24
Peak memory 209188 kb
Host smart-c2ec3682-c73a-4236-90b7-0d792ac8ce63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3647296125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.3647296125
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.473876090
Short name T375
Test name
Test status
Simulation time 178093762 ps
CPU time 1.99 seconds
Started Mar 05 01:20:52 PM PST 24
Finished Mar 05 01:20:54 PM PST 24
Peak memory 209768 kb
Host smart-80722f9e-c968-4447-ba0f-e480031feb97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473876090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.473876090
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.3210201351
Short name T570
Test name
Test status
Simulation time 36708353 ps
CPU time 0.83 seconds
Started Mar 05 01:21:16 PM PST 24
Finished Mar 05 01:21:17 PM PST 24
Peak memory 205788 kb
Host smart-0a1a088c-b6fa-41a4-bbe4-a2687eec71c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3210201351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.3210201351
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.437297561
Short name T819
Test name
Test status
Simulation time 674730545 ps
CPU time 8.43 seconds
Started Mar 05 01:20:53 PM PST 24
Finished Mar 05 01:21:02 PM PST 24
Peak memory 222440 kb
Host smart-6e86289f-2b53-43e2-9daf-708c62a009b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437297561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.437297561
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.503273240
Short name T47
Test name
Test status
Simulation time 167195549 ps
CPU time 3.58 seconds
Started Mar 05 01:20:50 PM PST 24
Finished Mar 05 01:20:53 PM PST 24
Peak memory 208252 kb
Host smart-9bb86c58-9485-417f-95b2-f1ca529bb180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503273240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.503273240
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.3941357094
Short name T289
Test name
Test status
Simulation time 93150786 ps
CPU time 4.82 seconds
Started Mar 05 01:20:59 PM PST 24
Finished Mar 05 01:21:04 PM PST 24
Peak memory 209000 kb
Host smart-afd49504-fd2c-41cd-ba07-3d539f75183b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941357094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.3941357094
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.1741646093
Short name T670
Test name
Test status
Simulation time 274895056 ps
CPU time 5.48 seconds
Started Mar 05 01:21:21 PM PST 24
Finished Mar 05 01:21:27 PM PST 24
Peak memory 213880 kb
Host smart-e7305374-35e6-4a6a-b4e3-240614d60910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741646093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.1741646093
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.411312812
Short name T213
Test name
Test status
Simulation time 141398483 ps
CPU time 3.49 seconds
Started Mar 05 01:20:49 PM PST 24
Finished Mar 05 01:20:53 PM PST 24
Peak memory 219424 kb
Host smart-323cc345-5535-4e8b-b59c-da15e2d0bac0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=411312812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.411312812
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.570530947
Short name T886
Test name
Test status
Simulation time 209491689 ps
CPU time 6.68 seconds
Started Mar 05 01:21:02 PM PST 24
Finished Mar 05 01:21:10 PM PST 24
Peak memory 214772 kb
Host smart-0a0b05bd-4b7c-41b3-9e5a-e30699ac66f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570530947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.570530947
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.125514584
Short name T775
Test name
Test status
Simulation time 348867406 ps
CPU time 3.86 seconds
Started Mar 05 01:20:53 PM PST 24
Finished Mar 05 01:20:57 PM PST 24
Peak memory 206360 kb
Host smart-5ae28fe5-f25f-4a9a-a028-48aae3dc4f88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125514584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.125514584
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.514462981
Short name T639
Test name
Test status
Simulation time 23554146864 ps
CPU time 34.45 seconds
Started Mar 05 01:21:00 PM PST 24
Finished Mar 05 01:21:34 PM PST 24
Peak memory 207636 kb
Host smart-4229702e-1093-49c0-9f0c-c55053af2668
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514462981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.514462981
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.2889910565
Short name T845
Test name
Test status
Simulation time 863404294 ps
CPU time 6.15 seconds
Started Mar 05 01:20:52 PM PST 24
Finished Mar 05 01:20:58 PM PST 24
Peak memory 208316 kb
Host smart-d675169b-4986-4c35-9a70-9958c3bb4956
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2889910565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.2889910565
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.2249367432
Short name T462
Test name
Test status
Simulation time 337078965 ps
CPU time 4.01 seconds
Started Mar 05 01:21:00 PM PST 24
Finished Mar 05 01:21:04 PM PST 24
Peak memory 208336 kb
Host smart-36eca6d8-f2f0-47b9-8c4f-9e36f7f52832
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2249367432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.2249367432
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.3368756831
Short name T806
Test name
Test status
Simulation time 69094179 ps
CPU time 2.43 seconds
Started Mar 05 01:21:01 PM PST 24
Finished Mar 05 01:21:03 PM PST 24
Peak memory 207580 kb
Host smart-33aa710a-b4f9-4616-a0ba-85c8581456c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368756831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.3368756831
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.753947000
Short name T438
Test name
Test status
Simulation time 134192359 ps
CPU time 2.93 seconds
Started Mar 05 01:20:59 PM PST 24
Finished Mar 05 01:21:03 PM PST 24
Peak memory 208112 kb
Host smart-14c45ce0-cffc-4246-b01a-5c816a7cda12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=753947000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.753947000
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.2412889125
Short name T694
Test name
Test status
Simulation time 15990189628 ps
CPU time 350.4 seconds
Started Mar 05 01:21:01 PM PST 24
Finished Mar 05 01:26:53 PM PST 24
Peak memory 218728 kb
Host smart-33a9dd09-7d8b-4950-b0d1-5c8feaf63b39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412889125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.2412889125
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.3988406738
Short name T189
Test name
Test status
Simulation time 634906400 ps
CPU time 4.43 seconds
Started Mar 05 01:20:53 PM PST 24
Finished Mar 05 01:20:57 PM PST 24
Peak memory 214136 kb
Host smart-4fc557d2-dcd5-493a-96d0-c4a9f5ea5069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988406738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.3988406738
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.759042531
Short name T532
Test name
Test status
Simulation time 81225585 ps
CPU time 1.98 seconds
Started Mar 05 01:20:56 PM PST 24
Finished Mar 05 01:20:58 PM PST 24
Peak memory 209944 kb
Host smart-2057ee85-0c2b-46db-ac87-4941e1cd7031
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=759042531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.759042531
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.1835145035
Short name T872
Test name
Test status
Simulation time 140061073 ps
CPU time 0.81 seconds
Started Mar 05 01:19:12 PM PST 24
Finished Mar 05 01:19:13 PM PST 24
Peak memory 205880 kb
Host smart-ae3e4614-f7c0-43ea-8ced-0f0910d9baf4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835145035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.1835145035
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.2449480006
Short name T414
Test name
Test status
Simulation time 58610060 ps
CPU time 2.44 seconds
Started Mar 05 01:19:12 PM PST 24
Finished Mar 05 01:19:15 PM PST 24
Peak memory 214184 kb
Host smart-78835943-b0f7-45e0-8069-e093e9902145
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2449480006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.2449480006
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.231785666
Short name T802
Test name
Test status
Simulation time 139771572 ps
CPU time 4.87 seconds
Started Mar 05 01:19:14 PM PST 24
Finished Mar 05 01:19:20 PM PST 24
Peak memory 209768 kb
Host smart-20bbd856-3465-4531-8c54-97ddc4f0a089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231785666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.231785666
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.13946015
Short name T617
Test name
Test status
Simulation time 112469322 ps
CPU time 4.94 seconds
Started Mar 05 01:19:20 PM PST 24
Finished Mar 05 01:19:26 PM PST 24
Peak memory 214148 kb
Host smart-44df2d0f-8be6-409f-8870-dd27e5dd6549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13946015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.13946015
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.2554646606
Short name T372
Test name
Test status
Simulation time 2746885639 ps
CPU time 8.62 seconds
Started Mar 05 01:19:15 PM PST 24
Finished Mar 05 01:19:24 PM PST 24
Peak memory 210768 kb
Host smart-32d4af1c-835e-459c-b6c7-7918be4f9221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554646606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.2554646606
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.2557501021
Short name T793
Test name
Test status
Simulation time 118312059 ps
CPU time 4.97 seconds
Started Mar 05 01:19:06 PM PST 24
Finished Mar 05 01:19:12 PM PST 24
Peak memory 218688 kb
Host smart-64ec2731-b5a6-4ac4-a53c-04a20c6da077
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557501021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.2557501021
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.2442821226
Short name T333
Test name
Test status
Simulation time 1951801639 ps
CPU time 36.03 seconds
Started Mar 05 01:19:25 PM PST 24
Finished Mar 05 01:20:01 PM PST 24
Peak memory 214196 kb
Host smart-e39c4525-0050-4d95-8814-3efe589109c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442821226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.2442821226
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.4120255181
Short name T11
Test name
Test status
Simulation time 1025579850 ps
CPU time 8.85 seconds
Started Mar 05 01:19:16 PM PST 24
Finished Mar 05 01:19:25 PM PST 24
Peak memory 231012 kb
Host smart-ba5cc99e-8635-45b1-a601-520940a7ab77
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4120255181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.4120255181
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.1920519876
Short name T459
Test name
Test status
Simulation time 185311609 ps
CPU time 5.79 seconds
Started Mar 05 01:19:32 PM PST 24
Finished Mar 05 01:19:40 PM PST 24
Peak memory 207496 kb
Host smart-24b1c6e7-3324-4abc-86aa-621d9e57fc19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920519876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.1920519876
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.3364665423
Short name T530
Test name
Test status
Simulation time 87314888 ps
CPU time 3.76 seconds
Started Mar 05 01:19:05 PM PST 24
Finished Mar 05 01:19:10 PM PST 24
Peak memory 208280 kb
Host smart-a7e1d7d9-f830-4386-876e-f1c06575ed3e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3364665423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.3364665423
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.1214845861
Short name T590
Test name
Test status
Simulation time 220741021 ps
CPU time 2.95 seconds
Started Mar 05 01:19:14 PM PST 24
Finished Mar 05 01:19:18 PM PST 24
Peak memory 208376 kb
Host smart-606a8ed0-8233-4aeb-979c-a40c5a63bcf8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214845861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.1214845861
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.1941108331
Short name T841
Test name
Test status
Simulation time 150964484 ps
CPU time 4.95 seconds
Started Mar 05 01:19:10 PM PST 24
Finished Mar 05 01:19:15 PM PST 24
Peak memory 207532 kb
Host smart-f84a8d36-3602-4d85-9423-5dec6ee9f74d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941108331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.1941108331
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.764598869
Short name T511
Test name
Test status
Simulation time 571881565 ps
CPU time 4.04 seconds
Started Mar 05 01:19:26 PM PST 24
Finished Mar 05 01:19:30 PM PST 24
Peak memory 209748 kb
Host smart-1ad5dfc9-0370-47c8-8b54-c53e10f1d619
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764598869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.764598869
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.1560878653
Short name T628
Test name
Test status
Simulation time 91181875 ps
CPU time 1.73 seconds
Started Mar 05 01:19:04 PM PST 24
Finished Mar 05 01:19:06 PM PST 24
Peak memory 206272 kb
Host smart-17d3b906-91cd-4097-812a-92affc85609d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560878653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.1560878653
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.2095161092
Short name T627
Test name
Test status
Simulation time 335795884 ps
CPU time 4.28 seconds
Started Mar 05 01:19:15 PM PST 24
Finished Mar 05 01:19:20 PM PST 24
Peak memory 214212 kb
Host smart-37ef70f1-d255-4e0d-a964-e2d8f83853c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2095161092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.2095161092
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.2931889224
Short name T376
Test name
Test status
Simulation time 81252857 ps
CPU time 2.53 seconds
Started Mar 05 01:19:09 PM PST 24
Finished Mar 05 01:19:12 PM PST 24
Peak memory 209752 kb
Host smart-188dc79a-881a-43e1-94aa-13b2a87b5ac1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2931889224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.2931889224
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.1275467832
Short name T858
Test name
Test status
Simulation time 23887766 ps
CPU time 0.9 seconds
Started Mar 05 01:21:00 PM PST 24
Finished Mar 05 01:21:01 PM PST 24
Peak memory 205820 kb
Host smart-a6aefd85-0b78-49ef-b955-aef6497d65c6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1275467832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.1275467832
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.1245751162
Short name T420
Test name
Test status
Simulation time 30045188 ps
CPU time 2.41 seconds
Started Mar 05 01:21:03 PM PST 24
Finished Mar 05 01:21:06 PM PST 24
Peak memory 214160 kb
Host smart-a8be7a09-eccc-4f35-8e47-5881088f89bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1245751162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.1245751162
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.1351414829
Short name T499
Test name
Test status
Simulation time 92992413 ps
CPU time 1.91 seconds
Started Mar 05 01:21:00 PM PST 24
Finished Mar 05 01:21:02 PM PST 24
Peak memory 218104 kb
Host smart-38647c21-92dd-464b-be5d-6407bc744159
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1351414829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.1351414829
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.2171209414
Short name T59
Test name
Test status
Simulation time 122989462 ps
CPU time 2.81 seconds
Started Mar 05 01:21:04 PM PST 24
Finished Mar 05 01:21:12 PM PST 24
Peak memory 207092 kb
Host smart-325bd019-a682-4211-82d3-300c08e09cfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2171209414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.2171209414
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.2105345502
Short name T93
Test name
Test status
Simulation time 253093646 ps
CPU time 3.66 seconds
Started Mar 05 01:20:55 PM PST 24
Finished Mar 05 01:20:59 PM PST 24
Peak memory 208428 kb
Host smart-c50b58f0-a549-4bb3-a214-0a07c5a57065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105345502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.2105345502
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.3793587951
Short name T298
Test name
Test status
Simulation time 106489361 ps
CPU time 3.74 seconds
Started Mar 05 01:21:20 PM PST 24
Finished Mar 05 01:21:24 PM PST 24
Peak memory 222264 kb
Host smart-59d007e5-19f2-41bb-aa89-94f0e34dba42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3793587951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.3793587951
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.3807258668
Short name T7
Test name
Test status
Simulation time 221698670 ps
CPU time 4.15 seconds
Started Mar 05 01:21:01 PM PST 24
Finished Mar 05 01:21:07 PM PST 24
Peak memory 214072 kb
Host smart-5f3393a2-f3eb-4a14-8640-85d36fe8a11b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807258668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.3807258668
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.3669854785
Short name T365
Test name
Test status
Simulation time 54982748 ps
CPU time 3.41 seconds
Started Mar 05 01:20:55 PM PST 24
Finished Mar 05 01:20:58 PM PST 24
Peak memory 209436 kb
Host smart-471110fd-0f63-4f27-893f-9683b02e3656
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669854785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.3669854785
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.1952621824
Short name T398
Test name
Test status
Simulation time 329019998 ps
CPU time 5.05 seconds
Started Mar 05 01:20:56 PM PST 24
Finished Mar 05 01:21:02 PM PST 24
Peak memory 208160 kb
Host smart-d923c9ba-74f0-4d0b-b5ab-78ffebc905f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952621824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.1952621824
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.1044469117
Short name T461
Test name
Test status
Simulation time 1593596577 ps
CPU time 55.45 seconds
Started Mar 05 01:20:52 PM PST 24
Finished Mar 05 01:21:48 PM PST 24
Peak memory 208196 kb
Host smart-674d995d-550b-4976-a79d-db507fb43308
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044469117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.1044469117
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.2549150382
Short name T700
Test name
Test status
Simulation time 137850193 ps
CPU time 3.35 seconds
Started Mar 05 01:20:48 PM PST 24
Finished Mar 05 01:20:52 PM PST 24
Peak memory 208292 kb
Host smart-af217343-9a12-438f-8b4d-8900ca141793
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2549150382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.2549150382
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.1277980999
Short name T79
Test name
Test status
Simulation time 67642307 ps
CPU time 3.39 seconds
Started Mar 05 01:20:54 PM PST 24
Finished Mar 05 01:20:57 PM PST 24
Peak memory 208096 kb
Host smart-a640c5c0-4b6c-4bb8-bdf4-cf9e2b1db394
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277980999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.1277980999
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.3670813614
Short name T362
Test name
Test status
Simulation time 113271320 ps
CPU time 4.6 seconds
Started Mar 05 01:21:23 PM PST 24
Finished Mar 05 01:21:28 PM PST 24
Peak memory 208608 kb
Host smart-3664d5d3-9b5b-49a6-a653-b802c22392e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3670813614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.3670813614
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.2052053796
Short name T464
Test name
Test status
Simulation time 62824342 ps
CPU time 3 seconds
Started Mar 05 01:20:58 PM PST 24
Finished Mar 05 01:21:02 PM PST 24
Peak memory 206460 kb
Host smart-0bd79096-8ca7-4253-804f-5ab692585143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052053796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.2052053796
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.3986387527
Short name T331
Test name
Test status
Simulation time 58795740 ps
CPU time 2.49 seconds
Started Mar 05 01:21:05 PM PST 24
Finished Mar 05 01:21:10 PM PST 24
Peak memory 207400 kb
Host smart-159aba42-a8a4-48a6-af2d-7002f0a42372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986387527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.3986387527
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.1293608539
Short name T556
Test name
Test status
Simulation time 54014190 ps
CPU time 2.87 seconds
Started Mar 05 01:20:53 PM PST 24
Finished Mar 05 01:20:56 PM PST 24
Peak memory 209596 kb
Host smart-aff02e34-25f6-4a49-9b31-deb3817c76d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1293608539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.1293608539
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.3874054483
Short name T98
Test name
Test status
Simulation time 31468916 ps
CPU time 0.8 seconds
Started Mar 05 01:21:00 PM PST 24
Finished Mar 05 01:21:01 PM PST 24
Peak memory 205900 kb
Host smart-3ddd7776-f2b1-42a7-b743-5430342462e5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3874054483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.3874054483
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.302270596
Short name T225
Test name
Test status
Simulation time 59488588 ps
CPU time 2.54 seconds
Started Mar 05 01:21:01 PM PST 24
Finished Mar 05 01:21:05 PM PST 24
Peak memory 214024 kb
Host smart-eb59446d-b6f4-42b1-bc43-cef85885e6a0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=302270596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.302270596
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.3896274355
Short name T768
Test name
Test status
Simulation time 50177529 ps
CPU time 2.69 seconds
Started Mar 05 01:20:57 PM PST 24
Finished Mar 05 01:21:00 PM PST 24
Peak memory 209016 kb
Host smart-07e43c9a-53f9-4e5a-8e3e-d5784b434abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896274355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.3896274355
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.1179566525
Short name T574
Test name
Test status
Simulation time 427465580 ps
CPU time 3.47 seconds
Started Mar 05 01:21:01 PM PST 24
Finished Mar 05 01:21:06 PM PST 24
Peak memory 217396 kb
Host smart-171a6297-a106-435b-a424-22c372f48155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179566525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.1179566525
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.626585328
Short name T783
Test name
Test status
Simulation time 288700882 ps
CPU time 8.72 seconds
Started Mar 05 01:21:01 PM PST 24
Finished Mar 05 01:21:15 PM PST 24
Peak memory 222244 kb
Host smart-5cff70a1-c392-46fe-b017-f263201ad810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626585328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.626585328
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.2756359012
Short name T601
Test name
Test status
Simulation time 196237008 ps
CPU time 3.12 seconds
Started Mar 05 01:21:01 PM PST 24
Finished Mar 05 01:21:04 PM PST 24
Peak memory 214144 kb
Host smart-43636183-65c4-4127-b322-57b344e5c3d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756359012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.2756359012
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.3944889923
Short name T320
Test name
Test status
Simulation time 70838731 ps
CPU time 3.03 seconds
Started Mar 05 01:20:59 PM PST 24
Finished Mar 05 01:21:03 PM PST 24
Peak memory 207648 kb
Host smart-909003ea-bdac-4caf-956e-6dc21e727d11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3944889923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.3944889923
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.3251109480
Short name T750
Test name
Test status
Simulation time 147062226 ps
CPU time 4.26 seconds
Started Mar 05 01:21:00 PM PST 24
Finished Mar 05 01:21:09 PM PST 24
Peak memory 208168 kb
Host smart-12a85764-ef06-44ed-a853-e9e2dff6820c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251109480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.3251109480
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.2269954079
Short name T582
Test name
Test status
Simulation time 739886629 ps
CPU time 8.36 seconds
Started Mar 05 01:20:56 PM PST 24
Finished Mar 05 01:21:05 PM PST 24
Peak memory 207588 kb
Host smart-39fd4618-24cb-4251-9696-2e164aa84db9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2269954079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.2269954079
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.1912648338
Short name T581
Test name
Test status
Simulation time 576556057 ps
CPU time 5.63 seconds
Started Mar 05 01:21:11 PM PST 24
Finished Mar 05 01:21:17 PM PST 24
Peak memory 207632 kb
Host smart-3fe04226-24b6-481d-8c8c-690886582fbb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1912648338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.1912648338
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.1126517803
Short name T490
Test name
Test status
Simulation time 874980706 ps
CPU time 8.89 seconds
Started Mar 05 01:20:56 PM PST 24
Finished Mar 05 01:21:06 PM PST 24
Peak memory 207828 kb
Host smart-5b99d2d5-690b-4db2-9895-961c406be1d5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126517803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.1126517803
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.2821650011
Short name T900
Test name
Test status
Simulation time 46238611 ps
CPU time 2.87 seconds
Started Mar 05 01:21:10 PM PST 24
Finished Mar 05 01:21:13 PM PST 24
Peak memory 209964 kb
Host smart-a2fca52f-9860-4c1e-a529-84bdf913380c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2821650011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.2821650011
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.1806696939
Short name T469
Test name
Test status
Simulation time 103651932 ps
CPU time 2.26 seconds
Started Mar 05 01:21:00 PM PST 24
Finished Mar 05 01:21:03 PM PST 24
Peak memory 208436 kb
Host smart-2e29077e-3149-4e1a-9db8-6525bd05f7c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806696939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.1806696939
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.197481009
Short name T578
Test name
Test status
Simulation time 304629641 ps
CPU time 15.27 seconds
Started Mar 05 01:20:55 PM PST 24
Finished Mar 05 01:21:11 PM PST 24
Peak memory 215968 kb
Host smart-60951a56-d7f7-4662-8d1a-c24df5c65a90
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197481009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.197481009
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_stress_all_with_rand_reset.734957132
Short name T124
Test name
Test status
Simulation time 605020175 ps
CPU time 10.23 seconds
Started Mar 05 01:21:01 PM PST 24
Finished Mar 05 01:21:11 PM PST 24
Peak memory 222460 kb
Host smart-21071f2a-d51e-408c-8978-4c331ed19e45
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=734957132 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all_with_rand_reset.734957132
Directory /workspace/41.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.534528275
Short name T274
Test name
Test status
Simulation time 1414103123 ps
CPU time 5.3 seconds
Started Mar 05 01:21:11 PM PST 24
Finished Mar 05 01:21:16 PM PST 24
Peak memory 207700 kb
Host smart-3deda963-e121-48fc-a32a-67a9079a3945
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=534528275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.534528275
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.128542953
Short name T668
Test name
Test status
Simulation time 22443910 ps
CPU time 1.56 seconds
Started Mar 05 01:20:59 PM PST 24
Finished Mar 05 01:21:05 PM PST 24
Peak memory 209488 kb
Host smart-eca97ebe-54ac-4b5a-ab31-b8684b25cea0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128542953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.128542953
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.1111983655
Short name T705
Test name
Test status
Simulation time 12196675 ps
CPU time 0.84 seconds
Started Mar 05 01:20:55 PM PST 24
Finished Mar 05 01:20:56 PM PST 24
Peak memory 205800 kb
Host smart-496f7a42-6ab9-41e1-a8b8-75790ce81c75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111983655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.1111983655
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.2559624148
Short name T817
Test name
Test status
Simulation time 279893800 ps
CPU time 7.94 seconds
Started Mar 05 01:20:57 PM PST 24
Finished Mar 05 01:21:05 PM PST 24
Peak memory 222536 kb
Host smart-d627ea54-45d9-4f42-b9af-0affc5c16649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559624148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.2559624148
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.3078745989
Short name T899
Test name
Test status
Simulation time 1021127288 ps
CPU time 2.57 seconds
Started Mar 05 01:20:57 PM PST 24
Finished Mar 05 01:21:00 PM PST 24
Peak memory 207192 kb
Host smart-01038253-e0da-4333-af5b-73ec8ccade48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078745989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.3078745989
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.3306559637
Short name T492
Test name
Test status
Simulation time 58998232 ps
CPU time 3.52 seconds
Started Mar 05 01:21:03 PM PST 24
Finished Mar 05 01:21:07 PM PST 24
Peak memory 209816 kb
Host smart-2c8b9b39-ead8-4c61-a02a-b55331d2b352
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306559637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.3306559637
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.1511483147
Short name T602
Test name
Test status
Simulation time 126548192 ps
CPU time 3.06 seconds
Started Mar 05 01:20:57 PM PST 24
Finished Mar 05 01:21:00 PM PST 24
Peak memory 220160 kb
Host smart-5a1af7fa-0511-49f6-8be8-8714018d7499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511483147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.1511483147
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.365538245
Short name T869
Test name
Test status
Simulation time 2007959735 ps
CPU time 42.58 seconds
Started Mar 05 01:20:58 PM PST 24
Finished Mar 05 01:21:41 PM PST 24
Peak memory 208912 kb
Host smart-c37c7b43-70b6-418c-9bf9-9703a7ba3a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365538245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.365538245
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.926094153
Short name T248
Test name
Test status
Simulation time 1125461526 ps
CPU time 12.66 seconds
Started Mar 05 01:21:01 PM PST 24
Finished Mar 05 01:21:13 PM PST 24
Peak memory 206500 kb
Host smart-e7a9a8b9-5733-4bc5-a621-08b4cae928e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926094153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.926094153
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.3080183584
Short name T718
Test name
Test status
Simulation time 453392509 ps
CPU time 3.53 seconds
Started Mar 05 01:21:01 PM PST 24
Finished Mar 05 01:21:06 PM PST 24
Peak memory 208588 kb
Host smart-4a112cc8-b907-4265-a8e6-917aa0bee65c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3080183584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.3080183584
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.730962643
Short name T745
Test name
Test status
Simulation time 3705119726 ps
CPU time 51.12 seconds
Started Mar 05 01:20:56 PM PST 24
Finished Mar 05 01:21:48 PM PST 24
Peak memory 208780 kb
Host smart-97217a88-8f8a-4cdc-ad45-0c7063d1fd8f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=730962643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.730962643
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.1719131475
Short name T437
Test name
Test status
Simulation time 208091807 ps
CPU time 2.91 seconds
Started Mar 05 01:20:57 PM PST 24
Finished Mar 05 01:21:01 PM PST 24
Peak memory 208372 kb
Host smart-fed7dfb6-4ae5-4e67-ab4d-8197a5245826
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719131475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.1719131475
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.2029814002
Short name T629
Test name
Test status
Simulation time 1498927707 ps
CPU time 4.38 seconds
Started Mar 05 01:21:00 PM PST 24
Finished Mar 05 01:21:04 PM PST 24
Peak memory 209372 kb
Host smart-41495282-a333-4fa6-a1c5-64667e4ba39b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029814002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.2029814002
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.3285270339
Short name T559
Test name
Test status
Simulation time 141370668 ps
CPU time 2.3 seconds
Started Mar 05 01:20:57 PM PST 24
Finished Mar 05 01:21:00 PM PST 24
Peak memory 206048 kb
Host smart-874279dc-8673-478c-903b-4fed90ba6ec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285270339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.3285270339
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.2739389864
Short name T318
Test name
Test status
Simulation time 175522589 ps
CPU time 8.66 seconds
Started Mar 05 01:21:04 PM PST 24
Finished Mar 05 01:21:12 PM PST 24
Peak memory 222084 kb
Host smart-0b1153a2-10bd-4037-877a-392f74c9f0e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739389864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.2739389864
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.1034529915
Short name T389
Test name
Test status
Simulation time 205953985 ps
CPU time 3.14 seconds
Started Mar 05 01:21:02 PM PST 24
Finished Mar 05 01:21:06 PM PST 24
Peak memory 207476 kb
Host smart-6ebaccb1-7312-4373-8754-9239896eba56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1034529915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.1034529915
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.1627922372
Short name T384
Test name
Test status
Simulation time 333279231 ps
CPU time 3.43 seconds
Started Mar 05 01:21:14 PM PST 24
Finished Mar 05 01:21:18 PM PST 24
Peak memory 209336 kb
Host smart-9c7c3111-17df-4c7d-81ea-74d13dfbfb00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627922372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.1627922372
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.3890986533
Short name T594
Test name
Test status
Simulation time 83973431 ps
CPU time 0.89 seconds
Started Mar 05 01:21:06 PM PST 24
Finished Mar 05 01:21:07 PM PST 24
Peak memory 205880 kb
Host smart-eb6efb76-80aa-40de-b8f3-6f2247f35ad5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890986533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.3890986533
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.522277344
Short name T422
Test name
Test status
Simulation time 779100587 ps
CPU time 21.07 seconds
Started Mar 05 01:21:07 PM PST 24
Finished Mar 05 01:21:29 PM PST 24
Peak memory 222220 kb
Host smart-5a076a26-3cac-4f77-a990-152d45c3b1fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=522277344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.522277344
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.1113765528
Short name T9
Test name
Test status
Simulation time 358076829 ps
CPU time 5.58 seconds
Started Mar 05 01:21:06 PM PST 24
Finished Mar 05 01:21:12 PM PST 24
Peak memory 214400 kb
Host smart-c3e6b1bc-d741-4007-ad8b-6faa33f64fd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113765528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.1113765528
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.3804684131
Short name T714
Test name
Test status
Simulation time 154150029 ps
CPU time 2.72 seconds
Started Mar 05 01:21:04 PM PST 24
Finished Mar 05 01:21:07 PM PST 24
Peak memory 214160 kb
Host smart-9676bcbc-6838-4f51-ae5e-be248bf4893f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3804684131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.3804684131
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.3052651039
Short name T23
Test name
Test status
Simulation time 125468540 ps
CPU time 3.28 seconds
Started Mar 05 01:21:01 PM PST 24
Finished Mar 05 01:21:04 PM PST 24
Peak memory 208732 kb
Host smart-85140e3c-c540-43ca-9255-4e12fb37420a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052651039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.3052651039
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.1164839720
Short name T760
Test name
Test status
Simulation time 48987060 ps
CPU time 3.69 seconds
Started Mar 05 01:20:57 PM PST 24
Finished Mar 05 01:21:01 PM PST 24
Peak memory 220072 kb
Host smart-f8b11201-e55e-41eb-b2be-27c629e9530f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1164839720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.1164839720
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.1685132056
Short name T314
Test name
Test status
Simulation time 627071702 ps
CPU time 4.57 seconds
Started Mar 05 01:21:08 PM PST 24
Finished Mar 05 01:21:14 PM PST 24
Peak memory 207196 kb
Host smart-6183f20d-cdc7-4dc4-9a85-1e2ef1829f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685132056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.1685132056
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.1415400553
Short name T632
Test name
Test status
Simulation time 1310879208 ps
CPU time 9.44 seconds
Started Mar 05 01:21:24 PM PST 24
Finished Mar 05 01:21:34 PM PST 24
Peak memory 207920 kb
Host smart-b9900bf4-d8eb-4d32-b35c-c4e3f53c33ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415400553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.1415400553
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.1512683216
Short name T716
Test name
Test status
Simulation time 181466349 ps
CPU time 2.72 seconds
Started Mar 05 01:21:15 PM PST 24
Finished Mar 05 01:21:18 PM PST 24
Peak memory 206256 kb
Host smart-d9007be6-ffe8-4725-ac5d-235d240c60a0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512683216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.1512683216
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.445456975
Short name T455
Test name
Test status
Simulation time 74423882 ps
CPU time 2.97 seconds
Started Mar 05 01:20:57 PM PST 24
Finished Mar 05 01:21:00 PM PST 24
Peak memory 206516 kb
Host smart-2180aba2-f935-4bf5-af8c-e32bf1b2a4be
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445456975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.445456975
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.481301894
Short name T566
Test name
Test status
Simulation time 212326255 ps
CPU time 2.8 seconds
Started Mar 05 01:21:09 PM PST 24
Finished Mar 05 01:21:12 PM PST 24
Peak memory 208048 kb
Host smart-c865a5a5-e3cb-4480-b498-eff18eb50fe8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481301894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.481301894
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.3712446462
Short name T592
Test name
Test status
Simulation time 47429822 ps
CPU time 2.12 seconds
Started Mar 05 01:21:00 PM PST 24
Finished Mar 05 01:21:02 PM PST 24
Peak memory 209228 kb
Host smart-4a697112-e7f9-41af-b4f5-2d43825ccf55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712446462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.3712446462
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.2614451889
Short name T798
Test name
Test status
Simulation time 359215895 ps
CPU time 4.09 seconds
Started Mar 05 01:21:16 PM PST 24
Finished Mar 05 01:21:20 PM PST 24
Peak memory 206180 kb
Host smart-6721afad-19a7-420f-8f68-c7ff43b6c66a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614451889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.2614451889
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all_with_rand_reset.473975315
Short name T579
Test name
Test status
Simulation time 282485480 ps
CPU time 16.77 seconds
Started Mar 05 01:20:56 PM PST 24
Finished Mar 05 01:21:13 PM PST 24
Peak memory 222332 kb
Host smart-3b3905be-b34a-4c73-88bd-9cf105982609
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473975315 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all_with_rand_reset.473975315
Directory /workspace/43.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.1154576773
Short name T81
Test name
Test status
Simulation time 227241580 ps
CPU time 5.02 seconds
Started Mar 05 01:21:00 PM PST 24
Finished Mar 05 01:21:06 PM PST 24
Peak memory 209664 kb
Host smart-b460af72-e32f-46a3-a9b6-8aaed98581cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154576773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.1154576773
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.3576564222
Short name T382
Test name
Test status
Simulation time 152018205 ps
CPU time 1.99 seconds
Started Mar 05 01:21:05 PM PST 24
Finished Mar 05 01:21:07 PM PST 24
Peak memory 210440 kb
Host smart-127e66fa-88bd-460e-aede-ec460488c003
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3576564222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.3576564222
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.2205383108
Short name T584
Test name
Test status
Simulation time 18503176 ps
CPU time 0.93 seconds
Started Mar 05 01:21:03 PM PST 24
Finished Mar 05 01:21:05 PM PST 24
Peak memory 205944 kb
Host smart-d90e0ad0-a381-4e05-9623-34c29d65c651
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205383108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.2205383108
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.1814248477
Short name T678
Test name
Test status
Simulation time 396377734 ps
CPU time 4.26 seconds
Started Mar 05 01:21:17 PM PST 24
Finished Mar 05 01:21:22 PM PST 24
Peak memory 208312 kb
Host smart-aef254a9-0a4b-474d-b688-8ce6ebc067ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814248477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.1814248477
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.4052661238
Short name T763
Test name
Test status
Simulation time 77371264 ps
CPU time 2.43 seconds
Started Mar 05 01:20:53 PM PST 24
Finished Mar 05 01:20:56 PM PST 24
Peak memory 209596 kb
Host smart-d2ead2da-45de-43b3-8891-0bac09a30af5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4052661238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.4052661238
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.3272833918
Short name T883
Test name
Test status
Simulation time 445535811 ps
CPU time 6.06 seconds
Started Mar 05 01:21:00 PM PST 24
Finished Mar 05 01:21:06 PM PST 24
Peak memory 209160 kb
Host smart-6c7451ca-634a-4753-b88f-9fd945339b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3272833918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.3272833918
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.146389203
Short name T665
Test name
Test status
Simulation time 3354228317 ps
CPU time 54.82 seconds
Started Mar 05 01:21:20 PM PST 24
Finished Mar 05 01:22:15 PM PST 24
Peak memory 221448 kb
Host smart-fdebb9e2-4af9-444f-926a-34679067c1fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146389203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.146389203
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.2519641440
Short name T217
Test name
Test status
Simulation time 251772603 ps
CPU time 3.5 seconds
Started Mar 05 01:21:13 PM PST 24
Finished Mar 05 01:21:17 PM PST 24
Peak memory 214064 kb
Host smart-4d7387ba-e0ba-4192-9f19-166aec89539c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2519641440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.2519641440
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.1257419410
Short name T637
Test name
Test status
Simulation time 315449217 ps
CPU time 7.8 seconds
Started Mar 05 01:21:23 PM PST 24
Finished Mar 05 01:21:31 PM PST 24
Peak memory 209020 kb
Host smart-a3ffdee6-0c8f-4372-8643-c5836ad8aeab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1257419410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.1257419410
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.3051314736
Short name T272
Test name
Test status
Simulation time 320323230 ps
CPU time 3.96 seconds
Started Mar 05 01:21:20 PM PST 24
Finished Mar 05 01:21:24 PM PST 24
Peak memory 208360 kb
Host smart-38352994-bf7e-44be-b2f1-842c81bf318e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051314736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.3051314736
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.1319151413
Short name T660
Test name
Test status
Simulation time 815179805 ps
CPU time 7.62 seconds
Started Mar 05 01:21:00 PM PST 24
Finished Mar 05 01:21:08 PM PST 24
Peak memory 208600 kb
Host smart-c063cb44-68bb-436a-8f89-d898b866d121
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319151413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.1319151413
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.4138235647
Short name T784
Test name
Test status
Simulation time 86116626 ps
CPU time 3.25 seconds
Started Mar 05 01:20:55 PM PST 24
Finished Mar 05 01:20:58 PM PST 24
Peak memory 207404 kb
Host smart-51b59a8f-bd52-4a9a-8b14-f46f9daa9472
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138235647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.4138235647
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.1255231893
Short name T761
Test name
Test status
Simulation time 2115782930 ps
CPU time 22.91 seconds
Started Mar 05 01:20:56 PM PST 24
Finished Mar 05 01:21:20 PM PST 24
Peak memory 208724 kb
Host smart-035c9094-65ab-4891-a36f-804fc970ed0b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255231893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.1255231893
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.3102605119
Short name T311
Test name
Test status
Simulation time 166583100 ps
CPU time 3.16 seconds
Started Mar 05 01:21:00 PM PST 24
Finished Mar 05 01:21:03 PM PST 24
Peak memory 209648 kb
Host smart-854962a1-a244-4188-9c58-d59f69eaee2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3102605119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.3102605119
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.707196750
Short name T470
Test name
Test status
Simulation time 116918917 ps
CPU time 3.08 seconds
Started Mar 05 01:21:21 PM PST 24
Finished Mar 05 01:21:24 PM PST 24
Peak memory 206392 kb
Host smart-8453b961-3f3e-49ff-b163-70769fe24514
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707196750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.707196750
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.2904394790
Short name T888
Test name
Test status
Simulation time 5220983168 ps
CPU time 64.88 seconds
Started Mar 05 01:20:58 PM PST 24
Finished Mar 05 01:22:04 PM PST 24
Peak memory 222336 kb
Host smart-9e2096f6-5f98-4255-9844-20ba63416a6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2904394790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.2904394790
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_stress_all_with_rand_reset.1821037365
Short name T863
Test name
Test status
Simulation time 134529303 ps
CPU time 8.65 seconds
Started Mar 05 01:20:59 PM PST 24
Finished Mar 05 01:21:08 PM PST 24
Peak memory 222316 kb
Host smart-72670a9b-c3ba-42f4-9ba8-c4332c701b61
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821037365 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all_with_rand_reset.1821037365
Directory /workspace/44.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.2522073109
Short name T339
Test name
Test status
Simulation time 372237823 ps
CPU time 7.59 seconds
Started Mar 05 01:21:06 PM PST 24
Finished Mar 05 01:21:14 PM PST 24
Peak memory 214052 kb
Host smart-29c1d6a6-7b35-49e7-967b-1ae53f1bd329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522073109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.2522073109
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.2176187366
Short name T120
Test name
Test status
Simulation time 193577580 ps
CPU time 2.37 seconds
Started Mar 05 01:20:57 PM PST 24
Finished Mar 05 01:21:00 PM PST 24
Peak memory 209700 kb
Host smart-29efc1aa-fd28-402f-ab60-e9fbd872709f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176187366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.2176187366
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.3371018367
Short name T439
Test name
Test status
Simulation time 117340208 ps
CPU time 0.77 seconds
Started Mar 05 01:21:01 PM PST 24
Finished Mar 05 01:21:02 PM PST 24
Peak memory 205640 kb
Host smart-3c6862a0-c03b-4e69-9a92-630c9f2236b5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371018367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.3371018367
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.4206914007
Short name T254
Test name
Test status
Simulation time 632078645 ps
CPU time 17.59 seconds
Started Mar 05 01:21:12 PM PST 24
Finished Mar 05 01:21:30 PM PST 24
Peak memory 214156 kb
Host smart-bddd30fd-f0ac-4e06-a43f-1656918117d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4206914007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.4206914007
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.4153356744
Short name T840
Test name
Test status
Simulation time 102662266 ps
CPU time 4.5 seconds
Started Mar 05 01:20:59 PM PST 24
Finished Mar 05 01:21:04 PM PST 24
Peak memory 209288 kb
Host smart-45fb6758-5ef3-4864-99b8-812ff2c7da65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153356744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.4153356744
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.700255927
Short name T844
Test name
Test status
Simulation time 56708794 ps
CPU time 2.91 seconds
Started Mar 05 01:21:01 PM PST 24
Finished Mar 05 01:21:06 PM PST 24
Peak memory 213932 kb
Host smart-9268f89e-8fe9-4eac-ae97-3ac8594614be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700255927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.700255927
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.74065594
Short name T544
Test name
Test status
Simulation time 56713765 ps
CPU time 3.38 seconds
Started Mar 05 01:20:57 PM PST 24
Finished Mar 05 01:21:01 PM PST 24
Peak memory 218460 kb
Host smart-7c4fb3db-81c2-414c-9bb2-3a47df6f7974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=74065594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.74065594
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.639162614
Short name T717
Test name
Test status
Simulation time 103225134 ps
CPU time 4.95 seconds
Started Mar 05 01:21:09 PM PST 24
Finished Mar 05 01:21:14 PM PST 24
Peak memory 211212 kb
Host smart-5b782f22-0840-4729-bbd7-8af36d3a67c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639162614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.639162614
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.1890236119
Short name T591
Test name
Test status
Simulation time 87129117 ps
CPU time 2.78 seconds
Started Mar 05 01:21:08 PM PST 24
Finished Mar 05 01:21:11 PM PST 24
Peak memory 209344 kb
Host smart-b54519a2-217b-4014-98d4-e5d8031687d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1890236119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.1890236119
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.205283618
Short name T651
Test name
Test status
Simulation time 388523723 ps
CPU time 5.48 seconds
Started Mar 05 01:21:01 PM PST 24
Finished Mar 05 01:21:06 PM PST 24
Peak memory 218120 kb
Host smart-3ff433fd-a5cc-4e1e-a1a1-0260743fa660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=205283618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.205283618
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.3092904333
Short name T194
Test name
Test status
Simulation time 34349002 ps
CPU time 2.39 seconds
Started Mar 05 01:21:03 PM PST 24
Finished Mar 05 01:21:06 PM PST 24
Peak memory 206420 kb
Host smart-5fb956b1-f6b8-4748-8ede-4c86eb4a2c86
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092904333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.3092904333
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.874476695
Short name T625
Test name
Test status
Simulation time 2353840982 ps
CPU time 4.89 seconds
Started Mar 05 01:21:26 PM PST 24
Finished Mar 05 01:21:31 PM PST 24
Peak memory 207892 kb
Host smart-1ca24871-5491-44da-95a9-fb885644b7f1
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874476695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.874476695
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.2157028296
Short name T565
Test name
Test status
Simulation time 345074347 ps
CPU time 7.68 seconds
Started Mar 05 01:20:55 PM PST 24
Finished Mar 05 01:21:04 PM PST 24
Peak memory 208416 kb
Host smart-6c8ff510-e37d-4be2-a4be-617101790912
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157028296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.2157028296
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.4131795441
Short name T773
Test name
Test status
Simulation time 68609385 ps
CPU time 3.56 seconds
Started Mar 05 01:21:08 PM PST 24
Finished Mar 05 01:21:12 PM PST 24
Peak memory 206564 kb
Host smart-6a3b1615-2c3d-47d7-8b92-4fc1868e963f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4131795441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.4131795441
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.1437929094
Short name T631
Test name
Test status
Simulation time 221256985 ps
CPU time 2.48 seconds
Started Mar 05 01:20:59 PM PST 24
Finished Mar 05 01:21:02 PM PST 24
Peak memory 207596 kb
Host smart-edf4ec84-057a-4c6f-a22b-b4669617b25e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437929094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.1437929094
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.2781842876
Short name T704
Test name
Test status
Simulation time 50979299 ps
CPU time 2.13 seconds
Started Mar 05 01:21:02 PM PST 24
Finished Mar 05 01:21:05 PM PST 24
Peak memory 208340 kb
Host smart-9c4cf1c8-5516-4f75-8334-fe80b881565d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2781842876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.2781842876
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all_with_rand_reset.1387687920
Short name T167
Test name
Test status
Simulation time 406022413 ps
CPU time 14.06 seconds
Started Mar 05 01:21:00 PM PST 24
Finished Mar 05 01:21:15 PM PST 24
Peak memory 222388 kb
Host smart-d6e835b8-bebd-40eb-9f39-a81e6ead1d29
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387687920 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all_with_rand_reset.1387687920
Directory /workspace/45.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.139837383
Short name T701
Test name
Test status
Simulation time 1317893902 ps
CPU time 18.79 seconds
Started Mar 05 01:21:05 PM PST 24
Finished Mar 05 01:21:25 PM PST 24
Peak memory 209644 kb
Host smart-0a1f5f71-b33b-4037-9939-c70d6c6ff208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=139837383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.139837383
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.3998876842
Short name T37
Test name
Test status
Simulation time 550852377 ps
CPU time 13.22 seconds
Started Mar 05 01:20:59 PM PST 24
Finished Mar 05 01:21:13 PM PST 24
Peak memory 210772 kb
Host smart-8caed550-8065-48bf-a8f0-0df6e51c5ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3998876842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.3998876842
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.58692211
Short name T506
Test name
Test status
Simulation time 13519261 ps
CPU time 0.94 seconds
Started Mar 05 01:21:20 PM PST 24
Finished Mar 05 01:21:21 PM PST 24
Peak memory 205944 kb
Host smart-7b063c72-b532-405a-b246-239483494e74
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58692211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.58692211
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.3397387264
Short name T270
Test name
Test status
Simulation time 38803335 ps
CPU time 3.1 seconds
Started Mar 05 01:21:04 PM PST 24
Finished Mar 05 01:21:08 PM PST 24
Peak memory 214160 kb
Host smart-5d8dff88-d1e1-4c7e-ad39-91ad484bb638
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3397387264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.3397387264
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.3425767605
Short name T731
Test name
Test status
Simulation time 435456929 ps
CPU time 3.62 seconds
Started Mar 05 01:21:02 PM PST 24
Finished Mar 05 01:21:07 PM PST 24
Peak memory 209448 kb
Host smart-96791e00-1ba9-4314-bc74-97ebb2edb221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3425767605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.3425767605
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.3223589073
Short name T75
Test name
Test status
Simulation time 1073335516 ps
CPU time 13.67 seconds
Started Mar 05 01:21:02 PM PST 24
Finished Mar 05 01:21:17 PM PST 24
Peak memory 208220 kb
Host smart-ae943b60-0181-4770-810e-d23518f240e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223589073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.3223589073
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.2537010908
Short name T24
Test name
Test status
Simulation time 2415015728 ps
CPU time 6.19 seconds
Started Mar 05 01:21:12 PM PST 24
Finished Mar 05 01:21:19 PM PST 24
Peak memory 219096 kb
Host smart-44aee2ab-05a2-43a7-99e7-3767b63b3b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537010908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.2537010908
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.1634285990
Short name T191
Test name
Test status
Simulation time 145231058 ps
CPU time 2.66 seconds
Started Mar 05 01:21:00 PM PST 24
Finished Mar 05 01:21:03 PM PST 24
Peak memory 220888 kb
Host smart-769e4095-4afb-4ad1-b0c0-b013f7ff05dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634285990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.1634285990
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.1944352945
Short name T222
Test name
Test status
Simulation time 186898621 ps
CPU time 2.99 seconds
Started Mar 05 01:21:02 PM PST 24
Finished Mar 05 01:21:06 PM PST 24
Peak memory 209108 kb
Host smart-0627e9fa-937c-41d2-b747-843816eef39f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944352945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.1944352945
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.1677784244
Short name T527
Test name
Test status
Simulation time 1185197863 ps
CPU time 16.25 seconds
Started Mar 05 01:21:04 PM PST 24
Finished Mar 05 01:21:21 PM PST 24
Peak memory 208188 kb
Host smart-2ec39716-9609-475d-b5c0-bf6f5a48672c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1677784244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.1677784244
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.3857718771
Short name T583
Test name
Test status
Simulation time 737919735 ps
CPU time 5.22 seconds
Started Mar 05 01:20:58 PM PST 24
Finished Mar 05 01:21:04 PM PST 24
Peak memory 207348 kb
Host smart-1361ea0a-8cfd-4a41-8a48-002695df8942
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857718771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.3857718771
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.150958481
Short name T466
Test name
Test status
Simulation time 251894775 ps
CPU time 3.35 seconds
Started Mar 05 01:21:15 PM PST 24
Finished Mar 05 01:21:19 PM PST 24
Peak memory 206376 kb
Host smart-313478c6-5d9b-4587-a9f2-7597d4b52a5c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150958481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.150958481
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.1942971532
Short name T905
Test name
Test status
Simulation time 254354834 ps
CPU time 2.96 seconds
Started Mar 05 01:21:04 PM PST 24
Finished Mar 05 01:21:07 PM PST 24
Peak memory 208564 kb
Host smart-d910a193-9e5d-4e89-8fb0-931ff0742bb7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1942971532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.1942971532
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.3169978367
Short name T890
Test name
Test status
Simulation time 488885267 ps
CPU time 2.71 seconds
Started Mar 05 01:21:27 PM PST 24
Finished Mar 05 01:21:30 PM PST 24
Peak memory 206500 kb
Host smart-fec906f3-2138-4b79-a91a-3670fa7a0429
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169978367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.3169978367
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.4019215015
Short name T824
Test name
Test status
Simulation time 470147041 ps
CPU time 3.82 seconds
Started Mar 05 01:21:15 PM PST 24
Finished Mar 05 01:21:19 PM PST 24
Peak memory 213972 kb
Host smart-d6cd5585-315e-4726-a781-3c537b50a8f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019215015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.4019215015
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.600605273
Short name T431
Test name
Test status
Simulation time 221871016 ps
CPU time 2.88 seconds
Started Mar 05 01:21:03 PM PST 24
Finished Mar 05 01:21:06 PM PST 24
Peak memory 206564 kb
Host smart-249da344-0722-45da-9dcd-737c21f76f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600605273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.600605273
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.2919496309
Short name T180
Test name
Test status
Simulation time 57079456139 ps
CPU time 276.73 seconds
Started Mar 05 01:21:22 PM PST 24
Finished Mar 05 01:26:04 PM PST 24
Peak memory 222388 kb
Host smart-f3966a27-eac3-42f9-aa5b-84798707ef4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919496309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.2919496309
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.3067860483
Short name T737
Test name
Test status
Simulation time 6123631813 ps
CPU time 40.99 seconds
Started Mar 05 01:21:24 PM PST 24
Finished Mar 05 01:22:05 PM PST 24
Peak memory 208872 kb
Host smart-d2edeed8-d929-4055-99b3-9eeed059d3de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067860483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.3067860483
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.3831686663
Short name T157
Test name
Test status
Simulation time 52514355 ps
CPU time 2.41 seconds
Started Mar 05 01:21:04 PM PST 24
Finished Mar 05 01:21:07 PM PST 24
Peak memory 209344 kb
Host smart-35458e2f-87c2-4b56-9c9d-ca5282b3fdf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3831686663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.3831686663
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.3329513915
Short name T776
Test name
Test status
Simulation time 12460267 ps
CPU time 0.76 seconds
Started Mar 05 01:21:28 PM PST 24
Finished Mar 05 01:21:29 PM PST 24
Peak memory 205880 kb
Host smart-c1ae2e1a-9730-48a7-8c00-3fe4f7df2f2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329513915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.3329513915
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.4021341593
Short name T337
Test name
Test status
Simulation time 267352393 ps
CPU time 4.21 seconds
Started Mar 05 01:21:03 PM PST 24
Finished Mar 05 01:21:08 PM PST 24
Peak memory 215120 kb
Host smart-59b0cb26-cf11-4b89-a773-f64179a9c95b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4021341593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.4021341593
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.984989776
Short name T564
Test name
Test status
Simulation time 226028623 ps
CPU time 3.26 seconds
Started Mar 05 01:21:04 PM PST 24
Finished Mar 05 01:21:08 PM PST 24
Peak memory 208040 kb
Host smart-cd3ab1aa-0ca9-4c2c-85f9-b98199d72729
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=984989776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.984989776
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.626308228
Short name T241
Test name
Test status
Simulation time 383575393 ps
CPU time 9.76 seconds
Started Mar 05 01:21:36 PM PST 24
Finished Mar 05 01:21:46 PM PST 24
Peak memory 210088 kb
Host smart-f8a6067e-35b4-4ebc-9e74-5dbfde4b5819
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626308228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.626308228
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.2379833676
Short name T820
Test name
Test status
Simulation time 76795993 ps
CPU time 3.55 seconds
Started Mar 05 01:21:02 PM PST 24
Finished Mar 05 01:21:07 PM PST 24
Peak memory 209220 kb
Host smart-fe41abc3-ce12-46db-a582-15787758c95f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379833676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.2379833676
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.3940536661
Short name T351
Test name
Test status
Simulation time 95842813 ps
CPU time 4.59 seconds
Started Mar 05 01:21:22 PM PST 24
Finished Mar 05 01:21:27 PM PST 24
Peak memory 222256 kb
Host smart-8032d320-d9b2-439b-acd1-9c966f7d6988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940536661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.3940536661
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.828808115
Short name T854
Test name
Test status
Simulation time 109094673 ps
CPU time 2.76 seconds
Started Mar 05 01:21:24 PM PST 24
Finished Mar 05 01:21:27 PM PST 24
Peak memory 206052 kb
Host smart-31988db3-8853-498e-ab23-92c9a3e7e027
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828808115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.828808115
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.1152893547
Short name T842
Test name
Test status
Simulation time 159629165 ps
CPU time 5.47 seconds
Started Mar 05 01:21:25 PM PST 24
Finished Mar 05 01:21:31 PM PST 24
Peak memory 214176 kb
Host smart-23ad254f-b9dd-4116-aca6-ef5a5fdd3494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152893547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.1152893547
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.4239895998
Short name T860
Test name
Test status
Simulation time 877460964 ps
CPU time 9.49 seconds
Started Mar 05 01:21:06 PM PST 24
Finished Mar 05 01:21:16 PM PST 24
Peak memory 208276 kb
Host smart-8eb00eb4-3b9d-4190-8113-70dfdf361b95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4239895998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.4239895998
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.3613170756
Short name T595
Test name
Test status
Simulation time 1753330889 ps
CPU time 22.08 seconds
Started Mar 05 01:21:24 PM PST 24
Finished Mar 05 01:21:46 PM PST 24
Peak memory 208340 kb
Host smart-550e56c1-e6a2-4a00-acd5-23973c292dd0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3613170756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.3613170756
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.3660601737
Short name T620
Test name
Test status
Simulation time 119515255 ps
CPU time 3.7 seconds
Started Mar 05 01:21:07 PM PST 24
Finished Mar 05 01:21:11 PM PST 24
Peak memory 208104 kb
Host smart-45c0b703-74e7-42c7-9490-27ae5e040bca
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660601737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.3660601737
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.3022684259
Short name T711
Test name
Test status
Simulation time 75744612 ps
CPU time 3.63 seconds
Started Mar 05 01:21:23 PM PST 24
Finished Mar 05 01:21:27 PM PST 24
Peak memory 208108 kb
Host smart-89257ffa-8425-4b9c-91d9-9caddaca114a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022684259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.3022684259
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.1605038434
Short name T744
Test name
Test status
Simulation time 372474766 ps
CPU time 4.37 seconds
Started Mar 05 01:21:15 PM PST 24
Finished Mar 05 01:21:20 PM PST 24
Peak memory 215312 kb
Host smart-6be0b9eb-aa02-4598-bf69-c9a21c957b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605038434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.1605038434
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.3713472816
Short name T866
Test name
Test status
Simulation time 22365649 ps
CPU time 1.88 seconds
Started Mar 05 01:21:29 PM PST 24
Finished Mar 05 01:21:32 PM PST 24
Peak memory 206708 kb
Host smart-3840d241-27ef-474c-84a2-278a841ffb6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713472816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.3713472816
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.4191672202
Short name T350
Test name
Test status
Simulation time 1412934317 ps
CPU time 18.37 seconds
Started Mar 05 01:21:19 PM PST 24
Finished Mar 05 01:21:37 PM PST 24
Peak memory 218700 kb
Host smart-8f0782e9-25f1-41bb-b2d0-59c94bb1626c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4191672202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.4191672202
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.3533975147
Short name T117
Test name
Test status
Simulation time 523037433 ps
CPU time 20.93 seconds
Started Mar 05 01:21:29 PM PST 24
Finished Mar 05 01:21:51 PM PST 24
Peak memory 222460 kb
Host smart-b1cae599-5b6c-4c60-91c4-e911761a0b2c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533975147 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all_with_rand_reset.3533975147
Directory /workspace/47.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.4272189917
Short name T652
Test name
Test status
Simulation time 7524225718 ps
CPU time 57.38 seconds
Started Mar 05 01:21:02 PM PST 24
Finished Mar 05 01:22:01 PM PST 24
Peak memory 222128 kb
Host smart-4e847aee-33f1-412b-9340-dd0a6ec51145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272189917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.4272189917
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.1086454984
Short name T377
Test name
Test status
Simulation time 1747039134 ps
CPU time 10.59 seconds
Started Mar 05 01:21:01 PM PST 24
Finished Mar 05 01:21:13 PM PST 24
Peak memory 210640 kb
Host smart-62187373-8789-422e-af92-d7fed586e54d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086454984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.1086454984
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.1110836980
Short name T507
Test name
Test status
Simulation time 46926833 ps
CPU time 0.94 seconds
Started Mar 05 01:21:23 PM PST 24
Finished Mar 05 01:21:24 PM PST 24
Peak memory 205944 kb
Host smart-246e119e-c28d-4a15-a456-8bb9ee915994
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110836980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.1110836980
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.1581745489
Short name T249
Test name
Test status
Simulation time 119243891 ps
CPU time 2.59 seconds
Started Mar 05 01:21:34 PM PST 24
Finished Mar 05 01:21:36 PM PST 24
Peak memory 214652 kb
Host smart-9a4347f0-dd72-455e-9968-c8dd53188616
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1581745489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.1581745489
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.251746857
Short name T338
Test name
Test status
Simulation time 621183224 ps
CPU time 2.79 seconds
Started Mar 05 01:21:46 PM PST 24
Finished Mar 05 01:21:49 PM PST 24
Peak memory 206544 kb
Host smart-0f7d6374-e3f4-4f7f-8f4a-a38bc6e9f379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251746857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.251746857
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.4227283155
Short name T92
Test name
Test status
Simulation time 68220277 ps
CPU time 3.55 seconds
Started Mar 05 01:21:02 PM PST 24
Finished Mar 05 01:21:07 PM PST 24
Peak memory 211232 kb
Host smart-ea9a9abc-306c-48fb-bc85-aec3b243d51e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227283155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.4227283155
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.3257151985
Short name T611
Test name
Test status
Simulation time 223938213 ps
CPU time 2.2 seconds
Started Mar 05 01:21:25 PM PST 24
Finished Mar 05 01:21:27 PM PST 24
Peak memory 205932 kb
Host smart-28db91d2-0a4f-4444-8d8d-d0c9fbd8a172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257151985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.3257151985
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.1602039303
Short name T657
Test name
Test status
Simulation time 204829698 ps
CPU time 4.38 seconds
Started Mar 05 01:21:12 PM PST 24
Finished Mar 05 01:21:17 PM PST 24
Peak memory 209696 kb
Host smart-99c6192b-39ba-40a1-ac0e-753605639e68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602039303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.1602039303
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.418873056
Short name T636
Test name
Test status
Simulation time 169844849 ps
CPU time 4.56 seconds
Started Mar 05 01:21:30 PM PST 24
Finished Mar 05 01:21:35 PM PST 24
Peak memory 206412 kb
Host smart-db248cd6-062e-42ef-9be7-91caf418999b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418873056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.418873056
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.562990693
Short name T517
Test name
Test status
Simulation time 140934010 ps
CPU time 2.6 seconds
Started Mar 05 01:21:05 PM PST 24
Finished Mar 05 01:21:08 PM PST 24
Peak memory 206976 kb
Host smart-08ad36c2-5863-4d7c-bc30-192cf1ba06f3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=562990693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.562990693
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.504539738
Short name T832
Test name
Test status
Simulation time 172492042 ps
CPU time 3.02 seconds
Started Mar 05 01:21:04 PM PST 24
Finished Mar 05 01:21:07 PM PST 24
Peak memory 207916 kb
Host smart-ea4c8996-9a0a-432b-b00e-e809b09251e1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504539738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.504539738
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.506525470
Short name T879
Test name
Test status
Simulation time 419657597 ps
CPU time 3.54 seconds
Started Mar 05 01:21:18 PM PST 24
Finished Mar 05 01:21:22 PM PST 24
Peak memory 208652 kb
Host smart-6587173b-ed08-436a-8de4-01a700301a32
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506525470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.506525470
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.255436379
Short name T494
Test name
Test status
Simulation time 58524143 ps
CPU time 2.6 seconds
Started Mar 05 01:21:17 PM PST 24
Finished Mar 05 01:21:20 PM PST 24
Peak memory 209624 kb
Host smart-9d7bedc9-6075-4ac6-8c48-46b5596c4687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255436379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.255436379
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.305017137
Short name T481
Test name
Test status
Simulation time 676103226 ps
CPU time 3.3 seconds
Started Mar 05 01:21:02 PM PST 24
Finished Mar 05 01:21:06 PM PST 24
Peak memory 208096 kb
Host smart-c83351e4-11e8-43c2-b292-a231ed77eca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305017137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.305017137
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.556669938
Short name T328
Test name
Test status
Simulation time 995058300 ps
CPU time 11.37 seconds
Started Mar 05 01:21:07 PM PST 24
Finished Mar 05 01:21:18 PM PST 24
Peak memory 215340 kb
Host smart-2ba95d12-3f03-4b2c-9631-240128f6cb4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556669938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.556669938
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.2066864558
Short name T723
Test name
Test status
Simulation time 12980703991 ps
CPU time 51.72 seconds
Started Mar 05 01:21:10 PM PST 24
Finished Mar 05 01:22:02 PM PST 24
Peak memory 208312 kb
Host smart-e98496aa-26ee-4821-85bd-37fc777c7fb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2066864558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.2066864558
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.3469061285
Short name T176
Test name
Test status
Simulation time 109655538 ps
CPU time 2.64 seconds
Started Mar 05 01:21:02 PM PST 24
Finished Mar 05 01:21:06 PM PST 24
Peak memory 209412 kb
Host smart-41e1fef0-33ef-4db1-89bf-bf4e5c5b6f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3469061285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.3469061285
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.4236726347
Short name T491
Test name
Test status
Simulation time 35629738 ps
CPU time 0.75 seconds
Started Mar 05 01:21:24 PM PST 24
Finished Mar 05 01:21:25 PM PST 24
Peak memory 205836 kb
Host smart-6a0934fb-742f-4236-84eb-cce516e850b8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236726347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.4236726347
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.2260676879
Short name T34
Test name
Test status
Simulation time 171046592 ps
CPU time 2.87 seconds
Started Mar 05 01:21:20 PM PST 24
Finished Mar 05 01:21:23 PM PST 24
Peak memory 208184 kb
Host smart-d4aa80bf-df8f-4174-aeec-728f1699f868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260676879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.2260676879
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.4009023518
Short name T791
Test name
Test status
Simulation time 70332069 ps
CPU time 2.72 seconds
Started Mar 05 01:21:05 PM PST 24
Finished Mar 05 01:21:08 PM PST 24
Peak memory 208892 kb
Host smart-8499510d-eafd-452c-87a6-b4675611b55f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009023518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.4009023518
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.617599614
Short name T373
Test name
Test status
Simulation time 103953281 ps
CPU time 4.16 seconds
Started Mar 05 01:21:16 PM PST 24
Finished Mar 05 01:21:20 PM PST 24
Peak memory 209248 kb
Host smart-834a8627-03e1-4f42-86dd-064ffa7188ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617599614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.617599614
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.905764284
Short name T38
Test name
Test status
Simulation time 59163124 ps
CPU time 2.94 seconds
Started Mar 05 01:21:23 PM PST 24
Finished Mar 05 01:21:26 PM PST 24
Peak memory 211008 kb
Host smart-1409e1d4-143d-4366-98c2-f6e00d7e28e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905764284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.905764284
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.1510452011
Short name T606
Test name
Test status
Simulation time 171071832 ps
CPU time 5.18 seconds
Started Mar 05 01:21:18 PM PST 24
Finished Mar 05 01:21:23 PM PST 24
Peak memory 208036 kb
Host smart-c063c389-5455-4ebd-a05c-9c6c49684035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510452011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.1510452011
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.1388445088
Short name T808
Test name
Test status
Simulation time 33933021 ps
CPU time 2.43 seconds
Started Mar 05 01:21:06 PM PST 24
Finished Mar 05 01:21:09 PM PST 24
Peak memory 207728 kb
Host smart-17ed2bec-806c-4cdc-ab6b-42ac903fd7cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388445088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.1388445088
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.2528096663
Short name T558
Test name
Test status
Simulation time 540839666 ps
CPU time 7.1 seconds
Started Mar 05 01:21:06 PM PST 24
Finished Mar 05 01:21:13 PM PST 24
Peak memory 207572 kb
Host smart-9481f7c8-0e48-4f78-a175-e016255a3699
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528096663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.2528096663
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.4052221983
Short name T473
Test name
Test status
Simulation time 558347879 ps
CPU time 5.84 seconds
Started Mar 05 01:21:04 PM PST 24
Finished Mar 05 01:21:10 PM PST 24
Peak memory 206512 kb
Host smart-23a3d1dd-37c3-40a3-b008-2297d558633a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052221983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.4052221983
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.2708218235
Short name T567
Test name
Test status
Simulation time 126930539 ps
CPU time 3.36 seconds
Started Mar 05 01:21:23 PM PST 24
Finished Mar 05 01:21:27 PM PST 24
Peak memory 206356 kb
Host smart-da73cb31-28c8-428f-8ddc-85c590be9b33
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708218235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.2708218235
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.3428359491
Short name T315
Test name
Test status
Simulation time 99049743 ps
CPU time 2.88 seconds
Started Mar 05 01:21:05 PM PST 24
Finished Mar 05 01:21:08 PM PST 24
Peak memory 206524 kb
Host smart-94818984-15b0-439c-a03a-12092be42086
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3428359491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.3428359491
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.678636368
Short name T452
Test name
Test status
Simulation time 549232589 ps
CPU time 3.02 seconds
Started Mar 05 01:21:05 PM PST 24
Finished Mar 05 01:21:09 PM PST 24
Peak memory 208300 kb
Host smart-32e13919-9c33-4304-8696-aba5c1c4d8e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678636368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.678636368
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.2102497796
Short name T622
Test name
Test status
Simulation time 61224281 ps
CPU time 2.85 seconds
Started Mar 05 01:21:26 PM PST 24
Finished Mar 05 01:21:29 PM PST 24
Peak memory 207664 kb
Host smart-d9b2da31-4855-4e58-ba61-17eb4e834c3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2102497796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.2102497796
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.2948219964
Short name T859
Test name
Test status
Simulation time 644660132 ps
CPU time 30.73 seconds
Started Mar 05 01:21:21 PM PST 24
Finished Mar 05 01:21:52 PM PST 24
Peak memory 217420 kb
Host smart-3144fab8-7d40-4648-8fb7-3e849c19f54c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2948219964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.2948219964
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.2325731822
Short name T158
Test name
Test status
Simulation time 93320183 ps
CPU time 2.64 seconds
Started Mar 05 01:21:35 PM PST 24
Finished Mar 05 01:21:38 PM PST 24
Peak memory 209688 kb
Host smart-d01543e4-5d6e-4587-85a7-a6407bf12e58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325731822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.2325731822
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.3310739260
Short name T513
Test name
Test status
Simulation time 31051916 ps
CPU time 0.77 seconds
Started Mar 05 01:19:20 PM PST 24
Finished Mar 05 01:19:21 PM PST 24
Peak memory 205876 kb
Host smart-cfda5ad9-216f-4d61-bf69-9f568484b5fa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310739260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.3310739260
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.2122957953
Short name T721
Test name
Test status
Simulation time 59270605 ps
CPU time 2.44 seconds
Started Mar 05 01:19:16 PM PST 24
Finished Mar 05 01:19:19 PM PST 24
Peak memory 210380 kb
Host smart-8f03c052-6f9c-4163-86cf-28ce6e3ff199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122957953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.2122957953
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.2892366932
Short name T525
Test name
Test status
Simulation time 94553616 ps
CPU time 2.5 seconds
Started Mar 05 01:19:33 PM PST 24
Finished Mar 05 01:19:38 PM PST 24
Peak memory 208604 kb
Host smart-6d288a70-3c10-431b-a357-b18d217dc6b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892366932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.2892366932
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.201659042
Short name T664
Test name
Test status
Simulation time 266664231 ps
CPU time 4.64 seconds
Started Mar 05 01:19:29 PM PST 24
Finished Mar 05 01:19:35 PM PST 24
Peak memory 208464 kb
Host smart-3f3c1170-c574-4edc-b098-8798ce2d09ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201659042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.201659042
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.276493313
Short name T297
Test name
Test status
Simulation time 12360615049 ps
CPU time 120.75 seconds
Started Mar 05 01:19:16 PM PST 24
Finished Mar 05 01:21:17 PM PST 24
Peak memory 222316 kb
Host smart-73638378-45b1-4375-8ac0-697901034353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276493313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.276493313
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.3816831867
Short name T649
Test name
Test status
Simulation time 112090212 ps
CPU time 4.92 seconds
Started Mar 05 01:19:29 PM PST 24
Finished Mar 05 01:19:35 PM PST 24
Peak memory 215660 kb
Host smart-105436da-3746-4267-b800-4e1789b21822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816831867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.3816831867
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.4120868391
Short name T347
Test name
Test status
Simulation time 151148336 ps
CPU time 2.75 seconds
Started Mar 05 01:19:15 PM PST 24
Finished Mar 05 01:19:18 PM PST 24
Peak memory 207164 kb
Host smart-09cf93a0-ecb9-4473-92fe-7a03840a64b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120868391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.4120868391
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.313197703
Short name T446
Test name
Test status
Simulation time 401964353 ps
CPU time 3.45 seconds
Started Mar 05 01:19:27 PM PST 24
Finished Mar 05 01:19:30 PM PST 24
Peak memory 206256 kb
Host smart-c292d897-005a-41b3-8e02-4e7418bd3e05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313197703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.313197703
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.2863616981
Short name T833
Test name
Test status
Simulation time 167717508 ps
CPU time 2.36 seconds
Started Mar 05 01:19:08 PM PST 24
Finished Mar 05 01:19:11 PM PST 24
Peak memory 206284 kb
Host smart-203d8d8a-7fa4-4aa9-9363-167f694175a9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863616981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.2863616981
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.3926399357
Short name T542
Test name
Test status
Simulation time 210018336 ps
CPU time 4.41 seconds
Started Mar 05 01:19:11 PM PST 24
Finished Mar 05 01:19:16 PM PST 24
Peak memory 208492 kb
Host smart-5a7d3e0f-f783-4a55-aec1-63d119ac7639
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3926399357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.3926399357
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.2055446540
Short name T557
Test name
Test status
Simulation time 160970314 ps
CPU time 2.74 seconds
Started Mar 05 01:19:09 PM PST 24
Finished Mar 05 01:19:12 PM PST 24
Peak memory 208512 kb
Host smart-7d7b1306-f221-4d65-81d4-dbe3a8f8dfa1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055446540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.2055446540
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.3683691676
Short name T614
Test name
Test status
Simulation time 167658855 ps
CPU time 2.78 seconds
Started Mar 05 01:19:18 PM PST 24
Finished Mar 05 01:19:21 PM PST 24
Peak memory 207280 kb
Host smart-c51f54b7-bd13-4711-992e-7b0475ef7952
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683691676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.3683691676
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.2689199713
Short name T193
Test name
Test status
Simulation time 105181194 ps
CPU time 4.63 seconds
Started Mar 05 01:19:25 PM PST 24
Finished Mar 05 01:19:29 PM PST 24
Peak memory 208020 kb
Host smart-a7cc3478-99a3-4b57-bf04-e8c34e251feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689199713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.2689199713
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all_with_rand_reset.2911409832
Short name T724
Test name
Test status
Simulation time 293198882 ps
CPU time 14.8 seconds
Started Mar 05 01:19:24 PM PST 24
Finished Mar 05 01:19:40 PM PST 24
Peak memory 222568 kb
Host smart-66f9fddd-75ee-42da-baf9-54afa312e12c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911409832 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all_with_rand_reset.2911409832
Directory /workspace/5.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.166904367
Short name T63
Test name
Test status
Simulation time 104751344 ps
CPU time 2.86 seconds
Started Mar 05 01:19:11 PM PST 24
Finished Mar 05 01:19:14 PM PST 24
Peak memory 209800 kb
Host smart-ac4bd32a-7235-4539-b20b-885e59188b92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166904367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.166904367
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.2235149795
Short name T440
Test name
Test status
Simulation time 76544359 ps
CPU time 0.84 seconds
Started Mar 05 01:19:41 PM PST 24
Finished Mar 05 01:19:42 PM PST 24
Peak memory 205812 kb
Host smart-d08ec47d-8218-4400-afd8-41398eeb13a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2235149795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.2235149795
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.881291335
Short name T734
Test name
Test status
Simulation time 224697286 ps
CPU time 3.1 seconds
Started Mar 05 01:19:16 PM PST 24
Finished Mar 05 01:19:21 PM PST 24
Peak memory 207296 kb
Host smart-ed5b4688-18b8-4f1f-a2e7-ad21131a27f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881291335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.881291335
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.951392925
Short name T290
Test name
Test status
Simulation time 1095135609 ps
CPU time 3.97 seconds
Started Mar 05 01:19:26 PM PST 24
Finished Mar 05 01:19:30 PM PST 24
Peak memory 210048 kb
Host smart-230cc26b-8b25-4f3f-8f8b-0cea43ae2303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951392925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.951392925
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.2424142014
Short name T198
Test name
Test status
Simulation time 238134776 ps
CPU time 5.76 seconds
Started Mar 05 01:19:23 PM PST 24
Finished Mar 05 01:19:29 PM PST 24
Peak memory 211480 kb
Host smart-766c8ed8-1188-4311-b1cb-303bfbe5609b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424142014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.2424142014
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.1676911524
Short name T207
Test name
Test status
Simulation time 196867423 ps
CPU time 2.46 seconds
Started Mar 05 01:19:16 PM PST 24
Finished Mar 05 01:19:20 PM PST 24
Peak memory 215696 kb
Host smart-42bc6970-f0ed-4ded-a4fc-c2f8b69935e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676911524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.1676911524
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.829366610
Short name T456
Test name
Test status
Simulation time 145281851 ps
CPU time 5.77 seconds
Started Mar 05 01:19:15 PM PST 24
Finished Mar 05 01:19:21 PM PST 24
Peak memory 214212 kb
Host smart-e4540d97-6c2c-4f16-9675-a8e576096429
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829366610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.829366610
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.975539603
Short name T593
Test name
Test status
Simulation time 292042376 ps
CPU time 3.28 seconds
Started Mar 05 01:19:14 PM PST 24
Finished Mar 05 01:19:18 PM PST 24
Peak memory 207980 kb
Host smart-50e4b474-46bb-4218-946f-12df698e5890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975539603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.975539603
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.1808310910
Short name T340
Test name
Test status
Simulation time 136240495 ps
CPU time 4.48 seconds
Started Mar 05 01:19:26 PM PST 24
Finished Mar 05 01:19:30 PM PST 24
Peak memory 207668 kb
Host smart-99fe3b4d-35e9-44a3-951b-4c5bfac96e49
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1808310910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.1808310910
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.1114442974
Short name T681
Test name
Test status
Simulation time 174053598 ps
CPU time 2.93 seconds
Started Mar 05 01:19:36 PM PST 24
Finished Mar 05 01:19:40 PM PST 24
Peak memory 206472 kb
Host smart-ba84c77e-aad3-4d43-bfa3-5783ac96c37c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114442974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.1114442974
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.197258655
Short name T871
Test name
Test status
Simulation time 131967537 ps
CPU time 4.27 seconds
Started Mar 05 01:19:16 PM PST 24
Finished Mar 05 01:19:22 PM PST 24
Peak memory 207884 kb
Host smart-b9062446-a1ed-4bef-95f6-c91fa77a0824
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197258655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.197258655
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.3217235439
Short name T774
Test name
Test status
Simulation time 146107385 ps
CPU time 2.24 seconds
Started Mar 05 01:19:14 PM PST 24
Finished Mar 05 01:19:17 PM PST 24
Peak memory 207436 kb
Host smart-aa325c72-c3b3-4fe6-b43a-6dd21ed8c644
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217235439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.3217235439
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.6273856
Short name T615
Test name
Test status
Simulation time 6848410608 ps
CPU time 61.59 seconds
Started Mar 05 01:19:15 PM PST 24
Finished Mar 05 01:20:17 PM PST 24
Peak memory 207508 kb
Host smart-20af9bf8-0516-49e3-910b-8471e2fa5dd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=6273856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.6273856
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.2901308444
Short name T361
Test name
Test status
Simulation time 3791421606 ps
CPU time 13.41 seconds
Started Mar 05 01:19:17 PM PST 24
Finished Mar 05 01:19:32 PM PST 24
Peak memory 218316 kb
Host smart-648c5155-a626-4841-bc9d-b201a40634a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2901308444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.2901308444
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.4169744597
Short name T119
Test name
Test status
Simulation time 56694908 ps
CPU time 1.6 seconds
Started Mar 05 01:19:24 PM PST 24
Finished Mar 05 01:19:26 PM PST 24
Peak memory 209348 kb
Host smart-3bba4dfe-a706-4ad3-be95-d65ebf287632
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4169744597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.4169744597
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.2337003385
Short name T810
Test name
Test status
Simulation time 59090040 ps
CPU time 0.88 seconds
Started Mar 05 01:19:20 PM PST 24
Finished Mar 05 01:19:21 PM PST 24
Peak memory 205940 kb
Host smart-b2325b31-0b1d-43ec-94f7-c5dd852b4e29
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337003385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.2337003385
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.3010210654
Short name T672
Test name
Test status
Simulation time 317937097 ps
CPU time 4.63 seconds
Started Mar 05 01:19:30 PM PST 24
Finished Mar 05 01:19:35 PM PST 24
Peak memory 215512 kb
Host smart-8fbc84f5-a4fd-4fc1-a9e8-824a98008748
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3010210654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.3010210654
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.1035452708
Short name T648
Test name
Test status
Simulation time 160358199 ps
CPU time 2.65 seconds
Started Mar 05 01:19:21 PM PST 24
Finished Mar 05 01:19:24 PM PST 24
Peak memory 209412 kb
Host smart-a7339801-892d-4113-a800-fedbda4f71fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035452708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.1035452708
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.2758254841
Short name T889
Test name
Test status
Simulation time 450001263 ps
CPU time 5.09 seconds
Started Mar 05 01:19:27 PM PST 24
Finished Mar 05 01:19:32 PM PST 24
Peak memory 209604 kb
Host smart-22521d19-96f7-4e14-b517-55c504b0f0da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758254841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.2758254841
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.928459929
Short name T855
Test name
Test status
Simulation time 622120043 ps
CPU time 6.82 seconds
Started Mar 05 01:19:30 PM PST 24
Finished Mar 05 01:19:38 PM PST 24
Peak memory 214112 kb
Host smart-dec09f35-731e-481d-b05b-d32492d885d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928459929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.928459929
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.4219348326
Short name T608
Test name
Test status
Simulation time 328288450 ps
CPU time 3.98 seconds
Started Mar 05 01:19:25 PM PST 24
Finished Mar 05 01:19:29 PM PST 24
Peak memory 209972 kb
Host smart-39a0881c-f381-4f5e-af3b-6a46cf88f0d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219348326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.4219348326
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.2594530798
Short name T708
Test name
Test status
Simulation time 127976600 ps
CPU time 4.34 seconds
Started Mar 05 01:19:21 PM PST 24
Finished Mar 05 01:19:26 PM PST 24
Peak memory 207112 kb
Host smart-9c41ca6a-4649-4589-8589-be77e3920ab1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2594530798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.2594530798
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.1403471531
Short name T674
Test name
Test status
Simulation time 152999763 ps
CPU time 3.16 seconds
Started Mar 05 01:19:37 PM PST 24
Finished Mar 05 01:19:41 PM PST 24
Peak memory 208544 kb
Host smart-2b4387d9-9d58-4511-aab5-c75d99c15a28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403471531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.1403471531
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.3806853612
Short name T477
Test name
Test status
Simulation time 416232565 ps
CPU time 3.22 seconds
Started Mar 05 01:19:27 PM PST 24
Finished Mar 05 01:19:30 PM PST 24
Peak memory 208236 kb
Host smart-7f639002-3e67-44d1-8402-5286373d663d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806853612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.3806853612
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.2348343508
Short name T634
Test name
Test status
Simulation time 85638759 ps
CPU time 1.84 seconds
Started Mar 05 01:19:38 PM PST 24
Finished Mar 05 01:19:40 PM PST 24
Peak memory 206460 kb
Host smart-bdbbbfc6-b695-4410-a978-fb7a17db4de7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2348343508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.2348343508
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.2715917996
Short name T677
Test name
Test status
Simulation time 332275369 ps
CPU time 5.71 seconds
Started Mar 05 01:19:21 PM PST 24
Finished Mar 05 01:19:27 PM PST 24
Peak memory 206484 kb
Host smart-e88a2ac9-f978-4dfe-9830-0dbf5bd163c0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2715917996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.2715917996
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.2687375204
Short name T828
Test name
Test status
Simulation time 57651596 ps
CPU time 2.1 seconds
Started Mar 05 01:19:36 PM PST 24
Finished Mar 05 01:19:39 PM PST 24
Peak memory 207516 kb
Host smart-6e1aebf2-890f-4d85-9162-80439e21745d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687375204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.2687375204
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.454051646
Short name T83
Test name
Test status
Simulation time 1093461731 ps
CPU time 3.22 seconds
Started Mar 05 01:19:35 PM PST 24
Finished Mar 05 01:19:39 PM PST 24
Peak memory 206320 kb
Host smart-887ec42f-10c1-4a34-bb31-ee80f43feee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454051646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.454051646
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.395201698
Short name T206
Test name
Test status
Simulation time 22557752265 ps
CPU time 274.19 seconds
Started Mar 05 01:19:31 PM PST 24
Finished Mar 05 01:24:06 PM PST 24
Peak memory 222452 kb
Host smart-de2d04f1-5a09-4139-a071-b8c6a151d543
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=395201698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.395201698
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.371272606
Short name T186
Test name
Test status
Simulation time 284973972 ps
CPU time 6.86 seconds
Started Mar 05 01:19:37 PM PST 24
Finished Mar 05 01:19:44 PM PST 24
Peak memory 218284 kb
Host smart-25d64080-ee0c-4ccf-8cbe-c42e6c00fe31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371272606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.371272606
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.2979107496
Short name T894
Test name
Test status
Simulation time 161356571 ps
CPU time 1.8 seconds
Started Mar 05 01:19:31 PM PST 24
Finished Mar 05 01:19:35 PM PST 24
Peak memory 209220 kb
Host smart-7baa423b-7e78-4542-a545-599b6f295796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2979107496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.2979107496
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.1884749767
Short name T742
Test name
Test status
Simulation time 28551803 ps
CPU time 0.95 seconds
Started Mar 05 01:19:36 PM PST 24
Finished Mar 05 01:19:38 PM PST 24
Peak memory 205756 kb
Host smart-eea1d755-29a5-48ad-9827-369f6a1db8c9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884749767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.1884749767
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.694778764
Short name T426
Test name
Test status
Simulation time 176902355 ps
CPU time 9.62 seconds
Started Mar 05 01:19:39 PM PST 24
Finished Mar 05 01:19:49 PM PST 24
Peak memory 215576 kb
Host smart-60a4d67b-a0de-4284-90a1-540ffb723abe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=694778764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.694778764
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.2619633077
Short name T201
Test name
Test status
Simulation time 1183524797 ps
CPU time 7.29 seconds
Started Mar 05 01:19:38 PM PST 24
Finished Mar 05 01:19:46 PM PST 24
Peak memory 218140 kb
Host smart-e8c60cf7-4e1e-40c5-b47b-4c8997092231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619633077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.2619633077
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.719222774
Short name T743
Test name
Test status
Simulation time 55530306 ps
CPU time 1.5 seconds
Started Mar 05 01:19:23 PM PST 24
Finished Mar 05 01:19:25 PM PST 24
Peak memory 207452 kb
Host smart-534928c6-76d1-4c66-af9b-18be8887d326
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719222774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.719222774
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.31158548
Short name T779
Test name
Test status
Simulation time 2944434298 ps
CPU time 16.92 seconds
Started Mar 05 01:19:15 PM PST 24
Finished Mar 05 01:19:32 PM PST 24
Peak memory 222116 kb
Host smart-ebbe68d1-5b88-4d2c-b06d-5e96cc79be3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=31158548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.31158548
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.1635053817
Short name T304
Test name
Test status
Simulation time 58990227 ps
CPU time 3.78 seconds
Started Mar 05 01:19:43 PM PST 24
Finished Mar 05 01:19:47 PM PST 24
Peak memory 214116 kb
Host smart-d057f9e8-c8be-4767-868c-769959a04d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635053817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.1635053817
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.531815120
Short name T203
Test name
Test status
Simulation time 132880883 ps
CPU time 2.74 seconds
Started Mar 05 01:19:53 PM PST 24
Finished Mar 05 01:19:56 PM PST 24
Peak memory 216232 kb
Host smart-950fc634-4cf9-483b-9a82-142708b32f05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531815120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.531815120
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.1858366866
Short name T400
Test name
Test status
Simulation time 330746542 ps
CPU time 5.8 seconds
Started Mar 05 01:19:32 PM PST 24
Finished Mar 05 01:19:40 PM PST 24
Peak memory 207204 kb
Host smart-e725043e-b3e5-4507-8a64-ba4c0b98882e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858366866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.1858366866
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.4181365451
Short name T451
Test name
Test status
Simulation time 113758061 ps
CPU time 2.27 seconds
Started Mar 05 01:19:27 PM PST 24
Finished Mar 05 01:19:29 PM PST 24
Peak memory 206328 kb
Host smart-69ba00e3-fa76-421a-8119-63e48ae300f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4181365451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.4181365451
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.866127217
Short name T816
Test name
Test status
Simulation time 291769689 ps
CPU time 4.79 seconds
Started Mar 05 01:19:23 PM PST 24
Finished Mar 05 01:19:28 PM PST 24
Peak memory 207992 kb
Host smart-d01a2107-daa8-4619-b67a-09c8e232fa5b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866127217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.866127217
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.85592516
Short name T510
Test name
Test status
Simulation time 276638529 ps
CPU time 3.3 seconds
Started Mar 05 01:19:28 PM PST 24
Finished Mar 05 01:19:32 PM PST 24
Peak memory 208040 kb
Host smart-cf32ff74-8906-4d84-86b5-e4b21dba3c93
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85592516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.85592516
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.3748702325
Short name T642
Test name
Test status
Simulation time 36125528 ps
CPU time 2.41 seconds
Started Mar 05 01:19:47 PM PST 24
Finished Mar 05 01:19:50 PM PST 24
Peak memory 206320 kb
Host smart-3d5d3483-4696-45cb-a2c7-8264f7b2a365
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748702325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.3748702325
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.758178302
Short name T14
Test name
Test status
Simulation time 72334180 ps
CPU time 2.32 seconds
Started Mar 05 01:19:42 PM PST 24
Finished Mar 05 01:19:44 PM PST 24
Peak memory 208920 kb
Host smart-04083717-6db6-4b1b-a0f0-7eda96822b4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758178302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.758178302
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.367574216
Short name T829
Test name
Test status
Simulation time 145400253 ps
CPU time 4.21 seconds
Started Mar 05 01:19:42 PM PST 24
Finished Mar 05 01:19:46 PM PST 24
Peak memory 206380 kb
Host smart-613f92cb-bbdd-42ba-9660-6390b8859737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367574216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.367574216
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.1771428788
Short name T62
Test name
Test status
Simulation time 502729051 ps
CPU time 20.3 seconds
Started Mar 05 01:19:36 PM PST 24
Finished Mar 05 01:19:57 PM PST 24
Peak memory 216880 kb
Host smart-a380df03-45f9-4548-8a56-5ee19ac2816f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1771428788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.1771428788
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.1386214684
Short name T26
Test name
Test status
Simulation time 1420452988 ps
CPU time 31.64 seconds
Started Mar 05 01:19:47 PM PST 24
Finished Mar 05 01:20:19 PM PST 24
Peak memory 207576 kb
Host smart-c898ff4e-79ec-4612-aaf6-ba53adc6fff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386214684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.1386214684
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.4035309621
Short name T381
Test name
Test status
Simulation time 26843915 ps
CPU time 1.93 seconds
Started Mar 05 01:19:40 PM PST 24
Finished Mar 05 01:19:42 PM PST 24
Peak memory 209792 kb
Host smart-45dd9294-4002-4df7-a659-c3c48a43063c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4035309621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.4035309621
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.826448737
Short name T485
Test name
Test status
Simulation time 102218400 ps
CPU time 0.73 seconds
Started Mar 05 01:19:38 PM PST 24
Finished Mar 05 01:19:39 PM PST 24
Peak memory 205828 kb
Host smart-56813146-704c-4c1b-9d98-a635f30bc4b0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826448737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.826448737
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.2575075558
Short name T909
Test name
Test status
Simulation time 76742986 ps
CPU time 3.02 seconds
Started Mar 05 01:19:41 PM PST 24
Finished Mar 05 01:19:45 PM PST 24
Peak memory 214996 kb
Host smart-d821c8bf-a1d6-4f3e-a462-bc015ae3011e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2575075558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.2575075558
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.1273588679
Short name T29
Test name
Test status
Simulation time 593818496 ps
CPU time 4.63 seconds
Started Mar 05 01:19:39 PM PST 24
Finished Mar 05 01:19:44 PM PST 24
Peak memory 207872 kb
Host smart-09fdd483-48e1-4593-9319-4114765ef037
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273588679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.1273588679
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.3003318444
Short name T907
Test name
Test status
Simulation time 75994975 ps
CPU time 2.11 seconds
Started Mar 05 01:19:46 PM PST 24
Finished Mar 05 01:19:48 PM PST 24
Peak memory 208344 kb
Host smart-58e03252-03b3-46fe-8699-797f8b1249df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003318444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.3003318444
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.1963562706
Short name T411
Test name
Test status
Simulation time 592012568 ps
CPU time 18.89 seconds
Started Mar 05 01:19:41 PM PST 24
Finished Mar 05 01:20:00 PM PST 24
Peak memory 214140 kb
Host smart-885c1f9a-9b0d-4069-810e-4b787bcadab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963562706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.1963562706
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.661921139
Short name T877
Test name
Test status
Simulation time 753513356 ps
CPU time 5.18 seconds
Started Mar 05 01:19:33 PM PST 24
Finished Mar 05 01:19:40 PM PST 24
Peak memory 210088 kb
Host smart-01832089-73a6-4e49-a92a-11ee61060edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661921139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.661921139
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.709220240
Short name T68
Test name
Test status
Simulation time 635316115 ps
CPU time 3.55 seconds
Started Mar 05 01:19:44 PM PST 24
Finished Mar 05 01:19:48 PM PST 24
Peak memory 208684 kb
Host smart-893761f1-64ca-466a-8c71-d42256c5a740
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709220240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.709220240
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.1795962843
Short name T898
Test name
Test status
Simulation time 121669570 ps
CPU time 2.68 seconds
Started Mar 05 01:19:53 PM PST 24
Finished Mar 05 01:19:56 PM PST 24
Peak memory 208392 kb
Host smart-47e055e7-f912-4650-be70-399cab7d72b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1795962843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.1795962843
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.555692285
Short name T653
Test name
Test status
Simulation time 55676047 ps
CPU time 2.36 seconds
Started Mar 05 01:19:43 PM PST 24
Finished Mar 05 01:19:45 PM PST 24
Peak memory 208252 kb
Host smart-7dd94082-9e55-4871-8a67-7022507114a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555692285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.555692285
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.3969852812
Short name T465
Test name
Test status
Simulation time 44692758 ps
CPU time 1.84 seconds
Started Mar 05 01:19:46 PM PST 24
Finished Mar 05 01:19:48 PM PST 24
Peak memory 206136 kb
Host smart-3a03b03b-852e-48cd-b5f5-0a493ad69c1b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3969852812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.3969852812
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.1084913888
Short name T305
Test name
Test status
Simulation time 125282929 ps
CPU time 3.94 seconds
Started Mar 05 01:19:37 PM PST 24
Finished Mar 05 01:19:41 PM PST 24
Peak memory 206716 kb
Host smart-1d7bf7ce-693f-4a10-b3ea-494966942b7b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1084913888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.1084913888
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.1726156329
Short name T99
Test name
Test status
Simulation time 70593120 ps
CPU time 2.62 seconds
Started Mar 05 01:19:34 PM PST 24
Finished Mar 05 01:19:38 PM PST 24
Peak memory 207028 kb
Host smart-7fa39cd9-e871-4387-a3a4-6a3d2e6c258f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726156329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.1726156329
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.405531545
Short name T746
Test name
Test status
Simulation time 166235896 ps
CPU time 3.53 seconds
Started Mar 05 01:19:41 PM PST 24
Finished Mar 05 01:19:45 PM PST 24
Peak memory 218300 kb
Host smart-2c332397-ce7f-4e58-947e-65afa5af7f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405531545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.405531545
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.3937388232
Short name T710
Test name
Test status
Simulation time 184939416 ps
CPU time 5.5 seconds
Started Mar 05 01:19:40 PM PST 24
Finished Mar 05 01:19:46 PM PST 24
Peak memory 206348 kb
Host smart-4933f56d-39df-42aa-bdf2-acadb9c556c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937388232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.3937388232
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.1573890353
Short name T177
Test name
Test status
Simulation time 829031742 ps
CPU time 16.01 seconds
Started Mar 05 01:19:37 PM PST 24
Finished Mar 05 01:19:54 PM PST 24
Peak memory 218268 kb
Host smart-5d8cd463-1f8b-4f06-8c9c-2ec3e6259617
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1573890353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.1573890353
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.4075189299
Short name T303
Test name
Test status
Simulation time 377225614 ps
CPU time 10.42 seconds
Started Mar 05 01:19:36 PM PST 24
Finished Mar 05 01:19:48 PM PST 24
Peak memory 209624 kb
Host smart-cae63adf-b4ed-478f-857d-8bcca358c3c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075189299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.4075189299
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.4218399684
Short name T474
Test name
Test status
Simulation time 58527714 ps
CPU time 2 seconds
Started Mar 05 01:19:39 PM PST 24
Finished Mar 05 01:19:42 PM PST 24
Peak memory 209448 kb
Host smart-967649da-75eb-4647-8078-dcd078a43cb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4218399684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.4218399684
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%