Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
81.36	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	51	0	51	100.00
Crosses	330	71	259	78.48

Variables for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
aes_sl_avail	2	0	2	100.00	100	1	1	2
aes_sl_avail_cp	2	0	2	100.00	100	1	1	2
kmac_sl_avail	2	0	2	100.00	100	1	1	2
kmac_sl_avail_cp	2	0	2	100.00	100	1	1	2
op	5	0	5	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
otbn_sl_avail	2	0	2	100.00	100	1	1	2
otbn_sl_avail_cp	2	0	2	100.00	100	1	1	2
regwen_cp	2	0	2	100.00	100	1	1	2
sideload_clear	8	0	8	100.00	100	1	1	8
sideload_clear_cp	5	0	5	100.00	100	1	1	0
state	7	0	7	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sideload_clear_x_state_op_cross	280	52	228	81.43	100	1	1	0
sideload_clear_x_sl_avail_cross	40	19	21	52.50	100	1	1	0
sideload_clear_x_regwen_cross	10	0	10	100.00	100	1	1	0

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4574

1

T2

13

T3

5

T4

2

auto[1]

502

1

T15

5

T35

2

T85

2

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4574

1

T2

13

T3

5

T4

2

auto[1]

502

1

T15

5

T35

2

T85

2

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4485

1

T2

13

T3

5

T4

2

auto[1]

591

1

T34

2

T241

5

T6

4

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4485

1

T2

13

T3

5

T4

2

auto[1]

591

1

T34

2

T241

5

T6

4

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	395	1			T35	4		T43	1		T6	5
auto[OpGenId]	1104	1			T3	1		T4	2		T5	2
auto[OpGenSwOut]	1019	1			T3	2		T26	2		T35	3
auto[OpGenHwOut]	2505	1			T2	13		T3	2		T15	12
auto[OpDisable]	53	1			T6	1		T47	1		T45	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	395	1			T35	4		T43	1		T6	5
auto[OpGenId]	1104	1			T3	1		T4	2		T5	2
auto[OpGenSwOut]	1019	1			T3	2		T26	2		T35	3
auto[OpGenHwOut]	2505	1			T2	13		T3	2		T15	12
auto[OpDisable]	53	1			T6	1		T47	1		T45	1

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4531

1

T2

8

T3

5

T4

2

auto[1]

545

1

T2

5

T17

5

T26

3

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4531

1

T2

8

T3

5

T4

2

auto[1]

545

1

T2

5

T17

5

T26

3

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4805

1

T2

13

T3

5

T4

2

auto[1]

271

1

T35

5

T122

4

T123

3

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1737	1			T2	2		T3	2		T4	1
auto[1]	686	1			T2	1		T3	1		T15	1
auto[2]	649	1			T2	4		T3	1		T4	1
auto[3]	657	1			T2	3		T15	2		T85	1
auto[4]	307	1			T34	1		T85	1		T152	1
auto[5]	355	1			T3	1		T15	1		T35	3
auto[6]	339	1			T2	1		T15	1		T5	1
auto[7]	346	1			T2	2		T17	2		T34	2

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1347	1			T2	3		T3	1		T15	2
clear_one[1]	686	1			T2	1		T3	1		T15	1
clear_one[2]	649	1			T2	4		T3	1		T4	1
clear_one[3]	657	1			T2	3		T15	2		T85	1
clear_none	1737	1			T2	2		T3	2		T4	1

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	990	1			T2	5		T3	1		T15	4
auto[StInit]	714	1			T2	1		T15	1		T5	1
auto[StCreatorRootKey]	550	1			T2	1		T3	1		T4	1
auto[StOwnerIntKey]	500	1			T2	1		T4	1		T15	1
auto[StOwnerKey]	444	1			T2	1		T3	1		T15	1
auto[StDisabled]	1750	1			T2	4		T3	2		T15	4
auto[StInvalid]	128	1			T51	3		T146	2		T101	5

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	990	1			T2	5		T3	1		T15	4
auto[StInit]	714	1			T2	1		T15	1		T5	1
auto[StCreatorRootKey]	550	1			T2	1		T3	1		T4	1
auto[StOwnerIntKey]	500	1			T2	1		T4	1		T15	1
auto[StOwnerKey]	444	1			T2	1		T3	1		T15	1
auto[StDisabled]	1750	1			T2	4		T3	2		T15	4
auto[StInvalid]	128	1			T51	3		T146	2		T101	5

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	52	228	81.43	52

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	10
[auto[0] - auto[1]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	2
[auto[2]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[2]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[2]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[2]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[3]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[3]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[4]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[4]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[4]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[4]]	[auto[StInvalid]]	[auto[OpAdvance]]	0	1	1
[auto[4]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[5] - auto[6]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	10
[auto[5] - auto[6]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	2
[auto[7]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[7]]	[auto[StInvalid]]	[auto[OpAdvance]]	0	1	1
[auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpAdvance]	5	1			T212	1		T266	1		T267	1
auto[0]	auto[StReset]	auto[OpGenId]	151	1			T3	1		T6	3		T47	3
auto[0]	auto[StReset]	auto[OpGenSwOut]	131	1			T23	1		T6	1		T47	1
auto[0]	auto[StReset]	auto[OpGenHwOut]	265	1			T2	1		T15	2		T17	1
auto[0]	auto[StInit]	auto[OpAdvance]	41	1			T47	1		T33	1		T93	1
auto[0]	auto[StInit]	auto[OpGenId]	102	1			T5	1		T28	1		T6	1
auto[0]	auto[StInit]	auto[OpGenSwOut]	98	1			T151	1		T44	1		T268	1
auto[0]	auto[StInit]	auto[OpGenHwOut]	157	1			T15	1		T35	1		T23	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	24	1			T43	1		T6	1		T56	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	53	1			T4	1		T6	2		T47	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	46	1			T230	1		T269	1		T30	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	61	1			T26	1		T152	1		T241	1
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	11	1			T6	1		T204	1		T270	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	26	1			T47	1		T53	1		T58	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	32	1			T26	1		T6	1		T46	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	57	1			T15	1		T152	1		T153	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T271	1		T272	1		T256	1
auto[0]	auto[StOwnerKey]	auto[OpGenId]	24	1			T230	1		T273	1		T274	1
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	15	1			T234	1		T56	1		T155	1
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	49	1			T17	1		T152	1		T275	1
auto[0]	auto[StDisabled]	auto[OpAdvance]	26	1			T35	1		T6	1		T45	1
auto[0]	auto[StDisabled]	auto[OpGenId]	69	1			T35	1		T6	1		T276	2
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	57	1			T3	1		T47	1		T53	1
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	176	1			T2	1		T17	1		T34	2
auto[0]	auto[StDisabled]	auto[OpDisable]	17	1			T58	1		T277	1		T278	1
auto[0]	auto[StInvalid]	auto[OpAdvance]	2	1			T51	1		T279	1		-	-
auto[0]	auto[StInvalid]	auto[OpGenId]	10	1			T231	1		T280	1		T281	1
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	13	1			T51	1		T146	1		T101	1
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	15	1			T51	1		T146	1		T282	1
auto[1]	auto[StReset]	auto[OpAdvance]	1	1			T283	1		-	-		-	-
auto[1]	auto[StReset]	auto[OpGenId]	20	1			T47	1		T284	1		T285	1
auto[1]	auto[StReset]	auto[OpGenSwOut]	22	1			T23	1		T24	1		T115	1
auto[1]	auto[StReset]	auto[OpGenHwOut]	53	1			T15	1		T85	1		T152	1
auto[1]	auto[StInit]	auto[OpAdvance]	9	1			T25	1		T286	1		T287	1
auto[1]	auto[StInit]	auto[OpGenId]	16	1			T25	2		T92	1		T93	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	7	1			T24	1		T286	1		T288	1
auto[1]	auto[StInit]	auto[OpGenHwOut]	28	1			T23	1		T289	1		T290	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	6	1			T216	1		T258	1		T291	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	7	1			T61	2		T204	1		T250	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	14	1			T284	1		T292	1		T61	2
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	35	1			T244	1		T47	2		T293	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	6	1			T61	1		T212	1		T294	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	10	1			T94	1		T216	1		T253	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	12	1			T47	1		T295	1		T204	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	43	1			T47	1		T240	1		T245	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T46	1		T204	1		T206	1
auto[1]	auto[StOwnerKey]	auto[OpGenId]	7	1			T296	1		T56	1		T297	1
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	19	1			T3	1		T6	1		T47	1
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	39	1			T298	1		T45	1		T299	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	26	1			T275	1		T236	1		T45	1
auto[1]	auto[StDisabled]	auto[OpGenId]	66	1			T151	1		T6	2		T230	1
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	58	1			T6	2		T239	1		T45	1
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	155	1			T2	1		T17	1		T85	1
auto[1]	auto[StDisabled]	auto[OpDisable]	6	1			T45	1		T56	1		T300	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	2	1			T89	1		T301	1		-	-
auto[1]	auto[StInvalid]	auto[OpGenId]	5	1			T282	1		T229	1		T201	1
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	8	1			T101	1		T91	1		T229	1
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	1	1			T302	1		-	-		-	-
auto[2]	auto[StReset]	auto[OpGenId]	23	1			T23	1		T122	1		T81	1
auto[2]	auto[StReset]	auto[OpGenSwOut]	15	1			T47	1		T58	1		T285	1
auto[2]	auto[StReset]	auto[OpGenHwOut]	52	1			T2	1		T47	2		T290	2
auto[2]	auto[StInit]	auto[OpAdvance]	7	1			T24	1		T92	1		T216	1
auto[2]	auto[StInit]	auto[OpGenId]	11	1			T104	1		T303	1		T304	1
auto[2]	auto[StInit]	auto[OpGenSwOut]	10	1			T92	1		T305	1		T306	1
auto[2]	auto[StInit]	auto[OpGenHwOut]	29	1			T34	1		T152	1		T78	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	7	1			T115	1		T65	1		T259	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	14	1			T47	1		T54	1		T216	2
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	14	1			T115	1		T216	2		T307	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	49	1			T2	1		T15	1		T34	1
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	7	1			T35	2		T250	1		T308	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	17	1			T4	1		T43	1		T276	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	12	1			T35	1		T6	1		T239	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	39	1			T17	1		T242	1		T244	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	3	1			T47	1		T292	1		T308	1
auto[2]	auto[StOwnerKey]	auto[OpGenId]	14	1			T56	1		T68	1		T69	1
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	11	1			T295	1		T210	1		T250	1
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	39	1			T2	1		T34	1		T35	1
auto[2]	auto[StDisabled]	auto[OpAdvance]	20	1			T238	1		T45	1		T56	1
auto[2]	auto[StDisabled]	auto[OpGenId]	42	1			T47	1		T309	2		T58	1
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	32	1			T26	1		T35	1		T233	1
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	157	1			T2	1		T3	1		T15	2
auto[2]	auto[StDisabled]	auto[OpDisable]	10	1			T6	1		T68	1		T310	1
auto[2]	auto[StInvalid]	auto[OpAdvance]	2	1			T227	1		T311	1		-	-
auto[2]	auto[StInvalid]	auto[OpGenId]	6	1			T88	1		T89	2		T312	1
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	3	1			T110	1		T313	1		T281	1
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	4	1			T91	1		T314	1		T315	1
auto[3]	auto[StReset]	auto[OpAdvance]	1	1			T316	1		-	-		-	-
auto[3]	auto[StReset]	auto[OpGenId]	17	1			T45	1		T317	1		T217	1
auto[3]	auto[StReset]	auto[OpGenSwOut]	23	1			T6	1		T47	1		T204	1
auto[3]	auto[StReset]	auto[OpGenHwOut]	53	1			T2	2		T15	1		T318	1
auto[3]	auto[StInit]	auto[OpAdvance]	10	1			T100	1		T212	1		T319	2
auto[3]	auto[StInit]	auto[OpGenId]	8	1			T285	1		T317	1		T316	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	14	1			T45	1		T81	1		T320	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	21	1			T2	1		T242	1		T47	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	9	1			T123	1		T321	1		T322	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	5	1			T323	1		T324	1		T204	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	14	1			T6	1		T233	1		T61	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	40	1			T44	1		T242	1		T325	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T326	1		T327	1		T98	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	16	1			T6	1		T81	1		T250	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	16	1			T44	1		T238	1		T328	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	34	1			T58	1		T147	1		T56	2
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	9	1			T236	1		T322	1		T291	1
auto[3]	auto[StOwnerKey]	auto[OpGenId]	9	1			T317	1		T307	1		T130	1
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	10	1			T27	1		T68	1		T140	1
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	36	1			T85	1		T153	1		T241	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	18	1			T274	1		T122	1		T123	1
auto[3]	auto[StDisabled]	auto[OpGenId]	52	1			T6	2		T47	1		T45	2
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	57	1			T230	1		T47	1		T273	1
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	157	1			T15	1		T152	2		T153	1
auto[3]	auto[StDisabled]	auto[OpDisable]	4	1			T67	1		T329	1		T330	1
auto[3]	auto[StInvalid]	auto[OpAdvance]	3	1			T229	1		T331	1		T332	1
auto[3]	auto[StInvalid]	auto[OpGenId]	6	1			T101	1		T229	1		T331	1
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	4	1			T101	1		T89	1		T201	1
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	6	1			T227	1		T311	1		T88	1
auto[4]	auto[StReset]	auto[OpGenId]	9	1			T6	2		T47	1		T57	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	13	1			T6	1		T204	2		T229	1
auto[4]	auto[StReset]	auto[OpGenHwOut]	14	1			T290	1		T318	1		T317	1
auto[4]	auto[StInit]	auto[OpAdvance]	4	1			T271	1		T333	1		T334	1
auto[4]	auto[StInit]	auto[OpGenId]	5	1			T23	1		T25	1		T92	1
auto[4]	auto[StInit]	auto[OpGenSwOut]	6	1			T335	1		T61	1		T336	1
auto[4]	auto[StInit]	auto[OpGenHwOut]	8	1			T45	1		T136	1		T139	1
auto[4]	auto[StCreatorRootKey]	auto[OpAdvance]	2	1			T268	1		T337	1		-	-
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	10	1			T338	1		T297	1		T339	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	7	1			T61	1		T340	1		T322	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	25	1			T232	1		T341	1		T299	1
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T342	1		T337	2		T257	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	3	1			T343	1		T344	1		T345	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	9	1			T230	1		T346	1		T347	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	16	1			T34	1		T85	1		T348	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T47	1		T349	1		T337	1
auto[4]	auto[StOwnerKey]	auto[OpGenId]	3	1			T47	1		T250	1		T350	1
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	6	1			T351	1		T79	1		T352	1
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	18	1			T240	1		T45	1		T147	1
auto[4]	auto[StDisabled]	auto[OpAdvance]	8	1			T292	1		T159	1		T247	1
auto[4]	auto[StDisabled]	auto[OpGenId]	33	1			T6	1		T47	1		T123	4
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	17	1			T6	1		T45	2		T58	1
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	63	1			T152	1		T242	1		T353	1
auto[4]	auto[StDisabled]	auto[OpDisable]	6	1			T66	1		T130	1		T354	1
auto[4]	auto[StInvalid]	auto[OpGenId]	3	1			T282	1		T331	1		T355	1
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	5	1			T235	1		T229	1		T356	2
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	5	1			T282	1		T311	1		T357	1
auto[5]	auto[StReset]	auto[OpAdvance]	1	1			T358	1		-	-		-	-
auto[5]	auto[StReset]	auto[OpGenId]	8	1			T45	1		T321	1		T338	1
auto[5]	auto[StReset]	auto[OpGenSwOut]	10	1			T64	1		T159	1		T88	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	17	1			T152	2		T139	1		T317	1
auto[5]	auto[StInit]	auto[OpAdvance]	5	1			T35	1		T6	1		T58	1
auto[5]	auto[StInit]	auto[OpGenId]	16	1			T23	1		T320	1		T359	4
auto[5]	auto[StInit]	auto[OpGenSwOut]	5	1			T204	1		T102	1		T259	1
auto[5]	auto[StInit]	auto[OpGenHwOut]	21	1			T85	1		T360	1		T299	1
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T322	1		T361	1		T362	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	9	1			T35	1		T58	1		T79	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	5	1			T35	1		T363	1		T364	2
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	23	1			T3	1		T85	1		T153	1
auto[5]	auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T206	1		T365	1		T261	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	9	1			T151	1		T366	1		T322	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	5	1			T47	1		T367	1		T361	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	21	1			T30	1		T325	1		T368	1
auto[5]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T156	1		T359	3		T267	1
auto[5]	auto[StOwnerKey]	auto[OpGenId]	14	1			T322	1		T306	4		T247	1
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	8	1			T324	1		T369	1		T365	2
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	20	1			T353	1		T244	1		T370	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	16	1			T30	1		T284	1		T366	1
auto[5]	auto[StDisabled]	auto[OpGenId]	30	1			T151	1		T6	1		T240	2
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	27	1			T232	1		T346	1		T58	1
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	62	1			T15	1		T153	1		T242	1
auto[5]	auto[StDisabled]	auto[OpDisable]	2	1			T47	1		T71	1		-	-
auto[5]	auto[StInvalid]	auto[OpAdvance]	1	1			T101	1		-	-		-	-
auto[5]	auto[StInvalid]	auto[OpGenId]	3	1			T229	1		T371	1		T372	1
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	2	1			T110	1		T201	1		-	-
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	1	1			T373	1		-	-		-	-
auto[6]	auto[StReset]	auto[OpAdvance]	1	1			T365	1		-	-		-	-
auto[6]	auto[StReset]	auto[OpGenId]	10	1			T374	1		T58	1		T217	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	6	1			T326	1		T375	1		T344	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	22	1			T2	1		T34	1		T289	1
auto[6]	auto[StInit]	auto[OpAdvance]	3	1			T92	1		T320	1		T358	1
auto[6]	auto[StInit]	auto[OpGenId]	8	1			T27	1		T8	1		T317	1
auto[6]	auto[StInit]	auto[OpGenSwOut]	9	1			T323	1		T92	1		T61	1
auto[6]	auto[StInit]	auto[OpGenHwOut]	15	1			T376	1		T377	1		T148	1
auto[6]	auto[StCreatorRootKey]	auto[OpAdvance]	5	1			T317	1		T378	3		T379	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	5	1			T58	1		T131	1		T380	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	4	1			T151	1		T107	1		T381	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	19	1			T289	1		T58	1		T108	1
auto[6]	auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T284	1		T107	1		T267	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	7	1			T303	1		T73	1		T267	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	10	1			T27	1		T58	1		T382	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	24	1			T241	1		T45	2		T376	1
auto[6]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T383	1		T107	1		T267	1
auto[6]	auto[StOwnerKey]	auto[OpGenId]	10	1			T335	1		T204	1		T209	1
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	12	1			T6	2		T56	1		T115	1
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	17	1			T15	1		T242	1		T318	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	12	1			T6	1		T45	1		T216	1
auto[6]	auto[StDisabled]	auto[OpGenId]	25	1			T5	1		T27	1		T45	2
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	24	1			T6	1		T58	1		T80	1
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	70	1			T17	1		T85	2		T151	1
auto[6]	auto[StDisabled]	auto[OpDisable]	4	1			T384	1		T385	1		T386	1
auto[6]	auto[StInvalid]	auto[OpAdvance]	3	1			T282	1		T280	1		T312	1
auto[6]	auto[StInvalid]	auto[OpGenId]	1	1			T387	1		-	-		-	-
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	1	1			T388	1		-	-		-	-
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	3	1			T314	1		T279	1		T389	1
auto[7]	auto[StReset]	auto[OpAdvance]	1	1			T122	1		-	-		-	-
auto[7]	auto[StReset]	auto[OpGenId]	12	1			T53	1		T246	1		T297	1
auto[7]	auto[StReset]	auto[OpGenSwOut]	8	1			T45	1		T323	1		T69	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	26	1			T34	1		T289	1		T360	1
auto[7]	auto[StInit]	auto[OpAdvance]	5	1			T122	1		T208	1		T390	1
auto[7]	auto[StInit]	auto[OpGenId]	13	1			T24	1		T324	1		T115	1
auto[7]	auto[StInit]	auto[OpGenSwOut]	7	1			T122	1		T391	1		T106	1
auto[7]	auto[StInit]	auto[OpGenHwOut]	16	1			T17	1		T53	1		T122	1
auto[7]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T122	1		T292	1		T222	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	5	1			T45	1		T392	1		T98	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	10	1			T47	1		T53	1		T69	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	16	1			T17	1		T139	1		T204	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T258	1		T266	1		T316	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	11	1			T56	1		T31	1		T393	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	5	1			T123	1		T61	1		T250	2
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	19	1			T2	1		T289	1		T318	1
auto[7]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T266	1		T394	1		T209	1
auto[7]	auto[StOwnerKey]	auto[OpGenId]	8	1			T395	1		T208	1		T396	1
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	2	1			T364	1		T397	1		-	-
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	13	1			T243	1		T360	1		T83	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	14	1			T47	1		T45	1		T58	1
auto[7]	auto[StDisabled]	auto[OpGenId]	26	1			T6	1		T122	1		T45	3
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	24	1			T47	2		T236	1		T45	1
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	78	1			T2	1		T34	1		T353	1
auto[7]	auto[StDisabled]	auto[OpDisable]	4	1			T58	1		T115	1		T72	1
auto[7]	auto[StInvalid]	auto[OpGenId]	2	1			T398	1		T315	1		-	-
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	5	1			T311	1		T313	1		T357	1
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	3	1			T312	1		T398	1		T388	1

---

Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1347

1

T2

3

T3

1

T15

2

clear_one[1]

auto[0]

auto[0]

auto[0]

369

1

T3

1

T15

1

T85

2

clear_one[1]

auto[0]

auto[0]

auto[1]

129

1

T2

1

T17

1

T6

1

clear_one[1]

auto[0]

auto[1]

auto[0]

144

1

T241

2

T230

1

T244

2

clear_one[1]

auto[0]

auto[1]

auto[1]

44

1

T275

1

T399

2

T400

1

clear_one[2]

auto[0]

auto[0]

auto[0]

372

1

T2

1

T3

1

T4

1

clear_one[2]

auto[0]

auto[0]

auto[1]

139

1

T2

3

T17

2

T26

1

clear_one[2]

auto[1]

auto[0]

auto[0]

114

1

T15

3

T85

1

T6

1

clear_one[2]

auto[1]

auto[0]

auto[1]

24

1

T69

1

T224

1

T401

4

clear_one[3]

auto[0]

auto[0]

auto[0]

371

1

T2

3

T15

1

T27

1

clear_one[3]

auto[0]

auto[1]

auto[0]

132

1

T241

1

T230

1

T47

1

clear_one[3]

auto[1]

auto[0]

auto[0]

117

1

T15

1

T85

1

T152

2

clear_one[3]

auto[1]

auto[1]

auto[0]

37

1

T6

2

T274

1

T58

2

clear_none

auto[0]

auto[0]

auto[0]

1226

1

T2

1

T3

2

T4

1

clear_none

auto[0]

auto[0]

auto[1]

132

1

T2

1

T17

2

T26

2

clear_none

auto[0]

auto[1]

auto[0]

142

1

T34

2

T241

2

T230

1

clear_none

auto[0]

auto[1]

auto[1]

27

1

T275

1

T402

1

T68

1

clear_none

auto[1]

auto[0]

auto[0]

121

1

T15

1

T152

3

T153

3

clear_none

auto[1]

auto[0]

auto[1]

24

1

T35

2

T43

1

T234

1

clear_none

auto[1]

auto[1]

auto[0]

39

1

T6

2

T47

2

T58

1

clear_none

auto[1]

auto[1]

auto[1]

26

1

T274

1

T45

1

T68

2

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1252	1			T2	3		T3	1		T15	2
clear_all	auto[1]	95	1			T35	2		T122	4		T123	3
clear_one[1]	auto[0]	649	1			T2	1		T3	1		T15	1
clear_one[1]	auto[1]	37	1			T212	1		T216	2		T401	1
clear_one[2]	auto[0]	619	1			T2	4		T3	1		T4	1
clear_one[2]	auto[1]	30	1			T35	3		T216	4		T401	3
clear_one[3]	auto[0]	622	1			T2	3		T15	2		T85	1
clear_one[3]	auto[1]	35	1			T212	1		T216	1		T156	2
clear_none	auto[0]	1663	1			T2	2		T3	2		T4	1
clear_none	auto[1]	74	1			T155	1		T212	2		T215	2