Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
43.16	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	360	216	144	40.00

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	168	112	40.00	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11104

1

T2

22

T3

16

T4

5

auto[Attestation]

7809

1

T2

3

T3

15

T4

7

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2723	1			T3	4		T5	1		T26	8
auto[Aes]	3360	1			T3	4		T4	3		T15	20
auto[Kmac]	3361	1			T3	6		T4	2		T5	2
auto[Otbn]	3430	1			T2	25		T3	8		T4	4

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7671	1			T2	8		T3	16		T4	4
auto[OpGenId]	6039	1			T3	9		T4	3		T5	5
auto[OpGenSwOut]	5845	1			T3	19		T4	3		T5	5
auto[OpGenHwOut]	7029	1			T2	25		T3	3		T4	6
auto[OpDisable]	116	1			T6	1		T47	1		T48	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

9973

1

T2

8

T3

16

T4

13

auto[OpDoneFail]

16727

1

T2

25

T3

31

T4

3

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6112	1			T2	18		T3	17		T4	1
auto[StInit]	4175	1			T2	2		T3	4		T4	4
auto[StCreatorRootKey]	2956	1			T2	2		T3	4		T4	3
auto[StOwnerIntKey]	2636	1			T2	2		T3	4		T4	2
auto[StOwnerKey]	2357	1			T2	2		T3	4		T4	6
auto[StDisabled]	7585	1			T2	7		T3	14		T15	7
auto[StInvalid]	879	1			T51	24		T146	21		T101	33

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	168	112	40.00	168

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	303	1			T3	1		T23	1		T27	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	126	1			T23	1		T6	1		T47	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	80	1			T35	1		T28	1		T6	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	78	1			T3	1		T27	2		T6	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	64	1			T6	1		T47	1		T226	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	186	1			T5	1		T26	2		T35	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	29	1			T101	1		T91	1		T227	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	321	1			T3	1		T86	1		T23	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	109	1			T23	1		T228	1		T47	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	75	1			T26	1		T37	1		T6	3
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	65	1			T86	1		T6	1		T47	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	60	1			T26	2		T151	1		T6	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	190	1			T5	2		T6	1		T47	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	23	1			T146	1		T101	1		T229	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	313	1			T3	1		T37	2		T6	3
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	98	1			T3	1		T6	1		T47	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	69	1			T19	1		T230	1		T48	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	55	1			T37	1		T45	2		T46	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	61	1			T86	1		T43	1		T47	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	196	1			T3	1		T5	1		T26	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	25	1			T101	1		T91	1		T231	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	336	1			T3	3		T23	1		T6	6
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	110	1			T23	3		T9	1		T47	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	85	1			T26	1		T232	1		T53	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	75	1			T228	1		T47	1		T233	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	50	1			T6	1		T234	1		T47	3
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	168	1			T5	1		T43	1		T6	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	29	1			T51	1		T146	1		T235	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	54	1			T6	1		T47	2		T45	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	97	1			T26	1		T35	1		T236	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	73	1			T35	1		T9	1		T37	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	61	1			T47	1		T237	1		T238	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	58	1			T3	1		T43	1		T6	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	217	1			T3	1		T26	1		T43	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	29	1			T101	2		T91	2		T235	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	66	1			T6	3		T47	5		T58	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	116	1			T44	1		T23	1		T230	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	80	1			T151	1		T44	1		T28	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	75	1			T3	1		T6	2		T47	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	51	1			T4	1		T6	1		T45	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	207	1			T3	1		T27	2		T6	5
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	22	1			T51	1		T146	1		T101	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	59	1			T6	4		T47	3		T45	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	123	1			T35	1		T36	1		T43	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	74	1			T26	1		T27	1		T233	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	70	1			T26	1		T35	1		T43	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	67	1			T3	1		T27	1		T6	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	207	1			T26	2		T151	1		T6	6
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	31	1			T51	1		T146	1		T101	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	62	1			T3	1		T6	4		T47	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	112	1			T3	1		T26	1		T36	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	77	1			T3	1		T4	1		T44	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	61	1			T35	2		T230	1		T239	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	70	1			T4	1		T27	1		T47	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	208	1			T3	2		T35	1		T86	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	39	1			T51	2		T146	2		T101	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	270	1			T23	1		T37	2		T27	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	124	1			T36	1		T6	2		T50	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	50	1			T47	4		T45	1		T58	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	70	1			T6	1		T240	1		T55	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	56	1			T35	1		T47	1		T233	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	170	1			T26	1		T43	1		T6	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	25	1			T101	2		T91	2		T231	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	501	1			T15	12		T85	10		T152	12
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	117	1			T15	1		T85	1		T152	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	94	1			T85	1		T153	1		T6	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	84	1			T15	1		T152	1		T44	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	75	1			T4	1		T15	1		T26	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	243	1			T15	3		T85	2		T43	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	27	1			T51	1		T146	1		T231	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	448	1			T34	8		T27	1		T6	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	129	1			T4	1		T34	1		T23	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	108	1			T28	1		T241	1		T47	3
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	89	1			T34	1		T35	1		T6	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	81	1			T4	1		T26	1		T34	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	244	1			T3	1		T5	1		T34	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	17	1			T51	1		T101	2		T231	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	449	1			T2	17		T17	1		T37	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	124	1			T2	1		T17	1		T35	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	94	1			T17	1		T9	1		T27	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	101	1			T43	1		T44	1		T242	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	83	1			T2	1		T4	1		T27	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	284	1			T2	3		T5	1		T17	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	29	1			T146	3		T91	3		T235	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	47	1			T6	4		T47	1		T45	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	101	1			T26	1		T43	1		T6	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	59	1			T35	1		T234	1		T47	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	59	1			T26	1		T43	1		T47	4
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	31	1			T6	2		T240	1		T45	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	176	1			T26	1		T35	1		T43	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	30	1			T101	2		T91	2		T231	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	43	1			T6	3		T47	1		T45	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	121	1			T6	1		T50	2		T243	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	118	1			T3	1		T15	1		T152	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	90	1			T85	1		T27	2		T6	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	83	1			T4	1		T26	1		T85	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	281	1			T15	1		T35	1		T85	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	23	1			T101	2		T91	2		T227	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	41	1			T3	1		T6	1		T45	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	126	1			T26	1		T241	1		T6	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	106	1			T34	1		T35	1		T6	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	92	1			T44	1		T241	1		T47	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	90	1			T244	1		T47	2		T245	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	305	1			T34	3		T43	1		T241	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	37	1			T51	1		T101	1		T91	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	52	1			T6	2		T45	1		T58	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	137	1			T4	1		T27	1		T6	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	114	1			T2	1		T26	1		T242	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	92	1			T2	1		T17	1		T44	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	87	1			T17	1		T242	1		T234	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	270	1			T2	1		T5	4		T17	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	32	1			T51	3		T146	1		T101	3

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	206	1			T3	1		T35	1		T28	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	660	1			T3	1		T5	1		T26	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	183	1			T26	2		T86	1		T151	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	660	1			T3	1		T5	2		T26	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	175	1			T19	1		T86	1		T43	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	642	1			T3	3		T5	1		T26	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	195	1			T26	1		T6	1		T234	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	658	1			T3	3		T5	1		T43	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	167	1			T3	1		T35	1		T43	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	422	1			T3	1		T26	2		T35	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	191	1			T3	1		T4	1		T151	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	426	1			T3	1		T44	1		T23	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	192	1			T3	1		T26	1		T35	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	439	1			T26	3		T35	1		T36	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	191	1			T3	1		T4	2		T35	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	438	1			T3	4		T26	1		T35	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	155	1			T35	1		T6	1		T47	5
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	610	1			T26	1		T36	1		T43	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	243	1			T4	1		T15	2		T85	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	898	1			T15	16		T26	1		T85	13
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	261	1			T4	1		T26	1		T34	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	855	1			T3	1		T4	1		T5	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	265	1			T2	1		T4	1		T17	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	899	1			T2	21		T5	1		T17	4
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	135	1			T35	1		T43	1		T6	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	368	1			T26	3		T35	1		T43	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	273	1			T3	1		T4	1		T15	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	486	1			T15	1		T26	1		T35	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	267	1			T34	1		T35	1		T44	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	530	1			T3	1		T26	1		T34	3
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	275	1			T2	2		T17	2		T26	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	509	1			T2	1		T4	1		T5	4