Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

30571

1

T2

37

T3

51

T4

17

auto[1]

273

1

T35

7

T122

1

T123

8

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	30584	1			T2	37		T3	51		T4	17
auto[134217728:268435455]	10	1			T35	1		T212	1		T430	1
auto[268435456:402653183]	8	1			T35	1		T306	1		T431	2
auto[402653184:536870911]	8	1			T430	1		T401	1		T107	1
auto[536870912:671088639]	10	1			T359	1		T414	2		T266	1
auto[671088640:805306367]	12	1			T122	1		T155	1		T291	1
auto[805306368:939524095]	14	1			T123	1		T401	1		T306	1
auto[939524096:1073741823]	9	1			T123	1		T401	1		T266	1
auto[1073741824:1207959551]	8	1			T215	1		T216	2		T107	1
auto[1207959552:1342177279]	7	1			T216	1		T430	1		T401	1
auto[1342177280:1476395007]	3	1			T107	1		T316	2		-	-
auto[1476395008:1610612735]	6	1			T107	1		T306	2		T369	1
auto[1610612736:1744830463]	11	1			T123	1		T212	2		T291	1
auto[1744830464:1879048191]	4	1			T35	1		T411	1		T412	1
auto[1879048192:2013265919]	12	1			T430	2		T401	1		T271	1
auto[2013265920:2147483647]	7	1			T35	1		T291	1		T107	1
auto[2147483648:2281701375]	7	1			T216	1		T266	1		T306	1
auto[2281701376:2415919103]	10	1			T349	1		T359	1		T107	1
auto[2415919104:2550136831]	10	1			T35	1		T349	1		T359	1
auto[2550136832:2684354559]	10	1			T35	1		T359	1		T414	1
auto[2684354560:2818572287]	8	1			T123	1		T212	1		T349	1
auto[2818572288:2952790015]	7	1			T216	1		T316	1		T365	1
auto[2952790016:3087007743]	7	1			T212	1		T156	1		T414	1
auto[3087007744:3221225471]	9	1			T401	1		T306	1		T316	1
auto[3221225472:3355443199]	6	1			T123	1		T430	1		T156	2
auto[3355443200:3489660927]	5	1			T35	1		T155	1		T359	1
auto[3489660928:3623878655]	6	1			T401	1		T359	1		T266	1
auto[3623878656:3758096383]	12	1			T414	1		T266	2		T306	1
auto[3758096384:3892314111]	9	1			T123	1		T215	1		T156	1
auto[3892314112:4026531839]	11	1			T123	1		T430	1		T359	1
auto[4026531840:4160749567]	5	1			T156	1		T401	1		T306	1
auto[4160749568:4294967295]	9	1			T123	1		T159	1		T306	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	30	34	53.12	30

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[671088640:805306367]]	[auto[0]]	--	--	5
[auto[939524096:1073741823] - auto[4160749568:4294967295]]	[auto[0]]	--	--	25

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	30570	1			T2	37		T3	51		T4	17
auto[0:134217727]	auto[1]	14	1			T216	2		T430	1		T156	1
auto[134217728:268435455]	auto[1]	10	1			T35	1		T212	1		T430	1
auto[268435456:402653183]	auto[1]	8	1			T35	1		T306	1		T431	2
auto[402653184:536870911]	auto[1]	8	1			T430	1		T401	1		T107	1
auto[536870912:671088639]	auto[1]	10	1			T359	1		T414	2		T266	1
auto[671088640:805306367]	auto[1]	12	1			T122	1		T155	1		T291	1
auto[805306368:939524095]	auto[0]	1	1			T316	1		-	-		-	-
auto[805306368:939524095]	auto[1]	13	1			T123	1		T401	1		T306	1
auto[939524096:1073741823]	auto[1]	9	1			T123	1		T401	1		T266	1
auto[1073741824:1207959551]	auto[1]	8	1			T215	1		T216	2		T107	1
auto[1207959552:1342177279]	auto[1]	7	1			T216	1		T430	1		T401	1
auto[1342177280:1476395007]	auto[1]	3	1			T107	1		T316	2		-	-
auto[1476395008:1610612735]	auto[1]	6	1			T107	1		T306	2		T369	1
auto[1610612736:1744830463]	auto[1]	11	1			T123	1		T212	2		T291	1
auto[1744830464:1879048191]	auto[1]	4	1			T35	1		T411	1		T412	1
auto[1879048192:2013265919]	auto[1]	12	1			T430	2		T401	1		T271	1
auto[2013265920:2147483647]	auto[1]	7	1			T35	1		T291	1		T107	1
auto[2147483648:2281701375]	auto[1]	7	1			T216	1		T266	1		T306	1
auto[2281701376:2415919103]	auto[1]	10	1			T349	1		T359	1		T107	1
auto[2415919104:2550136831]	auto[1]	10	1			T35	1		T349	1		T359	1
auto[2550136832:2684354559]	auto[1]	10	1			T35	1		T359	1		T414	1
auto[2684354560:2818572287]	auto[1]	8	1			T123	1		T212	1		T349	1
auto[2818572288:2952790015]	auto[1]	7	1			T216	1		T316	1		T365	1
auto[2952790016:3087007743]	auto[1]	7	1			T212	1		T156	1		T414	1
auto[3087007744:3221225471]	auto[1]	9	1			T401	1		T306	1		T316	1
auto[3221225472:3355443199]	auto[1]	6	1			T123	1		T430	1		T156	2
auto[3355443200:3489660927]	auto[1]	5	1			T35	1		T155	1		T359	1
auto[3489660928:3623878655]	auto[1]	6	1			T401	1		T359	1		T266	1
auto[3623878656:3758096383]	auto[1]	12	1			T414	1		T266	2		T306	1
auto[3758096384:3892314111]	auto[1]	9	1			T123	1		T215	1		T156	1
auto[3892314112:4026531839]	auto[1]	11	1			T123	1		T430	1		T359	1
auto[4026531840:4160749567]	auto[1]	5	1			T156	1		T401	1		T306	1
auto[4160749568:4294967295]	auto[1]	9	1			T123	1		T159	1		T306	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1490

1

T5

1

T44

2

T28

1

auto[1]

1625

1

T4

2

T5

2

T19

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	125	1			T19	1		T26	1		T6	2
auto[134217728:268435455]	97	1			T6	5		T47	2		T274	1
auto[268435456:402653183]	92	1			T26	1		T6	3		T47	3
auto[402653184:536870911]	111	1			T9	1		T27	1		T6	1
auto[536870912:671088639]	89	1			T6	1		T275	1		T274	1
auto[671088640:805306367]	113	1			T44	1		T23	1		T27	1
auto[805306368:939524095]	105	1			T47	1		T53	1		T7	1
auto[939524096:1073741823]	84	1			T6	1		T52	1		T47	2
auto[1073741824:1207959551]	85	1			T6	1		T47	1		T45	1
auto[1207959552:1342177279]	109	1			T6	2		T47	2		T122	2
auto[1342177280:1476395007]	87	1			T4	1		T6	2		T47	1
auto[1476395008:1610612735]	104	1			T43	1		T6	1		T47	1
auto[1610612736:1744830463]	92	1			T9	1		T6	3		T234	1
auto[1744830464:1879048191]	100	1			T47	2		T24	1		T238	1
auto[1879048192:2013265919]	98	1			T23	1		T6	3		T47	2
auto[2013265920:2147483647]	100	1			T43	1		T6	1		T24	1
auto[2147483648:2281701375]	92	1			T6	1		T274	1		T233	1
auto[2281701376:2415919103]	90	1			T26	1		T28	2		T6	3
auto[2415919104:2550136831]	85	1			T234	1		T232	2		T8	1
auto[2550136832:2684354559]	94	1			T26	1		T6	2		T274	1
auto[2684354560:2818572287]	100	1			T43	1		T6	2		T236	1
auto[2818572288:2952790015]	83	1			T6	1		T45	2		T8	2
auto[2952790016:3087007743]	106	1			T4	1		T6	1		T52	1
auto[3087007744:3221225471]	96	1			T5	1		T44	1		T6	1
auto[3221225472:3355443199]	103	1			T23	1		T27	1		T6	1
auto[3355443200:3489660927]	82	1			T43	1		T6	3		T275	1
auto[3489660928:3623878655]	92	1			T23	1		T9	1		T6	1
auto[3623878656:3758096383]	99	1			T6	1		T47	2		T48	1
auto[3758096384:3892314111]	109	1			T44	1		T23	1		T27	1
auto[3892314112:4026531839]	96	1			T5	1		T23	1		T6	2
auto[4026531840:4160749567]	99	1			T27	1		T6	3		T234	1
auto[4160749568:4294967295]	98	1			T5	1		T35	1		T6	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	68	1			T6	2		T232	1		T368	1
auto[0:134217727]	auto[1]	57	1			T19	1		T26	1		T233	1
auto[134217728:268435455]	auto[0]	52	1			T6	2		T47	2		T7	1
auto[134217728:268435455]	auto[1]	45	1			T6	3		T274	1		T24	1
auto[268435456:402653183]	auto[0]	47	1			T6	1		T47	1		T45	3
auto[268435456:402653183]	auto[1]	45	1			T26	1		T6	2		T47	2
auto[402653184:536870911]	auto[0]	55	1			T6	1		T47	2		T45	2
auto[402653184:536870911]	auto[1]	56	1			T9	1		T27	1		T52	1
auto[536870912:671088639]	auto[0]	49	1			T6	1		T275	1		T66	1
auto[536870912:671088639]	auto[1]	40	1			T274	1		T54	1		T351	1
auto[671088640:805306367]	auto[0]	59	1			T44	1		T23	1		T27	1
auto[671088640:805306367]	auto[1]	54	1			T236	1		T45	4		T101	1
auto[805306368:939524095]	auto[0]	52	1			T7	1		T351	1		T66	1
auto[805306368:939524095]	auto[1]	53	1			T47	1		T53	1		T45	1
auto[939524096:1073741823]	auto[0]	37	1			T47	2		T238	1		T7	1
auto[939524096:1073741823]	auto[1]	47	1			T6	1		T52	1		T274	1
auto[1073741824:1207959551]	auto[0]	40	1			T6	1		T47	1		T374	2
auto[1073741824:1207959551]	auto[1]	45	1			T45	1		T46	1		T137	1
auto[1207959552:1342177279]	auto[0]	58	1			T47	1		T122	1		T7	2
auto[1207959552:1342177279]	auto[1]	51	1			T6	2		T47	1		T122	1
auto[1342177280:1476395007]	auto[0]	40	1			T6	2		T275	1		T7	1
auto[1342177280:1476395007]	auto[1]	47	1			T4	1		T47	1		T54	1
auto[1476395008:1610612735]	auto[0]	45	1			T6	1		T47	1		T232	1
auto[1476395008:1610612735]	auto[1]	59	1			T43	1		T45	2		T323	1
auto[1610612736:1744830463]	auto[0]	38	1			T6	2		T234	1		T47	1
auto[1610612736:1744830463]	auto[1]	54	1			T9	1		T6	1		T47	1
auto[1744830464:1879048191]	auto[0]	50	1			T47	1		T432	1		T93	1
auto[1744830464:1879048191]	auto[1]	50	1			T47	1		T24	1		T238	1
auto[1879048192:2013265919]	auto[0]	43	1			T23	1		T6	1		T47	2
auto[1879048192:2013265919]	auto[1]	55	1			T6	2		T269	1		T236	1
auto[2013265920:2147483647]	auto[0]	58	1			T6	1		T63	1		T146	1
auto[2013265920:2147483647]	auto[1]	42	1			T43	1		T24	1		T323	1
auto[2147483648:2281701375]	auto[0]	39	1			T6	1		T7	1		T58	2
auto[2147483648:2281701375]	auto[1]	53	1			T274	1		T233	1		T238	1
auto[2281701376:2415919103]	auto[0]	42	1			T28	1		T6	1		T45	1
auto[2281701376:2415919103]	auto[1]	48	1			T26	1		T28	1		T6	2
auto[2415919104:2550136831]	auto[0]	43	1			T234	1		T232	2		T8	1
auto[2415919104:2550136831]	auto[1]	42	1			T46	1		T80	1		T146	1
auto[2550136832:2684354559]	auto[0]	43	1			T6	1		T274	1		T93	1
auto[2550136832:2684354559]	auto[1]	51	1			T26	1		T6	1		T238	1
auto[2684354560:2818572287]	auto[0]	45	1			T6	1		T236	1		T374	1
auto[2684354560:2818572287]	auto[1]	55	1			T43	1		T6	1		T24	1
auto[2818572288:2952790015]	auto[0]	37	1			T6	1		T45	1		T123	1
auto[2818572288:2952790015]	auto[1]	46	1			T45	1		T8	2		T58	2
auto[2952790016:3087007743]	auto[0]	50	1			T6	1		T52	1		T45	1
auto[2952790016:3087007743]	auto[1]	56	1			T4	1		T47	1		T232	1
auto[3087007744:3221225471]	auto[0]	48	1			T44	1		T63	1		T58	1
auto[3087007744:3221225471]	auto[1]	48	1			T5	1		T6	1		T232	1
auto[3221225472:3355443199]	auto[0]	46	1			T23	1		T6	1		T50	1
auto[3221225472:3355443199]	auto[1]	57	1			T27	1		T47	1		T122	1
auto[3355443200:3489660927]	auto[0]	47	1			T6	2		T63	1		T58	1
auto[3355443200:3489660927]	auto[1]	35	1			T43	1		T6	1		T275	1
auto[3489660928:3623878655]	auto[0]	42	1			T23	1		T6	1		T52	1
auto[3489660928:3623878655]	auto[1]	50	1			T9	1		T234	1		T236	1
auto[3623878656:3758096383]	auto[0]	40	1			T47	1		T275	1		T53	1
auto[3623878656:3758096383]	auto[1]	59	1			T6	1		T47	1		T48	1
auto[3758096384:3892314111]	auto[0]	44	1			T27	1		T6	2		T52	1
auto[3758096384:3892314111]	auto[1]	65	1			T44	1		T23	1		T234	1
auto[3892314112:4026531839]	auto[0]	49	1			T23	1		T6	2		T45	1
auto[3892314112:4026531839]	auto[1]	47	1			T5	1		T47	1		T54	2
auto[4026531840:4160749567]	auto[0]	44	1			T6	1		T47	1		T269	1
auto[4026531840:4160749567]	auto[1]	55	1			T27	1		T6	2		T234	1
auto[4160749568:4294967295]	auto[0]	40	1			T5	1		T6	1		T47	1
auto[4160749568:4294967295]	auto[1]	58	1			T35	1		T6	1		T45	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1472

1

T4

1

T5

1

T44

3

auto[1]

1644

1

T4

1

T5

2

T19

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	102	1			T26	1		T28	1		T6	1
auto[134217728:268435455]	95	1			T6	2		T47	1		T122	1
auto[268435456:402653183]	91	1			T6	1		T52	1		T47	2
auto[402653184:536870911]	86	1			T5	1		T6	3		T52	1
auto[536870912:671088639]	108	1			T44	2		T47	2		T53	1
auto[671088640:805306367]	90	1			T23	1		T275	1		T236	1
auto[805306368:939524095]	97	1			T27	1		T6	3		T232	1
auto[939524096:1073741823]	98	1			T6	2		T50	1		T274	1
auto[1073741824:1207959551]	83	1			T9	1		T6	3		T47	2
auto[1207959552:1342177279]	107	1			T5	1		T26	1		T6	1
auto[1342177280:1476395007]	88	1			T6	1		T234	1		T47	2
auto[1476395008:1610612735]	96	1			T6	3		T52	1		T234	1
auto[1610612736:1744830463]	99	1			T28	1		T6	3		T47	2
auto[1744830464:1879048191]	124	1			T23	1		T27	1		T6	2
auto[1879048192:2013265919]	92	1			T44	1		T23	1		T6	2
auto[2013265920:2147483647]	114	1			T43	1		T27	1		T6	1
auto[2147483648:2281701375]	102	1			T23	1		T27	1		T6	4
auto[2281701376:2415919103]	91	1			T19	1		T26	1		T35	1
auto[2415919104:2550136831]	92	1			T26	1		T6	3		T234	1
auto[2550136832:2684354559]	104	1			T43	1		T23	1		T27	1
auto[2684354560:2818572287]	106	1			T4	1		T6	1		T47	1
auto[2818572288:2952790015]	92	1			T9	1		T6	1		T47	2
auto[2952790016:3087007743]	81	1			T43	1		T52	1		T24	1
auto[3087007744:3221225471]	108	1			T43	1		T6	1		T47	2
auto[3221225472:3355443199]	113	1			T5	1		T6	2		T47	1
auto[3355443200:3489660927]	101	1			T9	1		T6	2		T7	1
auto[3489660928:3623878655]	96	1			T23	1		T6	1		T232	1
auto[3623878656:3758096383]	85	1			T275	1		T45	3		T323	1
auto[3758096384:3892314111]	96	1			T6	2		T234	2		T47	2
auto[3892314112:4026531839]	92	1			T4	1		T236	3		T232	1
auto[4026531840:4160749567]	91	1			T6	3		T52	1		T47	1
auto[4160749568:4294967295]	96	1			T24	1		T238	2		T45	3

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	56	1			T28	1		T6	1		T47	2
auto[0:134217727]	auto[1]	46	1			T26	1		T48	1		T54	1
auto[134217728:268435455]	auto[0]	49	1			T6	1		T45	2		T114	1
auto[134217728:268435455]	auto[1]	46	1			T6	1		T47	1		T122	1
auto[268435456:402653183]	auto[0]	45	1			T6	1		T45	1		T66	1
auto[268435456:402653183]	auto[1]	46	1			T52	1		T47	2		T8	1
auto[402653184:536870911]	auto[0]	35	1			T5	1		T6	3		T52	1
auto[402653184:536870911]	auto[1]	51	1			T24	1		T238	1		T45	1
auto[536870912:671088639]	auto[0]	45	1			T44	2		T47	2		T53	1
auto[536870912:671088639]	auto[1]	63	1			T45	1		T54	1		T51	1
auto[671088640:805306367]	auto[0]	46	1			T23	1		T275	1		T7	1
auto[671088640:805306367]	auto[1]	44	1			T236	1		T45	1		T58	1
auto[805306368:939524095]	auto[0]	41	1			T6	1		T30	1		T45	1
auto[805306368:939524095]	auto[1]	56	1			T27	1		T6	2		T232	1
auto[939524096:1073741823]	auto[0]	38	1			T6	2		T50	1		T292	1
auto[939524096:1073741823]	auto[1]	60	1			T274	1		T45	1		T33	1
auto[1073741824:1207959551]	auto[0]	47	1			T6	2		T47	1		T45	1
auto[1073741824:1207959551]	auto[1]	36	1			T9	1		T6	1		T47	1
auto[1207959552:1342177279]	auto[0]	55	1			T6	1		T47	1		T275	1
auto[1207959552:1342177279]	auto[1]	52	1			T5	1		T26	1		T274	1
auto[1342177280:1476395007]	auto[0]	44	1			T6	1		T47	1		T275	1
auto[1342177280:1476395007]	auto[1]	44	1			T234	1		T47	1		T274	1
auto[1476395008:1610612735]	auto[0]	39	1			T6	2		T52	1		T232	1
auto[1476395008:1610612735]	auto[1]	57	1			T6	1		T234	1		T122	1
auto[1610612736:1744830463]	auto[0]	41	1			T6	2		T45	1		T54	1
auto[1610612736:1744830463]	auto[1]	58	1			T28	1		T6	1		T47	2
auto[1744830464:1879048191]	auto[0]	56	1			T23	1		T50	2		T269	1
auto[1744830464:1879048191]	auto[1]	68	1			T27	1		T6	2		T47	1
auto[1879048192:2013265919]	auto[0]	47	1			T44	1		T23	1		T6	1
auto[1879048192:2013265919]	auto[1]	45	1			T6	1		T47	1		T233	1
auto[2013265920:2147483647]	auto[0]	50	1			T27	1		T6	1		T58	2
auto[2013265920:2147483647]	auto[1]	64	1			T43	1		T47	1		T53	1
auto[2147483648:2281701375]	auto[0]	54	1			T23	1		T27	1		T6	3
auto[2147483648:2281701375]	auto[1]	48	1			T6	1		T234	1		T47	1
auto[2281701376:2415919103]	auto[0]	38	1			T53	1		T45	1		T309	1
auto[2281701376:2415919103]	auto[1]	53	1			T19	1		T26	1		T35	1
auto[2415919104:2550136831]	auto[0]	46	1			T6	2		T47	1		T309	1
auto[2415919104:2550136831]	auto[1]	46	1			T26	1		T6	1		T234	1
auto[2550136832:2684354559]	auto[0]	43	1			T27	1		T6	1		T45	2
auto[2550136832:2684354559]	auto[1]	61	1			T43	1		T23	1		T6	2
auto[2684354560:2818572287]	auto[0]	47	1			T6	1		T45	1		T66	1
auto[2684354560:2818572287]	auto[1]	59	1			T4	1		T47	1		T238	1
auto[2818572288:2952790015]	auto[0]	48	1			T351	1		T58	1		T101	1
auto[2818572288:2952790015]	auto[1]	44	1			T9	1		T6	1		T47	2
auto[2952790016:3087007743]	auto[0]	42	1			T52	1		T45	1		T296	1
auto[2952790016:3087007743]	auto[1]	39	1			T43	1		T24	1		T122	1
auto[3087007744:3221225471]	auto[0]	56	1			T6	1		T47	1		T233	1
auto[3087007744:3221225471]	auto[1]	52	1			T43	1		T47	1		T24	1
auto[3221225472:3355443199]	auto[0]	55	1			T6	1		T47	1		T45	1
auto[3221225472:3355443199]	auto[1]	58	1			T5	1		T6	1		T45	1
auto[3355443200:3489660927]	auto[0]	47	1			T6	1		T7	1		T374	1
auto[3355443200:3489660927]	auto[1]	54	1			T9	1		T6	1		T45	1
auto[3489660928:3623878655]	auto[0]	40	1			T23	1		T7	1		T45	2
auto[3489660928:3623878655]	auto[1]	56	1			T6	1		T232	1		T53	1
auto[3623878656:3758096383]	auto[0]	43	1			T275	1		T45	2		T432	1
auto[3623878656:3758096383]	auto[1]	42	1			T45	1		T323	1		T433	1
auto[3758096384:3892314111]	auto[0]	49	1			T6	2		T234	1		T47	2
auto[3758096384:3892314111]	auto[1]	47	1			T234	1		T274	1		T45	1
auto[3892314112:4026531839]	auto[0]	47	1			T4	1		T236	2		T232	1
auto[3892314112:4026531839]	auto[1]	45	1			T236	1		T45	1		T93	1
auto[4026531840:4160749567]	auto[0]	37	1			T6	1		T47	1		T232	2
auto[4026531840:4160749567]	auto[1]	54	1			T6	2		T52	1		T45	1
auto[4160749568:4294967295]	auto[0]	46	1			T45	1		T58	1		T433	1
auto[4160749568:4294967295]	auto[1]	50	1			T24	1		T238	2		T45	2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1489

1

T4

1

T5

1

T44

1

auto[1]

1625

1

T4

1

T5

2

T19

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	95	1			T27	1		T6	3		T47	2
auto[134217728:268435455]	98	1			T27	1		T6	2		T47	1
auto[268435456:402653183]	91	1			T28	1		T6	3		T52	1
auto[402653184:536870911]	105	1			T5	1		T6	2		T52	2
auto[536870912:671088639]	99	1			T23	1		T6	1		T234	1
auto[671088640:805306367]	108	1			T26	1		T6	1		T234	1
auto[805306368:939524095]	89	1			T44	1		T28	1		T6	1
auto[939524096:1073741823]	101	1			T6	1		T47	2		T24	1
auto[1073741824:1207959551]	97	1			T43	1		T6	1		T30	1
auto[1207959552:1342177279]	105	1			T26	1		T23	1		T6	1
auto[1342177280:1476395007]	93	1			T6	1		T45	2		T324	1
auto[1476395008:1610612735]	95	1			T19	1		T26	2		T6	3
auto[1610612736:1744830463]	96	1			T6	1		T52	1		T234	1
auto[1744830464:1879048191]	112	1			T35	1		T6	4		T236	1
auto[1879048192:2013265919]	99	1			T6	1		T47	1		T122	1
auto[2013265920:2147483647]	90	1			T27	1		T6	1		T52	1
auto[2147483648:2281701375]	87	1			T234	1		T47	2		T323	1
auto[2281701376:2415919103]	91	1			T9	1		T27	1		T6	2
auto[2415919104:2550136831]	92	1			T6	2		T47	2		T232	1
auto[2550136832:2684354559]	108	1			T44	1		T6	1		T47	1
auto[2684354560:2818572287]	89	1			T9	1		T6	3		T47	1
auto[2818572288:2952790015]	96	1			T43	1		T6	1		T47	1
auto[2952790016:3087007743]	97	1			T6	3		T47	3		T269	1
auto[3087007744:3221225471]	94	1			T23	1		T47	3		T236	1
auto[3221225472:3355443199]	87	1			T5	1		T23	1		T6	1
auto[3355443200:3489660927]	93	1			T4	2		T6	1		T50	1
auto[3489660928:3623878655]	125	1			T5	1		T44	1		T9	1
auto[3623878656:3758096383]	87	1			T6	1		T47	2		T236	1
auto[3758096384:3892314111]	104	1			T23	1		T27	1		T234	1
auto[3892314112:4026531839]	87	1			T23	1		T6	1		T50	1
auto[4026531840:4160749567]	107	1			T43	2		T6	7		T47	1
auto[4160749568:4294967295]	97	1			T236	1		T30	1		T7	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	50	1			T27	1		T6	2		T47	1
auto[0:134217727]	auto[1]	45	1			T6	1		T47	1		T274	1
auto[134217728:268435455]	auto[0]	41	1			T27	1		T6	1		T47	1
auto[134217728:268435455]	auto[1]	57	1			T6	1		T45	2		T33	1
auto[268435456:402653183]	auto[0]	44	1			T6	2		T45	1		T58	2
auto[268435456:402653183]	auto[1]	47	1			T28	1		T6	1		T52	1
auto[402653184:536870911]	auto[0]	54	1			T6	1		T52	2		T45	1
auto[402653184:536870911]	auto[1]	51	1			T5	1		T6	1		T24	1
auto[536870912:671088639]	auto[0]	56	1			T6	1		T234	1		T47	1
auto[536870912:671088639]	auto[1]	43	1			T23	1		T47	1		T238	1
auto[671088640:805306367]	auto[0]	51	1			T92	1		T284	1		T217	1
auto[671088640:805306367]	auto[1]	57	1			T26	1		T6	1		T234	1
auto[805306368:939524095]	auto[0]	44	1			T44	1		T28	1		T6	1
auto[805306368:939524095]	auto[1]	45	1			T53	1		T122	1		T45	1
auto[939524096:1073741823]	auto[0]	47	1			T47	1		T122	1		T58	2
auto[939524096:1073741823]	auto[1]	54	1			T6	1		T47	1		T24	1
auto[1073741824:1207959551]	auto[0]	48	1			T6	1		T30	1		T45	1
auto[1073741824:1207959551]	auto[1]	49	1			T43	1		T45	1		T51	1
auto[1207959552:1342177279]	auto[0]	50	1			T23	1		T6	1		T232	2
auto[1207959552:1342177279]	auto[1]	55	1			T26	1		T46	1		T67	1
auto[1342177280:1476395007]	auto[0]	48	1			T45	1		T324	1		T58	3
auto[1342177280:1476395007]	auto[1]	45	1			T6	1		T45	1		T69	1
auto[1476395008:1610612735]	auto[0]	49	1			T6	3		T50	1		T7	1
auto[1476395008:1610612735]	auto[1]	46	1			T19	1		T26	2		T53	1
auto[1610612736:1744830463]	auto[0]	45	1			T52	1		T47	1		T275	1
auto[1610612736:1744830463]	auto[1]	51	1			T6	1		T234	1		T238	2
auto[1744830464:1879048191]	auto[0]	50	1			T6	2		T53	1		T309	1
auto[1744830464:1879048191]	auto[1]	62	1			T35	1		T6	2		T236	1
auto[1879048192:2013265919]	auto[0]	46	1			T45	2		T8	1		T92	1
auto[1879048192:2013265919]	auto[1]	53	1			T6	1		T47	1		T122	1
auto[2013265920:2147483647]	auto[0]	49	1			T6	1		T52	1		T45	1
auto[2013265920:2147483647]	auto[1]	41	1			T27	1		T275	1		T233	1
auto[2147483648:2281701375]	auto[0]	42	1			T47	2		T146	1		T253	1
auto[2147483648:2281701375]	auto[1]	45	1			T234	1		T323	1		T368	1
auto[2281701376:2415919103]	auto[0]	43	1			T6	1		T47	1		T238	1
auto[2281701376:2415919103]	auto[1]	48	1			T9	1		T27	1		T6	1
auto[2415919104:2550136831]	auto[0]	49	1			T6	1		T47	1		T232	1
auto[2415919104:2550136831]	auto[1]	43	1			T6	1		T47	1		T68	1
auto[2550136832:2684354559]	auto[0]	48	1			T6	1		T47	1		T7	1
auto[2550136832:2684354559]	auto[1]	60	1			T44	1		T232	1		T233	1
auto[2684354560:2818572287]	auto[0]	47	1			T6	3		T351	1		T61	2
auto[2684354560:2818572287]	auto[1]	42	1			T9	1		T47	1		T48	1
auto[2818572288:2952790015]	auto[0]	40	1			T7	1		T323	1		T56	2
auto[2818572288:2952790015]	auto[1]	56	1			T43	1		T6	1		T47	1
auto[2952790016:3087007743]	auto[0]	48	1			T6	2		T47	1		T269	1
auto[2952790016:3087007743]	auto[1]	49	1			T6	1		T47	2		T30	1
auto[3087007744:3221225471]	auto[0]	43	1			T23	1		T47	1		T236	1
auto[3087007744:3221225471]	auto[1]	51	1			T47	2		T274	2		T24	1
auto[3221225472:3355443199]	auto[0]	39	1			T23	1		T275	1		T7	1
auto[3221225472:3355443199]	auto[1]	48	1			T5	1		T6	1		T45	2
auto[3355443200:3489660927]	auto[0]	41	1			T4	1		T6	1		T50	1
auto[3355443200:3489660927]	auto[1]	52	1			T4	1		T236	1		T45	1
auto[3489660928:3623878655]	auto[0]	60	1			T5	1		T6	2		T232	1
auto[3489660928:3623878655]	auto[1]	65	1			T44	1		T9	1		T47	2
auto[3623878656:3758096383]	auto[0]	42	1			T6	1		T47	1		T236	1
auto[3623878656:3758096383]	auto[1]	45	1			T47	1		T122	1		T238	1
auto[3758096384:3892314111]	auto[0]	43	1			T23	1		T234	1		T47	1
auto[3758096384:3892314111]	auto[1]	61	1			T27	1		T274	1		T233	1
auto[3892314112:4026531839]	auto[0]	45	1			T23	1		T6	1		T50	1
auto[3892314112:4026531839]	auto[1]	42	1			T24	1		T233	1		T122	1
auto[4026531840:4160749567]	auto[0]	47	1			T6	3		T47	1		T351	1
auto[4026531840:4160749567]	auto[1]	60	1			T43	2		T6	4		T54	1
auto[4160749568:4294967295]	auto[0]	40	1			T7	1		T45	1		T374	1
auto[4160749568:4294967295]	auto[1]	57	1			T236	1		T30	1		T45	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1490

1

T4

1

T5

1

T43

1

auto[1]

1624

1

T4

1

T5

2

T19

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	100	1			T6	1		T274	2		T7	1
auto[134217728:268435455]	85	1			T44	2		T6	2		T234	1
auto[268435456:402653183]	115	1			T6	1		T50	1		T47	2
auto[402653184:536870911]	97	1			T6	1		T233	1		T45	1
auto[536870912:671088639]	96	1			T6	2		T122	1		T238	1
auto[671088640:805306367]	99	1			T26	1		T50	1		T275	1
auto[805306368:939524095]	93	1			T6	4		T236	1		T45	1
auto[939524096:1073741823]	92	1			T43	1		T6	2		T47	1
auto[1073741824:1207959551]	89	1			T26	1		T27	1		T6	3
auto[1207959552:1342177279]	94	1			T43	1		T44	1		T27	1
auto[1342177280:1476395007]	96	1			T23	1		T6	3		T274	1
auto[1476395008:1610612735]	86	1			T4	1		T6	1		T47	1
auto[1610612736:1744830463]	96	1			T26	1		T6	1		T47	4
auto[1744830464:1879048191]	89	1			T43	1		T6	4		T232	1
auto[1879048192:2013265919]	96	1			T6	2		T234	1		T232	1
auto[2013265920:2147483647]	99	1			T6	2		T52	1		T47	1
auto[2147483648:2281701375]	108	1			T5	1		T35	1		T27	1
auto[2281701376:2415919103]	100	1			T28	1		T23	1		T6	1
auto[2415919104:2550136831]	93	1			T23	1		T27	1		T6	2
auto[2550136832:2684354559]	88	1			T6	3		T47	1		T275	1
auto[2684354560:2818572287]	75	1			T47	1		T275	1		T24	1
auto[2818572288:2952790015]	94	1			T23	1		T9	1		T6	1
auto[2952790016:3087007743]	107	1			T4	1		T43	1		T6	1
auto[3087007744:3221225471]	109	1			T19	1		T9	2		T6	2
auto[3221225472:3355443199]	104	1			T6	3		T232	1		T53	1
auto[3355443200:3489660927]	92	1			T50	1		T47	2		T238	1
auto[3489660928:3623878655]	92	1			T5	1		T28	1		T6	2
auto[3623878656:3758096383]	103	1			T5	1		T26	1		T23	1
auto[3758096384:3892314111]	114	1			T234	1		T47	1		T53	1
auto[3892314112:4026531839]	104	1			T27	1		T6	1		T236	1
auto[4026531840:4160749567]	110	1			T23	1		T6	1		T52	1
auto[4160749568:4294967295]	99	1			T6	1		T323	1		T368	1