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Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2753 1 T4 2 T5 3 T19 1
auto[1] 283 1 T35 6 T122 4 T123 2


Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] 100 1 T27 1 T6 1 T234 1
auto[134217728:268435455] 112 1 T19 1 T23 1 T9 1
auto[268435456:402653183] 101 1 T35 1 T6 2 T47 2
auto[402653184:536870911] 85 1 T44 1 T6 2 T232 1
auto[536870912:671088639] 102 1 T27 1 T6 1 T275 1
auto[671088640:805306367] 82 1 T35 2 T27 1 T7 1
auto[805306368:939524095] 90 1 T47 1 T275 2 T238 1
auto[939524096:1073741823] 97 1 T4 1 T43 1 T27 1
auto[1073741824:1207959551] 80 1 T26 1 T43 1 T47 2
auto[1207959552:1342177279] 89 1 T23 1 T6 1 T236 1
auto[1342177280:1476395007] 96 1 T43 1 T6 1 T47 1
auto[1476395008:1610612735] 94 1 T28 1 T52 1 T234 1
auto[1610612736:1744830463] 101 1 T9 1 T6 2 T63 1
auto[1744830464:1879048191] 96 1 T6 1 T236 1 T53 1
auto[1879048192:2013265919] 98 1 T23 1 T6 1 T47 1
auto[2013265920:2147483647] 118 1 T43 1 T6 4 T52 1
auto[2147483648:2281701375] 93 1 T5 1 T6 2 T47 3
auto[2281701376:2415919103] 85 1 T26 1 T44 1 T232 1
auto[2415919104:2550136831] 90 1 T232 1 T122 1 T45 2
auto[2550136832:2684354559] 102 1 T234 1 T47 1 T45 2
auto[2684354560:2818572287] 96 1 T5 1 T9 1 T47 1
auto[2818572288:2952790015] 98 1 T4 1 T6 2 T47 1
auto[2952790016:3087007743] 97 1 T28 1 T45 4 T54 1
auto[3087007744:3221225471] 78 1 T5 1 T23 1 T6 2
auto[3221225472:3355443199] 92 1 T26 1 T6 1 T47 1
auto[3355443200:3489660927] 102 1 T23 1 T47 4 T232 1
auto[3489660928:3623878655] 102 1 T23 1 T269 1 T122 1
auto[3623878656:3758096383] 89 1 T6 1 T51 1 T58 2
auto[3758096384:3892314111] 100 1 T26 1 T35 1 T274 1
auto[3892314112:4026531839] 93 1 T35 2 T6 2 T234 1
auto[4026531840:4160749567] 97 1 T35 1 T234 1 T236 1
auto[4160749568:4294967295] 81 1 T44 1 T27 1 T236 1


Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cpregwen_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] auto[0] 88 1 T27 1 T6 1 T234 1
auto[0:134217727] auto[1] 12 1 T216 1 T349 1 T359 1
auto[134217728:268435455] auto[0] 104 1 T19 1 T23 1 T9 1
auto[134217728:268435455] auto[1] 8 1 T123 1 T155 1 T215 1
auto[268435456:402653183] auto[0] 92 1 T35 1 T6 2 T47 2
auto[268435456:402653183] auto[1] 9 1 T414 1 T439 1 T431 2
auto[402653184:536870911] auto[0] 81 1 T44 1 T6 2 T232 1
auto[402653184:536870911] auto[1] 4 1 T359 1 T414 1 T306 1
auto[536870912:671088639] auto[0] 92 1 T27 1 T6 1 T275 1
auto[536870912:671088639] auto[1] 10 1 T215 1 T216 1 T430 1
auto[671088640:805306367] auto[0] 70 1 T27 1 T7 1 T45 1
auto[671088640:805306367] auto[1] 12 1 T35 2 T216 1 T401 1
auto[805306368:939524095] auto[0] 85 1 T47 1 T275 2 T238 1
auto[805306368:939524095] auto[1] 5 1 T413 1 T365 1 T361 1
auto[939524096:1073741823] auto[0] 89 1 T4 1 T43 1 T27 1
auto[939524096:1073741823] auto[1] 8 1 T122 1 T266 1 T316 2
auto[1073741824:1207959551] auto[0] 70 1 T26 1 T43 1 T47 2
auto[1073741824:1207959551] auto[1] 10 1 T401 1 T359 1 T266 1
auto[1207959552:1342177279] auto[0] 75 1 T23 1 T6 1 T236 1
auto[1207959552:1342177279] auto[1] 14 1 T216 1 T401 1 T291 2
auto[1342177280:1476395007] auto[0] 86 1 T43 1 T6 1 T47 1
auto[1342177280:1476395007] auto[1] 10 1 T155 1 T359 1 T306 1
auto[1476395008:1610612735] auto[0] 85 1 T28 1 T52 1 T234 1
auto[1476395008:1610612735] auto[1] 9 1 T401 1 T316 1 T365 1
auto[1610612736:1744830463] auto[0] 94 1 T9 1 T6 2 T63 1
auto[1610612736:1744830463] auto[1] 7 1 T216 1 T291 1 T412 1
auto[1744830464:1879048191] auto[0] 88 1 T6 1 T236 1 T53 1
auto[1744830464:1879048191] auto[1] 8 1 T401 1 T359 1 T159 1
auto[1879048192:2013265919] auto[0] 85 1 T23 1 T6 1 T47 1
auto[1879048192:2013265919] auto[1] 13 1 T123 1 T215 1 T216 1
auto[2013265920:2147483647] auto[0] 105 1 T43 1 T6 4 T52 1
auto[2013265920:2147483647] auto[1] 13 1 T212 1 T216 1 T266 2
auto[2147483648:2281701375] auto[0] 76 1 T5 1 T6 2 T47 3
auto[2147483648:2281701375] auto[1] 17 1 T159 1 T107 1 T337 1
auto[2281701376:2415919103] auto[0] 83 1 T26 1 T44 1 T232 1
auto[2281701376:2415919103] auto[1] 2 1 T316 1 T439 1 - -
auto[2415919104:2550136831] auto[0] 84 1 T232 1 T45 2 T324 1
auto[2415919104:2550136831] auto[1] 6 1 T122 1 T365 1 T361 1
auto[2550136832:2684354559] auto[0] 89 1 T234 1 T47 1 T45 2
auto[2550136832:2684354559] auto[1] 13 1 T156 1 T401 1 T291 1
auto[2684354560:2818572287] auto[0] 87 1 T5 1 T9 1 T47 1
auto[2684354560:2818572287] auto[1] 9 1 T122 1 T212 1 T430 1
auto[2818572288:2952790015] auto[0] 85 1 T4 1 T6 2 T47 1
auto[2818572288:2952790015] auto[1] 13 1 T337 1 T411 1 T365 1
auto[2952790016:3087007743] auto[0] 91 1 T28 1 T45 4 T54 1
auto[2952790016:3087007743] auto[1] 6 1 T401 1 T396 1 T365 1
auto[3087007744:3221225471] auto[0] 68 1 T5 1 T23 1 T6 2
auto[3087007744:3221225471] auto[1] 10 1 T414 2 T306 1 T411 1
auto[3221225472:3355443199] auto[0] 87 1 T26 1 T6 1 T47 1
auto[3221225472:3355443199] auto[1] 5 1 T212 1 T216 1 T337 1
auto[3355443200:3489660927] auto[0] 99 1 T23 1 T47 4 T232 1
auto[3355443200:3489660927] auto[1] 3 1 T411 1 T443 1 T442 1
auto[3489660928:3623878655] auto[0] 95 1 T23 1 T269 1 T30 1
auto[3489660928:3623878655] auto[1] 7 1 T122 1 T216 1 T359 1
auto[3623878656:3758096383] auto[0] 82 1 T6 1 T51 1 T58 2
auto[3623878656:3758096383] auto[1] 7 1 T107 1 T306 1 T267 1
auto[3758096384:3892314111] auto[0] 91 1 T26 1 T274 1 T238 1
auto[3758096384:3892314111] auto[1] 9 1 T35 1 T430 1 T159 2
auto[3892314112:4026531839] auto[0] 88 1 T6 2 T234 1 T47 1
auto[3892314112:4026531839] auto[1] 5 1 T35 2 T266 1 T443 1
auto[4026531840:4160749567] auto[0] 90 1 T234 1 T236 1 T53 1
auto[4026531840:4160749567] auto[1] 7 1 T35 1 T212 1 T365 2
auto[4160749568:4294967295] auto[0] 69 1 T44 1 T27 1 T236 1
auto[4160749568:4294967295] auto[1] 12 1 T401 2 T266 1 T337 1

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