Unified Coverage Report :: Group Instance : key_version

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

6509

1

T4

4

T5

7

T19

1

auto[1]

305

1

T35

8

T122

3

T123

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	2731	1			T4	1		T5	3		T26	8
auto[134217728:268435455]	156	1			T5	1		T35	1		T27	2
auto[268435456:402653183]	162	1			T44	1		T23	1		T9	1
auto[402653184:536870911]	155	1			T4	1		T19	1		T35	1
auto[536870912:671088639]	128	1			T35	1		T23	1		T6	4
auto[671088640:805306367]	115	1			T6	1		T47	1		T233	1
auto[805306368:939524095]	123	1			T43	2		T23	1		T47	1
auto[939524096:1073741823]	138	1			T26	1		T43	1		T23	2
auto[1073741824:1207959551]	133	1			T44	1		T23	1		T27	1
auto[1207959552:1342177279]	113	1			T6	1		T47	2		T232	2
auto[1342177280:1476395007]	133	1			T9	1		T47	2		T24	1
auto[1476395008:1610612735]	146	1			T28	1		T27	1		T6	1
auto[1610612736:1744830463]	137	1			T4	1		T6	1		T234	1
auto[1744830464:1879048191]	112	1			T26	1		T43	1		T27	1
auto[1879048192:2013265919]	133	1			T6	3		T275	1		T232	1
auto[2013265920:2147483647]	138	1			T26	1		T6	2		T47	3
auto[2147483648:2281701375]	119	1			T27	1		T6	1		T47	1
auto[2281701376:2415919103]	144	1			T35	1		T27	2		T6	4
auto[2415919104:2550136831]	122	1			T5	1		T27	1		T6	2
auto[2550136832:2684354559]	126	1			T6	2		T47	4		T274	1
auto[2684354560:2818572287]	130	1			T27	1		T6	2		T47	1
auto[2818572288:2952790015]	136	1			T26	2		T35	1		T23	1
auto[2952790016:3087007743]	131	1			T44	1		T27	2		T234	1
auto[3087007744:3221225471]	133	1			T35	1		T6	5		T236	1
auto[3221225472:3355443199]	136	1			T35	1		T23	1		T47	3
auto[3355443200:3489660927]	116	1			T26	1		T23	1		T27	1
auto[3489660928:3623878655]	131	1			T5	1		T6	2		T47	1
auto[3623878656:3758096383]	130	1			T26	1		T35	1		T6	1
auto[3758096384:3892314111]	137	1			T4	1		T26	1		T24	1
auto[3892314112:4026531839]	120	1			T23	1		T47	1		T45	4
auto[4026531840:4160749567]	123	1			T5	1		T28	1		T27	1
auto[4160749568:4294967295]	127	1			T26	2		T6	2		T47	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	2719	1			T4	1		T5	3		T26	8
auto[0:134217727]	auto[1]	12	1			T35	1		T291	1		T306	1
auto[134217728:268435455]	auto[0]	146	1			T5	1		T27	2		T6	1
auto[134217728:268435455]	auto[1]	10	1			T35	1		T430	1		T156	1
auto[268435456:402653183]	auto[0]	148	1			T44	1		T23	1		T9	1
auto[268435456:402653183]	auto[1]	14	1			T216	1		T401	1		T266	1
auto[402653184:536870911]	auto[0]	145	1			T4	1		T19	1		T35	1
auto[402653184:536870911]	auto[1]	10	1			T401	1		T316	1		T267	1
auto[536870912:671088639]	auto[0]	121	1			T23	1		T6	4		T47	2
auto[536870912:671088639]	auto[1]	7	1			T35	1		T401	1		T159	1
auto[671088640:805306367]	auto[0]	109	1			T6	1		T47	1		T233	1
auto[671088640:805306367]	auto[1]	6	1			T122	1		T337	1		T365	1
auto[805306368:939524095]	auto[0]	112	1			T43	2		T23	1		T47	1
auto[805306368:939524095]	auto[1]	11	1			T216	1		T349	1		T337	1
auto[939524096:1073741823]	auto[0]	123	1			T26	1		T43	1		T23	2
auto[939524096:1073741823]	auto[1]	15	1			T430	1		T414	4		T159	1
auto[1073741824:1207959551]	auto[0]	126	1			T44	1		T23	1		T27	1
auto[1073741824:1207959551]	auto[1]	7	1			T216	1		T291	1		T337	1
auto[1207959552:1342177279]	auto[0]	104	1			T6	1		T47	2		T232	2
auto[1207959552:1342177279]	auto[1]	9	1			T359	1		T414	1		T159	1
auto[1342177280:1476395007]	auto[0]	129	1			T9	1		T47	2		T24	1
auto[1342177280:1476395007]	auto[1]	4	1			T414	1		T266	1		T316	1
auto[1476395008:1610612735]	auto[0]	132	1			T28	1		T27	1		T6	1
auto[1476395008:1610612735]	auto[1]	14	1			T155	1		T430	1		T401	1
auto[1610612736:1744830463]	auto[0]	127	1			T4	1		T6	1		T234	1
auto[1610612736:1744830463]	auto[1]	10	1			T215	1		T401	1		T291	1
auto[1744830464:1879048191]	auto[0]	107	1			T26	1		T43	1		T27	1
auto[1744830464:1879048191]	auto[1]	5	1			T122	1		T359	1		T378	1
auto[1879048192:2013265919]	auto[0]	128	1			T6	3		T275	1		T232	1
auto[1879048192:2013265919]	auto[1]	5	1			T359	1		T414	1		T435	1
auto[2013265920:2147483647]	auto[0]	131	1			T26	1		T6	2		T47	3
auto[2013265920:2147483647]	auto[1]	7	1			T122	1		T401	1		T266	2
auto[2147483648:2281701375]	auto[0]	108	1			T27	1		T6	1		T47	1
auto[2147483648:2281701375]	auto[1]	11	1			T430	1		T359	1		T414	1
auto[2281701376:2415919103]	auto[0]	138	1			T27	2		T6	4		T47	3
auto[2281701376:2415919103]	auto[1]	6	1			T35	1		T156	1		T266	2
auto[2415919104:2550136831]	auto[0]	115	1			T5	1		T27	1		T6	2
auto[2415919104:2550136831]	auto[1]	7	1			T107	1		T306	1		T411	1
auto[2550136832:2684354559]	auto[0]	114	1			T6	2		T47	4		T274	1
auto[2550136832:2684354559]	auto[1]	12	1			T156	1		T401	1		T414	1
auto[2684354560:2818572287]	auto[0]	113	1			T27	1		T6	2		T47	1
auto[2684354560:2818572287]	auto[1]	17	1			T156	1		T401	1		T291	1
auto[2818572288:2952790015]	auto[0]	126	1			T26	2		T23	1		T9	1
auto[2818572288:2952790015]	auto[1]	10	1			T35	1		T216	1		T349	1
auto[2952790016:3087007743]	auto[0]	124	1			T44	1		T27	2		T234	1
auto[2952790016:3087007743]	auto[1]	7	1			T123	1		T401	1		T159	1
auto[3087007744:3221225471]	auto[0]	122	1			T6	5		T236	1		T232	1
auto[3087007744:3221225471]	auto[1]	11	1			T35	1		T401	1		T291	1
auto[3221225472:3355443199]	auto[0]	129	1			T23	1		T47	3		T53	1
auto[3221225472:3355443199]	auto[1]	7	1			T35	1		T401	1		T349	1
auto[3355443200:3489660927]	auto[0]	109	1			T26	1		T23	1		T27	1
auto[3355443200:3489660927]	auto[1]	7	1			T414	2		T107	2		T271	1
auto[3489660928:3623878655]	auto[0]	119	1			T5	1		T6	2		T47	1
auto[3489660928:3623878655]	auto[1]	12	1			T216	1		T414	2		T306	1
auto[3623878656:3758096383]	auto[0]	115	1			T26	1		T6	1		T52	1
auto[3623878656:3758096383]	auto[1]	15	1			T35	1		T216	1		T401	3
auto[3758096384:3892314111]	auto[0]	128	1			T4	1		T26	1		T24	1
auto[3758096384:3892314111]	auto[1]	9	1			T216	1		T401	1		T107	2
auto[3892314112:4026531839]	auto[0]	105	1			T23	1		T47	1		T45	4
auto[3892314112:4026531839]	auto[1]	15	1			T430	1		T401	1		T291	1
auto[4026531840:4160749567]	auto[0]	114	1			T5	1		T28	1		T27	1
auto[4026531840:4160749567]	auto[1]	9	1			T123	1		T359	1		T159	1
auto[4160749568:4294967295]	auto[0]	123	1			T26	2		T6	2		T47	1
auto[4160749568:4294967295]	auto[1]	4	1			T291	1		T283	1		T436	1