Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.81 99.07 98.03 98.30 100.00 99.11 98.41 91.76


Total test records in report: 1064
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T1007 /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.1779869057 Mar 12 01:05:18 PM PDT 24 Mar 12 01:05:20 PM PDT 24 299220752 ps
T1008 /workspace/coverage/cover_reg_top/48.keymgr_intr_test.3631845296 Mar 12 01:05:54 PM PDT 24 Mar 12 01:05:55 PM PDT 24 11397899 ps
T1009 /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.489065137 Mar 12 01:05:29 PM PDT 24 Mar 12 01:05:31 PM PDT 24 78009844 ps
T1010 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.158191080 Mar 12 01:05:19 PM PDT 24 Mar 12 01:05:29 PM PDT 24 3747379766 ps
T1011 /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.982206904 Mar 12 01:05:35 PM PDT 24 Mar 12 01:05:38 PM PDT 24 149055916 ps
T1012 /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.3976277013 Mar 12 01:05:28 PM PDT 24 Mar 12 01:05:34 PM PDT 24 297627397 ps
T186 /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.4029627131 Mar 12 01:05:22 PM PDT 24 Mar 12 01:05:31 PM PDT 24 1596073923 ps
T1013 /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.3882710296 Mar 12 01:05:37 PM PDT 24 Mar 12 01:05:39 PM PDT 24 149953707 ps
T1014 /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.2730477337 Mar 12 01:05:19 PM PDT 24 Mar 12 01:05:26 PM PDT 24 499235730 ps
T1015 /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.1549596358 Mar 12 01:05:19 PM PDT 24 Mar 12 01:05:21 PM PDT 24 116015939 ps
T176 /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.3801534961 Mar 12 01:05:32 PM PDT 24 Mar 12 01:06:52 PM PDT 24 22991867613 ps
T1016 /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.926954594 Mar 12 01:05:33 PM PDT 24 Mar 12 01:05:35 PM PDT 24 29450961 ps
T1017 /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.3169005810 Mar 12 01:05:18 PM PDT 24 Mar 12 01:05:19 PM PDT 24 54252347 ps
T1018 /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.49506280 Mar 12 01:05:13 PM PDT 24 Mar 12 01:05:15 PM PDT 24 14263912 ps
T1019 /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.1664027744 Mar 12 01:05:25 PM PDT 24 Mar 12 01:05:28 PM PDT 24 36759159 ps
T1020 /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.2272401441 Mar 12 01:05:37 PM PDT 24 Mar 12 01:05:38 PM PDT 24 37588442 ps
T405 /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.2766312969 Mar 12 01:05:05 PM PDT 24 Mar 12 01:05:15 PM PDT 24 919863386 ps
T1021 /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.158110476 Mar 12 01:05:16 PM PDT 24 Mar 12 01:05:18 PM PDT 24 84456500 ps
T1022 /workspace/coverage/cover_reg_top/27.keymgr_intr_test.2437889469 Mar 12 01:05:34 PM PDT 24 Mar 12 01:05:36 PM PDT 24 36931510 ps
T1023 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.1119948105 Mar 12 01:05:29 PM PDT 24 Mar 12 01:05:39 PM PDT 24 173712029 ps
T1024 /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.3141560485 Mar 12 01:05:05 PM PDT 24 Mar 12 01:05:09 PM PDT 24 134388541 ps
T1025 /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.982294104 Mar 12 01:05:30 PM PDT 24 Mar 12 01:05:35 PM PDT 24 171415788 ps
T1026 /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.3496198193 Mar 12 01:05:20 PM PDT 24 Mar 12 01:05:22 PM PDT 24 15155593 ps
T1027 /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.1470594512 Mar 12 01:05:34 PM PDT 24 Mar 12 01:05:37 PM PDT 24 333903558 ps
T1028 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.1991872169 Mar 12 01:05:25 PM PDT 24 Mar 12 01:05:28 PM PDT 24 214859859 ps
T1029 /workspace/coverage/cover_reg_top/40.keymgr_intr_test.3625373448 Mar 12 01:05:45 PM PDT 24 Mar 12 01:05:46 PM PDT 24 12183363 ps
T1030 /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.3241248128 Mar 12 01:05:06 PM PDT 24 Mar 12 01:05:10 PM PDT 24 261963163 ps
T1031 /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.4094694775 Mar 12 01:05:33 PM PDT 24 Mar 12 01:05:35 PM PDT 24 142535627 ps
T1032 /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.2884008923 Mar 12 01:05:13 PM PDT 24 Mar 12 01:05:18 PM PDT 24 396417306 ps
T1033 /workspace/coverage/cover_reg_top/35.keymgr_intr_test.1836559979 Mar 12 01:05:49 PM PDT 24 Mar 12 01:05:50 PM PDT 24 37602669 ps
T406 /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.1741784486 Mar 12 01:05:18 PM PDT 24 Mar 12 01:05:25 PM PDT 24 287876055 ps
T1034 /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.1491768429 Mar 12 01:05:13 PM PDT 24 Mar 12 01:05:15 PM PDT 24 371016507 ps
T1035 /workspace/coverage/cover_reg_top/43.keymgr_intr_test.4196794140 Mar 12 01:05:49 PM PDT 24 Mar 12 01:05:50 PM PDT 24 13165171 ps
T1036 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.3771511525 Mar 12 01:05:17 PM PDT 24 Mar 12 01:05:22 PM PDT 24 702291812 ps
T1037 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.262965019 Mar 12 01:05:31 PM PDT 24 Mar 12 01:05:47 PM PDT 24 2525295066 ps
T1038 /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.871873274 Mar 12 01:05:13 PM PDT 24 Mar 12 01:05:28 PM PDT 24 673540124 ps
T1039 /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.606155530 Mar 12 01:05:34 PM PDT 24 Mar 12 01:05:36 PM PDT 24 96150413 ps
T1040 /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.3165796091 Mar 12 01:05:09 PM PDT 24 Mar 12 01:05:13 PM PDT 24 270603419 ps
T1041 /workspace/coverage/cover_reg_top/17.keymgr_intr_test.1547692210 Mar 12 01:05:34 PM PDT 24 Mar 12 01:05:36 PM PDT 24 34761443 ps
T1042 /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.3616996448 Mar 12 01:05:07 PM PDT 24 Mar 12 01:05:09 PM PDT 24 142988663 ps
T1043 /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.4172880648 Mar 12 01:05:29 PM PDT 24 Mar 12 01:05:34 PM PDT 24 279268050 ps
T1044 /workspace/coverage/cover_reg_top/13.keymgr_intr_test.2747627200 Mar 12 01:05:32 PM PDT 24 Mar 12 01:05:34 PM PDT 24 43368633 ps
T1045 /workspace/coverage/cover_reg_top/6.keymgr_intr_test.3400636928 Mar 12 01:05:18 PM PDT 24 Mar 12 01:05:19 PM PDT 24 10391469 ps
T1046 /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.533321975 Mar 12 01:05:28 PM PDT 24 Mar 12 01:05:29 PM PDT 24 65796476 ps
T175 /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.2944509950 Mar 12 01:05:02 PM PDT 24 Mar 12 01:05:12 PM PDT 24 337313889 ps
T1047 /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.796861906 Mar 12 01:05:33 PM PDT 24 Mar 12 01:05:39 PM PDT 24 151826982 ps
T1048 /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.3357691127 Mar 12 01:05:12 PM PDT 24 Mar 12 01:05:17 PM PDT 24 694972876 ps
T1049 /workspace/coverage/cover_reg_top/0.keymgr_intr_test.1061415575 Mar 12 01:05:05 PM PDT 24 Mar 12 01:05:06 PM PDT 24 35162505 ps
T1050 /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.2476620495 Mar 12 01:05:29 PM PDT 24 Mar 12 01:05:32 PM PDT 24 281905459 ps
T1051 /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.1960015648 Mar 12 01:05:29 PM PDT 24 Mar 12 01:05:32 PM PDT 24 73055071 ps
T1052 /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.739139055 Mar 12 01:05:17 PM PDT 24 Mar 12 01:05:19 PM PDT 24 97564119 ps
T1053 /workspace/coverage/cover_reg_top/37.keymgr_intr_test.2157115522 Mar 12 01:05:46 PM PDT 24 Mar 12 01:05:47 PM PDT 24 46529969 ps
T1054 /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.40135349 Mar 12 01:05:22 PM PDT 24 Mar 12 01:05:24 PM PDT 24 204141852 ps
T1055 /workspace/coverage/cover_reg_top/45.keymgr_intr_test.3427142892 Mar 12 01:05:52 PM PDT 24 Mar 12 01:05:53 PM PDT 24 42376140 ps
T1056 /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.3770278587 Mar 12 01:05:36 PM PDT 24 Mar 12 01:05:37 PM PDT 24 46731700 ps
T1057 /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.2708796608 Mar 12 01:05:34 PM PDT 24 Mar 12 01:05:43 PM PDT 24 165028681 ps
T1058 /workspace/coverage/cover_reg_top/32.keymgr_intr_test.2961086301 Mar 12 01:05:51 PM PDT 24 Mar 12 01:05:52 PM PDT 24 30405814 ps
T1059 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.1449084953 Mar 12 01:05:36 PM PDT 24 Mar 12 01:05:39 PM PDT 24 576690908 ps
T1060 /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.1577299374 Mar 12 01:05:22 PM PDT 24 Mar 12 01:05:25 PM PDT 24 673092773 ps
T178 /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.2700203938 Mar 12 01:05:32 PM PDT 24 Mar 12 01:05:43 PM PDT 24 254402724 ps
T1061 /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.391911433 Mar 12 01:05:10 PM PDT 24 Mar 12 01:05:22 PM PDT 24 256921603 ps
T1062 /workspace/coverage/cover_reg_top/25.keymgr_intr_test.3596213393 Mar 12 01:05:33 PM PDT 24 Mar 12 01:05:35 PM PDT 24 27224154 ps
T1063 /workspace/coverage/cover_reg_top/34.keymgr_intr_test.3974866796 Mar 12 01:05:43 PM PDT 24 Mar 12 01:05:44 PM PDT 24 13762280 ps
T1064 /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.2024309897 Mar 12 01:05:33 PM PDT 24 Mar 12 01:05:42 PM PDT 24 414874719 ps

Test location /workspace/coverage/default/19.keymgr_custom_cm.2626260396
Short name T19
Test name
Test status
Simulation time 139621794 ps
CPU time 6.64 seconds
Started Mar 12 01:56:54 PM PDT 24
Finished Mar 12 01:57:00 PM PDT 24
Peak memory 216908 kb
Host smart-dad8e7a4-26e6-4f42-aef9-d49f2f30519e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2626260396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.2626260396
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.1226880745
Short name T6
Test name
Test status
Simulation time 6890402543 ps
CPU time 202.3 seconds
Started Mar 12 01:56:25 PM PDT 24
Finished Mar 12 01:59:48 PM PDT 24
Peak memory 217444 kb
Host smart-45a83c2f-1e1e-4da8-be1d-c49183d892ea
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226880745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.1226880745
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.93110781
Short name T26
Test name
Test status
Simulation time 101920121 ps
CPU time 5.17 seconds
Started Mar 12 01:57:05 PM PDT 24
Finished Mar 12 01:57:12 PM PDT 24
Peak memory 209380 kb
Host smart-f4a6220d-6a02-408e-b978-122a6e89781f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93110781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.93110781
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.2494178067
Short name T45
Test name
Test status
Simulation time 28088672721 ps
CPU time 99.42 seconds
Started Mar 12 01:57:25 PM PDT 24
Finished Mar 12 01:59:04 PM PDT 24
Peak memory 222740 kb
Host smart-6b5ccc43-0f41-47a5-ba9a-9b38e2524aac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494178067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.2494178067
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.2703888665
Short name T13
Test name
Test status
Simulation time 270158619 ps
CPU time 9.15 seconds
Started Mar 12 01:55:01 PM PDT 24
Finished Mar 12 01:55:11 PM PDT 24
Peak memory 231504 kb
Host smart-b5de8543-c9d5-4eac-98b2-4d3283f4b9e7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703888665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.2703888665
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/29.keymgr_stress_all_with_rand_reset.385711540
Short name T134
Test name
Test status
Simulation time 905431463 ps
CPU time 13.17 seconds
Started Mar 12 01:58:03 PM PDT 24
Finished Mar 12 01:58:16 PM PDT 24
Peak memory 222824 kb
Host smart-a3f3d7ac-5b0c-4dc7-ac4f-0260878d9382
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385711540 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all_with_rand_reset.385711540
Directory /workspace/29.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.161176039
Short name T47
Test name
Test status
Simulation time 5349898245 ps
CPU time 62.91 seconds
Started Mar 12 01:54:24 PM PDT 24
Finished Mar 12 01:55:28 PM PDT 24
Peak memory 215824 kb
Host smart-4907794d-49ca-40e3-9da9-22da54dcba5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161176039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.161176039
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.2771964817
Short name T165
Test name
Test status
Simulation time 124706272 ps
CPU time 4.72 seconds
Started Mar 12 01:57:24 PM PDT 24
Finished Mar 12 01:57:29 PM PDT 24
Peak memory 217536 kb
Host smart-ee5be114-c986-462a-93d6-b7d27305bd65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2771964817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.2771964817
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.965589683
Short name T58
Test name
Test status
Simulation time 8608564084 ps
CPU time 73.69 seconds
Started Mar 12 01:56:17 PM PDT 24
Finished Mar 12 01:57:31 PM PDT 24
Peak memory 222808 kb
Host smart-43677713-a189-4ddb-82e5-1824493ef65d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965589683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.965589683
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.1871160111
Short name T216
Test name
Test status
Simulation time 3265057829 ps
CPU time 46.29 seconds
Started Mar 12 01:54:42 PM PDT 24
Finished Mar 12 01:55:29 PM PDT 24
Peak memory 215376 kb
Host smart-32bff781-34c6-4dad-b4c3-11c0f30bece9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1871160111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.1871160111
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.582567174
Short name T128
Test name
Test status
Simulation time 233035726 ps
CPU time 9.48 seconds
Started Mar 12 01:05:15 PM PDT 24
Finished Mar 12 01:05:25 PM PDT 24
Peak memory 214416 kb
Host smart-db129876-d7cd-43c5-bbff-2bf4ada4b14c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=582567174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.k
eymgr_shadow_reg_errors_with_csr_rw.582567174
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.2842272119
Short name T49
Test name
Test status
Simulation time 3991839397 ps
CPU time 79.75 seconds
Started Mar 12 01:59:01 PM PDT 24
Finished Mar 12 02:00:21 PM PDT 24
Peak memory 221032 kb
Host smart-1119dc97-84ce-4645-8e1e-f6c0efcaeb61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842272119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.2842272119
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.1023638987
Short name T365
Test name
Test status
Simulation time 1851928737 ps
CPU time 51.15 seconds
Started Mar 12 01:58:27 PM PDT 24
Finished Mar 12 01:59:19 PM PDT 24
Peak memory 215264 kb
Host smart-e1afc794-3e9b-4717-964e-d147f09f9db1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1023638987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.1023638987
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.1053924735
Short name T23
Test name
Test status
Simulation time 383435854 ps
CPU time 4.77 seconds
Started Mar 12 01:59:02 PM PDT 24
Finished Mar 12 01:59:07 PM PDT 24
Peak memory 210596 kb
Host smart-7b4e9174-fca7-4ea2-8271-1ec849358ff3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053924735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.1053924735
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.27353035
Short name T36
Test name
Test status
Simulation time 41784195 ps
CPU time 1.58 seconds
Started Mar 12 01:55:15 PM PDT 24
Finished Mar 12 01:55:17 PM PDT 24
Peak memory 209500 kb
Host smart-36b4c1f2-a56b-4f4a-8d9c-589597ad6c89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=27353035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.27353035
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.562280406
Short name T359
Test name
Test status
Simulation time 3351045649 ps
CPU time 47.58 seconds
Started Mar 12 01:54:31 PM PDT 24
Finished Mar 12 01:55:19 PM PDT 24
Peak memory 216584 kb
Host smart-614329aa-a860-4005-bac6-00aaa5219ab2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=562280406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.562280406
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.1992906370
Short name T61
Test name
Test status
Simulation time 16138264703 ps
CPU time 49.41 seconds
Started Mar 12 01:56:57 PM PDT 24
Finished Mar 12 01:57:46 PM PDT 24
Peak memory 222740 kb
Host smart-30c1f1fb-d81b-4d00-9471-2f4d9317a29a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1992906370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.1992906370
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.426858553
Short name T35
Test name
Test status
Simulation time 605263930 ps
CPU time 4.25 seconds
Started Mar 12 01:55:42 PM PDT 24
Finished Mar 12 01:55:47 PM PDT 24
Peak memory 214516 kb
Host smart-37ec6f91-f124-48d9-aa32-54d280e24ed5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=426858553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.426858553
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.3618978862
Short name T316
Test name
Test status
Simulation time 395458495 ps
CPU time 6.35 seconds
Started Mar 12 01:57:47 PM PDT 24
Finished Mar 12 01:57:54 PM PDT 24
Peak memory 215184 kb
Host smart-7638004e-1d3d-4470-abd2-213440bf57ec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3618978862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.3618978862
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_stress_all_with_rand_reset.2014110406
Short name T115
Test name
Test status
Simulation time 1829354876 ps
CPU time 22.99 seconds
Started Mar 12 01:56:07 PM PDT 24
Finished Mar 12 01:56:30 PM PDT 24
Peak memory 222832 kb
Host smart-cfe5cfbd-e203-4fd4-9bb4-0d1c57682e8a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014110406 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all_with_rand_reset.2014110406
Directory /workspace/11.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.3441023382
Short name T101
Test name
Test status
Simulation time 475241700 ps
CPU time 6.61 seconds
Started Mar 12 01:56:56 PM PDT 24
Finished Mar 12 01:57:03 PM PDT 24
Peak memory 221948 kb
Host smart-57dd74b7-6ba2-4966-bde9-0d7dac4368bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3441023382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.3441023382
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.3988278372
Short name T124
Test name
Test status
Simulation time 615657583 ps
CPU time 3.64 seconds
Started Mar 12 01:05:31 PM PDT 24
Finished Mar 12 01:05:36 PM PDT 24
Peak memory 214432 kb
Host smart-0c2a3a5d-91bd-4d43-a6f1-d026a3b80826
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988278372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.3988278372
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.1625202394
Short name T172
Test name
Test status
Simulation time 264462860 ps
CPU time 11.6 seconds
Started Mar 12 01:05:10 PM PDT 24
Finished Mar 12 01:05:22 PM PDT 24
Peak memory 206000 kb
Host smart-b82bdd98-e955-4826-b340-61a93c4fe328
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625202394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.1
625202394
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.3677478349
Short name T306
Test name
Test status
Simulation time 2765655823 ps
CPU time 155.74 seconds
Started Mar 12 01:59:21 PM PDT 24
Finished Mar 12 02:01:57 PM PDT 24
Peak memory 222648 kb
Host smart-39af081e-b799-42b5-a6d3-62fcff399149
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3677478349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.3677478349
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.1961445207
Short name T93
Test name
Test status
Simulation time 9080668624 ps
CPU time 83.62 seconds
Started Mar 12 01:58:28 PM PDT 24
Finished Mar 12 01:59:52 PM PDT 24
Peak memory 221148 kb
Host smart-c9c26633-b27a-4e36-91e4-8ea53970e7f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1961445207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.1961445207
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.1204773354
Short name T204
Test name
Test status
Simulation time 3613876500 ps
CPU time 67.74 seconds
Started Mar 12 01:54:43 PM PDT 24
Finished Mar 12 01:55:50 PM PDT 24
Peak memory 216552 kb
Host smart-87ce7e24-c75d-45b7-825c-7b89b0bf63bb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204773354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.1204773354
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.9613824
Short name T40
Test name
Test status
Simulation time 269337029 ps
CPU time 9.5 seconds
Started Mar 12 01:56:42 PM PDT 24
Finished Mar 12 01:56:52 PM PDT 24
Peak memory 214548 kb
Host smart-a5a65342-836f-4c12-a668-5000853f4390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9613824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.9613824
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.3340513343
Short name T159
Test name
Test status
Simulation time 54537071 ps
CPU time 3.99 seconds
Started Mar 12 01:58:22 PM PDT 24
Finished Mar 12 01:58:29 PM PDT 24
Peak memory 215256 kb
Host smart-1f5f0681-f300-478c-986a-c9ddf5791e21
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3340513343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.3340513343
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.1452233459
Short name T446
Test name
Test status
Simulation time 19933928 ps
CPU time 0.91 seconds
Started Mar 12 01:56:05 PM PDT 24
Finished Mar 12 01:56:06 PM PDT 24
Peak memory 206116 kb
Host smart-8da9bc7f-88da-4690-95c5-a34e70a1ddd7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1452233459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.1452233459
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.3021626447
Short name T30
Test name
Test status
Simulation time 259413261 ps
CPU time 4.08 seconds
Started Mar 12 01:58:52 PM PDT 24
Finished Mar 12 01:58:56 PM PDT 24
Peak memory 218288 kb
Host smart-4c0edf2b-8c5b-4cd2-bcc2-b2fc348371d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3021626447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.3021626447
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.1500347116
Short name T21
Test name
Test status
Simulation time 552758488 ps
CPU time 4.14 seconds
Started Mar 12 01:59:07 PM PDT 24
Finished Mar 12 01:59:12 PM PDT 24
Peak memory 222920 kb
Host smart-84333acc-e41e-4ce1-a605-f01591b7e724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500347116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.1500347116
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.3870591535
Short name T390
Test name
Test status
Simulation time 1377375758 ps
CPU time 10.63 seconds
Started Mar 12 01:58:30 PM PDT 24
Finished Mar 12 01:58:40 PM PDT 24
Peak memory 214500 kb
Host smart-5b06f32b-b645-4706-be3b-a18670f66fa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3870591535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.3870591535
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.2194213880
Short name T397
Test name
Test status
Simulation time 229963510 ps
CPU time 7.11 seconds
Started Mar 12 01:57:04 PM PDT 24
Finished Mar 12 01:57:13 PM PDT 24
Peak memory 215392 kb
Host smart-45e0f126-db9d-4176-881f-c4a67aa73dce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2194213880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.2194213880
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.1175592023
Short name T442
Test name
Test status
Simulation time 6013055095 ps
CPU time 80.6 seconds
Started Mar 12 01:56:39 PM PDT 24
Finished Mar 12 01:58:00 PM PDT 24
Peak memory 222752 kb
Host smart-5d074832-cf6f-44e2-93ad-dce2e44eeea9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1175592023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.1175592023
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.1274068611
Short name T229
Test name
Test status
Simulation time 197771634 ps
CPU time 7.91 seconds
Started Mar 12 01:56:35 PM PDT 24
Finished Mar 12 01:56:43 PM PDT 24
Peak memory 222620 kb
Host smart-35df11e1-7502-4829-ad2b-e570223d1dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274068611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.1274068611
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.2265470981
Short name T56
Test name
Test status
Simulation time 2720277925 ps
CPU time 23.71 seconds
Started Mar 12 01:58:01 PM PDT 24
Finished Mar 12 01:58:25 PM PDT 24
Peak memory 220616 kb
Host smart-86968c8f-3907-4340-b4b1-f7dcf8d121f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265470981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.2265470981
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.473256345
Short name T250
Test name
Test status
Simulation time 506298518 ps
CPU time 18.83 seconds
Started Mar 12 01:55:55 PM PDT 24
Finished Mar 12 01:56:14 PM PDT 24
Peak memory 222764 kb
Host smart-69b2f7bf-1b20-4248-91e3-33ead12af7e3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473256345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.473256345
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.3087092762
Short name T279
Test name
Test status
Simulation time 238530312 ps
CPU time 4.05 seconds
Started Mar 12 01:56:14 PM PDT 24
Finished Mar 12 01:56:18 PM PDT 24
Peak memory 222676 kb
Host smart-6ab71891-e476-4085-a793-a8df2c53cace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087092762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.3087092762
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.3382528870
Short name T441
Test name
Test status
Simulation time 2557926429 ps
CPU time 141.26 seconds
Started Mar 12 01:53:51 PM PDT 24
Finished Mar 12 01:56:14 PM PDT 24
Peak memory 215116 kb
Host smart-824d2cf1-2631-4f37-b247-7f800a2f80fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3382528870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.3382528870
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.396389178
Short name T152
Test name
Test status
Simulation time 188943490 ps
CPU time 5.33 seconds
Started Mar 12 01:57:47 PM PDT 24
Finished Mar 12 01:57:53 PM PDT 24
Peak memory 208576 kb
Host smart-a985eac9-cb58-48f0-b2f4-7bd7ce24047a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=396389178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.396389178
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.4029627131
Short name T186
Test name
Test status
Simulation time 1596073923 ps
CPU time 9.29 seconds
Started Mar 12 01:05:22 PM PDT 24
Finished Mar 12 01:05:31 PM PDT 24
Peak memory 209596 kb
Host smart-c2ea87c9-461f-4796-b802-09a40958560d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4029627131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_er
r.4029627131
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.1668317907
Short name T354
Test name
Test status
Simulation time 2860351504 ps
CPU time 82.44 seconds
Started Mar 12 01:54:01 PM PDT 24
Finished Mar 12 01:55:24 PM PDT 24
Peak memory 217320 kb
Host smart-57044995-c910-43aa-af90-e8619c0debf8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1668317907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.1668317907
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.1882354046
Short name T311
Test name
Test status
Simulation time 304483694 ps
CPU time 3.56 seconds
Started Mar 12 01:56:05 PM PDT 24
Finished Mar 12 01:56:08 PM PDT 24
Peak memory 210680 kb
Host smart-f1c5ef99-ecc1-4742-b3b9-d5460ad10f7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882354046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.1882354046
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.2633977688
Short name T122
Test name
Test status
Simulation time 52273162 ps
CPU time 3.56 seconds
Started Mar 12 01:56:54 PM PDT 24
Finished Mar 12 01:56:58 PM PDT 24
Peak memory 215624 kb
Host smart-860638fd-8087-4a27-9a6d-71cbe10efa36
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2633977688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.2633977688
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.139835803
Short name T107
Test name
Test status
Simulation time 3898632521 ps
CPU time 22.05 seconds
Started Mar 12 01:58:40 PM PDT 24
Finished Mar 12 01:59:02 PM PDT 24
Peak memory 215788 kb
Host smart-11093e1d-2c49-4f1a-886f-02b1f2fad52e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=139835803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.139835803
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.944140837
Short name T174
Test name
Test status
Simulation time 381770537 ps
CPU time 10.3 seconds
Started Mar 12 01:05:15 PM PDT 24
Finished Mar 12 01:05:26 PM PDT 24
Peak memory 209356 kb
Host smart-0c20f1e2-90a7-4355-9c80-e60523f72be2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944140837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err.
944140837
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.3801534961
Short name T176
Test name
Test status
Simulation time 22991867613 ps
CPU time 78.69 seconds
Started Mar 12 01:05:32 PM PDT 24
Finished Mar 12 01:06:52 PM PDT 24
Peak memory 228916 kb
Host smart-8b6608f5-b3cf-4119-9ba3-c25a9074d96b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801534961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.3801534961
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.3241248128
Short name T1030
Test name
Test status
Simulation time 261963163 ps
CPU time 3 seconds
Started Mar 12 01:05:06 PM PDT 24
Finished Mar 12 01:05:10 PM PDT 24
Peak memory 214532 kb
Host smart-4a1e93bc-9afa-408f-8cb0-562cdbe09f9e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3241248128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.3241248128
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.2062493219
Short name T177
Test name
Test status
Simulation time 432690501 ps
CPU time 6.24 seconds
Started Mar 12 01:05:19 PM PDT 24
Finished Mar 12 01:05:25 PM PDT 24
Peak memory 214024 kb
Host smart-be66de68-4c5f-4463-9a09-3ee6a85b5018
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062493219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.2062493219
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.1912436989
Short name T166
Test name
Test status
Simulation time 637634190 ps
CPU time 18.46 seconds
Started Mar 12 01:55:21 PM PDT 24
Finished Mar 12 01:55:40 PM PDT 24
Peak memory 215488 kb
Host smart-37b25836-abeb-42e9-b963-a12bf1812564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912436989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.1912436989
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.2815267371
Short name T304
Test name
Test status
Simulation time 155055504 ps
CPU time 2.96 seconds
Started Mar 12 01:53:50 PM PDT 24
Finished Mar 12 01:53:55 PM PDT 24
Peak memory 214496 kb
Host smart-46418a8f-f145-4167-a518-32b65042bf1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815267371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.2815267371
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.512674187
Short name T291
Test name
Test status
Simulation time 2273069098 ps
CPU time 60.66 seconds
Started Mar 12 01:55:54 PM PDT 24
Finished Mar 12 01:56:55 PM PDT 24
Peak memory 214592 kb
Host smart-9ddc5ef4-408c-495c-bc09-46374f3d5830
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=512674187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.512674187
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.3195759987
Short name T219
Test name
Test status
Simulation time 344626326 ps
CPU time 3.71 seconds
Started Mar 12 01:57:45 PM PDT 24
Finished Mar 12 01:57:49 PM PDT 24
Peak memory 210244 kb
Host smart-62e88354-203b-4c8a-896d-bb9c757a5123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3195759987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.3195759987
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.3340328765
Short name T337
Test name
Test status
Simulation time 810605111 ps
CPU time 10.34 seconds
Started Mar 12 01:58:51 PM PDT 24
Finished Mar 12 01:59:01 PM PDT 24
Peak memory 214532 kb
Host smart-e9287496-bfe6-46c3-829a-dbd40631d6f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3340328765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.3340328765
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.2777063784
Short name T312
Test name
Test status
Simulation time 927171794 ps
CPU time 5.48 seconds
Started Mar 12 01:59:21 PM PDT 24
Finished Mar 12 01:59:27 PM PDT 24
Peak memory 222664 kb
Host smart-29f26181-6dca-4369-89a8-4b391e1d3538
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2777063784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.2777063784
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.1537128715
Short name T185
Test name
Test status
Simulation time 2582448494 ps
CPU time 17.55 seconds
Started Mar 12 01:05:29 PM PDT 24
Finished Mar 12 01:05:47 PM PDT 24
Peak memory 209028 kb
Host smart-3939092e-044d-429c-8dea-4771f9dd459e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537128715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.1537128715
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.4286892290
Short name T34
Test name
Test status
Simulation time 1004428943 ps
CPU time 7.85 seconds
Started Mar 12 01:57:12 PM PDT 24
Finished Mar 12 01:57:20 PM PDT 24
Peak memory 208856 kb
Host smart-7cc8043c-b68e-4501-bc43-56bcd6ce3044
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286892290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.4286892290
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload.1605869373
Short name T288
Test name
Test status
Simulation time 183209132 ps
CPU time 4.17 seconds
Started Mar 12 01:57:23 PM PDT 24
Finished Mar 12 01:57:27 PM PDT 24
Peak memory 208348 kb
Host smart-81e8a89d-7e35-4e32-8774-b35ce69939af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1605869373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.1605869373
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.3756891612
Short name T44
Test name
Test status
Simulation time 217223706 ps
CPU time 5.02 seconds
Started Mar 12 01:57:34 PM PDT 24
Finished Mar 12 01:57:40 PM PDT 24
Peak memory 209432 kb
Host smart-2d64b226-e5da-47f1-91cd-0165d8b0366f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756891612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.3756891612
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.2952816312
Short name T110
Test name
Test status
Simulation time 898308501 ps
CPU time 10.34 seconds
Started Mar 12 01:58:01 PM PDT 24
Finished Mar 12 01:58:12 PM PDT 24
Peak memory 211328 kb
Host smart-644f5280-0e6a-4e8c-a3a1-cb52a450282e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2952816312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.2952816312
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.2231783531
Short name T91
Test name
Test status
Simulation time 578554883 ps
CPU time 5.6 seconds
Started Mar 12 01:59:10 PM PDT 24
Finished Mar 12 01:59:16 PM PDT 24
Peak memory 222624 kb
Host smart-46e41ab3-3b6a-44b3-83c3-2fec13b17fa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231783531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.2231783531
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.2987672687
Short name T407
Test name
Test status
Simulation time 159087158 ps
CPU time 2.47 seconds
Started Mar 12 01:57:12 PM PDT 24
Finished Mar 12 01:57:15 PM PDT 24
Peak memory 209860 kb
Host smart-cd33af44-b0bc-4c03-ae0a-86a8d846c6c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2987672687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.2987672687
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.2165006809
Short name T168
Test name
Test status
Simulation time 515534162 ps
CPU time 5.14 seconds
Started Mar 12 01:56:05 PM PDT 24
Finished Mar 12 01:56:10 PM PDT 24
Peak memory 217228 kb
Host smart-40c12b4e-0015-4b0c-b03d-f36f124cb366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2165006809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.2165006809
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.2885845575
Short name T171
Test name
Test status
Simulation time 696225235 ps
CPU time 5.35 seconds
Started Mar 12 01:57:15 PM PDT 24
Finished Mar 12 01:57:20 PM PDT 24
Peak memory 217356 kb
Host smart-9fe50639-40e6-4735-acf2-7b130f58d8a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885845575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.2885845575
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.883499581
Short name T170
Test name
Test status
Simulation time 194705857 ps
CPU time 6.33 seconds
Started Mar 12 01:57:15 PM PDT 24
Finished Mar 12 01:57:22 PM PDT 24
Peak memory 222988 kb
Host smart-6cff86d1-4b04-4732-8fa5-b674d86e959a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883499581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.883499581
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.1078310553
Short name T169
Test name
Test status
Simulation time 66392149 ps
CPU time 3.4 seconds
Started Mar 12 01:59:30 PM PDT 24
Finished Mar 12 01:59:34 PM PDT 24
Peak memory 217408 kb
Host smart-850b55c7-2c27-462d-9768-90d3086335d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078310553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.1078310553
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.3403145533
Short name T326
Test name
Test status
Simulation time 382990386 ps
CPU time 4.54 seconds
Started Mar 12 01:56:06 PM PDT 24
Finished Mar 12 01:56:11 PM PDT 24
Peak memory 218416 kb
Host smart-39c31d3b-41e8-458b-9f2f-d4e4ae5f233c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403145533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.3403145533
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.3874866026
Short name T334
Test name
Test status
Simulation time 55503741 ps
CPU time 3.43 seconds
Started Mar 12 01:56:25 PM PDT 24
Finished Mar 12 01:56:29 PM PDT 24
Peak memory 210360 kb
Host smart-14ec45e9-69a0-4a0f-a420-0a1cc86c4c6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3874866026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.3874866026
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.762947949
Short name T251
Test name
Test status
Simulation time 10896731355 ps
CPU time 46.27 seconds
Started Mar 12 01:57:04 PM PDT 24
Finished Mar 12 01:57:53 PM PDT 24
Peak memory 222724 kb
Host smart-f4cb496b-2835-407f-9493-6860f93b7c41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=762947949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.762947949
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.1627827168
Short name T209
Test name
Test status
Simulation time 1758737142 ps
CPU time 35.75 seconds
Started Mar 12 01:57:13 PM PDT 24
Finished Mar 12 01:57:49 PM PDT 24
Peak memory 215088 kb
Host smart-3c78786a-c612-4b01-a3b7-e0d6fc1cd05c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627827168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.1627827168
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.2989950835
Short name T358
Test name
Test status
Simulation time 63530457 ps
CPU time 4.31 seconds
Started Mar 12 01:57:33 PM PDT 24
Finished Mar 12 01:57:38 PM PDT 24
Peak memory 215680 kb
Host smart-bd61c15f-c47d-4a32-b13e-f83293ef9402
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2989950835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.2989950835
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.2767909300
Short name T883
Test name
Test status
Simulation time 1118835123 ps
CPU time 46.2 seconds
Started Mar 12 01:58:14 PM PDT 24
Finished Mar 12 01:59:00 PM PDT 24
Peak memory 222644 kb
Host smart-51cc4b4b-c331-4df3-9007-069b89b5e903
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2767909300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.2767909300
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.379847293
Short name T184
Test name
Test status
Simulation time 1264090944 ps
CPU time 20.13 seconds
Started Mar 12 01:05:33 PM PDT 24
Finished Mar 12 01:05:54 PM PDT 24
Peak memory 214200 kb
Host smart-1de8147c-70a9-4813-a7f5-4ad8f2db5f85
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379847293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_err
.379847293
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.1705038317
Short name T189
Test name
Test status
Simulation time 594978333 ps
CPU time 4.82 seconds
Started Mar 12 01:05:32 PM PDT 24
Finished Mar 12 01:05:38 PM PDT 24
Peak memory 209404 kb
Host smart-b463a381-7e83-4d7a-af43-757eaa39a9c9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705038317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er
r.1705038317
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.2944509950
Short name T175
Test name
Test status
Simulation time 337313889 ps
CPU time 8.26 seconds
Started Mar 12 01:05:02 PM PDT 24
Finished Mar 12 01:05:12 PM PDT 24
Peak memory 209512 kb
Host smart-bee8314e-4262-4b92-bc8a-c0cb57cdb963
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944509950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.2944509950
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.3040436672
Short name T182
Test name
Test status
Simulation time 4773633752 ps
CPU time 46.05 seconds
Started Mar 12 01:05:23 PM PDT 24
Finished Mar 12 01:06:09 PM PDT 24
Peak memory 214272 kb
Host smart-313bf143-e8be-45d4-bd0c-a458c5112055
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040436672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.3040436672
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.1296856743
Short name T11
Test name
Test status
Simulation time 183484126 ps
CPU time 2.07 seconds
Started Mar 12 01:57:03 PM PDT 24
Finished Mar 12 01:57:07 PM PDT 24
Peak memory 208800 kb
Host smart-0746b0d8-87df-45ca-8c4b-d199e9d5cc0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296856743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.1296856743
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.3078999005
Short name T192
Test name
Test status
Simulation time 95356244 ps
CPU time 2.46 seconds
Started Mar 12 01:58:51 PM PDT 24
Finished Mar 12 01:58:53 PM PDT 24
Peak memory 214464 kb
Host smart-dd46ffea-32ec-44f8-90a0-8f9766c6e3ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078999005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.3078999005
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.2766312969
Short name T405
Test name
Test status
Simulation time 919863386 ps
CPU time 9.43 seconds
Started Mar 12 01:05:05 PM PDT 24
Finished Mar 12 01:05:15 PM PDT 24
Peak memory 209740 kb
Host smart-e929824b-8a5f-425b-9d90-d822ed800bbe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766312969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.2766312969
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.1952308960
Short name T315
Test name
Test status
Simulation time 71572001 ps
CPU time 3.54 seconds
Started Mar 12 01:54:00 PM PDT 24
Finished Mar 12 01:54:04 PM PDT 24
Peak memory 210696 kb
Host smart-63aad466-d579-440d-8449-96a07f1ae2ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1952308960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.1952308960
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.1888885965
Short name T123
Test name
Test status
Simulation time 211155473 ps
CPU time 12.43 seconds
Started Mar 12 01:54:12 PM PDT 24
Finished Mar 12 01:54:25 PM PDT 24
Peak memory 214384 kb
Host smart-cc9a96e1-dfb8-4919-8577-c1fb9f2f6287
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1888885965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.1888885965
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.2667688200
Short name T331
Test name
Test status
Simulation time 577669562 ps
CPU time 5.39 seconds
Started Mar 12 01:54:11 PM PDT 24
Finished Mar 12 01:54:17 PM PDT 24
Peak memory 211124 kb
Host smart-fb6f59c2-d66e-410e-a2d0-7edea4f94db5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667688200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.2667688200
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.4071184373
Short name T254
Test name
Test status
Simulation time 2927339954 ps
CPU time 37.12 seconds
Started Mar 12 01:56:05 PM PDT 24
Finished Mar 12 01:56:42 PM PDT 24
Peak memory 222712 kb
Host smart-6f70d59c-0d82-4bf7-a0ef-16f767e13712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4071184373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.4071184373
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.2927537049
Short name T329
Test name
Test status
Simulation time 80351995 ps
CPU time 2.12 seconds
Started Mar 12 01:56:03 PM PDT 24
Finished Mar 12 01:56:05 PM PDT 24
Peak memory 208820 kb
Host smart-9866cfd2-d9dd-4114-b239-e6297b42f821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2927537049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.2927537049
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.4175770530
Short name T361
Test name
Test status
Simulation time 1795507658 ps
CPU time 9.16 seconds
Started Mar 12 01:56:14 PM PDT 24
Finished Mar 12 01:56:23 PM PDT 24
Peak memory 214544 kb
Host smart-3328df0e-8d5f-4ec3-940d-dc2f2a54d483
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4175770530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.4175770530
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.199233231
Short name T842
Test name
Test status
Simulation time 563114624 ps
CPU time 8.29 seconds
Started Mar 12 01:56:23 PM PDT 24
Finished Mar 12 01:56:32 PM PDT 24
Peak memory 215492 kb
Host smart-2c81ce1c-ef91-4335-90ff-17df1cdb65e0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=199233231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.199233231
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.3137637069
Short name T248
Test name
Test status
Simulation time 85313071 ps
CPU time 2.36 seconds
Started Mar 12 01:56:27 PM PDT 24
Finished Mar 12 01:56:29 PM PDT 24
Peak memory 221088 kb
Host smart-6950c50e-6b54-4138-9146-43ef43bcdca8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137637069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.3137637069
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.2494524953
Short name T256
Test name
Test status
Simulation time 4612557956 ps
CPU time 35.72 seconds
Started Mar 12 01:56:39 PM PDT 24
Finished Mar 12 01:57:15 PM PDT 24
Peak memory 222704 kb
Host smart-beb43590-819a-4bd2-97a2-80ca83a4d544
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2494524953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.2494524953
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.1919567679
Short name T373
Test name
Test status
Simulation time 649529593 ps
CPU time 8.61 seconds
Started Mar 12 01:56:51 PM PDT 24
Finished Mar 12 01:56:59 PM PDT 24
Peak memory 214356 kb
Host smart-db8a7e29-c782-48b8-a88b-b12c2c510975
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1919567679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.1919567679
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_sideload.2669160957
Short name T345
Test name
Test status
Simulation time 29485736 ps
CPU time 2.18 seconds
Started Mar 12 01:56:36 PM PDT 24
Finished Mar 12 01:56:38 PM PDT 24
Peak memory 208744 kb
Host smart-b2239869-3824-4578-b76f-e46063335485
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669160957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.2669160957
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_random.1239714213
Short name T323
Test name
Test status
Simulation time 882390486 ps
CPU time 10.17 seconds
Started Mar 12 01:57:15 PM PDT 24
Finished Mar 12 01:57:25 PM PDT 24
Peak memory 209884 kb
Host smart-726a068d-e75c-4da5-a7b1-173f60ef3f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1239714213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.1239714213
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.4089273398
Short name T388
Test name
Test status
Simulation time 345502317 ps
CPU time 6.71 seconds
Started Mar 12 01:57:22 PM PDT 24
Finished Mar 12 01:57:29 PM PDT 24
Peak memory 214524 kb
Host smart-cfd702e3-c54b-46d7-a1c0-b83ac81e7b2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089273398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.4089273398
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.1485856178
Short name T387
Test name
Test status
Simulation time 2311070935 ps
CPU time 16.71 seconds
Started Mar 12 01:57:35 PM PDT 24
Finished Mar 12 01:57:52 PM PDT 24
Peak memory 214400 kb
Host smart-ac44c351-b0f7-41e2-b930-32c2377167f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485856178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.1485856178
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.376164628
Short name T259
Test name
Test status
Simulation time 128554076 ps
CPU time 6.24 seconds
Started Mar 12 01:57:47 PM PDT 24
Finished Mar 12 01:57:53 PM PDT 24
Peak memory 220220 kb
Host smart-7de38439-6c02-439b-a832-22124ba1cdb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376164628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.376164628
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.1964466752
Short name T264
Test name
Test status
Simulation time 112277699 ps
CPU time 6.56 seconds
Started Mar 12 01:57:59 PM PDT 24
Finished Mar 12 01:58:06 PM PDT 24
Peak memory 210280 kb
Host smart-97e33a18-2291-4a9a-8071-669e384b5df3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964466752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.1964466752
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.2461297790
Short name T252
Test name
Test status
Simulation time 137555949 ps
CPU time 4.78 seconds
Started Mar 12 01:54:44 PM PDT 24
Finished Mar 12 01:54:49 PM PDT 24
Peak memory 222992 kb
Host smart-94af49ff-289b-4d39-a5e8-f09b0703f815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461297790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.2461297790
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.1276155054
Short name T301
Test name
Test status
Simulation time 535694144 ps
CPU time 4.03 seconds
Started Mar 12 01:58:13 PM PDT 24
Finished Mar 12 01:58:17 PM PDT 24
Peak memory 222568 kb
Host smart-bfe590e7-23cf-4c06-9979-90c3d271f1f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1276155054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.1276155054
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.54980516
Short name T262
Test name
Test status
Simulation time 2942744599 ps
CPU time 7.29 seconds
Started Mar 12 01:58:16 PM PDT 24
Finished Mar 12 01:58:23 PM PDT 24
Peak memory 218480 kb
Host smart-08deafd4-79d2-4228-a805-9ae477d6027b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54980516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.54980516
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.1652060575
Short name T378
Test name
Test status
Simulation time 279887045 ps
CPU time 15.75 seconds
Started Mar 12 01:59:00 PM PDT 24
Finished Mar 12 01:59:16 PM PDT 24
Peak memory 214492 kb
Host smart-603fceda-3bf2-4151-b336-4a1be0c3529c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1652060575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.1652060575
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.2791790275
Short name T283
Test name
Test status
Simulation time 265429176 ps
CPU time 4.91 seconds
Started Mar 12 01:59:32 PM PDT 24
Finished Mar 12 01:59:37 PM PDT 24
Peak memory 215764 kb
Host smart-9a166b10-0ef1-4157-a054-cbb96fd54489
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2791790275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.2791790275
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.2941695728
Short name T302
Test name
Test status
Simulation time 401335178 ps
CPU time 11.1 seconds
Started Mar 12 01:59:33 PM PDT 24
Finished Mar 12 01:59:44 PM PDT 24
Peak memory 222580 kb
Host smart-c7946ed8-03f1-418a-bef6-7808e9ebf935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2941695728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.2941695728
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.2822237441
Short name T167
Test name
Test status
Simulation time 114509196 ps
CPU time 3.89 seconds
Started Mar 12 01:58:18 PM PDT 24
Finished Mar 12 01:58:24 PM PDT 24
Peak memory 218320 kb
Host smart-c41edf87-cf54-456e-9bea-7078c1e203d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822237441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.2822237441
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.3141560485
Short name T1024
Test name
Test status
Simulation time 134388541 ps
CPU time 4.08 seconds
Started Mar 12 01:05:05 PM PDT 24
Finished Mar 12 01:05:09 PM PDT 24
Peak memory 206000 kb
Host smart-5aec5539-3fbd-4445-b673-88e52f1814df
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141560485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.3
141560485
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.1440311776
Short name T994
Test name
Test status
Simulation time 33533998 ps
CPU time 1.03 seconds
Started Mar 12 01:05:10 PM PDT 24
Finished Mar 12 01:05:11 PM PDT 24
Peak memory 205924 kb
Host smart-5108bbbd-e9bd-4a38-a1f9-b2ccfedd261d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440311776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.1
440311776
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.1535127594
Short name T949
Test name
Test status
Simulation time 125089711 ps
CPU time 1.85 seconds
Started Mar 12 01:05:06 PM PDT 24
Finished Mar 12 01:05:09 PM PDT 24
Peak memory 214416 kb
Host smart-d5f1dd79-d46e-4cfc-8bd8-3986d570d1bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1535127594 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.1535127594
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.1621670389
Short name T963
Test name
Test status
Simulation time 44645880 ps
CPU time 1.1 seconds
Started Mar 12 01:05:13 PM PDT 24
Finished Mar 12 01:05:15 PM PDT 24
Peak memory 205880 kb
Host smart-2a37f0dc-bcff-4c90-8805-8cf85ecf0c21
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621670389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.1621670389
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.1061415575
Short name T1049
Test name
Test status
Simulation time 35162505 ps
CPU time 0.83 seconds
Started Mar 12 01:05:05 PM PDT 24
Finished Mar 12 01:05:06 PM PDT 24
Peak memory 205708 kb
Host smart-89466127-cb7a-4ae2-8e8b-dcdf98de9671
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1061415575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.1061415575
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.3616996448
Short name T1042
Test name
Test status
Simulation time 142988663 ps
CPU time 2.05 seconds
Started Mar 12 01:05:07 PM PDT 24
Finished Mar 12 01:05:09 PM PDT 24
Peak memory 206020 kb
Host smart-23c8f8b1-0b7c-4211-b213-5503a542117a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3616996448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.3616996448
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.341331364
Short name T127
Test name
Test status
Simulation time 925983210 ps
CPU time 7.42 seconds
Started Mar 12 01:05:11 PM PDT 24
Finished Mar 12 01:05:19 PM PDT 24
Peak memory 214480 kb
Host smart-3d69c7cb-7af5-47b0-96a6-07d58eb473b5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341331364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.k
eymgr_shadow_reg_errors_with_csr_rw.341331364
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.2156837314
Short name T1005
Test name
Test status
Simulation time 106090080 ps
CPU time 3.19 seconds
Started Mar 12 01:05:06 PM PDT 24
Finished Mar 12 01:05:10 PM PDT 24
Peak memory 213968 kb
Host smart-b1bbaa31-c496-4d07-b078-0ae6e21c9b15
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156837314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.2156837314
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.2703691500
Short name T919
Test name
Test status
Simulation time 170945631 ps
CPU time 3.84 seconds
Started Mar 12 01:05:15 PM PDT 24
Finished Mar 12 01:05:19 PM PDT 24
Peak memory 208956 kb
Host smart-ee491ae2-58a8-4bea-a9b4-5f91384b7f21
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2703691500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.2703691500
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.2937400712
Short name T977
Test name
Test status
Simulation time 2043633775 ps
CPU time 11.35 seconds
Started Mar 12 01:05:05 PM PDT 24
Finished Mar 12 01:05:17 PM PDT 24
Peak memory 205940 kb
Host smart-2988ead0-8439-40b8-9ac9-5b2b830df30c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937400712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.2
937400712
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.2424475107
Short name T896
Test name
Test status
Simulation time 1000633061 ps
CPU time 11.95 seconds
Started Mar 12 01:05:11 PM PDT 24
Finished Mar 12 01:05:24 PM PDT 24
Peak memory 206004 kb
Host smart-29c4ed91-841a-4b4e-8c19-b4b491c7f7ba
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424475107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.2
424475107
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.1802502230
Short name T984
Test name
Test status
Simulation time 33892843 ps
CPU time 1.46 seconds
Started Mar 12 01:05:03 PM PDT 24
Finished Mar 12 01:05:06 PM PDT 24
Peak memory 205992 kb
Host smart-9cede8a0-0e74-4d33-83fb-95160bd12641
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802502230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.1
802502230
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.3522495591
Short name T971
Test name
Test status
Simulation time 746512649 ps
CPU time 1.98 seconds
Started Mar 12 01:05:15 PM PDT 24
Finished Mar 12 01:05:17 PM PDT 24
Peak memory 214228 kb
Host smart-a20e69f2-9640-492b-b8c4-076a54f17196
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3522495591 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.3522495591
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.49506280
Short name T1018
Test name
Test status
Simulation time 14263912 ps
CPU time 1.13 seconds
Started Mar 12 01:05:13 PM PDT 24
Finished Mar 12 01:05:15 PM PDT 24
Peak memory 206024 kb
Host smart-7200f59d-57fb-45bf-819b-562b1582aca0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49506280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.49506280
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.1117270783
Short name T937
Test name
Test status
Simulation time 11089149 ps
CPU time 0.7 seconds
Started Mar 12 01:05:13 PM PDT 24
Finished Mar 12 01:05:14 PM PDT 24
Peak memory 205688 kb
Host smart-1112b9de-f6ef-4258-977a-3b6080ca2982
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1117270783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.1117270783
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.343141905
Short name T921
Test name
Test status
Simulation time 22359360 ps
CPU time 1.82 seconds
Started Mar 12 01:05:13 PM PDT 24
Finished Mar 12 01:05:15 PM PDT 24
Peak memory 205984 kb
Host smart-66dbafbd-21d2-4734-955c-1ff432c27e1b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343141905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sam
e_csr_outstanding.343141905
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.457682789
Short name T979
Test name
Test status
Simulation time 1634139713 ps
CPU time 9.12 seconds
Started Mar 12 01:05:06 PM PDT 24
Finished Mar 12 01:05:15 PM PDT 24
Peak memory 214532 kb
Host smart-83ac6b3d-f7ae-49a8-8249-23862a58c3ac
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=457682789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shadow
_reg_errors.457682789
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.2629935993
Short name T932
Test name
Test status
Simulation time 43110706 ps
CPU time 2.78 seconds
Started Mar 12 01:05:13 PM PDT 24
Finished Mar 12 01:05:16 PM PDT 24
Peak memory 214200 kb
Host smart-cf403022-8db6-4e92-9772-d1cfde3e75ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629935993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.2629935993
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.3604041902
Short name T995
Test name
Test status
Simulation time 28786800 ps
CPU time 2.13 seconds
Started Mar 12 01:05:29 PM PDT 24
Finished Mar 12 01:05:32 PM PDT 24
Peak memory 214244 kb
Host smart-6135678f-a979-4c46-9fd9-9970d6228abd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604041902 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.3604041902
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.2028476428
Short name T951
Test name
Test status
Simulation time 14876395 ps
CPU time 1.19 seconds
Started Mar 12 01:05:22 PM PDT 24
Finished Mar 12 01:05:24 PM PDT 24
Peak memory 206108 kb
Host smart-9e98abf9-cb7d-4b31-9041-0b5b3479de38
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028476428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.2028476428
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.3114678081
Short name T902
Test name
Test status
Simulation time 30024313 ps
CPU time 0.7 seconds
Started Mar 12 01:05:21 PM PDT 24
Finished Mar 12 01:05:22 PM PDT 24
Peak memory 205684 kb
Host smart-7864a8cd-ade4-4ce8-afe2-c6e5c8e29799
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3114678081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.3114678081
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.2294461034
Short name T160
Test name
Test status
Simulation time 81570777 ps
CPU time 1.62 seconds
Started Mar 12 01:05:21 PM PDT 24
Finished Mar 12 01:05:23 PM PDT 24
Peak memory 205932 kb
Host smart-673d490c-93a3-4969-917b-a1b2a759419e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294461034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.2294461034
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.2939750024
Short name T907
Test name
Test status
Simulation time 227835450 ps
CPU time 3.4 seconds
Started Mar 12 01:05:19 PM PDT 24
Finished Mar 12 01:05:22 PM PDT 24
Peak memory 218904 kb
Host smart-a89091d7-f611-42cb-a75f-ddbc88c6bb22
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939750024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.2939750024
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.1166634453
Short name T996
Test name
Test status
Simulation time 939647873 ps
CPU time 5.59 seconds
Started Mar 12 01:05:20 PM PDT 24
Finished Mar 12 01:05:26 PM PDT 24
Peak memory 222652 kb
Host smart-4b96c990-25d0-4de0-896a-7cad8d7eac82
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166634453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.keymgr_shadow_reg_errors_with_csr_rw.1166634453
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.1577299374
Short name T1060
Test name
Test status
Simulation time 673092773 ps
CPU time 3.12 seconds
Started Mar 12 01:05:22 PM PDT 24
Finished Mar 12 01:05:25 PM PDT 24
Peak memory 214100 kb
Host smart-ddd9da45-f562-4055-8b22-c7f3f762e581
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577299374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.1577299374
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.2155316248
Short name T943
Test name
Test status
Simulation time 56615062 ps
CPU time 2.39 seconds
Started Mar 12 01:05:19 PM PDT 24
Finished Mar 12 01:05:22 PM PDT 24
Peak memory 214356 kb
Host smart-3a655b6f-4e68-477b-a4eb-281c6dda83a1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2155316248 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.2155316248
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.430927321
Short name T920
Test name
Test status
Simulation time 38131090 ps
CPU time 1.51 seconds
Started Mar 12 01:05:29 PM PDT 24
Finished Mar 12 01:05:31 PM PDT 24
Peak memory 205632 kb
Host smart-abda93fb-3ce6-4f85-a22f-c7882e2e35bf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=430927321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.430927321
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.3761136944
Short name T898
Test name
Test status
Simulation time 39752165 ps
CPU time 0.81 seconds
Started Mar 12 01:05:21 PM PDT 24
Finished Mar 12 01:05:22 PM PDT 24
Peak memory 205696 kb
Host smart-86211702-21b4-4242-80b8-1c8cc1d355aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761136944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.3761136944
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.717574429
Short name T953
Test name
Test status
Simulation time 124719991 ps
CPU time 2.44 seconds
Started Mar 12 01:05:20 PM PDT 24
Finished Mar 12 01:05:23 PM PDT 24
Peak memory 205924 kb
Host smart-da22f62e-88b8-414b-83e7-7fad0ed05603
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717574429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_sa
me_csr_outstanding.717574429
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.1516447391
Short name T121
Test name
Test status
Simulation time 166792742 ps
CPU time 4.83 seconds
Started Mar 12 01:05:22 PM PDT 24
Finished Mar 12 01:05:27 PM PDT 24
Peak memory 214476 kb
Host smart-8455cb52-ddee-4c4c-9255-e85f355de744
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1516447391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.1516447391
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.2730477337
Short name T1014
Test name
Test status
Simulation time 499235730 ps
CPU time 6.34 seconds
Started Mar 12 01:05:19 PM PDT 24
Finished Mar 12 01:05:26 PM PDT 24
Peak memory 220532 kb
Host smart-c653113e-adcf-4fb6-aeda-b0a9e904cd09
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730477337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.2730477337
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.2326533252
Short name T928
Test name
Test status
Simulation time 283107353 ps
CPU time 2.22 seconds
Started Mar 12 01:05:22 PM PDT 24
Finished Mar 12 01:05:24 PM PDT 24
Peak memory 214204 kb
Host smart-c613684b-7ddc-4afd-b2c2-7750270b3371
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326533252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.2326533252
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.3669852784
Short name T958
Test name
Test status
Simulation time 50769885 ps
CPU time 2.25 seconds
Started Mar 12 01:05:37 PM PDT 24
Finished Mar 12 01:05:39 PM PDT 24
Peak memory 214224 kb
Host smart-d32ba399-b160-4c69-9570-b75913f6a6ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3669852784 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.3669852784
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.533321975
Short name T1046
Test name
Test status
Simulation time 65796476 ps
CPU time 1.09 seconds
Started Mar 12 01:05:28 PM PDT 24
Finished Mar 12 01:05:29 PM PDT 24
Peak memory 206008 kb
Host smart-c4e48ae5-bfc9-4c95-af37-d6c5dc108920
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=533321975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.533321975
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.1502599036
Short name T957
Test name
Test status
Simulation time 8198065 ps
CPU time 0.8 seconds
Started Mar 12 01:05:29 PM PDT 24
Finished Mar 12 01:05:33 PM PDT 24
Peak memory 205640 kb
Host smart-f17b1ab6-f60f-4c75-a5d5-fa5e889720af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502599036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.1502599036
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.1845384633
Short name T164
Test name
Test status
Simulation time 67583037 ps
CPU time 2.1 seconds
Started Mar 12 01:05:30 PM PDT 24
Finished Mar 12 01:05:35 PM PDT 24
Peak memory 206000 kb
Host smart-81398c93-fda6-43e3-a664-dc1a88bf9e20
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845384633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.1845384633
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.3977637189
Short name T120
Test name
Test status
Simulation time 89105117 ps
CPU time 2.87 seconds
Started Mar 12 01:05:22 PM PDT 24
Finished Mar 12 01:05:25 PM PDT 24
Peak memory 214480 kb
Host smart-5187fedb-9a8f-4827-94dc-041dcff33fe1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3977637189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.3977637189
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.4035007809
Short name T126
Test name
Test status
Simulation time 227415516 ps
CPU time 8.36 seconds
Started Mar 12 01:05:19 PM PDT 24
Finished Mar 12 01:05:28 PM PDT 24
Peak memory 214560 kb
Host smart-aff69b46-fbd2-4444-b214-1ea6e4fb7a16
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035007809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.4035007809
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.982294104
Short name T1025
Test name
Test status
Simulation time 171415788 ps
CPU time 2.74 seconds
Started Mar 12 01:05:30 PM PDT 24
Finished Mar 12 01:05:35 PM PDT 24
Peak memory 216268 kb
Host smart-c32e04cf-752d-4530-aba5-005f55fb0367
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982294104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.982294104
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.326600980
Short name T992
Test name
Test status
Simulation time 285040340 ps
CPU time 1.69 seconds
Started Mar 12 01:05:32 PM PDT 24
Finished Mar 12 01:05:35 PM PDT 24
Peak memory 214312 kb
Host smart-550389dd-2e02-4214-b842-44586bfd29ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326600980 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.326600980
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.2938562148
Short name T965
Test name
Test status
Simulation time 84093140 ps
CPU time 1.13 seconds
Started Mar 12 01:05:28 PM PDT 24
Finished Mar 12 01:05:30 PM PDT 24
Peak memory 206020 kb
Host smart-0c905107-d4d3-42f9-a633-07d021ab8d79
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938562148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.2938562148
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.2747627200
Short name T1044
Test name
Test status
Simulation time 43368633 ps
CPU time 0.78 seconds
Started Mar 12 01:05:32 PM PDT 24
Finished Mar 12 01:05:34 PM PDT 24
Peak memory 205724 kb
Host smart-3fe1ba32-ea05-4f2e-9e9a-ce443ba4e0a5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2747627200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.2747627200
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.1376395770
Short name T999
Test name
Test status
Simulation time 38124969 ps
CPU time 2.58 seconds
Started Mar 12 01:05:31 PM PDT 24
Finished Mar 12 01:05:35 PM PDT 24
Peak memory 205992 kb
Host smart-a03a3bc6-0a40-4365-8fd4-532a92da999d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1376395770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.1376395770
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.1449084953
Short name T1059
Test name
Test status
Simulation time 576690908 ps
CPU time 2.5 seconds
Started Mar 12 01:05:36 PM PDT 24
Finished Mar 12 01:05:39 PM PDT 24
Peak memory 214540 kb
Host smart-d9a5370b-5553-4dd3-8c7f-6c6c0793097a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1449084953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.1449084953
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.2033386715
Short name T1006
Test name
Test status
Simulation time 97893595 ps
CPU time 3.91 seconds
Started Mar 12 01:05:33 PM PDT 24
Finished Mar 12 01:05:38 PM PDT 24
Peak memory 214500 kb
Host smart-3e670681-6c1e-422b-bb12-e4a63080e773
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033386715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.2033386715
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.982206904
Short name T1011
Test name
Test status
Simulation time 149055916 ps
CPU time 2.24 seconds
Started Mar 12 01:05:35 PM PDT 24
Finished Mar 12 01:05:38 PM PDT 24
Peak memory 214168 kb
Host smart-fa9d1c20-6b1e-4fae-94c2-06769e3cc387
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=982206904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.982206904
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.1795826319
Short name T913
Test name
Test status
Simulation time 673549088 ps
CPU time 1.33 seconds
Started Mar 12 01:05:31 PM PDT 24
Finished Mar 12 01:05:34 PM PDT 24
Peak memory 214320 kb
Host smart-08aefab4-8b8d-4d36-86a3-e8371b4b2b75
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795826319 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.1795826319
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.1979102261
Short name T947
Test name
Test status
Simulation time 29639733 ps
CPU time 1.13 seconds
Started Mar 12 01:05:33 PM PDT 24
Finished Mar 12 01:05:35 PM PDT 24
Peak memory 205996 kb
Host smart-49475d4d-28bd-4f42-8843-a903ed6b938a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979102261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.1979102261
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.774323467
Short name T904
Test name
Test status
Simulation time 39771564 ps
CPU time 0.85 seconds
Started Mar 12 01:05:29 PM PDT 24
Finished Mar 12 01:05:33 PM PDT 24
Peak memory 205668 kb
Host smart-268a651b-23e3-499f-9b5e-4a425d81a3cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=774323467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.774323467
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.3882710296
Short name T1013
Test name
Test status
Simulation time 149953707 ps
CPU time 2.13 seconds
Started Mar 12 01:05:37 PM PDT 24
Finished Mar 12 01:05:39 PM PDT 24
Peak memory 206024 kb
Host smart-849c1860-4d37-4a91-a9c1-eb10c2b2ad8e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3882710296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s
ame_csr_outstanding.3882710296
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.262965019
Short name T1037
Test name
Test status
Simulation time 2525295066 ps
CPU time 14.82 seconds
Started Mar 12 01:05:31 PM PDT 24
Finished Mar 12 01:05:47 PM PDT 24
Peak memory 214500 kb
Host smart-069d767b-62cb-4ea1-bcf8-6ac4bc5d4035
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262965019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shado
w_reg_errors.262965019
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.1119948105
Short name T1023
Test name
Test status
Simulation time 173712029 ps
CPU time 9.46 seconds
Started Mar 12 01:05:29 PM PDT 24
Finished Mar 12 01:05:39 PM PDT 24
Peak memory 214432 kb
Host smart-4e1aba68-83fb-42fc-b1f0-308a94eb43fd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1119948105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.1119948105
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.3626714686
Short name T942
Test name
Test status
Simulation time 277963440 ps
CPU time 3.52 seconds
Started Mar 12 01:05:37 PM PDT 24
Finished Mar 12 01:05:40 PM PDT 24
Peak memory 214156 kb
Host smart-de0311b5-d119-433f-9860-0d893719c0d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626714686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.3626714686
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.2848867410
Short name T905
Test name
Test status
Simulation time 170876849 ps
CPU time 4.34 seconds
Started Mar 12 01:05:36 PM PDT 24
Finished Mar 12 01:05:40 PM PDT 24
Peak memory 209628 kb
Host smart-6688d6b3-cdb1-4321-a43e-4c6c158a951e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848867410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.2848867410
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.606155530
Short name T1039
Test name
Test status
Simulation time 96150413 ps
CPU time 1.25 seconds
Started Mar 12 01:05:34 PM PDT 24
Finished Mar 12 01:05:36 PM PDT 24
Peak memory 206060 kb
Host smart-bcc9b1cb-0279-4e42-ab34-f243b51f5829
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=606155530 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.606155530
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.451488940
Short name T911
Test name
Test status
Simulation time 38689343 ps
CPU time 1.07 seconds
Started Mar 12 01:05:36 PM PDT 24
Finished Mar 12 01:05:37 PM PDT 24
Peak memory 205852 kb
Host smart-be31b4ff-4b81-4361-9675-8f03a43e2703
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451488940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.451488940
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.947351461
Short name T964
Test name
Test status
Simulation time 36171806 ps
CPU time 0.74 seconds
Started Mar 12 01:05:35 PM PDT 24
Finished Mar 12 01:05:36 PM PDT 24
Peak memory 205732 kb
Host smart-c5ab2471-eb6f-4644-90e5-657464df954d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=947351461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.947351461
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.1960015648
Short name T1051
Test name
Test status
Simulation time 73055071 ps
CPU time 1.54 seconds
Started Mar 12 01:05:29 PM PDT 24
Finished Mar 12 01:05:32 PM PDT 24
Peak memory 205864 kb
Host smart-0ccc6a73-cc53-420c-9637-f473ef743385
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960015648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.1960015648
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.2342357438
Short name T1000
Test name
Test status
Simulation time 169617220 ps
CPU time 3.52 seconds
Started Mar 12 01:05:33 PM PDT 24
Finished Mar 12 01:05:38 PM PDT 24
Peak memory 222636 kb
Host smart-9d6c60e9-f87a-4660-a931-f0950000a6d3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2342357438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.2342357438
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.1501644209
Short name T125
Test name
Test status
Simulation time 270899314 ps
CPU time 8.53 seconds
Started Mar 12 01:05:33 PM PDT 24
Finished Mar 12 01:05:43 PM PDT 24
Peak memory 214496 kb
Host smart-d80cc673-83ae-4d6d-b19a-95374f515be9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1501644209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.1501644209
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.79488811
Short name T1001
Test name
Test status
Simulation time 247526876 ps
CPU time 2.57 seconds
Started Mar 12 01:05:32 PM PDT 24
Finished Mar 12 01:05:35 PM PDT 24
Peak memory 214172 kb
Host smart-b61f1455-67e0-4709-88da-eedd957cec5d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79488811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.79488811
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.1240375083
Short name T193
Test name
Test status
Simulation time 116229233 ps
CPU time 6.27 seconds
Started Mar 12 01:05:33 PM PDT 24
Finished Mar 12 01:05:41 PM PDT 24
Peak memory 209024 kb
Host smart-550f3814-0f31-47f1-bf02-c2908ce99377
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1240375083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.1240375083
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.926954594
Short name T1016
Test name
Test status
Simulation time 29450961 ps
CPU time 1.52 seconds
Started Mar 12 01:05:33 PM PDT 24
Finished Mar 12 01:05:35 PM PDT 24
Peak memory 214348 kb
Host smart-e30a3651-4007-4b35-8e90-f33dd24fabad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926954594 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.926954594
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.1749636288
Short name T952
Test name
Test status
Simulation time 33464707 ps
CPU time 1.17 seconds
Started Mar 12 01:05:29 PM PDT 24
Finished Mar 12 01:05:33 PM PDT 24
Peak memory 206012 kb
Host smart-7b5f0b97-0f86-4952-9193-cebe93cc6f2f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749636288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.1749636288
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.3739908393
Short name T895
Test name
Test status
Simulation time 19480427 ps
CPU time 0.82 seconds
Started Mar 12 01:05:35 PM PDT 24
Finished Mar 12 01:05:36 PM PDT 24
Peak memory 205628 kb
Host smart-f1240774-954d-4add-8f9f-889a274b5dec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3739908393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.3739908393
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.1470594512
Short name T1027
Test name
Test status
Simulation time 333903558 ps
CPU time 2.35 seconds
Started Mar 12 01:05:34 PM PDT 24
Finished Mar 12 01:05:37 PM PDT 24
Peak memory 205980 kb
Host smart-28e11092-53f2-4592-966b-2cc57dbb79c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1470594512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.1470594512
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.2015890817
Short name T933
Test name
Test status
Simulation time 260097777 ps
CPU time 1.99 seconds
Started Mar 12 01:05:30 PM PDT 24
Finished Mar 12 01:05:35 PM PDT 24
Peak memory 214512 kb
Host smart-3371acbe-eb23-49a6-87f3-8f28a31cb5ef
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2015890817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.2015890817
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.4172880648
Short name T1043
Test name
Test status
Simulation time 279268050 ps
CPU time 4.66 seconds
Started Mar 12 01:05:29 PM PDT 24
Finished Mar 12 01:05:34 PM PDT 24
Peak memory 214520 kb
Host smart-fdc9004b-ce53-417a-b922-acb2d7a75171
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172880648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.4172880648
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.2476620495
Short name T1050
Test name
Test status
Simulation time 281905459 ps
CPU time 2.48 seconds
Started Mar 12 01:05:29 PM PDT 24
Finished Mar 12 01:05:32 PM PDT 24
Peak memory 216212 kb
Host smart-66f742ee-e5b8-41e3-99be-576885848cdb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476620495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.2476620495
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.1496499455
Short name T173
Test name
Test status
Simulation time 367918948 ps
CPU time 9.11 seconds
Started Mar 12 01:05:32 PM PDT 24
Finished Mar 12 01:05:42 PM PDT 24
Peak memory 209400 kb
Host smart-be71be05-f463-4d77-b4bd-0a5f3c7c5a20
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1496499455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.1496499455
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.3216573822
Short name T989
Test name
Test status
Simulation time 54011165 ps
CPU time 2.06 seconds
Started Mar 12 01:05:36 PM PDT 24
Finished Mar 12 01:05:38 PM PDT 24
Peak memory 214204 kb
Host smart-429ec2c0-6e0d-4e34-8c65-f249302fa872
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3216573822 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.3216573822
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.3770278587
Short name T1056
Test name
Test status
Simulation time 46731700 ps
CPU time 1.04 seconds
Started Mar 12 01:05:36 PM PDT 24
Finished Mar 12 01:05:37 PM PDT 24
Peak memory 205596 kb
Host smart-e972dc42-abbb-496d-a158-f17e1d4748b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770278587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.3770278587
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.1547692210
Short name T1041
Test name
Test status
Simulation time 34761443 ps
CPU time 0.82 seconds
Started Mar 12 01:05:34 PM PDT 24
Finished Mar 12 01:05:36 PM PDT 24
Peak memory 205672 kb
Host smart-6eedbdc5-00aa-4a73-9b9c-4e63b36547cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1547692210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.1547692210
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.4049076604
Short name T960
Test name
Test status
Simulation time 184761199 ps
CPU time 3.83 seconds
Started Mar 12 01:05:37 PM PDT 24
Finished Mar 12 01:05:41 PM PDT 24
Peak memory 206088 kb
Host smart-08b689bb-4c7c-42fe-83bb-dcf83c8d11b5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4049076604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.4049076604
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.2024309897
Short name T1064
Test name
Test status
Simulation time 414874719 ps
CPU time 7.15 seconds
Started Mar 12 01:05:33 PM PDT 24
Finished Mar 12 01:05:42 PM PDT 24
Peak memory 214416 kb
Host smart-f389bc63-8dfc-43f1-b2ff-0555d126b270
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024309897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.keymgr_shadow_reg_errors_with_csr_rw.2024309897
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.2605429467
Short name T929
Test name
Test status
Simulation time 964802629 ps
CPU time 3.48 seconds
Started Mar 12 01:05:33 PM PDT 24
Finished Mar 12 01:05:38 PM PDT 24
Peak memory 214164 kb
Host smart-192fcb21-e5e9-4fed-9622-ad7ed5ffded2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605429467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.2605429467
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.2700203938
Short name T178
Test name
Test status
Simulation time 254402724 ps
CPU time 9.12 seconds
Started Mar 12 01:05:32 PM PDT 24
Finished Mar 12 01:05:43 PM PDT 24
Peak memory 209132 kb
Host smart-37ce7cb8-f0b7-4341-9c43-e3dfd05c908a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2700203938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.2700203938
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.4094694775
Short name T1031
Test name
Test status
Simulation time 142535627 ps
CPU time 1.54 seconds
Started Mar 12 01:05:33 PM PDT 24
Finished Mar 12 01:05:35 PM PDT 24
Peak memory 214200 kb
Host smart-aaaec6b5-ffe0-45d7-b311-a5f04a87f76c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4094694775 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.4094694775
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.1853998152
Short name T974
Test name
Test status
Simulation time 14015041 ps
CPU time 1.07 seconds
Started Mar 12 01:05:31 PM PDT 24
Finished Mar 12 01:05:34 PM PDT 24
Peak memory 205884 kb
Host smart-402c3abc-df66-4dc1-98f0-13188b21084f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1853998152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.1853998152
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.504477009
Short name T983
Test name
Test status
Simulation time 8964440 ps
CPU time 0.87 seconds
Started Mar 12 01:05:32 PM PDT 24
Finished Mar 12 01:05:34 PM PDT 24
Peak memory 205680 kb
Host smart-607e2729-c42b-455c-8170-c2e1d537a06c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504477009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.504477009
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.489065137
Short name T1009
Test name
Test status
Simulation time 78009844 ps
CPU time 1.94 seconds
Started Mar 12 01:05:29 PM PDT 24
Finished Mar 12 01:05:31 PM PDT 24
Peak memory 205912 kb
Host smart-28b22c31-02d3-4f36-9104-8fa998b5e7d5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=489065137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_sa
me_csr_outstanding.489065137
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.2869026013
Short name T973
Test name
Test status
Simulation time 60892451 ps
CPU time 2.43 seconds
Started Mar 12 01:05:32 PM PDT 24
Finished Mar 12 01:05:36 PM PDT 24
Peak memory 214620 kb
Host smart-c0fbfd41-e11a-45ac-9982-42ea80f32744
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869026013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.2869026013
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.2708796608
Short name T1057
Test name
Test status
Simulation time 165028681 ps
CPU time 8.72 seconds
Started Mar 12 01:05:34 PM PDT 24
Finished Mar 12 01:05:43 PM PDT 24
Peak memory 214508 kb
Host smart-84ebbab8-41e4-450e-a053-d1e608b5fcce
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2708796608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.2708796608
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.796861906
Short name T1047
Test name
Test status
Simulation time 151826982 ps
CPU time 5.13 seconds
Started Mar 12 01:05:33 PM PDT 24
Finished Mar 12 01:05:39 PM PDT 24
Peak memory 215480 kb
Host smart-fa9bcf43-66c1-4378-bad1-7a44f756083a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796861906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.796861906
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.3296129551
Short name T944
Test name
Test status
Simulation time 80337505 ps
CPU time 1.45 seconds
Started Mar 12 01:05:36 PM PDT 24
Finished Mar 12 01:05:38 PM PDT 24
Peak memory 214200 kb
Host smart-8e1d8e00-216d-46c0-b636-c99f5e3cdd38
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296129551 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.3296129551
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.2272401441
Short name T1020
Test name
Test status
Simulation time 37588442 ps
CPU time 1.61 seconds
Started Mar 12 01:05:37 PM PDT 24
Finished Mar 12 01:05:38 PM PDT 24
Peak memory 205864 kb
Host smart-81089285-d54c-4323-a6ef-68df741f6015
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272401441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.2272401441
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.2164866787
Short name T903
Test name
Test status
Simulation time 17821955 ps
CPU time 0.72 seconds
Started Mar 12 01:05:39 PM PDT 24
Finished Mar 12 01:05:39 PM PDT 24
Peak memory 205676 kb
Host smart-2d85b896-16c9-4064-ae81-591e6dbae413
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164866787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.2164866787
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.1487363649
Short name T993
Test name
Test status
Simulation time 450137637 ps
CPU time 4.53 seconds
Started Mar 12 01:05:39 PM PDT 24
Finished Mar 12 01:05:43 PM PDT 24
Peak memory 205916 kb
Host smart-0a31486c-bac7-45c5-8af6-750285ba2490
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487363649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.1487363649
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.4028651115
Short name T976
Test name
Test status
Simulation time 367844535 ps
CPU time 3.73 seconds
Started Mar 12 01:05:35 PM PDT 24
Finished Mar 12 01:05:39 PM PDT 24
Peak memory 214496 kb
Host smart-5486564d-f4c8-432e-8f15-1d319a235992
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028651115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.4028651115
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.3856890149
Short name T119
Test name
Test status
Simulation time 428460521 ps
CPU time 12.97 seconds
Started Mar 12 01:05:33 PM PDT 24
Finished Mar 12 01:05:47 PM PDT 24
Peak memory 220284 kb
Host smart-0cc85a3d-d7b7-4254-8cc2-2da11a48c341
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3856890149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.3856890149
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.2838234693
Short name T923
Test name
Test status
Simulation time 45947246 ps
CPU time 3.02 seconds
Started Mar 12 01:05:33 PM PDT 24
Finished Mar 12 01:05:38 PM PDT 24
Peak memory 215316 kb
Host smart-1df4709e-95b6-4f9c-9782-939f69904ed4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838234693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.2838234693
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.376618125
Short name T991
Test name
Test status
Simulation time 234617184 ps
CPU time 3.4 seconds
Started Mar 12 01:05:38 PM PDT 24
Finished Mar 12 01:05:41 PM PDT 24
Peak memory 208932 kb
Host smart-6ebed3dd-9259-43aa-a58f-3d2c2f63b114
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=376618125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_err
.376618125
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.909283139
Short name T948
Test name
Test status
Simulation time 1340194727 ps
CPU time 7.06 seconds
Started Mar 12 01:05:10 PM PDT 24
Finished Mar 12 01:05:18 PM PDT 24
Peak memory 206048 kb
Host smart-d85aa371-9fa0-4706-a733-63529f0c959d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909283139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.909283139
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.2335347263
Short name T968
Test name
Test status
Simulation time 255644417 ps
CPU time 6.28 seconds
Started Mar 12 01:05:04 PM PDT 24
Finished Mar 12 01:05:11 PM PDT 24
Peak memory 206036 kb
Host smart-da5479c9-8b2f-4992-8b9f-919d1cce247d
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335347263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.2
335347263
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.3828246409
Short name T934
Test name
Test status
Simulation time 244734182 ps
CPU time 1.08 seconds
Started Mar 12 01:05:09 PM PDT 24
Finished Mar 12 01:05:11 PM PDT 24
Peak memory 205920 kb
Host smart-ffaf7029-eb2f-4c20-b425-959f273790e8
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828246409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.3
828246409
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.1996242495
Short name T909
Test name
Test status
Simulation time 107266869 ps
CPU time 1.17 seconds
Started Mar 12 01:05:06 PM PDT 24
Finished Mar 12 01:05:08 PM PDT 24
Peak memory 214500 kb
Host smart-8cd900b4-bf09-4b18-9d20-38d3930883f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1996242495 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.1996242495
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.1491768429
Short name T1034
Test name
Test status
Simulation time 371016507 ps
CPU time 1.34 seconds
Started Mar 12 01:05:13 PM PDT 24
Finished Mar 12 01:05:15 PM PDT 24
Peak memory 205984 kb
Host smart-b4f637a0-0048-4e2c-b41c-e0f1373221de
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1491768429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.1491768429
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.1226058361
Short name T990
Test name
Test status
Simulation time 10315527 ps
CPU time 0.74 seconds
Started Mar 12 01:05:11 PM PDT 24
Finished Mar 12 01:05:12 PM PDT 24
Peak memory 205700 kb
Host smart-fc635a76-f5f9-4009-babb-5c0114c1b1bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226058361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.1226058361
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.2083397349
Short name T922
Test name
Test status
Simulation time 174023850 ps
CPU time 3.73 seconds
Started Mar 12 01:05:13 PM PDT 24
Finished Mar 12 01:05:17 PM PDT 24
Peak memory 205984 kb
Host smart-1f3a3b3c-3ab7-4e5a-bdfe-0045c498bb25
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083397349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.2083397349
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.161946384
Short name T959
Test name
Test status
Simulation time 1196588827 ps
CPU time 12.12 seconds
Started Mar 12 01:05:05 PM PDT 24
Finished Mar 12 01:05:18 PM PDT 24
Peak memory 214536 kb
Host smart-f0274950-d164-49b4-a8f3-9df8bbf44e58
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161946384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shadow
_reg_errors.161946384
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.2175541719
Short name T915
Test name
Test status
Simulation time 915066030 ps
CPU time 6.21 seconds
Started Mar 12 01:05:05 PM PDT 24
Finished Mar 12 01:05:11 PM PDT 24
Peak memory 214516 kb
Host smart-6e30a85b-b6f9-45f3-bf99-ed51a27b78c5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175541719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.2175541719
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.3165796091
Short name T1040
Test name
Test status
Simulation time 270603419 ps
CPU time 3.86 seconds
Started Mar 12 01:05:09 PM PDT 24
Finished Mar 12 01:05:13 PM PDT 24
Peak memory 214164 kb
Host smart-7bb5ab57-d6d7-44eb-9638-671a07187cd0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3165796091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.3165796091
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.3636002114
Short name T936
Test name
Test status
Simulation time 16584573 ps
CPU time 0.75 seconds
Started Mar 12 01:05:32 PM PDT 24
Finished Mar 12 01:05:34 PM PDT 24
Peak memory 205680 kb
Host smart-d9c75535-9dce-47ff-ba10-e5845779f30b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636002114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.3636002114
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.1977382576
Short name T897
Test name
Test status
Simulation time 14492691 ps
CPU time 0.97 seconds
Started Mar 12 01:05:37 PM PDT 24
Finished Mar 12 01:05:38 PM PDT 24
Peak memory 205744 kb
Host smart-17cd13ec-adfd-493f-b076-a52dffbe57f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977382576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.1977382576
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.1435370640
Short name T894
Test name
Test status
Simulation time 19120818 ps
CPU time 0.86 seconds
Started Mar 12 01:05:37 PM PDT 24
Finished Mar 12 01:05:38 PM PDT 24
Peak memory 205644 kb
Host smart-9d86ef2f-b312-41d2-b9f0-23e91400a00a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1435370640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.1435370640
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.3015862686
Short name T924
Test name
Test status
Simulation time 15765534 ps
CPU time 0.94 seconds
Started Mar 12 01:05:33 PM PDT 24
Finished Mar 12 01:05:35 PM PDT 24
Peak memory 205836 kb
Host smart-44d9899b-2c2f-4cda-a624-98a8d5096633
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3015862686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.3015862686
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.1186038779
Short name T916
Test name
Test status
Simulation time 34623699 ps
CPU time 0.83 seconds
Started Mar 12 01:05:34 PM PDT 24
Finished Mar 12 01:05:36 PM PDT 24
Peak memory 205644 kb
Host smart-0d096252-e4e2-49b6-8edf-ffac027ed0a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1186038779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.1186038779
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.3596213393
Short name T1062
Test name
Test status
Simulation time 27224154 ps
CPU time 0.78 seconds
Started Mar 12 01:05:33 PM PDT 24
Finished Mar 12 01:05:35 PM PDT 24
Peak memory 205672 kb
Host smart-91034002-7d69-4f97-ab03-6f5c8443aac6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596213393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.3596213393
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.2727013728
Short name T987
Test name
Test status
Simulation time 19970825 ps
CPU time 0.78 seconds
Started Mar 12 01:05:39 PM PDT 24
Finished Mar 12 01:05:40 PM PDT 24
Peak memory 205632 kb
Host smart-bde8621d-2e9b-4d48-91a4-91c6e44dff79
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727013728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.2727013728
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.2437889469
Short name T1022
Test name
Test status
Simulation time 36931510 ps
CPU time 0.73 seconds
Started Mar 12 01:05:34 PM PDT 24
Finished Mar 12 01:05:36 PM PDT 24
Peak memory 205644 kb
Host smart-9d91fca5-546c-4685-8301-92fb1a9da00b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2437889469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.2437889469
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.694903331
Short name T969
Test name
Test status
Simulation time 44788423 ps
CPU time 0.73 seconds
Started Mar 12 01:05:31 PM PDT 24
Finished Mar 12 01:05:33 PM PDT 24
Peak memory 205656 kb
Host smart-d1656446-4c44-438a-ae13-843f6994c900
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694903331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.694903331
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.2203099459
Short name T981
Test name
Test status
Simulation time 23606933 ps
CPU time 0.71 seconds
Started Mar 12 01:05:52 PM PDT 24
Finished Mar 12 01:05:53 PM PDT 24
Peak memory 205584 kb
Host smart-24baf417-07bd-4801-b56f-3b2a15c7559a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203099459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.2203099459
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.4128083653
Short name T163
Test name
Test status
Simulation time 978878722 ps
CPU time 10.97 seconds
Started Mar 12 01:05:15 PM PDT 24
Finished Mar 12 01:05:26 PM PDT 24
Peak memory 206048 kb
Host smart-13df0e89-5e77-4838-ae21-bd43bf74148f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128083653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.4
128083653
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.871873274
Short name T1038
Test name
Test status
Simulation time 673540124 ps
CPU time 15.31 seconds
Started Mar 12 01:05:13 PM PDT 24
Finished Mar 12 01:05:28 PM PDT 24
Peak memory 206116 kb
Host smart-400e5d65-2d9e-46a5-b6b4-2d352cc1d46c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=871873274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.871873274
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.1476170758
Short name T938
Test name
Test status
Simulation time 68237515 ps
CPU time 1.14 seconds
Started Mar 12 01:05:13 PM PDT 24
Finished Mar 12 01:05:14 PM PDT 24
Peak memory 205984 kb
Host smart-7811cd1f-e922-428b-bd9b-57eff62f9623
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1476170758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.1
476170758
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.2431981996
Short name T956
Test name
Test status
Simulation time 55356343 ps
CPU time 1.49 seconds
Started Mar 12 01:05:10 PM PDT 24
Finished Mar 12 01:05:12 PM PDT 24
Peak memory 214268 kb
Host smart-9a29e3fa-2730-45e8-a83d-a042d58e558e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2431981996 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.2431981996
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.1659576280
Short name T918
Test name
Test status
Simulation time 11359144 ps
CPU time 1.03 seconds
Started Mar 12 01:05:13 PM PDT 24
Finished Mar 12 01:05:14 PM PDT 24
Peak memory 205988 kb
Host smart-1ffc1ed4-3928-4f57-9d14-2f388f0df2ee
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1659576280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.1659576280
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.3314795529
Short name T946
Test name
Test status
Simulation time 37242463 ps
CPU time 0.81 seconds
Started Mar 12 01:05:06 PM PDT 24
Finished Mar 12 01:05:07 PM PDT 24
Peak memory 205716 kb
Host smart-a9316e54-2dda-478d-b082-06f31ee64651
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3314795529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.3314795529
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.799677079
Short name T945
Test name
Test status
Simulation time 92539496 ps
CPU time 3.37 seconds
Started Mar 12 01:05:04 PM PDT 24
Finished Mar 12 01:05:08 PM PDT 24
Peak memory 206084 kb
Host smart-7cff89b7-8e57-4fd4-bbd2-334dab944a03
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799677079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sam
e_csr_outstanding.799677079
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.3337420393
Short name T908
Test name
Test status
Simulation time 327613799 ps
CPU time 7.56 seconds
Started Mar 12 01:05:13 PM PDT 24
Finished Mar 12 01:05:21 PM PDT 24
Peak memory 214536 kb
Host smart-022d7613-3fc2-4125-9ce0-beb4ac962b09
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3337420393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.3337420393
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.1571624797
Short name T118
Test name
Test status
Simulation time 224144891 ps
CPU time 7.55 seconds
Started Mar 12 01:05:06 PM PDT 24
Finished Mar 12 01:05:14 PM PDT 24
Peak memory 214764 kb
Host smart-cef73713-2da3-4999-a461-84483f6a1ca0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1571624797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.1571624797
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.630961163
Short name T900
Test name
Test status
Simulation time 54948640 ps
CPU time 1.84 seconds
Started Mar 12 01:05:15 PM PDT 24
Finished Mar 12 01:05:17 PM PDT 24
Peak memory 216136 kb
Host smart-c6200a0e-f98c-4e76-94f6-565e356c440e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630961163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.630961163
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.2884008923
Short name T1032
Test name
Test status
Simulation time 396417306 ps
CPU time 4.94 seconds
Started Mar 12 01:05:13 PM PDT 24
Finished Mar 12 01:05:18 PM PDT 24
Peak memory 209360 kb
Host smart-7333164f-6987-4f5e-9b37-6ef473578881
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884008923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err
.2884008923
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.1899684039
Short name T988
Test name
Test status
Simulation time 10674578 ps
CPU time 0.7 seconds
Started Mar 12 01:05:50 PM PDT 24
Finished Mar 12 01:05:51 PM PDT 24
Peak memory 205704 kb
Host smart-3a91525f-0b65-4edd-9a2a-7adb66c71d24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899684039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.1899684039
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.2314205537
Short name T980
Test name
Test status
Simulation time 20197574 ps
CPU time 0.71 seconds
Started Mar 12 01:05:49 PM PDT 24
Finished Mar 12 01:05:50 PM PDT 24
Peak memory 205704 kb
Host smart-8443267a-833f-4994-8fbb-c88f3eb9a81d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314205537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.2314205537
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.2961086301
Short name T1058
Test name
Test status
Simulation time 30405814 ps
CPU time 1 seconds
Started Mar 12 01:05:51 PM PDT 24
Finished Mar 12 01:05:52 PM PDT 24
Peak memory 205876 kb
Host smart-0faae564-ed9c-474d-98b6-808b827b27d8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2961086301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.2961086301
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.1444545443
Short name T926
Test name
Test status
Simulation time 28602679 ps
CPU time 0.79 seconds
Started Mar 12 01:05:45 PM PDT 24
Finished Mar 12 01:05:46 PM PDT 24
Peak memory 205672 kb
Host smart-54e412bf-c13d-4f1c-8ca2-9802b86a8a69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444545443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.1444545443
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.3974866796
Short name T1063
Test name
Test status
Simulation time 13762280 ps
CPU time 0.88 seconds
Started Mar 12 01:05:43 PM PDT 24
Finished Mar 12 01:05:44 PM PDT 24
Peak memory 205736 kb
Host smart-a84c5772-9ce3-4f38-8b92-8fb59cd80f69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974866796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.3974866796
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.1836559979
Short name T1033
Test name
Test status
Simulation time 37602669 ps
CPU time 0.71 seconds
Started Mar 12 01:05:49 PM PDT 24
Finished Mar 12 01:05:50 PM PDT 24
Peak memory 205680 kb
Host smart-0ab84827-21be-4a9b-914e-baf7bcee3e32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836559979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.1836559979
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.955738090
Short name T892
Test name
Test status
Simulation time 127883163 ps
CPU time 0.87 seconds
Started Mar 12 01:05:50 PM PDT 24
Finished Mar 12 01:05:51 PM PDT 24
Peak memory 205724 kb
Host smart-24074ff8-4f92-4a8a-94bf-d4f44f4ba733
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=955738090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.955738090
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.2157115522
Short name T1053
Test name
Test status
Simulation time 46529969 ps
CPU time 0.87 seconds
Started Mar 12 01:05:46 PM PDT 24
Finished Mar 12 01:05:47 PM PDT 24
Peak memory 205604 kb
Host smart-099ab5ab-9ae5-49e2-8bf2-a692f7e42a01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2157115522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.2157115522
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.3351277650
Short name T978
Test name
Test status
Simulation time 29556078 ps
CPU time 0.72 seconds
Started Mar 12 01:05:38 PM PDT 24
Finished Mar 12 01:05:39 PM PDT 24
Peak memory 205704 kb
Host smart-b7de1284-6bdf-4d2d-8cec-be19390e874e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351277650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.3351277650
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.1952414005
Short name T967
Test name
Test status
Simulation time 8929186 ps
CPU time 0.71 seconds
Started Mar 12 01:05:54 PM PDT 24
Finished Mar 12 01:05:55 PM PDT 24
Peak memory 205704 kb
Host smart-f266e24a-a722-4fc1-9af0-778c6de49c2b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952414005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.1952414005
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.2930643121
Short name T986
Test name
Test status
Simulation time 367775397 ps
CPU time 9.83 seconds
Started Mar 12 01:05:03 PM PDT 24
Finished Mar 12 01:05:14 PM PDT 24
Peak memory 205900 kb
Host smart-97872e0c-b15e-4a6c-b098-025a9c9609bc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930643121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.2
930643121
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.391911433
Short name T1061
Test name
Test status
Simulation time 256921603 ps
CPU time 11.7 seconds
Started Mar 12 01:05:10 PM PDT 24
Finished Mar 12 01:05:22 PM PDT 24
Peak memory 205972 kb
Host smart-01d62154-fc8e-46ce-be49-9fabf92ce66c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=391911433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.391911433
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.1600288072
Short name T917
Test name
Test status
Simulation time 68726364 ps
CPU time 1.61 seconds
Started Mar 12 01:05:13 PM PDT 24
Finished Mar 12 01:05:15 PM PDT 24
Peak memory 205852 kb
Host smart-4b6aa339-b9e4-43e2-9d9e-fd0bc101dbe9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600288072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.1
600288072
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.3057279250
Short name T972
Test name
Test status
Simulation time 21167474 ps
CPU time 1.33 seconds
Started Mar 12 01:05:12 PM PDT 24
Finished Mar 12 01:05:14 PM PDT 24
Peak memory 214304 kb
Host smart-c31de098-5634-4122-b682-33fdf20aff8a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057279250 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.3057279250
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.2446851717
Short name T1004
Test name
Test status
Simulation time 163950053 ps
CPU time 1.12 seconds
Started Mar 12 01:05:04 PM PDT 24
Finished Mar 12 01:05:06 PM PDT 24
Peak memory 206008 kb
Host smart-474032b4-7f28-45f3-9dbc-2c2dff386843
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446851717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.2446851717
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.779439758
Short name T914
Test name
Test status
Simulation time 16205261 ps
CPU time 0.76 seconds
Started Mar 12 01:05:06 PM PDT 24
Finished Mar 12 01:05:07 PM PDT 24
Peak memory 205620 kb
Host smart-cea9d855-0750-494e-9dd4-fdb1914855c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=779439758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.779439758
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.4123887085
Short name T982
Test name
Test status
Simulation time 200140315 ps
CPU time 1.7 seconds
Started Mar 12 01:05:06 PM PDT 24
Finished Mar 12 01:05:08 PM PDT 24
Peak memory 205844 kb
Host smart-3b2e1d9a-71e8-475a-bdfc-a9fafc6a15b4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123887085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.4123887085
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.3357691127
Short name T1048
Test name
Test status
Simulation time 694972876 ps
CPU time 4.68 seconds
Started Mar 12 01:05:12 PM PDT 24
Finished Mar 12 01:05:17 PM PDT 24
Peak memory 214532 kb
Host smart-f2bd41e5-6e98-46ca-b759-89921512b52d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3357691127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.3357691127
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.2849295944
Short name T985
Test name
Test status
Simulation time 826550478 ps
CPU time 9.37 seconds
Started Mar 12 01:05:13 PM PDT 24
Finished Mar 12 01:05:23 PM PDT 24
Peak memory 214584 kb
Host smart-d39426a5-f436-4b7f-9555-2b58a10825a5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2849295944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.2849295944
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.412733798
Short name T935
Test name
Test status
Simulation time 41958870 ps
CPU time 2.83 seconds
Started Mar 12 01:05:13 PM PDT 24
Finished Mar 12 01:05:16 PM PDT 24
Peak memory 222328 kb
Host smart-e4a8eea7-5d01-4ba2-ba96-3a96635903b9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412733798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.412733798
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.3625373448
Short name T1029
Test name
Test status
Simulation time 12183363 ps
CPU time 0.7 seconds
Started Mar 12 01:05:45 PM PDT 24
Finished Mar 12 01:05:46 PM PDT 24
Peak memory 205728 kb
Host smart-de621404-688b-4833-b7b7-e284bf0b5a3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3625373448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.3625373448
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.2710159624
Short name T939
Test name
Test status
Simulation time 10164076 ps
CPU time 0.81 seconds
Started Mar 12 01:05:48 PM PDT 24
Finished Mar 12 01:05:49 PM PDT 24
Peak memory 205700 kb
Host smart-d0e58b92-6d1d-4a2d-af22-d6e6109f0a9c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2710159624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.2710159624
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.2141789295
Short name T925
Test name
Test status
Simulation time 15505686 ps
CPU time 0.89 seconds
Started Mar 12 01:05:48 PM PDT 24
Finished Mar 12 01:05:49 PM PDT 24
Peak memory 205876 kb
Host smart-df35bfd6-f604-4424-93a3-204a2d4163e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141789295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.2141789295
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.4196794140
Short name T1035
Test name
Test status
Simulation time 13165171 ps
CPU time 0.74 seconds
Started Mar 12 01:05:49 PM PDT 24
Finished Mar 12 01:05:50 PM PDT 24
Peak memory 205708 kb
Host smart-41a130cc-d1db-42e6-a50d-c748c61dccb3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4196794140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.4196794140
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.114939026
Short name T955
Test name
Test status
Simulation time 16320189 ps
CPU time 0.71 seconds
Started Mar 12 01:05:50 PM PDT 24
Finished Mar 12 01:05:51 PM PDT 24
Peak memory 205720 kb
Host smart-861021eb-f7dd-44f2-a5a0-d7080c05366b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114939026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.114939026
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.3427142892
Short name T1055
Test name
Test status
Simulation time 42376140 ps
CPU time 0.75 seconds
Started Mar 12 01:05:52 PM PDT 24
Finished Mar 12 01:05:53 PM PDT 24
Peak memory 205648 kb
Host smart-deaf6912-c17b-4306-8b51-48c58bbf5238
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427142892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.3427142892
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.2465338903
Short name T998
Test name
Test status
Simulation time 35809177 ps
CPU time 0.74 seconds
Started Mar 12 01:05:46 PM PDT 24
Finished Mar 12 01:05:47 PM PDT 24
Peak memory 205512 kb
Host smart-45cf354c-4d05-4f49-9931-9344ab6fb749
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465338903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.2465338903
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.3510873539
Short name T906
Test name
Test status
Simulation time 9856785 ps
CPU time 0.86 seconds
Started Mar 12 01:05:48 PM PDT 24
Finished Mar 12 01:05:49 PM PDT 24
Peak memory 205708 kb
Host smart-d1114324-d624-488f-b4be-434e373d51de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510873539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.3510873539
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.3631845296
Short name T1008
Test name
Test status
Simulation time 11397899 ps
CPU time 0.73 seconds
Started Mar 12 01:05:54 PM PDT 24
Finished Mar 12 01:05:55 PM PDT 24
Peak memory 205700 kb
Host smart-cf04e74b-0117-440a-b739-2e358c4493b9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631845296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.3631845296
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.3003618943
Short name T940
Test name
Test status
Simulation time 11727512 ps
CPU time 0.88 seconds
Started Mar 12 01:05:50 PM PDT 24
Finished Mar 12 01:05:51 PM PDT 24
Peak memory 205704 kb
Host smart-277a939d-2e5d-4f93-8d8c-cf4f0d6bcd45
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3003618943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.3003618943
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.739139055
Short name T1052
Test name
Test status
Simulation time 97564119 ps
CPU time 1.89 seconds
Started Mar 12 01:05:17 PM PDT 24
Finished Mar 12 01:05:19 PM PDT 24
Peak memory 205980 kb
Host smart-25642fc7-de47-49b4-bb9f-81011748cb04
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739139055 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.739139055
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.158110476
Short name T1021
Test name
Test status
Simulation time 84456500 ps
CPU time 1.37 seconds
Started Mar 12 01:05:16 PM PDT 24
Finished Mar 12 01:05:18 PM PDT 24
Peak memory 205972 kb
Host smart-ac2aa5ad-d76e-44ec-8791-c16350950423
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158110476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.158110476
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.4018804168
Short name T966
Test name
Test status
Simulation time 47919279 ps
CPU time 0.84 seconds
Started Mar 12 01:05:18 PM PDT 24
Finished Mar 12 01:05:19 PM PDT 24
Peak memory 205528 kb
Host smart-625ecceb-b6c3-4b6f-a210-ceab6f8da936
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018804168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.4018804168
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.2802097677
Short name T950
Test name
Test status
Simulation time 46320165 ps
CPU time 2.69 seconds
Started Mar 12 01:05:17 PM PDT 24
Finished Mar 12 01:05:20 PM PDT 24
Peak memory 205956 kb
Host smart-da592497-5a7e-4a1d-8574-d55e778bba53
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2802097677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.2802097677
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.1428455560
Short name T117
Test name
Test status
Simulation time 191361807 ps
CPU time 2.32 seconds
Started Mar 12 01:05:19 PM PDT 24
Finished Mar 12 01:05:21 PM PDT 24
Peak memory 222592 kb
Host smart-339cd2e9-5398-46c9-a5e2-152f0c20a136
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1428455560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.1428455560
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.271133411
Short name T954
Test name
Test status
Simulation time 1446704765 ps
CPU time 5 seconds
Started Mar 12 01:05:16 PM PDT 24
Finished Mar 12 01:05:21 PM PDT 24
Peak memory 214528 kb
Host smart-5d22b155-537c-4dfc-9b65-993e79101196
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=271133411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.k
eymgr_shadow_reg_errors_with_csr_rw.271133411
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.2820482647
Short name T912
Test name
Test status
Simulation time 426808076 ps
CPU time 3 seconds
Started Mar 12 01:05:17 PM PDT 24
Finished Mar 12 01:05:20 PM PDT 24
Peak memory 214248 kb
Host smart-6a5f9a57-0146-4050-b112-34e7b01651c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2820482647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.2820482647
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.1293895967
Short name T975
Test name
Test status
Simulation time 23638251 ps
CPU time 1.8 seconds
Started Mar 12 01:05:20 PM PDT 24
Finished Mar 12 01:05:22 PM PDT 24
Peak memory 214292 kb
Host smart-9ddb4785-8604-4e39-8275-c99d2a294017
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293895967 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.1293895967
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.1812197726
Short name T961
Test name
Test status
Simulation time 33412817 ps
CPU time 0.88 seconds
Started Mar 12 01:05:18 PM PDT 24
Finished Mar 12 01:05:19 PM PDT 24
Peak memory 205836 kb
Host smart-9081f10b-b996-4646-9e8e-ffa909a0eb9d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1812197726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.1812197726
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.3400636928
Short name T1045
Test name
Test status
Simulation time 10391469 ps
CPU time 0.84 seconds
Started Mar 12 01:05:18 PM PDT 24
Finished Mar 12 01:05:19 PM PDT 24
Peak memory 205660 kb
Host smart-21aa2b37-5073-49df-aae2-2dfcc04d2b60
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3400636928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.3400636928
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.3830715724
Short name T162
Test name
Test status
Simulation time 503665278 ps
CPU time 3.71 seconds
Started Mar 12 01:05:17 PM PDT 24
Finished Mar 12 01:05:21 PM PDT 24
Peak memory 205972 kb
Host smart-15bf7f34-7fbd-467a-a853-b1b0de70cca2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830715724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.3830715724
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.1822436959
Short name T930
Test name
Test status
Simulation time 525692331 ps
CPU time 3.03 seconds
Started Mar 12 01:05:17 PM PDT 24
Finished Mar 12 01:05:21 PM PDT 24
Peak memory 214384 kb
Host smart-27b244ce-3a30-428a-906f-9d3a86b0d781
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822436959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.1822436959
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.967020553
Short name T927
Test name
Test status
Simulation time 582533280 ps
CPU time 7.34 seconds
Started Mar 12 01:05:18 PM PDT 24
Finished Mar 12 01:05:25 PM PDT 24
Peak memory 214508 kb
Host smart-2751c266-ec94-4680-a77e-934350dceb73
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967020553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.k
eymgr_shadow_reg_errors_with_csr_rw.967020553
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.3852461847
Short name T970
Test name
Test status
Simulation time 131630385 ps
CPU time 2.46 seconds
Started Mar 12 01:05:20 PM PDT 24
Finished Mar 12 01:05:22 PM PDT 24
Peak memory 216356 kb
Host smart-2311faf1-c045-4975-8164-6844fc680129
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3852461847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.3852461847
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.1549596358
Short name T1015
Test name
Test status
Simulation time 116015939 ps
CPU time 1.29 seconds
Started Mar 12 01:05:19 PM PDT 24
Finished Mar 12 01:05:21 PM PDT 24
Peak memory 214284 kb
Host smart-c8d87e1c-8cec-45a2-b087-259bd2777ee7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549596358 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.1549596358
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.3169005810
Short name T1017
Test name
Test status
Simulation time 54252347 ps
CPU time 1.04 seconds
Started Mar 12 01:05:18 PM PDT 24
Finished Mar 12 01:05:19 PM PDT 24
Peak memory 205736 kb
Host smart-0a15e453-e377-418c-ae53-c1fe996658c3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169005810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.3169005810
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.2764714937
Short name T910
Test name
Test status
Simulation time 26234097 ps
CPU time 0.73 seconds
Started Mar 12 01:05:22 PM PDT 24
Finished Mar 12 01:05:23 PM PDT 24
Peak memory 205668 kb
Host smart-c4f0930b-67b1-43cd-a6bb-5829ea8a5bb0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764714937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.2764714937
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.4113327542
Short name T161
Test name
Test status
Simulation time 93308449 ps
CPU time 1.39 seconds
Started Mar 12 01:05:18 PM PDT 24
Finished Mar 12 01:05:20 PM PDT 24
Peak memory 206020 kb
Host smart-e9c359da-c89f-4615-83cf-081815d0c840
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113327542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.4113327542
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.1779869057
Short name T1007
Test name
Test status
Simulation time 299220752 ps
CPU time 1.88 seconds
Started Mar 12 01:05:18 PM PDT 24
Finished Mar 12 01:05:20 PM PDT 24
Peak memory 222540 kb
Host smart-67efd78f-e1c2-4261-8b71-63591ec941ea
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779869057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.1779869057
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.3976277013
Short name T1012
Test name
Test status
Simulation time 297627397 ps
CPU time 4.35 seconds
Started Mar 12 01:05:28 PM PDT 24
Finished Mar 12 01:05:34 PM PDT 24
Peak memory 214460 kb
Host smart-aa9e9819-c366-4515-90b5-1561133bc55f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976277013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
keymgr_shadow_reg_errors_with_csr_rw.3976277013
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.3947853992
Short name T931
Test name
Test status
Simulation time 221959908 ps
CPU time 3.84 seconds
Started Mar 12 01:05:16 PM PDT 24
Finished Mar 12 01:05:20 PM PDT 24
Peak memory 214196 kb
Host smart-2b03fd2b-2c6b-425a-b8f3-f75269e89d22
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3947853992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.3947853992
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.1741784486
Short name T406
Test name
Test status
Simulation time 287876055 ps
CPU time 6.89 seconds
Started Mar 12 01:05:18 PM PDT 24
Finished Mar 12 01:05:25 PM PDT 24
Peak memory 209384 kb
Host smart-6dd0a479-74c2-4676-8071-1a1cc299efc2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741784486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.1741784486
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.1351917295
Short name T962
Test name
Test status
Simulation time 185997206 ps
CPU time 1.32 seconds
Started Mar 12 01:05:20 PM PDT 24
Finished Mar 12 01:05:21 PM PDT 24
Peak memory 214280 kb
Host smart-7c51ca51-366d-4ccc-924e-8ac3f62aa00f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351917295 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.1351917295
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.2132962133
Short name T997
Test name
Test status
Simulation time 29273692 ps
CPU time 1.19 seconds
Started Mar 12 01:05:18 PM PDT 24
Finished Mar 12 01:05:20 PM PDT 24
Peak memory 205980 kb
Host smart-822e58b2-a7e1-4dd1-a3bc-12799ce7d0ec
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132962133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.2132962133
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.2973869869
Short name T941
Test name
Test status
Simulation time 15820599 ps
CPU time 0.87 seconds
Started Mar 12 01:05:22 PM PDT 24
Finished Mar 12 01:05:23 PM PDT 24
Peak memory 205704 kb
Host smart-07c1c555-c092-449a-a76a-8b0a16f218f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973869869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.2973869869
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.1664027744
Short name T1019
Test name
Test status
Simulation time 36759159 ps
CPU time 2.17 seconds
Started Mar 12 01:05:25 PM PDT 24
Finished Mar 12 01:05:28 PM PDT 24
Peak memory 206076 kb
Host smart-117fdf22-e1e4-445f-9efd-52b3f3221dde
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1664027744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.1664027744
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.1495066339
Short name T1003
Test name
Test status
Simulation time 257095055 ps
CPU time 1.64 seconds
Started Mar 12 01:05:18 PM PDT 24
Finished Mar 12 01:05:20 PM PDT 24
Peak memory 214528 kb
Host smart-2af2683e-6f81-45f1-a2a6-4fe3426601fb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1495066339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.1495066339
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.3771511525
Short name T1036
Test name
Test status
Simulation time 702291812 ps
CPU time 4.69 seconds
Started Mar 12 01:05:17 PM PDT 24
Finished Mar 12 01:05:22 PM PDT 24
Peak memory 214616 kb
Host smart-c4e97714-1471-4fab-9d9e-81b8cf34ed0f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771511525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
keymgr_shadow_reg_errors_with_csr_rw.3771511525
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.1613740416
Short name T901
Test name
Test status
Simulation time 81252329 ps
CPU time 3.08 seconds
Started Mar 12 01:05:20 PM PDT 24
Finished Mar 12 01:05:24 PM PDT 24
Peak memory 215312 kb
Host smart-44ed3c95-a046-4e82-a42b-faa98a4963d9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1613740416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.1613740416
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.1325771611
Short name T183
Test name
Test status
Simulation time 141842771 ps
CPU time 6.29 seconds
Started Mar 12 01:05:19 PM PDT 24
Finished Mar 12 01:05:25 PM PDT 24
Peak memory 209544 kb
Host smart-b7ee0b3d-a833-4500-9cc1-4f3a75c9627b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1325771611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.1325771611
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.3689260213
Short name T1002
Test name
Test status
Simulation time 55454238 ps
CPU time 1.23 seconds
Started Mar 12 01:05:21 PM PDT 24
Finished Mar 12 01:05:22 PM PDT 24
Peak memory 205976 kb
Host smart-82f6403d-01f9-42d4-b0b7-b1c0511ff70f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3689260213 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.3689260213
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.3496198193
Short name T1026
Test name
Test status
Simulation time 15155593 ps
CPU time 1.26 seconds
Started Mar 12 01:05:20 PM PDT 24
Finished Mar 12 01:05:22 PM PDT 24
Peak memory 205996 kb
Host smart-2b19c7be-f70a-48a8-942f-9222b9c40ef3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496198193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.3496198193
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.445451419
Short name T899
Test name
Test status
Simulation time 17990171 ps
CPU time 0.78 seconds
Started Mar 12 01:05:18 PM PDT 24
Finished Mar 12 01:05:19 PM PDT 24
Peak memory 205632 kb
Host smart-8f22cb40-824d-45d8-9123-f4a772989204
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445451419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.445451419
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.40135349
Short name T1054
Test name
Test status
Simulation time 204141852 ps
CPU time 2.25 seconds
Started Mar 12 01:05:22 PM PDT 24
Finished Mar 12 01:05:24 PM PDT 24
Peak memory 205956 kb
Host smart-aec14f05-a19a-4557-ad39-c11e218a2770
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40135349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_same
_csr_outstanding.40135349
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.1991872169
Short name T1028
Test name
Test status
Simulation time 214859859 ps
CPU time 2.52 seconds
Started Mar 12 01:05:25 PM PDT 24
Finished Mar 12 01:05:28 PM PDT 24
Peak memory 214512 kb
Host smart-da3e7b3f-070f-400a-a4c6-b59131106804
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1991872169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.1991872169
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.158191080
Short name T1010
Test name
Test status
Simulation time 3747379766 ps
CPU time 10.43 seconds
Started Mar 12 01:05:19 PM PDT 24
Finished Mar 12 01:05:29 PM PDT 24
Peak memory 214632 kb
Host smart-5135c091-68b1-4ed0-a0a0-0e423f963238
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=158191080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.k
eymgr_shadow_reg_errors_with_csr_rw.158191080
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.1999316498
Short name T893
Test name
Test status
Simulation time 143082054 ps
CPU time 5.09 seconds
Started Mar 12 01:05:18 PM PDT 24
Finished Mar 12 01:05:24 PM PDT 24
Peak memory 214264 kb
Host smart-bcb8679d-dacd-4513-976b-1d63e3978512
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1999316498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.1999316498
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.2049212756
Short name T191
Test name
Test status
Simulation time 119954863 ps
CPU time 5.44 seconds
Started Mar 12 01:05:20 PM PDT 24
Finished Mar 12 01:05:26 PM PDT 24
Peak memory 209624 kb
Host smart-2568aaaf-47dd-4e0a-a7d4-38be048a83c0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2049212756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.2049212756
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.2324747805
Short name T552
Test name
Test status
Simulation time 69298163 ps
CPU time 0.86 seconds
Started Mar 12 01:54:01 PM PDT 24
Finished Mar 12 01:54:02 PM PDT 24
Peak memory 206172 kb
Host smart-e1dad771-423e-4484-b77d-671ffcc8f487
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2324747805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.2324747805
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.138433517
Short name T65
Test name
Test status
Simulation time 49097336 ps
CPU time 2.4 seconds
Started Mar 12 01:53:56 PM PDT 24
Finished Mar 12 01:53:59 PM PDT 24
Peak memory 210156 kb
Host smart-40064dfd-cf5e-432b-937d-2db5973e5491
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138433517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.138433517
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.3559915406
Short name T386
Test name
Test status
Simulation time 75817741 ps
CPU time 3.88 seconds
Started Mar 12 01:53:50 PM PDT 24
Finished Mar 12 01:53:56 PM PDT 24
Peak memory 207520 kb
Host smart-951755a9-5ca4-4d0f-9547-e3c1fc93856f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559915406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.3559915406
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.1772505649
Short name T670
Test name
Test status
Simulation time 283461793 ps
CPU time 3.35 seconds
Started Mar 12 01:53:50 PM PDT 24
Finished Mar 12 01:53:54 PM PDT 24
Peak memory 209840 kb
Host smart-d9575c92-8027-4083-9c47-6ccc4e63c12d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772505649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.1772505649
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.2121493546
Short name T816
Test name
Test status
Simulation time 3547729886 ps
CPU time 10.86 seconds
Started Mar 12 01:53:58 PM PDT 24
Finished Mar 12 01:54:10 PM PDT 24
Peak memory 210244 kb
Host smart-dfe42ae4-d80e-494a-857b-09bbe914da2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121493546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.2121493546
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.824189110
Short name T12
Test name
Test status
Simulation time 1036402619 ps
CPU time 28.84 seconds
Started Mar 12 01:53:59 PM PDT 24
Finished Mar 12 01:54:29 PM PDT 24
Peak memory 239972 kb
Host smart-f0bd7f82-3c98-4667-a8b7-c99871000a17
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824189110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.824189110
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload.1273009710
Short name T565
Test name
Test status
Simulation time 133873346 ps
CPU time 4.52 seconds
Started Mar 12 01:53:50 PM PDT 24
Finished Mar 12 01:53:56 PM PDT 24
Peak memory 206800 kb
Host smart-64c42090-7155-47cf-98f1-02f147f78e24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273009710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.1273009710
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.672716650
Short name T503
Test name
Test status
Simulation time 57163612 ps
CPU time 3.27 seconds
Started Mar 12 01:53:53 PM PDT 24
Finished Mar 12 01:53:58 PM PDT 24
Peak memory 206908 kb
Host smart-e39a71df-876f-4ffb-b039-2248a98ea64d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=672716650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.672716650
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.2827468600
Short name T668
Test name
Test status
Simulation time 128073508 ps
CPU time 3.3 seconds
Started Mar 12 01:53:57 PM PDT 24
Finished Mar 12 01:54:01 PM PDT 24
Peak memory 206808 kb
Host smart-db1cbc3f-0749-44c4-8ce4-f0cc0ee8124c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2827468600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.2827468600
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.4156091122
Short name T455
Test name
Test status
Simulation time 339859650 ps
CPU time 9.1 seconds
Started Mar 12 01:53:49 PM PDT 24
Finished Mar 12 01:53:59 PM PDT 24
Peak memory 208092 kb
Host smart-4669e9f4-bcea-4dc4-8091-d8e89616f8b4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4156091122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.4156091122
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.2546548822
Short name T520
Test name
Test status
Simulation time 2372217969 ps
CPU time 16.96 seconds
Started Mar 12 01:53:57 PM PDT 24
Finished Mar 12 01:54:15 PM PDT 24
Peak memory 221520 kb
Host smart-19afe2af-a36d-401c-9728-75e532371d50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546548822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.2546548822
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.2007114899
Short name T545
Test name
Test status
Simulation time 42998679 ps
CPU time 2.75 seconds
Started Mar 12 01:53:51 PM PDT 24
Finished Mar 12 01:53:55 PM PDT 24
Peak memory 208724 kb
Host smart-697b47de-62e9-4101-9476-9d3da56b2320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007114899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.2007114899
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all_with_rand_reset.2884795487
Short name T180
Test name
Test status
Simulation time 712987217 ps
CPU time 9.6 seconds
Started Mar 12 01:53:59 PM PDT 24
Finished Mar 12 01:54:10 PM PDT 24
Peak memory 222880 kb
Host smart-bca7b67d-17da-4871-ae79-b21cfd1211b2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2884795487 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all_with_rand_reset.2884795487
Directory /workspace/0.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.771089039
Short name T747
Test name
Test status
Simulation time 1469646017 ps
CPU time 6.49 seconds
Started Mar 12 01:53:51 PM PDT 24
Finished Mar 12 01:53:59 PM PDT 24
Peak memory 209712 kb
Host smart-a41120c7-f273-4442-a81d-8d251c094d5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771089039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.771089039
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.4008914406
Short name T203
Test name
Test status
Simulation time 65395843 ps
CPU time 3.71 seconds
Started Mar 12 01:53:58 PM PDT 24
Finished Mar 12 01:54:02 PM PDT 24
Peak memory 209756 kb
Host smart-e92d8ee7-47b2-4ae4-aee1-a05a2db7fe05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008914406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.4008914406
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.1165811147
Short name T567
Test name
Test status
Simulation time 199925753 ps
CPU time 0.79 seconds
Started Mar 12 01:54:26 PM PDT 24
Finished Mar 12 01:54:28 PM PDT 24
Peak memory 206108 kb
Host smart-a57c4f33-4a06-43d2-8023-c0aab44b622f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1165811147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.1165811147
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.1327451737
Short name T804
Test name
Test status
Simulation time 221727683 ps
CPU time 4.01 seconds
Started Mar 12 01:54:23 PM PDT 24
Finished Mar 12 01:54:28 PM PDT 24
Peak memory 221580 kb
Host smart-9611c6f8-5276-4874-8b56-c986535227af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327451737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.1327451737
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.256361284
Short name T76
Test name
Test status
Simulation time 76844753 ps
CPU time 2.08 seconds
Started Mar 12 01:54:10 PM PDT 24
Finished Mar 12 01:54:12 PM PDT 24
Peak memory 207880 kb
Host smart-0cb040da-5723-4b00-a930-96c3e77ca979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256361284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.256361284
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.99418535
Short name T866
Test name
Test status
Simulation time 190531933 ps
CPU time 5.18 seconds
Started Mar 12 01:54:11 PM PDT 24
Finished Mar 12 01:54:16 PM PDT 24
Peak memory 209192 kb
Host smart-da7fed3c-078c-4cb6-b569-6f7627fecb2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99418535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.99418535
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.1236414154
Short name T54
Test name
Test status
Simulation time 798735058 ps
CPU time 6.43 seconds
Started Mar 12 01:54:10 PM PDT 24
Finished Mar 12 01:54:16 PM PDT 24
Peak memory 222656 kb
Host smart-a9287985-a41a-45b2-80b9-9a1c0232a135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236414154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.1236414154
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.1087996738
Short name T706
Test name
Test status
Simulation time 513806764 ps
CPU time 7.09 seconds
Started Mar 12 01:54:12 PM PDT 24
Finished Mar 12 01:54:19 PM PDT 24
Peak memory 208988 kb
Host smart-f90f6343-e54b-4541-9d97-316084efeb2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087996738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.1087996738
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.19234252
Short name T14
Test name
Test status
Simulation time 1666232063 ps
CPU time 24.45 seconds
Started Mar 12 01:54:24 PM PDT 24
Finished Mar 12 01:54:49 PM PDT 24
Peak memory 230676 kb
Host smart-367d8cdc-5c17-4cf2-b6c2-e344e941bc68
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19234252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.19234252
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload.2701907902
Short name T678
Test name
Test status
Simulation time 1719741254 ps
CPU time 48.66 seconds
Started Mar 12 01:53:57 PM PDT 24
Finished Mar 12 01:54:47 PM PDT 24
Peak memory 208904 kb
Host smart-cbf58157-e7a1-4d49-bf87-f286e108c393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2701907902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.2701907902
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.2734605060
Short name T617
Test name
Test status
Simulation time 1594459743 ps
CPU time 9.96 seconds
Started Mar 12 01:54:01 PM PDT 24
Finished Mar 12 01:54:11 PM PDT 24
Peak memory 206960 kb
Host smart-05ba735c-82a8-419d-a2be-c95279d901ef
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734605060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.2734605060
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.919692232
Short name T641
Test name
Test status
Simulation time 249542943 ps
CPU time 2.78 seconds
Started Mar 12 01:53:58 PM PDT 24
Finished Mar 12 01:54:02 PM PDT 24
Peak memory 208692 kb
Host smart-3061d598-a05a-492f-aa4c-4c06e5a1988e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919692232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.919692232
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.2286743041
Short name T783
Test name
Test status
Simulation time 409776978 ps
CPU time 2.85 seconds
Started Mar 12 01:53:58 PM PDT 24
Finished Mar 12 01:54:02 PM PDT 24
Peak memory 207412 kb
Host smart-2f3f1b01-1340-4d9d-a7c7-9213ad67e69e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286743041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.2286743041
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.1146104219
Short name T522
Test name
Test status
Simulation time 37289973 ps
CPU time 1.89 seconds
Started Mar 12 01:54:23 PM PDT 24
Finished Mar 12 01:54:25 PM PDT 24
Peak memory 209640 kb
Host smart-de54f06d-81c6-4df0-91a8-3da5199f2df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146104219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.1146104219
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.2830576472
Short name T448
Test name
Test status
Simulation time 209306916 ps
CPU time 3.32 seconds
Started Mar 12 01:53:57 PM PDT 24
Finished Mar 12 01:54:01 PM PDT 24
Peak memory 208584 kb
Host smart-6b51ff05-16dc-458a-bd7e-965eb02282d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830576472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.2830576472
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.1594003730
Short name T484
Test name
Test status
Simulation time 463250290 ps
CPU time 4.97 seconds
Started Mar 12 01:54:11 PM PDT 24
Finished Mar 12 01:54:16 PM PDT 24
Peak memory 207724 kb
Host smart-39b367fa-04a8-418d-875a-38f1f7e6886c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1594003730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.1594003730
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.3687049492
Short name T187
Test name
Test status
Simulation time 126261664 ps
CPU time 4.26 seconds
Started Mar 12 01:54:24 PM PDT 24
Finished Mar 12 01:54:29 PM PDT 24
Peak memory 210136 kb
Host smart-3d0dc499-b862-41cc-bde7-bf629b9029e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3687049492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.3687049492
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.1269976302
Short name T319
Test name
Test status
Simulation time 113803772 ps
CPU time 3.95 seconds
Started Mar 12 01:56:06 PM PDT 24
Finished Mar 12 01:56:10 PM PDT 24
Peak memory 209380 kb
Host smart-0f3a21fa-d0ad-4138-9abe-6f8ba8db7a82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269976302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.1269976302
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.3815487001
Short name T158
Test name
Test status
Simulation time 70997956 ps
CPU time 3.7 seconds
Started Mar 12 01:56:04 PM PDT 24
Finished Mar 12 01:56:08 PM PDT 24
Peak memory 222604 kb
Host smart-62a7081b-d21a-4b22-bcb3-f21c83ce5d61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815487001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.3815487001
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.2648103765
Short name T530
Test name
Test status
Simulation time 180972141 ps
CPU time 2.99 seconds
Started Mar 12 01:55:54 PM PDT 24
Finished Mar 12 01:55:57 PM PDT 24
Peak memory 209808 kb
Host smart-a58c2b4b-0e5c-445c-83f2-5028543434bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648103765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.2648103765
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.239472607
Short name T307
Test name
Test status
Simulation time 163197411 ps
CPU time 2.52 seconds
Started Mar 12 01:55:53 PM PDT 24
Finished Mar 12 01:55:56 PM PDT 24
Peak memory 206632 kb
Host smart-703336ec-6998-4c95-a28a-1006334607cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=239472607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.239472607
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.3820539846
Short name T526
Test name
Test status
Simulation time 301144936 ps
CPU time 3.87 seconds
Started Mar 12 01:55:56 PM PDT 24
Finished Mar 12 01:56:00 PM PDT 24
Peak memory 208772 kb
Host smart-4f93c69e-ee53-4952-bc26-b7a52eea8f74
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820539846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.3820539846
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.2598533583
Short name T467
Test name
Test status
Simulation time 127355751 ps
CPU time 2.55 seconds
Started Mar 12 01:55:52 PM PDT 24
Finished Mar 12 01:55:55 PM PDT 24
Peak memory 208852 kb
Host smart-15158f7a-6168-466f-8f9f-a89c611c437c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598533583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.2598533583
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.171304231
Short name T720
Test name
Test status
Simulation time 91395419 ps
CPU time 3.7 seconds
Started Mar 12 01:55:53 PM PDT 24
Finished Mar 12 01:55:57 PM PDT 24
Peak memory 206640 kb
Host smart-d9b0ab6d-6d35-4eb4-bb2b-47980a9cfe78
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171304231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.171304231
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.3430620710
Short name T477
Test name
Test status
Simulation time 388965440 ps
CPU time 3 seconds
Started Mar 12 01:56:04 PM PDT 24
Finished Mar 12 01:56:07 PM PDT 24
Peak memory 216100 kb
Host smart-a12b6ace-82a3-46ac-baa9-cb09bd5bc666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3430620710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.3430620710
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.381865714
Short name T634
Test name
Test status
Simulation time 54669296 ps
CPU time 2.68 seconds
Started Mar 12 01:55:52 PM PDT 24
Finished Mar 12 01:55:55 PM PDT 24
Peak memory 207816 kb
Host smart-758464a3-5ca2-4dc3-87ff-96f2ea84de83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381865714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.381865714
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.3791579032
Short name T868
Test name
Test status
Simulation time 889231142 ps
CPU time 34.87 seconds
Started Mar 12 01:56:03 PM PDT 24
Finished Mar 12 01:56:38 PM PDT 24
Peak memory 220584 kb
Host smart-80d7e92d-f8c5-4dc7-a882-97709a806613
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3791579032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.3791579032
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_stress_all_with_rand_reset.1786343022
Short name T133
Test name
Test status
Simulation time 595298541 ps
CPU time 9.89 seconds
Started Mar 12 01:56:08 PM PDT 24
Finished Mar 12 01:56:18 PM PDT 24
Peak memory 222848 kb
Host smart-6d9faa24-6a40-462b-bb26-496e9113b3e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786343022 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all_with_rand_reset.1786343022
Directory /workspace/10.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.3422469840
Short name T274
Test name
Test status
Simulation time 1941685074 ps
CPU time 8.98 seconds
Started Mar 12 01:56:03 PM PDT 24
Finished Mar 12 01:56:12 PM PDT 24
Peak memory 208080 kb
Host smart-27a2da0b-36aa-423e-a01a-70aadfae6e04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422469840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.3422469840
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.1318222215
Short name T513
Test name
Test status
Simulation time 402681549 ps
CPU time 3.09 seconds
Started Mar 12 01:56:04 PM PDT 24
Finished Mar 12 01:56:07 PM PDT 24
Peak memory 210320 kb
Host smart-ebaa8284-1dff-4a03-ad7d-35054cc63c7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318222215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.1318222215
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.3626224295
Short name T557
Test name
Test status
Simulation time 52027287 ps
CPU time 0.97 seconds
Started Mar 12 01:56:05 PM PDT 24
Finished Mar 12 01:56:06 PM PDT 24
Peak memory 206048 kb
Host smart-6a8a13a6-42ef-4d7d-a56c-b90521250ea3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626224295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.3626224295
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.3998329138
Short name T414
Test name
Test status
Simulation time 624789162 ps
CPU time 8.07 seconds
Started Mar 12 01:56:06 PM PDT 24
Finished Mar 12 01:56:14 PM PDT 24
Peak memory 214496 kb
Host smart-fbc184d2-ad19-473c-82a2-416e5dd7a7c2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3998329138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.3998329138
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.1823841744
Short name T517
Test name
Test status
Simulation time 66984859 ps
CPU time 2.26 seconds
Started Mar 12 01:56:04 PM PDT 24
Finished Mar 12 01:56:06 PM PDT 24
Peak memory 209340 kb
Host smart-7e4b4b52-1b24-4c3a-af66-61c3bf66cf0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1823841744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.1823841744
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.2418196561
Short name T218
Test name
Test status
Simulation time 501086011 ps
CPU time 5.74 seconds
Started Mar 12 01:56:04 PM PDT 24
Finished Mar 12 01:56:10 PM PDT 24
Peak memory 214492 kb
Host smart-d694383a-3465-48b2-8f2e-acf3c02a5e7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418196561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.2418196561
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.83783167
Short name T882
Test name
Test status
Simulation time 83932708 ps
CPU time 4.3 seconds
Started Mar 12 01:56:03 PM PDT 24
Finished Mar 12 01:56:08 PM PDT 24
Peak memory 220344 kb
Host smart-e587ac4d-fba1-4fd2-8ee3-23a5d14677a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83783167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.83783167
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.4095319577
Short name T458
Test name
Test status
Simulation time 148289221 ps
CPU time 5.68 seconds
Started Mar 12 01:56:07 PM PDT 24
Finished Mar 12 01:56:13 PM PDT 24
Peak memory 214540 kb
Host smart-e90c519d-fb39-499e-9ead-e97202716989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4095319577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.4095319577
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.4166493790
Short name T507
Test name
Test status
Simulation time 87958048 ps
CPU time 1.93 seconds
Started Mar 12 01:56:04 PM PDT 24
Finished Mar 12 01:56:06 PM PDT 24
Peak memory 206868 kb
Host smart-7df50f62-8c96-4395-b0be-f1439f597d7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166493790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.4166493790
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.3618709853
Short name T551
Test name
Test status
Simulation time 73610448 ps
CPU time 3.77 seconds
Started Mar 12 01:56:05 PM PDT 24
Finished Mar 12 01:56:09 PM PDT 24
Peak memory 208924 kb
Host smart-c65e3e5b-b740-448e-9210-a8a6fe572de6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618709853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.3618709853
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.883366351
Short name T794
Test name
Test status
Simulation time 605519857 ps
CPU time 5.47 seconds
Started Mar 12 01:56:06 PM PDT 24
Finished Mar 12 01:56:12 PM PDT 24
Peak memory 208756 kb
Host smart-da945035-61ad-463b-846d-3b53b4f75d24
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=883366351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.883366351
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.3665684354
Short name T77
Test name
Test status
Simulation time 275933460 ps
CPU time 3.53 seconds
Started Mar 12 01:56:07 PM PDT 24
Finished Mar 12 01:56:11 PM PDT 24
Peak memory 206872 kb
Host smart-739feb04-d45a-4b05-9d6e-d3e175b339ee
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665684354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.3665684354
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.1716240202
Short name T589
Test name
Test status
Simulation time 329739040 ps
CPU time 2.89 seconds
Started Mar 12 01:56:06 PM PDT 24
Finished Mar 12 01:56:09 PM PDT 24
Peak memory 209076 kb
Host smart-2b5059af-1a26-4e72-a4d0-04a507e46a30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1716240202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.1716240202
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.4082119457
Short name T602
Test name
Test status
Simulation time 105661935 ps
CPU time 4.2 seconds
Started Mar 12 01:56:05 PM PDT 24
Finished Mar 12 01:56:09 PM PDT 24
Peak memory 207140 kb
Host smart-113fe1c0-f7b5-42dd-b71c-90eddd925ab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4082119457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.4082119457
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.167787943
Short name T850
Test name
Test status
Simulation time 22780707027 ps
CPU time 243.58 seconds
Started Mar 12 01:56:06 PM PDT 24
Finished Mar 12 02:00:10 PM PDT 24
Peak memory 222856 kb
Host smart-be9fa2cc-29d3-48e3-967c-66eff5ace5aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167787943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.167787943
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.2482837979
Short name T657
Test name
Test status
Simulation time 81826939 ps
CPU time 2.67 seconds
Started Mar 12 01:56:06 PM PDT 24
Finished Mar 12 01:56:09 PM PDT 24
Peak memory 210220 kb
Host smart-e5499fc8-a6ac-4a62-a7d5-bc8b1b835418
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2482837979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.2482837979
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.2501291577
Short name T653
Test name
Test status
Simulation time 17140102 ps
CPU time 0.99 seconds
Started Mar 12 01:56:16 PM PDT 24
Finished Mar 12 01:56:17 PM PDT 24
Peak memory 206172 kb
Host smart-bc0f533c-eed1-46a0-89e8-e30f095e735d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501291577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.2501291577
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.281575772
Short name T156
Test name
Test status
Simulation time 141016655 ps
CPU time 5.21 seconds
Started Mar 12 01:56:19 PM PDT 24
Finished Mar 12 01:56:24 PM PDT 24
Peak memory 214428 kb
Host smart-91e355be-336b-4c5a-b478-c67b0915f7c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=281575772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.281575772
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.4068981013
Short name T619
Test name
Test status
Simulation time 277746527 ps
CPU time 3.46 seconds
Started Mar 12 01:56:14 PM PDT 24
Finished Mar 12 01:56:18 PM PDT 24
Peak memory 214564 kb
Host smart-e3b8db2b-f3c1-4898-85d2-a0d25781b95a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068981013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.4068981013
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.1169235835
Short name T278
Test name
Test status
Simulation time 422260953 ps
CPU time 1.56 seconds
Started Mar 12 01:56:15 PM PDT 24
Finished Mar 12 01:56:16 PM PDT 24
Peak memory 206852 kb
Host smart-98120518-d193-483d-b6d0-afc44f252400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1169235835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.1169235835
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.3194305108
Short name T662
Test name
Test status
Simulation time 1362727303 ps
CPU time 4.37 seconds
Started Mar 12 01:56:16 PM PDT 24
Finished Mar 12 01:56:20 PM PDT 24
Peak memory 218912 kb
Host smart-9e1f1231-a423-4bb7-b58d-6698f7d11e96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194305108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.3194305108
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.3990257095
Short name T577
Test name
Test status
Simulation time 49544411 ps
CPU time 2.64 seconds
Started Mar 12 01:56:13 PM PDT 24
Finished Mar 12 01:56:16 PM PDT 24
Peak memory 208916 kb
Host smart-797f09c1-8d19-4a66-945f-cb42d05c5b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990257095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.3990257095
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.409812195
Short name T751
Test name
Test status
Simulation time 140329109 ps
CPU time 6.05 seconds
Started Mar 12 01:56:17 PM PDT 24
Finished Mar 12 01:56:23 PM PDT 24
Peak memory 218472 kb
Host smart-5b013996-5131-4f5a-87e9-83e491a03bcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409812195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.409812195
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.3336160131
Short name T506
Test name
Test status
Simulation time 350124994 ps
CPU time 5.56 seconds
Started Mar 12 01:56:02 PM PDT 24
Finished Mar 12 01:56:08 PM PDT 24
Peak memory 207832 kb
Host smart-124c0e1e-de4c-414c-8255-f24f64e9dbe9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3336160131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.3336160131
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.1865154936
Short name T289
Test name
Test status
Simulation time 1046837168 ps
CPU time 5.42 seconds
Started Mar 12 01:56:14 PM PDT 24
Finished Mar 12 01:56:19 PM PDT 24
Peak memory 208820 kb
Host smart-0f66094b-88f4-4af3-887b-5ec7aa5d3294
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1865154936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.1865154936
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.1474098475
Short name T886
Test name
Test status
Simulation time 60754255 ps
CPU time 2.68 seconds
Started Mar 12 01:56:04 PM PDT 24
Finished Mar 12 01:56:06 PM PDT 24
Peak memory 206816 kb
Host smart-c8943516-d349-4b75-a705-688ca15d9b3e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474098475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.1474098475
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.1899530462
Short name T705
Test name
Test status
Simulation time 175456714 ps
CPU time 4.09 seconds
Started Mar 12 01:56:18 PM PDT 24
Finished Mar 12 01:56:22 PM PDT 24
Peak memory 208632 kb
Host smart-753b99d9-4319-43ac-84c4-6c1fe67d759c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899530462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.1899530462
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.4069690230
Short name T367
Test name
Test status
Simulation time 87840702 ps
CPU time 3.53 seconds
Started Mar 12 01:56:14 PM PDT 24
Finished Mar 12 01:56:17 PM PDT 24
Peak memory 208820 kb
Host smart-8d9f4b8c-3486-41c4-835a-71ac3d4cdfa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069690230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.4069690230
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.2391993346
Short name T800
Test name
Test status
Simulation time 91411458 ps
CPU time 1.75 seconds
Started Mar 12 01:56:06 PM PDT 24
Finished Mar 12 01:56:07 PM PDT 24
Peak memory 206652 kb
Host smart-7b5b7a8e-4a86-4720-9cc2-356db5b33639
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391993346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.2391993346
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.793981520
Short name T852
Test name
Test status
Simulation time 239324271 ps
CPU time 8.74 seconds
Started Mar 12 01:56:18 PM PDT 24
Finished Mar 12 01:56:27 PM PDT 24
Peak memory 209776 kb
Host smart-6f9b767b-865f-43d9-9c86-878da4b3aa05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793981520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.793981520
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.1023938085
Short name T144
Test name
Test status
Simulation time 87577008 ps
CPU time 3.11 seconds
Started Mar 12 01:56:17 PM PDT 24
Finished Mar 12 01:56:20 PM PDT 24
Peak memory 210436 kb
Host smart-bd1fe566-8ea8-4a72-9551-3317cbb7f94d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1023938085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.1023938085
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.4035512598
Short name T688
Test name
Test status
Simulation time 9261897 ps
CPU time 0.82 seconds
Started Mar 12 01:56:17 PM PDT 24
Finished Mar 12 01:56:19 PM PDT 24
Peak memory 206148 kb
Host smart-99d00a60-51fa-4672-bd74-3009609e12ae
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4035512598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.4035512598
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.3019792435
Short name T721
Test name
Test status
Simulation time 502541345 ps
CPU time 4.64 seconds
Started Mar 12 01:56:15 PM PDT 24
Finished Mar 12 01:56:20 PM PDT 24
Peak memory 221808 kb
Host smart-550826f9-0717-4dfa-be10-afb9b463dad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3019792435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.3019792435
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.3157537772
Short name T225
Test name
Test status
Simulation time 31290185 ps
CPU time 1.7 seconds
Started Mar 12 01:56:19 PM PDT 24
Finished Mar 12 01:56:21 PM PDT 24
Peak memory 207584 kb
Host smart-66e53559-2a23-46f8-ba6f-340353fd489d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3157537772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.3157537772
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.1808253531
Short name T839
Test name
Test status
Simulation time 1547507218 ps
CPU time 23.25 seconds
Started Mar 12 01:56:14 PM PDT 24
Finished Mar 12 01:56:37 PM PDT 24
Peak memory 209648 kb
Host smart-527747e7-6dc4-4e0e-8f7a-9f4caa7050dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808253531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.1808253531
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.83893535
Short name T594
Test name
Test status
Simulation time 262167557 ps
CPU time 8.65 seconds
Started Mar 12 01:56:15 PM PDT 24
Finished Mar 12 01:56:24 PM PDT 24
Peak memory 212420 kb
Host smart-4c354e5c-4fcd-4517-a809-ad1aa8862a68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83893535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.83893535
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.3543788466
Short name T374
Test name
Test status
Simulation time 537915964 ps
CPU time 4.41 seconds
Started Mar 12 01:56:20 PM PDT 24
Finished Mar 12 01:56:24 PM PDT 24
Peak memory 222668 kb
Host smart-868bd526-fcbb-40a9-a99f-3f438a042f54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543788466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.3543788466
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.626461394
Short name T701
Test name
Test status
Simulation time 241302529 ps
CPU time 3.38 seconds
Started Mar 12 01:56:15 PM PDT 24
Finished Mar 12 01:56:19 PM PDT 24
Peak memory 208332 kb
Host smart-5ce398f4-8fc0-49cf-b660-2172ee775084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=626461394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.626461394
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.3952970824
Short name T879
Test name
Test status
Simulation time 106011140 ps
CPU time 2.98 seconds
Started Mar 12 01:56:14 PM PDT 24
Finished Mar 12 01:56:17 PM PDT 24
Peak memory 206844 kb
Host smart-aa63e0f6-5d70-40e9-81a4-6671486b3c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952970824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.3952970824
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.2424051082
Short name T582
Test name
Test status
Simulation time 153122955 ps
CPU time 4.83 seconds
Started Mar 12 01:56:17 PM PDT 24
Finished Mar 12 01:56:22 PM PDT 24
Peak memory 207712 kb
Host smart-3bd00a87-27e1-490a-b366-c677c90283d6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424051082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.2424051082
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.1104923777
Short name T541
Test name
Test status
Simulation time 184178570 ps
CPU time 2.5 seconds
Started Mar 12 01:56:14 PM PDT 24
Finished Mar 12 01:56:17 PM PDT 24
Peak memory 207452 kb
Host smart-0b8917bc-613d-4981-9528-5b589192810a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1104923777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.1104923777
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.939997443
Short name T814
Test name
Test status
Simulation time 72717827 ps
CPU time 3.32 seconds
Started Mar 12 01:56:14 PM PDT 24
Finished Mar 12 01:56:17 PM PDT 24
Peak memory 206844 kb
Host smart-71c8bc20-04b7-4650-ae36-2cc5c0e0b199
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939997443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.939997443
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.366134178
Short name T268
Test name
Test status
Simulation time 386228130 ps
CPU time 9.13 seconds
Started Mar 12 01:56:15 PM PDT 24
Finished Mar 12 01:56:24 PM PDT 24
Peak memory 208640 kb
Host smart-c2cddde3-7891-4c99-8797-8fd42252f573
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366134178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.366134178
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.1949499397
Short name T782
Test name
Test status
Simulation time 79222977 ps
CPU time 2.35 seconds
Started Mar 12 01:56:14 PM PDT 24
Finished Mar 12 01:56:17 PM PDT 24
Peak memory 206476 kb
Host smart-28f50580-5c64-42c8-987f-d2538a284f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1949499397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.1949499397
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.3040704981
Short name T806
Test name
Test status
Simulation time 1329239246 ps
CPU time 50.85 seconds
Started Mar 12 01:56:17 PM PDT 24
Finished Mar 12 01:57:08 PM PDT 24
Peak memory 220684 kb
Host smart-0a8a0799-9a81-44e1-99ad-2234cdc88537
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040704981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.3040704981
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.2576893927
Short name T823
Test name
Test status
Simulation time 408851503 ps
CPU time 6.22 seconds
Started Mar 12 01:56:13 PM PDT 24
Finished Mar 12 01:56:20 PM PDT 24
Peak memory 214460 kb
Host smart-cfed2bbd-77d9-4e61-87a0-9a64b7b03e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576893927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.2576893927
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.1708043811
Short name T179
Test name
Test status
Simulation time 261320376 ps
CPU time 3.4 seconds
Started Mar 12 01:56:20 PM PDT 24
Finished Mar 12 01:56:23 PM PDT 24
Peak memory 210076 kb
Host smart-18076e24-7386-409a-9ef1-2fa5df8dea8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1708043811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.1708043811
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.1098074399
Short name T855
Test name
Test status
Simulation time 24086239 ps
CPU time 0.91 seconds
Started Mar 12 01:56:27 PM PDT 24
Finished Mar 12 01:56:28 PM PDT 24
Peak memory 206136 kb
Host smart-133c4e4b-4bae-4020-ad61-d9cce7719ce2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098074399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.1098074399
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.2847346681
Short name T711
Test name
Test status
Simulation time 1229515324 ps
CPU time 60.97 seconds
Started Mar 12 01:56:29 PM PDT 24
Finished Mar 12 01:57:30 PM PDT 24
Peak memory 215036 kb
Host smart-f6da135f-5016-43a6-bddb-6c7d86d92b11
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2847346681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.2847346681
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.3566835777
Short name T64
Test name
Test status
Simulation time 73414764 ps
CPU time 3.42 seconds
Started Mar 12 01:56:25 PM PDT 24
Finished Mar 12 01:56:29 PM PDT 24
Peak memory 221640 kb
Host smart-f12933d1-e253-4122-8235-19b4cc841407
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566835777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.3566835777
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.3422758905
Short name T637
Test name
Test status
Simulation time 25309355 ps
CPU time 1.93 seconds
Started Mar 12 01:56:25 PM PDT 24
Finished Mar 12 01:56:27 PM PDT 24
Peak memory 216236 kb
Host smart-572ca1b2-eacc-4058-a478-1dc6c1f58b18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3422758905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.3422758905
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.1764752939
Short name T739
Test name
Test status
Simulation time 113380660 ps
CPU time 2.2 seconds
Started Mar 12 01:56:24 PM PDT 24
Finished Mar 12 01:56:26 PM PDT 24
Peak memory 206520 kb
Host smart-ad2ccfa9-c864-46a8-ad4b-7b746fe6808f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1764752939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.1764752939
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.2121264201
Short name T202
Test name
Test status
Simulation time 3561483106 ps
CPU time 28.99 seconds
Started Mar 12 01:56:25 PM PDT 24
Finished Mar 12 01:56:54 PM PDT 24
Peak memory 209192 kb
Host smart-da6b1b55-85fa-46dc-9afa-6e853838da9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121264201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.2121264201
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.4062743105
Short name T230
Test name
Test status
Simulation time 52015949 ps
CPU time 2.75 seconds
Started Mar 12 01:56:26 PM PDT 24
Finished Mar 12 01:56:30 PM PDT 24
Peak memory 206824 kb
Host smart-cbeac961-69d9-4711-b87c-0cd1631d758a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062743105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.4062743105
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.658052747
Short name T834
Test name
Test status
Simulation time 383689529 ps
CPU time 5.47 seconds
Started Mar 12 01:56:29 PM PDT 24
Finished Mar 12 01:56:35 PM PDT 24
Peak memory 208360 kb
Host smart-4bbb6abc-8d5c-4256-9bae-5b419c8175af
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658052747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.658052747
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.1148792612
Short name T564
Test name
Test status
Simulation time 35498554 ps
CPU time 2.44 seconds
Started Mar 12 01:56:25 PM PDT 24
Finished Mar 12 01:56:27 PM PDT 24
Peak memory 208476 kb
Host smart-6eb2131e-e218-4c96-be38-5e432fb3f9de
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1148792612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.1148792612
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.1971986764
Short name T832
Test name
Test status
Simulation time 437919606 ps
CPU time 3.83 seconds
Started Mar 12 01:56:24 PM PDT 24
Finished Mar 12 01:56:28 PM PDT 24
Peak memory 208808 kb
Host smart-7d4d24ec-1deb-4dd3-b207-fc0a00842d87
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971986764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.1971986764
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.2151974909
Short name T692
Test name
Test status
Simulation time 44252316 ps
CPU time 1.74 seconds
Started Mar 12 01:56:30 PM PDT 24
Finished Mar 12 01:56:32 PM PDT 24
Peak memory 207332 kb
Host smart-d99b6f39-88f6-4b5a-91c4-dca331a1abc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2151974909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.2151974909
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.83456651
Short name T447
Test name
Test status
Simulation time 1902188573 ps
CPU time 20.63 seconds
Started Mar 12 01:56:15 PM PDT 24
Finished Mar 12 01:56:35 PM PDT 24
Peak memory 207776 kb
Host smart-3d1e6c64-262a-4ea3-9719-947b7f15fe7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=83456651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.83456651
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.1100862415
Short name T452
Test name
Test status
Simulation time 10506531546 ps
CPU time 21.34 seconds
Started Mar 12 01:56:27 PM PDT 24
Finished Mar 12 01:56:48 PM PDT 24
Peak memory 208760 kb
Host smart-b736c8ca-069e-4b04-9613-5cd86426fd5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1100862415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.1100862415
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.116249416
Short name T756
Test name
Test status
Simulation time 50490595 ps
CPU time 3.18 seconds
Started Mar 12 01:56:25 PM PDT 24
Finished Mar 12 01:56:28 PM PDT 24
Peak memory 208328 kb
Host smart-50857f4e-9f6a-414a-b0f2-fa8b24918ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116249416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.116249416
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.3913675794
Short name T408
Test name
Test status
Simulation time 203545526 ps
CPU time 1.95 seconds
Started Mar 12 01:56:23 PM PDT 24
Finished Mar 12 01:56:25 PM PDT 24
Peak memory 209756 kb
Host smart-64287ac1-39d7-4127-95d4-2843eea966f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3913675794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.3913675794
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.2831491151
Short name T523
Test name
Test status
Simulation time 29123511 ps
CPU time 0.95 seconds
Started Mar 12 01:56:35 PM PDT 24
Finished Mar 12 01:56:36 PM PDT 24
Peak memory 206220 kb
Host smart-f4ba2057-d1e1-4858-a175-26da0346af76
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2831491151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.2831491151
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.3610089435
Short name T380
Test name
Test status
Simulation time 200028703 ps
CPU time 2.92 seconds
Started Mar 12 01:56:28 PM PDT 24
Finished Mar 12 01:56:31 PM PDT 24
Peak memory 208640 kb
Host smart-af36bd99-448a-40b7-a421-9a70c1183c0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3610089435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.3610089435
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.2746777122
Short name T580
Test name
Test status
Simulation time 47650743 ps
CPU time 2.62 seconds
Started Mar 12 01:56:30 PM PDT 24
Finished Mar 12 01:56:33 PM PDT 24
Peak memory 214356 kb
Host smart-56dc60f2-24cc-43dd-a6d8-6252de7118c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746777122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.2746777122
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.2086991327
Short name T857
Test name
Test status
Simulation time 106915315 ps
CPU time 2.13 seconds
Started Mar 12 01:56:24 PM PDT 24
Finished Mar 12 01:56:27 PM PDT 24
Peak memory 214964 kb
Host smart-068ec180-1973-4e90-b366-3102d015226a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086991327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.2086991327
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.4248288728
Short name T236
Test name
Test status
Simulation time 171395486 ps
CPU time 6.11 seconds
Started Mar 12 01:56:26 PM PDT 24
Finished Mar 12 01:56:32 PM PDT 24
Peak memory 209336 kb
Host smart-2819358c-b065-4352-8ea3-c2adf460f8b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4248288728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.4248288728
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.4151584507
Short name T422
Test name
Test status
Simulation time 6724687973 ps
CPU time 15.79 seconds
Started Mar 12 01:56:27 PM PDT 24
Finished Mar 12 01:56:43 PM PDT 24
Peak memory 208184 kb
Host smart-0d0ebe7a-043c-4f8e-9598-c8fa1979e9b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151584507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.4151584507
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.2307573519
Short name T85
Test name
Test status
Simulation time 1992028775 ps
CPU time 8.77 seconds
Started Mar 12 01:56:24 PM PDT 24
Finished Mar 12 01:56:33 PM PDT 24
Peak memory 208972 kb
Host smart-68c97543-387a-4968-af78-ed2dc4f37da8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2307573519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.2307573519
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.1248880924
Short name T479
Test name
Test status
Simulation time 119045201 ps
CPU time 4.66 seconds
Started Mar 12 01:56:24 PM PDT 24
Finished Mar 12 01:56:29 PM PDT 24
Peak memory 206816 kb
Host smart-0e21c1cd-2218-45cd-a819-8a40de4e1b48
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1248880924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.1248880924
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.433114351
Short name T549
Test name
Test status
Simulation time 5255951826 ps
CPU time 53.07 seconds
Started Mar 12 01:56:27 PM PDT 24
Finished Mar 12 01:57:20 PM PDT 24
Peak memory 208700 kb
Host smart-d4a70023-7b66-4c3b-87d0-cde7a83cdcd5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433114351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.433114351
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.3470513650
Short name T432
Test name
Test status
Simulation time 179626237 ps
CPU time 2.32 seconds
Started Mar 12 01:56:23 PM PDT 24
Finished Mar 12 01:56:25 PM PDT 24
Peak memory 209616 kb
Host smart-23ec70a1-f556-46a6-aa35-1d281a5d34c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470513650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.3470513650
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.1343567509
Short name T149
Test name
Test status
Simulation time 279714620 ps
CPU time 3.2 seconds
Started Mar 12 01:56:24 PM PDT 24
Finished Mar 12 01:56:27 PM PDT 24
Peak memory 208700 kb
Host smart-084ee89a-0584-4cf5-933f-f04517c4fa4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1343567509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.1343567509
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.3432409690
Short name T793
Test name
Test status
Simulation time 780348933 ps
CPU time 11.68 seconds
Started Mar 12 01:56:42 PM PDT 24
Finished Mar 12 01:56:54 PM PDT 24
Peak memory 222820 kb
Host smart-7d640f68-0896-4647-89ee-ae1a3804338b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432409690 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.3432409690
Directory /workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.527241668
Short name T669
Test name
Test status
Simulation time 244255070 ps
CPU time 3.62 seconds
Started Mar 12 01:56:28 PM PDT 24
Finished Mar 12 01:56:31 PM PDT 24
Peak memory 218356 kb
Host smart-44a7943e-1ae2-46d3-852c-796f49773717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=527241668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.527241668
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.1395796961
Short name T744
Test name
Test status
Simulation time 30377685 ps
CPU time 1.94 seconds
Started Mar 12 01:56:25 PM PDT 24
Finished Mar 12 01:56:27 PM PDT 24
Peak memory 209732 kb
Host smart-d774e2c5-7a1c-4efc-9578-62692280fe1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395796961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.1395796961
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.2509201470
Short name T474
Test name
Test status
Simulation time 18310881 ps
CPU time 1.03 seconds
Started Mar 12 01:56:36 PM PDT 24
Finished Mar 12 01:56:37 PM PDT 24
Peak memory 206336 kb
Host smart-7bb33bee-25f7-49c4-b5c1-c7e754c32040
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509201470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.2509201470
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.3169497918
Short name T604
Test name
Test status
Simulation time 239726735 ps
CPU time 6.97 seconds
Started Mar 12 01:56:35 PM PDT 24
Finished Mar 12 01:56:42 PM PDT 24
Peak memory 217844 kb
Host smart-e4a00d19-6b2e-4aa7-bef1-4267413e99d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3169497918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.3169497918
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.4110217159
Short name T66
Test name
Test status
Simulation time 704768329 ps
CPU time 4.91 seconds
Started Mar 12 01:56:39 PM PDT 24
Finished Mar 12 01:56:44 PM PDT 24
Peak memory 218508 kb
Host smart-bce5e133-e83c-4b3d-a50a-f655756b96d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110217159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.4110217159
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.940268694
Short name T94
Test name
Test status
Simulation time 1092090118 ps
CPU time 29.66 seconds
Started Mar 12 01:56:36 PM PDT 24
Finished Mar 12 01:57:06 PM PDT 24
Peak memory 214536 kb
Host smart-29653c74-7900-431e-9569-dffeb6922095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940268694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.940268694
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.1600472663
Short name T712
Test name
Test status
Simulation time 78734992 ps
CPU time 3.56 seconds
Started Mar 12 01:56:41 PM PDT 24
Finished Mar 12 01:56:45 PM PDT 24
Peak memory 214608 kb
Host smart-1639e72d-04b4-4b29-88df-212b74769801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1600472663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.1600472663
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.3463549869
Short name T610
Test name
Test status
Simulation time 5713061266 ps
CPU time 39.74 seconds
Started Mar 12 01:56:35 PM PDT 24
Finished Mar 12 01:57:15 PM PDT 24
Peak memory 214592 kb
Host smart-6ddffbc3-da05-4ae6-a510-a329dbd332c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3463549869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.3463549869
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.795240325
Short name T391
Test name
Test status
Simulation time 267586204 ps
CPU time 7.15 seconds
Started Mar 12 01:56:34 PM PDT 24
Finished Mar 12 01:56:42 PM PDT 24
Peak memory 208952 kb
Host smart-8fc80e90-1e52-434d-964f-cce93e1c5084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795240325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.795240325
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.3757322091
Short name T671
Test name
Test status
Simulation time 26555066 ps
CPU time 1.92 seconds
Started Mar 12 01:56:42 PM PDT 24
Finished Mar 12 01:56:44 PM PDT 24
Peak memory 206900 kb
Host smart-d4c21cf7-3eb9-418a-88c2-db5071722b42
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757322091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.3757322091
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.3562270751
Short name T245
Test name
Test status
Simulation time 213728675 ps
CPU time 6.65 seconds
Started Mar 12 01:56:35 PM PDT 24
Finished Mar 12 01:56:42 PM PDT 24
Peak memory 208032 kb
Host smart-435ec61f-7a77-4a91-83e0-7eff8fa1d1da
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3562270751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.3562270751
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.2754258364
Short name T489
Test name
Test status
Simulation time 183407282 ps
CPU time 6.53 seconds
Started Mar 12 01:56:36 PM PDT 24
Finished Mar 12 01:56:42 PM PDT 24
Peak memory 208320 kb
Host smart-184b3600-77be-4f9d-b44e-cd7db3fb169a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754258364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.2754258364
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.3030333031
Short name T581
Test name
Test status
Simulation time 268717721 ps
CPU time 3.2 seconds
Started Mar 12 01:56:35 PM PDT 24
Finished Mar 12 01:56:39 PM PDT 24
Peak memory 209864 kb
Host smart-d4563fd7-efd5-4bee-87b1-a99b88b63223
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030333031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.3030333031
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.771786737
Short name T426
Test name
Test status
Simulation time 44896722 ps
CPU time 1.7 seconds
Started Mar 12 01:56:34 PM PDT 24
Finished Mar 12 01:56:37 PM PDT 24
Peak memory 206708 kb
Host smart-e77b5536-b6ba-4384-8ece-f5171e20be61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771786737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.771786737
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.3407806069
Short name T488
Test name
Test status
Simulation time 7734403957 ps
CPU time 35.92 seconds
Started Mar 12 01:56:34 PM PDT 24
Finished Mar 12 01:57:11 PM PDT 24
Peak memory 222748 kb
Host smart-0f81ae5c-07b5-402e-b1bc-1b66f385cff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3407806069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.3407806069
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.42567668
Short name T812
Test name
Test status
Simulation time 77851296 ps
CPU time 2.41 seconds
Started Mar 12 01:56:35 PM PDT 24
Finished Mar 12 01:56:38 PM PDT 24
Peak memory 210268 kb
Host smart-7c2e36f5-ec75-42dd-b96e-5d706c4bce14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42567668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.42567668
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.2311226290
Short name T733
Test name
Test status
Simulation time 170351393 ps
CPU time 0.94 seconds
Started Mar 12 01:56:44 PM PDT 24
Finished Mar 12 01:56:45 PM PDT 24
Peak memory 206336 kb
Host smart-e92cf84d-3960-419b-93ee-fa122d909fb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311226290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.2311226290
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.224515209
Short name T431
Test name
Test status
Simulation time 174051160 ps
CPU time 9.35 seconds
Started Mar 12 01:56:42 PM PDT 24
Finished Mar 12 01:56:51 PM PDT 24
Peak memory 214464 kb
Host smart-a232ba28-6437-4917-bc1b-95c3a041e72c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=224515209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.224515209
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.1274539316
Short name T74
Test name
Test status
Simulation time 109984722 ps
CPU time 4.47 seconds
Started Mar 12 01:56:47 PM PDT 24
Finished Mar 12 01:56:51 PM PDT 24
Peak memory 210144 kb
Host smart-524a2e4c-67ef-4f53-9839-e8e745b24aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1274539316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.1274539316
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.2301147042
Short name T719
Test name
Test status
Simulation time 1195077236 ps
CPU time 6.83 seconds
Started Mar 12 01:56:45 PM PDT 24
Finished Mar 12 01:56:52 PM PDT 24
Peak memory 214524 kb
Host smart-2a04653e-fc80-4c8a-a4df-0e5ab2eb0d07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2301147042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.2301147042
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.3328878999
Short name T646
Test name
Test status
Simulation time 442334449 ps
CPU time 3.92 seconds
Started Mar 12 01:56:46 PM PDT 24
Finished Mar 12 01:56:50 PM PDT 24
Peak memory 220272 kb
Host smart-6ed40493-a378-4253-ab32-ac226225a946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328878999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.3328878999
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.1192708567
Short name T420
Test name
Test status
Simulation time 363322221 ps
CPU time 4.97 seconds
Started Mar 12 01:56:42 PM PDT 24
Finished Mar 12 01:56:48 PM PDT 24
Peak memory 207360 kb
Host smart-6e2f3ede-9356-460f-94d2-e8718ad8d568
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192708567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.1192708567
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.3092267225
Short name T724
Test name
Test status
Simulation time 572008869 ps
CPU time 5.4 seconds
Started Mar 12 01:56:43 PM PDT 24
Finished Mar 12 01:56:49 PM PDT 24
Peak memory 206880 kb
Host smart-baa9e55d-ef6f-4f2b-b8bf-da461b138d22
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092267225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.3092267225
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.2818083084
Short name T450
Test name
Test status
Simulation time 986545538 ps
CPU time 34.14 seconds
Started Mar 12 01:56:45 PM PDT 24
Finished Mar 12 01:57:20 PM PDT 24
Peak memory 208392 kb
Host smart-a4a9f59f-a57f-4587-9782-67f1aca33682
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818083084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.2818083084
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.752221324
Short name T341
Test name
Test status
Simulation time 6854960356 ps
CPU time 56.85 seconds
Started Mar 12 01:56:45 PM PDT 24
Finished Mar 12 01:57:42 PM PDT 24
Peak memory 208728 kb
Host smart-d7bdf81f-3670-41d0-9e4b-16f2a49d7e6b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=752221324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.752221324
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.1247582259
Short name T548
Test name
Test status
Simulation time 71339371 ps
CPU time 2.77 seconds
Started Mar 12 01:56:44 PM PDT 24
Finished Mar 12 01:56:47 PM PDT 24
Peak memory 209648 kb
Host smart-4e14885c-97ed-40a3-9b86-ce9c57226a2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1247582259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.1247582259
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.2223292509
Short name T425
Test name
Test status
Simulation time 346177566 ps
CPU time 3.53 seconds
Started Mar 12 01:56:42 PM PDT 24
Finished Mar 12 01:56:45 PM PDT 24
Peak memory 208260 kb
Host smart-afc62e0e-06ce-48db-86d4-d1de8fe27fd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223292509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.2223292509
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.1446823780
Short name T340
Test name
Test status
Simulation time 2150925056 ps
CPU time 14.46 seconds
Started Mar 12 01:56:44 PM PDT 24
Finished Mar 12 01:56:59 PM PDT 24
Peak memory 208796 kb
Host smart-c7209b98-171f-4cfc-8c1a-11b5b5e2839b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446823780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.1446823780
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.2862513500
Short name T233
Test name
Test status
Simulation time 953695069 ps
CPU time 8.01 seconds
Started Mar 12 01:56:43 PM PDT 24
Finished Mar 12 01:56:51 PM PDT 24
Peak memory 207804 kb
Host smart-3975e59b-78cf-4e19-a9b1-53f961e8edd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862513500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.2862513500
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.3583958273
Short name T113
Test name
Test status
Simulation time 249119309 ps
CPU time 5.4 seconds
Started Mar 12 01:56:45 PM PDT 24
Finished Mar 12 01:56:50 PM PDT 24
Peak memory 210844 kb
Host smart-fca3123d-d5ff-4e39-a522-03ca3d738dfe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583958273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.3583958273
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.2731483195
Short name T480
Test name
Test status
Simulation time 32414962 ps
CPU time 0.82 seconds
Started Mar 12 01:56:55 PM PDT 24
Finished Mar 12 01:56:56 PM PDT 24
Peak memory 206148 kb
Host smart-10d3c28e-6026-469d-97f9-c2801513fbdb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2731483195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.2731483195
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.2260753451
Short name T28
Test name
Test status
Simulation time 9505531278 ps
CPU time 52.33 seconds
Started Mar 12 01:56:52 PM PDT 24
Finished Mar 12 01:57:45 PM PDT 24
Peak memory 222948 kb
Host smart-2e4a596c-4b25-4f05-b4c2-21473fb7156b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260753451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.2260753451
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.1369988964
Short name T53
Test name
Test status
Simulation time 121298848 ps
CPU time 4.87 seconds
Started Mar 12 01:56:56 PM PDT 24
Finished Mar 12 01:57:02 PM PDT 24
Peak memory 209944 kb
Host smart-93e73f11-fbe3-424c-819b-a16bc521d87a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369988964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.1369988964
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.1484523448
Short name T633
Test name
Test status
Simulation time 1315394428 ps
CPU time 5.39 seconds
Started Mar 12 01:56:53 PM PDT 24
Finished Mar 12 01:56:58 PM PDT 24
Peak memory 222648 kb
Host smart-c28c87eb-5e73-4001-b549-b0031aa8c743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1484523448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.1484523448
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.1978772413
Short name T761
Test name
Test status
Simulation time 92220064 ps
CPU time 4.63 seconds
Started Mar 12 01:56:56 PM PDT 24
Finished Mar 12 01:57:01 PM PDT 24
Peak memory 222640 kb
Host smart-39c3f1de-b8fd-43dc-b215-5bf34028161a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1978772413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.1978772413
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.525654254
Short name T601
Test name
Test status
Simulation time 407727098 ps
CPU time 4.66 seconds
Started Mar 12 01:56:55 PM PDT 24
Finished Mar 12 01:57:00 PM PDT 24
Peak memory 209904 kb
Host smart-c3d886fa-4d87-4d40-9be2-0863e5723151
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525654254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.525654254
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.87174845
Short name T578
Test name
Test status
Simulation time 88667013 ps
CPU time 2.5 seconds
Started Mar 12 01:56:44 PM PDT 24
Finished Mar 12 01:56:47 PM PDT 24
Peak memory 206336 kb
Host smart-f901acf9-404c-4129-a7ce-1d5704612cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87174845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.87174845
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.800126526
Short name T376
Test name
Test status
Simulation time 185616295 ps
CPU time 2.99 seconds
Started Mar 12 01:56:54 PM PDT 24
Finished Mar 12 01:56:57 PM PDT 24
Peak memory 207200 kb
Host smart-dfd6bc61-0287-450a-852b-98f7db2e8e0c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800126526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.800126526
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.1488891627
Short name T728
Test name
Test status
Simulation time 2987081880 ps
CPU time 38.97 seconds
Started Mar 12 01:56:52 PM PDT 24
Finished Mar 12 01:57:31 PM PDT 24
Peak memory 207776 kb
Host smart-46af7f84-02c3-4118-bd09-3b14dea90dcd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1488891627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.1488891627
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.1425750896
Short name T299
Test name
Test status
Simulation time 24178240 ps
CPU time 1.91 seconds
Started Mar 12 01:56:55 PM PDT 24
Finished Mar 12 01:56:57 PM PDT 24
Peak memory 208680 kb
Host smart-b21850f9-9cd5-498a-8d0b-d847ba0669e5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425750896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.1425750896
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.1183171229
Short name T534
Test name
Test status
Simulation time 124637021 ps
CPU time 3.65 seconds
Started Mar 12 01:56:52 PM PDT 24
Finished Mar 12 01:56:56 PM PDT 24
Peak memory 218324 kb
Host smart-3e19521f-1096-4ece-8498-6f7f74e6ce1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1183171229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.1183171229
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.1376820659
Short name T819
Test name
Test status
Simulation time 233856294 ps
CPU time 4.57 seconds
Started Mar 12 01:56:45 PM PDT 24
Finished Mar 12 01:56:49 PM PDT 24
Peak memory 207824 kb
Host smart-7bc7fc93-0737-440e-803f-273b59558662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1376820659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.1376820659
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.4053823639
Short name T865
Test name
Test status
Simulation time 134243122 ps
CPU time 6.36 seconds
Started Mar 12 01:56:56 PM PDT 24
Finished Mar 12 01:57:03 PM PDT 24
Peak memory 209840 kb
Host smart-5d536d01-0ffa-47e2-ab78-0eb65db035dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053823639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.4053823639
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.1746999027
Short name T403
Test name
Test status
Simulation time 196623136 ps
CPU time 1.96 seconds
Started Mar 12 01:56:54 PM PDT 24
Finished Mar 12 01:56:57 PM PDT 24
Peak memory 209804 kb
Host smart-a29a2369-cd84-444b-bfcc-83de219ecad5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746999027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.1746999027
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.418489862
Short name T18
Test name
Test status
Simulation time 35845430 ps
CPU time 0.78 seconds
Started Mar 12 01:57:08 PM PDT 24
Finished Mar 12 01:57:08 PM PDT 24
Peak memory 206140 kb
Host smart-7d70fe17-c15f-464f-b25f-8a50983cd6b9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418489862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.418489862
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.2148380855
Short name T394
Test name
Test status
Simulation time 198882994 ps
CPU time 4.03 seconds
Started Mar 12 01:56:55 PM PDT 24
Finished Mar 12 01:57:00 PM PDT 24
Peak memory 215572 kb
Host smart-018315c9-805a-4dd5-b493-a8063d5c1183
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2148380855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.2148380855
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.204231166
Short name T476
Test name
Test status
Simulation time 25127077 ps
CPU time 1.64 seconds
Started Mar 12 01:56:53 PM PDT 24
Finished Mar 12 01:56:55 PM PDT 24
Peak memory 209212 kb
Host smart-1b09a5c0-ce96-40cb-8686-c036d061ea3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204231166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.204231166
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.2261620538
Short name T625
Test name
Test status
Simulation time 128288604 ps
CPU time 5.17 seconds
Started Mar 12 01:56:54 PM PDT 24
Finished Mar 12 01:56:59 PM PDT 24
Peak memory 222228 kb
Host smart-f974e89b-bd5b-493c-aa39-cd49a7cc2b06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2261620538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.2261620538
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.2474402294
Short name T759
Test name
Test status
Simulation time 1438966993 ps
CPU time 5.77 seconds
Started Mar 12 01:56:53 PM PDT 24
Finished Mar 12 01:56:59 PM PDT 24
Peak memory 222508 kb
Host smart-0f7a0712-7ae7-420e-ba5b-b5120a685788
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474402294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.2474402294
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.347439378
Short name T46
Test name
Test status
Simulation time 849280272 ps
CPU time 3.1 seconds
Started Mar 12 01:56:57 PM PDT 24
Finished Mar 12 01:57:01 PM PDT 24
Peak memory 214588 kb
Host smart-31c49869-ba77-4d85-86c4-58f83bf6d35d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347439378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.347439378
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.212411644
Short name T779
Test name
Test status
Simulation time 177524253 ps
CPU time 6.29 seconds
Started Mar 12 01:56:58 PM PDT 24
Finished Mar 12 01:57:04 PM PDT 24
Peak memory 218456 kb
Host smart-c352bc8b-ba1c-44bf-98ea-449f6454c654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212411644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.212411644
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.303086010
Short name T762
Test name
Test status
Simulation time 133499920 ps
CPU time 3.67 seconds
Started Mar 12 01:56:54 PM PDT 24
Finished Mar 12 01:56:59 PM PDT 24
Peak memory 206732 kb
Host smart-512a7aa6-9593-4ca6-b3ab-9209d9308120
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303086010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.303086010
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.1507620382
Short name T659
Test name
Test status
Simulation time 319162807 ps
CPU time 3.2 seconds
Started Mar 12 01:56:53 PM PDT 24
Finished Mar 12 01:56:56 PM PDT 24
Peak memory 208012 kb
Host smart-45852513-5024-4dd2-83a9-3300c777170c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1507620382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.1507620382
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.858003225
Short name T544
Test name
Test status
Simulation time 130219756 ps
CPU time 3.64 seconds
Started Mar 12 01:56:54 PM PDT 24
Finished Mar 12 01:56:58 PM PDT 24
Peak memory 208724 kb
Host smart-4cc334c2-b87e-4b28-aba3-1237a6bb0d9a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=858003225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.858003225
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.307681580
Short name T138
Test name
Test status
Simulation time 73882288 ps
CPU time 3.62 seconds
Started Mar 12 01:56:54 PM PDT 24
Finished Mar 12 01:56:59 PM PDT 24
Peak memory 208792 kb
Host smart-8d40a407-8b02-432e-9718-7679a6bcd30f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=307681580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.307681580
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.2783606438
Short name T434
Test name
Test status
Simulation time 202830701 ps
CPU time 3.12 seconds
Started Mar 12 01:56:55 PM PDT 24
Finished Mar 12 01:56:58 PM PDT 24
Peak memory 209088 kb
Host smart-86f227ca-41ff-4646-b506-5e42c977680d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2783606438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.2783606438
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.3396527006
Short name T428
Test name
Test status
Simulation time 1902623227 ps
CPU time 37.41 seconds
Started Mar 12 01:56:53 PM PDT 24
Finished Mar 12 01:57:30 PM PDT 24
Peak memory 208280 kb
Host smart-c7d47e5d-0ede-4185-91ea-863464535efa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3396527006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.3396527006
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.3514868983
Short name T364
Test name
Test status
Simulation time 816274622 ps
CPU time 31.57 seconds
Started Mar 12 01:57:05 PM PDT 24
Finished Mar 12 01:57:39 PM PDT 24
Peak memory 215636 kb
Host smart-849adf88-3dfa-49b8-a1c4-d902f84819cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514868983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.3514868983
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.3221306959
Short name T860
Test name
Test status
Simulation time 82969985 ps
CPU time 2.42 seconds
Started Mar 12 01:56:52 PM PDT 24
Finished Mar 12 01:56:55 PM PDT 24
Peak memory 208328 kb
Host smart-d3550ab1-5685-49c7-a376-0d52bb245517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221306959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.3221306959
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.3035205287
Short name T429
Test name
Test status
Simulation time 77021165 ps
CPU time 1.81 seconds
Started Mar 12 01:56:54 PM PDT 24
Finished Mar 12 01:56:56 PM PDT 24
Peak memory 210104 kb
Host smart-ddfeefdf-c250-4abb-bc5b-cde63f14a612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035205287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.3035205287
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.1751255770
Short name T449
Test name
Test status
Simulation time 77217001 ps
CPU time 0.81 seconds
Started Mar 12 01:54:43 PM PDT 24
Finished Mar 12 01:54:44 PM PDT 24
Peak memory 206088 kb
Host smart-654a4d78-1af7-427a-b553-9de3fabf3a0a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751255770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.1751255770
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.4270670003
Short name T742
Test name
Test status
Simulation time 233216365 ps
CPU time 3.25 seconds
Started Mar 12 01:54:31 PM PDT 24
Finished Mar 12 01:54:35 PM PDT 24
Peak memory 217692 kb
Host smart-682ea051-186f-4cb3-aba4-40b4c735aeaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270670003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.4270670003
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.276137218
Short name T277
Test name
Test status
Simulation time 57500675 ps
CPU time 2.74 seconds
Started Mar 12 01:54:32 PM PDT 24
Finished Mar 12 01:54:35 PM PDT 24
Peak memory 209176 kb
Host smart-b7c09cbd-7bbb-41ed-902d-d484f7f73247
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276137218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.276137218
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.49227837
Short name T286
Test name
Test status
Simulation time 925543116 ps
CPU time 10.21 seconds
Started Mar 12 01:54:32 PM PDT 24
Finished Mar 12 01:54:43 PM PDT 24
Peak memory 221128 kb
Host smart-74224835-9698-4ff6-9528-4a68a70bfc49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49227837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.49227837
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.340254104
Short name T398
Test name
Test status
Simulation time 1168304862 ps
CPU time 33.51 seconds
Started Mar 12 01:54:30 PM PDT 24
Finished Mar 12 01:55:04 PM PDT 24
Peak memory 222544 kb
Host smart-6d95c2ac-f077-4fb4-9a0e-29d4a570e1fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340254104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.340254104
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.2984658954
Short name T890
Test name
Test status
Simulation time 159145189 ps
CPU time 3.89 seconds
Started Mar 12 01:54:31 PM PDT 24
Finished Mar 12 01:54:35 PM PDT 24
Peak memory 222616 kb
Host smart-13e173db-673a-4ae2-920e-bbb0bf19593b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984658954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.2984658954
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.3017598900
Short name T324
Test name
Test status
Simulation time 456683563 ps
CPU time 9.31 seconds
Started Mar 12 01:54:32 PM PDT 24
Finished Mar 12 01:54:41 PM PDT 24
Peak memory 218536 kb
Host smart-7a31514b-552b-42ab-8272-db092d81b3ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3017598900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.3017598900
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.219725697
Short name T103
Test name
Test status
Simulation time 330756498 ps
CPU time 10.63 seconds
Started Mar 12 01:54:41 PM PDT 24
Finished Mar 12 01:54:52 PM PDT 24
Peak memory 231436 kb
Host smart-673c81a9-c393-4e16-bfef-552a4cf94fbc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=219725697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.219725697
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.1690090867
Short name T554
Test name
Test status
Simulation time 377562518 ps
CPU time 6.58 seconds
Started Mar 12 01:54:25 PM PDT 24
Finished Mar 12 01:54:32 PM PDT 24
Peak memory 207100 kb
Host smart-6186ea70-52e8-4675-b886-df6a30126cc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690090867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.1690090867
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.494198945
Short name T639
Test name
Test status
Simulation time 1288585746 ps
CPU time 19.96 seconds
Started Mar 12 01:54:24 PM PDT 24
Finished Mar 12 01:54:44 PM PDT 24
Peak memory 208632 kb
Host smart-57cb9b28-25f8-4847-ae8e-fb278669b529
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=494198945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.494198945
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.785143781
Short name T807
Test name
Test status
Simulation time 7886870421 ps
CPU time 64.91 seconds
Started Mar 12 01:54:24 PM PDT 24
Finished Mar 12 01:55:30 PM PDT 24
Peak memory 208712 kb
Host smart-14aba35c-20f3-47e2-b903-e9ee23af300d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785143781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.785143781
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.4100648662
Short name T459
Test name
Test status
Simulation time 62157276 ps
CPU time 2.41 seconds
Started Mar 12 01:54:25 PM PDT 24
Finished Mar 12 01:54:28 PM PDT 24
Peak memory 206872 kb
Host smart-e867aacc-8a65-4d2d-8618-dc4091cab438
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100648662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.4100648662
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.3082632761
Short name T383
Test name
Test status
Simulation time 23395012 ps
CPU time 1.9 seconds
Started Mar 12 01:54:44 PM PDT 24
Finished Mar 12 01:54:46 PM PDT 24
Peak memory 207032 kb
Host smart-77a6b328-eecb-45a6-bc7c-aa8ef3b3a4f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3082632761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.3082632761
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.2257752112
Short name T418
Test name
Test status
Simulation time 487718799 ps
CPU time 3.54 seconds
Started Mar 12 01:54:24 PM PDT 24
Finished Mar 12 01:54:28 PM PDT 24
Peak memory 208404 kb
Host smart-eba05504-8d5e-4ce9-ac2f-560e29175d3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2257752112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.2257752112
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.3698446673
Short name T553
Test name
Test status
Simulation time 2446478123 ps
CPU time 15.89 seconds
Started Mar 12 01:54:43 PM PDT 24
Finished Mar 12 01:54:59 PM PDT 24
Peak memory 214632 kb
Host smart-ce5bd6a1-dd8d-44c5-8d4a-ec0508f3a922
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3698446673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.3698446673
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.1864123379
Short name T210
Test name
Test status
Simulation time 1116887903 ps
CPU time 9.7 seconds
Started Mar 12 01:54:32 PM PDT 24
Finished Mar 12 01:54:42 PM PDT 24
Peak memory 209848 kb
Host smart-bcde9864-69da-453d-904a-68a673bdf1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864123379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.1864123379
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.2348272599
Short name T181
Test name
Test status
Simulation time 58510739 ps
CPU time 2.88 seconds
Started Mar 12 01:54:43 PM PDT 24
Finished Mar 12 01:54:46 PM PDT 24
Peak memory 210088 kb
Host smart-8506d4cb-dcbf-4607-b7c6-31f3ebf98bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2348272599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.2348272599
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.3515039642
Short name T695
Test name
Test status
Simulation time 16383991 ps
CPU time 0.77 seconds
Started Mar 12 01:57:03 PM PDT 24
Finished Mar 12 01:57:06 PM PDT 24
Peak memory 206184 kb
Host smart-45ad17d4-6d66-45ad-a042-01f9624433aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515039642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.3515039642
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.193416912
Short name T846
Test name
Test status
Simulation time 25439434 ps
CPU time 1.9 seconds
Started Mar 12 01:57:06 PM PDT 24
Finished Mar 12 01:57:09 PM PDT 24
Peak memory 217512 kb
Host smart-d4b261f8-ee23-4470-87a5-b6b2974f109c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193416912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.193416912
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.627031814
Short name T73
Test name
Test status
Simulation time 156911995 ps
CPU time 3.48 seconds
Started Mar 12 01:57:04 PM PDT 24
Finished Mar 12 01:57:10 PM PDT 24
Peak memory 207564 kb
Host smart-a8bb11eb-2eb7-45d4-9e13-4598332b471d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627031814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.627031814
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.1487992672
Short name T416
Test name
Test status
Simulation time 712209485 ps
CPU time 3.52 seconds
Started Mar 12 01:57:06 PM PDT 24
Finished Mar 12 01:57:11 PM PDT 24
Peak memory 209176 kb
Host smart-2b54e986-67fd-49cb-b219-871ad0e84956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487992672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.1487992672
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.3850531711
Short name T419
Test name
Test status
Simulation time 44874323 ps
CPU time 2.67 seconds
Started Mar 12 01:57:03 PM PDT 24
Finished Mar 12 01:57:08 PM PDT 24
Peak memory 207792 kb
Host smart-326c875c-d40b-49ca-b927-d6a66f0cf809
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850531711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.3850531711
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.3033215585
Short name T683
Test name
Test status
Simulation time 1237337202 ps
CPU time 5.42 seconds
Started Mar 12 01:57:06 PM PDT 24
Finished Mar 12 01:57:12 PM PDT 24
Peak memory 209596 kb
Host smart-2f3648e0-156c-4645-8ecc-eba15a2cd354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3033215585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.3033215585
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.2383968465
Short name T559
Test name
Test status
Simulation time 219421208 ps
CPU time 2.91 seconds
Started Mar 12 01:57:07 PM PDT 24
Finished Mar 12 01:57:10 PM PDT 24
Peak memory 208640 kb
Host smart-70c3feb5-1273-4bb2-8728-086fce676784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383968465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.2383968465
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.1228942764
Short name T290
Test name
Test status
Simulation time 706610900 ps
CPU time 6.24 seconds
Started Mar 12 01:57:04 PM PDT 24
Finished Mar 12 01:57:12 PM PDT 24
Peak memory 208608 kb
Host smart-d5a39ea1-c228-4bf7-ab9d-919dbf8c807e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228942764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.1228942764
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.2563914451
Short name T714
Test name
Test status
Simulation time 1231142352 ps
CPU time 7.84 seconds
Started Mar 12 01:57:04 PM PDT 24
Finished Mar 12 01:57:14 PM PDT 24
Peak memory 208744 kb
Host smart-885d98fc-9f8d-4502-92d9-47c3856de9ae
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563914451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.2563914451
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.3790517141
Short name T838
Test name
Test status
Simulation time 256917540 ps
CPU time 7.71 seconds
Started Mar 12 01:57:06 PM PDT 24
Finished Mar 12 01:57:15 PM PDT 24
Peak memory 208716 kb
Host smart-07e20b42-c4f6-4154-969d-33690251ba94
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790517141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.3790517141
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.255837621
Short name T269
Test name
Test status
Simulation time 53062118 ps
CPU time 2.01 seconds
Started Mar 12 01:57:05 PM PDT 24
Finished Mar 12 01:57:08 PM PDT 24
Peak memory 208712 kb
Host smart-f2e3db19-300d-49fe-b1b9-b2bb4a8b99b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255837621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.255837621
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.4059515496
Short name T870
Test name
Test status
Simulation time 75300292 ps
CPU time 3.27 seconds
Started Mar 12 01:57:03 PM PDT 24
Finished Mar 12 01:57:09 PM PDT 24
Peak memory 208448 kb
Host smart-893d545e-f7a3-47e1-8746-5d545d686602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059515496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.4059515496
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.3756200951
Short name T140
Test name
Test status
Simulation time 725990379 ps
CPU time 3.57 seconds
Started Mar 12 01:57:05 PM PDT 24
Finished Mar 12 01:57:10 PM PDT 24
Peak memory 210004 kb
Host smart-798e45ac-6606-4039-8e24-8ec9143274ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3756200951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.3756200951
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.1534018591
Short name T59
Test name
Test status
Simulation time 192749033 ps
CPU time 2.53 seconds
Started Mar 12 01:57:06 PM PDT 24
Finished Mar 12 01:57:10 PM PDT 24
Peak memory 210000 kb
Host smart-3b19dfe4-4be0-420f-b944-97ee165826be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534018591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.1534018591
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.4024677389
Short name T539
Test name
Test status
Simulation time 12022573 ps
CPU time 0.88 seconds
Started Mar 12 01:57:15 PM PDT 24
Finished Mar 12 01:57:16 PM PDT 24
Peak memory 206084 kb
Host smart-aaca5c30-a22d-4b9b-9159-fb2520e97b05
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4024677389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.4024677389
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.2709661071
Short name T443
Test name
Test status
Simulation time 76957638 ps
CPU time 2.98 seconds
Started Mar 12 01:57:06 PM PDT 24
Finished Mar 12 01:57:10 PM PDT 24
Peak memory 214484 kb
Host smart-c7c66fe4-66ad-4d00-8d26-e5b1e5767912
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2709661071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.2709661071
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.1522061601
Short name T821
Test name
Test status
Simulation time 597603908 ps
CPU time 16.55 seconds
Started Mar 12 01:57:03 PM PDT 24
Finished Mar 12 01:57:21 PM PDT 24
Peak memory 214516 kb
Host smart-8e38fbff-ff63-4a75-bda2-2310d296f155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522061601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.1522061601
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.4155303025
Short name T415
Test name
Test status
Simulation time 532918557 ps
CPU time 9.89 seconds
Started Mar 12 01:57:04 PM PDT 24
Finished Mar 12 01:57:16 PM PDT 24
Peak memory 219380 kb
Host smart-214405cc-acdd-4256-856f-933e84396e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155303025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.4155303025
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.1253229191
Short name T314
Test name
Test status
Simulation time 1660212472 ps
CPU time 20.74 seconds
Started Mar 12 01:57:04 PM PDT 24
Finished Mar 12 01:57:27 PM PDT 24
Peak memory 210896 kb
Host smart-24f125d7-c1ed-4eac-bc22-77eb92c51821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1253229191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.1253229191
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.1790874259
Short name T758
Test name
Test status
Simulation time 52355309 ps
CPU time 2.19 seconds
Started Mar 12 01:57:05 PM PDT 24
Finished Mar 12 01:57:09 PM PDT 24
Peak memory 208640 kb
Host smart-8ac2dc36-dbb8-4343-a5b1-52667e8f0ca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790874259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.1790874259
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.1119326348
Short name T368
Test name
Test status
Simulation time 1061810279 ps
CPU time 24.56 seconds
Started Mar 12 01:57:05 PM PDT 24
Finished Mar 12 01:57:31 PM PDT 24
Peak memory 208596 kb
Host smart-450cc854-dc6c-4f79-87ad-70886677d930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1119326348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.1119326348
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.576409063
Short name T346
Test name
Test status
Simulation time 199475342 ps
CPU time 3.62 seconds
Started Mar 12 01:57:03 PM PDT 24
Finished Mar 12 01:57:07 PM PDT 24
Peak memory 206764 kb
Host smart-acf7e035-8a0e-4966-98b0-9662645b1cd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576409063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.576409063
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.4028305137
Short name T665
Test name
Test status
Simulation time 1955461059 ps
CPU time 27.28 seconds
Started Mar 12 01:57:04 PM PDT 24
Finished Mar 12 01:57:34 PM PDT 24
Peak memory 208752 kb
Host smart-e087e0b3-f80a-41e4-8bdd-de361a07ff74
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028305137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.4028305137
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.3296105313
Short name T573
Test name
Test status
Simulation time 1610701377 ps
CPU time 46.7 seconds
Started Mar 12 01:57:04 PM PDT 24
Finished Mar 12 01:57:53 PM PDT 24
Peak memory 208484 kb
Host smart-a56e3243-553c-431c-93fc-1c23910ae339
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3296105313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.3296105313
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.3598701699
Short name T566
Test name
Test status
Simulation time 2739374538 ps
CPU time 20.72 seconds
Started Mar 12 01:57:05 PM PDT 24
Finished Mar 12 01:57:28 PM PDT 24
Peak memory 208668 kb
Host smart-7daec4fe-b053-4c3d-9db9-62fbf203599e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3598701699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.3598701699
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.1529742223
Short name T702
Test name
Test status
Simulation time 475825073 ps
CPU time 1.69 seconds
Started Mar 12 01:57:16 PM PDT 24
Finished Mar 12 01:57:18 PM PDT 24
Peak memory 208076 kb
Host smart-647b67f9-f355-4d99-9df7-1c55fc3c6e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529742223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.1529742223
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.3878612989
Short name T579
Test name
Test status
Simulation time 241867495 ps
CPU time 3.29 seconds
Started Mar 12 01:57:03 PM PDT 24
Finished Mar 12 01:57:09 PM PDT 24
Peak memory 208788 kb
Host smart-d5ebba7b-9552-440e-bbf5-7019ec3bb474
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3878612989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.3878612989
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all_with_rand_reset.3815609574
Short name T116
Test name
Test status
Simulation time 3958417358 ps
CPU time 14.73 seconds
Started Mar 12 01:57:12 PM PDT 24
Finished Mar 12 01:57:27 PM PDT 24
Peak memory 222836 kb
Host smart-d54fb6c4-20d4-43cc-8344-13a0b9dfc69e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815609574 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all_with_rand_reset.3815609574
Directory /workspace/21.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.357887771
Short name T647
Test name
Test status
Simulation time 14402740 ps
CPU time 0.89 seconds
Started Mar 12 01:57:15 PM PDT 24
Finished Mar 12 01:57:16 PM PDT 24
Peak memory 206204 kb
Host smart-d677e3f5-a631-4209-8246-c04f23bfb09e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357887771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.357887771
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.1406280997
Short name T369
Test name
Test status
Simulation time 61077625 ps
CPU time 2.59 seconds
Started Mar 12 01:57:13 PM PDT 24
Finished Mar 12 01:57:15 PM PDT 24
Peak memory 214524 kb
Host smart-7254f54a-cb2a-48f3-a67b-1f830504ed60
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1406280997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.1406280997
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.1634570920
Short name T384
Test name
Test status
Simulation time 63368736 ps
CPU time 2.37 seconds
Started Mar 12 01:57:13 PM PDT 24
Finished Mar 12 01:57:15 PM PDT 24
Peak memory 206968 kb
Host smart-92f9e1ec-6b62-483e-adf4-8800e0d27c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634570920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.1634570920
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.1498410756
Short name T99
Test name
Test status
Simulation time 281192900 ps
CPU time 9.67 seconds
Started Mar 12 01:57:12 PM PDT 24
Finished Mar 12 01:57:21 PM PDT 24
Peak memory 214564 kb
Host smart-12181118-ea5f-4982-a045-b09a7d4e3005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498410756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.1498410756
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.2733321239
Short name T88
Test name
Test status
Simulation time 537835268 ps
CPU time 3.55 seconds
Started Mar 12 01:57:14 PM PDT 24
Finished Mar 12 01:57:18 PM PDT 24
Peak memory 222668 kb
Host smart-3a800f2e-fc9a-4041-a9dc-1472e956241e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2733321239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.2733321239
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.1105321576
Short name T766
Test name
Test status
Simulation time 351551363 ps
CPU time 11.57 seconds
Started Mar 12 01:57:15 PM PDT 24
Finished Mar 12 01:57:27 PM PDT 24
Peak memory 222728 kb
Host smart-8b085300-9c35-4b2d-a8fa-8ed108e216da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105321576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.1105321576
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_sideload.3729552583
Short name T666
Test name
Test status
Simulation time 269668265 ps
CPU time 6.68 seconds
Started Mar 12 01:57:16 PM PDT 24
Finished Mar 12 01:57:23 PM PDT 24
Peak memory 208468 kb
Host smart-1c4a4545-9c14-4e5c-b537-426fb0337bc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3729552583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.3729552583
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.1008411433
Short name T525
Test name
Test status
Simulation time 95476151 ps
CPU time 3.54 seconds
Started Mar 12 01:57:11 PM PDT 24
Finished Mar 12 01:57:15 PM PDT 24
Peak memory 208556 kb
Host smart-54ca53d9-54d0-4889-813b-0e007d8c903a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1008411433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.1008411433
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.857452869
Short name T596
Test name
Test status
Simulation time 120973337 ps
CPU time 2.53 seconds
Started Mar 12 01:57:13 PM PDT 24
Finished Mar 12 01:57:16 PM PDT 24
Peak memory 207580 kb
Host smart-18c7ac4e-2fa9-44cd-ab4c-4ffe872991e6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857452869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.857452869
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.1251055956
Short name T377
Test name
Test status
Simulation time 210994920 ps
CPU time 8.09 seconds
Started Mar 12 01:57:12 PM PDT 24
Finished Mar 12 01:57:20 PM PDT 24
Peak memory 208500 kb
Host smart-b3e9e206-66ad-449a-ba37-657ba29dfb12
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1251055956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.1251055956
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.2310254430
Short name T296
Test name
Test status
Simulation time 236555216 ps
CPU time 3.16 seconds
Started Mar 12 01:57:13 PM PDT 24
Finished Mar 12 01:57:17 PM PDT 24
Peak memory 209208 kb
Host smart-e08c1eed-0fc2-498e-beb7-fef6b204e4fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310254430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.2310254430
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.1477747331
Short name T453
Test name
Test status
Simulation time 69711411 ps
CPU time 2.4 seconds
Started Mar 12 01:57:14 PM PDT 24
Finished Mar 12 01:57:17 PM PDT 24
Peak memory 207292 kb
Host smart-c51eab05-46f9-4fba-a60c-d075a55ce77c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477747331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.1477747331
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.3999659066
Short name T3
Test name
Test status
Simulation time 130453242 ps
CPU time 5.77 seconds
Started Mar 12 01:57:16 PM PDT 24
Finished Mar 12 01:57:22 PM PDT 24
Peak memory 208772 kb
Host smart-6b181cfd-38d2-45be-9ab3-330808a4309c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999659066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.3999659066
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_stress_all_with_rand_reset.612843880
Short name T736
Test name
Test status
Simulation time 261286909 ps
CPU time 10.05 seconds
Started Mar 12 01:57:17 PM PDT 24
Finished Mar 12 01:57:27 PM PDT 24
Peak memory 222812 kb
Host smart-db3ceeef-bde4-4cf6-8e05-df76b57179ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612843880 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all_with_rand_reset.612843880
Directory /workspace/22.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.1975682190
Short name T309
Test name
Test status
Simulation time 828914104 ps
CPU time 3.57 seconds
Started Mar 12 01:57:15 PM PDT 24
Finished Mar 12 01:57:19 PM PDT 24
Peak memory 208368 kb
Host smart-fdd58545-fcd4-49bd-bd29-616efbac97ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1975682190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.1975682190
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.1124026082
Short name T815
Test name
Test status
Simulation time 62903428 ps
CPU time 1.87 seconds
Started Mar 12 01:57:13 PM PDT 24
Finished Mar 12 01:57:15 PM PDT 24
Peak memory 209908 kb
Host smart-6fbc5d0e-6486-4dad-b007-e4e4a129c691
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1124026082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.1124026082
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.2643559925
Short name T835
Test name
Test status
Simulation time 49022330 ps
CPU time 0.98 seconds
Started Mar 12 01:57:26 PM PDT 24
Finished Mar 12 01:57:27 PM PDT 24
Peak memory 206288 kb
Host smart-a021c015-2a23-4277-b3a5-5b73cb2b52dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2643559925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.2643559925
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.2191725015
Short name T439
Test name
Test status
Simulation time 204535788 ps
CPU time 3.68 seconds
Started Mar 12 01:57:13 PM PDT 24
Finished Mar 12 01:57:16 PM PDT 24
Peak memory 214424 kb
Host smart-33547cd4-b8cc-4c5a-9090-9558db74c56b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2191725015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.2191725015
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.422007779
Short name T583
Test name
Test status
Simulation time 632738135 ps
CPU time 20.05 seconds
Started Mar 12 01:57:15 PM PDT 24
Finished Mar 12 01:57:35 PM PDT 24
Peak memory 209916 kb
Host smart-7e4e9aef-f7cf-41e0-baba-0f97e76db499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422007779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.422007779
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.4027708468
Short name T95
Test name
Test status
Simulation time 272298648 ps
CPU time 5.19 seconds
Started Mar 12 01:57:15 PM PDT 24
Finished Mar 12 01:57:20 PM PDT 24
Peak memory 214496 kb
Host smart-421c9227-bd62-4287-8720-cec75011f13e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4027708468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.4027708468
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.671396657
Short name T51
Test name
Test status
Simulation time 814137423 ps
CPU time 23 seconds
Started Mar 12 01:57:15 PM PDT 24
Finished Mar 12 01:57:39 PM PDT 24
Peak memory 214684 kb
Host smart-b0a5118e-6feb-4f61-b8f7-84023e7c3241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=671396657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.671396657
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.238888232
Short name T810
Test name
Test status
Simulation time 96332199 ps
CPU time 2.76 seconds
Started Mar 12 01:57:15 PM PDT 24
Finished Mar 12 01:57:18 PM PDT 24
Peak memory 220128 kb
Host smart-680676e9-d8be-46a7-ab98-74b7eede37a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=238888232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.238888232
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.4161690196
Short name T856
Test name
Test status
Simulation time 291520210 ps
CPU time 4.12 seconds
Started Mar 12 01:57:14 PM PDT 24
Finished Mar 12 01:57:18 PM PDT 24
Peak memory 207664 kb
Host smart-4a95b386-8239-4018-b3fc-64a24abb02b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4161690196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.4161690196
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.2296633878
Short name T830
Test name
Test status
Simulation time 983098688 ps
CPU time 7.8 seconds
Started Mar 12 01:57:16 PM PDT 24
Finished Mar 12 01:57:24 PM PDT 24
Peak memory 208688 kb
Host smart-17a2effe-a86d-4c55-9526-c28008ebe147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2296633878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.2296633878
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.850825156
Short name T863
Test name
Test status
Simulation time 411318079 ps
CPU time 6.05 seconds
Started Mar 12 01:57:13 PM PDT 24
Finished Mar 12 01:57:19 PM PDT 24
Peak memory 208748 kb
Host smart-f5380dce-863f-4897-b3bc-d01b1df1b2a9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=850825156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.850825156
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.3070242429
Short name T784
Test name
Test status
Simulation time 143570440 ps
CPU time 4.15 seconds
Started Mar 12 01:57:14 PM PDT 24
Finished Mar 12 01:57:19 PM PDT 24
Peak memory 208880 kb
Host smart-aed71fba-5a05-487a-ad5c-edebd902e70a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3070242429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.3070242429
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.1739519037
Short name T111
Test name
Test status
Simulation time 136623312 ps
CPU time 4.67 seconds
Started Mar 12 01:57:17 PM PDT 24
Finished Mar 12 01:57:22 PM PDT 24
Peak memory 209700 kb
Host smart-2fee7eae-33e1-405f-a0f0-49033cea897b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1739519037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.1739519037
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.3098801692
Short name T750
Test name
Test status
Simulation time 2823437371 ps
CPU time 46.07 seconds
Started Mar 12 01:57:13 PM PDT 24
Finished Mar 12 01:57:59 PM PDT 24
Peak memory 208600 kb
Host smart-bdf2361f-164a-49e3-88ef-ab3e1207776a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3098801692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.3098801692
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.2717214865
Short name T330
Test name
Test status
Simulation time 2105040467 ps
CPU time 23.36 seconds
Started Mar 12 01:57:23 PM PDT 24
Finished Mar 12 01:57:46 PM PDT 24
Peak memory 222148 kb
Host smart-67603f60-c26e-43ab-ab03-aeff00c6c9d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717214865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.2717214865
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.2996193930
Short name T644
Test name
Test status
Simulation time 86747480 ps
CPU time 4.38 seconds
Started Mar 12 01:57:15 PM PDT 24
Finished Mar 12 01:57:19 PM PDT 24
Peak memory 209880 kb
Host smart-62b4a659-3332-4737-bce2-fa18950a9b2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996193930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.2996193930
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.1079521019
Short name T848
Test name
Test status
Simulation time 87779804 ps
CPU time 1.35 seconds
Started Mar 12 01:57:16 PM PDT 24
Finished Mar 12 01:57:17 PM PDT 24
Peak memory 209756 kb
Host smart-e9e27788-c1f7-4e43-b92f-00b02dc5e449
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079521019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.1079521019
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.893072984
Short name T869
Test name
Test status
Simulation time 30271850 ps
CPU time 0.97 seconds
Started Mar 12 01:57:22 PM PDT 24
Finished Mar 12 01:57:23 PM PDT 24
Peak memory 206240 kb
Host smart-2aaf2bce-508a-4a1d-b612-f895b65c4410
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893072984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.893072984
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.4088695854
Short name T745
Test name
Test status
Simulation time 102954686 ps
CPU time 6.3 seconds
Started Mar 12 01:57:24 PM PDT 24
Finished Mar 12 01:57:30 PM PDT 24
Peak memory 214532 kb
Host smart-33e41cd6-a322-4e30-a232-24a4560bedcc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4088695854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.4088695854
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.2523261927
Short name T385
Test name
Test status
Simulation time 102439960 ps
CPU time 4.23 seconds
Started Mar 12 01:57:23 PM PDT 24
Finished Mar 12 01:57:27 PM PDT 24
Peak memory 207288 kb
Host smart-747a0dd8-d18f-40fa-8770-3e5ff4fa2c64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2523261927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.2523261927
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.3677288099
Short name T25
Test name
Test status
Simulation time 692322960 ps
CPU time 13.36 seconds
Started Mar 12 01:57:24 PM PDT 24
Finished Mar 12 01:57:37 PM PDT 24
Peak memory 214532 kb
Host smart-4a2762b4-6dc5-46d6-b1ac-3c5f799f0b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677288099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.3677288099
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.3261115425
Short name T674
Test name
Test status
Simulation time 77671777 ps
CPU time 2.07 seconds
Started Mar 12 01:57:25 PM PDT 24
Finished Mar 12 01:57:27 PM PDT 24
Peak memory 206368 kb
Host smart-9148ad75-2782-4fba-adc1-f9181c41f8e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261115425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.3261115425
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.2724266082
Short name T343
Test name
Test status
Simulation time 486573919 ps
CPU time 4.27 seconds
Started Mar 12 01:57:24 PM PDT 24
Finished Mar 12 01:57:28 PM PDT 24
Peak memory 208320 kb
Host smart-4fb8bc8f-ff6e-4dd4-af3a-62fb5ed2756c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724266082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.2724266082
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.4113337247
Short name T295
Test name
Test status
Simulation time 183873705 ps
CPU time 2.77 seconds
Started Mar 12 01:57:23 PM PDT 24
Finished Mar 12 01:57:26 PM PDT 24
Peak memory 206700 kb
Host smart-10350ffe-6a0c-4d94-828f-4554def53f24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113337247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.4113337247
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.479342745
Short name T650
Test name
Test status
Simulation time 172098565 ps
CPU time 3.78 seconds
Started Mar 12 01:57:21 PM PDT 24
Finished Mar 12 01:57:25 PM PDT 24
Peak memory 208620 kb
Host smart-ab2a5e7c-e616-4358-9d64-fd285ba1ae0c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479342745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.479342745
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.4255637003
Short name T781
Test name
Test status
Simulation time 352199642 ps
CPU time 9.72 seconds
Started Mar 12 01:57:22 PM PDT 24
Finished Mar 12 01:57:32 PM PDT 24
Peak memory 208744 kb
Host smart-4d7cf9a7-277d-440a-889f-5f29dee96b5d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255637003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.4255637003
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.2265898807
Short name T592
Test name
Test status
Simulation time 72677545 ps
CPU time 3.08 seconds
Started Mar 12 01:57:22 PM PDT 24
Finished Mar 12 01:57:26 PM PDT 24
Peak memory 206784 kb
Host smart-a843b9b1-2edf-4d25-a921-148d46705c09
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265898807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.2265898807
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.2764937871
Short name T491
Test name
Test status
Simulation time 53280927 ps
CPU time 1.76 seconds
Started Mar 12 01:57:27 PM PDT 24
Finished Mar 12 01:57:29 PM PDT 24
Peak memory 214416 kb
Host smart-44b87db0-e813-4d60-9156-8b52b65d847f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764937871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.2764937871
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.3047231467
Short name T748
Test name
Test status
Simulation time 1875467621 ps
CPU time 56.68 seconds
Started Mar 12 01:57:22 PM PDT 24
Finished Mar 12 01:58:19 PM PDT 24
Peak memory 207772 kb
Host smart-014e3b9f-9aa4-459d-b445-d8b8ec6c572b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3047231467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.3047231467
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.4074216889
Short name T843
Test name
Test status
Simulation time 609817126 ps
CPU time 16.52 seconds
Started Mar 12 01:57:26 PM PDT 24
Finished Mar 12 01:57:42 PM PDT 24
Peak memory 209824 kb
Host smart-84d2b500-c8ad-4692-b51b-8326ee0dc1b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4074216889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.4074216889
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.3141495219
Short name T609
Test name
Test status
Simulation time 144220130 ps
CPU time 1.81 seconds
Started Mar 12 01:57:22 PM PDT 24
Finished Mar 12 01:57:24 PM PDT 24
Peak memory 210040 kb
Host smart-fb04f843-bc80-4e8c-97f9-90ffc65f9e27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3141495219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.3141495219
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.827905356
Short name T457
Test name
Test status
Simulation time 26134749 ps
CPU time 0.79 seconds
Started Mar 12 01:57:34 PM PDT 24
Finished Mar 12 01:57:35 PM PDT 24
Peak memory 206104 kb
Host smart-bc54b298-d9da-4d85-9a54-a40dba5437d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=827905356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.827905356
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.3848762327
Short name T770
Test name
Test status
Simulation time 2682665950 ps
CPU time 6.56 seconds
Started Mar 12 01:57:34 PM PDT 24
Finished Mar 12 01:57:41 PM PDT 24
Peak memory 209876 kb
Host smart-3444aa21-c210-4b51-9632-ba473636d591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848762327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.3848762327
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.1433777749
Short name T571
Test name
Test status
Simulation time 655213232 ps
CPU time 2.64 seconds
Started Mar 12 01:57:32 PM PDT 24
Finished Mar 12 01:57:35 PM PDT 24
Peak memory 207708 kb
Host smart-040c6fac-2e46-4964-aa62-8ce68b06d229
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433777749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.1433777749
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.3087991540
Short name T214
Test name
Test status
Simulation time 447479551 ps
CPU time 8.19 seconds
Started Mar 12 01:57:34 PM PDT 24
Finished Mar 12 01:57:43 PM PDT 24
Peak memory 209620 kb
Host smart-9d0d68d3-1d4e-4ee2-807b-c908825cefd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3087991540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.3087991540
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.1218942790
Short name T231
Test name
Test status
Simulation time 192944903 ps
CPU time 5.61 seconds
Started Mar 12 01:57:33 PM PDT 24
Finished Mar 12 01:57:39 PM PDT 24
Peak memory 214396 kb
Host smart-6a132731-3aa0-4316-b058-8e5047e768f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218942790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.1218942790
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.3897587694
Short name T818
Test name
Test status
Simulation time 184117684 ps
CPU time 2.92 seconds
Started Mar 12 01:57:33 PM PDT 24
Finished Mar 12 01:57:36 PM PDT 24
Peak memory 214572 kb
Host smart-bcee21a8-a20b-450f-82bc-ca442fd2f526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897587694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.3897587694
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.1100604912
Short name T492
Test name
Test status
Simulation time 190425327 ps
CPU time 6.86 seconds
Started Mar 12 01:57:32 PM PDT 24
Finished Mar 12 01:57:39 PM PDT 24
Peak memory 218640 kb
Host smart-86e8128a-ad71-41a5-9e87-ebde403940a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100604912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.1100604912
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.15879842
Short name T519
Test name
Test status
Simulation time 163250004 ps
CPU time 4.02 seconds
Started Mar 12 01:57:34 PM PDT 24
Finished Mar 12 01:57:39 PM PDT 24
Peak memory 208940 kb
Host smart-96bed4a0-88f2-4d16-bc4d-51646ed49770
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15879842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.15879842
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.3047589169
Short name T874
Test name
Test status
Simulation time 413739934 ps
CPU time 8.19 seconds
Started Mar 12 01:57:23 PM PDT 24
Finished Mar 12 01:57:31 PM PDT 24
Peak memory 208012 kb
Host smart-994ee0ce-e733-4611-97d3-69910a872e72
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3047589169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.3047589169
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.1574192629
Short name T859
Test name
Test status
Simulation time 786195399 ps
CPU time 6.74 seconds
Started Mar 12 01:57:34 PM PDT 24
Finished Mar 12 01:57:41 PM PDT 24
Peak memory 208808 kb
Host smart-14e37d91-bae1-4269-8b4a-55f710523f28
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574192629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.1574192629
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_smoke.2146432926
Short name T708
Test name
Test status
Simulation time 203699192 ps
CPU time 6.46 seconds
Started Mar 12 01:57:24 PM PDT 24
Finished Mar 12 01:57:31 PM PDT 24
Peak memory 206768 kb
Host smart-b6a13875-bc03-4f54-b602-00d3de2571c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146432926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.2146432926
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.2278544186
Short name T595
Test name
Test status
Simulation time 14173891369 ps
CPU time 139.06 seconds
Started Mar 12 01:57:35 PM PDT 24
Finished Mar 12 01:59:54 PM PDT 24
Peak memory 214360 kb
Host smart-ff2bda66-fa5e-49a9-a29e-55f0da7c7951
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278544186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.2278544186
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_stress_all_with_rand_reset.2672777335
Short name T114
Test name
Test status
Simulation time 735381339 ps
CPU time 8.82 seconds
Started Mar 12 01:57:36 PM PDT 24
Finished Mar 12 01:57:45 PM PDT 24
Peak memory 222796 kb
Host smart-0caaf943-6986-44c1-ac93-1cb181ddd8cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2672777335 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all_with_rand_reset.2672777335
Directory /workspace/25.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.3175600164
Short name T638
Test name
Test status
Simulation time 334697200 ps
CPU time 11.77 seconds
Started Mar 12 01:57:34 PM PDT 24
Finished Mar 12 01:57:47 PM PDT 24
Peak memory 208944 kb
Host smart-05d287c2-7a11-4b0a-b56d-8148df97badf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175600164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.3175600164
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.3364269798
Short name T404
Test name
Test status
Simulation time 61321431 ps
CPU time 2.67 seconds
Started Mar 12 01:57:33 PM PDT 24
Finished Mar 12 01:57:36 PM PDT 24
Peak memory 210212 kb
Host smart-4ce279ce-3f20-4e1c-b4cc-c9a9bc9e5e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364269798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.3364269798
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.1543213782
Short name T445
Test name
Test status
Simulation time 37453249 ps
CPU time 0.76 seconds
Started Mar 12 01:57:46 PM PDT 24
Finished Mar 12 01:57:47 PM PDT 24
Peak memory 206136 kb
Host smart-41a1ba5f-f24c-407f-97ff-592f3313b077
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1543213782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.1543213782
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.355973195
Short name T362
Test name
Test status
Simulation time 83069443 ps
CPU time 3.4 seconds
Started Mar 12 01:57:34 PM PDT 24
Finished Mar 12 01:57:38 PM PDT 24
Peak memory 215372 kb
Host smart-4310bbd0-5a37-4cfd-a242-692812ffc4c6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=355973195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.355973195
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.1822662058
Short name T841
Test name
Test status
Simulation time 76500653 ps
CPU time 2.35 seconds
Started Mar 12 01:57:46 PM PDT 24
Finished Mar 12 01:57:49 PM PDT 24
Peak memory 209020 kb
Host smart-bebf3acd-8d7b-4802-a3c6-6c13d1553636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1822662058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.1822662058
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.2580734694
Short name T576
Test name
Test status
Simulation time 75050894 ps
CPU time 2.85 seconds
Started Mar 12 01:57:35 PM PDT 24
Finished Mar 12 01:57:38 PM PDT 24
Peak memory 207336 kb
Host smart-dda442f0-ea03-4aa6-8421-b7c48044740c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580734694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.2580734694
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.3555938715
Short name T801
Test name
Test status
Simulation time 85097788 ps
CPU time 3.68 seconds
Started Mar 12 01:57:35 PM PDT 24
Finished Mar 12 01:57:39 PM PDT 24
Peak memory 209180 kb
Host smart-76d2e84d-db01-456c-b9c2-10b960b1d2c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3555938715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.3555938715
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.3806376409
Short name T673
Test name
Test status
Simulation time 104353408 ps
CPU time 5.53 seconds
Started Mar 12 01:57:33 PM PDT 24
Finished Mar 12 01:57:40 PM PDT 24
Peak memory 216672 kb
Host smart-8af714be-e8e1-4946-83b9-6a4e0550991f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3806376409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.3806376409
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.407652097
Short name T106
Test name
Test status
Simulation time 281932191 ps
CPU time 3.8 seconds
Started Mar 12 01:57:33 PM PDT 24
Finished Mar 12 01:57:37 PM PDT 24
Peak memory 210072 kb
Host smart-6fba96f4-4cb7-459f-a057-9c5dc512030b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407652097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.407652097
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.268417859
Short name T427
Test name
Test status
Simulation time 64922059 ps
CPU time 2.98 seconds
Started Mar 12 01:57:36 PM PDT 24
Finished Mar 12 01:57:39 PM PDT 24
Peak memory 208132 kb
Host smart-951a6e6c-459d-40b8-8731-ba10241e251d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268417859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.268417859
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.3993667822
Short name T861
Test name
Test status
Simulation time 113597509 ps
CPU time 3.16 seconds
Started Mar 12 01:57:35 PM PDT 24
Finished Mar 12 01:57:38 PM PDT 24
Peak memory 206852 kb
Host smart-13195a51-4c3c-4196-91a6-c3e8eb827e76
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993667822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.3993667822
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.4011130898
Short name T769
Test name
Test status
Simulation time 107645912 ps
CPU time 3.91 seconds
Started Mar 12 01:57:34 PM PDT 24
Finished Mar 12 01:57:38 PM PDT 24
Peak memory 207788 kb
Host smart-4b34a479-d7c7-4bd0-98bb-21f1ade8c1e4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011130898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.4011130898
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.1987536451
Short name T17
Test name
Test status
Simulation time 2645029787 ps
CPU time 17.6 seconds
Started Mar 12 01:57:33 PM PDT 24
Finished Mar 12 01:57:52 PM PDT 24
Peak memory 208340 kb
Host smart-a8a6bdcd-8fc9-4ade-804a-547a1b6d7613
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1987536451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.1987536451
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.4062889902
Short name T222
Test name
Test status
Simulation time 424932824 ps
CPU time 3.5 seconds
Started Mar 12 01:57:49 PM PDT 24
Finished Mar 12 01:57:52 PM PDT 24
Peak memory 209936 kb
Host smart-c95e0fb8-3756-4c89-bd6d-3f704855d03f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062889902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.4062889902
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.1287042443
Short name T237
Test name
Test status
Simulation time 37681986 ps
CPU time 2.38 seconds
Started Mar 12 01:57:35 PM PDT 24
Finished Mar 12 01:57:38 PM PDT 24
Peak memory 208372 kb
Host smart-e16d686d-719e-44f1-9ad5-8f7df0d366f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1287042443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.1287042443
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.2029691428
Short name T844
Test name
Test status
Simulation time 1078733281 ps
CPU time 15.53 seconds
Started Mar 12 01:57:49 PM PDT 24
Finished Mar 12 01:58:04 PM PDT 24
Peak memory 222652 kb
Host smart-8b62ed84-7234-4202-8b64-5f7aaf2ce852
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029691428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.2029691428
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_stress_all_with_rand_reset.3807957212
Short name T129
Test name
Test status
Simulation time 191028082 ps
CPU time 10.5 seconds
Started Mar 12 01:57:48 PM PDT 24
Finished Mar 12 01:57:59 PM PDT 24
Peak memory 222752 kb
Host smart-14b0b229-0f52-43a2-85f5-6cf68f993467
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3807957212 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all_with_rand_reset.3807957212
Directory /workspace/26.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.458189016
Short name T284
Test name
Test status
Simulation time 180726166 ps
CPU time 6.06 seconds
Started Mar 12 01:57:34 PM PDT 24
Finished Mar 12 01:57:41 PM PDT 24
Peak memory 218480 kb
Host smart-9140bb31-307a-4485-9c19-0d6416220121
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=458189016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.458189016
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.341759530
Short name T612
Test name
Test status
Simulation time 44851128 ps
CPU time 0.92 seconds
Started Mar 12 01:57:44 PM PDT 24
Finished Mar 12 01:57:45 PM PDT 24
Peak memory 206160 kb
Host smart-3ee7e584-94b7-4ccb-9566-f223f7c029aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=341759530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.341759530
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.1052187891
Short name T611
Test name
Test status
Simulation time 176682253 ps
CPU time 3 seconds
Started Mar 12 01:57:44 PM PDT 24
Finished Mar 12 01:57:47 PM PDT 24
Peak memory 209556 kb
Host smart-65a7b428-d263-4a15-a661-1a77270b9f0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052187891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.1052187891
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.192018428
Short name T862
Test name
Test status
Simulation time 57133675 ps
CPU time 2.03 seconds
Started Mar 12 01:57:47 PM PDT 24
Finished Mar 12 01:57:49 PM PDT 24
Peak memory 207104 kb
Host smart-1ba38764-3f58-4e3c-8005-a1a995e8823f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=192018428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.192018428
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.849405205
Short name T344
Test name
Test status
Simulation time 651107865 ps
CPU time 4.18 seconds
Started Mar 12 01:57:48 PM PDT 24
Finished Mar 12 01:57:52 PM PDT 24
Peak memory 221148 kb
Host smart-91b79043-7906-481c-a429-a7bb7a0a5515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=849405205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.849405205
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.10057874
Short name T622
Test name
Test status
Simulation time 198853474 ps
CPU time 4.94 seconds
Started Mar 12 01:57:44 PM PDT 24
Finished Mar 12 01:57:49 PM PDT 24
Peak memory 210432 kb
Host smart-12fa804d-b3fe-4c42-a329-4be86b2766ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10057874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.10057874
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_random.1277174752
Short name T789
Test name
Test status
Simulation time 486628916 ps
CPU time 9.85 seconds
Started Mar 12 01:57:48 PM PDT 24
Finished Mar 12 01:57:58 PM PDT 24
Peak memory 208968 kb
Host smart-75ff35e6-084e-46cd-8692-e22395a3e355
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277174752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.1277174752
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.874895699
Short name T335
Test name
Test status
Simulation time 1997611396 ps
CPU time 49.11 seconds
Started Mar 12 01:57:47 PM PDT 24
Finished Mar 12 01:58:36 PM PDT 24
Peak memory 208976 kb
Host smart-e0d99145-793b-4c5c-8f64-3c3cb56dadd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874895699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.874895699
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.1134885555
Short name T524
Test name
Test status
Simulation time 257169389 ps
CPU time 7.14 seconds
Started Mar 12 01:57:48 PM PDT 24
Finished Mar 12 01:57:56 PM PDT 24
Peak memory 209000 kb
Host smart-85d8a6a8-340c-412d-9085-1f6be31a5024
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1134885555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.1134885555
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.1208229023
Short name T777
Test name
Test status
Simulation time 165016340 ps
CPU time 5.15 seconds
Started Mar 12 01:57:46 PM PDT 24
Finished Mar 12 01:57:51 PM PDT 24
Peak memory 208628 kb
Host smart-9db4d3cc-e903-4ddc-a3ac-f57a67dac93f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208229023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.1208229023
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.1825861493
Short name T729
Test name
Test status
Simulation time 438950443 ps
CPU time 4.84 seconds
Started Mar 12 01:57:48 PM PDT 24
Finished Mar 12 01:57:53 PM PDT 24
Peak memory 208924 kb
Host smart-fcf53eef-3a52-455e-95fb-2149ca0cd10f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1825861493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.1825861493
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.1277213320
Short name T607
Test name
Test status
Simulation time 1776471056 ps
CPU time 20.22 seconds
Started Mar 12 01:57:45 PM PDT 24
Finished Mar 12 01:58:05 PM PDT 24
Peak memory 208888 kb
Host smart-7b3d4cf8-463f-472f-bc0c-3a8618355025
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277213320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.1277213320
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.3406169513
Short name T347
Test name
Test status
Simulation time 2655771305 ps
CPU time 23.92 seconds
Started Mar 12 01:57:47 PM PDT 24
Finished Mar 12 01:58:11 PM PDT 24
Peak memory 214568 kb
Host smart-d3cdeb13-2d49-4710-ac51-37ce5db960d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406169513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.3406169513
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.3193015149
Short name T351
Test name
Test status
Simulation time 1367492035 ps
CPU time 10.46 seconds
Started Mar 12 01:57:46 PM PDT 24
Finished Mar 12 01:57:56 PM PDT 24
Peak memory 208768 kb
Host smart-ab253017-084d-48b6-9479-35bf18080277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3193015149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.3193015149
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.2462071707
Short name T195
Test name
Test status
Simulation time 194329357 ps
CPU time 2.81 seconds
Started Mar 12 01:57:47 PM PDT 24
Finished Mar 12 01:57:50 PM PDT 24
Peak memory 219360 kb
Host smart-dfefef5f-2a4c-4f41-974d-959cf927a179
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462071707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.2462071707
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.2263263451
Short name T16
Test name
Test status
Simulation time 36194964 ps
CPU time 1.3 seconds
Started Mar 12 01:58:00 PM PDT 24
Finished Mar 12 01:58:02 PM PDT 24
Peak memory 206216 kb
Host smart-9805da9e-2dd8-443f-81ab-ecaeed1f1b43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263263451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.2263263451
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.2114111320
Short name T430
Test name
Test status
Simulation time 229558275 ps
CPU time 4.18 seconds
Started Mar 12 01:58:02 PM PDT 24
Finished Mar 12 01:58:07 PM PDT 24
Peak memory 215924 kb
Host smart-bf5234ec-7994-40d5-bc69-2bdb89f30e2b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2114111320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.2114111320
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.1281397356
Short name T157
Test name
Test status
Simulation time 815546703 ps
CPU time 3.78 seconds
Started Mar 12 01:58:02 PM PDT 24
Finished Mar 12 01:58:06 PM PDT 24
Peak memory 221480 kb
Host smart-2c6847c7-05e0-429c-b046-3eb8dadb3360
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281397356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.1281397356
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.962372424
Short name T70
Test name
Test status
Simulation time 149566989 ps
CPU time 2.27 seconds
Started Mar 12 01:58:01 PM PDT 24
Finished Mar 12 01:58:04 PM PDT 24
Peak memory 209084 kb
Host smart-550ca63e-1925-4b65-b399-1d1c582aa1c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962372424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.962372424
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.1638627516
Short name T778
Test name
Test status
Simulation time 259112120 ps
CPU time 5.72 seconds
Started Mar 12 01:58:03 PM PDT 24
Finished Mar 12 01:58:08 PM PDT 24
Peak memory 222544 kb
Host smart-138eebf2-bdd6-4a9a-ad5e-f93e1bae1255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1638627516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.1638627516
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.2459925564
Short name T679
Test name
Test status
Simulation time 50179297 ps
CPU time 3.55 seconds
Started Mar 12 01:58:00 PM PDT 24
Finished Mar 12 01:58:04 PM PDT 24
Peak memory 208928 kb
Host smart-5b532ed1-c485-41e6-9baf-f9a0195b912d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459925564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.2459925564
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.3198448655
Short name T366
Test name
Test status
Simulation time 102926822 ps
CPU time 4.92 seconds
Started Mar 12 01:57:48 PM PDT 24
Finished Mar 12 01:57:53 PM PDT 24
Peak memory 214504 kb
Host smart-f8f22bc6-0667-462d-9165-0fd67abf08a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3198448655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.3198448655
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.2403924632
Short name T811
Test name
Test status
Simulation time 580701277 ps
CPU time 3.12 seconds
Started Mar 12 01:57:48 PM PDT 24
Finished Mar 12 01:57:51 PM PDT 24
Peak memory 206808 kb
Host smart-c65187b6-4f0f-4371-ba60-3331fcd08602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2403924632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.2403924632
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.3156657749
Short name T791
Test name
Test status
Simulation time 96359011 ps
CPU time 4.38 seconds
Started Mar 12 01:57:47 PM PDT 24
Finished Mar 12 01:57:52 PM PDT 24
Peak memory 208892 kb
Host smart-bec98a35-d96a-4f56-ac79-da28ba3831d5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3156657749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.3156657749
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.3477303155
Short name T696
Test name
Test status
Simulation time 98403570 ps
CPU time 3.18 seconds
Started Mar 12 01:57:46 PM PDT 24
Finished Mar 12 01:57:50 PM PDT 24
Peak memory 206956 kb
Host smart-46eb4e0b-d651-4f73-b0d9-364b4dcdd8ab
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477303155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.3477303155
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.3227602608
Short name T831
Test name
Test status
Simulation time 245762416 ps
CPU time 7.58 seconds
Started Mar 12 01:57:47 PM PDT 24
Finished Mar 12 01:57:55 PM PDT 24
Peak memory 208640 kb
Host smart-3973e8ee-4033-4818-8e93-db008c0a90bb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227602608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.3227602608
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.1713911096
Short name T328
Test name
Test status
Simulation time 329482937 ps
CPU time 4.06 seconds
Started Mar 12 01:58:01 PM PDT 24
Finished Mar 12 01:58:05 PM PDT 24
Peak memory 208020 kb
Host smart-d769a283-5e04-4998-be7b-b8ccdb38e56d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1713911096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.1713911096
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.3848160898
Short name T86
Test name
Test status
Simulation time 161136846 ps
CPU time 4.47 seconds
Started Mar 12 01:57:47 PM PDT 24
Finished Mar 12 01:57:52 PM PDT 24
Peak memory 208260 kb
Host smart-30e0993a-b8d0-4510-a8a2-b2e448603a17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3848160898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.3848160898
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all_with_rand_reset.1697263732
Short name T817
Test name
Test status
Simulation time 291563398 ps
CPU time 10.1 seconds
Started Mar 12 01:58:02 PM PDT 24
Finished Mar 12 01:58:12 PM PDT 24
Peak memory 220828 kb
Host smart-7179f60c-90d7-44c2-90af-a528d54a8ef8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1697263732 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all_with_rand_reset.1697263732
Directory /workspace/28.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.93407039
Short name T599
Test name
Test status
Simulation time 1252229507 ps
CPU time 33.14 seconds
Started Mar 12 01:58:00 PM PDT 24
Finished Mar 12 01:58:33 PM PDT 24
Peak memory 209068 kb
Host smart-aa509e72-80cc-4fac-93a5-fea7db337082
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93407039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.93407039
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.3165470994
Short name T790
Test name
Test status
Simulation time 93745156 ps
CPU time 2.74 seconds
Started Mar 12 01:58:01 PM PDT 24
Finished Mar 12 01:58:04 PM PDT 24
Peak memory 209652 kb
Host smart-354a5992-7ba1-443e-a181-52702d2d2af1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165470994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.3165470994
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.3693342632
Short name T495
Test name
Test status
Simulation time 34435806 ps
CPU time 0.76 seconds
Started Mar 12 01:58:02 PM PDT 24
Finished Mar 12 01:58:03 PM PDT 24
Peak memory 205984 kb
Host smart-25453070-d76f-4978-b0fe-f55a3aaf6f24
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3693342632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.3693342632
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.853641023
Short name T271
Test name
Test status
Simulation time 72985815 ps
CPU time 3.5 seconds
Started Mar 12 01:58:00 PM PDT 24
Finished Mar 12 01:58:04 PM PDT 24
Peak memory 214452 kb
Host smart-e78a7917-6f06-4347-ab34-580dbdb26484
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=853641023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.853641023
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.3401211314
Short name T667
Test name
Test status
Simulation time 143163938 ps
CPU time 2.61 seconds
Started Mar 12 01:58:00 PM PDT 24
Finished Mar 12 01:58:03 PM PDT 24
Peak memory 209992 kb
Host smart-a78151f6-7d15-49ec-90ec-064756c8c87d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3401211314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.3401211314
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.2226366802
Short name T853
Test name
Test status
Simulation time 133576057 ps
CPU time 1.52 seconds
Started Mar 12 01:58:00 PM PDT 24
Finished Mar 12 01:58:02 PM PDT 24
Peak memory 207476 kb
Host smart-153998e1-7f02-41fe-beb8-ae2691f5e523
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226366802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.2226366802
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.1458835965
Short name T497
Test name
Test status
Simulation time 49918410 ps
CPU time 3.12 seconds
Started Mar 12 01:58:01 PM PDT 24
Finished Mar 12 01:58:05 PM PDT 24
Peak memory 219832 kb
Host smart-2b1fc681-7735-47bc-9c09-4074fd4cecf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458835965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.1458835965
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_random.3393250074
Short name T813
Test name
Test status
Simulation time 590054673 ps
CPU time 9.51 seconds
Started Mar 12 01:57:59 PM PDT 24
Finished Mar 12 01:58:09 PM PDT 24
Peak memory 209364 kb
Host smart-b8521263-14cb-4832-ba4e-76e747714fc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3393250074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.3393250074
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.3691994433
Short name T509
Test name
Test status
Simulation time 387750042 ps
CPU time 4.91 seconds
Started Mar 12 01:58:02 PM PDT 24
Finished Mar 12 01:58:07 PM PDT 24
Peak memory 208544 kb
Host smart-682d0abf-b122-4f9e-a543-babdd640191c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691994433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.3691994433
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.3269502112
Short name T498
Test name
Test status
Simulation time 26003969 ps
CPU time 2.11 seconds
Started Mar 12 01:58:01 PM PDT 24
Finished Mar 12 01:58:04 PM PDT 24
Peak memory 208664 kb
Host smart-37bc9ce2-f074-4350-9aee-662fc7dde449
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269502112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.3269502112
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.834568220
Short name T546
Test name
Test status
Simulation time 505066082 ps
CPU time 3.96 seconds
Started Mar 12 01:58:01 PM PDT 24
Finished Mar 12 01:58:05 PM PDT 24
Peak memory 208620 kb
Host smart-a862ab3c-a195-404c-8056-092dacc55ea6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834568220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.834568220
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.569477995
Short name T2
Test name
Test status
Simulation time 210676439 ps
CPU time 4.03 seconds
Started Mar 12 01:58:01 PM PDT 24
Finished Mar 12 01:58:05 PM PDT 24
Peak memory 208840 kb
Host smart-a6ca4569-b0d8-4c07-8c1c-51e88896933f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=569477995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.569477995
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.881750714
Short name T833
Test name
Test status
Simulation time 51569240 ps
CPU time 2.28 seconds
Started Mar 12 01:58:02 PM PDT 24
Finished Mar 12 01:58:04 PM PDT 24
Peak memory 207128 kb
Host smart-21cd787d-bb21-486f-956d-e86530ee657c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=881750714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.881750714
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.1458482438
Short name T717
Test name
Test status
Simulation time 426027819 ps
CPU time 8.5 seconds
Started Mar 12 01:58:01 PM PDT 24
Finished Mar 12 01:58:09 PM PDT 24
Peak memory 207860 kb
Host smart-5500affc-c2cf-47a0-96de-cb79a5abc32b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458482438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.1458482438
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.983798347
Short name T795
Test name
Test status
Simulation time 4732580052 ps
CPU time 50.13 seconds
Started Mar 12 01:58:01 PM PDT 24
Finished Mar 12 01:58:52 PM PDT 24
Peak memory 222712 kb
Host smart-ebb7fd3b-0c3a-4821-a175-26382e632cee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=983798347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.983798347
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.1228904954
Short name T294
Test name
Test status
Simulation time 31805461 ps
CPU time 2.45 seconds
Started Mar 12 01:58:02 PM PDT 24
Finished Mar 12 01:58:04 PM PDT 24
Peak memory 207096 kb
Host smart-0f35ebef-8cad-4f15-9674-eebbce552c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228904954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.1228904954
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.3709854361
Short name T690
Test name
Test status
Simulation time 75033523 ps
CPU time 3.48 seconds
Started Mar 12 01:57:59 PM PDT 24
Finished Mar 12 01:58:03 PM PDT 24
Peak memory 210228 kb
Host smart-6e9c23d2-7b33-4c5c-a4a6-638a94dc103c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709854361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.3709854361
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.2531840785
Short name T444
Test name
Test status
Simulation time 19529978 ps
CPU time 1.05 seconds
Started Mar 12 01:54:52 PM PDT 24
Finished Mar 12 01:54:54 PM PDT 24
Peak memory 206224 kb
Host smart-5f174277-7603-493d-b876-b97007b85f5e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531840785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.2531840785
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.2339380913
Short name T75
Test name
Test status
Simulation time 37544023 ps
CPU time 2.06 seconds
Started Mar 12 01:54:43 PM PDT 24
Finished Mar 12 01:54:46 PM PDT 24
Peak memory 209864 kb
Host smart-d61eb530-1ed9-48bc-91a4-6bcad704c810
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339380913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.2339380913
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.1552552882
Short name T24
Test name
Test status
Simulation time 124121360 ps
CPU time 4.99 seconds
Started Mar 12 01:54:43 PM PDT 24
Finished Mar 12 01:54:48 PM PDT 24
Peak memory 219156 kb
Host smart-5c3143c4-195c-4d7d-b34c-b7278e621af4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1552552882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.1552552882
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.309026454
Short name T280
Test name
Test status
Simulation time 538299740 ps
CPU time 12.19 seconds
Started Mar 12 01:54:43 PM PDT 24
Finished Mar 12 01:54:55 PM PDT 24
Peak memory 222540 kb
Host smart-ac6e4b53-3f79-4e48-b8e6-dd8274c03af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=309026454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.309026454
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.2131354594
Short name T510
Test name
Test status
Simulation time 125067748 ps
CPU time 2.98 seconds
Started Mar 12 01:54:43 PM PDT 24
Finished Mar 12 01:54:46 PM PDT 24
Peak memory 208432 kb
Host smart-f838cd38-bdb3-4bd5-a1d2-89a741a75da0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131354594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.2131354594
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.2140220739
Short name T105
Test name
Test status
Simulation time 242406448 ps
CPU time 4.23 seconds
Started Mar 12 01:54:41 PM PDT 24
Finished Mar 12 01:54:46 PM PDT 24
Peak memory 209784 kb
Host smart-b934f4b9-c7bb-4746-896a-e8c18a339255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2140220739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.2140220739
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.668191272
Short name T42
Test name
Test status
Simulation time 15121014022 ps
CPU time 215.21 seconds
Started Mar 12 01:54:52 PM PDT 24
Finished Mar 12 01:58:28 PM PDT 24
Peak memory 290992 kb
Host smart-dd335c21-3c31-443f-bcda-e9d168eafabc
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=668191272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.668191272
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sideload.3747320671
Short name T276
Test name
Test status
Simulation time 1114151990 ps
CPU time 5.22 seconds
Started Mar 12 01:54:42 PM PDT 24
Finished Mar 12 01:54:47 PM PDT 24
Peak memory 208376 kb
Host smart-a0ecef8f-c6d4-4011-a60f-630a519b7b89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747320671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.3747320671
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.2364393198
Short name T873
Test name
Test status
Simulation time 978029376 ps
CPU time 14.99 seconds
Started Mar 12 01:54:42 PM PDT 24
Finished Mar 12 01:54:57 PM PDT 24
Peak memory 207960 kb
Host smart-9f3c397e-277c-4a57-b237-3e09a9a33e3b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2364393198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.2364393198
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.3322178130
Short name T561
Test name
Test status
Simulation time 206345311 ps
CPU time 3.01 seconds
Started Mar 12 01:54:43 PM PDT 24
Finished Mar 12 01:54:46 PM PDT 24
Peak memory 208812 kb
Host smart-6677229b-d53c-4781-9038-b6400ed054d8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3322178130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.3322178130
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.1102837286
Short name T504
Test name
Test status
Simulation time 753672069 ps
CPU time 7.01 seconds
Started Mar 12 01:54:42 PM PDT 24
Finished Mar 12 01:54:49 PM PDT 24
Peak memory 208100 kb
Host smart-d8cec35a-6917-43d7-8b2f-6163d6fd63bc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1102837286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.1102837286
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.3062912402
Short name T787
Test name
Test status
Simulation time 57464206 ps
CPU time 2.86 seconds
Started Mar 12 01:54:42 PM PDT 24
Finished Mar 12 01:54:45 PM PDT 24
Peak memory 208496 kb
Host smart-acd414c5-58c3-43d1-b732-f21225409983
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062912402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.3062912402
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.2106991229
Short name T460
Test name
Test status
Simulation time 409530000 ps
CPU time 3.7 seconds
Started Mar 12 01:54:42 PM PDT 24
Finished Mar 12 01:54:46 PM PDT 24
Peak memory 206576 kb
Host smart-f07296e5-7f5c-4bf1-9243-cde5f458dbfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106991229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.2106991229
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.3333938643
Short name T80
Test name
Test status
Simulation time 6715583846 ps
CPU time 47.5 seconds
Started Mar 12 01:54:41 PM PDT 24
Finished Mar 12 01:55:29 PM PDT 24
Peak memory 209076 kb
Host smart-a53b25f2-e556-41b6-8c3d-0d56a2b361b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333938643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.3333938643
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.1723749021
Short name T788
Test name
Test status
Simulation time 1933003801 ps
CPU time 11.17 seconds
Started Mar 12 01:54:41 PM PDT 24
Finished Mar 12 01:54:52 PM PDT 24
Peak memory 210456 kb
Host smart-28e3cf3b-c35d-4d49-8b78-d2da080c01f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1723749021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.1723749021
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.422786572
Short name T1
Test name
Test status
Simulation time 33784139 ps
CPU time 0.71 seconds
Started Mar 12 01:58:14 PM PDT 24
Finished Mar 12 01:58:14 PM PDT 24
Peak memory 206068 kb
Host smart-10845b06-bedc-43ea-ac05-4ad3cdf30582
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=422786572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.422786572
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.871727972
Short name T435
Test name
Test status
Simulation time 55115046 ps
CPU time 3.97 seconds
Started Mar 12 01:58:01 PM PDT 24
Finished Mar 12 01:58:05 PM PDT 24
Peak memory 215268 kb
Host smart-7a44910b-ae74-443d-a140-95f1ebca4b6d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=871727972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.871727972
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.3221725964
Short name T741
Test name
Test status
Simulation time 709824297 ps
CPU time 5.46 seconds
Started Mar 12 01:58:13 PM PDT 24
Finished Mar 12 01:58:19 PM PDT 24
Peak memory 210060 kb
Host smart-864dbd1e-8521-42c2-9d7e-c81b792151fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221725964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.3221725964
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.2702171314
Short name T112
Test name
Test status
Simulation time 9390632794 ps
CPU time 49.6 seconds
Started Mar 12 01:58:01 PM PDT 24
Finished Mar 12 01:58:51 PM PDT 24
Peak memory 214584 kb
Host smart-4d13f647-aaa0-4a0f-b4da-d3a28944bfd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702171314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.2702171314
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.664780706
Short name T808
Test name
Test status
Simulation time 397389112 ps
CPU time 3.76 seconds
Started Mar 12 01:58:13 PM PDT 24
Finished Mar 12 01:58:17 PM PDT 24
Peak memory 222752 kb
Host smart-36657a2e-c3c4-4c57-8869-37be68042d49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664780706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.664780706
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.2810877728
Short name T332
Test name
Test status
Simulation time 279064920 ps
CPU time 7.31 seconds
Started Mar 12 01:58:12 PM PDT 24
Finished Mar 12 01:58:19 PM PDT 24
Peak memory 214552 kb
Host smart-e3c79d9a-9b6b-4851-b405-80ee8a62bbbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810877728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.2810877728
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.1806641549
Short name T350
Test name
Test status
Simulation time 132900870 ps
CPU time 4.1 seconds
Started Mar 12 01:58:01 PM PDT 24
Finished Mar 12 01:58:06 PM PDT 24
Peak memory 208612 kb
Host smart-85590766-0b04-4353-9b9b-9a3bb9b20a51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1806641549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.1806641549
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.1271664188
Short name T514
Test name
Test status
Simulation time 580877520 ps
CPU time 12.5 seconds
Started Mar 12 01:58:03 PM PDT 24
Finished Mar 12 01:58:15 PM PDT 24
Peak memory 218708 kb
Host smart-2e3283d2-9f76-4764-8a7b-af7ed5893130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1271664188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.1271664188
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.2122987306
Short name T587
Test name
Test status
Simulation time 619350792 ps
CPU time 4.01 seconds
Started Mar 12 01:58:02 PM PDT 24
Finished Mar 12 01:58:06 PM PDT 24
Peak memory 206728 kb
Host smart-eab6842c-6e98-453d-8013-1fb0a390cf5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2122987306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.2122987306
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.3985994412
Short name T570
Test name
Test status
Simulation time 182362093 ps
CPU time 1.96 seconds
Started Mar 12 01:58:01 PM PDT 24
Finished Mar 12 01:58:03 PM PDT 24
Peak memory 206860 kb
Host smart-c58d2f41-3ec6-400a-8791-26d2773d8bfb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985994412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.3985994412
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.2656486668
Short name T244
Test name
Test status
Simulation time 46800028 ps
CPU time 2.94 seconds
Started Mar 12 01:58:02 PM PDT 24
Finished Mar 12 01:58:05 PM PDT 24
Peak memory 206908 kb
Host smart-b2e5c79f-0b93-4158-9db3-a46c9afde43d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2656486668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.2656486668
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.946270865
Short name T884
Test name
Test status
Simulation time 367569989 ps
CPU time 3.44 seconds
Started Mar 12 01:58:02 PM PDT 24
Finished Mar 12 01:58:06 PM PDT 24
Peak memory 208580 kb
Host smart-df9ce96b-4a76-48d6-8710-1e2d4ddf9eb2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946270865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.946270865
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.1666113838
Short name T651
Test name
Test status
Simulation time 202562840 ps
CPU time 4.7 seconds
Started Mar 12 01:58:14 PM PDT 24
Finished Mar 12 01:58:19 PM PDT 24
Peak memory 218556 kb
Host smart-d9ee9bd9-b9ca-4c70-9669-7093f2c9c8b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666113838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.1666113838
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.476415042
Short name T465
Test name
Test status
Simulation time 59110260 ps
CPU time 3.07 seconds
Started Mar 12 01:58:00 PM PDT 24
Finished Mar 12 01:58:04 PM PDT 24
Peak memory 208488 kb
Host smart-30367123-6112-4918-9f2d-8af6a5835cc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476415042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.476415042
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.2100616441
Short name T205
Test name
Test status
Simulation time 3624764913 ps
CPU time 88.3 seconds
Started Mar 12 01:58:15 PM PDT 24
Finished Mar 12 01:59:44 PM PDT 24
Peak memory 217652 kb
Host smart-a8c2064a-78d8-41bb-b602-8571f6a8365b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100616441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.2100616441
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.2041063645
Short name T339
Test name
Test status
Simulation time 2782991312 ps
CPU time 19.31 seconds
Started Mar 12 01:58:14 PM PDT 24
Finished Mar 12 01:58:33 PM PDT 24
Peak memory 210180 kb
Host smart-e77d2e78-05be-4256-9422-82ab6a73c12a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041063645 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.2041063645
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.664819132
Short name T38
Test name
Test status
Simulation time 75261343 ps
CPU time 2.52 seconds
Started Mar 12 01:58:13 PM PDT 24
Finished Mar 12 01:58:16 PM PDT 24
Peak memory 210128 kb
Host smart-728e7e82-df21-4258-93f5-56d0ff271a34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664819132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.664819132
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.3895321694
Short name T141
Test name
Test status
Simulation time 51497188 ps
CPU time 0.76 seconds
Started Mar 12 01:58:15 PM PDT 24
Finished Mar 12 01:58:16 PM PDT 24
Peak memory 206148 kb
Host smart-f18556c3-1a47-4110-b1ad-4f20356ef0e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895321694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.3895321694
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.638296301
Short name T267
Test name
Test status
Simulation time 717048270 ps
CPU time 12.14 seconds
Started Mar 12 01:58:13 PM PDT 24
Finished Mar 12 01:58:25 PM PDT 24
Peak memory 215276 kb
Host smart-3bc60445-afa3-4eef-8380-441fa1e3dbd9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=638296301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.638296301
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.2585079244
Short name T22
Test name
Test status
Simulation time 113631133 ps
CPU time 3.1 seconds
Started Mar 12 01:58:17 PM PDT 24
Finished Mar 12 01:58:21 PM PDT 24
Peak memory 221456 kb
Host smart-a411b469-5902-48c0-9e3a-d66cdcd3afb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585079244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.2585079244
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.1609886552
Short name T527
Test name
Test status
Simulation time 518992286 ps
CPU time 4.47 seconds
Started Mar 12 01:58:13 PM PDT 24
Finished Mar 12 01:58:18 PM PDT 24
Peak memory 207340 kb
Host smart-eb6fe9ab-a1cc-4e6c-83a7-d008cdea67ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609886552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.1609886552
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.2846135217
Short name T96
Test name
Test status
Simulation time 58277076 ps
CPU time 2.42 seconds
Started Mar 12 01:58:14 PM PDT 24
Finished Mar 12 01:58:17 PM PDT 24
Peak memory 214424 kb
Host smart-b3843e8e-e590-4e37-9311-0a4ed5c16e1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846135217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.2846135217
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.2449383097
Short name T260
Test name
Test status
Simulation time 73399005 ps
CPU time 3.17 seconds
Started Mar 12 01:58:16 PM PDT 24
Finished Mar 12 01:58:21 PM PDT 24
Peak memory 210508 kb
Host smart-22a324c8-30ff-413c-ac6d-1b04d51b4333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449383097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.2449383097
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.85156325
Short name T598
Test name
Test status
Simulation time 1303005902 ps
CPU time 9.83 seconds
Started Mar 12 01:58:15 PM PDT 24
Finished Mar 12 01:58:25 PM PDT 24
Peak memory 218612 kb
Host smart-fa676930-befc-4e45-9dfd-489d145cb7dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=85156325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.85156325
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.3300196457
Short name T760
Test name
Test status
Simulation time 29690258 ps
CPU time 2.22 seconds
Started Mar 12 01:58:12 PM PDT 24
Finished Mar 12 01:58:15 PM PDT 24
Peak memory 206644 kb
Host smart-9ba05a57-d1b5-4baa-81c3-737a9308f653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300196457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.3300196457
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.2669935445
Short name T147
Test name
Test status
Simulation time 1725303012 ps
CPU time 45.11 seconds
Started Mar 12 01:58:15 PM PDT 24
Finished Mar 12 01:59:00 PM PDT 24
Peak memory 208212 kb
Host smart-5590e266-de0b-4ce5-82d3-994d456bd6cf
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2669935445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.2669935445
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.2286811827
Short name T531
Test name
Test status
Simulation time 30273034 ps
CPU time 2.2 seconds
Started Mar 12 01:58:14 PM PDT 24
Finished Mar 12 01:58:16 PM PDT 24
Peak memory 206904 kb
Host smart-f82e265a-9922-49a0-befe-ffca2954159e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286811827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.2286811827
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.303538551
Short name T624
Test name
Test status
Simulation time 34083562 ps
CPU time 2.34 seconds
Started Mar 12 01:58:16 PM PDT 24
Finished Mar 12 01:58:18 PM PDT 24
Peak memory 208796 kb
Host smart-26fddf3d-91c6-4212-b283-0ce755faed94
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303538551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.303538551
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.3006597687
Short name T743
Test name
Test status
Simulation time 71405899 ps
CPU time 3.21 seconds
Started Mar 12 01:58:18 PM PDT 24
Finished Mar 12 01:58:22 PM PDT 24
Peak memory 209868 kb
Host smart-552328cd-c8b0-4a0f-b6bc-073c825f4d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006597687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.3006597687
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.1178180145
Short name T888
Test name
Test status
Simulation time 95048942 ps
CPU time 4.16 seconds
Started Mar 12 01:58:13 PM PDT 24
Finished Mar 12 01:58:18 PM PDT 24
Peak memory 207308 kb
Host smart-85d7dc6c-caa0-406b-81a0-69393bcec7aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1178180145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.1178180145
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.578554295
Short name T603
Test name
Test status
Simulation time 100985112 ps
CPU time 4.68 seconds
Started Mar 12 01:58:14 PM PDT 24
Finished Mar 12 01:58:19 PM PDT 24
Peak memory 207292 kb
Host smart-fcb2443e-ef11-4ba2-9b89-6489a8e08eff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=578554295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.578554295
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.1707196305
Short name T881
Test name
Test status
Simulation time 74423704 ps
CPU time 2.41 seconds
Started Mar 12 01:58:13 PM PDT 24
Finished Mar 12 01:58:15 PM PDT 24
Peak memory 210176 kb
Host smart-1b5ca4e7-01a3-407d-b3a3-518c1db09afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1707196305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.1707196305
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.1818296914
Short name T776
Test name
Test status
Simulation time 11155944 ps
CPU time 0.75 seconds
Started Mar 12 01:58:13 PM PDT 24
Finished Mar 12 01:58:14 PM PDT 24
Peak memory 206180 kb
Host smart-6e86d97b-bbdf-486e-bc26-fb981e4c7bbd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818296914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.1818296914
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.3313197005
Short name T215
Test name
Test status
Simulation time 34559043 ps
CPU time 2.74 seconds
Started Mar 12 01:58:15 PM PDT 24
Finished Mar 12 01:58:17 PM PDT 24
Peak memory 214576 kb
Host smart-c4168380-9945-416b-a1b2-0234c9fce31b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3313197005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.3313197005
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.1270516408
Short name T773
Test name
Test status
Simulation time 22316721 ps
CPU time 1.63 seconds
Started Mar 12 01:58:17 PM PDT 24
Finished Mar 12 01:58:20 PM PDT 24
Peak memory 209828 kb
Host smart-790378ac-c2d8-4ff6-8975-7b849d2dcab8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270516408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.1270516408
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.3588614209
Short name T854
Test name
Test status
Simulation time 619734032 ps
CPU time 5.78 seconds
Started Mar 12 01:58:17 PM PDT 24
Finished Mar 12 01:58:23 PM PDT 24
Peak memory 208892 kb
Host smart-34d35205-d944-4619-b9b7-628c59997d67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588614209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.3588614209
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.4204738112
Short name T146
Test name
Test status
Simulation time 390396810 ps
CPU time 4.99 seconds
Started Mar 12 01:58:13 PM PDT 24
Finished Mar 12 01:58:19 PM PDT 24
Peak memory 209068 kb
Host smart-c42ad6f8-8246-4ffd-aaee-2a1862b7dd9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204738112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.4204738112
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.1808860100
Short name T631
Test name
Test status
Simulation time 389897905 ps
CPU time 4.84 seconds
Started Mar 12 01:58:15 PM PDT 24
Finished Mar 12 01:58:20 PM PDT 24
Peak memory 210132 kb
Host smart-16a39122-b8bd-49ba-9f9d-e5e1c6412af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808860100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.1808860100
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.2919233425
Short name T521
Test name
Test status
Simulation time 944446815 ps
CPU time 7.75 seconds
Started Mar 12 01:58:15 PM PDT 24
Finished Mar 12 01:58:23 PM PDT 24
Peak memory 208632 kb
Host smart-c095a1b5-8fe0-46b8-bfd4-2db42ca42e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2919233425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.2919233425
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.2795460555
Short name T399
Test name
Test status
Simulation time 112052078 ps
CPU time 3.54 seconds
Started Mar 12 01:58:16 PM PDT 24
Finished Mar 12 01:58:19 PM PDT 24
Peak memory 207804 kb
Host smart-73004589-82a1-4627-b328-304061becec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795460555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.2795460555
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.2551386968
Short name T15
Test name
Test status
Simulation time 627524183 ps
CPU time 7.24 seconds
Started Mar 12 01:58:16 PM PDT 24
Finished Mar 12 01:58:23 PM PDT 24
Peak memory 208676 kb
Host smart-31cd276a-ae3a-4147-bb79-04925d46251b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551386968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.2551386968
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.408714974
Short name T535
Test name
Test status
Simulation time 20618046 ps
CPU time 1.84 seconds
Started Mar 12 01:58:15 PM PDT 24
Finished Mar 12 01:58:17 PM PDT 24
Peak memory 206696 kb
Host smart-35a30a26-dacf-4931-8f5f-65a57801d0b3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=408714974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.408714974
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.3060596661
Short name T676
Test name
Test status
Simulation time 24942600 ps
CPU time 1.92 seconds
Started Mar 12 01:58:15 PM PDT 24
Finished Mar 12 01:58:17 PM PDT 24
Peak memory 206748 kb
Host smart-83ff1b35-6841-437c-ae59-2322949fd3f0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3060596661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.3060596661
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.1192541714
Short name T740
Test name
Test status
Simulation time 266215033 ps
CPU time 3.14 seconds
Started Mar 12 01:58:18 PM PDT 24
Finished Mar 12 01:58:22 PM PDT 24
Peak memory 209308 kb
Host smart-9662065f-2acc-4594-8c44-53ade097c0df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192541714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.1192541714
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.810082027
Short name T451
Test name
Test status
Simulation time 71900302 ps
CPU time 3.32 seconds
Started Mar 12 01:58:15 PM PDT 24
Finished Mar 12 01:58:19 PM PDT 24
Peak memory 208448 kb
Host smart-7353b374-dd41-41c9-91c6-68cb7ef37f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810082027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.810082027
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.1619842764
Short name T829
Test name
Test status
Simulation time 1176825960 ps
CPU time 24.07 seconds
Started Mar 12 01:58:16 PM PDT 24
Finished Mar 12 01:58:40 PM PDT 24
Peak memory 222636 kb
Host smart-ed839468-3f4b-4b1b-97cc-2e208625bc81
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1619842764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.1619842764
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_stress_all_with_rand_reset.4067083992
Short name T196
Test name
Test status
Simulation time 4279571097 ps
CPU time 24.03 seconds
Started Mar 12 01:58:16 PM PDT 24
Finished Mar 12 01:58:40 PM PDT 24
Peak memory 222872 kb
Host smart-b4d1891c-d801-4745-8675-e2b61f505ad6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067083992 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all_with_rand_reset.4067083992
Directory /workspace/32.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.3113971640
Short name T797
Test name
Test status
Simulation time 946380906 ps
CPU time 11.55 seconds
Started Mar 12 01:58:15 PM PDT 24
Finished Mar 12 01:58:27 PM PDT 24
Peak memory 218348 kb
Host smart-190b0594-67a4-404a-8b98-9a182812bfef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3113971640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.3113971640
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.3472466348
Short name T410
Test name
Test status
Simulation time 240060358 ps
CPU time 1.82 seconds
Started Mar 12 01:58:14 PM PDT 24
Finished Mar 12 01:58:16 PM PDT 24
Peak memory 210184 kb
Host smart-4cb12bdc-f6cf-44a6-b922-1c32eeeb567b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3472466348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.3472466348
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.1743884959
Short name T685
Test name
Test status
Simulation time 12950271 ps
CPU time 0.78 seconds
Started Mar 12 01:58:19 PM PDT 24
Finished Mar 12 01:58:21 PM PDT 24
Peak memory 206164 kb
Host smart-94e18014-49bd-4ee7-b6ea-1ba15ae18359
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1743884959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.1743884959
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.2065539130
Short name T62
Test name
Test status
Simulation time 55622191 ps
CPU time 2.73 seconds
Started Mar 12 01:58:16 PM PDT 24
Finished Mar 12 01:58:19 PM PDT 24
Peak memory 208980 kb
Host smart-b73fc64b-348a-48b3-a598-089ad51ed177
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2065539130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.2065539130
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.1815663328
Short name T707
Test name
Test status
Simulation time 182211525 ps
CPU time 3.43 seconds
Started Mar 12 01:58:18 PM PDT 24
Finished Mar 12 01:58:22 PM PDT 24
Peak memory 220500 kb
Host smart-5d2bac7d-6d4b-465a-84ee-6c124c293522
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815663328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.1815663328
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.520346978
Short name T389
Test name
Test status
Simulation time 3379316073 ps
CPU time 50.97 seconds
Started Mar 12 01:58:16 PM PDT 24
Finished Mar 12 01:59:07 PM PDT 24
Peak memory 220208 kb
Host smart-aab2ba9c-87c3-46d3-82b0-131e5019e2b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520346978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.520346978
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.3488172436
Short name T57
Test name
Test status
Simulation time 143205236 ps
CPU time 3.08 seconds
Started Mar 12 01:58:15 PM PDT 24
Finished Mar 12 01:58:18 PM PDT 24
Peak memory 220156 kb
Host smart-55bf5b1b-3caf-44c4-9a74-ac7c9f444ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3488172436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.3488172436
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.2903890790
Short name T628
Test name
Test status
Simulation time 930345538 ps
CPU time 10.31 seconds
Started Mar 12 01:58:16 PM PDT 24
Finished Mar 12 01:58:27 PM PDT 24
Peak memory 209220 kb
Host smart-97654cdb-6ddd-4dd3-9c34-7fba7913f5e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2903890790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.2903890790
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.676170161
Short name T726
Test name
Test status
Simulation time 140292243 ps
CPU time 2.61 seconds
Started Mar 12 01:58:14 PM PDT 24
Finished Mar 12 01:58:17 PM PDT 24
Peak memory 206780 kb
Host smart-dcc85701-e25f-41d7-aa25-3f2b4a374074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=676170161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.676170161
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.4179378390
Short name T83
Test name
Test status
Simulation time 16418595888 ps
CPU time 51.69 seconds
Started Mar 12 01:58:15 PM PDT 24
Finished Mar 12 01:59:07 PM PDT 24
Peak memory 207896 kb
Host smart-a34c8b82-cd94-4ca5-94c0-2c8b91542183
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4179378390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.4179378390
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.2204142445
Short name T370
Test name
Test status
Simulation time 2146628128 ps
CPU time 24.24 seconds
Started Mar 12 01:58:16 PM PDT 24
Finished Mar 12 01:58:42 PM PDT 24
Peak memory 208312 kb
Host smart-b9bad795-43d3-4e1a-9f1a-ddb8e557f720
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204142445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.2204142445
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.231779949
Short name T145
Test name
Test status
Simulation time 142824518 ps
CPU time 4.43 seconds
Started Mar 12 01:58:15 PM PDT 24
Finished Mar 12 01:58:20 PM PDT 24
Peak memory 206884 kb
Host smart-8e016ae2-5828-4715-83c8-48cb1e9b8eae
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231779949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.231779949
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.4120178108
Short name T437
Test name
Test status
Simulation time 667544305 ps
CPU time 9.41 seconds
Started Mar 12 01:58:18 PM PDT 24
Finished Mar 12 01:58:29 PM PDT 24
Peak memory 214428 kb
Host smart-49ee3d26-a7ce-4b5c-a91e-9c808e6357ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120178108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.4120178108
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.801794594
Short name T805
Test name
Test status
Simulation time 231542311 ps
CPU time 1.92 seconds
Started Mar 12 01:58:17 PM PDT 24
Finished Mar 12 01:58:20 PM PDT 24
Peak memory 206960 kb
Host smart-bcc997c3-027e-4481-b548-6a955fadd45d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801794594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.801794594
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.3289108852
Short name T752
Test name
Test status
Simulation time 774802310 ps
CPU time 24.19 seconds
Started Mar 12 01:58:13 PM PDT 24
Finished Mar 12 01:58:38 PM PDT 24
Peak memory 216064 kb
Host smart-26efa50c-2e1c-4b88-8ac2-35e6b88b556f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3289108852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.3289108852
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.2392573108
Short name T297
Test name
Test status
Simulation time 40167419 ps
CPU time 2.72 seconds
Started Mar 12 01:58:15 PM PDT 24
Finished Mar 12 01:58:17 PM PDT 24
Peak memory 214496 kb
Host smart-bfe840a1-ce2f-4096-bf74-dc5d3bb85c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392573108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.2392573108
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.3598488800
Short name T658
Test name
Test status
Simulation time 327170102 ps
CPU time 2.31 seconds
Started Mar 12 01:58:14 PM PDT 24
Finished Mar 12 01:58:17 PM PDT 24
Peak memory 210456 kb
Host smart-2bcc99f4-1183-4a44-afa7-23815ca3a213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598488800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.3598488800
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.3765089366
Short name T655
Test name
Test status
Simulation time 11619923 ps
CPU time 0.74 seconds
Started Mar 12 01:58:25 PM PDT 24
Finished Mar 12 01:58:28 PM PDT 24
Peak memory 206136 kb
Host smart-2a23cf4f-a260-4e92-8a97-1913559221bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765089366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.3765089366
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.1742416094
Short name T413
Test name
Test status
Simulation time 284800920 ps
CPU time 4.54 seconds
Started Mar 12 01:58:28 PM PDT 24
Finished Mar 12 01:58:33 PM PDT 24
Peak memory 215396 kb
Host smart-cdbbeaf4-2f6c-422b-8a66-ae17df47de5e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1742416094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.1742416094
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.1372758888
Short name T39
Test name
Test status
Simulation time 135519384 ps
CPU time 2.52 seconds
Started Mar 12 01:58:24 PM PDT 24
Finished Mar 12 01:58:27 PM PDT 24
Peak memory 209732 kb
Host smart-6a9dc06a-a377-4774-a105-6dc0b1ac0034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372758888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.1372758888
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.4284185623
Short name T796
Test name
Test status
Simulation time 135184481 ps
CPU time 3.05 seconds
Started Mar 12 01:58:29 PM PDT 24
Finished Mar 12 01:58:32 PM PDT 24
Peak memory 209924 kb
Host smart-54338318-1ee4-40f9-93a4-8e5e2a665353
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284185623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.4284185623
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.1285443213
Short name T336
Test name
Test status
Simulation time 1419557259 ps
CPU time 10.09 seconds
Started Mar 12 01:58:21 PM PDT 24
Finished Mar 12 01:58:33 PM PDT 24
Peak memory 209524 kb
Host smart-af077fa4-fd67-4e22-be56-7c36a8e0e9b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1285443213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.1285443213
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.1592845001
Short name T8
Test name
Test status
Simulation time 376268836 ps
CPU time 3.65 seconds
Started Mar 12 01:58:25 PM PDT 24
Finished Mar 12 01:58:30 PM PDT 24
Peak memory 220288 kb
Host smart-50013ffc-b688-46e5-b4a8-c712224649b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592845001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.1592845001
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.1237577049
Short name T629
Test name
Test status
Simulation time 189042948 ps
CPU time 3.57 seconds
Started Mar 12 01:58:26 PM PDT 24
Finished Mar 12 01:58:31 PM PDT 24
Peak memory 207960 kb
Host smart-287ba162-60c0-4493-871f-4d517d415266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237577049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.1237577049
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.255476291
Short name T767
Test name
Test status
Simulation time 76239687 ps
CPU time 1.74 seconds
Started Mar 12 01:58:17 PM PDT 24
Finished Mar 12 01:58:20 PM PDT 24
Peak memory 206856 kb
Host smart-01e224dd-d59c-4a0a-8213-9077a50d7c9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255476291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.255476291
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.2842287047
Short name T840
Test name
Test status
Simulation time 848932347 ps
CPU time 8.53 seconds
Started Mar 12 01:58:16 PM PDT 24
Finished Mar 12 01:58:24 PM PDT 24
Peak memory 208700 kb
Host smart-1e4836a7-59ea-430a-a631-73e1969429d9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2842287047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.2842287047
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.2225377809
Short name T325
Test name
Test status
Simulation time 46964297 ps
CPU time 2.58 seconds
Started Mar 12 01:58:18 PM PDT 24
Finished Mar 12 01:58:22 PM PDT 24
Peak memory 208628 kb
Host smart-f7478a74-cf15-4410-8e82-319eea17656f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2225377809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.2225377809
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.1606302383
Short name T730
Test name
Test status
Simulation time 610954940 ps
CPU time 7.53 seconds
Started Mar 12 01:58:18 PM PDT 24
Finished Mar 12 01:58:28 PM PDT 24
Peak memory 208512 kb
Host smart-4962f2f0-54dd-4247-9732-3d68ba310197
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606302383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.1606302383
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.3712890894
Short name T876
Test name
Test status
Simulation time 30365918 ps
CPU time 2.18 seconds
Started Mar 12 01:58:23 PM PDT 24
Finished Mar 12 01:58:27 PM PDT 24
Peak memory 218212 kb
Host smart-af01cdd7-3e0d-467b-9849-25433dee8df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3712890894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.3712890894
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.3952821497
Short name T528
Test name
Test status
Simulation time 78975355 ps
CPU time 3.47 seconds
Started Mar 12 01:58:17 PM PDT 24
Finished Mar 12 01:58:22 PM PDT 24
Peak memory 208608 kb
Host smart-b8c691cb-f4ba-42ce-9ae4-29e3a559a5e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3952821497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.3952821497
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.1985430231
Short name T308
Test name
Test status
Simulation time 28993069333 ps
CPU time 194.01 seconds
Started Mar 12 01:58:24 PM PDT 24
Finished Mar 12 02:01:40 PM PDT 24
Peak memory 217644 kb
Host smart-bee616ab-47bf-42a4-a4e1-9e52a29a2c8c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1985430231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.1985430231
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.3524088787
Short name T485
Test name
Test status
Simulation time 223533939 ps
CPU time 6.91 seconds
Started Mar 12 01:58:25 PM PDT 24
Finished Mar 12 01:58:34 PM PDT 24
Peak memory 210368 kb
Host smart-306583fa-084e-4ec9-a59a-3f526ce45a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3524088787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.3524088787
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.587104587
Short name T502
Test name
Test status
Simulation time 306455207 ps
CPU time 3.23 seconds
Started Mar 12 01:58:28 PM PDT 24
Finished Mar 12 01:58:31 PM PDT 24
Peak memory 210188 kb
Host smart-322fb222-528f-4b3c-b739-35dae1cf0a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587104587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.587104587
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.926873804
Short name T501
Test name
Test status
Simulation time 15198281 ps
CPU time 0.73 seconds
Started Mar 12 01:58:27 PM PDT 24
Finished Mar 12 01:58:29 PM PDT 24
Peak memory 206112 kb
Host smart-b9539362-f657-44c4-b454-1e6df35c8c11
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926873804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.926873804
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.522693246
Short name T440
Test name
Test status
Simulation time 66407208 ps
CPU time 4.86 seconds
Started Mar 12 01:58:25 PM PDT 24
Finished Mar 12 01:58:32 PM PDT 24
Peak memory 214980 kb
Host smart-9e4dc4f2-d37e-482f-805a-1a9e0d4a74df
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=522693246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.522693246
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.859095323
Short name T675
Test name
Test status
Simulation time 251700330 ps
CPU time 3.15 seconds
Started Mar 12 01:58:27 PM PDT 24
Finished Mar 12 01:58:31 PM PDT 24
Peak memory 217840 kb
Host smart-ad7190ad-bc89-421d-8d52-934a3a732b2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859095323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.859095323
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.771388917
Short name T310
Test name
Test status
Simulation time 4552784957 ps
CPU time 26.42 seconds
Started Mar 12 01:58:27 PM PDT 24
Finished Mar 12 01:58:54 PM PDT 24
Peak memory 209056 kb
Host smart-4bf921c7-aa73-4031-9f55-b05808203333
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771388917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.771388917
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.1091707516
Short name T63
Test name
Test status
Simulation time 124466462 ps
CPU time 5.22 seconds
Started Mar 12 01:58:27 PM PDT 24
Finished Mar 12 01:58:33 PM PDT 24
Peak memory 209312 kb
Host smart-fb635c97-060f-4e0a-8393-65fef7a80979
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091707516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.1091707516
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.2292718143
Short name T43
Test name
Test status
Simulation time 3000105258 ps
CPU time 18.78 seconds
Started Mar 12 01:58:25 PM PDT 24
Finished Mar 12 01:58:45 PM PDT 24
Peak memory 208268 kb
Host smart-5334ef60-1027-45ea-a918-80fdd1a9dbab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292718143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.2292718143
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.497592854
Short name T239
Test name
Test status
Simulation time 561919640 ps
CPU time 4.11 seconds
Started Mar 12 01:58:27 PM PDT 24
Finished Mar 12 01:58:32 PM PDT 24
Peak memory 208576 kb
Host smart-ea1ada65-f159-4d78-a9ff-dd71b1a7ab13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497592854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.497592854
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.1083983570
Short name T454
Test name
Test status
Simulation time 59087247 ps
CPU time 3.26 seconds
Started Mar 12 01:58:22 PM PDT 24
Finished Mar 12 01:58:26 PM PDT 24
Peak memory 206828 kb
Host smart-596c08af-c63c-41c8-8fb5-9498ab1b6b97
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083983570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.1083983570
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.1277792371
Short name T78
Test name
Test status
Simulation time 246417320 ps
CPU time 3.29 seconds
Started Mar 12 01:58:28 PM PDT 24
Finished Mar 12 01:58:32 PM PDT 24
Peak memory 208972 kb
Host smart-61362568-4e8d-4ff5-9f2a-3f911865e0c0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277792371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.1277792371
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.2499614077
Short name T590
Test name
Test status
Simulation time 58006871 ps
CPU time 2.39 seconds
Started Mar 12 01:58:22 PM PDT 24
Finished Mar 12 01:58:25 PM PDT 24
Peak memory 206588 kb
Host smart-2b5006b7-6eac-461a-9f83-b3d8f41ec986
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499614077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.2499614077
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.3417752227
Short name T395
Test name
Test status
Simulation time 2301470221 ps
CPU time 39.74 seconds
Started Mar 12 01:58:28 PM PDT 24
Finished Mar 12 01:59:08 PM PDT 24
Peak memory 218764 kb
Host smart-4f70c9c4-5e1f-4fe7-bfdd-2b812afb1fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417752227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.3417752227
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.2184474040
Short name T608
Test name
Test status
Simulation time 128950110 ps
CPU time 3.15 seconds
Started Mar 12 01:58:27 PM PDT 24
Finished Mar 12 01:58:31 PM PDT 24
Peak memory 208024 kb
Host smart-edc05dac-e677-49e9-b08b-078e8edbd84f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184474040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.2184474040
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.3697680969
Short name T206
Test name
Test status
Simulation time 9707444799 ps
CPU time 127.86 seconds
Started Mar 12 01:58:24 PM PDT 24
Finished Mar 12 02:00:34 PM PDT 24
Peak memory 217580 kb
Host smart-c1de9111-9965-445e-ba7e-416eaea38a38
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697680969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.3697680969
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.2034319448
Short name T680
Test name
Test status
Simulation time 150665702 ps
CPU time 5.83 seconds
Started Mar 12 01:58:28 PM PDT 24
Finished Mar 12 01:58:34 PM PDT 24
Peak memory 222824 kb
Host smart-92346c4d-5245-4f11-862b-a9170ce99b1f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034319448 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.2034319448
Directory /workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.3517974551
Short name T496
Test name
Test status
Simulation time 151610401 ps
CPU time 4.24 seconds
Started Mar 12 01:58:27 PM PDT 24
Finished Mar 12 01:58:32 PM PDT 24
Peak memory 208896 kb
Host smart-6afb01d8-09bd-4eb8-9e6d-7670762c1a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517974551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.3517974551
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.3230661160
Short name T55
Test name
Test status
Simulation time 89631373 ps
CPU time 3.2 seconds
Started Mar 12 01:58:27 PM PDT 24
Finished Mar 12 01:58:31 PM PDT 24
Peak memory 210228 kb
Host smart-5ab3f676-beb1-45cb-801f-4278ef9d29fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3230661160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.3230661160
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.2338146047
Short name T462
Test name
Test status
Simulation time 29411505 ps
CPU time 0.83 seconds
Started Mar 12 01:58:34 PM PDT 24
Finished Mar 12 01:58:34 PM PDT 24
Peak memory 206104 kb
Host smart-f2c16fa3-fa78-403c-8d62-b8e8cb8a75d2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2338146047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.2338146047
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.988297921
Short name T33
Test name
Test status
Simulation time 122753367 ps
CPU time 4.55 seconds
Started Mar 12 01:58:33 PM PDT 24
Finished Mar 12 01:58:38 PM PDT 24
Peak memory 210700 kb
Host smart-46eccf20-75ab-4a4a-9efc-e065562eb1a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988297921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.988297921
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.3288639391
Short name T493
Test name
Test status
Simulation time 126278737 ps
CPU time 1.87 seconds
Started Mar 12 01:58:32 PM PDT 24
Finished Mar 12 01:58:34 PM PDT 24
Peak memory 208544 kb
Host smart-654f7055-229c-47bd-9bd6-886a18e3b454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3288639391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.3288639391
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.229790834
Short name T102
Test name
Test status
Simulation time 456131581 ps
CPU time 5 seconds
Started Mar 12 01:58:31 PM PDT 24
Finished Mar 12 01:58:36 PM PDT 24
Peak memory 219732 kb
Host smart-47fd0076-1500-4182-bb2a-4ceea65c99f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229790834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.229790834
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.952520130
Short name T802
Test name
Test status
Simulation time 155271510 ps
CPU time 3.14 seconds
Started Mar 12 01:58:33 PM PDT 24
Finished Mar 12 01:58:36 PM PDT 24
Peak memory 207672 kb
Host smart-446305e6-6d7d-4b0d-b86a-da63df68f319
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=952520130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.952520130
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.4288902032
Short name T615
Test name
Test status
Simulation time 188611442 ps
CPU time 4.57 seconds
Started Mar 12 01:58:26 PM PDT 24
Finished Mar 12 01:58:32 PM PDT 24
Peak memory 209256 kb
Host smart-00e17e24-ca5d-47f0-b6a3-5ea0f0c7cf01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288902032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.4288902032
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.2274563969
Short name T400
Test name
Test status
Simulation time 180148107 ps
CPU time 2.86 seconds
Started Mar 12 01:58:27 PM PDT 24
Finished Mar 12 01:58:31 PM PDT 24
Peak memory 206880 kb
Host smart-9fbd135d-447f-4108-a072-c6e547dc62fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274563969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.2274563969
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.560072755
Short name T738
Test name
Test status
Simulation time 60448565 ps
CPU time 3.14 seconds
Started Mar 12 01:58:28 PM PDT 24
Finished Mar 12 01:58:31 PM PDT 24
Peak memory 208468 kb
Host smart-44c29ce9-45e3-43a2-9bcd-089746efee91
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560072755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.560072755
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.3247976770
Short name T627
Test name
Test status
Simulation time 63847662 ps
CPU time 3.56 seconds
Started Mar 12 01:58:26 PM PDT 24
Finished Mar 12 01:58:31 PM PDT 24
Peak memory 208512 kb
Host smart-549fa6b1-dcbb-4f86-b8f8-1a225545be1e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247976770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.3247976770
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.959997653
Short name T643
Test name
Test status
Simulation time 513176539 ps
CPU time 7.56 seconds
Started Mar 12 01:58:28 PM PDT 24
Finished Mar 12 01:58:36 PM PDT 24
Peak memory 208536 kb
Host smart-5a6b9198-cd85-4cce-85b1-ec2c015f6f5c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=959997653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.959997653
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.1486280348
Short name T586
Test name
Test status
Simulation time 237210522 ps
CPU time 2.97 seconds
Started Mar 12 01:58:31 PM PDT 24
Finished Mar 12 01:58:34 PM PDT 24
Peak memory 209056 kb
Host smart-a98bf4fe-8d8d-40aa-8441-c6eaef49f2ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486280348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.1486280348
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.3409241056
Short name T584
Test name
Test status
Simulation time 2685567471 ps
CPU time 19.31 seconds
Started Mar 12 01:58:27 PM PDT 24
Finished Mar 12 01:58:47 PM PDT 24
Peak memory 208108 kb
Host smart-51adff12-f4e8-430c-8867-8014c6448e07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3409241056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.3409241056
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.2491987195
Short name T69
Test name
Test status
Simulation time 3913937509 ps
CPU time 31.32 seconds
Started Mar 12 01:58:35 PM PDT 24
Finished Mar 12 01:59:06 PM PDT 24
Peak memory 221928 kb
Host smart-0479e331-3712-423b-aaa0-eecab193d6f7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491987195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.2491987195
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.937822291
Short name T614
Test name
Test status
Simulation time 36641404 ps
CPU time 3.02 seconds
Started Mar 12 01:58:32 PM PDT 24
Finished Mar 12 01:58:35 PM PDT 24
Peak memory 207512 kb
Host smart-f22030c1-932a-40df-8af1-bf64cd677940
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937822291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.937822291
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.531207924
Short name T764
Test name
Test status
Simulation time 111117146 ps
CPU time 2.59 seconds
Started Mar 12 01:58:34 PM PDT 24
Finished Mar 12 01:58:36 PM PDT 24
Peak memory 209828 kb
Host smart-2b58fe8c-c3d6-40a5-b6ee-a6f6daa5244f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=531207924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.531207924
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.3116535630
Short name T499
Test name
Test status
Simulation time 20670050 ps
CPU time 1.02 seconds
Started Mar 12 01:58:32 PM PDT 24
Finished Mar 12 01:58:33 PM PDT 24
Peak memory 206340 kb
Host smart-0eb5e2f4-c633-4cdb-b431-ce730dfc3782
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116535630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.3116535630
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.645940264
Short name T649
Test name
Test status
Simulation time 138183226 ps
CPU time 3.22 seconds
Started Mar 12 01:58:35 PM PDT 24
Finished Mar 12 01:58:38 PM PDT 24
Peak memory 215364 kb
Host smart-e702de8c-f3b3-4e09-96a9-70c222a0beac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=645940264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.645940264
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.1907063106
Short name T104
Test name
Test status
Simulation time 123867390 ps
CPU time 2.72 seconds
Started Mar 12 01:58:35 PM PDT 24
Finished Mar 12 01:58:38 PM PDT 24
Peak memory 209532 kb
Host smart-45364bf5-0950-41a5-a2b8-36ecbb1772e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1907063106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.1907063106
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.860811731
Short name T785
Test name
Test status
Simulation time 161399174 ps
CPU time 4.83 seconds
Started Mar 12 01:58:33 PM PDT 24
Finished Mar 12 01:58:38 PM PDT 24
Peak memory 207220 kb
Host smart-5a3c71af-bcc9-4557-a725-27f13494575f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=860811731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.860811731
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.225932575
Short name T313
Test name
Test status
Simulation time 5548772665 ps
CPU time 62.18 seconds
Started Mar 12 01:58:31 PM PDT 24
Finished Mar 12 01:59:33 PM PDT 24
Peak memory 222812 kb
Host smart-33e67680-1f6b-41b8-8f26-8b5d795ef43d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225932575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.225932575
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.1172987841
Short name T533
Test name
Test status
Simulation time 306222768 ps
CPU time 4.59 seconds
Started Mar 12 01:58:36 PM PDT 24
Finished Mar 12 01:58:40 PM PDT 24
Peak memory 220404 kb
Host smart-85f04d31-764c-4a76-b76c-c179c0c9d6f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172987841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.1172987841
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.2506804380
Short name T224
Test name
Test status
Simulation time 1494131358 ps
CPU time 40.68 seconds
Started Mar 12 01:58:35 PM PDT 24
Finished Mar 12 01:59:16 PM PDT 24
Peak memory 209448 kb
Host smart-61fdc962-0499-491e-ac5e-e7cdf99fe622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506804380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.2506804380
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.774315607
Short name T827
Test name
Test status
Simulation time 111207627 ps
CPU time 2.92 seconds
Started Mar 12 01:58:32 PM PDT 24
Finished Mar 12 01:58:35 PM PDT 24
Peak memory 206784 kb
Host smart-c0d878c8-4a76-4539-82ec-1ec7c647c7d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774315607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.774315607
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.3619181778
Short name T318
Test name
Test status
Simulation time 713143720 ps
CPU time 5.47 seconds
Started Mar 12 01:58:33 PM PDT 24
Finished Mar 12 01:58:39 PM PDT 24
Peak memory 208956 kb
Host smart-7c771a76-9707-4ed6-90b2-a39fb20bdb36
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619181778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.3619181778
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.2686329316
Short name T822
Test name
Test status
Simulation time 1051850664 ps
CPU time 16.78 seconds
Started Mar 12 01:58:33 PM PDT 24
Finished Mar 12 01:58:50 PM PDT 24
Peak memory 208076 kb
Host smart-db5565f4-c9df-4c84-890a-88be7c6055fc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686329316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.2686329316
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.2817037435
Short name T108
Test name
Test status
Simulation time 180894329 ps
CPU time 4.95 seconds
Started Mar 12 01:58:32 PM PDT 24
Finished Mar 12 01:58:37 PM PDT 24
Peak memory 207888 kb
Host smart-a4fae36b-fa16-4b7a-b00d-bc1c545df604
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2817037435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.2817037435
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.968486054
Short name T464
Test name
Test status
Simulation time 2726704892 ps
CPU time 26.16 seconds
Started Mar 12 01:58:34 PM PDT 24
Finished Mar 12 01:59:00 PM PDT 24
Peak memory 209284 kb
Host smart-df027e08-c2fa-4939-9132-ff4c21644891
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=968486054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.968486054
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.1181719072
Short name T500
Test name
Test status
Simulation time 232352172 ps
CPU time 3.3 seconds
Started Mar 12 01:58:34 PM PDT 24
Finished Mar 12 01:58:37 PM PDT 24
Peak memory 206760 kb
Host smart-a9e10771-81de-4b04-9ab2-cd7cdc0442b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181719072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.1181719072
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.1260948053
Short name T732
Test name
Test status
Simulation time 1785695129 ps
CPU time 14.38 seconds
Started Mar 12 01:58:32 PM PDT 24
Finished Mar 12 01:58:46 PM PDT 24
Peak memory 209804 kb
Host smart-3f2b34e6-cc5f-4310-b41d-667b8139d69d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1260948053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.1260948053
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.850264878
Short name T845
Test name
Test status
Simulation time 449417363 ps
CPU time 3.01 seconds
Started Mar 12 01:58:34 PM PDT 24
Finished Mar 12 01:58:37 PM PDT 24
Peak memory 210088 kb
Host smart-f23cc69f-fc40-4433-992f-ccc1a3863abe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850264878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.850264878
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.1492922250
Short name T483
Test name
Test status
Simulation time 23652381 ps
CPU time 0.95 seconds
Started Mar 12 01:58:40 PM PDT 24
Finished Mar 12 01:58:41 PM PDT 24
Peak memory 206336 kb
Host smart-b1628625-9bc2-43df-9fb7-3cb927cf9429
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492922250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.1492922250
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.2566146978
Short name T212
Test name
Test status
Simulation time 211600181 ps
CPU time 4.49 seconds
Started Mar 12 01:58:40 PM PDT 24
Finished Mar 12 01:58:44 PM PDT 24
Peak memory 214536 kb
Host smart-5135d249-0f22-4f50-a9e2-e1b04f9a36bd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2566146978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.2566146978
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.3855743544
Short name T826
Test name
Test status
Simulation time 79007108 ps
CPU time 2.42 seconds
Started Mar 12 01:58:45 PM PDT 24
Finished Mar 12 01:58:47 PM PDT 24
Peak memory 209624 kb
Host smart-b3a8f5aa-c04e-441f-be20-71c370385f76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3855743544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.3855743544
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.2724942486
Short name T136
Test name
Test status
Simulation time 70860940 ps
CPU time 2.47 seconds
Started Mar 12 01:58:44 PM PDT 24
Finished Mar 12 01:58:47 PM PDT 24
Peak memory 209436 kb
Host smart-a123c902-076a-44fa-b567-f070ad204778
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2724942486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.2724942486
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.1083104760
Short name T709
Test name
Test status
Simulation time 325401537 ps
CPU time 4.07 seconds
Started Mar 12 01:58:40 PM PDT 24
Finished Mar 12 01:58:44 PM PDT 24
Peak memory 209660 kb
Host smart-2c214fb1-daba-42ac-ba6b-1b0f11232475
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1083104760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.1083104760
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.3993366007
Short name T684
Test name
Test status
Simulation time 222542219 ps
CPU time 3.65 seconds
Started Mar 12 01:58:39 PM PDT 24
Finished Mar 12 01:58:43 PM PDT 24
Peak memory 220272 kb
Host smart-1b8d5610-06c6-499e-9206-556b4f65a6c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993366007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.3993366007
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.2809020185
Short name T221
Test name
Test status
Simulation time 2020917096 ps
CPU time 13.74 seconds
Started Mar 12 01:58:40 PM PDT 24
Finished Mar 12 01:58:54 PM PDT 24
Peak memory 208728 kb
Host smart-09203aa7-79a8-445c-84b8-2377871c36ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2809020185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.2809020185
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.2908802667
Short name T151
Test name
Test status
Simulation time 46590829 ps
CPU time 2.63 seconds
Started Mar 12 01:58:40 PM PDT 24
Finished Mar 12 01:58:43 PM PDT 24
Peak memory 206848 kb
Host smart-dd2edcbd-1d5e-455f-813b-d8bff13c5acc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2908802667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.2908802667
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.579793880
Short name T556
Test name
Test status
Simulation time 148710863 ps
CPU time 2.47 seconds
Started Mar 12 01:58:41 PM PDT 24
Finished Mar 12 01:58:44 PM PDT 24
Peak memory 206788 kb
Host smart-577abcae-8c8d-44d2-9b0d-8f26b9f3ecbc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=579793880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.579793880
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.1892563007
Short name T511
Test name
Test status
Simulation time 987357006 ps
CPU time 3.52 seconds
Started Mar 12 01:58:39 PM PDT 24
Finished Mar 12 01:58:43 PM PDT 24
Peak memory 208536 kb
Host smart-3b958d3d-55db-4c3a-9a22-1563925de2ec
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1892563007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.1892563007
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.4054800515
Short name T755
Test name
Test status
Simulation time 139891510 ps
CPU time 2.66 seconds
Started Mar 12 01:58:45 PM PDT 24
Finished Mar 12 01:58:48 PM PDT 24
Peak memory 208660 kb
Host smart-ceba36c4-2385-4198-ac21-948ec414c871
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4054800515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.4054800515
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.1584009036
Short name T836
Test name
Test status
Simulation time 653006578 ps
CPU time 13.22 seconds
Started Mar 12 01:58:39 PM PDT 24
Finished Mar 12 01:58:53 PM PDT 24
Peak memory 208228 kb
Host smart-bb68122a-b69a-4e4c-afad-0551829a96b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1584009036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.1584009036
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.193295998
Short name T727
Test name
Test status
Simulation time 235936888 ps
CPU time 2.76 seconds
Started Mar 12 01:58:42 PM PDT 24
Finished Mar 12 01:58:45 PM PDT 24
Peak memory 206816 kb
Host smart-0f39bb64-0fcb-4a1e-8079-fd4cfea34055
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193295998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.193295998
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.3960135038
Short name T618
Test name
Test status
Simulation time 111820392060 ps
CPU time 500.74 seconds
Started Mar 12 01:58:39 PM PDT 24
Finished Mar 12 02:07:00 PM PDT 24
Peak memory 220924 kb
Host smart-da4aa9fb-0406-41fa-8015-4105c94d7f7e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960135038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.3960135038
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.1682932675
Short name T27
Test name
Test status
Simulation time 254533523 ps
CPU time 5.67 seconds
Started Mar 12 01:58:46 PM PDT 24
Finished Mar 12 01:58:51 PM PDT 24
Peak memory 210024 kb
Host smart-aae3616f-741c-4c10-9d1a-a5b5658d6640
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682932675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.1682932675
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.221291513
Short name T249
Test name
Test status
Simulation time 119980951 ps
CPU time 3.05 seconds
Started Mar 12 01:58:42 PM PDT 24
Finished Mar 12 01:58:46 PM PDT 24
Peak memory 209784 kb
Host smart-742dd83e-feac-4ab4-8524-82f095615be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=221291513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.221291513
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.2239360201
Short name T472
Test name
Test status
Simulation time 53088211 ps
CPU time 0.73 seconds
Started Mar 12 01:58:51 PM PDT 24
Finished Mar 12 01:58:52 PM PDT 24
Peak memory 206104 kb
Host smart-4d6dc25c-6ebc-4ed2-bf43-fcb8db9af216
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2239360201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.2239360201
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.1063209493
Short name T681
Test name
Test status
Simulation time 75552748 ps
CPU time 3.54 seconds
Started Mar 12 01:58:38 PM PDT 24
Finished Mar 12 01:58:42 PM PDT 24
Peak memory 218336 kb
Host smart-60b63c0c-53f1-4623-82f0-d7955a836b6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063209493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.1063209493
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.4054251265
Short name T737
Test name
Test status
Simulation time 178668079 ps
CPU time 3.25 seconds
Started Mar 12 01:58:41 PM PDT 24
Finished Mar 12 01:58:45 PM PDT 24
Peak memory 208564 kb
Host smart-0f03c525-1daf-4aed-9215-cb8a372ce612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4054251265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.4054251265
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.2353584770
Short name T201
Test name
Test status
Simulation time 983713028 ps
CPU time 36.06 seconds
Started Mar 12 01:58:52 PM PDT 24
Finished Mar 12 01:59:28 PM PDT 24
Peak memory 216220 kb
Host smart-0006f12d-f01a-494d-b82c-50e20f32fbca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353584770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.2353584770
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.359446191
Short name T265
Test name
Test status
Simulation time 59497409 ps
CPU time 4.16 seconds
Started Mar 12 01:58:41 PM PDT 24
Finished Mar 12 01:58:45 PM PDT 24
Peak memory 214476 kb
Host smart-8e5965ad-b888-4863-b2a7-52d57065deaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359446191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.359446191
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.1062728587
Short name T593
Test name
Test status
Simulation time 363946384 ps
CPU time 8.99 seconds
Started Mar 12 01:58:43 PM PDT 24
Finished Mar 12 01:58:53 PM PDT 24
Peak memory 209212 kb
Host smart-cfaa1ddd-013e-45ff-b029-21702de7428a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062728587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.1062728587
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.3478371938
Short name T293
Test name
Test status
Simulation time 47722477 ps
CPU time 2.7 seconds
Started Mar 12 01:58:41 PM PDT 24
Finished Mar 12 01:58:44 PM PDT 24
Peak memory 208008 kb
Host smart-29501f6e-3899-4260-a11c-643ae10eab42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478371938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.3478371938
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.3905286981
Short name T575
Test name
Test status
Simulation time 506286608 ps
CPU time 5.06 seconds
Started Mar 12 01:58:46 PM PDT 24
Finished Mar 12 01:58:51 PM PDT 24
Peak memory 207444 kb
Host smart-1a5e961a-1f8f-44ed-9c18-34e5b31c87aa
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905286981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.3905286981
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.1176187760
Short name T572
Test name
Test status
Simulation time 980257193 ps
CPU time 14.29 seconds
Started Mar 12 01:58:40 PM PDT 24
Finished Mar 12 01:58:54 PM PDT 24
Peak memory 207968 kb
Host smart-311aaf65-42ab-4f2e-951a-8ad08a69555c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176187760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.1176187760
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.1279308096
Short name T482
Test name
Test status
Simulation time 1418354561 ps
CPU time 44.36 seconds
Started Mar 12 01:58:42 PM PDT 24
Finished Mar 12 01:59:27 PM PDT 24
Peak memory 208508 kb
Host smart-19558b65-67c3-4132-87f5-7e4fcab9f053
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279308096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.1279308096
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.940254407
Short name T4
Test name
Test status
Simulation time 429271554 ps
CPU time 12.96 seconds
Started Mar 12 01:58:51 PM PDT 24
Finished Mar 12 01:59:04 PM PDT 24
Peak memory 208616 kb
Host smart-b88e7ae2-6188-4280-9202-c024ca178e8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940254407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.940254407
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.3708716736
Short name T228
Test name
Test status
Simulation time 1092264800 ps
CPU time 5.93 seconds
Started Mar 12 01:58:41 PM PDT 24
Finished Mar 12 01:58:48 PM PDT 24
Peak memory 207720 kb
Host smart-f1bc222b-38fe-47c1-b66b-ff184f1e6e4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708716736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.3708716736
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.611604880
Short name T207
Test name
Test status
Simulation time 2295129854 ps
CPU time 54.51 seconds
Started Mar 12 01:58:52 PM PDT 24
Finished Mar 12 01:59:47 PM PDT 24
Peak memory 216204 kb
Host smart-81ffecc9-d884-442c-a48a-3436fb03b312
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611604880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.611604880
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.1158763871
Short name T803
Test name
Test status
Simulation time 801550301 ps
CPU time 7.45 seconds
Started Mar 12 01:58:40 PM PDT 24
Finished Mar 12 01:58:48 PM PDT 24
Peak memory 214492 kb
Host smart-c412cd38-804b-4d05-b456-6adb214b5933
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1158763871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.1158763871
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.116597675
Short name T132
Test name
Test status
Simulation time 183185151 ps
CPU time 2.04 seconds
Started Mar 12 01:58:52 PM PDT 24
Finished Mar 12 01:58:54 PM PDT 24
Peak memory 209628 kb
Host smart-89e8c9e1-1c58-430c-a572-7e6e17360fdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116597675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.116597675
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.2335936034
Short name T693
Test name
Test status
Simulation time 16892546 ps
CPU time 0.92 seconds
Started Mar 12 01:55:00 PM PDT 24
Finished Mar 12 01:55:02 PM PDT 24
Peak memory 206316 kb
Host smart-1415db57-090b-410c-a888-a6461a09cc3d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335936034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.2335936034
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.305073572
Short name T436
Test name
Test status
Simulation time 216513811 ps
CPU time 12.14 seconds
Started Mar 12 01:54:53 PM PDT 24
Finished Mar 12 01:55:05 PM PDT 24
Peak memory 222640 kb
Host smart-db8cf6cb-184b-4a5a-a851-fc1183dde4c7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=305073572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.305073572
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.2116426985
Short name T41
Test name
Test status
Simulation time 259256380 ps
CPU time 3.81 seconds
Started Mar 12 01:55:01 PM PDT 24
Finished Mar 12 01:55:05 PM PDT 24
Peak memory 208336 kb
Host smart-d0ab9b2a-7d3a-4272-8b07-e7f3cb0e75ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2116426985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.2116426985
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.888255826
Short name T716
Test name
Test status
Simulation time 344789588 ps
CPU time 3.35 seconds
Started Mar 12 01:55:02 PM PDT 24
Finished Mar 12 01:55:05 PM PDT 24
Peak memory 218700 kb
Host smart-bc40e77b-5a3f-4b01-b070-4063a1d1db32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888255826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.888255826
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.72752716
Short name T768
Test name
Test status
Simulation time 579202170 ps
CPU time 3.49 seconds
Started Mar 12 01:55:01 PM PDT 24
Finished Mar 12 01:55:05 PM PDT 24
Peak memory 221376 kb
Host smart-33b72401-fa96-41ba-967f-2d03dd1f2aac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=72752716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.72752716
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.3482738124
Short name T50
Test name
Test status
Simulation time 133862721 ps
CPU time 3.71 seconds
Started Mar 12 01:55:01 PM PDT 24
Finished Mar 12 01:55:05 PM PDT 24
Peak memory 219992 kb
Host smart-ee4cf123-0bb4-411b-b2c6-f1a57106168d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3482738124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.3482738124
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.48917019
Short name T433
Test name
Test status
Simulation time 1674379877 ps
CPU time 13.56 seconds
Started Mar 12 01:54:51 PM PDT 24
Finished Mar 12 01:55:05 PM PDT 24
Peak memory 207868 kb
Host smart-d5236a83-c4ac-442e-a014-4cff8fa75a77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48917019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.48917019
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sideload.3585264204
Short name T273
Test name
Test status
Simulation time 1368099289 ps
CPU time 4.91 seconds
Started Mar 12 01:54:52 PM PDT 24
Finished Mar 12 01:54:57 PM PDT 24
Peak memory 206900 kb
Host smart-05a6305d-cbfa-41e2-939b-a246b12a2e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585264204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.3585264204
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.2473057928
Short name T243
Test name
Test status
Simulation time 5075192131 ps
CPU time 39.88 seconds
Started Mar 12 01:54:51 PM PDT 24
Finished Mar 12 01:55:31 PM PDT 24
Peak memory 208244 kb
Host smart-fcb86950-a089-4ceb-8362-aaab11251a0e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473057928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.2473057928
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.3424591529
Short name T585
Test name
Test status
Simulation time 102582266 ps
CPU time 2.74 seconds
Started Mar 12 01:54:51 PM PDT 24
Finished Mar 12 01:54:54 PM PDT 24
Peak memory 206688 kb
Host smart-f989fa64-1540-40ee-83f6-8a90ab9eb4fb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424591529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.3424591529
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.2517188674
Short name T560
Test name
Test status
Simulation time 857383002 ps
CPU time 6.29 seconds
Started Mar 12 01:54:53 PM PDT 24
Finished Mar 12 01:54:59 PM PDT 24
Peak memory 207960 kb
Host smart-70e6e298-0ada-4527-a33c-5bb5eaea6a23
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2517188674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.2517188674
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.3813490884
Short name T305
Test name
Test status
Simulation time 66279167 ps
CPU time 2.23 seconds
Started Mar 12 01:55:00 PM PDT 24
Finished Mar 12 01:55:02 PM PDT 24
Peak memory 222660 kb
Host smart-2083f8e3-433e-4f31-8212-aa0ce2f1feaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813490884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.3813490884
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.334806977
Short name T616
Test name
Test status
Simulation time 48269046 ps
CPU time 3.06 seconds
Started Mar 12 01:54:53 PM PDT 24
Finished Mar 12 01:54:56 PM PDT 24
Peak memory 208644 kb
Host smart-9d8e7a4a-3238-49ff-bc2f-0b512df44e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334806977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.334806977
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.1513738736
Short name T247
Test name
Test status
Simulation time 1506642442 ps
CPU time 16.81 seconds
Started Mar 12 01:54:59 PM PDT 24
Finished Mar 12 01:55:16 PM PDT 24
Peak memory 222688 kb
Host smart-e6b90cbc-437f-4b37-b18d-6ce33d49a31f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513738736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.1513738736
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.3968771601
Short name T232
Test name
Test status
Simulation time 1998900780 ps
CPU time 42.78 seconds
Started Mar 12 01:55:00 PM PDT 24
Finished Mar 12 01:55:43 PM PDT 24
Peak memory 218516 kb
Host smart-013e7c28-c5c3-4790-8950-c05b3a337ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3968771601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.3968771601
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.892126433
Short name T60
Test name
Test status
Simulation time 287976895 ps
CPU time 3.34 seconds
Started Mar 12 01:54:59 PM PDT 24
Finished Mar 12 01:55:03 PM PDT 24
Peak memory 209852 kb
Host smart-a0800ad9-b377-4f42-b855-a813992f0791
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=892126433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.892126433
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.1294065863
Short name T532
Test name
Test status
Simulation time 154373610 ps
CPU time 0.75 seconds
Started Mar 12 01:58:51 PM PDT 24
Finished Mar 12 01:58:52 PM PDT 24
Peak memory 206060 kb
Host smart-b80f39c9-648c-4196-bed9-e2d613f49135
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294065863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.1294065863
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.1494061992
Short name T885
Test name
Test status
Simulation time 540999403 ps
CPU time 5.36 seconds
Started Mar 12 01:58:51 PM PDT 24
Finished Mar 12 01:58:56 PM PDT 24
Peak memory 219220 kb
Host smart-3d6553ba-b7a1-4638-a6b2-83035f05d12e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494061992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.1494061992
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.2606360087
Short name T891
Test name
Test status
Simulation time 146824001 ps
CPU time 2.64 seconds
Started Mar 12 01:58:50 PM PDT 24
Finished Mar 12 01:58:53 PM PDT 24
Peak memory 218644 kb
Host smart-9d46c6b3-ffb3-4065-87f1-93ed69f08b35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606360087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.2606360087
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.1662372371
Short name T417
Test name
Test status
Simulation time 465345410 ps
CPU time 10.25 seconds
Started Mar 12 01:58:50 PM PDT 24
Finished Mar 12 01:59:01 PM PDT 24
Peak memory 214544 kb
Host smart-6988a31f-02cc-4d72-9b59-9f51bd63b9c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1662372371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.1662372371
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.672457406
Short name T227
Test name
Test status
Simulation time 53218778 ps
CPU time 3.74 seconds
Started Mar 12 01:58:52 PM PDT 24
Finished Mar 12 01:58:56 PM PDT 24
Peak memory 214416 kb
Host smart-c6245155-cbcf-46c4-89bc-fb48a149d23c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=672457406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.672457406
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.1035153835
Short name T258
Test name
Test status
Simulation time 3274469936 ps
CPU time 46.2 seconds
Started Mar 12 01:58:51 PM PDT 24
Finished Mar 12 01:59:38 PM PDT 24
Peak memory 222612 kb
Host smart-31acd901-13d4-413d-84ce-314ffd6a6066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035153835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.1035153835
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.1053095974
Short name T5
Test name
Test status
Simulation time 1025484958 ps
CPU time 9.97 seconds
Started Mar 12 01:58:52 PM PDT 24
Finished Mar 12 01:59:02 PM PDT 24
Peak memory 216048 kb
Host smart-7316e031-e862-4430-90e2-f2d7ff0e3c1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053095974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.1053095974
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.3789895410
Short name T591
Test name
Test status
Simulation time 96017963 ps
CPU time 2.68 seconds
Started Mar 12 01:58:51 PM PDT 24
Finished Mar 12 01:58:54 PM PDT 24
Peak memory 206752 kb
Host smart-83f1f783-18a0-4d30-b652-89f2479fe607
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3789895410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.3789895410
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.547858780
Short name T757
Test name
Test status
Simulation time 598237376 ps
CPU time 4.22 seconds
Started Mar 12 01:58:52 PM PDT 24
Finished Mar 12 01:58:57 PM PDT 24
Peak memory 208584 kb
Host smart-12cbbbc3-0798-4c19-8cca-d6db3ff64ae2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547858780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.547858780
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.4019236999
Short name T424
Test name
Test status
Simulation time 12409255867 ps
CPU time 61.95 seconds
Started Mar 12 01:58:52 PM PDT 24
Finished Mar 12 01:59:54 PM PDT 24
Peak memory 209208 kb
Host smart-c6c32a8c-f5c6-418b-81e2-55dd53acfe62
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019236999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.4019236999
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.4252456044
Short name T348
Test name
Test status
Simulation time 3034241491 ps
CPU time 44.62 seconds
Started Mar 12 01:58:52 PM PDT 24
Finished Mar 12 01:59:37 PM PDT 24
Peak memory 207880 kb
Host smart-9758143f-3f59-4d68-9235-e8c988d99d76
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252456044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.4252456044
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.203939782
Short name T303
Test name
Test status
Simulation time 809356584 ps
CPU time 5.58 seconds
Started Mar 12 01:58:49 PM PDT 24
Finished Mar 12 01:58:55 PM PDT 24
Peak memory 218396 kb
Host smart-4205bc0b-1da3-45bd-a73a-14ee87b27c4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203939782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.203939782
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.113493081
Short name T142
Test name
Test status
Simulation time 318390275 ps
CPU time 3.67 seconds
Started Mar 12 01:58:52 PM PDT 24
Finished Mar 12 01:58:56 PM PDT 24
Peak memory 208592 kb
Host smart-23521ba7-5a1b-4cf8-b93b-e293e9921370
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113493081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.113493081
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.2365510246
Short name T199
Test name
Test status
Simulation time 33743229 ps
CPU time 0.75 seconds
Started Mar 12 01:58:51 PM PDT 24
Finished Mar 12 01:58:52 PM PDT 24
Peak memory 206156 kb
Host smart-9584ee89-8729-43cc-b289-350093e4ad3d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2365510246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.2365510246
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.3108150002
Short name T342
Test name
Test status
Simulation time 163433712 ps
CPU time 4.4 seconds
Started Mar 12 01:58:51 PM PDT 24
Finished Mar 12 01:58:56 PM PDT 24
Peak memory 208244 kb
Host smart-6b088d90-39f1-439e-be7f-5ddee8b51991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108150002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.3108150002
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.29355287
Short name T486
Test name
Test status
Simulation time 44169340 ps
CPU time 0.77 seconds
Started Mar 12 01:59:03 PM PDT 24
Finished Mar 12 01:59:04 PM PDT 24
Peak memory 206176 kb
Host smart-6875a71b-c1a8-4396-898c-244387f4705f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29355287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.29355287
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.4243025327
Short name T734
Test name
Test status
Simulation time 290657727 ps
CPU time 3.81 seconds
Started Mar 12 01:59:02 PM PDT 24
Finished Mar 12 01:59:06 PM PDT 24
Peak memory 208976 kb
Host smart-40dc1180-826c-42e5-8b10-bc8a0f5f74c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243025327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.4243025327
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.2728281379
Short name T824
Test name
Test status
Simulation time 173544179 ps
CPU time 2.38 seconds
Started Mar 12 01:59:02 PM PDT 24
Finished Mar 12 01:59:05 PM PDT 24
Peak memory 209372 kb
Host smart-8b485b08-1a3b-4376-bfa4-c3581231d076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728281379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.2728281379
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.1984057212
Short name T282
Test name
Test status
Simulation time 521403761 ps
CPU time 10.92 seconds
Started Mar 12 01:59:02 PM PDT 24
Finished Mar 12 01:59:13 PM PDT 24
Peak memory 210536 kb
Host smart-f3748be3-9bd9-4309-8ea5-04c7132336af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1984057212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.1984057212
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.3496889249
Short name T7
Test name
Test status
Simulation time 672722125 ps
CPU time 5.28 seconds
Started Mar 12 01:59:00 PM PDT 24
Finished Mar 12 01:59:05 PM PDT 24
Peak memory 220316 kb
Host smart-a315c5a6-2414-4bf3-9c3a-5ff3e04e719c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3496889249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.3496889249
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.1845619016
Short name T478
Test name
Test status
Simulation time 48552654 ps
CPU time 3.5 seconds
Started Mar 12 01:59:03 PM PDT 24
Finished Mar 12 01:59:07 PM PDT 24
Peak memory 207868 kb
Host smart-62be7564-495e-4044-875e-c4c16cbd64d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845619016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.1845619016
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.3000230222
Short name T887
Test name
Test status
Simulation time 292330600 ps
CPU time 3.4 seconds
Started Mar 12 01:59:00 PM PDT 24
Finished Mar 12 01:59:04 PM PDT 24
Peak memory 208672 kb
Host smart-0db28687-4594-41a8-a69d-5f0f481a4524
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000230222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.3000230222
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.1518110661
Short name T153
Test name
Test status
Simulation time 462165947 ps
CPU time 5.4 seconds
Started Mar 12 01:58:59 PM PDT 24
Finished Mar 12 01:59:05 PM PDT 24
Peak memory 206900 kb
Host smart-177a8019-a140-4892-a913-fa4e2406d8c8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518110661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.1518110661
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.3815034224
Short name T241
Test name
Test status
Simulation time 1316538590 ps
CPU time 7.89 seconds
Started Mar 12 01:59:03 PM PDT 24
Finished Mar 12 01:59:11 PM PDT 24
Peak memory 207796 kb
Host smart-171ee497-6dd8-48f3-8b6a-bdfb245c2410
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815034224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.3815034224
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.970021740
Short name T536
Test name
Test status
Simulation time 172539969 ps
CPU time 2.92 seconds
Started Mar 12 01:59:00 PM PDT 24
Finished Mar 12 01:59:03 PM PDT 24
Peak memory 209016 kb
Host smart-eef97495-9c60-4a8e-938d-90c08b60509b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=970021740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.970021740
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.4072084512
Short name T321
Test name
Test status
Simulation time 392732011 ps
CPU time 4.7 seconds
Started Mar 12 01:59:00 PM PDT 24
Finished Mar 12 01:59:05 PM PDT 24
Peak memory 209748 kb
Host smart-945ad4f2-14c5-4763-898d-68da3abee765
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072084512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.4072084512
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.1090791099
Short name T568
Test name
Test status
Simulation time 375785478 ps
CPU time 2.06 seconds
Started Mar 12 01:58:52 PM PDT 24
Finished Mar 12 01:58:54 PM PDT 24
Peak memory 208476 kb
Host smart-2f201a40-95b8-4ad2-90f2-9373f72ddab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090791099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.1090791099
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.2651004923
Short name T238
Test name
Test status
Simulation time 81524842 ps
CPU time 3.92 seconds
Started Mar 12 01:59:00 PM PDT 24
Finished Mar 12 01:59:05 PM PDT 24
Peak memory 209308 kb
Host smart-55a3e4f0-42c1-4bc1-bab7-df90b8bcb4b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651004923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.2651004923
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.2950977454
Short name T735
Test name
Test status
Simulation time 65905092 ps
CPU time 2.85 seconds
Started Mar 12 01:59:01 PM PDT 24
Finished Mar 12 01:59:04 PM PDT 24
Peak memory 210000 kb
Host smart-e5cec2a2-5f54-48eb-b610-10048651a44d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950977454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.2950977454
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.1409466644
Short name T505
Test name
Test status
Simulation time 10551489 ps
CPU time 0.75 seconds
Started Mar 12 01:59:01 PM PDT 24
Finished Mar 12 01:59:02 PM PDT 24
Peak memory 206116 kb
Host smart-afe8a258-4f68-4f85-a41d-d66839019b8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409466644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.1409466644
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.362259775
Short name T266
Test name
Test status
Simulation time 52878765 ps
CPU time 3.99 seconds
Started Mar 12 01:59:02 PM PDT 24
Finished Mar 12 01:59:06 PM PDT 24
Peak memory 214448 kb
Host smart-2ec1538a-718a-47ea-82da-3fc8a9cbcbab
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=362259775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.362259775
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.857435953
Short name T31
Test name
Test status
Simulation time 517953165 ps
CPU time 2.67 seconds
Started Mar 12 01:59:00 PM PDT 24
Finished Mar 12 01:59:03 PM PDT 24
Peak memory 208052 kb
Host smart-c74ad768-58c7-4ced-9316-f0c9bbe8380c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857435953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.857435953
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.359913001
Short name T213
Test name
Test status
Simulation time 687992888 ps
CPU time 4.29 seconds
Started Mar 12 01:59:02 PM PDT 24
Finished Mar 12 01:59:07 PM PDT 24
Peak memory 207740 kb
Host smart-90571b7c-8229-4e4a-817c-1e135c46405b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359913001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.359913001
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.410462779
Short name T320
Test name
Test status
Simulation time 614592599 ps
CPU time 11.78 seconds
Started Mar 12 01:59:00 PM PDT 24
Finished Mar 12 01:59:12 PM PDT 24
Peak memory 209780 kb
Host smart-5875d479-acc9-44af-8486-2adc668917fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=410462779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.410462779
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.3856357635
Short name T357
Test name
Test status
Simulation time 300222792 ps
CPU time 4.08 seconds
Started Mar 12 01:59:02 PM PDT 24
Finished Mar 12 01:59:06 PM PDT 24
Peak memory 214344 kb
Host smart-eb3ae800-4c1d-4d8b-920f-20ab7ad91cd0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856357635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.3856357635
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.661086133
Short name T469
Test name
Test status
Simulation time 123482296 ps
CPU time 3.86 seconds
Started Mar 12 01:59:03 PM PDT 24
Finished Mar 12 01:59:07 PM PDT 24
Peak memory 214432 kb
Host smart-b353c9dd-ea87-4c99-9c76-a73d35bdee0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=661086133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.661086133
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.2074146400
Short name T689
Test name
Test status
Simulation time 1144065856 ps
CPU time 12.44 seconds
Started Mar 12 01:58:58 PM PDT 24
Finished Mar 12 01:59:11 PM PDT 24
Peak memory 209016 kb
Host smart-dbec4790-b8c5-429f-8f82-cc2c7df22175
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074146400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.2074146400
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.1897486758
Short name T402
Test name
Test status
Simulation time 127831429 ps
CPU time 2.79 seconds
Started Mar 12 01:59:00 PM PDT 24
Finished Mar 12 01:59:03 PM PDT 24
Peak memory 206872 kb
Host smart-4863efa2-2570-47e0-9314-1f8557a6464e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1897486758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.1897486758
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.3134300930
Short name T626
Test name
Test status
Simulation time 209125785 ps
CPU time 4.02 seconds
Started Mar 12 01:59:01 PM PDT 24
Finished Mar 12 01:59:06 PM PDT 24
Peak memory 207560 kb
Host smart-7a511c74-8857-4ac9-9976-b8585b383cd8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134300930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.3134300930
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.3182343754
Short name T878
Test name
Test status
Simulation time 385529226 ps
CPU time 5.54 seconds
Started Mar 12 01:59:00 PM PDT 24
Finished Mar 12 01:59:06 PM PDT 24
Peak memory 206876 kb
Host smart-c5bd52fe-bdbf-4910-bc39-050a96289bc0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182343754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.3182343754
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.268728947
Short name T508
Test name
Test status
Simulation time 59045759 ps
CPU time 3.36 seconds
Started Mar 12 01:59:03 PM PDT 24
Finished Mar 12 01:59:07 PM PDT 24
Peak memory 208788 kb
Host smart-6aa8389d-15d5-457e-8cbc-6e57f6067256
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268728947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.268728947
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.2799732838
Short name T392
Test name
Test status
Simulation time 105151800 ps
CPU time 3.87 seconds
Started Mar 12 01:59:03 PM PDT 24
Finished Mar 12 01:59:07 PM PDT 24
Peak memory 208844 kb
Host smart-3bc8f427-ab1e-44d0-9d07-efcb76b409ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2799732838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.2799732838
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.4084307545
Short name T468
Test name
Test status
Simulation time 52651783 ps
CPU time 3.05 seconds
Started Mar 12 01:59:00 PM PDT 24
Finished Mar 12 01:59:03 PM PDT 24
Peak memory 206636 kb
Host smart-f28eea9d-fd26-47bd-ab17-17fec67334d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084307545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.4084307545
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.318874946
Short name T72
Test name
Test status
Simulation time 5206636703 ps
CPU time 28.06 seconds
Started Mar 12 01:59:01 PM PDT 24
Finished Mar 12 01:59:30 PM PDT 24
Peak memory 215348 kb
Host smart-e575c718-75de-4ed6-98e6-b777a480b4c1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318874946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.318874946
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_stress_all_with_rand_reset.1200919234
Short name T809
Test name
Test status
Simulation time 153344337 ps
CPU time 11.92 seconds
Started Mar 12 01:59:02 PM PDT 24
Finished Mar 12 01:59:15 PM PDT 24
Peak memory 222792 kb
Host smart-0308e75c-dfe9-4ca4-925b-1f87fbf4cd9c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200919234 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all_with_rand_reset.1200919234
Directory /workspace/42.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.3556396961
Short name T352
Test name
Test status
Simulation time 51848825 ps
CPU time 3.69 seconds
Started Mar 12 01:59:01 PM PDT 24
Finished Mar 12 01:59:05 PM PDT 24
Peak memory 210096 kb
Host smart-9ea7b189-568e-4426-8dc3-415ae18b5fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556396961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.3556396961
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.1206658993
Short name T648
Test name
Test status
Simulation time 380472474 ps
CPU time 3.02 seconds
Started Mar 12 01:59:01 PM PDT 24
Finished Mar 12 01:59:04 PM PDT 24
Peak memory 210268 kb
Host smart-12caed0a-9b81-4d5b-887c-c843b65c37d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206658993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.1206658993
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.3000409221
Short name T889
Test name
Test status
Simulation time 47342793 ps
CPU time 0.83 seconds
Started Mar 12 01:59:09 PM PDT 24
Finished Mar 12 01:59:10 PM PDT 24
Peak memory 206196 kb
Host smart-690e8b3c-8a95-43f9-9244-b176e7e20c2c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3000409221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.3000409221
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.354313667
Short name T412
Test name
Test status
Simulation time 269158358 ps
CPU time 3.73 seconds
Started Mar 12 01:59:00 PM PDT 24
Finished Mar 12 01:59:03 PM PDT 24
Peak memory 214436 kb
Host smart-2e4ae0a1-fc1f-4863-8fb0-38f784b34aa9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=354313667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.354313667
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.2069378911
Short name T10
Test name
Test status
Simulation time 2233895417 ps
CPU time 15.72 seconds
Started Mar 12 01:59:00 PM PDT 24
Finished Mar 12 01:59:16 PM PDT 24
Peak memory 217032 kb
Host smart-8beddbae-ea75-4292-bc76-8aa478e25865
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069378911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.2069378911
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.2698072519
Short name T605
Test name
Test status
Simulation time 63151271 ps
CPU time 1.69 seconds
Started Mar 12 01:59:03 PM PDT 24
Finished Mar 12 01:59:05 PM PDT 24
Peak memory 209212 kb
Host smart-e020407e-f930-4273-ac48-9202d5ed7ec8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2698072519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.2698072519
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.715323127
Short name T100
Test name
Test status
Simulation time 856940793 ps
CPU time 5.23 seconds
Started Mar 12 01:59:01 PM PDT 24
Finished Mar 12 01:59:07 PM PDT 24
Peak memory 214600 kb
Host smart-fa67c966-f83b-4538-8853-b58d64a7f016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=715323127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.715323127
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.591757457
Short name T89
Test name
Test status
Simulation time 180500896 ps
CPU time 6.47 seconds
Started Mar 12 01:59:02 PM PDT 24
Finished Mar 12 01:59:09 PM PDT 24
Peak memory 222608 kb
Host smart-fc16f220-04e1-4843-9fb9-40e224da8873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=591757457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.591757457
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.2797935052
Short name T471
Test name
Test status
Simulation time 284344937 ps
CPU time 1.59 seconds
Started Mar 12 01:59:02 PM PDT 24
Finished Mar 12 01:59:04 PM PDT 24
Peak memory 206308 kb
Host smart-c17a10c1-d638-4cb3-8868-148b697188ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2797935052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.2797935052
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.2055569072
Short name T516
Test name
Test status
Simulation time 49646398 ps
CPU time 3.47 seconds
Started Mar 12 01:59:00 PM PDT 24
Finished Mar 12 01:59:04 PM PDT 24
Peak memory 207628 kb
Host smart-d8da6c94-f7d4-45fe-b260-156f6ef7c17c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055569072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.2055569072
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.932299727
Short name T871
Test name
Test status
Simulation time 131909191 ps
CPU time 2.56 seconds
Started Mar 12 01:59:00 PM PDT 24
Finished Mar 12 01:59:03 PM PDT 24
Peak memory 207308 kb
Host smart-cbeff58d-7883-4705-8086-931eb9e1a2e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=932299727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.932299727
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.2329340989
Short name T211
Test name
Test status
Simulation time 112176496 ps
CPU time 2.37 seconds
Started Mar 12 01:59:03 PM PDT 24
Finished Mar 12 01:59:05 PM PDT 24
Peak memory 206824 kb
Host smart-f215e3a8-d9fe-4f91-9bba-4e6e5e7d118a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2329340989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.2329340989
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.2848419068
Short name T461
Test name
Test status
Simulation time 118605630 ps
CPU time 2.26 seconds
Started Mar 12 01:58:59 PM PDT 24
Finished Mar 12 01:59:02 PM PDT 24
Peak memory 206784 kb
Host smart-cf601b37-c29a-496d-a0e9-71547c473df0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848419068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.2848419068
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.1832295208
Short name T691
Test name
Test status
Simulation time 3365204607 ps
CPU time 58.14 seconds
Started Mar 12 01:59:03 PM PDT 24
Finished Mar 12 02:00:01 PM PDT 24
Peak memory 208336 kb
Host smart-71d4f273-28df-4ac3-ac9d-5cab91f253a0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832295208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.1832295208
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.790102990
Short name T490
Test name
Test status
Simulation time 265344205 ps
CPU time 3.54 seconds
Started Mar 12 01:59:13 PM PDT 24
Finished Mar 12 01:59:17 PM PDT 24
Peak memory 218576 kb
Host smart-0b260e77-eabf-4051-8195-8a6886af2cfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790102990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.790102990
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.2933414616
Short name T606
Test name
Test status
Simulation time 1169539344 ps
CPU time 3.55 seconds
Started Mar 12 01:59:00 PM PDT 24
Finished Mar 12 01:59:04 PM PDT 24
Peak memory 208424 kb
Host smart-8864691c-d1c6-4e09-bd9b-dcfb796e943d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933414616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.2933414616
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.3636975202
Short name T68
Test name
Test status
Simulation time 1433380738 ps
CPU time 20.17 seconds
Started Mar 12 01:59:14 PM PDT 24
Finished Mar 12 01:59:35 PM PDT 24
Peak memory 216740 kb
Host smart-a34a2ac8-2759-4e98-a40f-b77e4a6e8871
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636975202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.3636975202
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_stress_all_with_rand_reset.4052697690
Short name T130
Test name
Test status
Simulation time 1845228142 ps
CPU time 13.1 seconds
Started Mar 12 01:59:10 PM PDT 24
Finished Mar 12 01:59:24 PM PDT 24
Peak memory 222840 kb
Host smart-e97f91e8-26a4-407b-a277-569b10e57913
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052697690 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all_with_rand_reset.4052697690
Directory /workspace/43.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.4093007258
Short name T697
Test name
Test status
Simulation time 346991824 ps
CPU time 10.51 seconds
Started Mar 12 01:58:59 PM PDT 24
Finished Mar 12 01:59:10 PM PDT 24
Peak memory 208496 kb
Host smart-8c4328be-cbe6-4837-afab-84191d5bb5d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4093007258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.4093007258
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.3594780351
Short name T771
Test name
Test status
Simulation time 67261962 ps
CPU time 2.11 seconds
Started Mar 12 01:59:09 PM PDT 24
Finished Mar 12 01:59:12 PM PDT 24
Peak memory 210012 kb
Host smart-fdd01990-de0d-4e07-b59d-d504a115e211
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594780351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.3594780351
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.2123062366
Short name T84
Test name
Test status
Simulation time 14503964 ps
CPU time 0.91 seconds
Started Mar 12 01:59:10 PM PDT 24
Finished Mar 12 01:59:11 PM PDT 24
Peak memory 206308 kb
Host smart-07b804de-8dc0-4f83-ad0e-da8ba2f5cbf9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123062366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.2123062366
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.3445267426
Short name T155
Test name
Test status
Simulation time 33468435 ps
CPU time 2.6 seconds
Started Mar 12 01:59:15 PM PDT 24
Finished Mar 12 01:59:18 PM PDT 24
Peak memory 214548 kb
Host smart-481f8b78-6381-4aca-8481-d5e6eff4730a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3445267426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.3445267426
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.2453001590
Short name T849
Test name
Test status
Simulation time 666389077 ps
CPU time 13.35 seconds
Started Mar 12 01:59:11 PM PDT 24
Finished Mar 12 01:59:24 PM PDT 24
Peak memory 210324 kb
Host smart-972a5d91-4ed7-4726-8fd2-cf4a1b012526
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2453001590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.2453001590
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.4279112293
Short name T197
Test name
Test status
Simulation time 1192868181 ps
CPU time 24.41 seconds
Started Mar 12 01:59:10 PM PDT 24
Finished Mar 12 01:59:36 PM PDT 24
Peak memory 214460 kb
Host smart-f439b3a4-803c-49f7-8cba-e4be083b426d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4279112293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.4279112293
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.3045168608
Short name T372
Test name
Test status
Simulation time 1185482359 ps
CPU time 7.01 seconds
Started Mar 12 01:59:11 PM PDT 24
Finished Mar 12 01:59:18 PM PDT 24
Peak memory 214528 kb
Host smart-1830ccd7-9c30-46b3-aa7d-ab68236c403d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3045168608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.3045168608
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.1194533092
Short name T52
Test name
Test status
Simulation time 77562667 ps
CPU time 3.67 seconds
Started Mar 12 01:59:10 PM PDT 24
Finished Mar 12 01:59:14 PM PDT 24
Peak memory 209768 kb
Host smart-e618be60-c15a-4a97-996a-5483cdbc2bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1194533092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.1194533092
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.539513528
Short name T109
Test name
Test status
Simulation time 974497408 ps
CPU time 13.42 seconds
Started Mar 12 01:59:11 PM PDT 24
Finished Mar 12 01:59:25 PM PDT 24
Peak memory 209556 kb
Host smart-d756c782-8ec9-4e3c-885b-a9f02e56067c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=539513528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.539513528
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.1702463364
Short name T851
Test name
Test status
Simulation time 589620441 ps
CPU time 7.35 seconds
Started Mar 12 01:59:09 PM PDT 24
Finished Mar 12 01:59:17 PM PDT 24
Peak memory 207920 kb
Host smart-437b5c0c-2024-4308-a747-183ac4b8c237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702463364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.1702463364
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.1949603069
Short name T148
Test name
Test status
Simulation time 3517830599 ps
CPU time 25.97 seconds
Started Mar 12 01:59:09 PM PDT 24
Finished Mar 12 01:59:36 PM PDT 24
Peak memory 208496 kb
Host smart-6190a747-41fb-4a93-b04d-adffa091c4f6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949603069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.1949603069
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.2473301626
Short name T487
Test name
Test status
Simulation time 836229169 ps
CPU time 8.9 seconds
Started Mar 12 01:59:08 PM PDT 24
Finished Mar 12 01:59:18 PM PDT 24
Peak memory 208160 kb
Host smart-79ded4c5-1d31-4250-839b-171b09d71c5d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2473301626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.2473301626
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.2218620075
Short name T473
Test name
Test status
Simulation time 82345867 ps
CPU time 3.26 seconds
Started Mar 12 01:59:07 PM PDT 24
Finished Mar 12 01:59:10 PM PDT 24
Peak memory 208192 kb
Host smart-c49366df-098a-428f-804a-48c13caaab60
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218620075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.2218620075
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.3243854526
Short name T470
Test name
Test status
Simulation time 426863653 ps
CPU time 3.35 seconds
Started Mar 12 01:59:09 PM PDT 24
Finished Mar 12 01:59:13 PM PDT 24
Peak memory 207944 kb
Host smart-31169a4e-713c-423c-a3db-de34b10adbbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243854526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.3243854526
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.2665228204
Short name T660
Test name
Test status
Simulation time 2925672248 ps
CPU time 16.49 seconds
Started Mar 12 01:59:08 PM PDT 24
Finished Mar 12 01:59:26 PM PDT 24
Peak memory 208644 kb
Host smart-f76d3466-1dfc-4f60-bc40-57f9ac30cde5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665228204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.2665228204
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.1612773718
Short name T255
Test name
Test status
Simulation time 6334461271 ps
CPU time 70.4 seconds
Started Mar 12 01:59:09 PM PDT 24
Finished Mar 12 02:00:20 PM PDT 24
Peak memory 217764 kb
Host smart-4b933471-db97-441b-ac32-53446f7b7786
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1612773718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.1612773718
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.3982665878
Short name T338
Test name
Test status
Simulation time 399899617 ps
CPU time 4.24 seconds
Started Mar 12 01:59:10 PM PDT 24
Finished Mar 12 01:59:15 PM PDT 24
Peak memory 209984 kb
Host smart-fd086b36-f7a8-447d-8507-2c5881085af8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982665878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.3982665878
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.3795286374
Short name T190
Test name
Test status
Simulation time 198712683 ps
CPU time 2.93 seconds
Started Mar 12 01:59:07 PM PDT 24
Finished Mar 12 01:59:10 PM PDT 24
Peak memory 210116 kb
Host smart-1e4da484-2a2c-456e-b711-ee8b5fce545a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795286374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.3795286374
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.3424373141
Short name T687
Test name
Test status
Simulation time 9519886 ps
CPU time 0.68 seconds
Started Mar 12 01:59:10 PM PDT 24
Finished Mar 12 01:59:11 PM PDT 24
Peak memory 206144 kb
Host smart-69dd4a15-228c-4dc1-bed9-3b41db2ce0c0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424373141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.3424373141
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.3911197779
Short name T379
Test name
Test status
Simulation time 493764895 ps
CPU time 9.1 seconds
Started Mar 12 01:59:11 PM PDT 24
Finished Mar 12 01:59:20 PM PDT 24
Peak memory 215432 kb
Host smart-b7435f6b-0a62-4fcd-bb00-39b34207e370
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3911197779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.3911197779
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.3570256429
Short name T828
Test name
Test status
Simulation time 255506248 ps
CPU time 3.3 seconds
Started Mar 12 01:59:11 PM PDT 24
Finished Mar 12 01:59:15 PM PDT 24
Peak memory 209804 kb
Host smart-91fc2644-4398-4eec-b948-7555981cbe98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570256429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.3570256429
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.2189929825
Short name T765
Test name
Test status
Simulation time 689689666 ps
CPU time 4.55 seconds
Started Mar 12 01:59:10 PM PDT 24
Finished Mar 12 01:59:15 PM PDT 24
Peak memory 209880 kb
Host smart-1e5911e4-ea31-41ab-bab6-0897aec9d234
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189929825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.2189929825
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.880740870
Short name T92
Test name
Test status
Simulation time 241242569 ps
CPU time 5.48 seconds
Started Mar 12 01:59:16 PM PDT 24
Finished Mar 12 01:59:21 PM PDT 24
Peak memory 214588 kb
Host smart-a503f9c5-b6e8-416f-9c4a-d7a7aca21aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880740870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.880740870
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.389808871
Short name T632
Test name
Test status
Simulation time 218240309 ps
CPU time 3.32 seconds
Started Mar 12 01:59:08 PM PDT 24
Finished Mar 12 01:59:12 PM PDT 24
Peak memory 222688 kb
Host smart-8a914b5d-533d-46e5-8dc0-d65353c3a771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=389808871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.389808871
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.495046094
Short name T393
Test name
Test status
Simulation time 264030212 ps
CPU time 4.95 seconds
Started Mar 12 01:59:11 PM PDT 24
Finished Mar 12 01:59:16 PM PDT 24
Peak memory 209976 kb
Host smart-0492756e-401e-4fa7-84cb-b72f8348b08e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495046094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.495046094
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.3433719330
Short name T880
Test name
Test status
Simulation time 220762114 ps
CPU time 3.13 seconds
Started Mar 12 01:59:08 PM PDT 24
Finished Mar 12 01:59:12 PM PDT 24
Peak memory 206660 kb
Host smart-c54303b4-a4d0-4720-8a59-a7604e705510
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3433719330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.3433719330
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.2853032331
Short name T872
Test name
Test status
Simulation time 409138437 ps
CPU time 2.79 seconds
Started Mar 12 01:59:09 PM PDT 24
Finished Mar 12 01:59:13 PM PDT 24
Peak memory 208468 kb
Host smart-ee1a0e7d-7450-4f56-b4c2-5d57347dea0a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853032331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.2853032331
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.1610823108
Short name T652
Test name
Test status
Simulation time 832704558 ps
CPU time 9.09 seconds
Started Mar 12 01:59:09 PM PDT 24
Finished Mar 12 01:59:19 PM PDT 24
Peak memory 208124 kb
Host smart-cd0a0973-1980-46d6-b8ce-a5fbd5d84536
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610823108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.1610823108
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.2045063357
Short name T543
Test name
Test status
Simulation time 187573427 ps
CPU time 6.05 seconds
Started Mar 12 01:59:09 PM PDT 24
Finished Mar 12 01:59:16 PM PDT 24
Peak memory 207956 kb
Host smart-1dc55bfd-4aea-4799-a6ee-8fa22b146a82
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045063357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.2045063357
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.4290037404
Short name T515
Test name
Test status
Simulation time 76407637 ps
CPU time 2.07 seconds
Started Mar 12 01:59:08 PM PDT 24
Finished Mar 12 01:59:11 PM PDT 24
Peak memory 209424 kb
Host smart-39b36dee-8f59-4f4d-bf64-8b10ac90b0b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4290037404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.4290037404
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.2393805113
Short name T847
Test name
Test status
Simulation time 350605112 ps
CPU time 3.25 seconds
Started Mar 12 01:59:09 PM PDT 24
Finished Mar 12 01:59:13 PM PDT 24
Peak memory 208388 kb
Host smart-42216f0f-be78-4afd-8abf-c2da5fa3ea2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393805113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.2393805113
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.2210449151
Short name T322
Test name
Test status
Simulation time 1851310141 ps
CPU time 17.68 seconds
Started Mar 12 01:59:10 PM PDT 24
Finished Mar 12 01:59:28 PM PDT 24
Peak memory 216756 kb
Host smart-5d903d8f-b56f-449b-93f7-9cffd016a97c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210449151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.2210449151
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.2196839171
Short name T333
Test name
Test status
Simulation time 178252443 ps
CPU time 5.41 seconds
Started Mar 12 01:59:10 PM PDT 24
Finished Mar 12 01:59:16 PM PDT 24
Peak memory 214580 kb
Host smart-f99de624-7f26-4e81-8636-d8a4eaeafeba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196839171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.2196839171
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.1427405915
Short name T409
Test name
Test status
Simulation time 186521596 ps
CPU time 2.4 seconds
Started Mar 12 01:59:10 PM PDT 24
Finished Mar 12 01:59:13 PM PDT 24
Peak memory 209820 kb
Host smart-714aa84e-18a0-4187-b6d7-4d6ec0173795
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427405915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.1427405915
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.909930032
Short name T749
Test name
Test status
Simulation time 23680788 ps
CPU time 0.82 seconds
Started Mar 12 01:59:19 PM PDT 24
Finished Mar 12 01:59:20 PM PDT 24
Peak memory 206072 kb
Host smart-a08af827-3481-4a6d-8997-9abe693fdac2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909930032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.909930032
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.1918545557
Short name T411
Test name
Test status
Simulation time 98825813 ps
CPU time 3.64 seconds
Started Mar 12 01:59:21 PM PDT 24
Finished Mar 12 01:59:25 PM PDT 24
Peak memory 214460 kb
Host smart-aa396076-eba1-437c-9179-ecdbeb2e57fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1918545557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.1918545557
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.1406170272
Short name T661
Test name
Test status
Simulation time 209521301 ps
CPU time 5.67 seconds
Started Mar 12 01:59:20 PM PDT 24
Finished Mar 12 01:59:26 PM PDT 24
Peak memory 209408 kb
Host smart-c751be98-1b70-467f-b6b7-512178ba3e91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406170272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.1406170272
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.2736632172
Short name T48
Test name
Test status
Simulation time 231279581 ps
CPU time 3.04 seconds
Started Mar 12 01:59:20 PM PDT 24
Finished Mar 12 01:59:23 PM PDT 24
Peak memory 207884 kb
Host smart-efeaa674-a184-40cb-87e9-74a0386d77ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736632172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.2736632172
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.3523968102
Short name T272
Test name
Test status
Simulation time 570529449 ps
CPU time 3.23 seconds
Started Mar 12 01:59:23 PM PDT 24
Finished Mar 12 01:59:26 PM PDT 24
Peak memory 209060 kb
Host smart-5421ba55-3886-43d9-a7b4-a3a4f7eecf5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523968102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.3523968102
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.775004532
Short name T774
Test name
Test status
Simulation time 254642340 ps
CPU time 1.4 seconds
Started Mar 12 01:59:20 PM PDT 24
Finished Mar 12 01:59:21 PM PDT 24
Peak memory 206296 kb
Host smart-a9d3a781-8b9e-45b6-9317-2061aab2f321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775004532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.775004532
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.903770416
Short name T698
Test name
Test status
Simulation time 1995969873 ps
CPU time 72.74 seconds
Started Mar 12 01:59:19 PM PDT 24
Finished Mar 12 02:00:31 PM PDT 24
Peak memory 209416 kb
Host smart-249ff68f-ff33-4529-9724-56946a958543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903770416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.903770416
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.2605807250
Short name T81
Test name
Test status
Simulation time 182128979 ps
CPU time 5.55 seconds
Started Mar 12 01:59:16 PM PDT 24
Finished Mar 12 01:59:21 PM PDT 24
Peak memory 208164 kb
Host smart-ff02c595-8603-484c-8633-7de52ed97943
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2605807250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.2605807250
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.1591718646
Short name T731
Test name
Test status
Simulation time 109597028 ps
CPU time 3.1 seconds
Started Mar 12 01:59:10 PM PDT 24
Finished Mar 12 01:59:14 PM PDT 24
Peak memory 207376 kb
Host smart-dad4e33d-f0cf-445e-ac17-83e5e4114844
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591718646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.1591718646
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.1730744946
Short name T600
Test name
Test status
Simulation time 73648168 ps
CPU time 3.69 seconds
Started Mar 12 01:59:08 PM PDT 24
Finished Mar 12 01:59:13 PM PDT 24
Peak memory 208680 kb
Host smart-e7ab1255-276d-4bf6-8d63-356b33ed48ac
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730744946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.1730744946
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.528160022
Short name T636
Test name
Test status
Simulation time 236445216 ps
CPU time 5.37 seconds
Started Mar 12 01:59:18 PM PDT 24
Finished Mar 12 01:59:24 PM PDT 24
Peak memory 208780 kb
Host smart-be6db19e-80b1-4c94-ba57-da34f1e8301c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528160022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.528160022
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.2149076206
Short name T381
Test name
Test status
Simulation time 1298680881 ps
CPU time 13.88 seconds
Started Mar 12 01:59:23 PM PDT 24
Finished Mar 12 01:59:37 PM PDT 24
Peak memory 209160 kb
Host smart-576647a9-b7d1-42dd-80d6-dbdba4da7289
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2149076206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.2149076206
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.1329552240
Short name T775
Test name
Test status
Simulation time 1867978950 ps
CPU time 18.88 seconds
Started Mar 12 01:59:11 PM PDT 24
Finished Mar 12 01:59:30 PM PDT 24
Peak memory 208556 kb
Host smart-093796ec-a4d0-4ec7-9564-a62aed8e2417
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329552240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.1329552240
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.444714838
Short name T317
Test name
Test status
Simulation time 2909805734 ps
CPU time 20.04 seconds
Started Mar 12 01:59:17 PM PDT 24
Finished Mar 12 01:59:37 PM PDT 24
Peak memory 222436 kb
Host smart-6dcd31f5-da65-4d89-ba25-ab77b5064a19
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=444714838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.444714838
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_stress_all_with_rand_reset.1861530107
Short name T131
Test name
Test status
Simulation time 479639550 ps
CPU time 18.04 seconds
Started Mar 12 01:59:18 PM PDT 24
Finished Mar 12 01:59:36 PM PDT 24
Peak memory 222832 kb
Host smart-2251049f-f4c0-48b0-8c8c-215c365e2bf0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1861530107 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all_with_rand_reset.1861530107
Directory /workspace/46.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.183105004
Short name T713
Test name
Test status
Simulation time 51612817 ps
CPU time 3.33 seconds
Started Mar 12 01:59:18 PM PDT 24
Finished Mar 12 01:59:21 PM PDT 24
Peak memory 210056 kb
Host smart-bb224eb4-13ab-4365-b0c7-cc8b395b743b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=183105004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.183105004
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.3089307170
Short name T547
Test name
Test status
Simulation time 41918334 ps
CPU time 2.33 seconds
Started Mar 12 01:59:19 PM PDT 24
Finished Mar 12 01:59:22 PM PDT 24
Peak memory 209932 kb
Host smart-f9913c07-bca1-4a1d-b9ee-355ca79356a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089307170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.3089307170
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.704791500
Short name T223
Test name
Test status
Simulation time 17932058 ps
CPU time 0.74 seconds
Started Mar 12 01:59:22 PM PDT 24
Finished Mar 12 01:59:23 PM PDT 24
Peak memory 206184 kb
Host smart-97c7c769-fafe-4c12-b86a-4ecc575b6205
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=704791500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.704791500
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.2558183234
Short name T396
Test name
Test status
Simulation time 133957181 ps
CPU time 7.36 seconds
Started Mar 12 01:59:22 PM PDT 24
Finished Mar 12 01:59:30 PM PDT 24
Peak memory 214504 kb
Host smart-623a3114-9385-4ab7-b31e-d70e1915bacb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2558183234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.2558183234
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.1284351128
Short name T772
Test name
Test status
Simulation time 314942571 ps
CPU time 10.77 seconds
Started Mar 12 01:59:18 PM PDT 24
Finished Mar 12 01:59:29 PM PDT 24
Peak memory 210188 kb
Host smart-3d1c24f9-7bda-421e-91cb-5152621f2cd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1284351128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.1284351128
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.989486561
Short name T71
Test name
Test status
Simulation time 209181843 ps
CPU time 5.24 seconds
Started Mar 12 01:59:19 PM PDT 24
Finished Mar 12 01:59:24 PM PDT 24
Peak memory 218228 kb
Host smart-c89d07aa-a3a1-4d9a-b43d-b8a991dc7949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989486561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.989486561
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.1131405957
Short name T98
Test name
Test status
Simulation time 253692659 ps
CPU time 9.95 seconds
Started Mar 12 01:59:19 PM PDT 24
Finished Mar 12 01:59:29 PM PDT 24
Peak memory 210036 kb
Host smart-cfdaf206-31ff-4d3b-8ddb-0e2f609f9d22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131405957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.1131405957
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.611812801
Short name T281
Test name
Test status
Simulation time 112990979 ps
CPU time 4.4 seconds
Started Mar 12 01:59:22 PM PDT 24
Finished Mar 12 01:59:26 PM PDT 24
Peak memory 211412 kb
Host smart-0dd25708-f426-4e3a-a6aa-93bfa083bbb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=611812801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.611812801
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.1240660891
Short name T217
Test name
Test status
Simulation time 58158571 ps
CPU time 2.38 seconds
Started Mar 12 01:59:18 PM PDT 24
Finished Mar 12 01:59:21 PM PDT 24
Peak memory 215348 kb
Host smart-6af9184a-9d78-4280-af2d-701bb63d1dae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240660891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.1240660891
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.3159975454
Short name T558
Test name
Test status
Simulation time 84665668 ps
CPU time 3.53 seconds
Started Mar 12 01:59:18 PM PDT 24
Finished Mar 12 01:59:21 PM PDT 24
Peak memory 207908 kb
Host smart-fdf1d1be-045e-4e25-9c7c-656b628828fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3159975454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.3159975454
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.2612237959
Short name T240
Test name
Test status
Simulation time 240024348 ps
CPU time 2.58 seconds
Started Mar 12 01:59:18 PM PDT 24
Finished Mar 12 01:59:20 PM PDT 24
Peak memory 206800 kb
Host smart-3e7af445-4ec5-4d5e-a1fc-71936e886bb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612237959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.2612237959
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.3484369997
Short name T360
Test name
Test status
Simulation time 70205780 ps
CPU time 3.12 seconds
Started Mar 12 01:59:20 PM PDT 24
Finished Mar 12 01:59:23 PM PDT 24
Peak memory 208580 kb
Host smart-ae250a6c-926a-438f-beaf-7530d87196ec
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3484369997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.3484369997
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.239856357
Short name T703
Test name
Test status
Simulation time 64152074 ps
CPU time 2.59 seconds
Started Mar 12 01:59:19 PM PDT 24
Finished Mar 12 01:59:21 PM PDT 24
Peak memory 207460 kb
Host smart-b9eda188-28af-4525-80d9-f00eb223f952
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=239856357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.239856357
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.3265222452
Short name T630
Test name
Test status
Simulation time 40521384 ps
CPU time 2.38 seconds
Started Mar 12 01:59:19 PM PDT 24
Finished Mar 12 01:59:21 PM PDT 24
Peak memory 206872 kb
Host smart-e3a7873b-8280-454f-ac98-05a6d141626b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265222452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.3265222452
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.155304704
Short name T375
Test name
Test status
Simulation time 1612111978 ps
CPU time 6.23 seconds
Started Mar 12 01:59:21 PM PDT 24
Finished Mar 12 01:59:28 PM PDT 24
Peak memory 209860 kb
Host smart-90d2bdd8-07ac-4dc9-aac3-ba3f0a5eff74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=155304704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.155304704
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.2339516340
Short name T623
Test name
Test status
Simulation time 90914065 ps
CPU time 3.15 seconds
Started Mar 12 01:59:19 PM PDT 24
Finished Mar 12 01:59:22 PM PDT 24
Peak memory 206772 kb
Host smart-ad7181e9-52ef-4c7a-a82c-3e1ea9cf93fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2339516340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.2339516340
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.2818603797
Short name T718
Test name
Test status
Simulation time 32418470012 ps
CPU time 181.53 seconds
Started Mar 12 01:59:20 PM PDT 24
Finished Mar 12 02:02:22 PM PDT 24
Peak memory 218588 kb
Host smart-b54b2547-c8f4-43af-8d72-7ae942d71cb5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818603797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.2818603797
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.538017430
Short name T275
Test name
Test status
Simulation time 86200724 ps
CPU time 3.21 seconds
Started Mar 12 01:59:24 PM PDT 24
Finished Mar 12 01:59:27 PM PDT 24
Peak memory 207308 kb
Host smart-51c683c4-62c1-4b80-9c4a-0b9504a00435
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538017430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.538017430
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.3517346010
Short name T150
Test name
Test status
Simulation time 168617343 ps
CPU time 2.42 seconds
Started Mar 12 01:59:21 PM PDT 24
Finished Mar 12 01:59:24 PM PDT 24
Peak memory 209832 kb
Host smart-094d63bc-72e0-4301-b842-a08edb397b09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3517346010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.3517346010
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.148366583
Short name T518
Test name
Test status
Simulation time 29590034 ps
CPU time 0.79 seconds
Started Mar 12 01:59:32 PM PDT 24
Finished Mar 12 01:59:33 PM PDT 24
Peak memory 206064 kb
Host smart-95a2150b-9fe1-4e4d-ba8b-0989006dc614
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148366583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.148366583
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.1123764775
Short name T550
Test name
Test status
Simulation time 144095371 ps
CPU time 3.5 seconds
Started Mar 12 01:59:20 PM PDT 24
Finished Mar 12 01:59:23 PM PDT 24
Peak memory 214428 kb
Host smart-16edb964-9ccc-488b-8c7b-f03ae631f968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123764775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.1123764775
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.993574194
Short name T87
Test name
Test status
Simulation time 156120931 ps
CPU time 4.11 seconds
Started Mar 12 01:59:29 PM PDT 24
Finished Mar 12 01:59:35 PM PDT 24
Peak memory 214432 kb
Host smart-7ae5355e-f0a9-4828-8cfa-324e1974d098
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993574194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.993574194
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.2437989937
Short name T143
Test name
Test status
Simulation time 374343937 ps
CPU time 3.24 seconds
Started Mar 12 01:59:22 PM PDT 24
Finished Mar 12 01:59:25 PM PDT 24
Peak memory 218720 kb
Host smart-4dcc0185-143b-4307-a7d4-b197c27c44de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437989937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.2437989937
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.2174654727
Short name T270
Test name
Test status
Simulation time 254557295 ps
CPU time 7.8 seconds
Started Mar 12 01:59:19 PM PDT 24
Finished Mar 12 01:59:27 PM PDT 24
Peak memory 209292 kb
Host smart-84abbf74-418c-4216-828c-35857c795fac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174654727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.2174654727
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.4134553868
Short name T635
Test name
Test status
Simulation time 151147983 ps
CPU time 2.75 seconds
Started Mar 12 01:59:19 PM PDT 24
Finished Mar 12 01:59:22 PM PDT 24
Peak memory 208452 kb
Host smart-16915353-6384-42d6-a2c4-7b5ce074a815
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4134553868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.4134553868
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.946630962
Short name T694
Test name
Test status
Simulation time 2442801013 ps
CPU time 37.18 seconds
Started Mar 12 01:59:19 PM PDT 24
Finished Mar 12 01:59:57 PM PDT 24
Peak memory 207876 kb
Host smart-4d5fc059-452d-42f2-a653-6f4d8a7bafa4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946630962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.946630962
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.3371642751
Short name T642
Test name
Test status
Simulation time 166114098 ps
CPU time 4.39 seconds
Started Mar 12 01:59:21 PM PDT 24
Finished Mar 12 01:59:26 PM PDT 24
Peak memory 208976 kb
Host smart-6071a5b3-1b8c-44f7-88ac-a572f07ba011
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3371642751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.3371642751
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.2546047205
Short name T466
Test name
Test status
Simulation time 237764565 ps
CPU time 4.67 seconds
Started Mar 12 01:59:21 PM PDT 24
Finished Mar 12 01:59:26 PM PDT 24
Peak memory 206876 kb
Host smart-f53fe330-b85f-4db2-ad00-345ecc56a71d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546047205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.2546047205
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.3196678022
Short name T877
Test name
Test status
Simulation time 483928465 ps
CPU time 3.54 seconds
Started Mar 12 01:59:31 PM PDT 24
Finished Mar 12 01:59:35 PM PDT 24
Peak memory 215324 kb
Host smart-b3eb5dee-c233-44ed-9341-beea1341d382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196678022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.3196678022
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.3414899273
Short name T562
Test name
Test status
Simulation time 172710898 ps
CPU time 3.52 seconds
Started Mar 12 01:59:23 PM PDT 24
Finished Mar 12 01:59:27 PM PDT 24
Peak memory 206696 kb
Host smart-feb228fd-b233-4e67-a4bd-7afebbb218e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3414899273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.3414899273
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.2404370251
Short name T481
Test name
Test status
Simulation time 379933579 ps
CPU time 14.88 seconds
Started Mar 12 01:59:29 PM PDT 24
Finished Mar 12 01:59:45 PM PDT 24
Peak memory 216204 kb
Host smart-1a6fe459-fce9-4926-95e1-559f17b1ed0e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404370251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.2404370251
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.439040464
Short name T825
Test name
Test status
Simulation time 251417378 ps
CPU time 3.72 seconds
Started Mar 12 01:59:20 PM PDT 24
Finished Mar 12 01:59:24 PM PDT 24
Peak memory 207476 kb
Host smart-63c209fc-ee32-46eb-b821-f136f9caedda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439040464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.439040464
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.1002809712
Short name T194
Test name
Test status
Simulation time 393685152 ps
CPU time 1.8 seconds
Started Mar 12 01:59:36 PM PDT 24
Finished Mar 12 01:59:38 PM PDT 24
Peak memory 209768 kb
Host smart-b4a537e9-d6cf-42f0-8588-b992b16b00c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1002809712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.1002809712
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.3100068470
Short name T597
Test name
Test status
Simulation time 17177241 ps
CPU time 0.85 seconds
Started Mar 12 01:59:32 PM PDT 24
Finished Mar 12 01:59:33 PM PDT 24
Peak memory 206060 kb
Host smart-cc4e43cd-2f69-4733-b2ae-7cec048538f8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3100068470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.3100068470
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.2526748173
Short name T837
Test name
Test status
Simulation time 195725866 ps
CPU time 2.31 seconds
Started Mar 12 01:59:30 PM PDT 24
Finished Mar 12 01:59:33 PM PDT 24
Peak memory 219344 kb
Host smart-c9548e0f-7527-44a6-9d97-c5d69eee4c63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2526748173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.2526748173
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.3299566741
Short name T220
Test name
Test status
Simulation time 65383426 ps
CPU time 2.71 seconds
Started Mar 12 01:59:29 PM PDT 24
Finished Mar 12 01:59:33 PM PDT 24
Peak memory 208052 kb
Host smart-3d952170-0ba3-439c-a8a3-f343754629a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3299566741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.3299566741
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.3803528642
Short name T723
Test name
Test status
Simulation time 107927955 ps
CPU time 5.17 seconds
Started Mar 12 01:59:30 PM PDT 24
Finished Mar 12 01:59:36 PM PDT 24
Peak memory 214496 kb
Host smart-f4e21489-4fa2-4c4b-aeca-2d0fdd2e47c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803528642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.3803528642
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.2352624425
Short name T542
Test name
Test status
Simulation time 358606435 ps
CPU time 18.09 seconds
Started Mar 12 01:59:35 PM PDT 24
Finished Mar 12 01:59:53 PM PDT 24
Peak memory 217984 kb
Host smart-a97958ed-2115-494a-8d49-db17d2792dc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352624425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.2352624425
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.3819687003
Short name T555
Test name
Test status
Simulation time 466633032 ps
CPU time 9.52 seconds
Started Mar 12 01:59:34 PM PDT 24
Finished Mar 12 01:59:44 PM PDT 24
Peak memory 209392 kb
Host smart-0891a56f-eb63-4014-a1e5-6780a95e9033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819687003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.3819687003
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.2115162472
Short name T79
Test name
Test status
Simulation time 1316693023 ps
CPU time 7.88 seconds
Started Mar 12 01:59:32 PM PDT 24
Finished Mar 12 01:59:40 PM PDT 24
Peak memory 207708 kb
Host smart-cd74ed5f-131a-4d46-94c1-ad558e83e37a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115162472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.2115162472
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.282098805
Short name T475
Test name
Test status
Simulation time 170566884 ps
CPU time 2.89 seconds
Started Mar 12 01:59:29 PM PDT 24
Finished Mar 12 01:59:33 PM PDT 24
Peak memory 206904 kb
Host smart-6fdf60fb-21e0-4243-95a8-9c5252f4b0ad
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=282098805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.282098805
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.3303359174
Short name T710
Test name
Test status
Simulation time 639008376 ps
CPU time 6.95 seconds
Started Mar 12 01:59:28 PM PDT 24
Finished Mar 12 01:59:36 PM PDT 24
Peak memory 208968 kb
Host smart-faa77db5-3cd7-47e3-b300-be05762dfef5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303359174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.3303359174
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.2527030340
Short name T353
Test name
Test status
Simulation time 909111212 ps
CPU time 10.28 seconds
Started Mar 12 01:59:31 PM PDT 24
Finished Mar 12 01:59:42 PM PDT 24
Peak memory 207904 kb
Host smart-cddc32b4-04c8-495c-b839-78dd3594717e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2527030340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.2527030340
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.2913508240
Short name T753
Test name
Test status
Simulation time 103275849 ps
CPU time 2.02 seconds
Started Mar 12 01:59:36 PM PDT 24
Finished Mar 12 01:59:38 PM PDT 24
Peak memory 207512 kb
Host smart-2fe32a94-2dc5-422d-8bae-81f8af170f79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2913508240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.2913508240
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.3594684264
Short name T621
Test name
Test status
Simulation time 122080717 ps
CPU time 4.75 seconds
Started Mar 12 01:59:30 PM PDT 24
Finished Mar 12 01:59:36 PM PDT 24
Peak memory 208440 kb
Host smart-7eda5922-76f4-4bf5-b481-46f4a722dab9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594684264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.3594684264
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.1035665540
Short name T423
Test name
Test status
Simulation time 94932072 ps
CPU time 4.57 seconds
Started Mar 12 01:59:30 PM PDT 24
Finished Mar 12 01:59:36 PM PDT 24
Peak memory 208364 kb
Host smart-c3c49a38-e2ee-4026-9336-b11d53030ae5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1035665540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.1035665540
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.837734016
Short name T200
Test name
Test status
Simulation time 472174876 ps
CPU time 6.43 seconds
Started Mar 12 01:59:27 PM PDT 24
Finished Mar 12 01:59:35 PM PDT 24
Peak memory 207092 kb
Host smart-6959b170-eb79-41a6-b156-d317007a6838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=837734016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.837734016
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.471820823
Short name T786
Test name
Test status
Simulation time 79107030 ps
CPU time 3.26 seconds
Started Mar 12 01:59:30 PM PDT 24
Finished Mar 12 01:59:34 PM PDT 24
Peak memory 210204 kb
Host smart-96377544-e153-4301-a442-7cb316fc9f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=471820823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.471820823
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.292990376
Short name T722
Test name
Test status
Simulation time 17704660 ps
CPU time 0.95 seconds
Started Mar 12 01:55:14 PM PDT 24
Finished Mar 12 01:55:15 PM PDT 24
Peak memory 206320 kb
Host smart-936527e4-b4c9-4d19-842b-e9991bae5f10
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292990376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.292990376
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.1727704992
Short name T349
Test name
Test status
Simulation time 32127894 ps
CPU time 2.71 seconds
Started Mar 12 01:55:15 PM PDT 24
Finished Mar 12 01:55:18 PM PDT 24
Peak memory 214304 kb
Host smart-238b7f33-30db-48dd-906c-7544b183d1b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1727704992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.1727704992
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.2469660526
Short name T9
Test name
Test status
Simulation time 110936368 ps
CPU time 3.62 seconds
Started Mar 12 01:55:14 PM PDT 24
Finished Mar 12 01:55:18 PM PDT 24
Peak memory 209640 kb
Host smart-1f53fec7-1838-4879-803d-3e32244ea1cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469660526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.2469660526
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.3500567849
Short name T864
Test name
Test status
Simulation time 454342185 ps
CPU time 3.9 seconds
Started Mar 12 01:55:15 PM PDT 24
Finished Mar 12 01:55:19 PM PDT 24
Peak memory 209636 kb
Host smart-bd36d918-c322-4b69-b178-16fa34e6cfe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500567849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.3500567849
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.372565647
Short name T97
Test name
Test status
Simulation time 86050691 ps
CPU time 4.27 seconds
Started Mar 12 01:55:13 PM PDT 24
Finished Mar 12 01:55:17 PM PDT 24
Peak memory 214508 kb
Host smart-39082765-713f-4f6f-8e4e-1709843abc2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372565647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.372565647
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.4145596132
Short name T355
Test name
Test status
Simulation time 161080039 ps
CPU time 5.67 seconds
Started Mar 12 01:55:11 PM PDT 24
Finished Mar 12 01:55:17 PM PDT 24
Peak memory 211408 kb
Host smart-36649592-1632-46ea-8f95-da0c702b6128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4145596132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.4145596132
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.1149539924
Short name T263
Test name
Test status
Simulation time 40522561 ps
CPU time 3.08 seconds
Started Mar 12 01:55:12 PM PDT 24
Finished Mar 12 01:55:15 PM PDT 24
Peak memory 215952 kb
Host smart-34304896-4288-4d92-9bb3-a3bb678cde23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149539924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.1149539924
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.2398896687
Short name T588
Test name
Test status
Simulation time 644614085 ps
CPU time 5.36 seconds
Started Mar 12 01:55:12 PM PDT 24
Finished Mar 12 01:55:17 PM PDT 24
Peak memory 207516 kb
Host smart-202732ac-bb1a-4206-8c69-513cf0c6bd16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398896687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.2398896687
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.1354886566
Short name T746
Test name
Test status
Simulation time 105893685 ps
CPU time 2.04 seconds
Started Mar 12 01:55:02 PM PDT 24
Finished Mar 12 01:55:04 PM PDT 24
Peak memory 206792 kb
Host smart-9002aeb3-c817-4c76-bd77-ed6a5f1587bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1354886566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.1354886566
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.3182564518
Short name T754
Test name
Test status
Simulation time 39568965 ps
CPU time 2.28 seconds
Started Mar 12 01:55:12 PM PDT 24
Finished Mar 12 01:55:14 PM PDT 24
Peak memory 208000 kb
Host smart-dd8d007e-2bc3-40f5-b8ea-c152750a2b75
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182564518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.3182564518
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.2405712976
Short name T798
Test name
Test status
Simulation time 366410909 ps
CPU time 3.75 seconds
Started Mar 12 01:55:10 PM PDT 24
Finished Mar 12 01:55:14 PM PDT 24
Peak memory 208832 kb
Host smart-ecbfaf02-d5f0-4231-a544-ecfcc5a7c2b7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405712976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.2405712976
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.3574579340
Short name T139
Test name
Test status
Simulation time 75138845 ps
CPU time 3.38 seconds
Started Mar 12 01:55:10 PM PDT 24
Finished Mar 12 01:55:14 PM PDT 24
Peak memory 208676 kb
Host smart-79c3f67d-b69d-4000-9c87-fef1bfefb719
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3574579340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.3574579340
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.937006998
Short name T704
Test name
Test status
Simulation time 82103004 ps
CPU time 1.83 seconds
Started Mar 12 01:55:15 PM PDT 24
Finished Mar 12 01:55:17 PM PDT 24
Peak memory 209888 kb
Host smart-97ef674c-367e-4bea-a8ad-100fcffd03cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937006998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.937006998
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.1217780229
Short name T421
Test name
Test status
Simulation time 25235077 ps
CPU time 2 seconds
Started Mar 12 01:55:01 PM PDT 24
Finished Mar 12 01:55:03 PM PDT 24
Peak memory 208492 kb
Host smart-c5cd5db1-bf2a-4ea2-b9d1-ad9b78fdaf77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1217780229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.1217780229
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.368874167
Short name T253
Test name
Test status
Simulation time 407504807 ps
CPU time 11.98 seconds
Started Mar 12 01:55:11 PM PDT 24
Finished Mar 12 01:55:23 PM PDT 24
Peak memory 215184 kb
Host smart-769b081a-3c00-46f8-bb46-539599d0bf7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368874167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.368874167
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_stress_all_with_rand_reset.310873229
Short name T135
Test name
Test status
Simulation time 1040608302 ps
CPU time 13.05 seconds
Started Mar 12 01:55:11 PM PDT 24
Finished Mar 12 01:55:25 PM PDT 24
Peak memory 222688 kb
Host smart-21c7a99c-1065-4b6c-8126-4939e75c8f25
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310873229 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all_with_rand_reset.310873229
Directory /workspace/5.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.1248285818
Short name T198
Test name
Test status
Simulation time 142775921 ps
CPU time 3.34 seconds
Started Mar 12 01:55:13 PM PDT 24
Finished Mar 12 01:55:17 PM PDT 24
Peak memory 207400 kb
Host smart-cc4b5fcf-233c-49eb-a073-e537fe15d11a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248285818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.1248285818
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.3728667099
Short name T529
Test name
Test status
Simulation time 52077213 ps
CPU time 0.76 seconds
Started Mar 12 01:55:23 PM PDT 24
Finished Mar 12 01:55:24 PM PDT 24
Peak memory 206184 kb
Host smart-81b4b65d-8644-4746-a779-ed19498b2b23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728667099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.3728667099
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.3761867405
Short name T763
Test name
Test status
Simulation time 35956706 ps
CPU time 2.73 seconds
Started Mar 12 01:55:19 PM PDT 24
Finished Mar 12 01:55:22 PM PDT 24
Peak memory 215592 kb
Host smart-bc34e12e-a09c-4eb4-95bd-4c3affa5c709
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3761867405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.3761867405
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.1450556810
Short name T494
Test name
Test status
Simulation time 129517366 ps
CPU time 4.19 seconds
Started Mar 12 01:55:22 PM PDT 24
Finished Mar 12 01:55:27 PM PDT 24
Peak memory 209152 kb
Host smart-00373779-a69a-4afd-b212-b8254d89674d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450556810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.1450556810
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.3051231351
Short name T90
Test name
Test status
Simulation time 2451809775 ps
CPU time 42.1 seconds
Started Mar 12 01:55:23 PM PDT 24
Finished Mar 12 01:56:05 PM PDT 24
Peak memory 214452 kb
Host smart-2b4c2d2a-9b6e-474f-b968-008fcc0c7f8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051231351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.3051231351
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.1892595903
Short name T246
Test name
Test status
Simulation time 196865056 ps
CPU time 3.79 seconds
Started Mar 12 01:55:21 PM PDT 24
Finished Mar 12 01:55:25 PM PDT 24
Peak memory 210080 kb
Host smart-d81fb34d-1b64-458c-ba85-359db6fa1030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892595903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.1892595903
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.340341783
Short name T137
Test name
Test status
Simulation time 169183792 ps
CPU time 4.45 seconds
Started Mar 12 01:55:22 PM PDT 24
Finished Mar 12 01:55:27 PM PDT 24
Peak memory 208520 kb
Host smart-fe99d157-6ed4-45c4-9ca7-2d83289cdf27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=340341783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.340341783
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.1309943997
Short name T664
Test name
Test status
Simulation time 34995622 ps
CPU time 2.63 seconds
Started Mar 12 01:55:21 PM PDT 24
Finished Mar 12 01:55:24 PM PDT 24
Peak memory 207476 kb
Host smart-be97565b-f1d0-4fb1-a755-7b60b09afadb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1309943997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.1309943997
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.4238977629
Short name T799
Test name
Test status
Simulation time 970305869 ps
CPU time 11.06 seconds
Started Mar 12 01:55:21 PM PDT 24
Finished Mar 12 01:55:33 PM PDT 24
Peak memory 207776 kb
Host smart-b1dc1d5c-9f0a-4c0e-8a24-5aac1e9531b5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4238977629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.4238977629
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.1021865235
Short name T537
Test name
Test status
Simulation time 191449688 ps
CPU time 2.97 seconds
Started Mar 12 01:55:21 PM PDT 24
Finished Mar 12 01:55:24 PM PDT 24
Peak memory 206760 kb
Host smart-e6113963-3c8f-4e91-b447-ec9cd2eb26da
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021865235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.1021865235
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.3086671934
Short name T242
Test name
Test status
Simulation time 43168505 ps
CPU time 2.78 seconds
Started Mar 12 01:55:28 PM PDT 24
Finished Mar 12 01:55:31 PM PDT 24
Peak memory 208476 kb
Host smart-14848876-130e-4428-86eb-d5d32b67413e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086671934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.3086671934
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.765950958
Short name T686
Test name
Test status
Simulation time 3961129582 ps
CPU time 19.97 seconds
Started Mar 12 01:55:28 PM PDT 24
Finished Mar 12 01:55:48 PM PDT 24
Peak memory 209196 kb
Host smart-15a8fa96-a125-4eb4-947a-cc9cdf5254c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=765950958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.765950958
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.1938241671
Short name T226
Test name
Test status
Simulation time 1992309238 ps
CPU time 36.94 seconds
Started Mar 12 01:55:14 PM PDT 24
Finished Mar 12 01:55:51 PM PDT 24
Peak memory 208212 kb
Host smart-560728a8-f473-4f4c-a2ad-7c68be67350c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1938241671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.1938241671
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.3934012174
Short name T208
Test name
Test status
Simulation time 2491936804 ps
CPU time 33.7 seconds
Started Mar 12 01:55:20 PM PDT 24
Finished Mar 12 01:55:54 PM PDT 24
Peak memory 220768 kb
Host smart-8673cbed-50b9-44e2-b3b0-c37e57eac139
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934012174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.3934012174
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.1956730558
Short name T363
Test name
Test status
Simulation time 3441620271 ps
CPU time 23.69 seconds
Started Mar 12 01:55:20 PM PDT 24
Finished Mar 12 01:55:44 PM PDT 24
Peak memory 209060 kb
Host smart-893f3c05-d203-4656-b637-d2eb51013675
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956730558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.1956730558
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.2975529790
Short name T37
Test name
Test status
Simulation time 403429763 ps
CPU time 2.92 seconds
Started Mar 12 01:55:22 PM PDT 24
Finished Mar 12 01:55:25 PM PDT 24
Peak memory 210140 kb
Host smart-a962da25-dbbc-4629-8e91-801ed3e056a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975529790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.2975529790
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.3335197989
Short name T672
Test name
Test status
Simulation time 37528157 ps
CPU time 0.89 seconds
Started Mar 12 01:55:30 PM PDT 24
Finished Mar 12 01:55:32 PM PDT 24
Peak memory 206172 kb
Host smart-4f641f52-f501-44d9-94df-15bb1c957119
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3335197989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.3335197989
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.2488040748
Short name T438
Test name
Test status
Simulation time 161564504 ps
CPU time 5.6 seconds
Started Mar 12 01:55:30 PM PDT 24
Finished Mar 12 01:55:36 PM PDT 24
Peak memory 215384 kb
Host smart-91970d6f-b28a-49f7-b238-febd4dfb2baf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2488040748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.2488040748
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.3633611648
Short name T29
Test name
Test status
Simulation time 1692146341 ps
CPU time 32.82 seconds
Started Mar 12 01:55:32 PM PDT 24
Finished Mar 12 01:56:05 PM PDT 24
Peak memory 222932 kb
Host smart-c521976e-b212-40f1-8c2a-5b0486d33c67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633611648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.3633611648
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.156911607
Short name T300
Test name
Test status
Simulation time 240406216 ps
CPU time 5.32 seconds
Started Mar 12 01:55:29 PM PDT 24
Finished Mar 12 01:55:35 PM PDT 24
Peak memory 214492 kb
Host smart-289f44cd-085b-42f9-84a3-11336c096ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156911607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.156911607
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.3495454626
Short name T663
Test name
Test status
Simulation time 1164177867 ps
CPU time 5.74 seconds
Started Mar 12 01:55:32 PM PDT 24
Finished Mar 12 01:55:38 PM PDT 24
Peak memory 214420 kb
Host smart-4e0bc5ba-c0c3-4ab6-baad-b7604aecc9e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495454626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.3495454626
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.2157038320
Short name T235
Test name
Test status
Simulation time 3591721506 ps
CPU time 11.44 seconds
Started Mar 12 01:55:29 PM PDT 24
Finished Mar 12 01:55:41 PM PDT 24
Peak memory 211572 kb
Host smart-5007f073-0ab7-4ba6-8ac7-ff6fa856bccc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157038320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.2157038320
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.2788387691
Short name T512
Test name
Test status
Simulation time 907169902 ps
CPU time 4.24 seconds
Started Mar 12 01:55:31 PM PDT 24
Finished Mar 12 01:55:36 PM PDT 24
Peak memory 209848 kb
Host smart-6962535c-1796-4687-85e3-28a91005da9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2788387691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.2788387691
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.50702731
Short name T234
Test name
Test status
Simulation time 1004034632 ps
CPU time 9.2 seconds
Started Mar 12 01:55:33 PM PDT 24
Finished Mar 12 01:55:42 PM PDT 24
Peak memory 207432 kb
Host smart-8140d7a5-783d-4030-84b6-c69311dd2cb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50702731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.50702731
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.3713071460
Short name T613
Test name
Test status
Simulation time 143669236 ps
CPU time 2.2 seconds
Started Mar 12 01:55:31 PM PDT 24
Finished Mar 12 01:55:34 PM PDT 24
Peak memory 207084 kb
Host smart-23963846-2324-40e5-b3f9-7f9a11551b98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713071460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.3713071460
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.3756007221
Short name T700
Test name
Test status
Simulation time 3118004562 ps
CPU time 11.19 seconds
Started Mar 12 01:55:31 PM PDT 24
Finished Mar 12 01:55:43 PM PDT 24
Peak memory 208056 kb
Host smart-d44e5d78-3116-4765-baf7-c2875c85734a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756007221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.3756007221
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.3038675012
Short name T820
Test name
Test status
Simulation time 69687098 ps
CPU time 2.62 seconds
Started Mar 12 01:55:30 PM PDT 24
Finished Mar 12 01:55:34 PM PDT 24
Peak memory 206816 kb
Host smart-d45db2e4-211e-4d42-be01-88114e0274b6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038675012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.3038675012
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.2519999717
Short name T867
Test name
Test status
Simulation time 20999863150 ps
CPU time 46.7 seconds
Started Mar 12 01:55:31 PM PDT 24
Finished Mar 12 01:56:18 PM PDT 24
Peak memory 208388 kb
Host smart-860b9272-95e4-4e9a-bfb3-ed36652046b1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2519999717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.2519999717
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.3300419740
Short name T715
Test name
Test status
Simulation time 106380895 ps
CPU time 2.21 seconds
Started Mar 12 01:55:30 PM PDT 24
Finished Mar 12 01:55:32 PM PDT 24
Peak memory 209692 kb
Host smart-af20edf0-ea35-48a8-b3bb-585b4e02f6a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300419740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.3300419740
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.237193370
Short name T569
Test name
Test status
Simulation time 121756227 ps
CPU time 1.99 seconds
Started Mar 12 01:55:31 PM PDT 24
Finished Mar 12 01:55:33 PM PDT 24
Peak memory 208236 kb
Host smart-bb256480-b50b-433b-8020-6618100673b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=237193370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.237193370
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.3057777969
Short name T292
Test name
Test status
Simulation time 525214996 ps
CPU time 8.27 seconds
Started Mar 12 01:55:32 PM PDT 24
Finished Mar 12 01:55:41 PM PDT 24
Peak memory 216084 kb
Host smart-fad0b429-dcca-446b-b714-d6e2967046f4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3057777969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.3057777969
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_stress_all_with_rand_reset.3744692619
Short name T257
Test name
Test status
Simulation time 173763877 ps
CPU time 10.4 seconds
Started Mar 12 01:55:32 PM PDT 24
Finished Mar 12 01:55:43 PM PDT 24
Peak memory 222736 kb
Host smart-cc3091ee-502a-4155-a5c5-f6708a261d41
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744692619 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all_with_rand_reset.3744692619
Directory /workspace/7.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.3116161918
Short name T382
Test name
Test status
Simulation time 160509012 ps
CPU time 5.42 seconds
Started Mar 12 01:55:32 PM PDT 24
Finished Mar 12 01:55:38 PM PDT 24
Peak memory 208840 kb
Host smart-4debe2be-58c2-4a4b-8554-47fffbe5bcf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116161918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.3116161918
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.1965125533
Short name T82
Test name
Test status
Simulation time 41194658 ps
CPU time 2.38 seconds
Started Mar 12 01:55:31 PM PDT 24
Finished Mar 12 01:55:34 PM PDT 24
Peak memory 209772 kb
Host smart-8ed7d2d0-b9e0-498a-8a19-fbfcb58e1edb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965125533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.1965125533
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.1183365984
Short name T154
Test name
Test status
Simulation time 12848004 ps
CPU time 0.9 seconds
Started Mar 12 01:55:40 PM PDT 24
Finished Mar 12 01:55:41 PM PDT 24
Peak memory 206192 kb
Host smart-f70ca046-6fd5-445e-9d6b-a3f6fbe86db9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1183365984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.1183365984
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.2212808637
Short name T401
Test name
Test status
Simulation time 943658071 ps
CPU time 10.49 seconds
Started Mar 12 01:55:41 PM PDT 24
Finished Mar 12 01:55:52 PM PDT 24
Peak memory 214440 kb
Host smart-6ada4aa6-4132-4a68-bd3e-68f770c4a691
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2212808637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.2212808637
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.3058973174
Short name T20
Test name
Test status
Simulation time 675212631 ps
CPU time 4.85 seconds
Started Mar 12 01:55:42 PM PDT 24
Finished Mar 12 01:55:47 PM PDT 24
Peak memory 209880 kb
Host smart-4948bc3b-4609-41ed-a5ea-b84bfd2a66e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3058973174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.3058973174
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.2293614561
Short name T67
Test name
Test status
Simulation time 77174627 ps
CPU time 2.07 seconds
Started Mar 12 01:55:38 PM PDT 24
Finished Mar 12 01:55:41 PM PDT 24
Peak memory 208804 kb
Host smart-1233474b-02be-462e-8e02-f87a2c695d40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293614561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.2293614561
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.1027289048
Short name T645
Test name
Test status
Simulation time 103962075 ps
CPU time 3.36 seconds
Started Mar 12 01:55:40 PM PDT 24
Finished Mar 12 01:55:44 PM PDT 24
Peak memory 214492 kb
Host smart-448ddd0f-471a-4e5c-837f-a5d06529ebaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027289048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.1027289048
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.2830048294
Short name T371
Test name
Test status
Simulation time 54155279 ps
CPU time 3.46 seconds
Started Mar 12 01:55:39 PM PDT 24
Finished Mar 12 01:55:43 PM PDT 24
Peak memory 214404 kb
Host smart-3ceedc81-ac82-4c01-aac5-25ace81d4d4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830048294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.2830048294
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.560358477
Short name T792
Test name
Test status
Simulation time 77583697 ps
CPU time 3.04 seconds
Started Mar 12 01:55:38 PM PDT 24
Finished Mar 12 01:55:41 PM PDT 24
Peak memory 214524 kb
Host smart-c24f434b-c10d-4052-8cfa-09d72b460eec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=560358477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.560358477
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.2932381703
Short name T725
Test name
Test status
Simulation time 55428322 ps
CPU time 3.34 seconds
Started Mar 12 01:55:41 PM PDT 24
Finished Mar 12 01:55:44 PM PDT 24
Peak memory 207868 kb
Host smart-e37f3eba-c417-4115-809d-3ed03828a185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932381703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.2932381703
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.3787739220
Short name T858
Test name
Test status
Simulation time 45123256 ps
CPU time 2.57 seconds
Started Mar 12 01:55:30 PM PDT 24
Finished Mar 12 01:55:33 PM PDT 24
Peak memory 208288 kb
Host smart-fb8b3f84-e51b-45b7-a3ca-2d96c3e2066e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787739220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.3787739220
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.2761942980
Short name T780
Test name
Test status
Simulation time 118411321 ps
CPU time 4.31 seconds
Started Mar 12 01:55:29 PM PDT 24
Finished Mar 12 01:55:34 PM PDT 24
Peak memory 208828 kb
Host smart-852ba77a-b953-4c8c-ab6e-6bbb3d6b987e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2761942980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.2761942980
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.2416533898
Short name T574
Test name
Test status
Simulation time 342921854 ps
CPU time 3.42 seconds
Started Mar 12 01:55:32 PM PDT 24
Finished Mar 12 01:55:36 PM PDT 24
Peak memory 208784 kb
Host smart-b9398e12-6841-4be2-8453-2a6c12adc073
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2416533898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.2416533898
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.3278054693
Short name T298
Test name
Test status
Simulation time 135612159 ps
CPU time 2.77 seconds
Started Mar 12 01:55:31 PM PDT 24
Finished Mar 12 01:55:34 PM PDT 24
Peak memory 206932 kb
Host smart-49de55d4-bfb8-4faa-b855-8f2dada489a7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278054693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.3278054693
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.897841650
Short name T640
Test name
Test status
Simulation time 96611110 ps
CPU time 1.67 seconds
Started Mar 12 01:55:42 PM PDT 24
Finished Mar 12 01:55:43 PM PDT 24
Peak memory 207620 kb
Host smart-956ee0be-f40e-41c3-897c-6515c4c351e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897841650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.897841650
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.1977734548
Short name T463
Test name
Test status
Simulation time 3912023625 ps
CPU time 26.69 seconds
Started Mar 12 01:55:31 PM PDT 24
Finished Mar 12 01:55:59 PM PDT 24
Peak memory 208756 kb
Host smart-a0c142fc-aa97-449b-bd5b-8106a880246c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977734548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.1977734548
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.3445590586
Short name T261
Test name
Test status
Simulation time 2498778382 ps
CPU time 58.01 seconds
Started Mar 12 01:55:41 PM PDT 24
Finished Mar 12 01:56:39 PM PDT 24
Peak memory 222828 kb
Host smart-1eb24610-7a34-4694-8d96-0ff68f14c9a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445590586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.3445590586
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.3217305879
Short name T285
Test name
Test status
Simulation time 854844099 ps
CPU time 7.82 seconds
Started Mar 12 01:55:40 PM PDT 24
Finished Mar 12 01:55:48 PM PDT 24
Peak memory 214468 kb
Host smart-80cecf3c-cdc0-4e84-829d-9fadcbd7fcea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217305879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.3217305879
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.1679735956
Short name T875
Test name
Test status
Simulation time 629326093 ps
CPU time 3.26 seconds
Started Mar 12 01:55:38 PM PDT 24
Finished Mar 12 01:55:42 PM PDT 24
Peak memory 209812 kb
Host smart-ab1efe5c-4b9d-465a-9136-333fa447c724
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679735956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.1679735956
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.3491964167
Short name T456
Test name
Test status
Simulation time 14439569 ps
CPU time 0.74 seconds
Started Mar 12 01:55:52 PM PDT 24
Finished Mar 12 01:55:53 PM PDT 24
Peak memory 206152 kb
Host smart-657276db-1e0f-491a-bdfe-c1c3685d78bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3491964167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.3491964167
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.2364864152
Short name T32
Test name
Test status
Simulation time 558129480 ps
CPU time 5.13 seconds
Started Mar 12 01:55:53 PM PDT 24
Finished Mar 12 01:55:58 PM PDT 24
Peak memory 214492 kb
Host smart-1ea63ecc-ad6e-4a83-a1c9-591ff177abd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364864152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.2364864152
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.1502228385
Short name T677
Test name
Test status
Simulation time 120125467 ps
CPU time 3.97 seconds
Started Mar 12 01:55:40 PM PDT 24
Finished Mar 12 01:55:44 PM PDT 24
Peak memory 209736 kb
Host smart-9eb88b38-3d4b-43c5-b601-841307cb06d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502228385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.1502228385
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.526273799
Short name T656
Test name
Test status
Simulation time 1111289598 ps
CPU time 5.06 seconds
Started Mar 12 01:55:39 PM PDT 24
Finished Mar 12 01:55:45 PM PDT 24
Peak memory 208692 kb
Host smart-a98e70a7-6f41-4b51-9970-5a8a1554aed9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526273799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.526273799
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.380235517
Short name T356
Test name
Test status
Simulation time 5553615940 ps
CPU time 40.25 seconds
Started Mar 12 01:55:55 PM PDT 24
Finished Mar 12 01:56:35 PM PDT 24
Peak memory 214496 kb
Host smart-5fb3af10-7cec-4168-ac2b-ae29e00f5051
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380235517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.380235517
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.1889372143
Short name T699
Test name
Test status
Simulation time 136481058 ps
CPU time 4.29 seconds
Started Mar 12 01:55:40 PM PDT 24
Finished Mar 12 01:55:45 PM PDT 24
Peak memory 209280 kb
Host smart-c966fb09-c84c-48be-9fd3-217d395214a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1889372143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.1889372143
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.2583321550
Short name T327
Test name
Test status
Simulation time 221778900 ps
CPU time 3.8 seconds
Started Mar 12 01:55:39 PM PDT 24
Finished Mar 12 01:55:43 PM PDT 24
Peak memory 208120 kb
Host smart-14f7e3db-f0f8-49c4-9ddf-8f8f95a4ea15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2583321550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.2583321550
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.3843443637
Short name T682
Test name
Test status
Simulation time 1397167249 ps
CPU time 39.65 seconds
Started Mar 12 01:55:41 PM PDT 24
Finished Mar 12 01:56:21 PM PDT 24
Peak memory 208448 kb
Host smart-36a67498-e405-471a-9926-b4a7e67ea147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843443637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.3843443637
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.2524590558
Short name T620
Test name
Test status
Simulation time 991243023 ps
CPU time 31.14 seconds
Started Mar 12 01:55:42 PM PDT 24
Finished Mar 12 01:56:13 PM PDT 24
Peak memory 208420 kb
Host smart-9e55c2d2-7321-467f-8fdb-a476a9499d12
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524590558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.2524590558
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.1042959425
Short name T540
Test name
Test status
Simulation time 23357826 ps
CPU time 1.84 seconds
Started Mar 12 01:55:42 PM PDT 24
Finished Mar 12 01:55:44 PM PDT 24
Peak memory 206880 kb
Host smart-53f03c89-3540-4920-85db-8d98b1c0b96b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1042959425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.1042959425
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.2914445181
Short name T538
Test name
Test status
Simulation time 25584660 ps
CPU time 2.14 seconds
Started Mar 12 01:55:42 PM PDT 24
Finished Mar 12 01:55:44 PM PDT 24
Peak memory 208488 kb
Host smart-39343832-ec7e-4713-85b2-8b39fe22b5b7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2914445181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.2914445181
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.1549577209
Short name T287
Test name
Test status
Simulation time 59445427 ps
CPU time 3.03 seconds
Started Mar 12 01:55:56 PM PDT 24
Finished Mar 12 01:55:59 PM PDT 24
Peak memory 209612 kb
Host smart-cc528fc0-8397-4f7c-93eb-7c89381b1a44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549577209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.1549577209
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.3643046426
Short name T563
Test name
Test status
Simulation time 188309892 ps
CPU time 6.54 seconds
Started Mar 12 01:55:39 PM PDT 24
Finished Mar 12 01:55:45 PM PDT 24
Peak memory 208224 kb
Host smart-8f5043f1-8878-4d6b-8964-4c06a83dd777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643046426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.3643046426
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.3741254883
Short name T654
Test name
Test status
Simulation time 340968435 ps
CPU time 8.05 seconds
Started Mar 12 01:55:42 PM PDT 24
Finished Mar 12 01:55:50 PM PDT 24
Peak memory 209188 kb
Host smart-56f04d7c-40a3-4d9d-bd5e-924440a8b095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3741254883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.3741254883
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.2455820933
Short name T188
Test name
Test status
Simulation time 208779756 ps
CPU time 2.82 seconds
Started Mar 12 01:55:52 PM PDT 24
Finished Mar 12 01:55:55 PM PDT 24
Peak memory 210232 kb
Host smart-b9018f3d-613d-420d-9348-c8f1d16fd17c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455820933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.2455820933
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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