Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
79.79	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	51	0	51	100.00
Crosses	330	77	253	76.67

Variables for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
aes_sl_avail	2	0	2	100.00	100	1	1	2
aes_sl_avail_cp	2	0	2	100.00	100	1	1	2
kmac_sl_avail	2	0	2	100.00	100	1	1	2
kmac_sl_avail_cp	2	0	2	100.00	100	1	1	2
op	5	0	5	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
otbn_sl_avail	2	0	2	100.00	100	1	1	2
otbn_sl_avail_cp	2	0	2	100.00	100	1	1	2
regwen_cp	2	0	2	100.00	100	1	1	2
sideload_clear	8	0	8	100.00	100	1	1	8
sideload_clear_cp	5	0	5	100.00	100	1	1	0
state	7	0	7	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sideload_clear_x_state_op_cross	280	58	222	79.29	100	1	1	0
sideload_clear_x_sl_avail_cross	40	19	21	52.50	100	1	1	0
sideload_clear_x_regwen_cross	10	0	10	100.00	100	1	1	0

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4991

1

T1

8

T2

7

T3

6

auto[1]

564

1

T15

2

T41

3

T42

1

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4991

1

T1

8

T2

7

T3

6

auto[1]

564

1

T15

2

T41

3

T42

1

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4960

1

T1

8

T2

7

T3

6

auto[1]

595

1

T15

2

T40

1

T102

1

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4960

1

T1

8

T2

7

T3

6

auto[1]

595

1

T15

2

T40

1

T102

1

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	427	1			T2	1		T40	1		T102	1
auto[OpGenId]	1177	1			T1	3		T2	3		T3	1
auto[OpGenSwOut]	1226	1			T1	3		T3	1		T13	4
auto[OpGenHwOut]	2635	1			T1	2		T2	3		T3	4
auto[OpDisable]	90	1			T22	1		T6	2		T58	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	427	1			T2	1		T40	1		T102	1
auto[OpGenId]	1177	1			T1	3		T2	3		T3	1
auto[OpGenSwOut]	1226	1			T1	3		T3	1		T13	4
auto[OpGenHwOut]	2635	1			T1	2		T2	3		T3	4
auto[OpDisable]	90	1			T22	1		T6	2		T58	1

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4961

1

T1

8

T2

7

T3

4

auto[1]

594

1

T3

2

T11

4

T22

3

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4961

1

T1

8

T2

7

T3

4

auto[1]

594

1

T3

2

T11

4

T22

3

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5288

1

T1

8

T2

7

T3

6

auto[1]

267

1

T102

2

T41

5

T42

16

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1917	1			T1	3		T2	1		T3	1
auto[1]	717	1			T2	2		T3	2		T11	2
auto[2]	715	1			T1	3		T3	1		T11	2
auto[3]	744	1			T11	1		T13	1		T15	2
auto[4]	372	1			T1	1		T3	1		T11	2
auto[5]	383	1			T1	1		T2	1		T3	1
auto[6]	368	1			T2	1		T40	1		T105	1
auto[7]	339	1			T2	2		T14	1		T23	1

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1462	1			T1	2		T2	4		T3	2
clear_one[1]	717	1			T2	2		T3	2		T11	2
clear_one[2]	715	1			T1	3		T3	1		T11	2
clear_one[3]	744	1			T11	1		T13	1		T15	2
clear_none	1917	1			T1	3		T2	1		T3	1

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1057	1			T1	3		T2	3		T3	1
auto[StInit]	793	1			T1	1		T2	1		T11	1
auto[StCreatorRootKey]	606	1			T1	1		T2	1		T11	1
auto[StOwnerIntKey]	547	1			T2	1		T3	1		T11	1
auto[StOwnerKey]	472	1			T3	1		T11	1		T14	1
auto[StDisabled]	1920	1			T1	3		T2	1		T3	3
auto[StInvalid]	160	1			T39	4		T51	3		T94	6

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1057	1			T1	3		T2	3		T3	1
auto[StInit]	793	1			T1	1		T2	1		T11	1
auto[StCreatorRootKey]	606	1			T1	1		T2	1		T11	1
auto[StOwnerIntKey]	547	1			T2	1		T3	1		T11	1
auto[StOwnerKey]	472	1			T3	1		T11	1		T14	1
auto[StDisabled]	1920	1			T1	3		T2	1		T3	3
auto[StInvalid]	160	1			T39	4		T51	3		T94	6

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	58	222	79.29	58

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[0]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[1] - auto[5]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	5
[auto[1] - auto[5]]	[auto[StReset]]	[auto[OpDisable]]	--	--	5
[auto[1] - auto[5]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	20
[auto[1] - auto[5]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	5
[auto[6]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[6]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[6]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[6]]	[auto[StInvalid]]	[auto[OpAdvance]]	0	1	1
[auto[6]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[7]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[7]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[7]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[7]]	[auto[StInvalid]]	[auto[OpAdvance]]	0	1	1
[auto[7]]	[auto[StInvalid]]	[auto[OpGenHwOut] , auto[OpDisable]]	--	--	2

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpAdvance]	5	1			T132	2		T237	1		T238	1
auto[0]	auto[StReset]	auto[OpGenId]	175	1			T1	2		T22	1		T206	1
auto[0]	auto[StReset]	auto[OpGenSwOut]	172	1			T3	1		T22	1		T42	2
auto[0]	auto[StReset]	auto[OpGenHwOut]	277	1			T2	1		T107	1		T41	1
auto[0]	auto[StInit]	auto[OpAdvance]	54	1			T19	1		T110	1		T6	1
auto[0]	auto[StInit]	auto[OpGenId]	117	1			T48	2		T6	1		T193	1
auto[0]	auto[StInit]	auto[OpGenSwOut]	112	1			T13	1		T15	1		T22	1
auto[0]	auto[StInit]	auto[OpGenHwOut]	191	1			T11	1		T14	1		T22	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	21	1			T40	1		T44	1		T57	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	58	1			T22	1		T6	2		T44	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	43	1			T197	1		T239	1		T53	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	71	1			T129	1		T210	1		T48	1
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	10	1			T132	1		T44	1		T62	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	33	1			T22	1		T6	1		T59	2
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	29	1			T48	1		T61	1		T62	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	51	1			T105	1		T129	1		T210	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	6	1			T122	1		T240	1		T235	1
auto[0]	auto[StOwnerKey]	auto[OpGenId]	32	1			T42	2		T194	1		T44	2
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	25	1			T58	1		T61	1		T204	1
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	53	1			T105	1		T42	1		T129	1
auto[0]	auto[StDisabled]	auto[OpAdvance]	23	1			T133	1		T44	1		T61	1
auto[0]	auto[StDisabled]	auto[OpGenId]	63	1			T133	1		T61	1		T53	1
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	71	1			T1	1		T6	2		T59	1
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	168	1			T210	2		T206	1		T207	1
auto[0]	auto[StDisabled]	auto[OpDisable]	24	1			T6	1		T59	1		T61	1
auto[0]	auto[StInvalid]	auto[OpAdvance]	2	1			T241	1		T242	1		-	-
auto[0]	auto[StInvalid]	auto[OpGenId]	9	1			T51	1		T94	2		T200	1
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	13	1			T201	1		T243	1		T85	1
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	9	1			T201	1		T85	1		T244	1
auto[1]	auto[StReset]	auto[OpGenId]	18	1			T203	1		T53	1		T245	1
auto[1]	auto[StReset]	auto[OpGenSwOut]	17	1			T61	1		T53	1		T121	1
auto[1]	auto[StReset]	auto[OpGenHwOut]	47	1			T39	1		T246	1		T247	1
auto[1]	auto[StInit]	auto[OpAdvance]	14	1			T2	1		T53	1		T95	1
auto[1]	auto[StInit]	auto[OpGenId]	9	1			T206	1		T248	1		T213	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	13	1			T22	1		T90	1		T222	1
auto[1]	auto[StInit]	auto[OpGenHwOut]	26	1			T209	1		T59	1		T249	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	9	1			T198	1		T70	1		T250	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	22	1			T15	1		T24	1		T133	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	12	1			T6	1		T53	1		T68	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	50	1			T22	1		T130	1		T131	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	6	1			T41	2		T59	1		T251	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	16	1			T252	1		T214	1		T127	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	16	1			T6	1		T123	2		T253	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	44	1			T22	1		T207	1		T6	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	6	1			T41	1		T42	1		T254	1
auto[1]	auto[StOwnerKey]	auto[OpGenId]	16	1			T70	1		T255	1		T256	1
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	11	1			T40	1		T107	1		T59	1
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	33	1			T11	1		T59	1		T257	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	21	1			T258	2		T259	1		T74	1
auto[1]	auto[StDisabled]	auto[OpGenId]	58	1			T3	1		T107	2		T102	2
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	51	1			T47	1		T24	1		T48	1
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	164	1			T2	1		T3	1		T11	1
auto[1]	auto[StDisabled]	auto[OpDisable]	15	1			T22	1		T6	1		T61	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	6	1			T186	1		T200	1		T260	1
auto[1]	auto[StInvalid]	auto[OpGenId]	7	1			T85	1		T261	1		T262	1
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	5	1			T186	2		T261	1		T263	1
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	5	1			T39	1		T196	1		T243	1
auto[2]	auto[StReset]	auto[OpGenId]	12	1			T59	1		T44	1		T68	1
auto[2]	auto[StReset]	auto[OpGenSwOut]	21	1			T44	1		T122	1		T264	1
auto[2]	auto[StReset]	auto[OpGenHwOut]	45	1			T130	2		T209	1		T265	1
auto[2]	auto[StInit]	auto[OpAdvance]	7	1			T28	1		T258	1		T266	1
auto[2]	auto[StInit]	auto[OpGenId]	16	1			T267	1		T89	1		T184	1
auto[2]	auto[StInit]	auto[OpGenSwOut]	20	1			T6	1		T53	1		T268	1
auto[2]	auto[StInit]	auto[OpGenHwOut]	29	1			T1	1		T21	1		T6	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	5	1			T269	1		T258	1		T74	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	15	1			T132	1		T59	1		T44	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	24	1			T101	1		T6	1		T44	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	32	1			T1	1		T105	1		T270	1
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T271	1		T73	1		T272	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	16	1			T102	1		T198	1		T44	2
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	17	1			T102	1		T59	1		T202	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	45	1			T3	1		T11	1		T14	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	7	1			T141	1		T203	1		T273	1
auto[2]	auto[StOwnerKey]	auto[OpGenId]	9	1			T62	1		T74	1		T274	1
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	14	1			T62	1		T123	1		T258	4
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	38	1			T14	1		T131	1		T48	1
auto[2]	auto[StDisabled]	auto[OpAdvance]	25	1			T41	1		T23	1		T133	1
auto[2]	auto[StDisabled]	auto[OpGenId]	39	1			T1	1		T102	1		T6	1
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	63	1			T15	1		T22	1		T41	2
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	173	1			T11	1		T14	3		T41	1
auto[2]	auto[StDisabled]	auto[OpDisable]	8	1			T59	1		T46	1		T234	1
auto[2]	auto[StInvalid]	auto[OpAdvance]	4	1			T39	1		T200	1		T85	1
auto[2]	auto[StInvalid]	auto[OpGenId]	7	1			T39	1		T196	1		T208	1
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	13	1			T94	1		T199	1		T196	1
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	7	1			T243	1		T266	1		T275	2
auto[3]	auto[StReset]	auto[OpGenId]	24	1			T6	2		T53	1		T62	1
auto[3]	auto[StReset]	auto[OpGenSwOut]	19	1			T264	1		T245	1		T187	1
auto[3]	auto[StReset]	auto[OpGenHwOut]	38	1			T130	1		T59	1		T276	1
auto[3]	auto[StInit]	auto[OpAdvance]	10	1			T89	1		T277	1		T278	1
auto[3]	auto[StInit]	auto[OpGenId]	12	1			T203	1		T267	1		T279	2
auto[3]	auto[StInit]	auto[OpGenSwOut]	17	1			T21	1		T59	1		T264	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	28	1			T19	1		T62	1		T247	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	6	1			T234	1		T280	1		T281	2
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	17	1			T47	1		T48	1		T58	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	21	1			T193	1		T62	1		T282	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	45	1			T11	1		T283	1		T284	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	12	1			T285	1		T286	1		T227	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	17	1			T6	1		T44	1		T61	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	13	1			T44	1		T270	1		T237	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	40	1			T283	1		T284	1		T237	2
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	6	1			T6	1		T53	1		T287	1
auto[3]	auto[StOwnerKey]	auto[OpGenId]	14	1			T44	1		T270	1		T288	1
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	19	1			T15	1		T198	1		T44	1
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	41	1			T130	1		T207	1		T209	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	22	1			T6	1		T289	1		T290	1
auto[3]	auto[StDisabled]	auto[OpGenId]	62	1			T22	2		T107	1		T101	1
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	74	1			T13	1		T23	1		T193	1
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	152	1			T15	1		T105	1		T129	1
auto[3]	auto[StDisabled]	auto[OpDisable]	14	1			T58	1		T44	1		T62	2
auto[3]	auto[StInvalid]	auto[OpAdvance]	2	1			T87	1		T291	1		-	-
auto[3]	auto[StInvalid]	auto[OpGenId]	5	1			T208	1		T244	1		T292	1
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	8	1			T199	1		T186	1		T275	1
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	6	1			T94	1		T261	1		T244	1
auto[4]	auto[StReset]	auto[OpGenId]	9	1			T42	1		T24	1		T53	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	12	1			T293	1		T294	1		T220	1
auto[4]	auto[StReset]	auto[OpGenHwOut]	20	1			T47	1		T295	1		T214	1
auto[4]	auto[StInit]	auto[OpAdvance]	7	1			T45	1		T296	1		T297	2
auto[4]	auto[StInit]	auto[OpGenId]	3	1			T298	1		T256	1		T299	1
auto[4]	auto[StInit]	auto[OpGenSwOut]	11	1			T44	1		T53	1		T89	1
auto[4]	auto[StInit]	auto[OpGenHwOut]	12	1			T300	1		T301	1		T295	1
auto[4]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T45	1		T302	1		T93	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	7	1			T123	1		T68	1		T219	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	7	1			T211	1		T69	1		T303	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	22	1			T6	1		T265	1		T61	1
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	6	1			T44	1		T288	1		T96	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	10	1			T23	1		T53	1		T122	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	7	1			T6	2		T234	1		T304	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	19	1			T62	1		T305	1		T306	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T62	1		T96	1		T307	1
auto[4]	auto[StOwnerKey]	auto[OpGenId]	4	1			T45	1		T308	1		T309	1
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	3	1			T61	1		T310	1		T311	1
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	21	1			T3	1		T210	1		T312	1
auto[4]	auto[StDisabled]	auto[OpAdvance]	14	1			T102	1		T42	1		T44	1
auto[4]	auto[StDisabled]	auto[OpGenId]	27	1			T6	2		T59	1		T96	1
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	31	1			T1	1		T13	2		T22	1
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	85	1			T11	2		T14	1		T42	2
auto[4]	auto[StDisabled]	auto[OpDisable]	6	1			T214	1		T177	1		T313	1
auto[4]	auto[StInvalid]	auto[OpAdvance]	4	1			T94	1		T314	1		T87	2
auto[4]	auto[StInvalid]	auto[OpGenId]	3	1			T244	1		T241	1		T262	1
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	5	1			T208	1		T262	1		T242	1
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	10	1			T186	2		T200	1		T315	1
auto[5]	auto[StReset]	auto[OpGenId]	14	1			T2	1		T22	1		T68	2
auto[5]	auto[StReset]	auto[OpGenSwOut]	16	1			T1	1		T6	1		T44	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	26	1			T6	2		T316	1		T317	1
auto[5]	auto[StInit]	auto[OpAdvance]	4	1			T42	1		T318	1		T225	1
auto[5]	auto[StInit]	auto[OpGenId]	10	1			T19	1		T42	1		T90	1
auto[5]	auto[StInit]	auto[OpGenSwOut]	5	1			T319	1		T68	1		T307	1
auto[5]	auto[StInit]	auto[OpGenHwOut]	15	1			T42	2		T62	1		T320	1
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	2	1			T59	1		T68	1		-	-
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	11	1			T44	1		T62	1		T219	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	11	1			T107	1		T42	2		T59	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	16	1			T42	1		T312	1		T321	1
auto[5]	auto[StOwnerIntKey]	auto[OpAdvance]	7	1			T132	1		T62	1		T122	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	5	1			T70	1		T192	1		T322	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	6	1			T42	2		T133	1		T53	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	21	1			T65	1		T6	1		T317	1
auto[5]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T132	1		T323	1		T250	1
auto[5]	auto[StOwnerKey]	auto[OpGenId]	6	1			T110	1		T53	1		T73	1
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	4	1			T324	1		T325	1		T326	1
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	21	1			T269	1		T249	1		T247	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	15	1			T132	1		T269	1		T53	1
auto[5]	auto[StDisabled]	auto[OpGenId]	17	1			T59	1		T202	1		T53	1
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	42	1			T59	1		T53	1		T62	1
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	82	1			T3	1		T15	1		T40	1
auto[5]	auto[StDisabled]	auto[OpDisable]	10	1			T61	1		T327	1		T72	1
auto[5]	auto[StInvalid]	auto[OpAdvance]	1	1			T328	1		-	-		-	-
auto[5]	auto[StInvalid]	auto[OpGenId]	3	1			T328	1		T292	2		-	-
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	2	1			T291	2		-	-		-	-
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	6	1			T94	1		T266	1		T261	1
auto[6]	auto[StReset]	auto[OpGenId]	7	1			T44	1		T51	1		T121	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	8	1			T62	1		T264	1		T329	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	32	1			T2	1		T48	1		T330	2
auto[6]	auto[StInit]	auto[OpAdvance]	4	1			T214	1		T86	1		T331	1
auto[6]	auto[StInit]	auto[OpGenId]	7	1			T69	1		T234	1		T76	1
auto[6]	auto[StInit]	auto[OpGenSwOut]	5	1			T97	1		T74	1		T49	1
auto[6]	auto[StInit]	auto[OpGenHwOut]	10	1			T332	1		T319	1		T333	1
auto[6]	auto[StCreatorRootKey]	auto[OpAdvance]	5	1			T53	1		T334	1		T335	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	9	1			T59	1		T289	1		T336	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	6	1			T214	1		T74	1		T337	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	20	1			T41	1		T338	1		T330	1
auto[6]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T101	1		T339	1		T340	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	10	1			T61	1		T68	1		T256	2
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	7	1			T61	1		T134	1		T268	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	27	1			T130	1		T131	1		T61	1
auto[6]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T48	1		T193	1		T62	1
auto[6]	auto[StOwnerKey]	auto[OpGenId]	9	1			T237	1		T341	1		T342	1
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	6	1			T205	1		T237	1		T73	1
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	20	1			T59	1		T134	4		T237	2
auto[6]	auto[StDisabled]	auto[OpAdvance]	23	1			T67	1		T214	2		T343	1
auto[6]	auto[StDisabled]	auto[OpGenId]	26	1			T40	1		T6	1		T202	1
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	29	1			T62	1		T122	1		T245	1
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	75	1			T105	1		T129	3		T130	1
auto[6]	auto[StDisabled]	auto[OpDisable]	5	1			T59	1		T214	1		T192	1
auto[6]	auto[StInvalid]	auto[OpGenId]	6	1			T39	1		T196	1		T266	1
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	3	1			T328	1		T344	2		-	-
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	2	1			T314	1		T345	1		-	-
auto[7]	auto[StReset]	auto[OpGenId]	13	1			T186	1		T79	1		T81	1
auto[7]	auto[StReset]	auto[OpGenSwOut]	9	1			T333	1		T266	1		T346	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	21	1			T59	1		T316	1		T320	1
auto[7]	auto[StInit]	auto[OpAdvance]	3	1			T299	1		T347	1		T348	1
auto[7]	auto[StInit]	auto[OpGenId]	6	1			T349	1		T294	1		T350	1
auto[7]	auto[StInit]	auto[OpGenSwOut]	6	1			T214	2		T70	1		T192	1
auto[7]	auto[StInit]	auto[OpGenHwOut]	10	1			T6	2		T343	1		T351	1
auto[7]	auto[StCreatorRootKey]	auto[OpAdvance]	2	1			T23	1		T352	1		-	-
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	7	1			T2	1		T277	1		T220	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	9	1			T202	1		T122	1		T253	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	18	1			T14	1		T209	1		T257	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T353	1		T214	1		T282	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	10	1			T2	1		T6	1		T58	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	14	1			T67	1		T290	1		T303	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	22	1			T354	1		T226	1		T355	1
auto[7]	auto[StOwnerKey]	auto[OpAdvance]	1	1			T30	1		-	-		-	-
auto[7]	auto[StOwnerKey]	auto[OpGenId]	9	1			T123	1		T83	1		T49	1
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	2	1			T343	1		T356	1		-	-
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	23	1			T284	1		T305	1		T357	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	13	1			T219	1		T220	1		T259	1
auto[7]	auto[StDisabled]	auto[OpGenId]	26	1			T358	1		T61	1		T62	1
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	25	1			T58	1		T270	1		T122	2
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	71	1			T207	1		T6	1		T59	1
auto[7]	auto[StDisabled]	auto[OpDisable]	8	1			T44	1		T53	1		T68	1
auto[7]	auto[StInvalid]	auto[OpGenId]	5	1			T51	2		T331	1		T345	1
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	2	1			T331	1		T345	1		-	-

---

Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1462

1

T1

2

T2

4

T3

2

clear_one[1]

auto[0]

auto[0]

auto[0]

409

1

T2

2

T3

1

T15

1

clear_one[1]

auto[0]

auto[0]

auto[1]

126

1

T3

1

T11

2

T22

2

clear_one[1]

auto[0]

auto[1]

auto[0]

138

1

T40

1

T42

6

T131

1

clear_one[1]

auto[0]

auto[1]

auto[1]

44

1

T102

1

T24

1

T48

1

clear_one[2]

auto[0]

auto[0]

auto[0]

420

1

T1

3

T14

5

T22

1

clear_one[2]

auto[0]

auto[0]

auto[1]

129

1

T3

1

T11

2

T105

1

clear_one[2]

auto[1]

auto[0]

auto[0]

127

1

T15

1

T41

3

T130

1

clear_one[2]

auto[1]

auto[0]

auto[1]

39

1

T23

1

T59

1

T141

1

clear_one[3]

auto[0]

auto[0]

auto[0]

431

1

T11

1

T13

1

T22

2

clear_one[3]

auto[0]

auto[1]

auto[0]

140

1

T15

1

T129

1

T131

1

clear_one[3]

auto[1]

auto[0]

auto[0]

120

1

T130

1

T207

1

T270

2

clear_one[3]

auto[1]

auto[1]

auto[0]

53

1

T15

1

T101

1

T23

1

clear_none

auto[0]

auto[0]

auto[0]

1379

1

T1

3

T2

1

T3

1

clear_none

auto[0]

auto[0]

auto[1]

159

1

T22

1

T105

2

T210

4

clear_none

auto[0]

auto[1]

auto[0]

124

1

T129

3

T206

1

T6

4

clear_none

auto[0]

auto[1]

auto[1]

30

1

T59

2

T44

1

T53

1

clear_none

auto[1]

auto[0]

auto[0]

122

1

T207

1

T6

1

T59

1

clear_none

auto[1]

auto[0]

auto[1]

37

1

T59

2

T62

1

T359

2

clear_none

auto[1]

auto[1]

auto[0]

36

1

T42

1

T6

2

T141

1

clear_none

auto[1]

auto[1]

auto[1]

30

1

T53

1

T360

1

T333

3

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1382	1			T1	2		T2	4		T3	2
clear_all	auto[1]	80	1			T42	9		T132	6		T134	3
clear_one[1]	auto[0]	682	1			T2	2		T3	2		T11	2
clear_one[1]	auto[1]	35	1			T102	1		T41	2		T42	5
clear_one[2]	auto[0]	675	1			T1	3		T3	1		T11	2
clear_one[2]	auto[1]	40	1			T102	1		T41	3		T141	1
clear_one[3]	auto[0]	697	1			T11	1		T13	1		T15	2
clear_one[3]	auto[1]	47	1			T237	2		T360	6		T290	6
clear_none	auto[0]	1852	1			T1	3		T2	1		T3	1
clear_none	auto[1]	65	1			T42	2		T132	2		T133	1