Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
43.16	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	360	216	144	40.00

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	168	112	40.00	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

12144

1

T1

19

T2

18

T3

6

auto[Attestation]

8642

1

T1

13

T2

6

T3

4

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	3123	1			T1	4		T2	1		T3	1
auto[Aes]	3646	1			T1	6		T2	6		T3	1
auto[Kmac]	3788	1			T1	6		T2	4		T3	2
auto[Otbn]	3659	1			T1	6		T2	2		T3	4

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	8426	1			T1	8		T2	8		T3	8
auto[OpGenId]	6570	1			T1	10		T2	11		T3	2
auto[OpGenSwOut]	6627	1			T1	13		T2	5		T3	3
auto[OpGenHwOut]	7589	1			T1	9		T2	8		T3	5
auto[OpDisable]	164	1			T22	1		T47	1		T48	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

11195

1

T1

13

T2

13

T3

8

auto[OpDoneFail]

18181

1

T1

27

T2

19

T3

10

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6684	1			T1	11		T2	13		T3	3
auto[StInit]	4631	1			T1	3		T2	1		T3	2
auto[StCreatorRootKey]	3434	1			T1	6		T2	6		T3	2
auto[StOwnerIntKey]	2944	1			T1	3		T2	3		T3	2
auto[StOwnerKey]	2545	1			T1	2		T2	3		T3	2
auto[StDisabled]	8118	1			T1	15		T2	6		T3	7
auto[StInvalid]	1020	1			T39	26		T51	36		T94	27

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	168	112	40.00	168

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	360	1			T15	2		T106	2		T21	3
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	132	1			T22	2		T19	1		T132	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	83	1			T102	1		T24	1		T34	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	76	1			T13	1		T22	1		T48	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	66	1			T48	1		T38	1		T59	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	202	1			T13	1		T16	1		T22	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	33	1			T51	1		T94	1		T196	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	323	1			T1	1		T15	1		T22	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	126	1			T13	1		T19	1		T197	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	78	1			T33	1		T197	1		T6	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	76	1			T22	1		T198	1		T44	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	75	1			T15	1		T109	1		T23	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	239	1			T1	2		T12	1		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	29	1			T39	1		T199	2		T200	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	350	1			T1	1		T2	3		T3	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	122	1			T19	1		T21	1		T6	3
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	84	1			T101	1		T48	1		T6	4
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	80	1			T1	1		T12	1		T106	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	74	1			T16	1		T108	1		T6	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	219	1			T2	1		T12	1		T102	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	42	1			T39	2		T94	1		T201	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	344	1			T1	2		T106	2		T108	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	126	1			T21	2		T6	1		T39	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	99	1			T106	1		T197	1		T48	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	74	1			T16	1		T108	1		T110	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	80	1			T22	1		T59	1		T202	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	223	1			T22	1		T40	1		T102	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	38	1			T51	1		T94	2		T201	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	84	1			T48	3		T6	1		T59	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	143	1			T41	1		T101	1		T23	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	94	1			T3	1		T65	1		T48	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	61	1			T48	1		T6	1		T133	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	65	1			T13	1		T40	1		T110	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	217	1			T16	1		T109	1		T41	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	38	1			T51	3		T94	1		T201	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	74	1			T48	1		T6	2		T59	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	112	1			T12	1		T22	1		T102	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	109	1			T16	1		T110	3		T6	4
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	73	1			T203	1		T62	1		T204	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	63	1			T2	1		T12	1		T198	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	229	1			T1	3		T13	2		T47	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	36	1			T39	4		T94	1		T201	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	74	1			T48	2		T6	4		T59	3
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	128	1			T15	1		T22	1		T19	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	104	1			T34	1		T6	2		T44	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	73	1			T23	1		T24	1		T48	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	59	1			T107	1		T48	1		T205	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	229	1			T1	1		T15	1		T40	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	27	1			T51	2		T201	1		T199	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	76	1			T48	3		T6	1		T59	4
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	133	1			T19	3		T32	1		T20	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	81	1			T107	1		T65	1		T42	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	84	1			T102	1		T41	1		T47	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	59	1			T1	1		T40	1		T59	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	221	1			T1	1		T16	1		T22	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	28	1			T201	4		T199	1		T200	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	301	1			T2	1		T15	1		T22	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	128	1			T102	1		T19	1		T21	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	87	1			T1	2		T24	1		T33	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	69	1			T22	1		T206	1		T6	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	62	1			T65	1		T101	1		T44	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	204	1			T40	1		T102	2		T41	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	31	1			T39	1		T94	2		T201	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	445	1			T2	2		T15	1		T22	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	145	1			T40	1		T19	2		T130	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	114	1			T41	1		T207	1		T6	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	91	1			T130	1		T23	1		T32	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	87	1			T2	1		T101	1		T23	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	277	1			T3	1		T15	1		T41	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	28	1			T39	2		T51	2		T196	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	524	1			T1	2		T15	1		T22	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	161	1			T129	1		T24	1		T20	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	108	1			T129	1		T132	1		T34	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	96	1			T14	1		T131	1		T198	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	101	1			T14	1		T101	1		T197	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	273	1			T1	1		T13	1		T15	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	28	1			T39	1		T199	1		T208	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	430	1			T1	1		T2	1		T22	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	129	1			T1	1		T3	1		T11	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	113	1			T13	1		T102	1		T32	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	113	1			T3	1		T11	1		T105	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	82	1			T3	1		T209	1		T59	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	264	1			T11	2		T40	1		T105	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	31	1			T51	2		T200	1		T208	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	47	1			T6	3		T59	2		T44	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	121	1			T22	1		T19	1		T6	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	69	1			T1	1		T41	1		T42	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	67	1			T40	1		T110	1		T48	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	55	1			T24	1		T48	1		T59	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	195	1			T1	1		T40	1		T102	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	33	1			T94	1		T199	1		T186	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	67	1			T6	3		T59	4		T44	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	127	1			T42	2		T101	1		T198	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	131	1			T130	1		T6	3		T38	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	99	1			T2	1		T65	1		T6	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	82	1			T42	1		T130	1		T207	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	273	1			T2	1		T15	1		T22	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	38	1			T51	2		T94	2		T201	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	51	1			T48	1		T6	3		T39	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	141	1			T14	1		T19	4		T131	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	119	1			T14	1		T131	1		T193	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	108	1			T15	1		T129	1		T32	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	86	1			T40	1		T42	1		T129	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	307	1			T14	4		T41	1		T42	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	20	1			T51	2		T94	1		T208	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	41	1			T6	3		T39	1		T59	3
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	150	1			T22	2		T105	1		T19	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	110	1			T2	1		T11	1		T22	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	99	1			T210	1		T209	1		T6	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	98	1			T11	1		T105	1		T210	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	307	1			T3	1		T11	2		T40	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	26	1			T39	1		T94	1		T201	1

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	208	1			T13	1		T22	1		T102	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	744	1			T13	1		T15	2		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	207	1			T15	1		T22	1		T109	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	739	1			T1	3		T12	1		T13	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	214	1			T1	1		T12	1		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	757	1			T1	1		T2	4		T3	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	229	1			T16	1		T22	1		T106	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	755	1			T1	2		T22	1		T40	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	199	1			T3	1		T13	1		T40	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	503	1			T16	1		T109	1		T41	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	225	1			T2	1		T12	1		T16	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	471	1			T1	3		T12	1		T13	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	214	1			T107	1		T23	1		T34	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	480	1			T1	1		T15	2		T22	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	206	1			T1	1		T40	1		T107	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	476	1			T1	1		T16	1		T22	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	195	1			T1	2		T22	1		T65	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	687	1			T2	1		T15	1		T22	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	274	1			T2	1		T41	1		T101	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	913	1			T2	2		T3	1		T15	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	288	1			T14	2		T129	1		T101	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	1003	1			T1	3		T13	1		T15	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	289	1			T3	2		T11	1		T13	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	873	1			T1	2		T2	1		T3	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	167	1			T1	1		T40	1		T41	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	420	1			T1	1		T22	1		T40	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	288	1			T2	1		T65	1		T42	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	529	1			T2	1		T15	1		T22	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	295	1			T14	1		T15	1		T40	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	537	1			T14	5		T19	4		T41	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	288	1			T2	1		T11	2		T22	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	543	1			T3	1		T11	2		T22	2