Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

33717

1

T1

46

T2

35

T3

23

auto[1]

297

1

T102

3

T41

4

T42

19

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	1	31	96.88

Automatically Generated Bins for sw_input_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
[auto[2281701376:2415919103]]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	33726	1			T1	46		T2	35		T3	23
auto[134217728:268435455]	7	1			T373	1		T318	1		T386	1
auto[268435456:402653183]	9	1			T102	1		T42	1		T373	1
auto[402653184:536870911]	10	1			T42	1		T239	1		T360	1
auto[536870912:671088639]	8	1			T42	1		T132	1		T133	1
auto[671088640:805306367]	5	1			T42	1		T132	1		T237	1
auto[805306368:939524095]	11	1			T42	2		T132	1		T302	2
auto[939524096:1073741823]	13	1			T42	1		T141	1		T134	1
auto[1073741824:1207959551]	12	1			T237	1		T360	3		T334	2
auto[1207959552:1342177279]	11	1			T102	1		T42	1		T371	1
auto[1342177280:1476395007]	11	1			T42	1		T279	1		T373	2
auto[1476395008:1610612735]	10	1			T42	1		T132	1		T374	1
auto[1610612736:1744830463]	10	1			T42	1		T374	1		T373	1
auto[1744830464:1879048191]	14	1			T42	1		T132	1		T290	1
auto[1879048192:2013265919]	7	1			T42	1		T132	1		T141	1
auto[2013265920:2147483647]	12	1			T41	1		T42	1		T290	1
auto[2147483648:2281701375]	9	1			T132	1		T141	1		T360	2
auto[2415919104:2550136831]	13	1			T42	1		T290	1		T279	1
auto[2550136832:2684354559]	9	1			T133	1		T134	1		T387	1
auto[2684354560:2818572287]	8	1			T237	1		T258	1		T373	1
auto[2818572288:2952790015]	8	1			T237	1		T290	1		T297	1
auto[2952790016:3087007743]	10	1			T41	1		T42	1		T360	1
auto[3087007744:3221225471]	17	1			T42	2		T132	1		T360	1
auto[3221225472:3355443199]	4	1			T132	1		T258	1		T388	1
auto[3355443200:3489660927]	11	1			T41	1		T141	2		T360	1
auto[3489660928:3623878655]	10	1			T134	1		T237	1		T373	1
auto[3623878656:3758096383]	12	1			T132	1		T290	1		T279	1
auto[3758096384:3892314111]	6	1			T360	1		T389	1		T390	2
auto[3892314112:4026531839]	8	1			T102	1		T360	1		T290	1
auto[4026531840:4160749567]	7	1			T371	1		T297	1		T388	1
auto[4160749568:4294967295]	6	1			T42	1		T290	1		T386	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	32	32	50.00	32

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Element holes

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[2281701376:2415919103]]	*	--	--	2

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[2147483648:2281701375]]	[auto[0]]	--	--	16
[auto[2415919104:2550136831] - auto[4160749568:4294967295]]	[auto[0]]	--	--	14

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	33717	1			T1	46		T2	35		T3	23
auto[0:134217727]	auto[1]	9	1			T41	1		T360	1		T373	1
auto[134217728:268435455]	auto[1]	7	1			T373	1		T318	1		T386	1
auto[268435456:402653183]	auto[1]	9	1			T102	1		T42	1		T373	1
auto[402653184:536870911]	auto[1]	10	1			T42	1		T239	1		T360	1
auto[536870912:671088639]	auto[1]	8	1			T42	1		T132	1		T133	1
auto[671088640:805306367]	auto[1]	5	1			T42	1		T132	1		T237	1
auto[805306368:939524095]	auto[1]	11	1			T42	2		T132	1		T302	2
auto[939524096:1073741823]	auto[1]	13	1			T42	1		T141	1		T134	1
auto[1073741824:1207959551]	auto[1]	12	1			T237	1		T360	3		T334	2
auto[1207959552:1342177279]	auto[1]	11	1			T102	1		T42	1		T371	1
auto[1342177280:1476395007]	auto[1]	11	1			T42	1		T279	1		T373	2
auto[1476395008:1610612735]	auto[1]	10	1			T42	1		T132	1		T374	1
auto[1610612736:1744830463]	auto[1]	10	1			T42	1		T374	1		T373	1
auto[1744830464:1879048191]	auto[1]	14	1			T42	1		T132	1		T290	1
auto[1879048192:2013265919]	auto[1]	7	1			T42	1		T132	1		T141	1
auto[2013265920:2147483647]	auto[1]	12	1			T41	1		T42	1		T290	1
auto[2147483648:2281701375]	auto[1]	9	1			T132	1		T141	1		T360	2
auto[2415919104:2550136831]	auto[1]	13	1			T42	1		T290	1		T279	1
auto[2550136832:2684354559]	auto[1]	9	1			T133	1		T134	1		T387	1
auto[2684354560:2818572287]	auto[1]	8	1			T237	1		T258	1		T373	1
auto[2818572288:2952790015]	auto[1]	8	1			T237	1		T290	1		T297	1
auto[2952790016:3087007743]	auto[1]	10	1			T41	1		T42	1		T360	1
auto[3087007744:3221225471]	auto[1]	17	1			T42	2		T132	1		T360	1
auto[3221225472:3355443199]	auto[1]	4	1			T132	1		T258	1		T388	1
auto[3355443200:3489660927]	auto[1]	11	1			T41	1		T141	2		T360	1
auto[3489660928:3623878655]	auto[1]	10	1			T134	1		T237	1		T373	1
auto[3623878656:3758096383]	auto[1]	12	1			T132	1		T290	1		T279	1
auto[3758096384:3892314111]	auto[1]	6	1			T360	1		T389	1		T390	2
auto[3892314112:4026531839]	auto[1]	8	1			T102	1		T360	1		T290	1
auto[4026531840:4160749567]	auto[1]	7	1			T371	1		T297	1		T388	1
auto[4160749568:4294967295]	auto[1]	6	1			T42	1		T290	1		T386	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1680

1

T1

2

T2

2

T22

5

auto[1]

1920

1

T1

3

T2

2

T22

6

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	96	1			T101	1		T24	1		T6	1
auto[134217728:268435455]	111	1			T42	1		T101	1		T110	1
auto[268435456:402653183]	132	1			T41	1		T65	1		T6	5
auto[402653184:536870911]	118	1			T65	1		T23	1		T20	1
auto[536870912:671088639]	123	1			T1	1		T2	1		T22	2
auto[671088640:805306367]	117	1			T40	1		T42	2		T21	1
auto[805306368:939524095]	101	1			T42	1		T48	1		T6	1
auto[939524096:1073741823]	123	1			T19	1		T133	1		T59	1
auto[1073741824:1207959551]	113	1			T1	1		T22	1		T102	1
auto[1207959552:1342177279]	127	1			T2	1		T42	1		T24	2
auto[1342177280:1476395007]	112	1			T198	1		T48	1		T6	3
auto[1476395008:1610612735]	116	1			T22	1		T23	1		T133	1
auto[1610612736:1744830463]	122	1			T41	1		T132	1		T24	1
auto[1744830464:1879048191]	116	1			T22	2		T197	1		T6	3
auto[1879048192:2013265919]	115	1			T31	1		T42	1		T6	3
auto[2013265920:2147483647]	120	1			T22	1		T24	1		T6	2
auto[2147483648:2281701375]	117	1			T42	1		T132	1		T198	1
auto[2281701376:2415919103]	129	1			T101	1		T198	1		T48	1
auto[2415919104:2550136831]	105	1			T6	2		T54	1		T58	1
auto[2550136832:2684354559]	113	1			T22	2		T41	1		T48	1
auto[2684354560:2818572287]	96	1			T1	1		T132	1		T48	1
auto[2818572288:2952790015]	82	1			T48	1		T6	3		T39	1
auto[2952790016:3087007743]	112	1			T1	2		T102	1		T41	1
auto[3087007744:3221225471]	114	1			T198	1		T48	1		T6	1
auto[3221225472:3355443199]	101	1			T22	1		T19	1		T101	1
auto[3355443200:3489660927]	106	1			T102	1		T65	1		T47	1
auto[3489660928:3623878655]	104	1			T47	1		T6	4		T193	2
auto[3623878656:3758096383]	104	1			T2	1		T40	1		T42	1
auto[3758096384:3892314111]	121	1			T2	1		T102	1		T65	1
auto[3892314112:4026531839]	108	1			T19	1		T41	1		T65	1
auto[4026531840:4160749567]	110	1			T47	1		T6	2		T39	1
auto[4160749568:4294967295]	116	1			T22	1		T20	1		T6	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	48	1			T193	1		T61	1		T7	1
auto[0:134217727]	auto[1]	48	1			T101	1		T24	1		T6	1
auto[134217728:268435455]	auto[0]	59	1			T42	1		T44	1		T97	1
auto[134217728:268435455]	auto[1]	52	1			T101	1		T110	1		T6	1
auto[268435456:402653183]	auto[0]	58	1			T6	1		T53	1		T88	1
auto[268435456:402653183]	auto[1]	74	1			T41	1		T65	1		T6	4
auto[402653184:536870911]	auto[0]	54	1			T20	1		T54	1		T59	1
auto[402653184:536870911]	auto[1]	64	1			T65	1		T23	1		T6	1
auto[536870912:671088639]	auto[0]	56	1			T2	1		T22	1		T40	1
auto[536870912:671088639]	auto[1]	67	1			T1	1		T22	1		T44	1
auto[671088640:805306367]	auto[0]	46	1			T40	1		T21	1		T44	1
auto[671088640:805306367]	auto[1]	71	1			T42	2		T133	1		T59	3
auto[805306368:939524095]	auto[0]	50	1			T42	1		T6	1		T44	1
auto[805306368:939524095]	auto[1]	51	1			T48	1		T43	1		T59	1
auto[939524096:1073741823]	auto[0]	59	1			T61	1		T53	1		T62	2
auto[939524096:1073741823]	auto[1]	64	1			T19	1		T133	1		T59	1
auto[1073741824:1207959551]	auto[0]	64	1			T22	1		T20	1		T6	2
auto[1073741824:1207959551]	auto[1]	49	1			T1	1		T102	1		T6	1
auto[1207959552:1342177279]	auto[0]	59	1			T42	1		T24	2		T21	1
auto[1207959552:1342177279]	auto[1]	68	1			T2	1		T48	1		T58	1
auto[1342177280:1476395007]	auto[0]	49	1			T48	1		T6	1		T62	1
auto[1342177280:1476395007]	auto[1]	63	1			T198	1		T6	2		T25	1
auto[1476395008:1610612735]	auto[0]	54	1			T23	1		T39	1		T44	1
auto[1476395008:1610612735]	auto[1]	62	1			T22	1		T133	1		T194	1
auto[1610612736:1744830463]	auto[0]	42	1			T132	1		T6	1		T193	1
auto[1610612736:1744830463]	auto[1]	80	1			T41	1		T24	1		T133	1
auto[1744830464:1879048191]	auto[0]	52	1			T22	2		T6	3		T61	2
auto[1744830464:1879048191]	auto[1]	64	1			T197	1		T39	1		T202	1
auto[1879048192:2013265919]	auto[0]	52	1			T6	2		T52	1		T288	1
auto[1879048192:2013265919]	auto[1]	63	1			T31	1		T42	1		T6	1
auto[2013265920:2147483647]	auto[0]	51	1			T44	1		T57	1		T53	1
auto[2013265920:2147483647]	auto[1]	69	1			T22	1		T24	1		T6	2
auto[2147483648:2281701375]	auto[0]	60	1			T42	1		T198	1		T21	1
auto[2147483648:2281701375]	auto[1]	57	1			T132	1		T6	1		T59	1
auto[2281701376:2415919103]	auto[0]	65	1			T54	1		T59	1		T53	1
auto[2281701376:2415919103]	auto[1]	64	1			T101	1		T198	1		T48	1
auto[2415919104:2550136831]	auto[0]	47	1			T44	1		T288	1		T61	1
auto[2415919104:2550136831]	auto[1]	58	1			T6	2		T54	1		T58	1
auto[2550136832:2684354559]	auto[0]	53	1			T22	1		T6	1		T193	1
auto[2550136832:2684354559]	auto[1]	60	1			T22	1		T41	1		T48	1
auto[2684354560:2818572287]	auto[0]	34	1			T193	1		T39	1		T44	1
auto[2684354560:2818572287]	auto[1]	62	1			T1	1		T132	1		T48	1
auto[2818572288:2952790015]	auto[0]	39	1			T6	2		T59	1		T201	1
auto[2818572288:2952790015]	auto[1]	43	1			T48	1		T6	1		T39	1
auto[2952790016:3087007743]	auto[0]	64	1			T1	2		T41	1		T48	1
auto[2952790016:3087007743]	auto[1]	48	1			T102	1		T6	1		T59	2
auto[3087007744:3221225471]	auto[0]	49	1			T269	1		T141	1		T53	1
auto[3087007744:3221225471]	auto[1]	65	1			T198	1		T48	1		T6	1
auto[3221225472:3355443199]	auto[0]	54	1			T19	1		T110	1		T6	2
auto[3221225472:3355443199]	auto[1]	47	1			T22	1		T101	1		T198	1
auto[3355443200:3489660927]	auto[0]	46	1			T65	1		T47	1		T6	1
auto[3355443200:3489660927]	auto[1]	60	1			T102	1		T23	1		T197	1
auto[3489660928:3623878655]	auto[0]	61	1			T6	3		T193	1		T59	1
auto[3489660928:3623878655]	auto[1]	43	1			T47	1		T6	1		T193	1
auto[3623878656:3758096383]	auto[0]	49	1			T40	1		T42	1		T193	1
auto[3623878656:3758096383]	auto[1]	55	1			T2	1		T6	2		T61	2
auto[3758096384:3892314111]	auto[0]	47	1			T2	1		T6	2		T54	1
auto[3758096384:3892314111]	auto[1]	74	1			T102	1		T65	1		T47	1
auto[3892314112:4026531839]	auto[0]	48	1			T41	1		T65	1		T6	2
auto[3892314112:4026531839]	auto[1]	60	1			T19	1		T6	3		T59	1
auto[4026531840:4160749567]	auto[0]	49	1			T47	1		T6	1		T59	1
auto[4026531840:4160749567]	auto[1]	61	1			T6	1		T39	1		T44	1
auto[4160749568:4294967295]	auto[0]	62	1			T20	1		T6	1		T59	1
auto[4160749568:4294967295]	auto[1]	54	1			T22	1		T53	1		T62	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1683

1

T1

1

T2

2

T22

6

auto[1]

1917

1

T1

4

T2

2

T22

5

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	105	1			T40	1		T24	1		T48	1
auto[134217728:268435455]	102	1			T65	1		T20	1		T6	6
auto[268435456:402653183]	120	1			T22	1		T102	1		T42	2
auto[402653184:536870911]	118	1			T31	1		T23	1		T132	1
auto[536870912:671088639]	136	1			T22	2		T47	1		T48	1
auto[671088640:805306367]	123	1			T48	1		T6	3		T193	1
auto[805306368:939524095]	133	1			T40	1		T41	1		T47	2
auto[939524096:1073741823]	113	1			T102	1		T101	1		T6	1
auto[1073741824:1207959551]	100	1			T1	1		T42	1		T6	1
auto[1207959552:1342177279]	109	1			T1	1		T22	1		T42	1
auto[1342177280:1476395007]	121	1			T1	1		T19	1		T42	1
auto[1476395008:1610612735]	108	1			T65	1		T110	1		T193	1
auto[1610612736:1744830463]	115	1			T22	1		T23	1		T133	1
auto[1744830464:1879048191]	94	1			T48	1		T133	2		T59	2
auto[1879048192:2013265919]	107	1			T22	2		T6	1		T54	1
auto[2013265920:2147483647]	103	1			T2	1		T22	1		T6	3
auto[2147483648:2281701375]	120	1			T41	1		T101	1		T198	1
auto[2281701376:2415919103]	91	1			T19	1		T6	3		T43	1
auto[2415919104:2550136831]	116	1			T101	1		T24	2		T6	1
auto[2550136832:2684354559]	124	1			T65	1		T6	2		T39	1
auto[2684354560:2818572287]	115	1			T132	1		T197	1		T6	2
auto[2818572288:2952790015]	110	1			T1	1		T132	1		T6	2
auto[2952790016:3087007743]	111	1			T41	1		T6	1		T133	1
auto[3087007744:3221225471]	114	1			T2	1		T19	1		T47	1
auto[3221225472:3355443199]	112	1			T22	1		T65	1		T24	1
auto[3355443200:3489660927]	108	1			T42	1		T198	1		T6	1
auto[3489660928:3623878655]	122	1			T22	1		T42	1		T20	2
auto[3623878656:3758096383]	108	1			T41	1		T6	2		T58	1
auto[3758096384:3892314111]	100	1			T102	2		T42	1		T101	1
auto[3892314112:4026531839]	117	1			T2	1		T22	1		T65	1
auto[4026531840:4160749567]	116	1			T2	1		T41	1		T6	2
auto[4160749568:4294967295]	109	1			T1	1		T40	1		T24	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	53	1			T40	1		T24	1		T48	1
auto[0:134217727]	auto[1]	52	1			T6	1		T59	2		T62	1
auto[134217728:268435455]	auto[0]	53	1			T20	1		T6	1		T202	2
auto[134217728:268435455]	auto[1]	49	1			T65	1		T6	5		T39	1
auto[268435456:402653183]	auto[0]	59	1			T22	1		T102	1		T42	2
auto[268435456:402653183]	auto[1]	61	1			T48	2		T59	1		T53	1
auto[402653184:536870911]	auto[0]	53	1			T6	3		T288	1		T61	1
auto[402653184:536870911]	auto[1]	65	1			T31	1		T23	1		T132	1
auto[536870912:671088639]	auto[0]	69	1			T47	1		T48	1		T44	1
auto[536870912:671088639]	auto[1]	67	1			T22	2		T6	1		T59	1
auto[671088640:805306367]	auto[0]	59	1			T48	1		T6	2		T44	1
auto[671088640:805306367]	auto[1]	64	1			T6	1		T193	1		T58	1
auto[805306368:939524095]	auto[0]	64	1			T40	1		T47	1		T20	1
auto[805306368:939524095]	auto[1]	69	1			T41	1		T47	1		T48	1
auto[939524096:1073741823]	auto[0]	50	1			T102	1		T193	1		T52	1
auto[939524096:1073741823]	auto[1]	63	1			T101	1		T6	1		T44	1
auto[1073741824:1207959551]	auto[0]	51	1			T42	1		T6	1		T61	1
auto[1073741824:1207959551]	auto[1]	49	1			T1	1		T134	1		T62	1
auto[1207959552:1342177279]	auto[0]	61	1			T1	1		T42	1		T52	1
auto[1207959552:1342177279]	auto[1]	48	1			T22	1		T197	1		T133	1
auto[1342177280:1476395007]	auto[0]	59	1			T42	1		T21	1		T6	2
auto[1342177280:1476395007]	auto[1]	62	1			T1	1		T19	1		T48	1
auto[1476395008:1610612735]	auto[0]	44	1			T65	1		T193	1		T44	1
auto[1476395008:1610612735]	auto[1]	64	1			T110	1		T59	3		T203	1
auto[1610612736:1744830463]	auto[0]	53	1			T22	1		T23	1		T97	1
auto[1610612736:1744830463]	auto[1]	62	1			T133	1		T353	1		T53	2
auto[1744830464:1879048191]	auto[0]	41	1			T133	1		T59	1		T53	1
auto[1744830464:1879048191]	auto[1]	53	1			T48	1		T133	1		T59	1
auto[1879048192:2013265919]	auto[0]	46	1			T22	1		T6	1		T54	1
auto[1879048192:2013265919]	auto[1]	61	1			T22	1		T193	1		T59	1
auto[2013265920:2147483647]	auto[0]	48	1			T2	1		T22	1		T6	1
auto[2013265920:2147483647]	auto[1]	55	1			T6	2		T59	1		T44	1
auto[2147483648:2281701375]	auto[0]	57	1			T41	1		T265	1		T269	1
auto[2147483648:2281701375]	auto[1]	63	1			T101	1		T198	1		T6	2
auto[2281701376:2415919103]	auto[0]	39	1			T19	1		T6	2		T59	1
auto[2281701376:2415919103]	auto[1]	52	1			T6	1		T43	1		T193	1
auto[2415919104:2550136831]	auto[0]	57	1			T24	1		T59	2		T288	1
auto[2415919104:2550136831]	auto[1]	59	1			T101	1		T24	1		T6	1
auto[2550136832:2684354559]	auto[0]	55	1			T65	1		T6	1		T39	1
auto[2550136832:2684354559]	auto[1]	69	1			T6	1		T61	1		T57	1
auto[2684354560:2818572287]	auto[0]	52	1			T6	1		T193	1		T58	1
auto[2684354560:2818572287]	auto[1]	63	1			T132	1		T197	1		T6	1
auto[2818572288:2952790015]	auto[0]	53	1			T132	1		T6	1		T39	1
auto[2818572288:2952790015]	auto[1]	57	1			T1	1		T6	1		T59	2
auto[2952790016:3087007743]	auto[0]	47	1			T41	1		T39	1		T62	1
auto[2952790016:3087007743]	auto[1]	64	1			T6	1		T133	1		T59	1
auto[3087007744:3221225471]	auto[0]	48	1			T2	1		T19	1		T47	1
auto[3087007744:3221225471]	auto[1]	66	1			T198	1		T59	1		T252	1
auto[3221225472:3355443199]	auto[0]	60	1			T22	1		T21	1		T6	2
auto[3221225472:3355443199]	auto[1]	52	1			T65	1		T24	1		T198	1
auto[3355443200:3489660927]	auto[0]	49	1			T44	2		T141	1		T53	1
auto[3355443200:3489660927]	auto[1]	59	1			T42	1		T198	1		T6	1
auto[3489660928:3623878655]	auto[0]	50	1			T22	1		T20	2		T39	2
auto[3489660928:3623878655]	auto[1]	72	1			T42	1		T48	1		T6	4
auto[3623878656:3758096383]	auto[0]	44	1			T6	2		T59	1		T62	2
auto[3623878656:3758096383]	auto[1]	64	1			T41	1		T58	1		T44	1
auto[3758096384:3892314111]	auto[0]	38	1			T6	1		T94	1		T28	1
auto[3758096384:3892314111]	auto[1]	62	1			T102	2		T42	1		T101	1
auto[3892314112:4026531839]	auto[0]	58	1			T110	2		T6	1		T62	2
auto[3892314112:4026531839]	auto[1]	59	1			T2	1		T22	1		T65	1
auto[4026531840:4160749567]	auto[0]	56	1			T54	1		T53	1		T94	1
auto[4026531840:4160749567]	auto[1]	60	1			T2	1		T41	1		T6	2
auto[4160749568:4294967295]	auto[0]	57	1			T40	1		T6	1		T59	3
auto[4160749568:4294967295]	auto[1]	52	1			T1	1		T24	1		T6	2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1660

1

T1

2

T2

1

T22

5

auto[1]

1939

1

T1

3

T2

3

T22

6

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	101	1			T2	1		T40	1		T6	2
auto[134217728:268435455]	124	1			T22	1		T41	1		T47	1
auto[268435456:402653183]	126	1			T47	1		T48	3		T21	1
auto[402653184:536870911]	81	1			T19	1		T41	1		T101	1
auto[536870912:671088639]	120	1			T41	1		T198	1		T48	1
auto[671088640:805306367]	105	1			T1	1		T102	1		T197	1
auto[805306368:939524095]	106	1			T102	1		T42	1		T48	1
auto[939524096:1073741823]	119	1			T22	1		T65	1		T132	1
auto[1073741824:1207959551]	120	1			T22	1		T6	4		T194	1
auto[1207959552:1342177279]	109	1			T2	1		T42	1		T20	1
auto[1342177280:1476395007]	117	1			T41	1		T6	3		T54	1
auto[1476395008:1610612735]	108	1			T22	1		T23	1		T110	1
auto[1610612736:1744830463]	107	1			T2	1		T22	1		T41	1
auto[1744830464:1879048191]	115	1			T102	1		T19	1		T101	1
auto[1879048192:2013265919]	110	1			T22	1		T31	1		T6	2
auto[2013265920:2147483647]	108	1			T65	1		T6	1		T133	1
auto[2147483648:2281701375]	125	1			T6	1		T133	1		T59	2
auto[2281701376:2415919103]	111	1			T22	2		T20	1		T6	1
auto[2415919104:2550136831]	117	1			T1	1		T22	1		T42	1
auto[2550136832:2684354559]	114	1			T39	1		T59	1		T44	2
auto[2684354560:2818572287]	121	1			T40	1		T65	1		T101	1
auto[2818572288:2952790015]	98	1			T19	1		T23	1		T24	2
auto[2952790016:3087007743]	111	1			T42	1		T101	1		T132	1
auto[3087007744:3221225471]	108	1			T42	1		T6	5		T54	1
auto[3221225472:3355443199]	114	1			T65	1		T6	4		T43	1
auto[3355443200:3489660927]	116	1			T42	1		T47	1		T20	1
auto[3489660928:3623878655]	103	1			T22	1		T102	1		T42	1
auto[3623878656:3758096383]	122	1			T2	1		T40	1		T65	1
auto[3758096384:3892314111]	126	1			T1	1		T42	1		T6	2
auto[3892314112:4026531839]	105	1			T20	1		T6	2		T54	1
auto[4026531840:4160749567]	107	1			T1	1		T24	1		T6	4
auto[4160749568:4294967295]	125	1			T1	1		T22	1		T48	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	51	1			T40	1		T6	1		T59	2
auto[0:134217727]	auto[1]	50	1			T2	1		T6	1		T58	1
auto[134217728:268435455]	auto[0]	62	1			T22	1		T47	1		T141	1
auto[134217728:268435455]	auto[1]	62	1			T41	1		T43	1		T45	1
auto[268435456:402653183]	auto[0]	67	1			T21	1		T6	1		T39	1
auto[268435456:402653183]	auto[1]	59	1			T47	1		T48	3		T6	1
auto[402653184:536870911]	auto[0]	36	1			T39	1		T59	1		T44	1
auto[402653184:536870911]	auto[1]	45	1			T19	1		T41	1		T101	1
auto[536870912:671088639]	auto[0]	57	1			T198	1		T6	2		T59	2
auto[536870912:671088639]	auto[1]	63	1			T41	1		T48	1		T59	1
auto[671088640:805306367]	auto[0]	36	1			T59	1		T44	1		T7	1
auto[671088640:805306367]	auto[1]	69	1			T1	1		T102	1		T197	1
auto[805306368:939524095]	auto[0]	51	1			T44	1		T298	1		T184	1
auto[805306368:939524095]	auto[1]	55	1			T102	1		T42	1		T48	1
auto[939524096:1073741823]	auto[0]	57	1			T44	1		T62	1		T264	1
auto[939524096:1073741823]	auto[1]	62	1			T22	1		T65	1		T132	1
auto[1073741824:1207959551]	auto[0]	47	1			T22	1		T6	1		T39	2
auto[1073741824:1207959551]	auto[1]	73	1			T6	3		T194	1		T59	2
auto[1207959552:1342177279]	auto[0]	55	1			T42	1		T20	1		T48	1
auto[1207959552:1342177279]	auto[1]	54	1			T2	1		T265	1		T252	1
auto[1342177280:1476395007]	auto[0]	54	1			T41	1		T6	1		T54	1
auto[1342177280:1476395007]	auto[1]	63	1			T6	2		T59	1		T53	1
auto[1476395008:1610612735]	auto[0]	57	1			T6	1		T193	1		T58	1
auto[1476395008:1610612735]	auto[1]	51	1			T22	1		T23	1		T110	1
auto[1610612736:1744830463]	auto[0]	52	1			T110	1		T6	1		T193	1
auto[1610612736:1744830463]	auto[1]	55	1			T2	1		T22	1		T41	1
auto[1744830464:1879048191]	auto[0]	37	1			T102	1		T19	1		T132	1
auto[1744830464:1879048191]	auto[1]	78	1			T101	1		T23	1		T197	1
auto[1879048192:2013265919]	auto[0]	53	1			T193	1		T39	1		T44	1
auto[1879048192:2013265919]	auto[1]	57	1			T22	1		T31	1		T6	2
auto[2013265920:2147483647]	auto[0]	56	1			T65	1		T44	1		T288	1
auto[2013265920:2147483647]	auto[1]	52	1			T6	1		T133	1		T59	1
auto[2147483648:2281701375]	auto[0]	51	1			T59	1		T97	1		T121	1
auto[2147483648:2281701375]	auto[1]	74	1			T6	1		T133	1		T59	1
auto[2281701376:2415919103]	auto[0]	45	1			T20	1		T59	1		T57	1
auto[2281701376:2415919103]	auto[1]	66	1			T22	2		T6	1		T133	2
auto[2415919104:2550136831]	auto[0]	67	1			T1	1		T22	1		T42	1
auto[2415919104:2550136831]	auto[1]	50	1			T51	1		T62	1		T204	1
auto[2550136832:2684354559]	auto[0]	54	1			T39	1		T44	1		T53	1
auto[2550136832:2684354559]	auto[1]	60	1			T59	1		T44	1		T202	1
auto[2684354560:2818572287]	auto[0]	53	1			T40	1		T6	1		T203	1
auto[2684354560:2818572287]	auto[1]	68	1			T65	1		T101	1		T198	1
auto[2818572288:2952790015]	auto[0]	46	1			T19	1		T23	1		T24	1
auto[2818572288:2952790015]	auto[1]	52	1			T24	1		T59	4		T61	1
auto[2952790016:3087007743]	auto[0]	49	1			T42	1		T48	1		T6	1
auto[2952790016:3087007743]	auto[1]	62	1			T101	1		T132	1		T110	1
auto[3087007744:3221225471]	auto[0]	50	1			T6	3		T53	1		T62	3
auto[3087007744:3221225471]	auto[1]	58	1			T42	1		T6	2		T54	1
auto[3221225472:3355443199]	auto[0]	58	1			T6	3		T193	1		T133	1
auto[3221225472:3355443199]	auto[1]	56	1			T65	1		T6	1		T43	1
auto[3355443200:3489660927]	auto[0]	41	1			T47	1		T20	1		T21	1
auto[3355443200:3489660927]	auto[1]	75	1			T42	1		T6	2		T58	1
auto[3489660928:3623878655]	auto[0]	46	1			T22	1		T6	1		T61	1
auto[3489660928:3623878655]	auto[1]	57	1			T102	1		T42	1		T6	1
auto[3623878656:3758096383]	auto[0]	51	1			T2	1		T40	1		T65	1
auto[3623878656:3758096383]	auto[1]	71	1			T24	1		T6	1		T59	1
auto[3758096384:3892314111]	auto[0]	63	1			T42	1		T6	1		T202	1
auto[3758096384:3892314111]	auto[1]	63	1			T1	1		T6	1		T45	1
auto[3892314112:4026531839]	auto[0]	49	1			T20	1		T6	1		T54	1
auto[3892314112:4026531839]	auto[1]	56	1			T6	1		T59	1		T62	4
auto[4026531840:4160749567]	auto[0]	49	1			T1	1		T24	1		T6	3
auto[4026531840:4160749567]	auto[1]	58	1			T6	1		T59	1		T62	1
auto[4160749568:4294967295]	auto[0]	60	1			T22	1		T61	1		T94	1
auto[4160749568:4294967295]	auto[1]	65	1			T1	1		T48	1		T6	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1693

1

T1

2

T2

2

T22

6

auto[1]

1907

1

T1

3

T2

2

T22

5

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	120	1			T42	1		T6	1		T193	1
auto[134217728:268435455]	104	1			T22	1		T6	4		T59	2
auto[268435456:402653183]	123	1			T102	1		T41	1		T42	1
auto[402653184:536870911]	100	1			T41	1		T65	1		T6	1
auto[536870912:671088639]	110	1			T19	1		T42	1		T6	2
auto[671088640:805306367]	112	1			T2	1		T22	1		T47	1
auto[805306368:939524095]	97	1			T22	1		T42	1		T48	1
auto[939524096:1073741823]	100	1			T22	2		T198	1		T6	2
auto[1073741824:1207959551]	107	1			T2	1		T42	1		T20	1
auto[1207959552:1342177279]	106	1			T102	1		T23	1		T43	1
auto[1342177280:1476395007]	115	1			T22	1		T65	1		T48	1
auto[1476395008:1610612735]	105	1			T65	1		T54	1		T59	1
auto[1610612736:1744830463]	118	1			T1	1		T41	1		T42	1
auto[1744830464:1879048191]	115	1			T1	2		T6	3		T193	1
auto[1879048192:2013265919]	108	1			T42	1		T47	1		T23	1
auto[2013265920:2147483647]	116	1			T132	1		T24	1		T6	3
auto[2147483648:2281701375]	131	1			T1	1		T22	2		T31	1
auto[2281701376:2415919103]	112	1			T1	1		T65	1		T198	1
auto[2415919104:2550136831]	106	1			T197	1		T194	1		T59	2
auto[2550136832:2684354559]	118	1			T41	2		T197	1		T20	1
auto[2684354560:2818572287]	120	1			T22	1		T47	1		T24	1
auto[2818572288:2952790015]	117	1			T101	1		T132	1		T6	3
auto[2952790016:3087007743]	104	1			T2	1		T40	2		T24	1
auto[3087007744:3221225471]	98	1			T21	1		T6	2		T193	1
auto[3221225472:3355443199]	124	1			T22	1		T20	1		T48	1
auto[3355443200:3489660927]	112	1			T6	2		T59	1		T269	1
auto[3489660928:3623878655]	131	1			T102	1		T19	1		T101	1
auto[3623878656:3758096383]	100	1			T2	1		T65	1		T42	1
auto[3758096384:3892314111]	112	1			T19	1		T47	1		T48	1
auto[3892314112:4026531839]	130	1			T6	2		T193	1		T44	1
auto[4026531840:4160749567]	118	1			T22	1		T102	1		T23	1
auto[4160749568:4294967295]	111	1			T40	1		T6	1		T133	1