Unified Coverage Report :: Group Instance : salt_5

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3150

1

T1

5

T2

4

T22

10

auto[1]

295

1

T102

4

T41

1

T42

15

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	115	1			T41	1		T42	1		T21	1
auto[134217728:268435455]	114	1			T22	1		T42	1		T132	1
auto[268435456:402653183]	101	1			T102	1		T23	1		T132	1
auto[402653184:536870911]	110	1			T42	1		T132	1		T24	1
auto[536870912:671088639]	112	1			T1	2		T22	1		T19	1
auto[671088640:805306367]	118	1			T40	1		T48	1		T6	3
auto[805306368:939524095]	104	1			T22	1		T102	1		T42	1
auto[939524096:1073741823]	100	1			T41	1		T101	2		T20	1
auto[1073741824:1207959551]	121	1			T22	1		T102	1		T42	1
auto[1207959552:1342177279]	126	1			T31	1		T42	2		T23	1
auto[1342177280:1476395007]	97	1			T2	1		T47	1		T132	1
auto[1476395008:1610612735]	104	1			T22	1		T40	1		T41	1
auto[1610612736:1744830463]	115	1			T47	1		T198	1		T6	2
auto[1744830464:1879048191]	112	1			T2	1		T41	1		T42	2
auto[1879048192:2013265919]	104	1			T22	1		T42	1		T47	1
auto[2013265920:2147483647]	99	1			T102	1		T6	1		T59	1
auto[2147483648:2281701375]	115	1			T1	1		T22	2		T42	1
auto[2281701376:2415919103]	100	1			T22	1		T65	1		T42	1
auto[2415919104:2550136831]	110	1			T21	1		T59	1		T44	1
auto[2550136832:2684354559]	96	1			T2	1		T42	1		T48	1
auto[2684354560:2818572287]	114	1			T22	1		T42	1		T23	1
auto[2818572288:2952790015]	110	1			T102	1		T198	1		T6	3
auto[2952790016:3087007743]	125	1			T42	1		T132	1		T197	1
auto[3087007744:3221225471]	111	1			T2	1		T102	1		T24	1
auto[3221225472:3355443199]	97	1			T1	1		T40	1		T102	1
auto[3355443200:3489660927]	107	1			T42	2		T6	2		T59	1
auto[3489660928:3623878655]	95	1			T1	1		T42	1		T132	1
auto[3623878656:3758096383]	96	1			T42	1		T24	1		T6	2
auto[3758096384:3892314111]	85	1			T47	1		T110	2		T193	1
auto[3892314112:4026531839]	96	1			T102	1		T41	1		T132	2
auto[4026531840:4160749567]	122	1			T19	1		T42	1		T132	2
auto[4160749568:4294967295]	114	1			T132	1		T6	5		T59	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	106	1			T41	1		T42	1		T21	1
auto[0:134217727]	auto[1]	9	1			T360	1		T390	1		T403	1
auto[134217728:268435455]	auto[0]	98	1			T22	1		T24	2		T6	3
auto[134217728:268435455]	auto[1]	16	1			T42	1		T132	1		T360	1
auto[268435456:402653183]	auto[0]	93	1			T23	1		T6	1		T133	1
auto[268435456:402653183]	auto[1]	8	1			T102	1		T132	1		T360	2
auto[402653184:536870911]	auto[0]	97	1			T42	1		T132	1		T24	1
auto[402653184:536870911]	auto[1]	13	1			T373	1		T334	1		T395	1
auto[536870912:671088639]	auto[0]	101	1			T1	2		T22	1		T19	1
auto[536870912:671088639]	auto[1]	11	1			T132	1		T237	1		T360	1
auto[671088640:805306367]	auto[0]	111	1			T40	1		T48	1		T6	3
auto[671088640:805306367]	auto[1]	7	1			T360	1		T373	1		T394	1
auto[805306368:939524095]	auto[0]	97	1			T22	1		T42	1		T6	4
auto[805306368:939524095]	auto[1]	7	1			T102	1		T279	1		T302	1
auto[939524096:1073741823]	auto[0]	91	1			T41	1		T101	2		T20	1
auto[939524096:1073741823]	auto[1]	9	1			T134	1		T290	2		T318	2
auto[1073741824:1207959551]	auto[0]	110	1			T22	1		T102	1		T48	1
auto[1073741824:1207959551]	auto[1]	11	1			T42	1		T239	1		T290	1
auto[1207959552:1342177279]	auto[0]	109	1			T31	1		T23	1		T20	1
auto[1207959552:1342177279]	auto[1]	17	1			T42	2		T132	1		T141	2
auto[1342177280:1476395007]	auto[0]	91	1			T2	1		T47	1		T132	1
auto[1342177280:1476395007]	auto[1]	6	1			T290	1		T402	1		T404	3
auto[1476395008:1610612735]	auto[0]	93	1			T22	1		T40	1		T41	1
auto[1476395008:1610612735]	auto[1]	11	1			T42	1		T279	1		T302	1
auto[1610612736:1744830463]	auto[0]	107	1			T47	1		T198	1		T6	2
auto[1610612736:1744830463]	auto[1]	8	1			T133	1		T134	1		T237	1
auto[1744830464:1879048191]	auto[0]	97	1			T2	1		T42	1		T48	1
auto[1744830464:1879048191]	auto[1]	15	1			T41	1		T42	1		T290	2
auto[1879048192:2013265919]	auto[0]	99	1			T22	1		T47	1		T20	1
auto[1879048192:2013265919]	auto[1]	5	1			T42	1		T296	1		T405	1
auto[2013265920:2147483647]	auto[0]	92	1			T102	1		T6	1		T59	1
auto[2013265920:2147483647]	auto[1]	7	1			T360	1		T372	1		T373	1
auto[2147483648:2281701375]	auto[0]	105	1			T1	1		T22	2		T101	1
auto[2147483648:2281701375]	auto[1]	10	1			T42	1		T290	1		T334	1
auto[2281701376:2415919103]	auto[0]	88	1			T22	1		T65	1		T193	1
auto[2281701376:2415919103]	auto[1]	12	1			T42	1		T132	1		T239	1
auto[2415919104:2550136831]	auto[0]	101	1			T21	1		T59	1		T44	1
auto[2415919104:2550136831]	auto[1]	9	1			T334	1		T371	1		T388	2
auto[2550136832:2684354559]	auto[0]	92	1			T2	1		T42	1		T48	1
auto[2550136832:2684354559]	auto[1]	4	1			T373	1		T334	1		T388	1
auto[2684354560:2818572287]	auto[0]	105	1			T22	1		T23	1		T193	1
auto[2684354560:2818572287]	auto[1]	9	1			T42	1		T237	1		T302	2
auto[2818572288:2952790015]	auto[0]	102	1			T102	1		T198	1		T6	3
auto[2818572288:2952790015]	auto[1]	8	1			T237	1		T258	1		T388	1
auto[2952790016:3087007743]	auto[0]	118	1			T197	1		T6	2		T193	1
auto[2952790016:3087007743]	auto[1]	7	1			T42	1		T132	1		T393	1
auto[3087007744:3221225471]	auto[0]	103	1			T2	1		T24	1		T198	1
auto[3087007744:3221225471]	auto[1]	8	1			T102	1		T360	1		T287	1
auto[3221225472:3355443199]	auto[0]	90	1			T1	1		T40	1		T19	1
auto[3221225472:3355443199]	auto[1]	7	1			T102	1		T42	1		T290	1
auto[3355443200:3489660927]	auto[0]	100	1			T42	1		T6	2		T59	1
auto[3355443200:3489660927]	auto[1]	7	1			T42	1		T296	1		T334	1
auto[3489660928:3623878655]	auto[0]	85	1			T1	1		T20	1		T48	1
auto[3489660928:3623878655]	auto[1]	10	1			T42	1		T132	1		T133	1
auto[3623878656:3758096383]	auto[0]	88	1			T42	1		T24	1		T6	2
auto[3623878656:3758096383]	auto[1]	8	1			T290	1		T373	1		T296	1
auto[3758096384:3892314111]	auto[0]	80	1			T47	1		T110	2		T193	1
auto[3758096384:3892314111]	auto[1]	5	1			T134	1		T290	1		T392	1
auto[3892314112:4026531839]	auto[0]	88	1			T102	1		T41	1		T132	1
auto[3892314112:4026531839]	auto[1]	8	1			T132	1		T133	1		T386	1
auto[4026531840:4160749567]	auto[0]	109	1			T19	1		T59	1		T44	1
auto[4026531840:4160749567]	auto[1]	13	1			T42	1		T132	2		T134	2
auto[4160749568:4294967295]	auto[0]	104	1			T6	5		T59	2		T269	1
auto[4160749568:4294967295]	auto[1]	10	1			T132	1		T237	1		T279	1