Unified Coverage Report :: Group Instance : key_version

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

7437

1

T1

10

T2

15

T22

19

auto[1]

304

1

T102

5

T41

5

T42

20

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	3082	1			T1	5		T2	7		T22	8
auto[134217728:268435455]	187	1			T22	2		T40	1		T31	1
auto[268435456:402653183]	185	1			T22	1		T41	1		T42	1
auto[402653184:536870911]	156	1			T2	1		T102	1		T6	1
auto[536870912:671088639]	146	1			T2	1		T19	2		T42	1
auto[671088640:805306367]	144	1			T102	2		T42	2		T23	1
auto[805306368:939524095]	118	1			T22	1		T23	1		T21	1
auto[939524096:1073741823]	156	1			T2	1		T42	2		T132	1
auto[1073741824:1207959551]	169	1			T42	1		T132	2		T110	1
auto[1207959552:1342177279]	141	1			T1	1		T2	1		T22	1
auto[1342177280:1476395007]	171	1			T42	3		T24	2		T197	1
auto[1476395008:1610612735]	122	1			T102	1		T41	1		T24	1
auto[1610612736:1744830463]	155	1			T40	1		T102	1		T24	1
auto[1744830464:1879048191]	164	1			T102	1		T19	1		T42	1
auto[1879048192:2013265919]	150	1			T102	1		T19	1		T42	1
auto[2013265920:2147483647]	166	1			T22	1		T41	3		T42	1
auto[2147483648:2281701375]	132	1			T40	1		T110	1		T198	2
auto[2281701376:2415919103]	144	1			T65	1		T132	1		T24	1
auto[2415919104:2550136831]	157	1			T42	1		T101	1		T23	1
auto[2550136832:2684354559]	127	1			T41	1		T24	2		T21	1
auto[2684354560:2818572287]	156	1			T102	1		T41	1		T47	1
auto[2818572288:2952790015]	126	1			T1	1		T42	2		T48	1
auto[2952790016:3087007743]	163	1			T1	1		T22	1		T41	1
auto[3087007744:3221225471]	142	1			T1	2		T2	2		T19	2
auto[3221225472:3355443199]	131	1			T47	1		T23	1		T20	1
auto[3355443200:3489660927]	141	1			T2	1		T22	2		T42	2
auto[3489660928:3623878655]	142	1			T42	1		T101	1		T48	1
auto[3623878656:3758096383]	158	1			T22	2		T41	1		T24	1
auto[3758096384:3892314111]	141	1			T2	1		T19	1		T42	2
auto[3892314112:4026531839]	164	1			T102	1		T42	1		T23	1
auto[4026531840:4160749567]	154	1			T19	1		T42	1		T101	1
auto[4160749568:4294967295]	151	1			T110	1		T6	1		T133	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	3077	1			T1	5		T2	7		T22	8
auto[0:134217727]	auto[1]	5	1			T41	1		T392	1		T387	1
auto[134217728:268435455]	auto[0]	176	1			T22	2		T40	1		T31	1
auto[134217728:268435455]	auto[1]	11	1			T360	1		T373	1		T334	1
auto[268435456:402653183]	auto[0]	176	1			T22	1		T132	1		T6	4
auto[268435456:402653183]	auto[1]	9	1			T41	1		T42	1		T134	1
auto[402653184:536870911]	auto[0]	144	1			T2	1		T6	1		T54	1
auto[402653184:536870911]	auto[1]	12	1			T102	1		T373	2		T371	1
auto[536870912:671088639]	auto[0]	136	1			T2	1		T19	2		T6	1
auto[536870912:671088639]	auto[1]	10	1			T42	1		T132	1		T141	1
auto[671088640:805306367]	auto[0]	135	1			T102	2		T42	1		T23	1
auto[671088640:805306367]	auto[1]	9	1			T42	1		T132	1		T360	1
auto[805306368:939524095]	auto[0]	110	1			T22	1		T23	1		T21	1
auto[805306368:939524095]	auto[1]	8	1			T239	1		T373	1		T387	1
auto[939524096:1073741823]	auto[0]	143	1			T2	1		T42	1		T132	1
auto[939524096:1073741823]	auto[1]	13	1			T42	1		T237	1		T302	1
auto[1073741824:1207959551]	auto[0]	157	1			T132	1		T110	1		T198	1
auto[1073741824:1207959551]	auto[1]	12	1			T42	1		T132	1		T141	1
auto[1207959552:1342177279]	auto[0]	128	1			T1	1		T2	1		T22	1
auto[1207959552:1342177279]	auto[1]	13	1			T102	1		T42	2		T141	1
auto[1342177280:1476395007]	auto[0]	156	1			T42	1		T24	2		T197	1
auto[1342177280:1476395007]	auto[1]	15	1			T42	2		T239	1		T360	1
auto[1476395008:1610612735]	auto[0]	116	1			T102	1		T41	1		T24	1
auto[1476395008:1610612735]	auto[1]	6	1			T134	1		T290	1		T387	1
auto[1610612736:1744830463]	auto[0]	148	1			T40	1		T24	1		T6	1
auto[1610612736:1744830463]	auto[1]	7	1			T102	1		T134	1		T360	2
auto[1744830464:1879048191]	auto[0]	150	1			T19	1		T6	7		T39	1
auto[1744830464:1879048191]	auto[1]	14	1			T102	1		T42	1		T134	1
auto[1879048192:2013265919]	auto[0]	140	1			T102	1		T19	1		T101	1
auto[1879048192:2013265919]	auto[1]	10	1			T42	1		T360	1		T258	1
auto[2013265920:2147483647]	auto[0]	159	1			T22	1		T41	2		T24	1
auto[2013265920:2147483647]	auto[1]	7	1			T41	1		T42	1		T239	1
auto[2147483648:2281701375]	auto[0]	122	1			T40	1		T110	1		T198	2
auto[2147483648:2281701375]	auto[1]	10	1			T258	2		T372	1		T334	1
auto[2281701376:2415919103]	auto[0]	136	1			T65	1		T24	1		T198	2
auto[2281701376:2415919103]	auto[1]	8	1			T132	1		T237	2		T360	1
auto[2415919104:2550136831]	auto[0]	148	1			T101	1		T23	1		T48	1
auto[2415919104:2550136831]	auto[1]	9	1			T42	1		T360	1		T393	1
auto[2550136832:2684354559]	auto[0]	123	1			T41	1		T24	2		T21	1
auto[2550136832:2684354559]	auto[1]	4	1			T372	1		T371	1		T387	1
auto[2684354560:2818572287]	auto[0]	144	1			T41	1		T47	1		T48	1
auto[2684354560:2818572287]	auto[1]	12	1			T102	1		T290	1		T373	1
auto[2818572288:2952790015]	auto[0]	116	1			T1	1		T42	2		T48	1
auto[2818572288:2952790015]	auto[1]	10	1			T237	1		T360	2		T371	1
auto[2952790016:3087007743]	auto[0]	150	1			T1	1		T22	1		T42	2
auto[2952790016:3087007743]	auto[1]	13	1			T41	1		T237	1		T302	2
auto[3087007744:3221225471]	auto[0]	135	1			T1	2		T2	2		T19	2
auto[3087007744:3221225471]	auto[1]	7	1			T134	1		T360	1		T238	1
auto[3221225472:3355443199]	auto[0]	125	1			T47	1		T23	1		T20	1
auto[3221225472:3355443199]	auto[1]	6	1			T296	2		T394	1		T395	1
auto[3355443200:3489660927]	auto[0]	129	1			T2	1		T22	2		T198	2
auto[3355443200:3489660927]	auto[1]	12	1			T42	2		T132	1		T334	1
auto[3489660928:3623878655]	auto[0]	133	1			T101	1		T48	1		T6	2
auto[3489660928:3623878655]	auto[1]	9	1			T42	1		T290	1		T238	1
auto[3623878656:3758096383]	auto[0]	150	1			T22	2		T24	1		T20	1
auto[3623878656:3758096383]	auto[1]	8	1			T41	1		T134	1		T371	1
auto[3758096384:3892314111]	auto[0]	133	1			T2	1		T19	1		T23	1
auto[3758096384:3892314111]	auto[1]	8	1			T42	2		T237	1		T290	1
auto[3892314112:4026531839]	auto[0]	153	1			T102	1		T23	1		T21	1
auto[3892314112:4026531839]	auto[1]	11	1			T42	1		T132	1		T258	1
auto[4026531840:4160749567]	auto[0]	150	1			T19	1		T101	1		T23	2
auto[4026531840:4160749567]	auto[1]	4	1			T42	1		T387	1		T396	1
auto[4160749568:4294967295]	auto[0]	139	1			T110	1		T6	1		T133	1
auto[4160749568:4294967295]	auto[1]	12	1			T141	1		T290	1		T258	1