Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.88 99.07 98.03 99.07 100.00 99.11 98.41 91.51


Total test records in report: 1072
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T1005 /workspace/coverage/cover_reg_top/42.keymgr_intr_test.3745728984 Mar 14 12:29:07 PM PDT 24 Mar 14 12:29:13 PM PDT 24 19481354 ps
T1006 /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.2197848396 Mar 14 12:28:36 PM PDT 24 Mar 14 12:28:41 PM PDT 24 569894993 ps
T1007 /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.843090700 Mar 14 12:28:39 PM PDT 24 Mar 14 12:28:40 PM PDT 24 23894491 ps
T1008 /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.1550131078 Mar 14 12:28:50 PM PDT 24 Mar 14 12:28:53 PM PDT 24 180594316 ps
T1009 /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.3817493613 Mar 14 12:28:39 PM PDT 24 Mar 14 12:28:41 PM PDT 24 262453542 ps
T1010 /workspace/coverage/cover_reg_top/30.keymgr_intr_test.1453824248 Mar 14 12:29:04 PM PDT 24 Mar 14 12:29:05 PM PDT 24 14990611 ps
T1011 /workspace/coverage/cover_reg_top/10.keymgr_intr_test.736410018 Mar 14 12:28:44 PM PDT 24 Mar 14 12:28:50 PM PDT 24 21192782 ps
T1012 /workspace/coverage/cover_reg_top/28.keymgr_intr_test.478714489 Mar 14 12:28:50 PM PDT 24 Mar 14 12:28:51 PM PDT 24 38335590 ps
T156 /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.1203492719 Mar 14 12:28:38 PM PDT 24 Mar 14 12:28:41 PM PDT 24 74283190 ps
T1013 /workspace/coverage/cover_reg_top/22.keymgr_intr_test.709774997 Mar 14 12:29:12 PM PDT 24 Mar 14 12:29:13 PM PDT 24 28241742 ps
T1014 /workspace/coverage/cover_reg_top/23.keymgr_intr_test.1758008589 Mar 14 12:29:03 PM PDT 24 Mar 14 12:29:03 PM PDT 24 9903334 ps
T1015 /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.1562264126 Mar 14 12:28:45 PM PDT 24 Mar 14 12:28:50 PM PDT 24 127641594 ps
T1016 /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.658428690 Mar 14 12:28:58 PM PDT 24 Mar 14 12:29:00 PM PDT 24 24223999 ps
T1017 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.3758773331 Mar 14 12:28:41 PM PDT 24 Mar 14 12:28:44 PM PDT 24 432424513 ps
T1018 /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.1736054747 Mar 14 12:28:40 PM PDT 24 Mar 14 12:28:42 PM PDT 24 57335072 ps
T1019 /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.1527523881 Mar 14 12:29:03 PM PDT 24 Mar 14 12:29:04 PM PDT 24 50001393 ps
T1020 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.814091438 Mar 14 12:28:39 PM PDT 24 Mar 14 12:28:44 PM PDT 24 250036266 ps
T157 /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.2027881082 Mar 14 12:29:06 PM PDT 24 Mar 14 12:29:19 PM PDT 24 481672696 ps
T1021 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.1067165011 Mar 14 12:29:08 PM PDT 24 Mar 14 12:29:13 PM PDT 24 215388247 ps
T1022 /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.4267025425 Mar 14 12:28:41 PM PDT 24 Mar 14 12:28:43 PM PDT 24 134523345 ps
T1023 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.2292523856 Mar 14 12:28:57 PM PDT 24 Mar 14 12:29:02 PM PDT 24 199834277 ps
T1024 /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.3770791122 Mar 14 12:29:04 PM PDT 24 Mar 14 12:29:06 PM PDT 24 57923473 ps
T1025 /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.2920013662 Mar 14 12:28:36 PM PDT 24 Mar 14 12:28:38 PM PDT 24 28494801 ps
T1026 /workspace/coverage/cover_reg_top/2.keymgr_intr_test.115400251 Mar 14 12:28:40 PM PDT 24 Mar 14 12:28:50 PM PDT 24 43286592 ps
T1027 /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.1329467389 Mar 14 12:28:25 PM PDT 24 Mar 14 12:28:27 PM PDT 24 47440562 ps
T1028 /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.2264038551 Mar 14 12:28:53 PM PDT 24 Mar 14 12:28:55 PM PDT 24 126250380 ps
T1029 /workspace/coverage/cover_reg_top/38.keymgr_intr_test.4254777727 Mar 14 12:28:48 PM PDT 24 Mar 14 12:28:49 PM PDT 24 9073447 ps
T1030 /workspace/coverage/cover_reg_top/45.keymgr_intr_test.1936253847 Mar 14 12:28:53 PM PDT 24 Mar 14 12:28:54 PM PDT 24 9606145 ps
T1031 /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.658458923 Mar 14 12:28:59 PM PDT 24 Mar 14 12:29:00 PM PDT 24 33038866 ps
T1032 /workspace/coverage/cover_reg_top/7.keymgr_intr_test.1824791136 Mar 14 12:28:41 PM PDT 24 Mar 14 12:28:41 PM PDT 24 17706559 ps
T1033 /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.1358419092 Mar 14 12:28:39 PM PDT 24 Mar 14 12:28:42 PM PDT 24 30835010 ps
T1034 /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.2449754010 Mar 14 12:28:44 PM PDT 24 Mar 14 12:28:48 PM PDT 24 130718550 ps
T1035 /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.331836839 Mar 14 12:28:57 PM PDT 24 Mar 14 12:29:22 PM PDT 24 1169913309 ps
T1036 /workspace/coverage/cover_reg_top/3.keymgr_intr_test.2027828295 Mar 14 12:28:40 PM PDT 24 Mar 14 12:28:41 PM PDT 24 15780718 ps
T1037 /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.1708725152 Mar 14 12:29:34 PM PDT 24 Mar 14 12:29:37 PM PDT 24 116151305 ps
T1038 /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.2211584431 Mar 14 12:28:30 PM PDT 24 Mar 14 12:28:31 PM PDT 24 19480124 ps
T1039 /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.1866064593 Mar 14 12:29:16 PM PDT 24 Mar 14 12:29:18 PM PDT 24 36600859 ps
T1040 /workspace/coverage/cover_reg_top/8.keymgr_intr_test.3813108243 Mar 14 12:28:40 PM PDT 24 Mar 14 12:28:41 PM PDT 24 43197483 ps
T1041 /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.101146389 Mar 14 12:29:13 PM PDT 24 Mar 14 12:29:15 PM PDT 24 210199989 ps
T1042 /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.4286262592 Mar 14 12:29:06 PM PDT 24 Mar 14 12:29:08 PM PDT 24 61352304 ps
T1043 /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.3621615798 Mar 14 12:28:54 PM PDT 24 Mar 14 12:29:02 PM PDT 24 296394838 ps
T1044 /workspace/coverage/cover_reg_top/16.keymgr_intr_test.3406104662 Mar 14 12:28:52 PM PDT 24 Mar 14 12:28:53 PM PDT 24 13981722 ps
T1045 /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.431637808 Mar 14 12:28:47 PM PDT 24 Mar 14 12:28:48 PM PDT 24 85610962 ps
T1046 /workspace/coverage/cover_reg_top/9.keymgr_intr_test.1971373198 Mar 14 12:28:47 PM PDT 24 Mar 14 12:28:48 PM PDT 24 39492686 ps
T1047 /workspace/coverage/cover_reg_top/19.keymgr_intr_test.1123682883 Mar 14 12:29:10 PM PDT 24 Mar 14 12:29:10 PM PDT 24 31677634 ps
T1048 /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.4090404190 Mar 14 12:29:06 PM PDT 24 Mar 14 12:29:08 PM PDT 24 22645134 ps
T1049 /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.992494330 Mar 14 12:28:37 PM PDT 24 Mar 14 12:28:40 PM PDT 24 1029661565 ps
T1050 /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.4272447060 Mar 14 12:28:24 PM PDT 24 Mar 14 12:28:31 PM PDT 24 521275524 ps
T1051 /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.835227951 Mar 14 12:28:41 PM PDT 24 Mar 14 12:28:48 PM PDT 24 229426081 ps
T1052 /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.25883696 Mar 14 12:28:42 PM PDT 24 Mar 14 12:28:45 PM PDT 24 100968782 ps
T1053 /workspace/coverage/cover_reg_top/20.keymgr_intr_test.1419016057 Mar 14 12:29:07 PM PDT 24 Mar 14 12:29:07 PM PDT 24 9812114 ps
T1054 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.1292782304 Mar 14 12:28:53 PM PDT 24 Mar 14 12:29:01 PM PDT 24 160736493 ps
T1055 /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.300797552 Mar 14 12:28:42 PM PDT 24 Mar 14 12:28:48 PM PDT 24 4900769933 ps
T1056 /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.669578895 Mar 14 12:28:41 PM PDT 24 Mar 14 12:28:44 PM PDT 24 248546716 ps
T1057 /workspace/coverage/cover_reg_top/31.keymgr_intr_test.289825325 Mar 14 12:29:14 PM PDT 24 Mar 14 12:29:15 PM PDT 24 29953194 ps
T1058 /workspace/coverage/cover_reg_top/43.keymgr_intr_test.1778621298 Mar 14 12:29:09 PM PDT 24 Mar 14 12:29:10 PM PDT 24 35654021 ps
T1059 /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.3680831878 Mar 14 12:28:50 PM PDT 24 Mar 14 12:29:08 PM PDT 24 2331477638 ps
T1060 /workspace/coverage/cover_reg_top/40.keymgr_intr_test.3435196903 Mar 14 12:28:58 PM PDT 24 Mar 14 12:28:59 PM PDT 24 14212609 ps
T1061 /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.884135080 Mar 14 12:29:16 PM PDT 24 Mar 14 12:29:24 PM PDT 24 571464466 ps
T1062 /workspace/coverage/cover_reg_top/48.keymgr_intr_test.2617798221 Mar 14 12:29:11 PM PDT 24 Mar 14 12:29:12 PM PDT 24 10643631 ps
T1063 /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.1032848281 Mar 14 12:28:37 PM PDT 24 Mar 14 12:28:41 PM PDT 24 182338280 ps
T1064 /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.2786651526 Mar 14 12:28:52 PM PDT 24 Mar 14 12:28:53 PM PDT 24 23804957 ps
T1065 /workspace/coverage/cover_reg_top/24.keymgr_intr_test.3615568237 Mar 14 12:29:14 PM PDT 24 Mar 14 12:29:15 PM PDT 24 12182453 ps
T150 /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.2539832693 Mar 14 12:29:13 PM PDT 24 Mar 14 12:29:29 PM PDT 24 786941684 ps
T1066 /workspace/coverage/cover_reg_top/13.keymgr_intr_test.2786881852 Mar 14 12:28:43 PM PDT 24 Mar 14 12:28:44 PM PDT 24 9653823 ps
T152 /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.3148394516 Mar 14 12:29:07 PM PDT 24 Mar 14 12:29:17 PM PDT 24 401702940 ps
T1067 /workspace/coverage/cover_reg_top/21.keymgr_intr_test.1247448320 Mar 14 12:29:06 PM PDT 24 Mar 14 12:29:07 PM PDT 24 18435891 ps
T1068 /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.4249224373 Mar 14 12:28:41 PM PDT 24 Mar 14 12:28:42 PM PDT 24 42604076 ps
T1069 /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.3764890302 Mar 14 12:29:34 PM PDT 24 Mar 14 12:29:38 PM PDT 24 168319198 ps
T1070 /workspace/coverage/cover_reg_top/0.keymgr_intr_test.1678628409 Mar 14 12:28:42 PM PDT 24 Mar 14 12:28:43 PM PDT 24 23825272 ps
T1071 /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.314081056 Mar 14 12:29:01 PM PDT 24 Mar 14 12:29:02 PM PDT 24 115316250 ps
T1072 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.1980897415 Mar 14 12:29:03 PM PDT 24 Mar 14 12:29:11 PM PDT 24 554389859 ps

Test location /workspace/coverage/default/33.keymgr_random.3076440257
Short name T1
Test name
Test status
Simulation time 1061574853 ps
CPU time 7.19 seconds
Started Mar 14 12:58:22 PM PDT 24
Finished Mar 14 12:58:29 PM PDT 24
Peak memory 218636 kb
Host smart-7b31cca6-b949-472f-9aa8-c149f4cc7838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3076440257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.3076440257
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.2197604198
Short name T6
Test name
Test status
Simulation time 5792250483 ps
CPU time 57.9 seconds
Started Mar 14 12:57:19 PM PDT 24
Finished Mar 14 12:58:17 PM PDT 24
Peak memory 222936 kb
Host smart-69486d05-7fb4-4079-a16b-215ef15930d6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197604198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.2197604198
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_stress_all_with_rand_reset.264197464
Short name T22
Test name
Test status
Simulation time 391060684 ps
CPU time 8.65 seconds
Started Mar 14 12:55:49 PM PDT 24
Finished Mar 14 12:55:58 PM PDT 24
Peak memory 220700 kb
Host smart-0be12a94-1823-4f13-825e-4384566e1a20
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264197464 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all_with_rand_reset.264197464
Directory /workspace/3.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.28511935
Short name T4
Test name
Test status
Simulation time 733448416 ps
CPU time 12.18 seconds
Started Mar 14 12:55:59 PM PDT 24
Finished Mar 14 12:56:12 PM PDT 24
Peak memory 231204 kb
Host smart-7001fec8-2279-48ef-ac1a-c2681235f654
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28511935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.28511935
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.1408818343
Short name T62
Test name
Test status
Simulation time 497779596 ps
CPU time 26.9 seconds
Started Mar 14 12:55:10 PM PDT 24
Finished Mar 14 12:55:37 PM PDT 24
Peak memory 216876 kb
Host smart-f9bf7ffc-e143-4f78-a441-aeddb969170d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1408818343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.1408818343
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.3652943124
Short name T142
Test name
Test status
Simulation time 7899560733 ps
CPU time 32.93 seconds
Started Mar 14 12:28:27 PM PDT 24
Finished Mar 14 12:29:00 PM PDT 24
Peak memory 205840 kb
Host smart-0b9284d2-91f0-40a9-9553-2671c25597c9
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652943124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.3
652943124
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.3273405052
Short name T42
Test name
Test status
Simulation time 973006823 ps
CPU time 52.87 seconds
Started Mar 14 12:57:37 PM PDT 24
Finished Mar 14 12:58:30 PM PDT 24
Peak memory 215780 kb
Host smart-06fc7080-7522-4325-8a6a-190998abdf47
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3273405052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.3273405052
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.1506654551
Short name T7
Test name
Test status
Simulation time 201316222 ps
CPU time 3.76 seconds
Started Mar 14 12:58:30 PM PDT 24
Finished Mar 14 12:58:34 PM PDT 24
Peak memory 211160 kb
Host smart-d61b8ef2-d15c-4a77-ae89-84430527b40c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506654551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.1506654551
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.1110224484
Short name T59
Test name
Test status
Simulation time 1284616832 ps
CPU time 29.2 seconds
Started Mar 14 12:59:15 PM PDT 24
Finished Mar 14 12:59:45 PM PDT 24
Peak memory 216444 kb
Host smart-55bec90d-21d0-4114-953c-db5830194096
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110224484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.1110224484
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_stress_all_with_rand_reset.3834317138
Short name T50
Test name
Test status
Simulation time 3289702003 ps
CPU time 22.69 seconds
Started Mar 14 12:58:06 PM PDT 24
Finished Mar 14 12:58:30 PM PDT 24
Peak memory 223048 kb
Host smart-5f19edfc-1ce5-4651-81a7-25b4c793c6e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834317138 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all_with_rand_reset.3834317138
Directory /workspace/28.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.867902614
Short name T115
Test name
Test status
Simulation time 619180397 ps
CPU time 16.01 seconds
Started Mar 14 12:28:44 PM PDT 24
Finished Mar 14 12:29:00 PM PDT 24
Peak memory 214292 kb
Host smart-7cc57ca2-8dfd-4b2e-979c-e8cdd9c75f6b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=867902614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.k
eymgr_shadow_reg_errors_with_csr_rw.867902614
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.510747769
Short name T89
Test name
Test status
Simulation time 5794481511 ps
CPU time 46.47 seconds
Started Mar 14 12:58:06 PM PDT 24
Finished Mar 14 12:58:54 PM PDT 24
Peak memory 209844 kb
Host smart-c73c906d-e34c-425e-979c-a3bc451bc649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510747769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.510747769
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.4091105460
Short name T360
Test name
Test status
Simulation time 27068973333 ps
CPU time 96.99 seconds
Started Mar 14 12:57:02 PM PDT 24
Finished Mar 14 12:58:39 PM PDT 24
Peak memory 216336 kb
Host smart-97c2265f-e758-42e4-bdf9-02c937b67d3a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4091105460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.4091105460
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_stress_all_with_rand_reset.3639030267
Short name T122
Test name
Test status
Simulation time 521363031 ps
CPU time 15.59 seconds
Started Mar 14 12:58:19 PM PDT 24
Finished Mar 14 12:58:35 PM PDT 24
Peak memory 222944 kb
Host smart-30aad28c-a41f-400e-9445-1503a5d7f93d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639030267 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all_with_rand_reset.3639030267
Directory /workspace/30.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.1409825468
Short name T399
Test name
Test status
Simulation time 1624557917 ps
CPU time 45.88 seconds
Started Mar 14 12:58:42 PM PDT 24
Finished Mar 14 12:59:28 PM PDT 24
Peak memory 214628 kb
Host smart-53bf543e-623f-4a0e-89d2-5f08b5727292
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1409825468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.1409825468
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.4171701283
Short name T94
Test name
Test status
Simulation time 1872473635 ps
CPU time 58.28 seconds
Started Mar 14 12:58:10 PM PDT 24
Finished Mar 14 12:59:09 PM PDT 24
Peak memory 222756 kb
Host smart-7131b12c-1f61-4862-905d-18c13978aef8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171701283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.4171701283
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.3329984389
Short name T214
Test name
Test status
Simulation time 1436580708 ps
CPU time 31.1 seconds
Started Mar 14 12:58:18 PM PDT 24
Finished Mar 14 12:58:49 PM PDT 24
Peak memory 222688 kb
Host smart-c368a8d9-5885-4a14-8ac9-0cd15116c66f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3329984389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.3329984389
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.2594889414
Short name T334
Test name
Test status
Simulation time 296836934 ps
CPU time 15.06 seconds
Started Mar 14 12:55:58 PM PDT 24
Finished Mar 14 12:56:13 PM PDT 24
Peak memory 214636 kb
Host smart-4a4b8ba4-bcfe-496e-a097-99d8836b8063
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2594889414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.2594889414
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.1081290619
Short name T31
Test name
Test status
Simulation time 61884299 ps
CPU time 3.14 seconds
Started Mar 14 12:57:51 PM PDT 24
Finished Mar 14 12:57:55 PM PDT 24
Peak memory 217204 kb
Host smart-5651e8ac-e99b-421b-bff1-37770cf08f16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081290619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.1081290619
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.2196846288
Short name T132
Test name
Test status
Simulation time 1728988568 ps
CPU time 15.44 seconds
Started Mar 14 12:57:40 PM PDT 24
Finished Mar 14 12:57:55 PM PDT 24
Peak memory 214568 kb
Host smart-4c6a9aba-9928-4cf5-8470-d33432428efa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2196846288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.2196846288
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.244769263
Short name T44
Test name
Test status
Simulation time 1469117290 ps
CPU time 43.3 seconds
Started Mar 14 12:57:00 PM PDT 24
Finished Mar 14 12:57:43 PM PDT 24
Peak memory 216056 kb
Host smart-986ada06-0e4d-4649-9bad-ce72f7c0f663
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244769263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.244769263
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_stress_all_with_rand_reset.151507922
Short name T69
Test name
Test status
Simulation time 1469567606 ps
CPU time 19.87 seconds
Started Mar 14 12:57:18 PM PDT 24
Finished Mar 14 12:57:38 PM PDT 24
Peak memory 220928 kb
Host smart-7ed6805b-0fb3-45d0-919f-6cf64176e6d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151507922 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all_with_rand_reset.151507922
Directory /workspace/18.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.2390895604
Short name T2
Test name
Test status
Simulation time 294352353 ps
CPU time 3.63 seconds
Started Mar 14 12:57:49 PM PDT 24
Finished Mar 14 12:57:53 PM PDT 24
Peak memory 221468 kb
Host smart-677adb52-e5ed-4361-aa7a-f403db627f38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390895604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.2390895604
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.4089774908
Short name T37
Test name
Test status
Simulation time 56807278 ps
CPU time 3.73 seconds
Started Mar 14 12:58:44 PM PDT 24
Finished Mar 14 12:58:48 PM PDT 24
Peak memory 220732 kb
Host smart-dc2ec379-c8b8-44b3-af1c-27a4f3ad07c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089774908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.4089774908
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.257959633
Short name T114
Test name
Test status
Simulation time 483928060 ps
CPU time 4.15 seconds
Started Mar 14 12:29:11 PM PDT 24
Finished Mar 14 12:29:15 PM PDT 24
Peak memory 214184 kb
Host smart-1bf1792e-37b8-4358-a418-2ecdaac4c1a4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=257959633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shado
w_reg_errors.257959633
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.1591432369
Short name T226
Test name
Test status
Simulation time 324162627 ps
CPU time 5.46 seconds
Started Mar 14 12:58:44 PM PDT 24
Finished Mar 14 12:58:49 PM PDT 24
Peak memory 218560 kb
Host smart-4cb27f45-84a2-483f-bc29-bd6ccc979f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1591432369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.1591432369
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.1345304670
Short name T864
Test name
Test status
Simulation time 722904856 ps
CPU time 10.36 seconds
Started Mar 14 12:56:33 PM PDT 24
Finished Mar 14 12:56:43 PM PDT 24
Peak memory 215432 kb
Host smart-403e51f5-aa6d-4510-9900-032c07d24757
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1345304670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.1345304670
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.2990836213
Short name T34
Test name
Test status
Simulation time 76151399 ps
CPU time 2.41 seconds
Started Mar 14 12:59:01 PM PDT 24
Finished Mar 14 12:59:03 PM PDT 24
Peak memory 210168 kb
Host smart-d81d0f8c-a48e-4f94-87f3-8fe082552c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990836213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.2990836213
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.2413994674
Short name T39
Test name
Test status
Simulation time 168755163 ps
CPU time 3.44 seconds
Started Mar 14 12:56:21 PM PDT 24
Finished Mar 14 12:56:24 PM PDT 24
Peak memory 214572 kb
Host smart-360362a5-d27c-4abb-8d95-c645188894f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413994674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.2413994674
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.3564235219
Short name T290
Test name
Test status
Simulation time 273202227 ps
CPU time 7.14 seconds
Started Mar 14 12:59:10 PM PDT 24
Finished Mar 14 12:59:17 PM PDT 24
Peak memory 214632 kb
Host smart-6e5318bb-67bb-48ab-93ef-f4cfede1801c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3564235219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.3564235219
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.1756575029
Short name T17
Test name
Test status
Simulation time 105800454 ps
CPU time 1.72 seconds
Started Mar 14 12:56:19 PM PDT 24
Finished Mar 14 12:56:21 PM PDT 24
Peak memory 208952 kb
Host smart-9fe018f1-126f-4ef7-9f2e-050e8a381365
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756575029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.1756575029
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.2045302932
Short name T74
Test name
Test status
Simulation time 548647108 ps
CPU time 28.56 seconds
Started Mar 14 12:55:40 PM PDT 24
Finished Mar 14 12:56:08 PM PDT 24
Peak memory 221528 kb
Host smart-25627e04-bf22-4b89-9250-3f2986e8681f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045302932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.2045302932
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.21796954
Short name T100
Test name
Test status
Simulation time 32612297 ps
CPU time 0.72 seconds
Started Mar 14 12:57:16 PM PDT 24
Finished Mar 14 12:57:17 PM PDT 24
Peak memory 206280 kb
Host smart-7ece9417-caab-42cb-bc33-2ef59f5715d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21796954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.21796954
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.1680243052
Short name T234
Test name
Test status
Simulation time 76200514914 ps
CPU time 709.96 seconds
Started Mar 14 12:59:07 PM PDT 24
Finished Mar 14 01:10:57 PM PDT 24
Peak memory 231060 kb
Host smart-6a2d64cc-767b-4295-a5be-c73be0ef2be7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680243052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.1680243052
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.1487926498
Short name T53
Test name
Test status
Simulation time 6099946327 ps
CPU time 96.11 seconds
Started Mar 14 12:55:57 PM PDT 24
Finished Mar 14 12:57:34 PM PDT 24
Peak memory 222856 kb
Host smart-33040baa-4179-4b03-b563-dacf44c0fade
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487926498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.1487926498
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.1693035333
Short name T85
Test name
Test status
Simulation time 1653673092 ps
CPU time 8.38 seconds
Started Mar 14 12:56:48 PM PDT 24
Finished Mar 14 12:56:58 PM PDT 24
Peak memory 214664 kb
Host smart-78741e0e-960f-48cc-b21d-6ed76667d66c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1693035333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.1693035333
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.309324323
Short name T842
Test name
Test status
Simulation time 322067264 ps
CPU time 9.31 seconds
Started Mar 14 12:56:47 PM PDT 24
Finished Mar 14 12:56:57 PM PDT 24
Peak memory 214912 kb
Host smart-021af475-94a3-4414-ab9d-cf5cb62bf8eb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=309324323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.309324323
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.1706839362
Short name T159
Test name
Test status
Simulation time 511912512 ps
CPU time 12.24 seconds
Started Mar 14 12:29:07 PM PDT 24
Finished Mar 14 12:29:19 PM PDT 24
Peak memory 209268 kb
Host smart-8265ce72-b36a-4b6c-9371-f7885a9c57b2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1706839362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.1706839362
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.3656490417
Short name T41
Test name
Test status
Simulation time 55070626 ps
CPU time 4.08 seconds
Started Mar 14 12:58:02 PM PDT 24
Finished Mar 14 12:58:08 PM PDT 24
Peak memory 215400 kb
Host smart-0dbf5a83-f074-4a36-bb30-27347783fb20
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3656490417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.3656490417
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.2178521194
Short name T38
Test name
Test status
Simulation time 1305337599 ps
CPU time 18.72 seconds
Started Mar 14 12:58:15 PM PDT 24
Finished Mar 14 12:58:34 PM PDT 24
Peak memory 211284 kb
Host smart-c298952e-a20a-419d-b223-6acf303cb2db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178521194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.2178521194
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.2572557616
Short name T155
Test name
Test status
Simulation time 208748693 ps
CPU time 4.43 seconds
Started Mar 14 12:28:44 PM PDT 24
Finished Mar 14 12:28:49 PM PDT 24
Peak memory 209320 kb
Host smart-e4f8fcfb-dd4a-4a11-9f32-c25c217610be
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572557616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.2572557616
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.2083842453
Short name T61
Test name
Test status
Simulation time 3033239600 ps
CPU time 25.31 seconds
Started Mar 14 12:57:09 PM PDT 24
Finished Mar 14 12:57:35 PM PDT 24
Peak memory 216412 kb
Host smart-f3585379-ec7e-4b94-ad90-1253cd21ad83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083842453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.2083842453
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.3605881081
Short name T225
Test name
Test status
Simulation time 4726522134 ps
CPU time 107.3 seconds
Started Mar 14 12:57:38 PM PDT 24
Finished Mar 14 12:59:26 PM PDT 24
Peak memory 222848 kb
Host smart-055aef18-b3e8-40e6-a09f-019ca2acf2a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605881081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.3605881081
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.4251873758
Short name T878
Test name
Test status
Simulation time 908803679 ps
CPU time 12.24 seconds
Started Mar 14 12:58:10 PM PDT 24
Finished Mar 14 12:58:22 PM PDT 24
Peak memory 215776 kb
Host smart-27187b34-af88-49ec-8b6a-3a7f147f1a9c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4251873758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.4251873758
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.2687759525
Short name T361
Test name
Test status
Simulation time 793390074 ps
CPU time 4.61 seconds
Started Mar 14 12:55:49 PM PDT 24
Finished Mar 14 12:55:54 PM PDT 24
Peak memory 222664 kb
Host smart-1c2281bb-6992-48eb-921a-f4e627ecc364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687759525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.2687759525
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.2645735954
Short name T328
Test name
Test status
Simulation time 217784280 ps
CPU time 4.96 seconds
Started Mar 14 12:58:31 PM PDT 24
Finished Mar 14 12:58:36 PM PDT 24
Peak memory 214588 kb
Host smart-20627ca4-5168-46d9-9fa4-c9a1974fa5ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645735954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.2645735954
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.3317381903
Short name T146
Test name
Test status
Simulation time 282665611 ps
CPU time 6.77 seconds
Started Mar 14 12:28:43 PM PDT 24
Finished Mar 14 12:28:50 PM PDT 24
Peak memory 213980 kb
Host smart-32a37844-711a-4438-83c6-043566cf2029
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317381903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.3317381903
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.687769164
Short name T166
Test name
Test status
Simulation time 288570990 ps
CPU time 3.38 seconds
Started Mar 14 12:57:06 PM PDT 24
Finished Mar 14 12:57:10 PM PDT 24
Peak memory 223008 kb
Host smart-98b58484-725f-4ca6-8f8b-0562b822b42e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687769164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.687769164
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.1772703713
Short name T849
Test name
Test status
Simulation time 117778042 ps
CPU time 4.37 seconds
Started Mar 14 12:57:08 PM PDT 24
Finished Mar 14 12:57:12 PM PDT 24
Peak memory 214640 kb
Host smart-58e7f8ba-d12a-4f66-ba14-3b3be9d1c35f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1772703713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.1772703713
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.54562668
Short name T186
Test name
Test status
Simulation time 1155994238 ps
CPU time 43.23 seconds
Started Mar 14 12:58:43 PM PDT 24
Finished Mar 14 12:59:26 PM PDT 24
Peak memory 219856 kb
Host smart-cbcf9728-2b5a-400c-b89e-a51e8e78b7fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=54562668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.54562668
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.2539832693
Short name T150
Test name
Test status
Simulation time 786941684 ps
CPU time 15.33 seconds
Started Mar 14 12:29:13 PM PDT 24
Finished Mar 14 12:29:29 PM PDT 24
Peak memory 209056 kb
Host smart-d26bd06d-af9e-40b1-99df-7aaf27bc4759
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2539832693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.2539832693
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.1203492719
Short name T156
Test name
Test status
Simulation time 74283190 ps
CPU time 3.69 seconds
Started Mar 14 12:28:38 PM PDT 24
Finished Mar 14 12:28:41 PM PDT 24
Peak memory 209136 kb
Host smart-390278f6-5450-4951-97ab-d7c48c20f203
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203492719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.1203492719
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.2854367097
Short name T169
Test name
Test status
Simulation time 129272431 ps
CPU time 2.89 seconds
Started Mar 14 12:57:02 PM PDT 24
Finished Mar 14 12:57:05 PM PDT 24
Peak memory 222636 kb
Host smart-3269bce9-ea17-4a5d-9e21-84463b15ffa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2854367097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.2854367097
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.1919486405
Short name T302
Test name
Test status
Simulation time 65924784 ps
CPU time 4.82 seconds
Started Mar 14 12:55:09 PM PDT 24
Finished Mar 14 12:55:14 PM PDT 24
Peak memory 215976 kb
Host smart-2f27e0c3-988e-43a1-88d4-a8975c95a1be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1919486405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.1919486405
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_random.1575219894
Short name T101
Test name
Test status
Simulation time 65025215 ps
CPU time 3.49 seconds
Started Mar 14 12:57:35 PM PDT 24
Finished Mar 14 12:57:39 PM PDT 24
Peak memory 209600 kb
Host smart-2b599ef0-167f-4c85-838a-1ce488639bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575219894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.1575219894
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.4069026153
Short name T266
Test name
Test status
Simulation time 429486103 ps
CPU time 5.47 seconds
Started Mar 14 12:55:49 PM PDT 24
Finished Mar 14 12:55:55 PM PDT 24
Peak memory 214588 kb
Host smart-b8a9917e-f9fa-4f64-867f-96156b4c89bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069026153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.4069026153
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.2040825796
Short name T345
Test name
Test status
Simulation time 7333546434 ps
CPU time 94.11 seconds
Started Mar 14 12:58:57 PM PDT 24
Finished Mar 14 01:00:31 PM PDT 24
Peak memory 225496 kb
Host smart-b880f352-961c-4328-9203-bf7995af3007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040825796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.2040825796
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.1129028143
Short name T168
Test name
Test status
Simulation time 47782430 ps
CPU time 2.56 seconds
Started Mar 14 12:57:37 PM PDT 24
Finished Mar 14 12:57:40 PM PDT 24
Peak memory 217568 kb
Host smart-1eb1ddc7-515a-48b1-bf74-a41c8b31eb07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1129028143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.1129028143
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.8588489
Short name T165
Test name
Test status
Simulation time 224773291 ps
CPU time 6.76 seconds
Started Mar 14 12:57:36 PM PDT 24
Finished Mar 14 12:57:43 PM PDT 24
Peak memory 217860 kb
Host smart-6324ba2b-b8ec-4501-9af9-60dad124c033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=8588489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.8588489
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.686692832
Short name T171
Test name
Test status
Simulation time 35619241 ps
CPU time 2.4 seconds
Started Mar 14 12:59:20 PM PDT 24
Finished Mar 14 12:59:22 PM PDT 24
Peak memory 223028 kb
Host smart-90113977-75f0-4c0b-8e19-d6190d81df7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=686692832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.686692832
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.2019138447
Short name T172
Test name
Test status
Simulation time 217483981 ps
CPU time 4.02 seconds
Started Mar 14 12:56:18 PM PDT 24
Finished Mar 14 12:56:22 PM PDT 24
Peak memory 222940 kb
Host smart-257f0f03-9209-4a07-be7c-a9b102169b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019138447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.2019138447
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.2828183233
Short name T373
Test name
Test status
Simulation time 937855915 ps
CPU time 8.98 seconds
Started Mar 14 12:56:33 PM PDT 24
Finished Mar 14 12:56:43 PM PDT 24
Peak memory 214572 kb
Host smart-bb08ceaf-a923-4b4b-a154-7a9e167675da
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2828183233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.2828183233
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.2764270261
Short name T241
Test name
Test status
Simulation time 121128556 ps
CPU time 4.61 seconds
Started Mar 14 12:57:01 PM PDT 24
Finished Mar 14 12:57:06 PM PDT 24
Peak memory 214572 kb
Host smart-9f9b525e-3863-4646-902b-6170917a6034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764270261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.2764270261
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.957720975
Short name T521
Test name
Test status
Simulation time 227754875 ps
CPU time 7.15 seconds
Started Mar 14 12:57:11 PM PDT 24
Finished Mar 14 12:57:18 PM PDT 24
Peak memory 208844 kb
Host smart-ad28748b-bb12-4432-90ea-e31419803fd0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=957720975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.957720975
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_stress_all_with_rand_reset.1179107040
Short name T123
Test name
Test status
Simulation time 1468135189 ps
CPU time 22.75 seconds
Started Mar 14 12:57:15 PM PDT 24
Finished Mar 14 12:57:38 PM PDT 24
Peak memory 221436 kb
Host smart-d7591ba2-0dd5-46f1-af8f-0240f00713be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179107040 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all_with_rand_reset.1179107040
Directory /workspace/19.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.keymgr_stress_all_with_rand_reset.1053292459
Short name T48
Test name
Test status
Simulation time 218552333 ps
CPU time 14.88 seconds
Started Mar 14 12:55:42 PM PDT 24
Finished Mar 14 12:55:57 PM PDT 24
Peak memory 223384 kb
Host smart-025e7fd8-9fc3-428b-b57a-a87a7b9750b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1053292459 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all_with_rand_reset.1053292459
Directory /workspace/2.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.2579492861
Short name T30
Test name
Test status
Simulation time 6890956632 ps
CPU time 100.22 seconds
Started Mar 14 12:57:51 PM PDT 24
Finished Mar 14 12:59:31 PM PDT 24
Peak memory 222852 kb
Host smart-6ba1b47b-f249-480a-aea0-ea057e6dbff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2579492861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.2579492861
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.2589371749
Short name T299
Test name
Test status
Simulation time 519383155 ps
CPU time 14.31 seconds
Started Mar 14 12:58:03 PM PDT 24
Finished Mar 14 12:58:19 PM PDT 24
Peak memory 209688 kb
Host smart-a2efaa52-fc59-423c-8947-9ab8e3d1aa73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2589371749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.2589371749
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.315693937
Short name T237
Test name
Test status
Simulation time 134835216 ps
CPU time 7.41 seconds
Started Mar 14 12:58:21 PM PDT 24
Finished Mar 14 12:58:29 PM PDT 24
Peak memory 215044 kb
Host smart-ae1a38d7-2cd2-48f4-9aa6-98652f8d12d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=315693937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.315693937
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.498243851
Short name T68
Test name
Test status
Simulation time 5560733303 ps
CPU time 56.14 seconds
Started Mar 14 12:58:15 PM PDT 24
Finished Mar 14 12:59:11 PM PDT 24
Peak memory 222968 kb
Host smart-c547007e-faee-412a-a720-f93221974560
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498243851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.498243851
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.584768809
Short name T784
Test name
Test status
Simulation time 659021776 ps
CPU time 8.47 seconds
Started Mar 14 12:59:16 PM PDT 24
Finished Mar 14 12:59:25 PM PDT 24
Peak memory 214616 kb
Host smart-f024db51-b7a4-4cd2-841e-edb80bb71e0c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=584768809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.584768809
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.3350190243
Short name T291
Test name
Test status
Simulation time 74977299 ps
CPU time 4.23 seconds
Started Mar 14 12:59:14 PM PDT 24
Finished Mar 14 12:59:19 PM PDT 24
Peak memory 222708 kb
Host smart-8ceea3e0-6d6f-4b8f-ae80-8dd11411d3f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350190243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.3350190243
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.476279073
Short name T45
Test name
Test status
Simulation time 140512390 ps
CPU time 3.61 seconds
Started Mar 14 12:59:22 PM PDT 24
Finished Mar 14 12:59:26 PM PDT 24
Peak memory 214652 kb
Host smart-2a21a8a4-f8a6-4409-931f-cae9750e2530
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=476279073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.476279073
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.3148394516
Short name T152
Test name
Test status
Simulation time 401702940 ps
CPU time 9.78 seconds
Started Mar 14 12:29:07 PM PDT 24
Finished Mar 14 12:29:17 PM PDT 24
Peak memory 218108 kb
Host smart-1178242f-518b-4cce-b71a-dcbb2dbdcdf9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3148394516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.3148394516
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.3228422344
Short name T149
Test name
Test status
Simulation time 2183800155 ps
CPU time 8.2 seconds
Started Mar 14 12:28:59 PM PDT 24
Finished Mar 14 12:29:07 PM PDT 24
Peak memory 208952 kb
Host smart-ecf289af-416b-4969-8e89-108d8878c9fc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3228422344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.3228422344
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.2027881082
Short name T157
Test name
Test status
Simulation time 481672696 ps
CPU time 13 seconds
Started Mar 14 12:29:06 PM PDT 24
Finished Mar 14 12:29:19 PM PDT 24
Peak memory 213944 kb
Host smart-73c50367-c7ce-4fe6-bb2a-16fedb207cd8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027881082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.2027881082
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.2476125775
Short name T144
Test name
Test status
Simulation time 144472947 ps
CPU time 2.39 seconds
Started Mar 14 12:55:21 PM PDT 24
Finished Mar 14 12:55:24 PM PDT 24
Peak memory 210396 kb
Host smart-ba21d229-34f7-4e91-88fb-18aa6fb5d6b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476125775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.2476125775
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.866475816
Short name T148
Test name
Test status
Simulation time 36677479 ps
CPU time 2.34 seconds
Started Mar 14 12:59:14 PM PDT 24
Finished Mar 14 12:59:17 PM PDT 24
Peak memory 210164 kb
Host smart-7373950b-d3a0-4b47-9a81-675aef0edf53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866475816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.866475816
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.1125312263
Short name T173
Test name
Test status
Simulation time 144181929 ps
CPU time 6.09 seconds
Started Mar 14 12:57:02 PM PDT 24
Finished Mar 14 12:57:09 PM PDT 24
Peak memory 217828 kb
Host smart-f155b67e-9fc9-4a12-a45d-c1f988526d84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1125312263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.1125312263
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.4254081681
Short name T167
Test name
Test status
Simulation time 48291456 ps
CPU time 3.27 seconds
Started Mar 14 12:56:34 PM PDT 24
Finished Mar 14 12:56:37 PM PDT 24
Peak memory 223012 kb
Host smart-1c7f3717-1197-429d-a2e0-05457e0cc8f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4254081681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.4254081681
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.3461934690
Short name T63
Test name
Test status
Simulation time 68257763 ps
CPU time 3.79 seconds
Started Mar 14 12:59:02 PM PDT 24
Finished Mar 14 12:59:05 PM PDT 24
Peak memory 218444 kb
Host smart-6ec3e68d-eca1-4ea5-a2f2-f12e80e9439e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3461934690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.3461934690
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_stress_all_with_rand_reset.102543350
Short name T110
Test name
Test status
Simulation time 369246476 ps
CPU time 7.56 seconds
Started Mar 14 12:55:11 PM PDT 24
Finished Mar 14 12:55:19 PM PDT 24
Peak memory 219384 kb
Host smart-c8c90c48-2141-4ba5-8a42-d746f7d53a88
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=102543350 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all_with_rand_reset.102543350
Directory /workspace/0.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.2260360668
Short name T502
Test name
Test status
Simulation time 856517981 ps
CPU time 17.16 seconds
Started Mar 14 12:55:10 PM PDT 24
Finished Mar 14 12:55:28 PM PDT 24
Peak memory 210572 kb
Host smart-e40c9ddc-f8d7-49ed-b564-05a4242aa6b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260360668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.2260360668
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.3936224848
Short name T92
Test name
Test status
Simulation time 105926437 ps
CPU time 4.57 seconds
Started Mar 14 12:56:48 PM PDT 24
Finished Mar 14 12:56:54 PM PDT 24
Peak memory 214556 kb
Host smart-1c2cc804-0312-4a99-97a5-4c34b77c9340
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936224848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.3936224848
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.3017813753
Short name T726
Test name
Test status
Simulation time 1155844096 ps
CPU time 16.02 seconds
Started Mar 14 12:56:47 PM PDT 24
Finished Mar 14 12:57:04 PM PDT 24
Peak memory 215260 kb
Host smart-ffffa480-c5b0-4808-9da2-e315bf9f2158
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017813753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.3017813753
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.2848032219
Short name T221
Test name
Test status
Simulation time 86463845 ps
CPU time 4.43 seconds
Started Mar 14 12:56:48 PM PDT 24
Finished Mar 14 12:56:53 PM PDT 24
Peak memory 211416 kb
Host smart-a7e8d031-da71-4913-a2fe-78bb2343c55f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2848032219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.2848032219
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.1547588634
Short name T402
Test name
Test status
Simulation time 480917341 ps
CPU time 3.27 seconds
Started Mar 14 12:57:21 PM PDT 24
Finished Mar 14 12:57:25 PM PDT 24
Peak memory 214444 kb
Host smart-33001be1-e44e-45ac-9a07-56e77c273713
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1547588634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.1547588634
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.3278432856
Short name T228
Test name
Test status
Simulation time 244025337 ps
CPU time 3.99 seconds
Started Mar 14 12:57:16 PM PDT 24
Finished Mar 14 12:57:20 PM PDT 24
Peak memory 219320 kb
Host smart-0ccad27a-a826-4553-82b8-1f08f3654477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278432856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.3278432856
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_stress_all_with_rand_reset.2161733119
Short name T352
Test name
Test status
Simulation time 336748583 ps
CPU time 13.72 seconds
Started Mar 14 12:57:40 PM PDT 24
Finished Mar 14 12:57:54 PM PDT 24
Peak memory 222948 kb
Host smart-247c6285-84bb-4225-9246-46f98a413bc7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161733119 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all_with_rand_reset.2161733119
Directory /workspace/22.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.2798833306
Short name T230
Test name
Test status
Simulation time 1309945189 ps
CPU time 55.05 seconds
Started Mar 14 12:57:50 PM PDT 24
Finished Mar 14 12:58:45 PM PDT 24
Peak memory 218080 kb
Host smart-aeb9d4aa-d6ca-4c26-9277-65df5d266789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798833306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.2798833306
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.3514768852
Short name T211
Test name
Test status
Simulation time 437764234 ps
CPU time 4.69 seconds
Started Mar 14 12:58:10 PM PDT 24
Finished Mar 14 12:58:16 PM PDT 24
Peak memory 219020 kb
Host smart-145c4e0e-f70d-4de3-9773-185b93de5d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514768852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.3514768852
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.1075290714
Short name T343
Test name
Test status
Simulation time 240657165 ps
CPU time 10.74 seconds
Started Mar 14 12:58:28 PM PDT 24
Finished Mar 14 12:58:40 PM PDT 24
Peak memory 219724 kb
Host smart-7dc1d4fd-58c0-4d57-84ad-97ce00fd7010
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075290714 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.1075290714
Directory /workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.1443097635
Short name T97
Test name
Test status
Simulation time 3125946612 ps
CPU time 57.3 seconds
Started Mar 14 12:58:30 PM PDT 24
Finished Mar 14 12:59:27 PM PDT 24
Peak memory 222728 kb
Host smart-7ab5dc85-7897-42d5-b5e4-646d840f2f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443097635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.1443097635
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.2509054477
Short name T174
Test name
Test status
Simulation time 1648263827 ps
CPU time 26.97 seconds
Started Mar 14 12:57:16 PM PDT 24
Finished Mar 14 12:57:43 PM PDT 24
Peak memory 218040 kb
Host smart-e71e0217-6fc2-4e34-a56d-0c857b378119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509054477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.2509054477
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.4037970893
Short name T170
Test name
Test status
Simulation time 311130434 ps
CPU time 9.25 seconds
Started Mar 14 12:58:43 PM PDT 24
Finished Mar 14 12:58:53 PM PDT 24
Peak memory 218624 kb
Host smart-31c90717-c59a-47c8-a0df-70d105b34681
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037970893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.4037970893
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.2905227484
Short name T175
Test name
Test status
Simulation time 2173845233 ps
CPU time 13.21 seconds
Started Mar 14 12:59:23 PM PDT 24
Finished Mar 14 12:59:37 PM PDT 24
Peak memory 216736 kb
Host smart-31fb75b7-92ca-428b-9b19-bc726a109d8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905227484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.2905227484
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.2449754010
Short name T1034
Test name
Test status
Simulation time 130718550 ps
CPU time 4.34 seconds
Started Mar 14 12:28:44 PM PDT 24
Finished Mar 14 12:28:48 PM PDT 24
Peak memory 205824 kb
Host smart-b7ab10f2-6de1-44d8-a6ac-45ea26aad764
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2449754010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.2
449754010
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.3434739190
Short name T920
Test name
Test status
Simulation time 436915429 ps
CPU time 11.48 seconds
Started Mar 14 12:28:35 PM PDT 24
Finished Mar 14 12:28:46 PM PDT 24
Peak memory 205712 kb
Host smart-4636a76c-63a7-4646-ab25-dc6c09e75a19
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434739190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.3
434739190
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.2211584431
Short name T1038
Test name
Test status
Simulation time 19480124 ps
CPU time 0.89 seconds
Started Mar 14 12:28:30 PM PDT 24
Finished Mar 14 12:28:31 PM PDT 24
Peak memory 205600 kb
Host smart-7ec2ca54-5238-4b82-89bc-093f56c81abc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2211584431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.2
211584431
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.3817493613
Short name T1009
Test name
Test status
Simulation time 262453542 ps
CPU time 1.1 seconds
Started Mar 14 12:28:39 PM PDT 24
Finished Mar 14 12:28:41 PM PDT 24
Peak memory 205852 kb
Host smart-3defa9ff-bd00-49c1-b7c1-a8bc2811d216
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3817493613 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.3817493613
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.3949513517
Short name T923
Test name
Test status
Simulation time 134436421 ps
CPU time 0.94 seconds
Started Mar 14 12:28:38 PM PDT 24
Finished Mar 14 12:28:39 PM PDT 24
Peak memory 205604 kb
Host smart-a2b47ad2-16c4-4c99-bae0-d01a4840284c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949513517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.3949513517
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.1678628409
Short name T1070
Test name
Test status
Simulation time 23825272 ps
CPU time 0.84 seconds
Started Mar 14 12:28:42 PM PDT 24
Finished Mar 14 12:28:43 PM PDT 24
Peak memory 205356 kb
Host smart-ada80870-fcf4-4331-92b2-b87f427697e0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1678628409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.1678628409
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.3750718285
Short name T927
Test name
Test status
Simulation time 63765970 ps
CPU time 1.89 seconds
Started Mar 14 12:28:44 PM PDT 24
Finished Mar 14 12:28:46 PM PDT 24
Peak memory 205640 kb
Host smart-a73e9bb7-705e-49c2-af5e-119afe57e7c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750718285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.3750718285
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.3494745882
Short name T932
Test name
Test status
Simulation time 871565840 ps
CPU time 2.68 seconds
Started Mar 14 12:28:42 PM PDT 24
Finished Mar 14 12:28:44 PM PDT 24
Peak memory 214140 kb
Host smart-01184fbc-cb10-4412-a9c9-84c912071f00
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494745882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.3494745882
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.753839829
Short name T922
Test name
Test status
Simulation time 172104358 ps
CPU time 3.88 seconds
Started Mar 14 12:28:47 PM PDT 24
Finished Mar 14 12:28:51 PM PDT 24
Peak memory 214268 kb
Host smart-640fcc10-8b13-4457-bc82-6136e53f0bd0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=753839829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.k
eymgr_shadow_reg_errors_with_csr_rw.753839829
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.1213779864
Short name T977
Test name
Test status
Simulation time 136673925 ps
CPU time 4.24 seconds
Started Mar 14 12:28:42 PM PDT 24
Finished Mar 14 12:28:46 PM PDT 24
Peak memory 213852 kb
Host smart-d7ec0ed3-2bf5-450b-8847-4119f82e4507
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213779864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.1213779864
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.235031940
Short name T147
Test name
Test status
Simulation time 1190360110 ps
CPU time 5.12 seconds
Started Mar 14 12:28:24 PM PDT 24
Finished Mar 14 12:28:29 PM PDT 24
Peak memory 209152 kb
Host smart-d2b89209-acbb-49d5-94d1-f0ff5c6d647a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235031940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err.
235031940
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.2127401150
Short name T181
Test name
Test status
Simulation time 958239430 ps
CPU time 5.46 seconds
Started Mar 14 12:28:41 PM PDT 24
Finished Mar 14 12:28:47 PM PDT 24
Peak memory 205816 kb
Host smart-78a7981e-34ca-4009-8801-e4f586ef21e6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2127401150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.2
127401150
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.3577364610
Short name T960
Test name
Test status
Simulation time 2306423497 ps
CPU time 17.62 seconds
Started Mar 14 12:28:41 PM PDT 24
Finished Mar 14 12:28:59 PM PDT 24
Peak memory 205732 kb
Host smart-f78cf82e-93ff-4488-9621-8d47bf7094d5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3577364610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.3
577364610
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.1331542660
Short name T933
Test name
Test status
Simulation time 57419834 ps
CPU time 1.08 seconds
Started Mar 14 12:28:41 PM PDT 24
Finished Mar 14 12:28:42 PM PDT 24
Peak memory 205672 kb
Host smart-8defe26e-ea54-44fd-b6d9-e2b5bcfbee63
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331542660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.1
331542660
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.843090700
Short name T1007
Test name
Test status
Simulation time 23894491 ps
CPU time 1.36 seconds
Started Mar 14 12:28:39 PM PDT 24
Finished Mar 14 12:28:40 PM PDT 24
Peak memory 205832 kb
Host smart-81cb5057-559a-496d-b0c3-c9ebd434ce0a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843090700 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.843090700
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.2786651526
Short name T1064
Test name
Test status
Simulation time 23804957 ps
CPU time 0.89 seconds
Started Mar 14 12:28:52 PM PDT 24
Finished Mar 14 12:28:53 PM PDT 24
Peak memory 205608 kb
Host smart-448d3777-ed04-4240-9b47-b167bbfce597
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786651526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.2786651526
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.3496577270
Short name T985
Test name
Test status
Simulation time 10925556 ps
CPU time 0.82 seconds
Started Mar 14 12:28:24 PM PDT 24
Finished Mar 14 12:28:28 PM PDT 24
Peak memory 205468 kb
Host smart-f2eb726e-e270-4e95-9f83-e04d44413c1d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496577270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.3496577270
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.1736054747
Short name T1018
Test name
Test status
Simulation time 57335072 ps
CPU time 2.08 seconds
Started Mar 14 12:28:40 PM PDT 24
Finished Mar 14 12:28:42 PM PDT 24
Peak memory 205768 kb
Host smart-be808e87-67f1-45bd-b78f-1f33d174be18
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1736054747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sa
me_csr_outstanding.1736054747
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.4272447060
Short name T1050
Test name
Test status
Simulation time 521275524 ps
CPU time 3.76 seconds
Started Mar 14 12:28:24 PM PDT 24
Finished Mar 14 12:28:31 PM PDT 24
Peak memory 218964 kb
Host smart-1e2de28d-7fef-4a6a-b6ce-1683a3e2c41f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272447060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.4272447060
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.847822349
Short name T934
Test name
Test status
Simulation time 184071355 ps
CPU time 6.27 seconds
Started Mar 14 12:28:20 PM PDT 24
Finished Mar 14 12:28:26 PM PDT 24
Peak memory 214320 kb
Host smart-62dd2cf8-c9c6-467d-998b-ddb9e8957048
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847822349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.k
eymgr_shadow_reg_errors_with_csr_rw.847822349
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.4044733555
Short name T983
Test name
Test status
Simulation time 145524538 ps
CPU time 3.25 seconds
Started Mar 14 12:28:39 PM PDT 24
Finished Mar 14 12:28:42 PM PDT 24
Peak memory 217200 kb
Host smart-ec147539-7d7e-421e-9222-d597d7bd18ba
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4044733555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.4044733555
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.332091721
Short name T1002
Test name
Test status
Simulation time 529699846 ps
CPU time 4.92 seconds
Started Mar 14 12:28:35 PM PDT 24
Finished Mar 14 12:28:40 PM PDT 24
Peak memory 209356 kb
Host smart-c3fe586b-4ce5-4288-8428-ae1d901227ff
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=332091721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err.
332091721
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.3157788788
Short name T993
Test name
Test status
Simulation time 82949294 ps
CPU time 1.6 seconds
Started Mar 14 12:28:54 PM PDT 24
Finished Mar 14 12:28:56 PM PDT 24
Peak memory 216904 kb
Host smart-1ba0731d-6f16-46e3-846d-a39860dab3d7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3157788788 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.3157788788
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.658428690
Short name T1016
Test name
Test status
Simulation time 24223999 ps
CPU time 1.41 seconds
Started Mar 14 12:28:58 PM PDT 24
Finished Mar 14 12:29:00 PM PDT 24
Peak memory 205548 kb
Host smart-70623b37-3c1b-40f4-b3b8-e6e29fa21b09
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658428690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.658428690
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.736410018
Short name T1011
Test name
Test status
Simulation time 21192782 ps
CPU time 0.8 seconds
Started Mar 14 12:28:44 PM PDT 24
Finished Mar 14 12:28:50 PM PDT 24
Peak memory 205548 kb
Host smart-6fa5f716-c7f5-4f64-be9e-c226e6b60ea5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736410018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.736410018
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.2885545609
Short name T944
Test name
Test status
Simulation time 91814619 ps
CPU time 1.64 seconds
Started Mar 14 12:29:46 PM PDT 24
Finished Mar 14 12:29:48 PM PDT 24
Peak memory 205688 kb
Host smart-421b8913-a643-4231-9a4a-6c5458f9a50c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885545609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.2885545609
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.2497766595
Short name T1000
Test name
Test status
Simulation time 847062663 ps
CPU time 13.2 seconds
Started Mar 14 12:28:38 PM PDT 24
Finished Mar 14 12:28:51 PM PDT 24
Peak memory 214588 kb
Host smart-833d6d81-aeee-4f20-bd4d-437923a719ea
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497766595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.2497766595
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.3586224379
Short name T117
Test name
Test status
Simulation time 250986258 ps
CPU time 6 seconds
Started Mar 14 12:29:46 PM PDT 24
Finished Mar 14 12:29:52 PM PDT 24
Peak memory 214308 kb
Host smart-48a3b9f4-600f-4227-ac08-4cef89d2db2e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3586224379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.keymgr_shadow_reg_errors_with_csr_rw.3586224379
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.2197848396
Short name T1006
Test name
Test status
Simulation time 569894993 ps
CPU time 4.68 seconds
Started Mar 14 12:28:36 PM PDT 24
Finished Mar 14 12:28:41 PM PDT 24
Peak memory 214100 kb
Host smart-8821fdab-5272-4bc7-b6ba-7bf979e3007c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197848396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.2197848396
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.3569129243
Short name T143
Test name
Test status
Simulation time 777978994 ps
CPU time 21.05 seconds
Started Mar 14 12:29:46 PM PDT 24
Finished Mar 14 12:30:07 PM PDT 24
Peak memory 209076 kb
Host smart-550540a1-6540-4b98-b68e-5284341edc3b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3569129243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_er
r.3569129243
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.2789195673
Short name T978
Test name
Test status
Simulation time 110512457 ps
CPU time 1.56 seconds
Started Mar 14 12:29:09 PM PDT 24
Finished Mar 14 12:29:11 PM PDT 24
Peak memory 216864 kb
Host smart-510704f7-d0cc-433c-ad44-a3d86dff5a9c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789195673 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.2789195673
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.585091016
Short name T956
Test name
Test status
Simulation time 63614161 ps
CPU time 1.19 seconds
Started Mar 14 12:29:09 PM PDT 24
Finished Mar 14 12:29:10 PM PDT 24
Peak memory 205800 kb
Host smart-148e6b6c-edf0-4994-9fc0-112f6d8fba99
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=585091016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.585091016
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.3321561628
Short name T969
Test name
Test status
Simulation time 20587864 ps
CPU time 0.67 seconds
Started Mar 14 12:28:46 PM PDT 24
Finished Mar 14 12:28:47 PM PDT 24
Peak memory 205420 kb
Host smart-1c77595f-214d-4625-be11-8434ffcff8bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321561628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.3321561628
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.2955775796
Short name T990
Test name
Test status
Simulation time 125276922 ps
CPU time 1.86 seconds
Started Mar 14 12:29:00 PM PDT 24
Finished Mar 14 12:29:02 PM PDT 24
Peak memory 205728 kb
Host smart-39079363-187e-44af-a499-091362128265
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2955775796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s
ame_csr_outstanding.2955775796
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.331836839
Short name T1035
Test name
Test status
Simulation time 1169913309 ps
CPU time 25.57 seconds
Started Mar 14 12:28:57 PM PDT 24
Finished Mar 14 12:29:22 PM PDT 24
Peak memory 220288 kb
Host smart-cceda3b4-665e-4448-a20c-6b597f7225ef
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331836839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shado
w_reg_errors.331836839
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.288468520
Short name T111
Test name
Test status
Simulation time 156022583 ps
CPU time 3.61 seconds
Started Mar 14 12:28:48 PM PDT 24
Finished Mar 14 12:28:52 PM PDT 24
Peak memory 220076 kb
Host smart-7ebeeb07-fcd8-4d4a-91dd-52887a71a498
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288468520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
keymgr_shadow_reg_errors_with_csr_rw.288468520
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.159518515
Short name T919
Test name
Test status
Simulation time 89421997 ps
CPU time 1.55 seconds
Started Mar 14 12:28:44 PM PDT 24
Finished Mar 14 12:28:46 PM PDT 24
Peak memory 213932 kb
Host smart-c0178e3a-5e18-4953-be19-33ac92416d17
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159518515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.159518515
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.3650905073
Short name T162
Test name
Test status
Simulation time 235133032 ps
CPU time 5.7 seconds
Started Mar 14 12:28:56 PM PDT 24
Finished Mar 14 12:29:02 PM PDT 24
Peak memory 208868 kb
Host smart-8c173da6-ad0f-4fc5-830f-9c36e6e058ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650905073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.3650905073
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.1827146341
Short name T929
Test name
Test status
Simulation time 209002704 ps
CPU time 1.48 seconds
Started Mar 14 12:28:47 PM PDT 24
Finished Mar 14 12:28:49 PM PDT 24
Peak memory 214040 kb
Host smart-9dba1f2f-640e-4e7c-ad34-b2b71ed7b11d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827146341 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.1827146341
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.1866064593
Short name T1039
Test name
Test status
Simulation time 36600859 ps
CPU time 1.4 seconds
Started Mar 14 12:29:16 PM PDT 24
Finished Mar 14 12:29:18 PM PDT 24
Peak memory 205788 kb
Host smart-5ae1b17c-ddc4-45db-89d9-eac77cdb7948
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1866064593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.1866064593
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.38696308
Short name T957
Test name
Test status
Simulation time 12897788 ps
CPU time 0.85 seconds
Started Mar 14 12:28:48 PM PDT 24
Finished Mar 14 12:28:49 PM PDT 24
Peak memory 205688 kb
Host smart-8cd700f1-92fd-437c-b945-b6d217e9eddd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38696308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.38696308
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.1562264126
Short name T1015
Test name
Test status
Simulation time 127641594 ps
CPU time 4.2 seconds
Started Mar 14 12:28:45 PM PDT 24
Finished Mar 14 12:28:50 PM PDT 24
Peak memory 205720 kb
Host smart-d0db80ad-7e4e-44c1-9bc0-a5f831120807
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562264126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.1562264126
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.1220365543
Short name T118
Test name
Test status
Simulation time 65785408 ps
CPU time 1.92 seconds
Started Mar 14 12:28:47 PM PDT 24
Finished Mar 14 12:28:50 PM PDT 24
Peak memory 222464 kb
Host smart-0a645291-613a-4987-b722-c10b97a6a6f8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1220365543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.1220365543
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.2455959484
Short name T964
Test name
Test status
Simulation time 2336232053 ps
CPU time 10.25 seconds
Started Mar 14 12:29:03 PM PDT 24
Finished Mar 14 12:29:14 PM PDT 24
Peak memory 214384 kb
Host smart-903c3dc4-2523-420d-8b36-37bb43d061d4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455959484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.2455959484
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.2977275177
Short name T972
Test name
Test status
Simulation time 102801036 ps
CPU time 1.97 seconds
Started Mar 14 12:29:02 PM PDT 24
Finished Mar 14 12:29:04 PM PDT 24
Peak memory 215988 kb
Host smart-1c8bf986-c4da-4a3b-8d96-ee8736f0e033
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977275177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.2977275177
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.2417549147
Short name T183
Test name
Test status
Simulation time 66962950 ps
CPU time 1.21 seconds
Started Mar 14 12:29:13 PM PDT 24
Finished Mar 14 12:29:14 PM PDT 24
Peak memory 213912 kb
Host smart-d86a5d35-7a75-4be5-9fdd-bc364db3eea7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417549147 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.2417549147
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.658458923
Short name T1031
Test name
Test status
Simulation time 33038866 ps
CPU time 1.06 seconds
Started Mar 14 12:28:59 PM PDT 24
Finished Mar 14 12:29:00 PM PDT 24
Peak memory 205868 kb
Host smart-29bb1f68-da13-4b20-b58b-f79b2c622aaa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658458923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.658458923
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.2786881852
Short name T1066
Test name
Test status
Simulation time 9653823 ps
CPU time 0.77 seconds
Started Mar 14 12:28:43 PM PDT 24
Finished Mar 14 12:28:44 PM PDT 24
Peak memory 205488 kb
Host smart-41630448-a980-4798-bdd8-d7c22c089537
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786881852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.2786881852
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.4286262592
Short name T1042
Test name
Test status
Simulation time 61352304 ps
CPU time 1.78 seconds
Started Mar 14 12:29:06 PM PDT 24
Finished Mar 14 12:29:08 PM PDT 24
Peak memory 205692 kb
Host smart-f2ae257e-5ca1-488c-860b-841b2de1a347
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4286262592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.4286262592
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.2550893011
Short name T119
Test name
Test status
Simulation time 488665896 ps
CPU time 14.25 seconds
Started Mar 14 12:28:44 PM PDT 24
Finished Mar 14 12:28:59 PM PDT 24
Peak memory 214356 kb
Host smart-f05de707-10e9-4a87-8e1e-c5eb2c678a35
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550893011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.2550893011
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.2292523856
Short name T1023
Test name
Test status
Simulation time 199834277 ps
CPU time 4.7 seconds
Started Mar 14 12:28:57 PM PDT 24
Finished Mar 14 12:29:02 PM PDT 24
Peak memory 220008 kb
Host smart-752432b5-a71e-4ecf-b9d6-f63079470680
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2292523856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.2292523856
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.1464334798
Short name T971
Test name
Test status
Simulation time 657173771 ps
CPU time 3.45 seconds
Started Mar 14 12:28:48 PM PDT 24
Finished Mar 14 12:28:52 PM PDT 24
Peak memory 217092 kb
Host smart-f97ce889-6bc6-42f5-98f3-b94530dc99f3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464334798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.1464334798
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.1418129924
Short name T916
Test name
Test status
Simulation time 210385786 ps
CPU time 3.09 seconds
Started Mar 14 12:29:05 PM PDT 24
Finished Mar 14 12:29:08 PM PDT 24
Peak memory 208904 kb
Host smart-c8094fa1-7764-4f5e-9d29-3ae15453e2f8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1418129924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er
r.1418129924
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.1247577949
Short name T942
Test name
Test status
Simulation time 419129326 ps
CPU time 1.63 seconds
Started Mar 14 12:29:11 PM PDT 24
Finished Mar 14 12:29:12 PM PDT 24
Peak memory 214024 kb
Host smart-5d7e639f-5585-4b80-8f39-3c28c5bd48fe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247577949 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.1247577949
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.419969937
Short name T996
Test name
Test status
Simulation time 12743653 ps
CPU time 0.87 seconds
Started Mar 14 12:29:04 PM PDT 24
Finished Mar 14 12:29:05 PM PDT 24
Peak memory 205604 kb
Host smart-d3a59525-7070-4399-853c-16c907885e7e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419969937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.419969937
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.3769346392
Short name T940
Test name
Test status
Simulation time 11505341 ps
CPU time 0.66 seconds
Started Mar 14 12:28:46 PM PDT 24
Finished Mar 14 12:28:47 PM PDT 24
Peak memory 205488 kb
Host smart-0559bff1-e4a7-4039-8c24-decbac63c009
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769346392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.3769346392
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.4090404190
Short name T1048
Test name
Test status
Simulation time 22645134 ps
CPU time 1.22 seconds
Started Mar 14 12:29:06 PM PDT 24
Finished Mar 14 12:29:08 PM PDT 24
Peak memory 205680 kb
Host smart-041bfcfb-d098-4c1f-a8bf-0a7c9db0f9f6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090404190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s
ame_csr_outstanding.4090404190
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.1980897415
Short name T1072
Test name
Test status
Simulation time 554389859 ps
CPU time 7.6 seconds
Started Mar 14 12:29:03 PM PDT 24
Finished Mar 14 12:29:11 PM PDT 24
Peak memory 214292 kb
Host smart-e92f5a99-94d6-4252-9b24-0c70d427bd59
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980897415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.1980897415
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.1292782304
Short name T1054
Test name
Test status
Simulation time 160736493 ps
CPU time 7.82 seconds
Started Mar 14 12:28:53 PM PDT 24
Finished Mar 14 12:29:01 PM PDT 24
Peak memory 214200 kb
Host smart-40acc76e-e28a-4884-ac65-c03dc51fbdd2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292782304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.1292782304
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.3276578385
Short name T958
Test name
Test status
Simulation time 28885884 ps
CPU time 1.53 seconds
Started Mar 14 12:28:47 PM PDT 24
Finished Mar 14 12:28:48 PM PDT 24
Peak memory 205684 kb
Host smart-9a5f0339-3927-42e8-a08a-d58058fc2ddc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276578385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.3276578385
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.2024102816
Short name T369
Test name
Test status
Simulation time 174983815 ps
CPU time 6.71 seconds
Started Mar 14 12:28:57 PM PDT 24
Finished Mar 14 12:29:04 PM PDT 24
Peak memory 209232 kb
Host smart-10e99036-7fd7-44d0-9d88-688bc7af4cdc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2024102816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.2024102816
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.3971117023
Short name T963
Test name
Test status
Simulation time 36366047 ps
CPU time 2.62 seconds
Started Mar 14 12:29:06 PM PDT 24
Finished Mar 14 12:29:09 PM PDT 24
Peak memory 213996 kb
Host smart-da4b8889-a0d1-4c96-954c-f6f722923e23
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3971117023 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.3971117023
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.3045710167
Short name T979
Test name
Test status
Simulation time 12023360 ps
CPU time 0.85 seconds
Started Mar 14 12:28:45 PM PDT 24
Finished Mar 14 12:28:46 PM PDT 24
Peak memory 205688 kb
Host smart-90cf8d33-75e6-4233-a0a1-ea0288953767
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3045710167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.3045710167
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.1528216300
Short name T974
Test name
Test status
Simulation time 8507015 ps
CPU time 0.77 seconds
Started Mar 14 12:29:01 PM PDT 24
Finished Mar 14 12:29:02 PM PDT 24
Peak memory 205448 kb
Host smart-2fc954ce-3f61-4c2f-a3d8-86870baf6c75
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528216300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.1528216300
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.2264038551
Short name T1028
Test name
Test status
Simulation time 126250380 ps
CPU time 2.01 seconds
Started Mar 14 12:28:53 PM PDT 24
Finished Mar 14 12:28:55 PM PDT 24
Peak memory 205788 kb
Host smart-0fe30d08-03b9-4514-9123-0845b6eb4bd4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2264038551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.2264038551
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.3764890302
Short name T1069
Test name
Test status
Simulation time 168319198 ps
CPU time 3.24 seconds
Started Mar 14 12:29:34 PM PDT 24
Finished Mar 14 12:29:38 PM PDT 24
Peak memory 214284 kb
Host smart-d25d6230-1ad1-4044-b966-f618fd224f77
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3764890302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.3764890302
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.3019601183
Short name T112
Test name
Test status
Simulation time 1377063706 ps
CPU time 8.97 seconds
Started Mar 14 12:28:46 PM PDT 24
Finished Mar 14 12:28:55 PM PDT 24
Peak memory 214384 kb
Host smart-9a0ba8f1-15b1-4e8c-a82c-9196c6ab85d6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3019601183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.3019601183
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.2205966970
Short name T190
Test name
Test status
Simulation time 546924611 ps
CPU time 3.19 seconds
Started Mar 14 12:29:34 PM PDT 24
Finished Mar 14 12:29:38 PM PDT 24
Peak memory 213832 kb
Host smart-271d232b-f421-4ba1-b43c-0cefa852fcdb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205966970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.2205966970
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.1091059280
Short name T153
Test name
Test status
Simulation time 450067566 ps
CPU time 8.26 seconds
Started Mar 14 12:29:15 PM PDT 24
Finished Mar 14 12:29:23 PM PDT 24
Peak memory 214048 kb
Host smart-e2e8c267-e73d-47df-b063-aec4b6d12160
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091059280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.1091059280
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.3606991605
Short name T1004
Test name
Test status
Simulation time 51708408 ps
CPU time 1.18 seconds
Started Mar 14 12:29:05 PM PDT 24
Finished Mar 14 12:29:06 PM PDT 24
Peak memory 205644 kb
Host smart-f82209e1-5667-41de-bd96-468d6ffbfcbb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606991605 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.3606991605
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.3468217
Short name T988
Test name
Test status
Simulation time 92816676 ps
CPU time 0.94 seconds
Started Mar 14 12:29:01 PM PDT 24
Finished Mar 14 12:29:02 PM PDT 24
Peak memory 205456 kb
Host smart-1b36aab5-22ed-4973-93b4-97353283a73c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.3468217
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.3406104662
Short name T1044
Test name
Test status
Simulation time 13981722 ps
CPU time 0.72 seconds
Started Mar 14 12:28:52 PM PDT 24
Finished Mar 14 12:28:53 PM PDT 24
Peak memory 205372 kb
Host smart-d510eb14-c0d1-43c8-beb8-1dfe4d3f00ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406104662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.3406104662
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.165396695
Short name T139
Test name
Test status
Simulation time 75198353 ps
CPU time 2.79 seconds
Started Mar 14 12:29:14 PM PDT 24
Finished Mar 14 12:29:17 PM PDT 24
Peak memory 205784 kb
Host smart-3e483dec-d433-459c-8cb2-9b5ffa49d1c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165396695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_sa
me_csr_outstanding.165396695
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.1249350687
Short name T937
Test name
Test status
Simulation time 245039573 ps
CPU time 4.12 seconds
Started Mar 14 12:29:08 PM PDT 24
Finished Mar 14 12:29:12 PM PDT 24
Peak memory 214220 kb
Host smart-ef8a2995-44b3-4ed2-824f-9c0ce84f39c7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249350687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.1249350687
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.884135080
Short name T1061
Test name
Test status
Simulation time 571464466 ps
CPU time 7.55 seconds
Started Mar 14 12:29:16 PM PDT 24
Finished Mar 14 12:29:24 PM PDT 24
Peak memory 214284 kb
Host smart-4218400c-4dfc-464d-94fd-8879c8739b26
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884135080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
keymgr_shadow_reg_errors_with_csr_rw.884135080
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.2195957958
Short name T912
Test name
Test status
Simulation time 31522903 ps
CPU time 1.76 seconds
Started Mar 14 12:28:46 PM PDT 24
Finished Mar 14 12:28:48 PM PDT 24
Peak memory 214000 kb
Host smart-d3c14fbf-6683-4f56-baf5-36236a3f64a2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195957958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.2195957958
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.3770791122
Short name T1024
Test name
Test status
Simulation time 57923473 ps
CPU time 1.74 seconds
Started Mar 14 12:29:04 PM PDT 24
Finished Mar 14 12:29:06 PM PDT 24
Peak memory 214044 kb
Host smart-9211fa90-ca7b-4074-b04d-898135c2f8a8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3770791122 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.3770791122
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.4132192506
Short name T138
Test name
Test status
Simulation time 11035721 ps
CPU time 1 seconds
Started Mar 14 12:28:47 PM PDT 24
Finished Mar 14 12:28:48 PM PDT 24
Peak memory 205740 kb
Host smart-68397d8b-5c3c-467d-ba1d-a05915f36918
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132192506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.4132192506
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.948850521
Short name T915
Test name
Test status
Simulation time 55950630 ps
CPU time 0.81 seconds
Started Mar 14 12:29:02 PM PDT 24
Finished Mar 14 12:29:02 PM PDT 24
Peak memory 205372 kb
Host smart-48ec1d92-a7a5-4f78-bf1e-611f05343fb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=948850521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.948850521
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.101146389
Short name T1041
Test name
Test status
Simulation time 210199989 ps
CPU time 2.02 seconds
Started Mar 14 12:29:13 PM PDT 24
Finished Mar 14 12:29:15 PM PDT 24
Peak memory 205648 kb
Host smart-f45645f0-34a9-47ac-9205-9a54f1796269
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=101146389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_sa
me_csr_outstanding.101146389
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.3621615798
Short name T1043
Test name
Test status
Simulation time 296394838 ps
CPU time 7.85 seconds
Started Mar 14 12:28:54 PM PDT 24
Finished Mar 14 12:29:02 PM PDT 24
Peak memory 214140 kb
Host smart-4a14b85a-6128-435e-a927-29b299cf1427
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3621615798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.keymgr_shadow_reg_errors_with_csr_rw.3621615798
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.2836965669
Short name T941
Test name
Test status
Simulation time 119943544 ps
CPU time 4.22 seconds
Started Mar 14 12:29:12 PM PDT 24
Finished Mar 14 12:29:16 PM PDT 24
Peak memory 213920 kb
Host smart-ae220207-b7e4-4c3a-acb5-e0cb44bc0599
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2836965669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.2836965669
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.2931647355
Short name T151
Test name
Test status
Simulation time 224088184 ps
CPU time 8.62 seconds
Started Mar 14 12:29:08 PM PDT 24
Finished Mar 14 12:29:17 PM PDT 24
Peak memory 213988 kb
Host smart-b81c4721-2a5b-4cb3-a915-12d3bba7d7d8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2931647355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.2931647355
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.3647584012
Short name T935
Test name
Test status
Simulation time 47061706 ps
CPU time 1.62 seconds
Started Mar 14 12:29:04 PM PDT 24
Finished Mar 14 12:29:05 PM PDT 24
Peak memory 214136 kb
Host smart-12590d7a-36cb-44e0-833c-674f8d3a61c1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3647584012 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.3647584012
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.3690169314
Short name T989
Test name
Test status
Simulation time 18294450 ps
CPU time 1.22 seconds
Started Mar 14 12:29:01 PM PDT 24
Finished Mar 14 12:29:03 PM PDT 24
Peak memory 205712 kb
Host smart-21e45c42-9b68-4ed5-9960-0fef4e34d2d9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3690169314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.3690169314
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.2533022656
Short name T908
Test name
Test status
Simulation time 20575926 ps
CPU time 0.83 seconds
Started Mar 14 12:29:11 PM PDT 24
Finished Mar 14 12:29:12 PM PDT 24
Peak memory 205412 kb
Host smart-557cdb2f-f759-490d-ad1a-4963a6394c15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533022656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.2533022656
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.3152899730
Short name T137
Test name
Test status
Simulation time 95395451 ps
CPU time 2.33 seconds
Started Mar 14 12:29:00 PM PDT 24
Finished Mar 14 12:29:03 PM PDT 24
Peak memory 213972 kb
Host smart-a6ed7818-193a-4b86-9c8f-adca63049ebc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3152899730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.3152899730
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.4128192921
Short name T116
Test name
Test status
Simulation time 796314147 ps
CPU time 4.11 seconds
Started Mar 14 12:29:23 PM PDT 24
Finished Mar 14 12:29:27 PM PDT 24
Peak memory 214276 kb
Host smart-e67db2c2-cb08-40dc-a5eb-085ec9e0a847
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128192921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.4128192921
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.4251124926
Short name T959
Test name
Test status
Simulation time 1067848787 ps
CPU time 7.44 seconds
Started Mar 14 12:29:01 PM PDT 24
Finished Mar 14 12:29:09 PM PDT 24
Peak memory 213968 kb
Host smart-35bf7d4d-53f0-4a9f-ad4e-7151413a9ac6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251124926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.4251124926
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.3811473930
Short name T987
Test name
Test status
Simulation time 95483017 ps
CPU time 2.15 seconds
Started Mar 14 12:28:56 PM PDT 24
Finished Mar 14 12:28:58 PM PDT 24
Peak memory 213928 kb
Host smart-a536cc9c-ecd9-4401-a925-416c8d9331b6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811473930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.3811473930
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.2164722505
Short name T943
Test name
Test status
Simulation time 185074073 ps
CPU time 1.58 seconds
Started Mar 14 12:29:07 PM PDT 24
Finished Mar 14 12:29:09 PM PDT 24
Peak memory 216464 kb
Host smart-6bff2911-c207-4dc9-8332-c1f0a534325a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164722505 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.2164722505
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.314081056
Short name T1071
Test name
Test status
Simulation time 115316250 ps
CPU time 1.21 seconds
Started Mar 14 12:29:01 PM PDT 24
Finished Mar 14 12:29:02 PM PDT 24
Peak memory 205792 kb
Host smart-d3832791-7774-43f5-9b3f-983aba883188
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314081056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.314081056
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.1123682883
Short name T1047
Test name
Test status
Simulation time 31677634 ps
CPU time 0.75 seconds
Started Mar 14 12:29:10 PM PDT 24
Finished Mar 14 12:29:10 PM PDT 24
Peak memory 205476 kb
Host smart-c1649053-a6c9-4b1e-94f3-45126ba26c3c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1123682883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.1123682883
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.1550131078
Short name T1008
Test name
Test status
Simulation time 180594316 ps
CPU time 2.26 seconds
Started Mar 14 12:28:50 PM PDT 24
Finished Mar 14 12:28:53 PM PDT 24
Peak memory 205668 kb
Host smart-0086fc22-2e56-4837-9757-7057be5160aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550131078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.1550131078
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.1067165011
Short name T1021
Test name
Test status
Simulation time 215388247 ps
CPU time 4.39 seconds
Started Mar 14 12:29:08 PM PDT 24
Finished Mar 14 12:29:13 PM PDT 24
Peak memory 214292 kb
Host smart-ad09554b-e1cf-40fd-abea-89755dba374d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1067165011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.1067165011
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.2453204774
Short name T113
Test name
Test status
Simulation time 956797862 ps
CPU time 6.56 seconds
Started Mar 14 12:29:11 PM PDT 24
Finished Mar 14 12:29:18 PM PDT 24
Peak memory 214236 kb
Host smart-4b90d9bc-3d48-4b64-b078-3a68f87e100c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2453204774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.2453204774
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.4283621649
Short name T917
Test name
Test status
Simulation time 53848680 ps
CPU time 2.37 seconds
Started Mar 14 12:29:18 PM PDT 24
Finished Mar 14 12:29:21 PM PDT 24
Peak memory 215952 kb
Host smart-258290ef-5902-47bc-a845-50c4261ce646
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4283621649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.4283621649
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.351751150
Short name T950
Test name
Test status
Simulation time 759120329 ps
CPU time 6.63 seconds
Started Mar 14 12:28:27 PM PDT 24
Finished Mar 14 12:28:34 PM PDT 24
Peak memory 205660 kb
Host smart-6a87e173-d925-447f-a1e1-0fd2d860f392
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=351751150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.351751150
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.272495780
Short name T991
Test name
Test status
Simulation time 14412048 ps
CPU time 1.15 seconds
Started Mar 14 12:28:36 PM PDT 24
Finished Mar 14 12:28:37 PM PDT 24
Peak memory 205692 kb
Host smart-e3be1e10-d328-48af-ab5f-f64d077b7065
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272495780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.272495780
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.1751116543
Short name T982
Test name
Test status
Simulation time 26912002 ps
CPU time 1.16 seconds
Started Mar 14 12:28:40 PM PDT 24
Finished Mar 14 12:28:41 PM PDT 24
Peak memory 205776 kb
Host smart-f99a83f1-b6a1-4318-a8e2-f8f9e382cd23
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1751116543 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.1751116543
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.2298766170
Short name T140
Test name
Test status
Simulation time 53712546 ps
CPU time 1.15 seconds
Started Mar 14 12:28:51 PM PDT 24
Finished Mar 14 12:28:53 PM PDT 24
Peak memory 205744 kb
Host smart-7b656e8f-affb-4050-bbab-a7e0a5aeb675
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2298766170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.2298766170
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.115400251
Short name T1026
Test name
Test status
Simulation time 43286592 ps
CPU time 0.79 seconds
Started Mar 14 12:28:40 PM PDT 24
Finished Mar 14 12:28:50 PM PDT 24
Peak memory 205468 kb
Host smart-d79f2538-9865-4ded-8b59-f96b62e67c5a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115400251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.115400251
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.2145016241
Short name T949
Test name
Test status
Simulation time 419887940 ps
CPU time 3.53 seconds
Started Mar 14 12:28:38 PM PDT 24
Finished Mar 14 12:28:42 PM PDT 24
Peak memory 213908 kb
Host smart-c7f7fab4-b6c6-43f4-ba98-0a80d88a2778
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2145016241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.2145016241
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.1329467389
Short name T1027
Test name
Test status
Simulation time 47440562 ps
CPU time 1.56 seconds
Started Mar 14 12:28:25 PM PDT 24
Finished Mar 14 12:28:27 PM PDT 24
Peak memory 214248 kb
Host smart-cbc28b3a-5693-4979-a2dc-79f4b6f36ea2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329467389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.1329467389
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.1263472305
Short name T954
Test name
Test status
Simulation time 368518031 ps
CPU time 4.26 seconds
Started Mar 14 12:28:42 PM PDT 24
Finished Mar 14 12:28:46 PM PDT 24
Peak memory 214144 kb
Host smart-30552a54-5441-45d9-a774-6a46bbc2882b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1263472305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.1263472305
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.2854107474
Short name T182
Test name
Test status
Simulation time 187847477 ps
CPU time 2.41 seconds
Started Mar 14 12:28:39 PM PDT 24
Finished Mar 14 12:28:41 PM PDT 24
Peak memory 213892 kb
Host smart-523ed0b3-9d99-4259-9dab-813c035295ca
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2854107474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.2854107474
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.2647563168
Short name T158
Test name
Test status
Simulation time 12356118093 ps
CPU time 31.89 seconds
Started Mar 14 12:28:53 PM PDT 24
Finished Mar 14 12:29:25 PM PDT 24
Peak memory 214096 kb
Host smart-904b528a-c809-4ee8-aa96-15cb25f70e11
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647563168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.2647563168
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.1419016057
Short name T1053
Test name
Test status
Simulation time 9812114 ps
CPU time 0.72 seconds
Started Mar 14 12:29:07 PM PDT 24
Finished Mar 14 12:29:07 PM PDT 24
Peak memory 205528 kb
Host smart-c1cd5dc0-1c6c-49d4-9a72-7de9da21ffda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419016057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.1419016057
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.1247448320
Short name T1067
Test name
Test status
Simulation time 18435891 ps
CPU time 0.71 seconds
Started Mar 14 12:29:06 PM PDT 24
Finished Mar 14 12:29:07 PM PDT 24
Peak memory 205420 kb
Host smart-b23d9852-5b2f-4546-9ed9-4f6d28e9dca2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247448320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.1247448320
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.709774997
Short name T1013
Test name
Test status
Simulation time 28241742 ps
CPU time 0.77 seconds
Started Mar 14 12:29:12 PM PDT 24
Finished Mar 14 12:29:13 PM PDT 24
Peak memory 205492 kb
Host smart-16854457-11e6-472f-9db3-b59eadf73109
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709774997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.709774997
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.1758008589
Short name T1014
Test name
Test status
Simulation time 9903334 ps
CPU time 0.77 seconds
Started Mar 14 12:29:03 PM PDT 24
Finished Mar 14 12:29:03 PM PDT 24
Peak memory 205436 kb
Host smart-92737070-1cfe-4120-b4e2-12335a7b6238
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1758008589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.1758008589
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.3615568237
Short name T1065
Test name
Test status
Simulation time 12182453 ps
CPU time 0.71 seconds
Started Mar 14 12:29:14 PM PDT 24
Finished Mar 14 12:29:15 PM PDT 24
Peak memory 205488 kb
Host smart-591b06ce-6dbd-4594-97c9-3165b71908ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3615568237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.3615568237
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.1690613824
Short name T970
Test name
Test status
Simulation time 16183090 ps
CPU time 0.77 seconds
Started Mar 14 12:29:03 PM PDT 24
Finished Mar 14 12:29:04 PM PDT 24
Peak memory 205552 kb
Host smart-6fe1db23-f67e-4131-877c-e8f8ddc6f0ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690613824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.1690613824
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.124863170
Short name T965
Test name
Test status
Simulation time 9778926 ps
CPU time 0.8 seconds
Started Mar 14 12:29:13 PM PDT 24
Finished Mar 14 12:29:15 PM PDT 24
Peak memory 205488 kb
Host smart-8a24c4fa-36c4-4feb-b372-64543dc86570
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=124863170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.124863170
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.3866103794
Short name T918
Test name
Test status
Simulation time 36630979 ps
CPU time 0.7 seconds
Started Mar 14 12:29:06 PM PDT 24
Finished Mar 14 12:29:06 PM PDT 24
Peak memory 205444 kb
Host smart-b4c3fccb-3b60-451e-8244-d74467ac4b74
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866103794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.3866103794
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.478714489
Short name T1012
Test name
Test status
Simulation time 38335590 ps
CPU time 0.69 seconds
Started Mar 14 12:28:50 PM PDT 24
Finished Mar 14 12:28:51 PM PDT 24
Peak memory 205412 kb
Host smart-470ce5f1-37e6-43f1-b071-6f80221a542b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478714489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.478714489
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.2937033250
Short name T999
Test name
Test status
Simulation time 9781065 ps
CPU time 0.86 seconds
Started Mar 14 12:28:57 PM PDT 24
Finished Mar 14 12:28:58 PM PDT 24
Peak memory 205380 kb
Host smart-1666ab57-73fa-45d6-86aa-00715a83905a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937033250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.2937033250
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.207031242
Short name T135
Test name
Test status
Simulation time 138831200 ps
CPU time 8.17 seconds
Started Mar 14 12:28:43 PM PDT 24
Finished Mar 14 12:28:51 PM PDT 24
Peak memory 205716 kb
Host smart-d82d48d6-d10c-43c1-bfd2-6be1957e56a7
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207031242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.207031242
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.1727152542
Short name T947
Test name
Test status
Simulation time 862262188 ps
CPU time 21.56 seconds
Started Mar 14 12:28:38 PM PDT 24
Finished Mar 14 12:28:59 PM PDT 24
Peak memory 205740 kb
Host smart-07698771-8368-4a4f-bef9-ac3d829ccdf2
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1727152542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.1
727152542
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.4251848307
Short name T180
Test name
Test status
Simulation time 156886180 ps
CPU time 1.09 seconds
Started Mar 14 12:28:42 PM PDT 24
Finished Mar 14 12:28:43 PM PDT 24
Peak memory 205692 kb
Host smart-ef0d1606-d4a6-4cc1-be7f-a36928bb61d2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251848307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.4
251848307
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.4267025425
Short name T1022
Test name
Test status
Simulation time 134523345 ps
CPU time 2.11 seconds
Started Mar 14 12:28:41 PM PDT 24
Finished Mar 14 12:28:43 PM PDT 24
Peak memory 214056 kb
Host smart-d15bd1ab-8351-4661-ab42-2cd6f408eb00
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4267025425 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.4267025425
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.4249224373
Short name T1068
Test name
Test status
Simulation time 42604076 ps
CPU time 0.89 seconds
Started Mar 14 12:28:41 PM PDT 24
Finished Mar 14 12:28:42 PM PDT 24
Peak memory 205564 kb
Host smart-fd8ba9b2-9934-44a2-bdf5-a8dcc354a2dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249224373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.4249224373
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.2027828295
Short name T1036
Test name
Test status
Simulation time 15780718 ps
CPU time 0.75 seconds
Started Mar 14 12:28:40 PM PDT 24
Finished Mar 14 12:28:41 PM PDT 24
Peak memory 205448 kb
Host smart-a08fff21-0b57-4183-8772-75c852f9f2ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2027828295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.2027828295
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.3927090801
Short name T136
Test name
Test status
Simulation time 176762646 ps
CPU time 2.07 seconds
Started Mar 14 12:28:40 PM PDT 24
Finished Mar 14 12:28:42 PM PDT 24
Peak memory 205680 kb
Host smart-1bd9a66a-6cbd-471c-8efc-418670fff0f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3927090801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.3927090801
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.1032848281
Short name T1063
Test name
Test status
Simulation time 182338280 ps
CPU time 3.68 seconds
Started Mar 14 12:28:37 PM PDT 24
Finished Mar 14 12:28:41 PM PDT 24
Peak memory 214348 kb
Host smart-61e1d560-49e5-41cc-93a1-8f1d965c5537
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032848281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.1032848281
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.2714205800
Short name T973
Test name
Test status
Simulation time 592626025 ps
CPU time 4.15 seconds
Started Mar 14 12:28:24 PM PDT 24
Finished Mar 14 12:28:28 PM PDT 24
Peak memory 222464 kb
Host smart-d4682810-1bbf-46b2-8442-c5f8c0e0e655
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714205800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.2714205800
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.2545353506
Short name T936
Test name
Test status
Simulation time 105908616 ps
CPU time 3.25 seconds
Started Mar 14 12:28:26 PM PDT 24
Finished Mar 14 12:28:34 PM PDT 24
Peak memory 213972 kb
Host smart-b9fe7787-036c-45f5-a6b8-02b294e1be17
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2545353506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.2545353506
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.882003291
Short name T368
Test name
Test status
Simulation time 317100597 ps
CPU time 6.43 seconds
Started Mar 14 12:28:40 PM PDT 24
Finished Mar 14 12:28:47 PM PDT 24
Peak memory 209456 kb
Host smart-066d293e-eec8-4566-b7ec-cb1788918b81
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=882003291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err.
882003291
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.1453824248
Short name T1010
Test name
Test status
Simulation time 14990611 ps
CPU time 0.87 seconds
Started Mar 14 12:29:04 PM PDT 24
Finished Mar 14 12:29:05 PM PDT 24
Peak memory 205612 kb
Host smart-a20833e9-0f1d-49d6-9d8b-4281ca23cde0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1453824248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.1453824248
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.289825325
Short name T1057
Test name
Test status
Simulation time 29953194 ps
CPU time 0.69 seconds
Started Mar 14 12:29:14 PM PDT 24
Finished Mar 14 12:29:15 PM PDT 24
Peak memory 205468 kb
Host smart-0c996f10-d5de-463e-8825-f97ae36d71be
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289825325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.289825325
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.2314038386
Short name T931
Test name
Test status
Simulation time 29834252 ps
CPU time 0.67 seconds
Started Mar 14 12:28:56 PM PDT 24
Finished Mar 14 12:28:56 PM PDT 24
Peak memory 205436 kb
Host smart-810252de-5a8e-471e-9ec9-f6b40bfa15a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314038386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.2314038386
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.3283416268
Short name T984
Test name
Test status
Simulation time 13987505 ps
CPU time 0.69 seconds
Started Mar 14 12:28:53 PM PDT 24
Finished Mar 14 12:28:54 PM PDT 24
Peak memory 205468 kb
Host smart-69faaaf7-bbd5-42aa-9c44-e3a7644327e5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283416268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.3283416268
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.2874151560
Short name T938
Test name
Test status
Simulation time 43522024 ps
CPU time 0.82 seconds
Started Mar 14 12:28:50 PM PDT 24
Finished Mar 14 12:28:51 PM PDT 24
Peak memory 205488 kb
Host smart-96c36cb8-aa23-4558-b517-f57a81c63210
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874151560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.2874151560
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.4289301717
Short name T952
Test name
Test status
Simulation time 13943372 ps
CPU time 0.73 seconds
Started Mar 14 12:29:08 PM PDT 24
Finished Mar 14 12:29:09 PM PDT 24
Peak memory 205368 kb
Host smart-e2982e42-19aa-48bc-b16c-f386bb50fd14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4289301717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.4289301717
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.446071068
Short name T925
Test name
Test status
Simulation time 10005168 ps
CPU time 0.78 seconds
Started Mar 14 12:29:06 PM PDT 24
Finished Mar 14 12:29:07 PM PDT 24
Peak memory 205368 kb
Host smart-70c9a291-af7e-4b8b-995d-922aed22ccf3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446071068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.446071068
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.4053303049
Short name T914
Test name
Test status
Simulation time 204934161 ps
CPU time 0.72 seconds
Started Mar 14 12:29:01 PM PDT 24
Finished Mar 14 12:29:02 PM PDT 24
Peak memory 205088 kb
Host smart-3d9eb200-0e2a-4dfe-9f3c-9382b3b3a997
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4053303049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.4053303049
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.4254777727
Short name T1029
Test name
Test status
Simulation time 9073447 ps
CPU time 0.78 seconds
Started Mar 14 12:28:48 PM PDT 24
Finished Mar 14 12:28:49 PM PDT 24
Peak memory 205392 kb
Host smart-5000c19b-d38e-4b48-bbd0-2e971a0fe3cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4254777727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.4254777727
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.785901689
Short name T948
Test name
Test status
Simulation time 11325766 ps
CPU time 0.69 seconds
Started Mar 14 12:29:10 PM PDT 24
Finished Mar 14 12:29:11 PM PDT 24
Peak memory 205428 kb
Host smart-38979eff-8893-4f32-a083-da0308e9d452
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785901689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.785901689
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.2374306296
Short name T926
Test name
Test status
Simulation time 128846240 ps
CPU time 8.66 seconds
Started Mar 14 12:28:43 PM PDT 24
Finished Mar 14 12:28:52 PM PDT 24
Peak memory 205748 kb
Host smart-7442218a-ff49-48ba-ab74-c979fca90605
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2374306296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.2
374306296
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.3680831878
Short name T1059
Test name
Test status
Simulation time 2331477638 ps
CPU time 17.71 seconds
Started Mar 14 12:28:50 PM PDT 24
Finished Mar 14 12:29:08 PM PDT 24
Peak memory 205868 kb
Host smart-5520d441-37c3-4dc1-927a-70e5f42790cc
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3680831878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.3
680831878
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.843547778
Short name T928
Test name
Test status
Simulation time 128724273 ps
CPU time 0.88 seconds
Started Mar 14 12:28:37 PM PDT 24
Finished Mar 14 12:28:38 PM PDT 24
Peak memory 205544 kb
Host smart-3683d338-6343-4f8b-bc10-14cb494bf588
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=843547778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.843547778
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.3566263996
Short name T975
Test name
Test status
Simulation time 23032393 ps
CPU time 1.5 seconds
Started Mar 14 12:28:38 PM PDT 24
Finished Mar 14 12:28:39 PM PDT 24
Peak memory 214052 kb
Host smart-51b3cb02-42fe-4cf0-9927-56e2d87facf5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3566263996 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.3566263996
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.506566229
Short name T961
Test name
Test status
Simulation time 15035228 ps
CPU time 0.92 seconds
Started Mar 14 12:28:43 PM PDT 24
Finished Mar 14 12:28:44 PM PDT 24
Peak memory 205584 kb
Host smart-1b7f030c-382a-42b1-b487-f0d283d72b84
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=506566229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.506566229
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.3155641195
Short name T909
Test name
Test status
Simulation time 20522909 ps
CPU time 0.71 seconds
Started Mar 14 12:28:42 PM PDT 24
Finished Mar 14 12:28:43 PM PDT 24
Peak memory 205412 kb
Host smart-7e519e0f-6766-4510-bad2-f5eac20f79ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155641195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.3155641195
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.3140213163
Short name T1001
Test name
Test status
Simulation time 422760938 ps
CPU time 3.54 seconds
Started Mar 14 12:28:40 PM PDT 24
Finished Mar 14 12:28:49 PM PDT 24
Peak memory 205812 kb
Host smart-04844000-c63b-401e-ad3f-11ed1b3ae819
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3140213163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.3140213163
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.300797552
Short name T1055
Test name
Test status
Simulation time 4900769933 ps
CPU time 6.16 seconds
Started Mar 14 12:28:42 PM PDT 24
Finished Mar 14 12:28:48 PM PDT 24
Peak memory 219888 kb
Host smart-13bb808c-507e-49dd-a02c-cbc1a5892263
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=300797552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shadow
_reg_errors.300797552
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.110233
Short name T962
Test name
Test status
Simulation time 316066403 ps
CPU time 7.62 seconds
Started Mar 14 12:28:40 PM PDT 24
Finished Mar 14 12:28:48 PM PDT 24
Peak memory 214124 kb
Host smart-415a0ba9-40fa-4c09-8f90-8c4ccf892e58
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SE
Q=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keym
gr_shadow_reg_errors_with_csr_rw.110233
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.431637808
Short name T1045
Test name
Test status
Simulation time 85610962 ps
CPU time 1.39 seconds
Started Mar 14 12:28:47 PM PDT 24
Finished Mar 14 12:28:48 PM PDT 24
Peak memory 213884 kb
Host smart-c5a2894d-2707-44af-b7ef-658e48699544
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431637808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.431637808
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.1682888159
Short name T164
Test name
Test status
Simulation time 701107651 ps
CPU time 4.99 seconds
Started Mar 14 12:28:43 PM PDT 24
Finished Mar 14 12:28:48 PM PDT 24
Peak memory 209280 kb
Host smart-56d6dbec-2153-4904-be64-4930740c61a8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1682888159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.1682888159
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.3435196903
Short name T1060
Test name
Test status
Simulation time 14212609 ps
CPU time 0.71 seconds
Started Mar 14 12:28:58 PM PDT 24
Finished Mar 14 12:28:59 PM PDT 24
Peak memory 205424 kb
Host smart-e198b939-ae8c-413a-895c-e30ff51f6075
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3435196903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.3435196903
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.2483148686
Short name T945
Test name
Test status
Simulation time 89044984 ps
CPU time 0.77 seconds
Started Mar 14 12:29:11 PM PDT 24
Finished Mar 14 12:29:12 PM PDT 24
Peak memory 205372 kb
Host smart-993f1657-3969-43a8-8eec-04661164c2a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2483148686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.2483148686
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.3745728984
Short name T1005
Test name
Test status
Simulation time 19481354 ps
CPU time 0.81 seconds
Started Mar 14 12:29:07 PM PDT 24
Finished Mar 14 12:29:13 PM PDT 24
Peak memory 205428 kb
Host smart-222d53d9-ab14-4187-884c-29104992a11d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745728984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.3745728984
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.1778621298
Short name T1058
Test name
Test status
Simulation time 35654021 ps
CPU time 0.76 seconds
Started Mar 14 12:29:09 PM PDT 24
Finished Mar 14 12:29:10 PM PDT 24
Peak memory 205372 kb
Host smart-42a6532b-73bd-4824-a29b-f8381c68a985
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778621298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.1778621298
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.3581147942
Short name T907
Test name
Test status
Simulation time 30046665 ps
CPU time 0.75 seconds
Started Mar 14 12:28:59 PM PDT 24
Finished Mar 14 12:29:00 PM PDT 24
Peak memory 205376 kb
Host smart-2dc1ed30-e85b-440f-a2c7-ce03730cda93
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581147942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.3581147942
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.1936253847
Short name T1030
Test name
Test status
Simulation time 9606145 ps
CPU time 0.69 seconds
Started Mar 14 12:28:53 PM PDT 24
Finished Mar 14 12:28:54 PM PDT 24
Peak memory 205380 kb
Host smart-ad31167a-a9b8-4253-a4cb-e027315b99df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936253847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.1936253847
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.4050407274
Short name T994
Test name
Test status
Simulation time 9257679 ps
CPU time 0.68 seconds
Started Mar 14 12:29:00 PM PDT 24
Finished Mar 14 12:29:01 PM PDT 24
Peak memory 205488 kb
Host smart-3539ea67-ed5d-4466-b3a6-78c48fc95831
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4050407274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.4050407274
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.3620999303
Short name T921
Test name
Test status
Simulation time 47768333 ps
CPU time 0.84 seconds
Started Mar 14 12:28:54 PM PDT 24
Finished Mar 14 12:28:55 PM PDT 24
Peak memory 205448 kb
Host smart-a45587d8-2098-41e6-b6d8-6554adc85932
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3620999303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.3620999303
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.2617798221
Short name T1062
Test name
Test status
Simulation time 10643631 ps
CPU time 0.89 seconds
Started Mar 14 12:29:11 PM PDT 24
Finished Mar 14 12:29:12 PM PDT 24
Peak memory 205448 kb
Host smart-08bc28c5-7fac-448c-9a92-2d6972e982fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617798221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.2617798221
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.3512878690
Short name T911
Test name
Test status
Simulation time 44610752 ps
CPU time 0.69 seconds
Started Mar 14 12:28:52 PM PDT 24
Finished Mar 14 12:28:53 PM PDT 24
Peak memory 205440 kb
Host smart-d64a058a-2904-462a-a304-c2d1f5027712
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512878690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.3512878690
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.3659955000
Short name T1003
Test name
Test status
Simulation time 28129853 ps
CPU time 1.46 seconds
Started Mar 14 12:28:53 PM PDT 24
Finished Mar 14 12:28:55 PM PDT 24
Peak memory 213956 kb
Host smart-fe362566-5ee5-490b-a0bc-7bfd007e8183
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659955000 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.3659955000
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.1527523881
Short name T1019
Test name
Test status
Simulation time 50001393 ps
CPU time 0.99 seconds
Started Mar 14 12:29:03 PM PDT 24
Finished Mar 14 12:29:04 PM PDT 24
Peak memory 205736 kb
Host smart-648d8cd0-8905-49a5-a77b-df77dba9c403
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1527523881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.1527523881
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.38537696
Short name T953
Test name
Test status
Simulation time 15623234 ps
CPU time 0.76 seconds
Started Mar 14 12:28:58 PM PDT 24
Finished Mar 14 12:28:59 PM PDT 24
Peak memory 205452 kb
Host smart-884e2b5f-9506-496e-ac02-cbeb791fa3c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38537696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.38537696
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.236010180
Short name T980
Test name
Test status
Simulation time 97909056 ps
CPU time 2.63 seconds
Started Mar 14 12:28:50 PM PDT 24
Finished Mar 14 12:28:53 PM PDT 24
Peak memory 205748 kb
Host smart-9dc2ff06-d463-472a-8ab6-4c95e295564b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236010180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sam
e_csr_outstanding.236010180
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.3604449748
Short name T968
Test name
Test status
Simulation time 172976199 ps
CPU time 3.17 seconds
Started Mar 14 12:28:47 PM PDT 24
Finished Mar 14 12:28:51 PM PDT 24
Peak memory 214256 kb
Host smart-fa6d99f4-8683-40b9-bd7c-b9fb00ae9a20
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604449748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.3604449748
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.1163833723
Short name T924
Test name
Test status
Simulation time 267184847 ps
CPU time 4.51 seconds
Started Mar 14 12:28:40 PM PDT 24
Finished Mar 14 12:28:45 PM PDT 24
Peak memory 220908 kb
Host smart-a04d4f89-273c-47c7-8dce-d90d37a589ac
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1163833723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
keymgr_shadow_reg_errors_with_csr_rw.1163833723
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.2760686560
Short name T910
Test name
Test status
Simulation time 305378220 ps
CPU time 2.97 seconds
Started Mar 14 12:28:48 PM PDT 24
Finished Mar 14 12:28:51 PM PDT 24
Peak memory 213996 kb
Host smart-fad2c0f5-674d-4f2d-b69d-e0f6dce14a61
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760686560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.2760686560
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.3396301354
Short name T976
Test name
Test status
Simulation time 47666097 ps
CPU time 1.33 seconds
Started Mar 14 12:28:48 PM PDT 24
Finished Mar 14 12:28:49 PM PDT 24
Peak memory 205828 kb
Host smart-aa5f0ec2-85f2-4183-b88b-905f376de6da
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3396301354 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.3396301354
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.3091703274
Short name T930
Test name
Test status
Simulation time 13801377 ps
CPU time 0.97 seconds
Started Mar 14 12:28:56 PM PDT 24
Finished Mar 14 12:28:57 PM PDT 24
Peak memory 205624 kb
Host smart-5c39cb36-57eb-4c2d-8431-c9a8bbf2a8a7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3091703274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.3091703274
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.335135432
Short name T939
Test name
Test status
Simulation time 113624334 ps
CPU time 0.76 seconds
Started Mar 14 12:28:39 PM PDT 24
Finished Mar 14 12:28:40 PM PDT 24
Peak memory 205468 kb
Host smart-6d83578f-440a-48e3-ad48-0c64c26fb241
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335135432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.335135432
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.13516589
Short name T966
Test name
Test status
Simulation time 165492396 ps
CPU time 2.03 seconds
Started Mar 14 12:28:48 PM PDT 24
Finished Mar 14 12:28:50 PM PDT 24
Peak memory 205840 kb
Host smart-3a02ae47-447e-429a-8085-8f58e4bef2ae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13516589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymg
r_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_same
_csr_outstanding.13516589
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.4162080381
Short name T967
Test name
Test status
Simulation time 206007412 ps
CPU time 2.14 seconds
Started Mar 14 12:28:39 PM PDT 24
Finished Mar 14 12:28:41 PM PDT 24
Peak memory 214216 kb
Host smart-db47d326-b62b-442b-8c1a-b3ab26b9d63a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162080381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.4162080381
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.828072340
Short name T120
Test name
Test status
Simulation time 536171109 ps
CPU time 8.3 seconds
Started Mar 14 12:28:52 PM PDT 24
Finished Mar 14 12:29:01 PM PDT 24
Peak memory 214292 kb
Host smart-6f8f0e25-d9d1-44e4-957f-3bbf475b5259
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828072340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.k
eymgr_shadow_reg_errors_with_csr_rw.828072340
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.2502378207
Short name T981
Test name
Test status
Simulation time 193486633 ps
CPU time 2.6 seconds
Started Mar 14 12:28:41 PM PDT 24
Finished Mar 14 12:28:44 PM PDT 24
Peak memory 213960 kb
Host smart-ec17c765-d5ca-4838-929a-9d8dd32760c7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2502378207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.2502378207
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.354104995
Short name T986
Test name
Test status
Simulation time 579605447 ps
CPU time 1.66 seconds
Started Mar 14 12:28:45 PM PDT 24
Finished Mar 14 12:28:46 PM PDT 24
Peak memory 214060 kb
Host smart-ca407fa4-caeb-459a-9096-bd397baa85a1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354104995 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.354104995
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.1506168
Short name T998
Test name
Test status
Simulation time 50021120 ps
CPU time 1.08 seconds
Started Mar 14 12:28:59 PM PDT 24
Finished Mar 14 12:29:05 PM PDT 24
Peak memory 205684 kb
Host smart-dfa9467e-9110-46a3-8dc9-71906cdc5759
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1506168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.1506168
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.1824791136
Short name T1032
Test name
Test status
Simulation time 17706559 ps
CPU time 0.69 seconds
Started Mar 14 12:28:41 PM PDT 24
Finished Mar 14 12:28:41 PM PDT 24
Peak memory 204416 kb
Host smart-9e790119-e5d8-4502-8ce1-d4b709a7b1fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1824791136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.1824791136
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.1358419092
Short name T1033
Test name
Test status
Simulation time 30835010 ps
CPU time 2.35 seconds
Started Mar 14 12:28:39 PM PDT 24
Finished Mar 14 12:28:42 PM PDT 24
Peak memory 205772 kb
Host smart-240301d3-9d9d-4d74-b705-72bb34176ca7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358419092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.1358419092
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.992494330
Short name T1049
Test name
Test status
Simulation time 1029661565 ps
CPU time 3.66 seconds
Started Mar 14 12:28:37 PM PDT 24
Finished Mar 14 12:28:40 PM PDT 24
Peak memory 222316 kb
Host smart-69f5ddd5-1656-414c-9013-d02249aee4a2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992494330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shadow
_reg_errors.992494330
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.25883696
Short name T1052
Test name
Test status
Simulation time 100968782 ps
CPU time 1.97 seconds
Started Mar 14 12:28:42 PM PDT 24
Finished Mar 14 12:28:45 PM PDT 24
Peak memory 222100 kb
Host smart-bbd84720-04be-40e0-9a90-cabc64451318
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25883696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.25883696
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.1859045965
Short name T997
Test name
Test status
Simulation time 25641926 ps
CPU time 1.49 seconds
Started Mar 14 12:28:43 PM PDT 24
Finished Mar 14 12:28:45 PM PDT 24
Peak memory 214012 kb
Host smart-901a3ca8-ccfa-4b59-860d-fdd3e84a209a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859045965 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.1859045965
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.385250333
Short name T955
Test name
Test status
Simulation time 27753657 ps
CPU time 1.2 seconds
Started Mar 14 12:28:40 PM PDT 24
Finished Mar 14 12:28:42 PM PDT 24
Peak memory 205548 kb
Host smart-44864f48-fcf0-4609-8318-7ab7c52111b3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385250333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.385250333
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.3813108243
Short name T1040
Test name
Test status
Simulation time 43197483 ps
CPU time 0.73 seconds
Started Mar 14 12:28:40 PM PDT 24
Finished Mar 14 12:28:41 PM PDT 24
Peak memory 205392 kb
Host smart-10aebbbf-499b-4ef7-9e5c-9ede954227f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3813108243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.3813108243
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.3731907325
Short name T946
Test name
Test status
Simulation time 181107921 ps
CPU time 2 seconds
Started Mar 14 12:28:46 PM PDT 24
Finished Mar 14 12:28:48 PM PDT 24
Peak memory 205776 kb
Host smart-50398e18-f852-4a00-a4fd-8d7c1d4018ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731907325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.3731907325
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.1510924801
Short name T995
Test name
Test status
Simulation time 1766834133 ps
CPU time 3.28 seconds
Started Mar 14 12:28:41 PM PDT 24
Finished Mar 14 12:28:45 PM PDT 24
Peak memory 222340 kb
Host smart-6bca4fcd-1d92-4265-ae6d-74936bd34a56
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1510924801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.1510924801
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.814091438
Short name T1020
Test name
Test status
Simulation time 250036266 ps
CPU time 5.04 seconds
Started Mar 14 12:28:39 PM PDT 24
Finished Mar 14 12:28:44 PM PDT 24
Peak memory 214300 kb
Host smart-c5386167-62cc-4c17-980e-c66e309436e7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=814091438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.k
eymgr_shadow_reg_errors_with_csr_rw.814091438
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.1708725152
Short name T1037
Test name
Test status
Simulation time 116151305 ps
CPU time 2.7 seconds
Started Mar 14 12:29:34 PM PDT 24
Finished Mar 14 12:29:37 PM PDT 24
Peak memory 213988 kb
Host smart-f2e1f5d8-fe09-4c9b-9153-390df64fd6d3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708725152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.1708725152
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.835227951
Short name T1051
Test name
Test status
Simulation time 229426081 ps
CPU time 6.12 seconds
Started Mar 14 12:28:41 PM PDT 24
Finished Mar 14 12:28:48 PM PDT 24
Peak memory 209080 kb
Host smart-27414825-6edc-4b32-870d-72e07c2bf50e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=835227951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err.
835227951
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.2920013662
Short name T1025
Test name
Test status
Simulation time 28494801 ps
CPU time 1.86 seconds
Started Mar 14 12:28:36 PM PDT 24
Finished Mar 14 12:28:38 PM PDT 24
Peak memory 214268 kb
Host smart-7e09a18b-b618-4dea-89a1-2d6b2398eefd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2920013662 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.2920013662
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.2617319394
Short name T913
Test name
Test status
Simulation time 17192721 ps
CPU time 0.93 seconds
Started Mar 14 12:28:39 PM PDT 24
Finished Mar 14 12:28:40 PM PDT 24
Peak memory 205584 kb
Host smart-bb599af1-1b31-46f8-84a0-fd4545371f21
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2617319394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.2617319394
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.1971373198
Short name T1046
Test name
Test status
Simulation time 39492686 ps
CPU time 0.8 seconds
Started Mar 14 12:28:47 PM PDT 24
Finished Mar 14 12:28:48 PM PDT 24
Peak memory 205436 kb
Host smart-b0606ca5-f2bb-49d8-bcc4-705947eea597
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971373198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.1971373198
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.797959830
Short name T951
Test name
Test status
Simulation time 38778506 ps
CPU time 1.32 seconds
Started Mar 14 12:29:35 PM PDT 24
Finished Mar 14 12:29:37 PM PDT 24
Peak memory 204928 kb
Host smart-5006f6b1-45f0-4441-804f-b5b020bab609
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=797959830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sam
e_csr_outstanding.797959830
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.3758773331
Short name T1017
Test name
Test status
Simulation time 432424513 ps
CPU time 2.95 seconds
Started Mar 14 12:28:41 PM PDT 24
Finished Mar 14 12:28:44 PM PDT 24
Peak memory 214232 kb
Host smart-af7373f1-15a1-4657-8bd8-2529b34a5913
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3758773331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.3758773331
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.2937464317
Short name T992
Test name
Test status
Simulation time 209031530 ps
CPU time 8.43 seconds
Started Mar 14 12:28:41 PM PDT 24
Finished Mar 14 12:28:49 PM PDT 24
Peak memory 213244 kb
Host smart-368b668f-d532-466e-b8d7-79b2b2179806
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2937464317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.2937464317
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.669578895
Short name T1056
Test name
Test status
Simulation time 248546716 ps
CPU time 2.74 seconds
Started Mar 14 12:28:41 PM PDT 24
Finished Mar 14 12:28:44 PM PDT 24
Peak memory 213888 kb
Host smart-c4270e52-c9c1-495c-a6c7-18e10177dab5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669578895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.669578895
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.3023084016
Short name T461
Test name
Test status
Simulation time 28635457 ps
CPU time 0.7 seconds
Started Mar 14 12:55:10 PM PDT 24
Finished Mar 14 12:55:11 PM PDT 24
Peak memory 206240 kb
Host smart-ee088373-18b6-487e-9712-96fa426bc75c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023084016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.3023084016
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.549684148
Short name T866
Test name
Test status
Simulation time 195852276 ps
CPU time 3.22 seconds
Started Mar 14 12:55:09 PM PDT 24
Finished Mar 14 12:55:13 PM PDT 24
Peak memory 216540 kb
Host smart-8f6a5424-f8c8-4e83-9404-3c2f64d8fdb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=549684148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.549684148
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.4007868502
Short name T616
Test name
Test status
Simulation time 78068117 ps
CPU time 3.06 seconds
Started Mar 14 12:55:11 PM PDT 24
Finished Mar 14 12:55:14 PM PDT 24
Peak memory 214564 kb
Host smart-7f1d05e6-b74e-4966-a655-527c8bc9bf65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4007868502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.4007868502
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.4013037945
Short name T782
Test name
Test status
Simulation time 300380324 ps
CPU time 4.06 seconds
Started Mar 14 12:55:10 PM PDT 24
Finished Mar 14 12:55:15 PM PDT 24
Peak memory 218960 kb
Host smart-566e4416-ac29-470b-a371-10b8eebad725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4013037945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.4013037945
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.317170669
Short name T201
Test name
Test status
Simulation time 2031825683 ps
CPU time 10.28 seconds
Started Mar 14 12:55:09 PM PDT 24
Finished Mar 14 12:55:20 PM PDT 24
Peak memory 214548 kb
Host smart-109c3114-2a68-424a-b44e-060327da086c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317170669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.317170669
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.3659459133
Short name T391
Test name
Test status
Simulation time 36287614 ps
CPU time 2.32 seconds
Started Mar 14 12:55:10 PM PDT 24
Finished Mar 14 12:55:13 PM PDT 24
Peak memory 208392 kb
Host smart-222ba763-0f7d-4176-8071-491370d01446
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659459133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.3659459133
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.2731171942
Short name T259
Test name
Test status
Simulation time 457674717 ps
CPU time 5.31 seconds
Started Mar 14 12:55:10 PM PDT 24
Finished Mar 14 12:55:16 PM PDT 24
Peak memory 209348 kb
Host smart-37f01508-acf6-40ee-a666-63054e774e65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731171942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.2731171942
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.1254129195
Short name T5
Test name
Test status
Simulation time 4600492144 ps
CPU time 56.38 seconds
Started Mar 14 12:55:12 PM PDT 24
Finished Mar 14 12:56:08 PM PDT 24
Peak memory 238292 kb
Host smart-5e8c58c8-4460-41ec-a79c-abb90e100585
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254129195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.1254129195
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload.367018899
Short name T107
Test name
Test status
Simulation time 195687797 ps
CPU time 2.74 seconds
Started Mar 14 12:55:09 PM PDT 24
Finished Mar 14 12:55:12 PM PDT 24
Peak memory 207480 kb
Host smart-8fef8f3e-b948-457c-b3c5-99c9d0464ad0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=367018899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.367018899
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.3553530038
Short name T529
Test name
Test status
Simulation time 191803894 ps
CPU time 2.72 seconds
Started Mar 14 12:55:11 PM PDT 24
Finished Mar 14 12:55:14 PM PDT 24
Peak memory 206944 kb
Host smart-19d4a5c1-be50-4c0e-a4ef-0b181ee6a131
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3553530038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.3553530038
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.782752000
Short name T675
Test name
Test status
Simulation time 420347993 ps
CPU time 4.45 seconds
Started Mar 14 12:55:10 PM PDT 24
Finished Mar 14 12:55:15 PM PDT 24
Peak memory 207148 kb
Host smart-c11b41e7-8261-4b75-b957-84eb0dba07c7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782752000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.782752000
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.3187824737
Short name T454
Test name
Test status
Simulation time 65009599 ps
CPU time 3.29 seconds
Started Mar 14 12:55:12 PM PDT 24
Finished Mar 14 12:55:15 PM PDT 24
Peak memory 207072 kb
Host smart-89796cdf-1ad4-491f-bba8-af973829ebb0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187824737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.3187824737
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.3083918534
Short name T298
Test name
Test status
Simulation time 81554672 ps
CPU time 2.71 seconds
Started Mar 14 12:55:10 PM PDT 24
Finished Mar 14 12:55:14 PM PDT 24
Peak memory 214592 kb
Host smart-ad6f2012-a09c-4475-b7ae-527c1ada0911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083918534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.3083918534
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.1132157263
Short name T420
Test name
Test status
Simulation time 43224770 ps
CPU time 2.72 seconds
Started Mar 14 12:55:00 PM PDT 24
Finished Mar 14 12:55:03 PM PDT 24
Peak memory 207816 kb
Host smart-68f6b8e5-e0e0-453d-b153-3cb0064efb82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132157263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.1132157263
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.1414847094
Short name T871
Test name
Test status
Simulation time 2272822685 ps
CPU time 54.23 seconds
Started Mar 14 12:55:10 PM PDT 24
Finished Mar 14 12:56:05 PM PDT 24
Peak memory 208160 kb
Host smart-478258de-96c1-42b6-ada3-3ba906c188e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1414847094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.1414847094
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.1886816174
Short name T558
Test name
Test status
Simulation time 12387054 ps
CPU time 0.87 seconds
Started Mar 14 12:55:31 PM PDT 24
Finished Mar 14 12:55:32 PM PDT 24
Peak memory 206240 kb
Host smart-299fca1d-1ab3-429a-a4b6-02a12aad09e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1886816174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.1886816174
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.3830700197
Short name T394
Test name
Test status
Simulation time 59291478 ps
CPU time 2.43 seconds
Started Mar 14 12:55:19 PM PDT 24
Finished Mar 14 12:55:22 PM PDT 24
Peak memory 214568 kb
Host smart-df8b22be-0681-4270-9aca-13f90d5cac51
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3830700197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.3830700197
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.2341699874
Short name T36
Test name
Test status
Simulation time 5430190015 ps
CPU time 30.73 seconds
Started Mar 14 12:55:20 PM PDT 24
Finished Mar 14 12:55:51 PM PDT 24
Peak memory 222864 kb
Host smart-bdd7ae84-7d7c-4c02-89bf-19150d57ea04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2341699874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.2341699874
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.1622847256
Short name T898
Test name
Test status
Simulation time 26547301 ps
CPU time 1.92 seconds
Started Mar 14 12:55:19 PM PDT 24
Finished Mar 14 12:55:21 PM PDT 24
Peak memory 210168 kb
Host smart-820bbb0c-4209-469a-9030-1efeda329567
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1622847256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.1622847256
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.2704555541
Short name T347
Test name
Test status
Simulation time 1043742467 ps
CPU time 22.38 seconds
Started Mar 14 12:55:20 PM PDT 24
Finished Mar 14 12:55:42 PM PDT 24
Peak memory 220540 kb
Host smart-a00c3438-6dbe-45e3-9dcf-4628c0e8c746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2704555541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.2704555541
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.3018179374
Short name T875
Test name
Test status
Simulation time 185788400 ps
CPU time 8.44 seconds
Started Mar 14 12:55:18 PM PDT 24
Finished Mar 14 12:55:26 PM PDT 24
Peak memory 222784 kb
Host smart-47492e96-2878-4abd-a111-b4a9eaf4a75d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018179374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.3018179374
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.92536192
Short name T235
Test name
Test status
Simulation time 1939105827 ps
CPU time 28.5 seconds
Started Mar 14 12:55:19 PM PDT 24
Finished Mar 14 12:55:48 PM PDT 24
Peak memory 214660 kb
Host smart-cf6eba30-4d02-48a2-a189-cee7bf48759a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=92536192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.92536192
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.3986740697
Short name T308
Test name
Test status
Simulation time 1626904471 ps
CPU time 5.44 seconds
Started Mar 14 12:55:19 PM PDT 24
Finished Mar 14 12:55:25 PM PDT 24
Peak memory 218552 kb
Host smart-fecc8609-af6f-4d21-a8b4-d94e3a3903ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986740697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.3986740697
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.2201009781
Short name T103
Test name
Test status
Simulation time 636135370 ps
CPU time 15.34 seconds
Started Mar 14 12:55:31 PM PDT 24
Finished Mar 14 12:55:46 PM PDT 24
Peak memory 238156 kb
Host smart-15f9590a-deac-44e4-a26c-65c672031cdb
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201009781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.2201009781
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload.99640968
Short name T381
Test name
Test status
Simulation time 283902195 ps
CPU time 6.86 seconds
Started Mar 14 12:55:09 PM PDT 24
Finished Mar 14 12:55:17 PM PDT 24
Peak memory 208988 kb
Host smart-c19585c9-d128-470d-854a-7085cd1b120b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99640968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.99640968
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.633211893
Short name T427
Test name
Test status
Simulation time 662615006 ps
CPU time 20.19 seconds
Started Mar 14 12:55:08 PM PDT 24
Finished Mar 14 12:55:29 PM PDT 24
Peak memory 209236 kb
Host smart-1bcc384f-d6b1-4c75-aa59-824d09e5cf91
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=633211893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.633211893
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.1050720826
Short name T505
Test name
Test status
Simulation time 63253954 ps
CPU time 3.32 seconds
Started Mar 14 12:55:09 PM PDT 24
Finished Mar 14 12:55:12 PM PDT 24
Peak memory 208700 kb
Host smart-338ad4a0-9148-4c6f-99a9-390861402802
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050720826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.1050720826
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.3053152990
Short name T317
Test name
Test status
Simulation time 67405339 ps
CPU time 3.24 seconds
Started Mar 14 12:55:21 PM PDT 24
Finished Mar 14 12:55:24 PM PDT 24
Peak memory 208868 kb
Host smart-1ee66c13-d0b5-46dc-ab6a-268c3057203c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053152990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.3053152990
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.1402623550
Short name T600
Test name
Test status
Simulation time 58129077 ps
CPU time 2.68 seconds
Started Mar 14 12:55:20 PM PDT 24
Finished Mar 14 12:55:23 PM PDT 24
Peak memory 209412 kb
Host smart-35568423-cde5-49a6-9d99-67e70fd67ff9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402623550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.1402623550
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.3682690876
Short name T796
Test name
Test status
Simulation time 57365999 ps
CPU time 2.15 seconds
Started Mar 14 12:55:10 PM PDT 24
Finished Mar 14 12:55:13 PM PDT 24
Peak memory 207044 kb
Host smart-f70ad9d2-3f20-4a64-be16-dd76c921c3ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682690876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.3682690876
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.2075231182
Short name T311
Test name
Test status
Simulation time 6975534206 ps
CPU time 38.11 seconds
Started Mar 14 12:55:21 PM PDT 24
Finished Mar 14 12:55:59 PM PDT 24
Peak memory 216876 kb
Host smart-19b8e023-d115-4c2a-8dfe-fed5748d2aa8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2075231182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.2075231182
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_stress_all_with_rand_reset.2552016130
Short name T724
Test name
Test status
Simulation time 319084612 ps
CPU time 11.67 seconds
Started Mar 14 12:55:30 PM PDT 24
Finished Mar 14 12:55:42 PM PDT 24
Peak memory 222952 kb
Host smart-a2af924f-6872-4d48-9375-b888eead1e5b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552016130 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all_with_rand_reset.2552016130
Directory /workspace/1.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.1959006188
Short name T289
Test name
Test status
Simulation time 26298179789 ps
CPU time 55.38 seconds
Started Mar 14 12:55:21 PM PDT 24
Finished Mar 14 12:56:17 PM PDT 24
Peak memory 222884 kb
Host smart-5436b6d5-aa6a-4a0c-a887-5bb7a5f681ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959006188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.1959006188
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.4067146151
Short name T566
Test name
Test status
Simulation time 27505606 ps
CPU time 0.94 seconds
Started Mar 14 12:56:47 PM PDT 24
Finished Mar 14 12:56:49 PM PDT 24
Peak memory 206360 kb
Host smart-d143b0a2-0312-44b1-ab96-225a2607347d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067146151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.4067146151
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.64842269
Short name T27
Test name
Test status
Simulation time 106362310 ps
CPU time 3.68 seconds
Started Mar 14 12:56:49 PM PDT 24
Finished Mar 14 12:56:54 PM PDT 24
Peak memory 220504 kb
Host smart-537b2229-8b7d-4923-8a0c-ea9c2fe268c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64842269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.64842269
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.3714241841
Short name T677
Test name
Test status
Simulation time 76980353 ps
CPU time 2.77 seconds
Started Mar 14 12:56:34 PM PDT 24
Finished Mar 14 12:56:37 PM PDT 24
Peak memory 209648 kb
Host smart-148d9c7c-b730-4fdf-8a08-75f3d8d1fc1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714241841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.3714241841
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.2730990602
Short name T685
Test name
Test status
Simulation time 90522185 ps
CPU time 3.23 seconds
Started Mar 14 12:56:32 PM PDT 24
Finished Mar 14 12:56:36 PM PDT 24
Peak memory 220576 kb
Host smart-51e5bc4b-369b-4b46-9706-c88f7a993c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730990602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.2730990602
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.4189289767
Short name T375
Test name
Test status
Simulation time 274637548 ps
CPU time 7.81 seconds
Started Mar 14 12:56:33 PM PDT 24
Finished Mar 14 12:56:41 PM PDT 24
Peak memory 208816 kb
Host smart-501a20c5-66e7-4164-969b-6ebf4d1a0d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189289767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.4189289767
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.4143432133
Short name T658
Test name
Test status
Simulation time 49690285 ps
CPU time 2.77 seconds
Started Mar 14 12:56:35 PM PDT 24
Finished Mar 14 12:56:38 PM PDT 24
Peak memory 207020 kb
Host smart-ce497d98-70a3-4126-9ee0-0f538c9777af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4143432133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.4143432133
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.1133561136
Short name T601
Test name
Test status
Simulation time 63050339 ps
CPU time 2.5 seconds
Started Mar 14 12:56:33 PM PDT 24
Finished Mar 14 12:56:36 PM PDT 24
Peak memory 207172 kb
Host smart-5205ffc6-7ff4-4e91-ae2f-3b4a54a0e620
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1133561136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.1133561136
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.177324243
Short name T476
Test name
Test status
Simulation time 83525731 ps
CPU time 1.9 seconds
Started Mar 14 12:56:35 PM PDT 24
Finished Mar 14 12:56:37 PM PDT 24
Peak memory 207108 kb
Host smart-08ae5e59-412b-4578-b749-792019aae1a0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177324243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.177324243
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.4030878117
Short name T621
Test name
Test status
Simulation time 94261540 ps
CPU time 3.59 seconds
Started Mar 14 12:56:33 PM PDT 24
Finished Mar 14 12:56:37 PM PDT 24
Peak memory 209228 kb
Host smart-0ca961ff-fcc0-449f-95d2-a815e3df494e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030878117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.4030878117
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.3953956668
Short name T829
Test name
Test status
Simulation time 2983649689 ps
CPU time 33.13 seconds
Started Mar 14 12:56:46 PM PDT 24
Finished Mar 14 12:57:20 PM PDT 24
Peak memory 209516 kb
Host smart-52182765-f7cb-4af2-b873-441047725315
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953956668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.3953956668
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.1779897221
Short name T377
Test name
Test status
Simulation time 65947766 ps
CPU time 2.23 seconds
Started Mar 14 12:56:31 PM PDT 24
Finished Mar 14 12:56:33 PM PDT 24
Peak memory 207012 kb
Host smart-96143873-471a-46a1-9e23-8a12db8991c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1779897221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.1779897221
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.3309915916
Short name T477
Test name
Test status
Simulation time 2161250747 ps
CPU time 51.69 seconds
Started Mar 14 12:56:50 PM PDT 24
Finished Mar 14 12:57:42 PM PDT 24
Peak memory 208212 kb
Host smart-fb677d57-d82e-44c2-93bf-05afe4f78d68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3309915916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.3309915916
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.556151121
Short name T145
Test name
Test status
Simulation time 133597237 ps
CPU time 4.02 seconds
Started Mar 14 12:56:48 PM PDT 24
Finished Mar 14 12:56:53 PM PDT 24
Peak memory 210412 kb
Host smart-839f03d5-1d49-4395-975e-12bf4a18ee95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556151121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.556151121
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.3795593520
Short name T774
Test name
Test status
Simulation time 26361067 ps
CPU time 0.76 seconds
Started Mar 14 12:56:48 PM PDT 24
Finished Mar 14 12:56:50 PM PDT 24
Peak memory 206208 kb
Host smart-b689c4a3-7a30-4f9a-ba52-f62abd853671
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795593520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.3795593520
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.1402704121
Short name T833
Test name
Test status
Simulation time 289688727 ps
CPU time 2.27 seconds
Started Mar 14 12:56:48 PM PDT 24
Finished Mar 14 12:56:51 PM PDT 24
Peak memory 209352 kb
Host smart-0b6d3619-1d7c-4559-8769-c7db331ca141
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1402704121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.1402704121
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.2806678422
Short name T776
Test name
Test status
Simulation time 284949180 ps
CPU time 4.96 seconds
Started Mar 14 12:56:50 PM PDT 24
Finished Mar 14 12:56:55 PM PDT 24
Peak memory 214512 kb
Host smart-423f9f91-7c96-477b-a21d-d08f06d5e754
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2806678422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.2806678422
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.4005127045
Short name T798
Test name
Test status
Simulation time 65214547 ps
CPU time 4.56 seconds
Started Mar 14 12:56:50 PM PDT 24
Finished Mar 14 12:56:55 PM PDT 24
Peak memory 222164 kb
Host smart-71182448-ede8-47e8-a8c1-d8c3ec3d9dee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4005127045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.4005127045
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.2929709662
Short name T695
Test name
Test status
Simulation time 977245353 ps
CPU time 33.74 seconds
Started Mar 14 12:56:47 PM PDT 24
Finished Mar 14 12:57:21 PM PDT 24
Peak memory 211112 kb
Host smart-60649d61-a21a-4e41-8f42-0d48b7a36047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2929709662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.2929709662
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.3475934855
Short name T463
Test name
Test status
Simulation time 92843690 ps
CPU time 4.45 seconds
Started Mar 14 12:56:49 PM PDT 24
Finished Mar 14 12:56:54 PM PDT 24
Peak memory 220764 kb
Host smart-7ae51bec-5aa5-4a55-8ec5-76beda8d09e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3475934855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.3475934855
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.3416386244
Short name T719
Test name
Test status
Simulation time 68234279 ps
CPU time 4.21 seconds
Started Mar 14 12:56:49 PM PDT 24
Finished Mar 14 12:56:54 PM PDT 24
Peak memory 209812 kb
Host smart-63234162-d904-4608-aa9c-4276b9e38a09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3416386244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.3416386244
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.3077467402
Short name T569
Test name
Test status
Simulation time 46914785 ps
CPU time 2.41 seconds
Started Mar 14 12:56:47 PM PDT 24
Finished Mar 14 12:56:50 PM PDT 24
Peak memory 208228 kb
Host smart-d1c11a3f-c07f-4cf0-80b4-391586dc4424
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077467402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.3077467402
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.4185066750
Short name T754
Test name
Test status
Simulation time 528505369 ps
CPU time 5.08 seconds
Started Mar 14 12:56:50 PM PDT 24
Finished Mar 14 12:56:56 PM PDT 24
Peak memory 208180 kb
Host smart-51e2e03d-36e3-4255-aaea-755434c4091c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185066750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.4185066750
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.3472313284
Short name T589
Test name
Test status
Simulation time 33197341 ps
CPU time 2.3 seconds
Started Mar 14 12:56:50 PM PDT 24
Finished Mar 14 12:56:53 PM PDT 24
Peak memory 207112 kb
Host smart-b974f95e-1b0c-4821-848c-144c4d935c08
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3472313284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.3472313284
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.2600798414
Short name T681
Test name
Test status
Simulation time 623600765 ps
CPU time 5.58 seconds
Started Mar 14 12:56:47 PM PDT 24
Finished Mar 14 12:56:53 PM PDT 24
Peak memory 209036 kb
Host smart-507cb522-d534-4e4e-a64d-24101bf13664
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2600798414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.2600798414
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.2352174139
Short name T456
Test name
Test status
Simulation time 1343031682 ps
CPU time 8.15 seconds
Started Mar 14 12:56:50 PM PDT 24
Finished Mar 14 12:56:58 PM PDT 24
Peak memory 210176 kb
Host smart-f4738158-0944-4d67-b08a-51ba2f064351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352174139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.2352174139
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.2245786627
Short name T431
Test name
Test status
Simulation time 36870939 ps
CPU time 2.46 seconds
Started Mar 14 12:56:50 PM PDT 24
Finished Mar 14 12:56:53 PM PDT 24
Peak memory 208704 kb
Host smart-f59c177f-67ed-4377-9422-217e6c631652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245786627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.2245786627
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.2359637816
Short name T307
Test name
Test status
Simulation time 1181062426 ps
CPU time 13.03 seconds
Started Mar 14 12:56:47 PM PDT 24
Finished Mar 14 12:57:00 PM PDT 24
Peak memory 222508 kb
Host smart-a8dc1061-681b-4cef-8fae-f1f598f8a6b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2359637816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.2359637816
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_stress_all_with_rand_reset.1098007452
Short name T126
Test name
Test status
Simulation time 194130656 ps
CPU time 11.91 seconds
Started Mar 14 12:56:52 PM PDT 24
Finished Mar 14 12:57:04 PM PDT 24
Peak memory 222948 kb
Host smart-ebeee4cd-4ba3-442b-b544-01757f9a2966
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098007452 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all_with_rand_reset.1098007452
Directory /workspace/11.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.491505898
Short name T533
Test name
Test status
Simulation time 2388640484 ps
CPU time 51.23 seconds
Started Mar 14 12:56:52 PM PDT 24
Finished Mar 14 12:57:43 PM PDT 24
Peak memory 208980 kb
Host smart-6afb3943-74f2-4e99-8c16-7a5327c8c6b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=491505898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.491505898
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.933416018
Short name T161
Test name
Test status
Simulation time 174559405 ps
CPU time 2.06 seconds
Started Mar 14 12:56:49 PM PDT 24
Finished Mar 14 12:56:51 PM PDT 24
Peak memory 210152 kb
Host smart-f149f591-fc0c-46d6-9f43-7c36ab402b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=933416018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.933416018
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.1475345624
Short name T657
Test name
Test status
Simulation time 25081400 ps
CPU time 0.74 seconds
Started Mar 14 12:56:48 PM PDT 24
Finished Mar 14 12:56:49 PM PDT 24
Peak memory 206264 kb
Host smart-d3ac38a7-9bb1-4d57-b359-66a6c65f231a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475345624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.1475345624
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.1935715188
Short name T396
Test name
Test status
Simulation time 171785902 ps
CPU time 9.56 seconds
Started Mar 14 12:56:51 PM PDT 24
Finished Mar 14 12:57:00 PM PDT 24
Peak memory 214572 kb
Host smart-e93f2fcc-756d-4113-8efb-ae9f148f93e1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1935715188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.1935715188
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.3788679846
Short name T313
Test name
Test status
Simulation time 305026336 ps
CPU time 3.58 seconds
Started Mar 14 12:56:47 PM PDT 24
Finished Mar 14 12:56:51 PM PDT 24
Peak memory 214696 kb
Host smart-d0fc2998-acb3-4ac3-b436-2ac1091ef29d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788679846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.3788679846
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.3535960486
Short name T267
Test name
Test status
Simulation time 41986854 ps
CPU time 2.61 seconds
Started Mar 14 12:56:48 PM PDT 24
Finished Mar 14 12:56:51 PM PDT 24
Peak memory 209132 kb
Host smart-923bbf3c-c4a1-434d-b143-6837d0b2b694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535960486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.3535960486
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.4176378346
Short name T242
Test name
Test status
Simulation time 208239911 ps
CPU time 6.91 seconds
Started Mar 14 12:56:49 PM PDT 24
Finished Mar 14 12:56:56 PM PDT 24
Peak memory 214604 kb
Host smart-95ab39cb-fd24-4dc5-a26a-770aa3e764ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176378346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.4176378346
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.253285333
Short name T54
Test name
Test status
Simulation time 192312845 ps
CPU time 2.7 seconds
Started Mar 14 12:56:52 PM PDT 24
Finished Mar 14 12:56:55 PM PDT 24
Peak memory 208176 kb
Host smart-2cd3cda3-9a12-4ecd-befe-cb7a37579f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=253285333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.253285333
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_sideload.1457528014
Short name T447
Test name
Test status
Simulation time 325908571 ps
CPU time 6.73 seconds
Started Mar 14 12:56:50 PM PDT 24
Finished Mar 14 12:56:57 PM PDT 24
Peak memory 209132 kb
Host smart-a9008861-fe25-47c2-b572-719a69ef5048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457528014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.1457528014
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.4160284453
Short name T742
Test name
Test status
Simulation time 225706850 ps
CPU time 7.23 seconds
Started Mar 14 12:56:48 PM PDT 24
Finished Mar 14 12:56:56 PM PDT 24
Peak memory 208216 kb
Host smart-43621179-cdc9-4380-8c46-58fb9abdaf61
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160284453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.4160284453
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.755695409
Short name T698
Test name
Test status
Simulation time 7789083815 ps
CPU time 55.95 seconds
Started Mar 14 12:56:48 PM PDT 24
Finished Mar 14 12:57:45 PM PDT 24
Peak memory 209228 kb
Host smart-7100a64f-c304-4e90-a99a-ab3507fb5454
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755695409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.755695409
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.2998124393
Short name T378
Test name
Test status
Simulation time 3461317580 ps
CPU time 17.5 seconds
Started Mar 14 12:56:49 PM PDT 24
Finished Mar 14 12:57:07 PM PDT 24
Peak memory 208236 kb
Host smart-80dd7694-aa30-45e5-b018-6e23060e7639
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2998124393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.2998124393
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.1323874156
Short name T376
Test name
Test status
Simulation time 2880896436 ps
CPU time 20.16 seconds
Started Mar 14 12:56:52 PM PDT 24
Finished Mar 14 12:57:12 PM PDT 24
Peak memory 209916 kb
Host smart-414d87bb-4b3a-4dd8-8ec8-83f8eaf52575
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323874156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.1323874156
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.2334014318
Short name T460
Test name
Test status
Simulation time 232406539 ps
CPU time 3.02 seconds
Started Mar 14 12:56:47 PM PDT 24
Finished Mar 14 12:56:50 PM PDT 24
Peak memory 206940 kb
Host smart-30aab836-c7fb-4491-a044-0fa1613c095a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2334014318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.2334014318
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.518961250
Short name T250
Test name
Test status
Simulation time 13195407611 ps
CPU time 180.12 seconds
Started Mar 14 12:56:48 PM PDT 24
Finished Mar 14 12:59:49 PM PDT 24
Peak memory 216516 kb
Host smart-62b55356-2f5c-4312-8ffe-2175fe9dbe41
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=518961250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.518961250
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_stress_all_with_rand_reset.1126004803
Short name T294
Test name
Test status
Simulation time 995700870 ps
CPU time 11.57 seconds
Started Mar 14 12:56:52 PM PDT 24
Finished Mar 14 12:57:03 PM PDT 24
Peak memory 222888 kb
Host smart-2f0201bd-1912-4e67-82da-871308972ae2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1126004803 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all_with_rand_reset.1126004803
Directory /workspace/12.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.3072821032
Short name T545
Test name
Test status
Simulation time 146480950 ps
CPU time 5.67 seconds
Started Mar 14 12:56:50 PM PDT 24
Finished Mar 14 12:56:56 PM PDT 24
Peak memory 208868 kb
Host smart-97d4b0a8-372f-40d8-88ed-adfab1735072
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072821032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.3072821032
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.850936674
Short name T835
Test name
Test status
Simulation time 110802043 ps
CPU time 2.69 seconds
Started Mar 14 12:56:49 PM PDT 24
Finished Mar 14 12:56:52 PM PDT 24
Peak memory 210364 kb
Host smart-471b0fca-b046-4ba3-9732-e96b02102ccb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850936674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.850936674
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.2003581451
Short name T642
Test name
Test status
Simulation time 59709161 ps
CPU time 0.86 seconds
Started Mar 14 12:57:06 PM PDT 24
Finished Mar 14 12:57:07 PM PDT 24
Peak memory 206200 kb
Host smart-71373eba-7770-4911-b5b6-aa572830ed35
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2003581451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.2003581451
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.4168330131
Short name T238
Test name
Test status
Simulation time 41545730 ps
CPU time 2.79 seconds
Started Mar 14 12:56:59 PM PDT 24
Finished Mar 14 12:57:02 PM PDT 24
Peak memory 214704 kb
Host smart-a42785e1-b9d2-4f1e-89d0-6cfdc0a698cd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4168330131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.4168330131
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.3922543225
Short name T889
Test name
Test status
Simulation time 725967191 ps
CPU time 2.52 seconds
Started Mar 14 12:57:00 PM PDT 24
Finished Mar 14 12:57:02 PM PDT 24
Peak memory 209212 kb
Host smart-c7c10d77-dda9-4d4d-90e6-79c86a497dfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922543225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.3922543225
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.3896874065
Short name T443
Test name
Test status
Simulation time 508563031 ps
CPU time 4.21 seconds
Started Mar 14 12:57:11 PM PDT 24
Finished Mar 14 12:57:16 PM PDT 24
Peak memory 209700 kb
Host smart-6523a5a3-c12c-499a-a9ac-e0c751612672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3896874065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.3896874065
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.118153440
Short name T275
Test name
Test status
Simulation time 300693435 ps
CPU time 4.02 seconds
Started Mar 14 12:57:08 PM PDT 24
Finished Mar 14 12:57:13 PM PDT 24
Peak memory 211276 kb
Host smart-d27e1981-f43c-489a-b453-7fa8e2200939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=118153440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.118153440
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.3942068576
Short name T729
Test name
Test status
Simulation time 92008697 ps
CPU time 4.26 seconds
Started Mar 14 12:56:59 PM PDT 24
Finished Mar 14 12:57:03 PM PDT 24
Peak memory 210516 kb
Host smart-890f6f8d-f549-49c7-9bb8-6a8351a5de34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942068576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.3942068576
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.345992201
Short name T815
Test name
Test status
Simulation time 5585837316 ps
CPU time 35.89 seconds
Started Mar 14 12:57:00 PM PDT 24
Finished Mar 14 12:57:36 PM PDT 24
Peak memory 210136 kb
Host smart-2669e5af-2bec-41e9-834a-c619ee2b0868
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345992201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.345992201
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.2117714945
Short name T586
Test name
Test status
Simulation time 1703810190 ps
CPU time 46.02 seconds
Started Mar 14 12:56:48 PM PDT 24
Finished Mar 14 12:57:34 PM PDT 24
Peak memory 208160 kb
Host smart-7f96f0af-dc06-41f3-a027-5d80de439c87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2117714945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.2117714945
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.3614620429
Short name T429
Test name
Test status
Simulation time 950353020 ps
CPU time 7.25 seconds
Started Mar 14 12:56:47 PM PDT 24
Finished Mar 14 12:56:55 PM PDT 24
Peak memory 208816 kb
Host smart-8675bdf5-bbdf-4b7a-87ed-cc203e877984
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3614620429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.3614620429
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.1235162011
Short name T465
Test name
Test status
Simulation time 267885650 ps
CPU time 7.83 seconds
Started Mar 14 12:56:52 PM PDT 24
Finished Mar 14 12:57:00 PM PDT 24
Peak memory 208544 kb
Host smart-16292f19-3fd3-47a1-958b-338f7f75c618
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1235162011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.1235162011
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.3747649550
Short name T893
Test name
Test status
Simulation time 81890373 ps
CPU time 3.14 seconds
Started Mar 14 12:56:50 PM PDT 24
Finished Mar 14 12:56:53 PM PDT 24
Peak memory 208352 kb
Host smart-0d462d7a-8159-4008-a93d-967ef3b59fc5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747649550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.3747649550
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.793749437
Short name T339
Test name
Test status
Simulation time 50982953 ps
CPU time 2.27 seconds
Started Mar 14 12:56:57 PM PDT 24
Finished Mar 14 12:57:00 PM PDT 24
Peak memory 208040 kb
Host smart-2050497e-23e8-4234-9610-1ef8643c5ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=793749437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.793749437
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.787378225
Short name T16
Test name
Test status
Simulation time 134608256 ps
CPU time 3.89 seconds
Started Mar 14 12:56:49 PM PDT 24
Finished Mar 14 12:56:53 PM PDT 24
Peak memory 206968 kb
Host smart-bcd0b18b-17c3-49c5-ae6f-3b2182e730d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787378225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.787378225
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.848386624
Short name T220
Test name
Test status
Simulation time 2356133038 ps
CPU time 48.59 seconds
Started Mar 14 12:56:57 PM PDT 24
Finished Mar 14 12:57:46 PM PDT 24
Peak memory 217164 kb
Host smart-75d05cdb-1323-438c-a16c-5e054be0bba3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=848386624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.848386624
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.1775957499
Short name T574
Test name
Test status
Simulation time 100059907 ps
CPU time 2.29 seconds
Started Mar 14 12:57:07 PM PDT 24
Finished Mar 14 12:57:09 PM PDT 24
Peak memory 207756 kb
Host smart-f277881d-b20d-44a5-b2c5-daafd186447a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775957499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.1775957499
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.3242670879
Short name T723
Test name
Test status
Simulation time 214197516 ps
CPU time 4.19 seconds
Started Mar 14 12:57:02 PM PDT 24
Finished Mar 14 12:57:07 PM PDT 24
Peak memory 210528 kb
Host smart-063682a0-53ab-4189-8360-44aa3374ab2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3242670879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.3242670879
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.598911152
Short name T846
Test name
Test status
Simulation time 13570756 ps
CPU time 0.72 seconds
Started Mar 14 12:57:10 PM PDT 24
Finished Mar 14 12:57:11 PM PDT 24
Peak memory 206112 kb
Host smart-1e471b41-863f-47a3-8c00-dc5027aa199d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=598911152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.598911152
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.1302099398
Short name T392
Test name
Test status
Simulation time 86590979 ps
CPU time 2.79 seconds
Started Mar 14 12:56:59 PM PDT 24
Finished Mar 14 12:57:02 PM PDT 24
Peak memory 215348 kb
Host smart-cd3d670f-4736-4ab7-9369-74b08edbf3f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1302099398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.1302099398
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.2323554529
Short name T71
Test name
Test status
Simulation time 112286309 ps
CPU time 3.23 seconds
Started Mar 14 12:56:59 PM PDT 24
Finished Mar 14 12:57:02 PM PDT 24
Peak memory 210384 kb
Host smart-b5a3cfc8-bc5d-4ccd-9f51-5958d95ea7ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323554529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.2323554529
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.2717095976
Short name T713
Test name
Test status
Simulation time 171088754 ps
CPU time 4.1 seconds
Started Mar 14 12:56:58 PM PDT 24
Finished Mar 14 12:57:02 PM PDT 24
Peak memory 209844 kb
Host smart-21185881-dc90-4abf-afbc-93986d2215bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717095976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.2717095976
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.3391038670
Short name T703
Test name
Test status
Simulation time 707136207 ps
CPU time 3.69 seconds
Started Mar 14 12:57:05 PM PDT 24
Finished Mar 14 12:57:09 PM PDT 24
Peak memory 211060 kb
Host smart-79c90551-7594-4a03-8ad3-0d1d76bbc04a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391038670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.3391038670
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.1327873467
Short name T212
Test name
Test status
Simulation time 2343857888 ps
CPU time 23.9 seconds
Started Mar 14 12:57:05 PM PDT 24
Finished Mar 14 12:57:29 PM PDT 24
Peak memory 210152 kb
Host smart-0c427451-9dea-4390-afa3-c088cb78cffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327873467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.1327873467
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.3432794033
Short name T901
Test name
Test status
Simulation time 502749434 ps
CPU time 7.22 seconds
Started Mar 14 12:57:00 PM PDT 24
Finished Mar 14 12:57:08 PM PDT 24
Peak memory 209568 kb
Host smart-6a1c221a-703f-4c5b-8553-44f4188c0cc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3432794033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.3432794033
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.2921228313
Short name T559
Test name
Test status
Simulation time 114653025 ps
CPU time 2.5 seconds
Started Mar 14 12:57:01 PM PDT 24
Finished Mar 14 12:57:04 PM PDT 24
Peak memory 207520 kb
Host smart-f622b04b-f7eb-42b7-9813-713d35f6e468
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2921228313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.2921228313
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.1326593218
Short name T704
Test name
Test status
Simulation time 195201933 ps
CPU time 2.82 seconds
Started Mar 14 12:57:07 PM PDT 24
Finished Mar 14 12:57:10 PM PDT 24
Peak memory 208896 kb
Host smart-ae6dc36b-77e8-43bf-8b75-2082d1572215
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326593218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.1326593218
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.1939914772
Short name T647
Test name
Test status
Simulation time 341743920 ps
CPU time 5.31 seconds
Started Mar 14 12:57:01 PM PDT 24
Finished Mar 14 12:57:06 PM PDT 24
Peak memory 208100 kb
Host smart-c1a8d7ad-97db-476e-b8c0-27185168816c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1939914772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.1939914772
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.910614826
Short name T321
Test name
Test status
Simulation time 371224349 ps
CPU time 3.97 seconds
Started Mar 14 12:57:06 PM PDT 24
Finished Mar 14 12:57:10 PM PDT 24
Peak memory 207704 kb
Host smart-7cf5a277-8c2e-482e-8859-435b1fb20d41
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=910614826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.910614826
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.3048289408
Short name T524
Test name
Test status
Simulation time 55441127 ps
CPU time 2.2 seconds
Started Mar 14 12:57:01 PM PDT 24
Finished Mar 14 12:57:03 PM PDT 24
Peak memory 208232 kb
Host smart-ff30f866-389e-4640-9645-b16bebff47fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048289408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.3048289408
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.2753673624
Short name T251
Test name
Test status
Simulation time 142499896 ps
CPU time 4.95 seconds
Started Mar 14 12:56:59 PM PDT 24
Finished Mar 14 12:57:04 PM PDT 24
Peak memory 209060 kb
Host smart-dd3a0783-4741-4619-8367-4946785011d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753673624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.2753673624
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.2022976085
Short name T367
Test name
Test status
Simulation time 32354950 ps
CPU time 1.79 seconds
Started Mar 14 12:56:56 PM PDT 24
Finished Mar 14 12:56:58 PM PDT 24
Peak memory 209960 kb
Host smart-245946cb-7556-400f-beef-2bf8ab8f3329
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022976085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.2022976085
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.547118311
Short name T869
Test name
Test status
Simulation time 37626747 ps
CPU time 0.88 seconds
Started Mar 14 12:56:57 PM PDT 24
Finished Mar 14 12:56:58 PM PDT 24
Peak memory 206260 kb
Host smart-8e1962af-bc33-4be9-89c4-80e711af6f45
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=547118311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.547118311
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.2253030408
Short name T327
Test name
Test status
Simulation time 1767536948 ps
CPU time 43.22 seconds
Started Mar 14 12:57:08 PM PDT 24
Finished Mar 14 12:57:52 PM PDT 24
Peak memory 218836 kb
Host smart-3c252f7c-09f3-45df-9452-f52dbb00f2b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2253030408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.2253030408
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.694734411
Short name T436
Test name
Test status
Simulation time 269283139 ps
CPU time 8.08 seconds
Started Mar 14 12:56:57 PM PDT 24
Finished Mar 14 12:57:05 PM PDT 24
Peak memory 214548 kb
Host smart-87489d9e-0d2e-46ed-9ffd-1d40cee3396a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694734411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.694734411
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.2660995461
Short name T458
Test name
Test status
Simulation time 75887162 ps
CPU time 2.82 seconds
Started Mar 14 12:56:59 PM PDT 24
Finished Mar 14 12:57:01 PM PDT 24
Peak memory 214584 kb
Host smart-261f1ccd-55ee-45cf-bb1b-9874c2f93266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660995461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.2660995461
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.3865595813
Short name T449
Test name
Test status
Simulation time 302561600 ps
CPU time 7.99 seconds
Started Mar 14 12:56:57 PM PDT 24
Finished Mar 14 12:57:05 PM PDT 24
Peak memory 209024 kb
Host smart-d4a072a2-4b11-4ccc-82d5-aeb7d35056f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865595813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.3865595813
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.3949767434
Short name T674
Test name
Test status
Simulation time 118715412 ps
CPU time 2.37 seconds
Started Mar 14 12:57:10 PM PDT 24
Finished Mar 14 12:57:12 PM PDT 24
Peak memory 206860 kb
Host smart-5aad532a-918b-4bdd-a39c-c9574cd246a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949767434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.3949767434
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.280264143
Short name T354
Test name
Test status
Simulation time 165232578 ps
CPU time 2.44 seconds
Started Mar 14 12:56:58 PM PDT 24
Finished Mar 14 12:57:00 PM PDT 24
Peak memory 208140 kb
Host smart-df75412b-a13b-47fd-83fb-7c5f0fd7109d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=280264143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.280264143
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.504668483
Short name T488
Test name
Test status
Simulation time 371796523 ps
CPU time 4.61 seconds
Started Mar 14 12:57:01 PM PDT 24
Finished Mar 14 12:57:06 PM PDT 24
Peak memory 208988 kb
Host smart-3af084a9-3e5e-4953-8ae5-ce0e3e7303f3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=504668483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.504668483
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.3847133068
Short name T688
Test name
Test status
Simulation time 110170354 ps
CPU time 2.71 seconds
Started Mar 14 12:57:11 PM PDT 24
Finished Mar 14 12:57:14 PM PDT 24
Peak memory 208840 kb
Host smart-c680d588-962c-4612-b84c-22913887e772
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3847133068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.3847133068
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.2744212564
Short name T628
Test name
Test status
Simulation time 82686194 ps
CPU time 2.17 seconds
Started Mar 14 12:56:57 PM PDT 24
Finished Mar 14 12:56:59 PM PDT 24
Peak memory 214544 kb
Host smart-2e022f4d-31b2-436b-bd66-55e950fbdc05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744212564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.2744212564
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.2918288811
Short name T425
Test name
Test status
Simulation time 2441116530 ps
CPU time 22.8 seconds
Started Mar 14 12:57:00 PM PDT 24
Finished Mar 14 12:57:23 PM PDT 24
Peak memory 207800 kb
Host smart-2d8f2d4b-fa5e-4406-859c-afb8ee5035a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2918288811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.2918288811
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.3083897211
Short name T841
Test name
Test status
Simulation time 775632631 ps
CPU time 6.09 seconds
Started Mar 14 12:57:07 PM PDT 24
Finished Mar 14 12:57:14 PM PDT 24
Peak memory 207784 kb
Host smart-9b1d36ed-c487-4355-ab85-c0bcc0c9c264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083897211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.3083897211
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.3728471598
Short name T33
Test name
Test status
Simulation time 83614686 ps
CPU time 2.8 seconds
Started Mar 14 12:56:59 PM PDT 24
Finished Mar 14 12:57:02 PM PDT 24
Peak memory 210640 kb
Host smart-b3748e0d-3981-4d56-bce5-6743ecadea7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3728471598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.3728471598
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.480522274
Short name T598
Test name
Test status
Simulation time 10299861 ps
CPU time 0.75 seconds
Started Mar 14 12:57:07 PM PDT 24
Finished Mar 14 12:57:08 PM PDT 24
Peak memory 206536 kb
Host smart-6329f571-8674-4108-85ac-bd94f33a3fa3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=480522274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.480522274
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.2335708575
Short name T906
Test name
Test status
Simulation time 72738089 ps
CPU time 1.98 seconds
Started Mar 14 12:57:09 PM PDT 24
Finished Mar 14 12:57:11 PM PDT 24
Peak memory 214908 kb
Host smart-e11f7ad0-25e0-4b91-9ff0-100cb54b3fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335708575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.2335708575
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.1405651425
Short name T304
Test name
Test status
Simulation time 39073995 ps
CPU time 2.32 seconds
Started Mar 14 12:57:05 PM PDT 24
Finished Mar 14 12:57:07 PM PDT 24
Peak memory 207332 kb
Host smart-62e0c7c7-e6f9-47f4-bf70-e285086cfca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405651425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.1405651425
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.929121400
Short name T830
Test name
Test status
Simulation time 553702025 ps
CPU time 16.09 seconds
Started Mar 14 12:57:06 PM PDT 24
Finished Mar 14 12:57:22 PM PDT 24
Peak memory 208748 kb
Host smart-49ee715f-0f6f-4262-996c-684645abe71f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929121400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.929121400
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.606603506
Short name T199
Test name
Test status
Simulation time 293314283 ps
CPU time 6.27 seconds
Started Mar 14 12:57:06 PM PDT 24
Finished Mar 14 12:57:12 PM PDT 24
Peak memory 222628 kb
Host smart-1c6a9bd4-a862-4189-a35d-0c79bdc53903
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606603506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.606603506
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.2075716959
Short name T568
Test name
Test status
Simulation time 90938656 ps
CPU time 2.66 seconds
Started Mar 14 12:57:06 PM PDT 24
Finished Mar 14 12:57:09 PM PDT 24
Peak memory 220400 kb
Host smart-b02e925a-961c-4063-9303-878129500a95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2075716959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.2075716959
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.679671693
Short name T665
Test name
Test status
Simulation time 88654691 ps
CPU time 3.05 seconds
Started Mar 14 12:57:07 PM PDT 24
Finished Mar 14 12:57:10 PM PDT 24
Peak memory 210280 kb
Host smart-cc2dd188-26f3-49ff-923a-9228c23f051b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679671693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.679671693
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.2248009367
Short name T474
Test name
Test status
Simulation time 774235430 ps
CPU time 19.8 seconds
Started Mar 14 12:56:57 PM PDT 24
Finished Mar 14 12:57:17 PM PDT 24
Peak memory 208604 kb
Host smart-7756e96b-eca2-4576-bfa9-23cc90288caf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248009367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.2248009367
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.2648255397
Short name T410
Test name
Test status
Simulation time 122333346 ps
CPU time 3.02 seconds
Started Mar 14 12:57:08 PM PDT 24
Finished Mar 14 12:57:11 PM PDT 24
Peak memory 207116 kb
Host smart-4499f253-6783-4fc7-a065-4cb7717cd244
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648255397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.2648255397
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.388060685
Short name T247
Test name
Test status
Simulation time 104479382 ps
CPU time 2.05 seconds
Started Mar 14 12:57:06 PM PDT 24
Finished Mar 14 12:57:08 PM PDT 24
Peak memory 209072 kb
Host smart-2fec73b8-3eab-46bc-a09f-aba22e2615d8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388060685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.388060685
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.204617541
Short name T421
Test name
Test status
Simulation time 199235705 ps
CPU time 4.39 seconds
Started Mar 14 12:57:07 PM PDT 24
Finished Mar 14 12:57:11 PM PDT 24
Peak memory 207144 kb
Host smart-fdd2c3b1-7ade-4ff0-a880-a002de073296
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=204617541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.204617541
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.34050168
Short name T252
Test name
Test status
Simulation time 1147833152 ps
CPU time 18.67 seconds
Started Mar 14 12:57:08 PM PDT 24
Finished Mar 14 12:57:28 PM PDT 24
Peak memory 209248 kb
Host smart-293b2e26-b052-4fbf-b1fc-919b36a2e51f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34050168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.34050168
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.953359085
Short name T480
Test name
Test status
Simulation time 962480278 ps
CPU time 10.08 seconds
Started Mar 14 12:57:19 PM PDT 24
Finished Mar 14 12:57:29 PM PDT 24
Peak memory 214504 kb
Host smart-33687b62-a9ca-4e20-afb4-99d64d6de03b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953359085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.953359085
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.2084373938
Short name T605
Test name
Test status
Simulation time 185242281 ps
CPU time 5.79 seconds
Started Mar 14 12:57:05 PM PDT 24
Finished Mar 14 12:57:11 PM PDT 24
Peak memory 210472 kb
Host smart-1c5969d9-5511-4369-bd32-fed332f982bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084373938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.2084373938
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.3391231974
Short name T544
Test name
Test status
Simulation time 50542911 ps
CPU time 0.78 seconds
Started Mar 14 12:57:22 PM PDT 24
Finished Mar 14 12:57:22 PM PDT 24
Peak memory 206148 kb
Host smart-7edc628c-f9ad-4c63-b76b-ef6211333847
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391231974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.3391231974
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.3220047446
Short name T390
Test name
Test status
Simulation time 1034031010 ps
CPU time 56.99 seconds
Started Mar 14 12:57:11 PM PDT 24
Finished Mar 14 12:58:08 PM PDT 24
Peak memory 214624 kb
Host smart-2606274a-1106-49a4-9620-40884ff3c744
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3220047446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.3220047446
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.3061684607
Short name T555
Test name
Test status
Simulation time 54004473 ps
CPU time 2.15 seconds
Started Mar 14 12:57:05 PM PDT 24
Finished Mar 14 12:57:07 PM PDT 24
Peak memory 220488 kb
Host smart-a6c63264-2679-4736-8f42-4f44d2d5ae2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3061684607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.3061684607
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.1392813052
Short name T452
Test name
Test status
Simulation time 47784401 ps
CPU time 1.78 seconds
Started Mar 14 12:57:08 PM PDT 24
Finished Mar 14 12:57:10 PM PDT 24
Peak memory 208392 kb
Host smart-de6a28a7-ff10-4556-aa34-90982e1d5b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392813052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.1392813052
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.468760076
Short name T350
Test name
Test status
Simulation time 7813864656 ps
CPU time 25.89 seconds
Started Mar 14 12:57:11 PM PDT 24
Finished Mar 14 12:57:37 PM PDT 24
Peak memory 222648 kb
Host smart-b8a2c249-384c-48bb-be83-663be57fc038
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468760076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.468760076
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.436361110
Short name T213
Test name
Test status
Simulation time 401508069 ps
CPU time 2.14 seconds
Started Mar 14 12:57:07 PM PDT 24
Finished Mar 14 12:57:09 PM PDT 24
Peak memory 220692 kb
Host smart-7eb461ee-717a-4d0b-9b9e-620c414b16dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=436361110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.436361110
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.3025840417
Short name T448
Test name
Test status
Simulation time 277883507 ps
CPU time 3.46 seconds
Started Mar 14 12:57:22 PM PDT 24
Finished Mar 14 12:57:25 PM PDT 24
Peak memory 210056 kb
Host smart-9fdf1cb1-035a-4b20-a0dd-7c15839e13d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025840417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.3025840417
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.125951323
Short name T80
Test name
Test status
Simulation time 567637219 ps
CPU time 5.64 seconds
Started Mar 14 12:57:07 PM PDT 24
Finished Mar 14 12:57:13 PM PDT 24
Peak memory 206904 kb
Host smart-85eda545-9fef-419a-bb84-20013a7e14f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=125951323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.125951323
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.1943252997
Short name T895
Test name
Test status
Simulation time 59748138 ps
CPU time 3.24 seconds
Started Mar 14 12:57:09 PM PDT 24
Finished Mar 14 12:57:13 PM PDT 24
Peak memory 209016 kb
Host smart-882e4c74-6b0b-4de5-8bf5-ea6bf20a080e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1943252997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.1943252997
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.2361503521
Short name T320
Test name
Test status
Simulation time 91652128 ps
CPU time 2.78 seconds
Started Mar 14 12:57:04 PM PDT 24
Finished Mar 14 12:57:07 PM PDT 24
Peak memory 208588 kb
Host smart-cb306a75-4325-43a9-a5a0-fa2f7ed04340
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2361503521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.2361503521
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.2810229412
Short name T462
Test name
Test status
Simulation time 115223848 ps
CPU time 1.78 seconds
Started Mar 14 12:57:08 PM PDT 24
Finished Mar 14 12:57:10 PM PDT 24
Peak memory 210048 kb
Host smart-688ce269-f331-4562-9e00-48e0b0fac4b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810229412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.2810229412
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.504246501
Short name T494
Test name
Test status
Simulation time 24220425 ps
CPU time 1.72 seconds
Started Mar 14 12:57:06 PM PDT 24
Finished Mar 14 12:57:07 PM PDT 24
Peak memory 207508 kb
Host smart-b0fa8148-4e89-4b80-a3b4-649dac82a13e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504246501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.504246501
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.1425128215
Short name T801
Test name
Test status
Simulation time 17165579 ps
CPU time 0.73 seconds
Started Mar 14 12:57:08 PM PDT 24
Finished Mar 14 12:57:09 PM PDT 24
Peak memory 206152 kb
Host smart-a7d8170e-09b0-45ed-ba0a-3263d4999155
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1425128215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.1425128215
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.3084405476
Short name T701
Test name
Test status
Simulation time 123688887 ps
CPU time 2.16 seconds
Started Mar 14 12:57:06 PM PDT 24
Finished Mar 14 12:57:08 PM PDT 24
Peak memory 207748 kb
Host smart-5fe0639c-188a-4dca-9959-72211cee67e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084405476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.3084405476
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.1575172420
Short name T365
Test name
Test status
Simulation time 217587799 ps
CPU time 4.93 seconds
Started Mar 14 12:57:11 PM PDT 24
Finished Mar 14 12:57:16 PM PDT 24
Peak memory 210724 kb
Host smart-5ef852e9-6e1d-4431-b112-3c05d9eebb77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575172420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.1575172420
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.997334137
Short name T102
Test name
Test status
Simulation time 298043622 ps
CPU time 4.09 seconds
Started Mar 14 12:57:06 PM PDT 24
Finished Mar 14 12:57:11 PM PDT 24
Peak memory 214564 kb
Host smart-1373d934-1f00-4b05-b155-43df0252f382
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=997334137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.997334137
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.2411595553
Short name T466
Test name
Test status
Simulation time 262452909 ps
CPU time 3.58 seconds
Started Mar 14 12:57:18 PM PDT 24
Finished Mar 14 12:57:21 PM PDT 24
Peak memory 210168 kb
Host smart-9b6648dd-cb50-4ccc-a2ce-9a39b82a2588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411595553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.2411595553
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.617745399
Short name T821
Test name
Test status
Simulation time 241624170 ps
CPU time 3.7 seconds
Started Mar 14 12:57:09 PM PDT 24
Finished Mar 14 12:57:12 PM PDT 24
Peak memory 214572 kb
Host smart-419fda2e-d33e-4a81-b561-a673e42c78a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617745399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.617745399
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.653775384
Short name T96
Test name
Test status
Simulation time 147929687 ps
CPU time 5.57 seconds
Started Mar 14 12:57:15 PM PDT 24
Finished Mar 14 12:57:21 PM PDT 24
Peak memory 209872 kb
Host smart-e31f3abb-3751-4304-8fe8-8f65e3f7b68f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653775384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.653775384
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.87097687
Short name T260
Test name
Test status
Simulation time 116319046 ps
CPU time 5.86 seconds
Started Mar 14 12:57:18 PM PDT 24
Finished Mar 14 12:57:24 PM PDT 24
Peak memory 222724 kb
Host smart-67559c9e-a617-442e-99fb-81e66429c9b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87097687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.87097687
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.2970501901
Short name T428
Test name
Test status
Simulation time 101985292 ps
CPU time 3.56 seconds
Started Mar 14 12:57:16 PM PDT 24
Finished Mar 14 12:57:20 PM PDT 24
Peak memory 209476 kb
Host smart-07647c43-28b7-4865-91fa-70402f227e2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970501901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.2970501901
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.3370775282
Short name T806
Test name
Test status
Simulation time 1679743639 ps
CPU time 4.25 seconds
Started Mar 14 12:57:06 PM PDT 24
Finished Mar 14 12:57:10 PM PDT 24
Peak memory 210516 kb
Host smart-4c40779f-450a-4902-aeba-6bbb2372a985
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3370775282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.3370775282
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.1222463231
Short name T894
Test name
Test status
Simulation time 29126466 ps
CPU time 2 seconds
Started Mar 14 12:57:13 PM PDT 24
Finished Mar 14 12:57:15 PM PDT 24
Peak memory 207184 kb
Host smart-d125ecab-d48f-46c8-ba07-41aacece7666
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1222463231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.1222463231
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.2088831523
Short name T655
Test name
Test status
Simulation time 856983992 ps
CPU time 9.21 seconds
Started Mar 14 12:57:10 PM PDT 24
Finished Mar 14 12:57:19 PM PDT 24
Peak memory 209352 kb
Host smart-ada9e6d9-8bb6-46b1-88f5-83a61337f795
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2088831523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.2088831523
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.148700157
Short name T826
Test name
Test status
Simulation time 74936648 ps
CPU time 1.71 seconds
Started Mar 14 12:57:09 PM PDT 24
Finished Mar 14 12:57:11 PM PDT 24
Peak memory 207096 kb
Host smart-6aa2605a-4423-4515-9977-49c0599df734
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=148700157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.148700157
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.1028453569
Short name T725
Test name
Test status
Simulation time 205239356 ps
CPU time 3.12 seconds
Started Mar 14 12:57:04 PM PDT 24
Finished Mar 14 12:57:07 PM PDT 24
Peak memory 208752 kb
Host smart-33432a50-e309-4269-8c6f-10923cf6ba54
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028453569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.1028453569
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.2123574143
Short name T264
Test name
Test status
Simulation time 93898837 ps
CPU time 2.17 seconds
Started Mar 14 12:57:18 PM PDT 24
Finished Mar 14 12:57:20 PM PDT 24
Peak memory 209968 kb
Host smart-08c7c29d-14ec-49be-9c86-47eea7a9b3b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2123574143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.2123574143
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.2218033539
Short name T617
Test name
Test status
Simulation time 223666933 ps
CPU time 2.56 seconds
Started Mar 14 12:57:19 PM PDT 24
Finished Mar 14 12:57:22 PM PDT 24
Peak memory 206836 kb
Host smart-a1738be4-bfc3-45a1-824b-8bef92372440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218033539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.2218033539
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.1062407208
Short name T672
Test name
Test status
Simulation time 119695210 ps
CPU time 5.34 seconds
Started Mar 14 12:57:17 PM PDT 24
Finished Mar 14 12:57:22 PM PDT 24
Peak memory 218776 kb
Host smart-a92fc8d4-ab33-4a39-ad9e-2befe6b42068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1062407208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.1062407208
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.2035967803
Short name T457
Test name
Test status
Simulation time 56884502 ps
CPU time 1.79 seconds
Started Mar 14 12:57:16 PM PDT 24
Finished Mar 14 12:57:18 PM PDT 24
Peak memory 210168 kb
Host smart-a7508ee2-3f85-4e6c-b245-db033e7d2f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035967803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.2035967803
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.3862091520
Short name T484
Test name
Test status
Simulation time 46148319 ps
CPU time 0.9 seconds
Started Mar 14 12:57:17 PM PDT 24
Finished Mar 14 12:57:18 PM PDT 24
Peak memory 206184 kb
Host smart-857bbcd2-9be8-4cc1-9052-98d47dece496
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3862091520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.3862091520
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.4032928831
Short name T374
Test name
Test status
Simulation time 141129535 ps
CPU time 2.85 seconds
Started Mar 14 12:57:15 PM PDT 24
Finished Mar 14 12:57:18 PM PDT 24
Peak memory 214784 kb
Host smart-b52727e7-eb7c-49b5-8ea6-6dd70fc57d4e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4032928831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.4032928831
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.1597058745
Short name T577
Test name
Test status
Simulation time 116003861 ps
CPU time 1.76 seconds
Started Mar 14 12:57:15 PM PDT 24
Finished Mar 14 12:57:17 PM PDT 24
Peak memory 207676 kb
Host smart-45314602-c6e5-48c9-9b90-74293c5619d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597058745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.1597058745
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.3560800668
Short name T90
Test name
Test status
Simulation time 74259915 ps
CPU time 2.94 seconds
Started Mar 14 12:57:16 PM PDT 24
Finished Mar 14 12:57:19 PM PDT 24
Peak memory 209284 kb
Host smart-2c519d04-4f39-44ca-90a4-0bd829d39aed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560800668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.3560800668
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.3689077454
Short name T314
Test name
Test status
Simulation time 76961536 ps
CPU time 4.48 seconds
Started Mar 14 12:57:16 PM PDT 24
Finished Mar 14 12:57:21 PM PDT 24
Peak memory 210276 kb
Host smart-9fc0dcc9-2c83-49ab-b7ff-7d9c83f59889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689077454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.3689077454
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_random.2152374077
Short name T536
Test name
Test status
Simulation time 102311237 ps
CPU time 5 seconds
Started Mar 14 12:57:17 PM PDT 24
Finished Mar 14 12:57:22 PM PDT 24
Peak memory 208176 kb
Host smart-4dc3327c-171e-463c-ad91-7c155b57d222
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2152374077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.2152374077
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.2250415427
Short name T492
Test name
Test status
Simulation time 35740596 ps
CPU time 2.33 seconds
Started Mar 14 12:57:16 PM PDT 24
Finished Mar 14 12:57:18 PM PDT 24
Peak memory 206896 kb
Host smart-b8941235-87e9-4277-a7d0-aee62d12c070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250415427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.2250415427
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.3790028138
Short name T483
Test name
Test status
Simulation time 443118483 ps
CPU time 5.8 seconds
Started Mar 14 12:57:17 PM PDT 24
Finished Mar 14 12:57:23 PM PDT 24
Peak memory 206424 kb
Host smart-37840128-ec7e-4048-a42a-81a0f0a46383
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790028138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.3790028138
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.4070391369
Short name T832
Test name
Test status
Simulation time 164380394 ps
CPU time 2.89 seconds
Started Mar 14 12:57:21 PM PDT 24
Finished Mar 14 12:57:24 PM PDT 24
Peak memory 207108 kb
Host smart-07ff3304-255c-4d5b-a0de-e09bc351e1eb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4070391369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.4070391369
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.483898603
Short name T576
Test name
Test status
Simulation time 846831937 ps
CPU time 30.29 seconds
Started Mar 14 12:57:18 PM PDT 24
Finished Mar 14 12:57:48 PM PDT 24
Peak memory 207932 kb
Host smart-22f5f9be-be63-4200-8fc9-62729bd95c9f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=483898603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.483898603
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.2634593772
Short name T735
Test name
Test status
Simulation time 130771594 ps
CPU time 3.16 seconds
Started Mar 14 12:57:17 PM PDT 24
Finished Mar 14 12:57:20 PM PDT 24
Peak memory 209136 kb
Host smart-eee3f847-712b-4e91-92e1-2b28c89bb3a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634593772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.2634593772
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.858025602
Short name T422
Test name
Test status
Simulation time 124380401 ps
CPU time 3.46 seconds
Started Mar 14 12:57:15 PM PDT 24
Finished Mar 14 12:57:19 PM PDT 24
Peak memory 208520 kb
Host smart-12bcebb6-a6f7-48d2-9539-73fc0906cc38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=858025602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.858025602
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.1500800421
Short name T70
Test name
Test status
Simulation time 6418278915 ps
CPU time 47.27 seconds
Started Mar 14 12:57:18 PM PDT 24
Finished Mar 14 12:58:05 PM PDT 24
Peak memory 215416 kb
Host smart-a884bca7-aa22-47a8-8f2f-6fb461a8a9e1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500800421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.1500800421
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.345773543
Short name T696
Test name
Test status
Simulation time 207865826 ps
CPU time 6.61 seconds
Started Mar 14 12:57:22 PM PDT 24
Finished Mar 14 12:57:29 PM PDT 24
Peak memory 207952 kb
Host smart-8c3b2fdb-76a3-4d27-94a9-93127552c884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345773543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.345773543
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.980905983
Short name T468
Test name
Test status
Simulation time 358298941 ps
CPU time 2.53 seconds
Started Mar 14 12:57:17 PM PDT 24
Finished Mar 14 12:57:20 PM PDT 24
Peak memory 209484 kb
Host smart-d5b5d136-20e7-4b3f-a4eb-398332c38d98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980905983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.980905983
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.1764889408
Short name T408
Test name
Test status
Simulation time 15534042 ps
CPU time 0.93 seconds
Started Mar 14 12:55:42 PM PDT 24
Finished Mar 14 12:55:43 PM PDT 24
Peak memory 206456 kb
Host smart-829e259a-b560-4a9b-95e4-680b0ae6dab8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764889408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.1764889408
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.2747145933
Short name T858
Test name
Test status
Simulation time 2711813008 ps
CPU time 138.98 seconds
Started Mar 14 12:55:30 PM PDT 24
Finished Mar 14 12:57:49 PM PDT 24
Peak memory 215848 kb
Host smart-d9d85711-1ff6-4af2-830c-3ae9accd1ca3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2747145933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.2747145933
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.305117371
Short name T812
Test name
Test status
Simulation time 260833641 ps
CPU time 2.42 seconds
Started Mar 14 12:55:29 PM PDT 24
Finished Mar 14 12:55:32 PM PDT 24
Peak memory 217004 kb
Host smart-49161ae2-4628-427f-828f-d20bcb495e3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305117371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.305117371
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.1015386496
Short name T579
Test name
Test status
Simulation time 731419179 ps
CPU time 6.82 seconds
Started Mar 14 12:55:29 PM PDT 24
Finished Mar 14 12:55:36 PM PDT 24
Peak memory 208492 kb
Host smart-fa84459e-4bad-4160-81c0-7dd0141009a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015386496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.1015386496
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.3949180426
Short name T814
Test name
Test status
Simulation time 31699919 ps
CPU time 2.19 seconds
Started Mar 14 12:55:29 PM PDT 24
Finished Mar 14 12:55:31 PM PDT 24
Peak memory 209284 kb
Host smart-6689a013-2040-475e-ad4f-eced27c0f946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3949180426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.3949180426
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.1982540382
Short name T500
Test name
Test status
Simulation time 5669362701 ps
CPU time 49.89 seconds
Started Mar 14 12:55:29 PM PDT 24
Finished Mar 14 12:56:20 PM PDT 24
Peak memory 222788 kb
Host smart-a52acba7-def2-4f38-bfe7-4493e48f5f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982540382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.1982540382
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.3139493048
Short name T65
Test name
Test status
Simulation time 84320359 ps
CPU time 4.7 seconds
Started Mar 14 12:55:29 PM PDT 24
Finished Mar 14 12:55:34 PM PDT 24
Peak memory 210008 kb
Host smart-7288b376-9d94-4525-b490-c1728ccb03ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139493048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.3139493048
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.3770428859
Short name T630
Test name
Test status
Simulation time 142889527 ps
CPU time 4.73 seconds
Started Mar 14 12:55:29 PM PDT 24
Finished Mar 14 12:55:34 PM PDT 24
Peak memory 207704 kb
Host smart-37c3332a-755a-496d-8a1c-1e7d3f4b72a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770428859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.3770428859
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.3890614251
Short name T10
Test name
Test status
Simulation time 8786408317 ps
CPU time 20.43 seconds
Started Mar 14 12:55:38 PM PDT 24
Finished Mar 14 12:55:58 PM PDT 24
Peak memory 232080 kb
Host smart-33a2f62f-018c-4315-b8ea-2e1c19c794a8
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890614251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.3890614251
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.3828796846
Short name T417
Test name
Test status
Simulation time 290313705 ps
CPU time 7.05 seconds
Started Mar 14 12:55:29 PM PDT 24
Finished Mar 14 12:55:37 PM PDT 24
Peak memory 208024 kb
Host smart-afa1c743-6c46-4ba8-a599-3b1710498e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828796846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.3828796846
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.627943416
Short name T872
Test name
Test status
Simulation time 132863794 ps
CPU time 2.43 seconds
Started Mar 14 12:55:29 PM PDT 24
Finished Mar 14 12:55:31 PM PDT 24
Peak memory 208824 kb
Host smart-2138b4e6-cd5f-429a-ab50-2d42c09db752
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=627943416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.627943416
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.3916422827
Short name T439
Test name
Test status
Simulation time 465944727 ps
CPU time 8.03 seconds
Started Mar 14 12:55:29 PM PDT 24
Finished Mar 14 12:55:37 PM PDT 24
Peak memory 208928 kb
Host smart-5ffeb810-57f2-4634-b42c-4f98bec02b49
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916422827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.3916422827
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.3788783284
Short name T338
Test name
Test status
Simulation time 437964801 ps
CPU time 4.76 seconds
Started Mar 14 12:55:28 PM PDT 24
Finished Mar 14 12:55:33 PM PDT 24
Peak memory 208344 kb
Host smart-d1575c57-32ad-4164-ba14-ca3af3f1bd70
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788783284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.3788783284
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.991594547
Short name T572
Test name
Test status
Simulation time 32975065 ps
CPU time 1.64 seconds
Started Mar 14 12:55:32 PM PDT 24
Finished Mar 14 12:55:33 PM PDT 24
Peak memory 216408 kb
Host smart-24d09ae5-e990-4106-b0e7-d6c3e4440d39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991594547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.991594547
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.4262809341
Short name T706
Test name
Test status
Simulation time 140037666 ps
CPU time 2.54 seconds
Started Mar 14 12:55:29 PM PDT 24
Finished Mar 14 12:55:32 PM PDT 24
Peak memory 207300 kb
Host smart-39d2afd2-db2a-4ecd-aeb7-8c4e6d197ead
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262809341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.4262809341
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.3491124836
Short name T253
Test name
Test status
Simulation time 2651432873 ps
CPU time 71.53 seconds
Started Mar 14 12:55:28 PM PDT 24
Finished Mar 14 12:56:40 PM PDT 24
Peak memory 214692 kb
Host smart-70d0737a-dea6-4ee0-b1d3-f3ff7b381981
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3491124836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.3491124836
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.495416044
Short name T775
Test name
Test status
Simulation time 254642083 ps
CPU time 2.68 seconds
Started Mar 14 12:55:31 PM PDT 24
Finished Mar 14 12:55:34 PM PDT 24
Peak memory 210544 kb
Host smart-23df345e-3b4f-43a2-a77d-84106d07d9f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495416044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.495416044
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.2536052595
Short name T643
Test name
Test status
Simulation time 15248323 ps
CPU time 0.91 seconds
Started Mar 14 12:57:26 PM PDT 24
Finished Mar 14 12:57:27 PM PDT 24
Peak memory 206372 kb
Host smart-90140610-4786-4b6d-ba3f-9d98c80e2195
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536052595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.2536052595
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.282276014
Short name T398
Test name
Test status
Simulation time 155581026 ps
CPU time 3.02 seconds
Started Mar 14 12:57:25 PM PDT 24
Finished Mar 14 12:57:28 PM PDT 24
Peak memory 222760 kb
Host smart-4772cb72-9ac1-4346-acd8-bfa9aec07d07
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=282276014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.282276014
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.2851947138
Short name T755
Test name
Test status
Simulation time 94654744 ps
CPU time 3.14 seconds
Started Mar 14 12:57:27 PM PDT 24
Finished Mar 14 12:57:30 PM PDT 24
Peak memory 209184 kb
Host smart-a7884416-8cef-469e-bd95-c968b3b14664
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851947138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.2851947138
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.4000920366
Short name T514
Test name
Test status
Simulation time 79237338 ps
CPU time 3.63 seconds
Started Mar 14 12:57:28 PM PDT 24
Finished Mar 14 12:57:32 PM PDT 24
Peak memory 218736 kb
Host smart-ee9b02cf-5dc3-4c14-ad33-712d1f14a5db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000920366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.4000920366
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.374381993
Short name T20
Test name
Test status
Simulation time 107104490 ps
CPU time 2.49 seconds
Started Mar 14 12:57:26 PM PDT 24
Finished Mar 14 12:57:29 PM PDT 24
Peak memory 208912 kb
Host smart-d12fc700-7729-40d9-be0b-d933ae5a2d50
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374381993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.374381993
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.4047554745
Short name T261
Test name
Test status
Simulation time 490549141 ps
CPU time 6.48 seconds
Started Mar 14 12:57:27 PM PDT 24
Finished Mar 14 12:57:34 PM PDT 24
Peak memory 214516 kb
Host smart-8d0845a4-2026-4ddc-94d2-847ef9f336ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047554745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.4047554745
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.2176842968
Short name T748
Test name
Test status
Simulation time 82340398 ps
CPU time 4.06 seconds
Started Mar 14 12:57:28 PM PDT 24
Finished Mar 14 12:57:33 PM PDT 24
Peak memory 209876 kb
Host smart-affa8d14-e612-4aec-9077-207719dcdb18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2176842968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.2176842968
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.2407747370
Short name T690
Test name
Test status
Simulation time 387074316 ps
CPU time 4.35 seconds
Started Mar 14 12:57:27 PM PDT 24
Finished Mar 14 12:57:32 PM PDT 24
Peak memory 210624 kb
Host smart-5613beb6-7427-4b38-8e72-369e9c514f39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407747370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.2407747370
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.1448997596
Short name T13
Test name
Test status
Simulation time 70698060 ps
CPU time 2.97 seconds
Started Mar 14 12:57:24 PM PDT 24
Finished Mar 14 12:57:27 PM PDT 24
Peak memory 208244 kb
Host smart-6de93eab-cf22-4657-b0ca-3358cea32f92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448997596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.1448997596
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.1140736414
Short name T438
Test name
Test status
Simulation time 177109388 ps
CPU time 3.54 seconds
Started Mar 14 12:57:27 PM PDT 24
Finished Mar 14 12:57:30 PM PDT 24
Peak memory 207160 kb
Host smart-9b71c091-e04d-41b0-bfa3-1c664a8c4308
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1140736414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.1140736414
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.319716570
Short name T486
Test name
Test status
Simulation time 154170845 ps
CPU time 3.22 seconds
Started Mar 14 12:57:21 PM PDT 24
Finished Mar 14 12:57:24 PM PDT 24
Peak memory 209040 kb
Host smart-c8416101-cee9-490f-9ca9-f1ae31e1e7f1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=319716570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.319716570
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.2720076020
Short name T424
Test name
Test status
Simulation time 3117227135 ps
CPU time 22.94 seconds
Started Mar 14 12:57:26 PM PDT 24
Finished Mar 14 12:57:49 PM PDT 24
Peak memory 209140 kb
Host smart-1e106627-8b6c-496c-91ce-b385f0fac8f3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2720076020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.2720076020
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.2651123007
Short name T82
Test name
Test status
Simulation time 324428572 ps
CPU time 4.15 seconds
Started Mar 14 12:57:25 PM PDT 24
Finished Mar 14 12:57:30 PM PDT 24
Peak memory 214644 kb
Host smart-ec2f6b15-a84c-404b-bfcd-dce94e0edf5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651123007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.2651123007
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.1137740784
Short name T757
Test name
Test status
Simulation time 71812063 ps
CPU time 2.99 seconds
Started Mar 14 12:57:17 PM PDT 24
Finished Mar 14 12:57:20 PM PDT 24
Peak memory 208740 kb
Host smart-9acff42d-b443-4411-808f-8ea5da8ca9cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1137740784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.1137740784
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.2346040441
Short name T75
Test name
Test status
Simulation time 1455708487 ps
CPU time 29.5 seconds
Started Mar 14 12:57:26 PM PDT 24
Finished Mar 14 12:57:56 PM PDT 24
Peak memory 217612 kb
Host smart-bc41dd97-b48c-4c9d-8ac7-335d5ef7f0e2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2346040441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.2346040441
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.4021433355
Short name T549
Test name
Test status
Simulation time 574519649 ps
CPU time 8.09 seconds
Started Mar 14 12:57:25 PM PDT 24
Finished Mar 14 12:57:33 PM PDT 24
Peak memory 208416 kb
Host smart-9763bde3-b4be-4d59-9cbf-b833fab87b6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021433355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.4021433355
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.1175800434
Short name T442
Test name
Test status
Simulation time 294564494 ps
CPU time 3.04 seconds
Started Mar 14 12:57:26 PM PDT 24
Finished Mar 14 12:57:30 PM PDT 24
Peak memory 210216 kb
Host smart-aa086672-8e58-4366-ac8c-811288de2068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1175800434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.1175800434
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.1295318992
Short name T487
Test name
Test status
Simulation time 49351535 ps
CPU time 0.79 seconds
Started Mar 14 12:57:38 PM PDT 24
Finished Mar 14 12:57:40 PM PDT 24
Peak memory 206204 kb
Host smart-086e357e-f990-48e9-bf35-974ab33fe6a3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1295318992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.1295318992
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.343755063
Short name T692
Test name
Test status
Simulation time 615957483 ps
CPU time 18.05 seconds
Started Mar 14 12:57:40 PM PDT 24
Finished Mar 14 12:57:58 PM PDT 24
Peak memory 222692 kb
Host smart-77f97599-afed-4115-92cf-51b4113e600a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343755063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.343755063
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.1987609560
Short name T245
Test name
Test status
Simulation time 40578808 ps
CPU time 1.84 seconds
Started Mar 14 12:57:35 PM PDT 24
Finished Mar 14 12:57:38 PM PDT 24
Peak memory 218672 kb
Host smart-b2736faf-22f8-4337-9e7c-31649e6f7896
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1987609560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.1987609560
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.2106207416
Short name T21
Test name
Test status
Simulation time 295296286 ps
CPU time 3.7 seconds
Started Mar 14 12:57:36 PM PDT 24
Finished Mar 14 12:57:40 PM PDT 24
Peak memory 215260 kb
Host smart-0558973e-90f4-4883-960b-b5caf94c3654
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106207416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.2106207416
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.88472366
Short name T315
Test name
Test status
Simulation time 592495904 ps
CPU time 5.67 seconds
Started Mar 14 12:57:40 PM PDT 24
Finished Mar 14 12:57:46 PM PDT 24
Peak memory 211056 kb
Host smart-27f00ccc-eca2-4567-b5e4-966e35aa1b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88472366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.88472366
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.1392884105
Short name T682
Test name
Test status
Simulation time 66502018 ps
CPU time 4.19 seconds
Started Mar 14 12:57:37 PM PDT 24
Finished Mar 14 12:57:41 PM PDT 24
Peak memory 210120 kb
Host smart-895746db-b19b-41f3-9801-df1ffb1ca161
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392884105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.1392884105
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.1891068337
Short name T185
Test name
Test status
Simulation time 190566843 ps
CPU time 3.01 seconds
Started Mar 14 12:57:40 PM PDT 24
Finished Mar 14 12:57:43 PM PDT 24
Peak memory 209916 kb
Host smart-70bc12aa-d226-4597-b1ca-da2a0501e494
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891068337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.1891068337
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.1297833395
Short name T346
Test name
Test status
Simulation time 147648009 ps
CPU time 5.2 seconds
Started Mar 14 12:57:25 PM PDT 24
Finished Mar 14 12:57:30 PM PDT 24
Peak memory 208840 kb
Host smart-abab6319-e9f8-410c-88f8-4a4e0d58e916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297833395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.1297833395
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.310702809
Short name T207
Test name
Test status
Simulation time 34093108 ps
CPU time 2.42 seconds
Started Mar 14 12:57:24 PM PDT 24
Finished Mar 14 12:57:27 PM PDT 24
Peak memory 207072 kb
Host smart-25c5ce70-af5c-43f8-ab37-3f6bd718a220
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=310702809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.310702809
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.2928801727
Short name T759
Test name
Test status
Simulation time 158380841 ps
CPU time 3 seconds
Started Mar 14 12:57:26 PM PDT 24
Finished Mar 14 12:57:29 PM PDT 24
Peak memory 209100 kb
Host smart-28f10cf4-ea7b-48f3-b9ab-7d319b5be1b7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928801727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.2928801727
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.711640909
Short name T209
Test name
Test status
Simulation time 41330034 ps
CPU time 2.48 seconds
Started Mar 14 12:57:26 PM PDT 24
Finished Mar 14 12:57:29 PM PDT 24
Peak memory 209040 kb
Host smart-30862f4e-4140-459e-9f3f-5576ebfd96aa
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=711640909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.711640909
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.305411572
Short name T348
Test name
Test status
Simulation time 212891263 ps
CPU time 2.88 seconds
Started Mar 14 12:57:38 PM PDT 24
Finished Mar 14 12:57:41 PM PDT 24
Peak memory 209944 kb
Host smart-44f845fa-71ab-41dd-9e6e-c456bb64890d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=305411572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.305411572
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.1216989630
Short name T840
Test name
Test status
Simulation time 6947224133 ps
CPU time 70.77 seconds
Started Mar 14 12:57:28 PM PDT 24
Finished Mar 14 12:58:39 PM PDT 24
Peak memory 208376 kb
Host smart-8f616929-e4c0-43fb-b13c-353dbd7b7b31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216989630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.1216989630
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.2612095705
Short name T788
Test name
Test status
Simulation time 968671530 ps
CPU time 25.99 seconds
Started Mar 14 12:57:39 PM PDT 24
Finished Mar 14 12:58:05 PM PDT 24
Peak memory 217464 kb
Host smart-7c866004-c87d-4758-a29c-e6ba82fefdc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612095705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.2612095705
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_stress_all_with_rand_reset.400316977
Short name T121
Test name
Test status
Simulation time 161090024 ps
CPU time 11.12 seconds
Started Mar 14 12:57:41 PM PDT 24
Finished Mar 14 12:57:52 PM PDT 24
Peak memory 222880 kb
Host smart-f1af80ec-0add-4993-a108-f164456d5759
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=400316977 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all_with_rand_reset.400316977
Directory /workspace/21.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.366073325
Short name T282
Test name
Test status
Simulation time 878113227 ps
CPU time 12.37 seconds
Started Mar 14 12:57:35 PM PDT 24
Finished Mar 14 12:57:47 PM PDT 24
Peak memory 214708 kb
Host smart-f208cc3f-6968-4c9a-bfa4-aa443da66a49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366073325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.366073325
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.335894202
Short name T884
Test name
Test status
Simulation time 195655531 ps
CPU time 1.86 seconds
Started Mar 14 12:57:36 PM PDT 24
Finished Mar 14 12:57:38 PM PDT 24
Peak memory 210460 kb
Host smart-d85c166e-da13-419f-9e2d-97de8092d37f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=335894202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.335894202
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.1989165452
Short name T876
Test name
Test status
Simulation time 45242749 ps
CPU time 0.9 seconds
Started Mar 14 12:57:38 PM PDT 24
Finished Mar 14 12:57:40 PM PDT 24
Peak memory 206224 kb
Host smart-65f3ac0f-9af0-486a-9b8f-748579a6a44a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989165452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.1989165452
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.2384129909
Short name T386
Test name
Test status
Simulation time 81478550 ps
CPU time 3.75 seconds
Started Mar 14 12:57:37 PM PDT 24
Finished Mar 14 12:57:41 PM PDT 24
Peak memory 215448 kb
Host smart-5459bfcc-084b-4a67-b24f-f9242f137587
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2384129909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.2384129909
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.143745865
Short name T636
Test name
Test status
Simulation time 59413372 ps
CPU time 2.96 seconds
Started Mar 14 12:57:37 PM PDT 24
Finished Mar 14 12:57:40 PM PDT 24
Peak memory 210656 kb
Host smart-73aaea23-8d60-4c7b-945e-11f05d033583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143745865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.143745865
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.262422461
Short name T508
Test name
Test status
Simulation time 484436819 ps
CPU time 5.77 seconds
Started Mar 14 12:57:38 PM PDT 24
Finished Mar 14 12:57:44 PM PDT 24
Peak memory 209320 kb
Host smart-c13f55df-2320-4739-86f9-0a68ec03ee6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262422461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.262422461
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.1981853727
Short name T717
Test name
Test status
Simulation time 106959665 ps
CPU time 5.11 seconds
Started Mar 14 12:57:40 PM PDT 24
Finished Mar 14 12:57:45 PM PDT 24
Peak memory 214636 kb
Host smart-a6c32d77-674e-4fb3-95c8-86d67cc20949
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981853727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.1981853727
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.1013823382
Short name T526
Test name
Test status
Simulation time 111267187 ps
CPU time 3.5 seconds
Started Mar 14 12:57:38 PM PDT 24
Finished Mar 14 12:57:42 PM PDT 24
Peak memory 216016 kb
Host smart-3e2e2906-a75d-494e-9e80-4109414c4f6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013823382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.1013823382
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_sideload.756560775
Short name T341
Test name
Test status
Simulation time 816734459 ps
CPU time 6.13 seconds
Started Mar 14 12:57:36 PM PDT 24
Finished Mar 14 12:57:43 PM PDT 24
Peak memory 208776 kb
Host smart-0220c400-d3b9-4e09-83d3-340cb67f6183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756560775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.756560775
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.1508854682
Short name T276
Test name
Test status
Simulation time 1641028574 ps
CPU time 6.95 seconds
Started Mar 14 12:57:37 PM PDT 24
Finished Mar 14 12:57:44 PM PDT 24
Peak memory 208676 kb
Host smart-e3d63b10-6311-45eb-8fa7-a6b04625491e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508854682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.1508854682
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.423979758
Short name T434
Test name
Test status
Simulation time 60942181 ps
CPU time 2.92 seconds
Started Mar 14 12:57:37 PM PDT 24
Finished Mar 14 12:57:40 PM PDT 24
Peak memory 207100 kb
Host smart-72ab3ec4-edf8-4e7f-a6ba-1450e94149cc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=423979758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.423979758
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.3695548222
Short name T611
Test name
Test status
Simulation time 193028559 ps
CPU time 2.95 seconds
Started Mar 14 12:57:38 PM PDT 24
Finished Mar 14 12:57:42 PM PDT 24
Peak memory 206976 kb
Host smart-1a3a8be5-8aec-4707-9efc-37b1900f7acf
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3695548222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.3695548222
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.3881553722
Short name T197
Test name
Test status
Simulation time 177905580 ps
CPU time 5.55 seconds
Started Mar 14 12:57:40 PM PDT 24
Finished Mar 14 12:57:46 PM PDT 24
Peak memory 208344 kb
Host smart-80341df7-7573-4ecc-96f4-8ad1c46b1737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3881553722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.3881553722
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.2668608084
Short name T799
Test name
Test status
Simulation time 20693596 ps
CPU time 1.78 seconds
Started Mar 14 12:57:37 PM PDT 24
Finished Mar 14 12:57:39 PM PDT 24
Peak memory 206952 kb
Host smart-d05368e4-e11d-42b3-9b72-407723bc5551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668608084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.2668608084
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.2918979112
Short name T335
Test name
Test status
Simulation time 1628370566 ps
CPU time 34.16 seconds
Started Mar 14 12:57:38 PM PDT 24
Finished Mar 14 12:58:12 PM PDT 24
Peak memory 215748 kb
Host smart-70ebba60-c38b-402c-b333-32c3d86d34fe
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2918979112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.2918979112
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.3589549474
Short name T678
Test name
Test status
Simulation time 8707046406 ps
CPU time 49.86 seconds
Started Mar 14 12:57:36 PM PDT 24
Finished Mar 14 12:58:26 PM PDT 24
Peak memory 209336 kb
Host smart-46891072-0348-40c3-93f9-cc1c85d7f405
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3589549474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.3589549474
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.4219985565
Short name T710
Test name
Test status
Simulation time 89631910 ps
CPU time 2.8 seconds
Started Mar 14 12:57:38 PM PDT 24
Finished Mar 14 12:57:42 PM PDT 24
Peak memory 209800 kb
Host smart-e1b924d8-ceb4-426e-bd44-10f6410412b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4219985565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.4219985565
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.823078965
Short name T534
Test name
Test status
Simulation time 16881244 ps
CPU time 0.98 seconds
Started Mar 14 12:57:37 PM PDT 24
Finished Mar 14 12:57:38 PM PDT 24
Peak memory 206456 kb
Host smart-3434a878-d355-49b5-a3eb-b8c06484b780
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823078965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.823078965
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.1122243371
Short name T184
Test name
Test status
Simulation time 128499901 ps
CPU time 3.36 seconds
Started Mar 14 12:57:38 PM PDT 24
Finished Mar 14 12:57:42 PM PDT 24
Peak memory 210068 kb
Host smart-630c08d5-1ecd-45a3-b4cc-eed4cd374c17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1122243371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.1122243371
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.1876148676
Short name T709
Test name
Test status
Simulation time 66462815 ps
CPU time 3.64 seconds
Started Mar 14 12:57:37 PM PDT 24
Finished Mar 14 12:57:41 PM PDT 24
Peak memory 214620 kb
Host smart-58aea446-6a63-4287-ab64-3fd75c1de7f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876148676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.1876148676
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.1117513115
Short name T344
Test name
Test status
Simulation time 69274923 ps
CPU time 4.44 seconds
Started Mar 14 12:57:38 PM PDT 24
Finished Mar 14 12:57:43 PM PDT 24
Peak memory 222736 kb
Host smart-6eda0255-428e-45e3-aaa6-f3551b665256
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117513115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.1117513115
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.112040853
Short name T43
Test name
Test status
Simulation time 113109082 ps
CPU time 2.88 seconds
Started Mar 14 12:57:37 PM PDT 24
Finished Mar 14 12:57:40 PM PDT 24
Peak memory 206468 kb
Host smart-cd2ef164-18f1-45ea-bf52-b98fe9ed99bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112040853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.112040853
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.2681369860
Short name T435
Test name
Test status
Simulation time 700645201 ps
CPU time 6.35 seconds
Started Mar 14 12:57:39 PM PDT 24
Finished Mar 14 12:57:46 PM PDT 24
Peak memory 214588 kb
Host smart-291adfac-f853-4ad0-b7e7-959c6b06ba20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681369860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.2681369860
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.1223991650
Short name T358
Test name
Test status
Simulation time 160041603 ps
CPU time 5.74 seconds
Started Mar 14 12:57:40 PM PDT 24
Finished Mar 14 12:57:46 PM PDT 24
Peak memory 208260 kb
Host smart-9241ed60-67c8-472b-893a-4e71044ba50b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1223991650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.1223991650
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.1292501957
Short name T453
Test name
Test status
Simulation time 60901616 ps
CPU time 3.16 seconds
Started Mar 14 12:57:39 PM PDT 24
Finished Mar 14 12:57:42 PM PDT 24
Peak memory 209020 kb
Host smart-01892057-9c0f-4b34-8cda-cc635ef717ef
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1292501957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.1292501957
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.2885812507
Short name T316
Test name
Test status
Simulation time 288991967 ps
CPU time 7.66 seconds
Started Mar 14 12:57:37 PM PDT 24
Finished Mar 14 12:57:45 PM PDT 24
Peak memory 209092 kb
Host smart-2227488d-952f-47a5-81a3-e415653c5429
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885812507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.2885812507
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.3110420005
Short name T283
Test name
Test status
Simulation time 88459541 ps
CPU time 1.88 seconds
Started Mar 14 12:57:38 PM PDT 24
Finished Mar 14 12:57:40 PM PDT 24
Peak memory 206928 kb
Host smart-3710aea1-5e28-48ef-acd8-0649ea404e53
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3110420005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.3110420005
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.3860592727
Short name T445
Test name
Test status
Simulation time 119722309 ps
CPU time 2.25 seconds
Started Mar 14 12:57:37 PM PDT 24
Finished Mar 14 12:57:39 PM PDT 24
Peak memory 208284 kb
Host smart-efaed6db-f467-4815-adc4-c75c11b64eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3860592727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.3860592727
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.3381326056
Short name T12
Test name
Test status
Simulation time 891548377 ps
CPU time 8.27 seconds
Started Mar 14 12:57:38 PM PDT 24
Finished Mar 14 12:57:46 PM PDT 24
Peak memory 207908 kb
Host smart-6738f475-ded3-4481-a821-06327180a89b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381326056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.3381326056
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all_with_rand_reset.3728545879
Short name T624
Test name
Test status
Simulation time 579251941 ps
CPU time 6.73 seconds
Started Mar 14 12:57:38 PM PDT 24
Finished Mar 14 12:57:46 PM PDT 24
Peak memory 222908 kb
Host smart-ea668c7b-d794-429c-8915-580dc11af4b1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728545879 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all_with_rand_reset.3728545879
Directory /workspace/23.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.1537345416
Short name T700
Test name
Test status
Simulation time 406647740 ps
CPU time 4.74 seconds
Started Mar 14 12:57:38 PM PDT 24
Finished Mar 14 12:57:44 PM PDT 24
Peak memory 218856 kb
Host smart-802bf877-572a-46c6-a6ab-38d458e849eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537345416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.1537345416
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.2441924985
Short name T736
Test name
Test status
Simulation time 111385089 ps
CPU time 1.6 seconds
Started Mar 14 12:57:37 PM PDT 24
Finished Mar 14 12:57:39 PM PDT 24
Peak memory 209920 kb
Host smart-352c04b6-b928-4f08-861d-0b2b0426bf29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441924985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.2441924985
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.3232359829
Short name T879
Test name
Test status
Simulation time 63787979 ps
CPU time 0.8 seconds
Started Mar 14 12:57:51 PM PDT 24
Finished Mar 14 12:57:52 PM PDT 24
Peak memory 206296 kb
Host smart-f8313c3f-f2a9-4279-ac4d-fb9bcd013d95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3232359829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.3232359829
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.3052909095
Short name T239
Test name
Test status
Simulation time 61434290 ps
CPU time 4.11 seconds
Started Mar 14 12:57:51 PM PDT 24
Finished Mar 14 12:57:55 PM PDT 24
Peak memory 214564 kb
Host smart-8b3ea5a4-17c0-4cff-89fc-92a2452bf7f7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3052909095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.3052909095
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.4160424552
Short name T293
Test name
Test status
Simulation time 554835246 ps
CPU time 8.83 seconds
Started Mar 14 12:57:55 PM PDT 24
Finished Mar 14 12:58:04 PM PDT 24
Peak memory 210204 kb
Host smart-12e39221-2573-4d78-bd32-4dc1fd023fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160424552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.4160424552
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.833604413
Short name T349
Test name
Test status
Simulation time 952510599 ps
CPU time 4.37 seconds
Started Mar 14 12:57:52 PM PDT 24
Finished Mar 14 12:57:57 PM PDT 24
Peak memory 208628 kb
Host smart-c2e32432-ae43-4e19-ad92-e981d35f0307
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833604413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.833604413
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.795592824
Short name T216
Test name
Test status
Simulation time 263132134 ps
CPU time 2.45 seconds
Started Mar 14 12:57:51 PM PDT 24
Finished Mar 14 12:57:53 PM PDT 24
Peak memory 220956 kb
Host smart-3b418ed1-b0be-4c0d-926f-3ebcf4b1e515
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=795592824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.795592824
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.2518837897
Short name T268
Test name
Test status
Simulation time 1532023346 ps
CPU time 7.31 seconds
Started Mar 14 12:57:51 PM PDT 24
Finished Mar 14 12:57:59 PM PDT 24
Peak memory 208160 kb
Host smart-58a09602-eee4-4424-842e-1f37d2c930ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2518837897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.2518837897
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.207085464
Short name T499
Test name
Test status
Simulation time 712690961 ps
CPU time 5.8 seconds
Started Mar 14 12:57:51 PM PDT 24
Finished Mar 14 12:57:57 PM PDT 24
Peak memory 208668 kb
Host smart-70882f39-3001-40c4-8621-5a90674f1d8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=207085464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.207085464
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.3042398974
Short name T580
Test name
Test status
Simulation time 95258494 ps
CPU time 3 seconds
Started Mar 14 12:57:51 PM PDT 24
Finished Mar 14 12:57:55 PM PDT 24
Peak memory 207140 kb
Host smart-c18be6ab-2004-40df-be96-f6caded19d9d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3042398974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.3042398974
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.1519158188
Short name T877
Test name
Test status
Simulation time 384233053 ps
CPU time 11.3 seconds
Started Mar 14 12:57:56 PM PDT 24
Finished Mar 14 12:58:07 PM PDT 24
Peak memory 209424 kb
Host smart-32f53e00-00e2-41e3-92f8-19e152c484ba
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519158188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.1519158188
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.1487826174
Short name T432
Test name
Test status
Simulation time 161829374 ps
CPU time 4.9 seconds
Started Mar 14 12:57:52 PM PDT 24
Finished Mar 14 12:57:57 PM PDT 24
Peak memory 207124 kb
Host smart-a72d2306-ba03-4eed-b1c9-73753e24a0a8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1487826174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.1487826174
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.2560053482
Short name T803
Test name
Test status
Simulation time 753964885 ps
CPU time 4.59 seconds
Started Mar 14 12:57:51 PM PDT 24
Finished Mar 14 12:57:55 PM PDT 24
Peak memory 210328 kb
Host smart-042d9777-661a-4102-acd6-657d1db2a393
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560053482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.2560053482
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.1448888007
Short name T733
Test name
Test status
Simulation time 146893114 ps
CPU time 5.21 seconds
Started Mar 14 12:57:38 PM PDT 24
Finished Mar 14 12:57:43 PM PDT 24
Peak memory 208040 kb
Host smart-4a79f865-004d-4027-a58f-f57f8571618d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1448888007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.1448888007
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.3085598777
Short name T791
Test name
Test status
Simulation time 1651275887 ps
CPU time 16.91 seconds
Started Mar 14 12:57:51 PM PDT 24
Finished Mar 14 12:58:08 PM PDT 24
Peak memory 219484 kb
Host smart-49f9b654-837c-45dc-98f3-e1a5e4f30e13
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3085598777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.3085598777
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_stress_all_with_rand_reset.16216124
Short name T274
Test name
Test status
Simulation time 2289695534 ps
CPU time 22.31 seconds
Started Mar 14 12:57:48 PM PDT 24
Finished Mar 14 12:58:10 PM PDT 24
Peak memory 222876 kb
Host smart-fc5b929e-e05b-46cd-80ce-4387caa654ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16216124 -assert nopostp
roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all_with_rand_reset.16216124
Directory /workspace/24.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.3214934496
Short name T764
Test name
Test status
Simulation time 1206552003 ps
CPU time 8.18 seconds
Started Mar 14 12:57:54 PM PDT 24
Finished Mar 14 12:58:03 PM PDT 24
Peak memory 209308 kb
Host smart-2093beea-3823-494a-ad3c-0e62c49c4372
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214934496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.3214934496
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.709392917
Short name T467
Test name
Test status
Simulation time 32027381 ps
CPU time 2.12 seconds
Started Mar 14 12:57:49 PM PDT 24
Finished Mar 14 12:57:52 PM PDT 24
Peak memory 209904 kb
Host smart-bac6bd4d-e61f-4c31-941b-99e592821962
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=709392917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.709392917
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.281069510
Short name T478
Test name
Test status
Simulation time 122859985 ps
CPU time 0.86 seconds
Started Mar 14 12:57:51 PM PDT 24
Finished Mar 14 12:57:52 PM PDT 24
Peak memory 206188 kb
Host smart-ad22a4eb-54c3-4c41-89f7-e5365603bc13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=281069510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.281069510
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.195337902
Short name T322
Test name
Test status
Simulation time 236385799 ps
CPU time 4.53 seconds
Started Mar 14 12:57:55 PM PDT 24
Finished Mar 14 12:57:59 PM PDT 24
Peak memory 216008 kb
Host smart-69a265d5-1cc2-4afb-898e-02a8707310f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=195337902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.195337902
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.3150568375
Short name T741
Test name
Test status
Simulation time 28031963 ps
CPU time 2.02 seconds
Started Mar 14 12:57:50 PM PDT 24
Finished Mar 14 12:57:52 PM PDT 24
Peak memory 214592 kb
Host smart-ffc90195-0d42-43ed-82c3-b6bd9f03fd1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150568375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.3150568375
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.1623252418
Short name T831
Test name
Test status
Simulation time 2582108895 ps
CPU time 21 seconds
Started Mar 14 12:57:55 PM PDT 24
Finished Mar 14 12:58:16 PM PDT 24
Peak memory 211388 kb
Host smart-ab33dfed-050d-44c3-a7a0-d118b5693199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623252418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.1623252418
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.2904989516
Short name T271
Test name
Test status
Simulation time 87196909 ps
CPU time 4.26 seconds
Started Mar 14 12:57:50 PM PDT 24
Finished Mar 14 12:57:55 PM PDT 24
Peak memory 209648 kb
Host smart-bb850757-6654-46a3-adcd-d791f561aeb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904989516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.2904989516
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.3720997851
Short name T563
Test name
Test status
Simulation time 311824049 ps
CPU time 5.94 seconds
Started Mar 14 12:57:49 PM PDT 24
Finished Mar 14 12:57:55 PM PDT 24
Peak memory 209336 kb
Host smart-595b2e8a-7875-4139-8ed6-be5c741dea8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720997851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.3720997851
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.971743752
Short name T737
Test name
Test status
Simulation time 346091870 ps
CPU time 9.03 seconds
Started Mar 14 12:57:49 PM PDT 24
Finished Mar 14 12:57:59 PM PDT 24
Peak memory 208040 kb
Host smart-477e7458-d4ab-4122-a1f4-8798f03c6c31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971743752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.971743752
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.3980732610
Short name T792
Test name
Test status
Simulation time 98821387 ps
CPU time 4.08 seconds
Started Mar 14 12:57:49 PM PDT 24
Finished Mar 14 12:57:53 PM PDT 24
Peak memory 209032 kb
Host smart-a11e1ef1-f2c0-4b14-9728-5bb5b926b3d2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3980732610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.3980732610
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.42122313
Short name T891
Test name
Test status
Simulation time 1336539992 ps
CPU time 18.36 seconds
Started Mar 14 12:57:49 PM PDT 24
Finished Mar 14 12:58:08 PM PDT 24
Peak memory 208872 kb
Host smart-f142ea21-e1b3-4460-b5a3-f7fca500bf34
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42122313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.42122313
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.1371203591
Short name T887
Test name
Test status
Simulation time 757154265 ps
CPU time 5.6 seconds
Started Mar 14 12:57:51 PM PDT 24
Finished Mar 14 12:57:56 PM PDT 24
Peak memory 208300 kb
Host smart-f057942a-e925-4a53-8db2-b1302afbc3ea
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1371203591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.1371203591
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.201678536
Short name T609
Test name
Test status
Simulation time 55471745 ps
CPU time 2.76 seconds
Started Mar 14 12:57:57 PM PDT 24
Finished Mar 14 12:58:00 PM PDT 24
Peak memory 208628 kb
Host smart-1237de88-f63d-4286-b795-ef60112f7782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201678536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.201678536
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.1968244879
Short name T874
Test name
Test status
Simulation time 80197881 ps
CPU time 2.66 seconds
Started Mar 14 12:57:53 PM PDT 24
Finished Mar 14 12:57:57 PM PDT 24
Peak memory 208696 kb
Host smart-11daf52c-2e88-4c66-b0b9-b6d04cbfb631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1968244879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.1968244879
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.2512287502
Short name T691
Test name
Test status
Simulation time 10183684802 ps
CPU time 65.81 seconds
Started Mar 14 12:57:50 PM PDT 24
Finished Mar 14 12:58:56 PM PDT 24
Peak memory 222896 kb
Host smart-0bab9343-12f5-4047-a624-9d50c2febedd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2512287502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.2512287502
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.1962468092
Short name T515
Test name
Test status
Simulation time 9666895925 ps
CPU time 48.81 seconds
Started Mar 14 12:57:50 PM PDT 24
Finished Mar 14 12:58:39 PM PDT 24
Peak memory 208640 kb
Host smart-f3c1c00f-a288-4ecd-ae32-aeb2d5439fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962468092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.1962468092
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.202673733
Short name T623
Test name
Test status
Simulation time 366946624 ps
CPU time 2.88 seconds
Started Mar 14 12:57:51 PM PDT 24
Finished Mar 14 12:57:55 PM PDT 24
Peak memory 210524 kb
Host smart-41d53106-d374-4486-bf29-b9bf577b25b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202673733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.202673733
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.120369371
Short name T189
Test name
Test status
Simulation time 14411729 ps
CPU time 0.75 seconds
Started Mar 14 12:57:57 PM PDT 24
Finished Mar 14 12:57:58 PM PDT 24
Peak memory 206356 kb
Host smart-fda9b840-4f4e-4218-9150-7a8a7453b650
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120369371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.120369371
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.1569558818
Short name T371
Test name
Test status
Simulation time 53751239 ps
CPU time 3.64 seconds
Started Mar 14 12:57:51 PM PDT 24
Finished Mar 14 12:57:55 PM PDT 24
Peak memory 214440 kb
Host smart-7a253bc4-769b-4598-abfe-120eaea0f911
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1569558818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.1569558818
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.3898262267
Short name T770
Test name
Test status
Simulation time 149388571 ps
CPU time 3.83 seconds
Started Mar 14 12:57:51 PM PDT 24
Finished Mar 14 12:57:55 PM PDT 24
Peak memory 210628 kb
Host smart-48e125f5-70c0-4b32-8e32-68ae3aa2baea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898262267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.3898262267
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.290939954
Short name T885
Test name
Test status
Simulation time 322369476 ps
CPU time 7.2 seconds
Started Mar 14 12:57:56 PM PDT 24
Finished Mar 14 12:58:03 PM PDT 24
Peak memory 209496 kb
Host smart-4f9509a9-4ea1-43de-bf60-3ad6594b8598
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290939954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.290939954
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.2574318060
Short name T243
Test name
Test status
Simulation time 76759191 ps
CPU time 4.11 seconds
Started Mar 14 12:57:52 PM PDT 24
Finished Mar 14 12:57:57 PM PDT 24
Peak memory 211064 kb
Host smart-12bf2ef3-0787-4f54-a292-a08f06daa3f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574318060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.2574318060
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.2310902212
Short name T861
Test name
Test status
Simulation time 479048030 ps
CPU time 4.24 seconds
Started Mar 14 12:57:49 PM PDT 24
Finished Mar 14 12:57:54 PM PDT 24
Peak memory 222804 kb
Host smart-b2740f62-d4b7-463c-a2d0-5758d12e9970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2310902212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.2310902212
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.1948020564
Short name T285
Test name
Test status
Simulation time 224157456 ps
CPU time 5.17 seconds
Started Mar 14 12:57:52 PM PDT 24
Finished Mar 14 12:57:58 PM PDT 24
Peak memory 210400 kb
Host smart-67130d0a-19c8-42aa-9c4b-d2a8bc50500f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948020564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.1948020564
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.245836446
Short name T550
Test name
Test status
Simulation time 307877090 ps
CPU time 2.27 seconds
Started Mar 14 12:57:51 PM PDT 24
Finished Mar 14 12:57:54 PM PDT 24
Peak memory 206960 kb
Host smart-863616ac-26c0-4169-a9a5-d444db10578e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245836446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.245836446
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.2805124601
Short name T856
Test name
Test status
Simulation time 148587183 ps
CPU time 5.87 seconds
Started Mar 14 12:57:51 PM PDT 24
Finished Mar 14 12:57:57 PM PDT 24
Peak memory 208648 kb
Host smart-9f640853-46c2-4e58-af85-8a62170efde5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2805124601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.2805124601
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.1725896452
Short name T702
Test name
Test status
Simulation time 134506781 ps
CPU time 4.27 seconds
Started Mar 14 12:57:49 PM PDT 24
Finished Mar 14 12:57:54 PM PDT 24
Peak memory 208828 kb
Host smart-c734035f-49f9-4da5-85bb-34af3971abdd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1725896452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.1725896452
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.1320218631
Short name T105
Test name
Test status
Simulation time 210302870 ps
CPU time 5.55 seconds
Started Mar 14 12:57:53 PM PDT 24
Finished Mar 14 12:57:59 PM PDT 24
Peak memory 208052 kb
Host smart-e18d2132-f241-44d4-981c-2496f36ac598
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1320218631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.1320218631
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.264613125
Short name T265
Test name
Test status
Simulation time 224294260 ps
CPU time 4.07 seconds
Started Mar 14 12:57:54 PM PDT 24
Finished Mar 14 12:57:59 PM PDT 24
Peak memory 214572 kb
Host smart-5714b825-2419-47f9-a53e-b679a9dca4fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=264613125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.264613125
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.1808135833
Short name T108
Test name
Test status
Simulation time 102214766 ps
CPU time 3.91 seconds
Started Mar 14 12:57:50 PM PDT 24
Finished Mar 14 12:57:54 PM PDT 24
Peak memory 208728 kb
Host smart-abf68743-156e-415e-b4e9-c11f0ead3c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808135833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.1808135833
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.1350562624
Short name T503
Test name
Test status
Simulation time 189876956 ps
CPU time 5.41 seconds
Started Mar 14 12:57:51 PM PDT 24
Finished Mar 14 12:57:57 PM PDT 24
Peak memory 222796 kb
Host smart-48821eb2-89aa-4230-9652-248e2e2b23c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350562624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.1350562624
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.1218751043
Short name T720
Test name
Test status
Simulation time 50881880 ps
CPU time 2.47 seconds
Started Mar 14 12:57:51 PM PDT 24
Finished Mar 14 12:57:54 PM PDT 24
Peak memory 209996 kb
Host smart-37ed554c-5cb6-44d7-a01c-3b35529efc6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218751043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.1218751043
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.2852855317
Short name T418
Test name
Test status
Simulation time 23843529 ps
CPU time 0.8 seconds
Started Mar 14 12:58:02 PM PDT 24
Finished Mar 14 12:58:04 PM PDT 24
Peak memory 206156 kb
Host smart-62158b67-7900-4718-8bd3-3d4adcf6d789
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2852855317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.2852855317
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.1905642945
Short name T141
Test name
Test status
Simulation time 92852487 ps
CPU time 3.65 seconds
Started Mar 14 12:58:02 PM PDT 24
Finished Mar 14 12:58:07 PM PDT 24
Peak memory 214644 kb
Host smart-1ffa03e3-bd39-4976-9c9d-e3d4c3157981
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1905642945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.1905642945
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.829315263
Short name T811
Test name
Test status
Simulation time 187518565 ps
CPU time 2.7 seconds
Started Mar 14 12:58:01 PM PDT 24
Finished Mar 14 12:58:04 PM PDT 24
Peak memory 209068 kb
Host smart-8ad1b899-df72-44ea-8235-ba71ebd9d81c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829315263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.829315263
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.2571774995
Short name T715
Test name
Test status
Simulation time 44682554 ps
CPU time 2.57 seconds
Started Mar 14 12:58:00 PM PDT 24
Finished Mar 14 12:58:03 PM PDT 24
Peak memory 214632 kb
Host smart-9d334f3a-1700-4a9e-9d38-4c8916132bf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571774995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.2571774995
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.616861602
Short name T587
Test name
Test status
Simulation time 71621542 ps
CPU time 3.53 seconds
Started Mar 14 12:58:02 PM PDT 24
Finished Mar 14 12:58:07 PM PDT 24
Peak memory 208892 kb
Host smart-f0fd3a47-83de-4855-a29e-e7bcfd183759
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616861602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.616861602
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.838683349
Short name T51
Test name
Test status
Simulation time 326647028 ps
CPU time 12.97 seconds
Started Mar 14 12:58:04 PM PDT 24
Finished Mar 14 12:58:19 PM PDT 24
Peak memory 214680 kb
Host smart-edd177d5-6c41-4ef6-917b-b5247c50e7b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=838683349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.838683349
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.1057598107
Short name T227
Test name
Test status
Simulation time 385697992 ps
CPU time 3.54 seconds
Started Mar 14 12:58:03 PM PDT 24
Finished Mar 14 12:58:09 PM PDT 24
Peak memory 219372 kb
Host smart-32116263-db18-4249-9547-619726345ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1057598107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.1057598107
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.3771676448
Short name T444
Test name
Test status
Simulation time 395102587 ps
CPU time 4.7 seconds
Started Mar 14 12:58:06 PM PDT 24
Finished Mar 14 12:58:13 PM PDT 24
Peak memory 209300 kb
Host smart-f96144ec-f412-43db-a8f4-50ab1aad6024
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771676448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.3771676448
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.3578969101
Short name T426
Test name
Test status
Simulation time 186884853 ps
CPU time 4.63 seconds
Started Mar 14 12:57:50 PM PDT 24
Finished Mar 14 12:57:55 PM PDT 24
Peak memory 208908 kb
Host smart-305a063b-b854-4f69-91dd-a986875f2e95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578969101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.3578969101
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.1421929368
Short name T257
Test name
Test status
Simulation time 261294038 ps
CPU time 4.39 seconds
Started Mar 14 12:58:01 PM PDT 24
Finished Mar 14 12:58:06 PM PDT 24
Peak memory 207468 kb
Host smart-19939740-2288-489e-ab63-51058dd46f06
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421929368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.1421929368
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.872211011
Short name T561
Test name
Test status
Simulation time 82605612 ps
CPU time 2.43 seconds
Started Mar 14 12:58:06 PM PDT 24
Finished Mar 14 12:58:11 PM PDT 24
Peak memory 207180 kb
Host smart-ea301b20-39ef-438c-ace4-629e7eaa6288
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872211011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.872211011
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.2446981127
Short name T903
Test name
Test status
Simulation time 419560664 ps
CPU time 7.79 seconds
Started Mar 14 12:58:01 PM PDT 24
Finished Mar 14 12:58:10 PM PDT 24
Peak memory 208900 kb
Host smart-9683a2f7-177e-4c03-95aa-95699f41b8b6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446981127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.2446981127
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.1089487045
Short name T604
Test name
Test status
Simulation time 81895666 ps
CPU time 3.7 seconds
Started Mar 14 12:58:02 PM PDT 24
Finished Mar 14 12:58:07 PM PDT 24
Peak memory 209988 kb
Host smart-176bb814-6ec2-489c-8e75-df393cc95770
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089487045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.1089487045
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.2374708815
Short name T597
Test name
Test status
Simulation time 1677200223 ps
CPU time 17.76 seconds
Started Mar 14 12:57:50 PM PDT 24
Finished Mar 14 12:58:08 PM PDT 24
Peak memory 208000 kb
Host smart-8da0e7b6-4cbc-4695-8171-810a5f396fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374708815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.2374708815
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.693403195
Short name T325
Test name
Test status
Simulation time 9196355602 ps
CPU time 93.2 seconds
Started Mar 14 12:58:07 PM PDT 24
Finished Mar 14 12:59:42 PM PDT 24
Peak memory 216456 kb
Host smart-d71a0d12-e639-4474-aa14-fe6e301d5198
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=693403195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.693403195
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.569809692
Short name T342
Test name
Test status
Simulation time 408359765 ps
CPU time 11.13 seconds
Started Mar 14 12:58:10 PM PDT 24
Finished Mar 14 12:58:22 PM PDT 24
Peak memory 218576 kb
Host smart-779e2e8d-46de-4034-800e-4901e1f5fd14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569809692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.569809692
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.302420336
Short name T78
Test name
Test status
Simulation time 327729298 ps
CPU time 2.56 seconds
Started Mar 14 12:58:03 PM PDT 24
Finished Mar 14 12:58:07 PM PDT 24
Peak memory 209932 kb
Host smart-67c4b049-2468-4c2f-8168-4667bcd08682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=302420336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.302420336
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.3931625890
Short name T637
Test name
Test status
Simulation time 56829425 ps
CPU time 0.74 seconds
Started Mar 14 12:58:06 PM PDT 24
Finished Mar 14 12:58:09 PM PDT 24
Peak memory 206272 kb
Host smart-72ab466d-a78c-4221-a70d-46a51d028048
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931625890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.3931625890
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.1924942355
Short name T231
Test name
Test status
Simulation time 3791517096 ps
CPU time 19.61 seconds
Started Mar 14 12:58:01 PM PDT 24
Finished Mar 14 12:58:21 PM PDT 24
Peak memory 223092 kb
Host smart-e70c70bc-0d80-47fd-a18a-ee39e41eb93c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1924942355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.1924942355
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.2260647597
Short name T58
Test name
Test status
Simulation time 95205028 ps
CPU time 3.16 seconds
Started Mar 14 12:58:05 PM PDT 24
Finished Mar 14 12:58:09 PM PDT 24
Peak memory 209964 kb
Host smart-37596282-e164-4274-8dc2-1c0feef035d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260647597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.2260647597
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.90657749
Short name T689
Test name
Test status
Simulation time 210194599 ps
CPU time 7.05 seconds
Started Mar 14 12:58:05 PM PDT 24
Finished Mar 14 12:58:13 PM PDT 24
Peak memory 222824 kb
Host smart-cb603f5a-966b-41d6-a2e1-8cf24f7e2584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90657749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.90657749
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_random.1814828767
Short name T203
Test name
Test status
Simulation time 112584593 ps
CPU time 4.91 seconds
Started Mar 14 12:58:10 PM PDT 24
Finished Mar 14 12:58:16 PM PDT 24
Peak memory 209752 kb
Host smart-bc1d3732-b4aa-40d9-8aeb-6b85d113f4a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814828767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.1814828767
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.3651298336
Short name T633
Test name
Test status
Simulation time 1036487648 ps
CPU time 4.79 seconds
Started Mar 14 12:57:59 PM PDT 24
Finished Mar 14 12:58:04 PM PDT 24
Peak memory 208712 kb
Host smart-d7371e91-c6b1-4207-af49-bd917ed065db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3651298336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.3651298336
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.95197258
Short name T714
Test name
Test status
Simulation time 9556672557 ps
CPU time 38.19 seconds
Started Mar 14 12:58:06 PM PDT 24
Finished Mar 14 12:58:46 PM PDT 24
Peak memory 208380 kb
Host smart-86482ee5-cd90-4449-bef8-aaba7b96551c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95197258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.95197258
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.263007599
Short name T753
Test name
Test status
Simulation time 410442868 ps
CPU time 10.84 seconds
Started Mar 14 12:58:06 PM PDT 24
Finished Mar 14 12:58:18 PM PDT 24
Peak memory 208148 kb
Host smart-a60572b7-25ae-4905-88de-f59cee18c1cd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263007599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.263007599
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.3988520867
Short name T644
Test name
Test status
Simulation time 1403498442 ps
CPU time 42.13 seconds
Started Mar 14 12:58:05 PM PDT 24
Finished Mar 14 12:58:48 PM PDT 24
Peak memory 208248 kb
Host smart-d745c998-357d-40db-bb70-dad169c837d1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3988520867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.3988520867
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.4044540430
Short name T437
Test name
Test status
Simulation time 40847260 ps
CPU time 2.22 seconds
Started Mar 14 12:58:04 PM PDT 24
Finished Mar 14 12:58:08 PM PDT 24
Peak memory 210100 kb
Host smart-29c4344d-a17d-4696-b349-9532c2bdf8e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044540430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.4044540430
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.599961861
Short name T543
Test name
Test status
Simulation time 209361536 ps
CPU time 2.67 seconds
Started Mar 14 12:58:11 PM PDT 24
Finished Mar 14 12:58:14 PM PDT 24
Peak memory 206820 kb
Host smart-3dd2d826-913f-4660-a644-23f2c8771583
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599961861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.599961861
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.3028139454
Short name T46
Test name
Test status
Simulation time 1173414054 ps
CPU time 12.39 seconds
Started Mar 14 12:58:01 PM PDT 24
Finished Mar 14 12:58:14 PM PDT 24
Peak memory 221368 kb
Host smart-bd18c11f-2c57-4f75-90d0-7ce0ecb9a591
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3028139454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.3028139454
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.1559952088
Short name T828
Test name
Test status
Simulation time 58775794 ps
CPU time 4.03 seconds
Started Mar 14 12:58:03 PM PDT 24
Finished Mar 14 12:58:08 PM PDT 24
Peak memory 214600 kb
Host smart-7d8efc19-e4c1-432a-936a-266666e17b48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1559952088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.1559952088
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.4078425208
Short name T620
Test name
Test status
Simulation time 197089971 ps
CPU time 2.66 seconds
Started Mar 14 12:58:01 PM PDT 24
Finished Mar 14 12:58:04 PM PDT 24
Peak memory 210736 kb
Host smart-1bb2f211-7e5c-41cc-816c-498f51dc83fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4078425208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.4078425208
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.3166445520
Short name T897
Test name
Test status
Simulation time 46323970 ps
CPU time 0.75 seconds
Started Mar 14 12:58:11 PM PDT 24
Finished Mar 14 12:58:12 PM PDT 24
Peak memory 206208 kb
Host smart-7ae3f761-a6f0-4c79-945d-c9fb514cd8d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166445520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.3166445520
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.761390817
Short name T224
Test name
Test status
Simulation time 108345798 ps
CPU time 4.69 seconds
Started Mar 14 12:58:02 PM PDT 24
Finished Mar 14 12:58:07 PM PDT 24
Peak memory 209996 kb
Host smart-12bcf495-ee2b-44ca-be61-614022997196
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=761390817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.761390817
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.2770176550
Short name T489
Test name
Test status
Simulation time 63233355 ps
CPU time 2.95 seconds
Started Mar 14 12:58:04 PM PDT 24
Finished Mar 14 12:58:08 PM PDT 24
Peak memory 208256 kb
Host smart-1947efe9-6335-40f4-bf56-becb57f69cb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2770176550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.2770176550
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.2000485479
Short name T196
Test name
Test status
Simulation time 2425896023 ps
CPU time 38.95 seconds
Started Mar 14 12:58:03 PM PDT 24
Finished Mar 14 12:58:44 PM PDT 24
Peak memory 216776 kb
Host smart-0f36c4b9-9242-4382-932a-cdce511ecd7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000485479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.2000485479
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.2049688542
Short name T57
Test name
Test status
Simulation time 182954342 ps
CPU time 3.09 seconds
Started Mar 14 12:58:02 PM PDT 24
Finished Mar 14 12:58:07 PM PDT 24
Peak memory 216016 kb
Host smart-1cc36aad-77be-4f49-8ba8-09eb21905fe3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049688542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.2049688542
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.718418421
Short name T269
Test name
Test status
Simulation time 4096674442 ps
CPU time 45.17 seconds
Started Mar 14 12:58:05 PM PDT 24
Finished Mar 14 12:58:51 PM PDT 24
Peak memory 218160 kb
Host smart-f82a0bab-8c6d-48db-9eda-d26ec2e5a2cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718418421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.718418421
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.2319478174
Short name T777
Test name
Test status
Simulation time 153571549 ps
CPU time 3.7 seconds
Started Mar 14 12:58:05 PM PDT 24
Finished Mar 14 12:58:10 PM PDT 24
Peak memory 207504 kb
Host smart-97af2ecb-f916-4a64-ba83-dd33441c97fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319478174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.2319478174
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.2465253590
Short name T707
Test name
Test status
Simulation time 1107949488 ps
CPU time 15.96 seconds
Started Mar 14 12:58:06 PM PDT 24
Finished Mar 14 12:58:23 PM PDT 24
Peak memory 208580 kb
Host smart-22e3491a-4e81-4e99-a395-20042eec2b73
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465253590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.2465253590
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.166079748
Short name T905
Test name
Test status
Simulation time 78530245 ps
CPU time 3.31 seconds
Started Mar 14 12:58:05 PM PDT 24
Finished Mar 14 12:58:09 PM PDT 24
Peak memory 209072 kb
Host smart-1ef78e4e-01e2-45b5-a832-7c2cd0abf541
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=166079748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.166079748
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.545232328
Short name T627
Test name
Test status
Simulation time 88846107 ps
CPU time 4.1 seconds
Started Mar 14 12:58:02 PM PDT 24
Finished Mar 14 12:58:07 PM PDT 24
Peak memory 209192 kb
Host smart-ced85fc2-7744-40da-a6e2-86a5013825fe
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=545232328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.545232328
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.1193607839
Short name T385
Test name
Test status
Simulation time 1723950190 ps
CPU time 6.24 seconds
Started Mar 14 12:58:06 PM PDT 24
Finished Mar 14 12:58:14 PM PDT 24
Peak memory 208784 kb
Host smart-2810e3df-d394-478f-8e16-59442d5b2218
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193607839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.1193607839
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.3380260077
Short name T380
Test name
Test status
Simulation time 823170220 ps
CPU time 8 seconds
Started Mar 14 12:58:04 PM PDT 24
Finished Mar 14 12:58:13 PM PDT 24
Peak memory 208936 kb
Host smart-ee3a142d-3938-4a55-b5fc-8f48ddf9bb48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3380260077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.3380260077
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.1199856706
Short name T337
Test name
Test status
Simulation time 24665090403 ps
CPU time 165.49 seconds
Started Mar 14 12:58:06 PM PDT 24
Finished Mar 14 01:00:53 PM PDT 24
Peak memory 222860 kb
Host smart-4ee4ae3e-c889-4d67-b61c-d9ca29522ff3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199856706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.1199856706
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.1162244243
Short name T323
Test name
Test status
Simulation time 91836213 ps
CPU time 4.42 seconds
Started Mar 14 12:58:05 PM PDT 24
Finished Mar 14 12:58:10 PM PDT 24
Peak memory 207980 kb
Host smart-c664773e-824b-4e5a-ac36-db69a8be1451
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162244243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.1162244243
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.3111710749
Short name T498
Test name
Test status
Simulation time 65645484 ps
CPU time 1.94 seconds
Started Mar 14 12:58:03 PM PDT 24
Finished Mar 14 12:58:07 PM PDT 24
Peak memory 210112 kb
Host smart-aa1ae920-79e6-4a13-9e15-ecb866a5dc71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3111710749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.3111710749
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.2893341322
Short name T407
Test name
Test status
Simulation time 85323014 ps
CPU time 1.04 seconds
Started Mar 14 12:55:48 PM PDT 24
Finished Mar 14 12:55:49 PM PDT 24
Peak memory 206492 kb
Host smart-d10a39c6-4e33-40b1-baa7-553f59add094
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893341322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.2893341322
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.1160263685
Short name T404
Test name
Test status
Simulation time 3316596297 ps
CPU time 42.17 seconds
Started Mar 14 12:55:38 PM PDT 24
Finished Mar 14 12:56:20 PM PDT 24
Peak memory 215960 kb
Host smart-e924da10-1e07-44cd-b0d3-418442377c12
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1160263685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.1160263685
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.3592946875
Short name T765
Test name
Test status
Simulation time 1028376907 ps
CPU time 6.05 seconds
Started Mar 14 12:55:48 PM PDT 24
Finished Mar 14 12:55:54 PM PDT 24
Peak memory 209304 kb
Host smart-21f4826a-f6d7-4227-9b51-42778ebf89b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3592946875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.3592946875
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.3731823404
Short name T575
Test name
Test status
Simulation time 87374881 ps
CPU time 3.66 seconds
Started Mar 14 12:55:39 PM PDT 24
Finished Mar 14 12:55:43 PM PDT 24
Peak memory 208392 kb
Host smart-6b68881f-8ab2-47fd-9e14-dce0f301cb54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731823404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.3731823404
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.2154055789
Short name T359
Test name
Test status
Simulation time 32310888 ps
CPU time 2.64 seconds
Started Mar 14 12:55:48 PM PDT 24
Finished Mar 14 12:55:50 PM PDT 24
Peak memory 209972 kb
Host smart-cd539472-9700-43c7-9837-61eb5ac84c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154055789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.2154055789
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.313081170
Short name T40
Test name
Test status
Simulation time 101148298 ps
CPU time 3.11 seconds
Started Mar 14 12:55:38 PM PDT 24
Finished Mar 14 12:55:41 PM PDT 24
Peak memory 207532 kb
Host smart-f2a6b730-5679-44a5-88d3-e19955f8e698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313081170 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.313081170
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.201910833
Short name T104
Test name
Test status
Simulation time 3033988806 ps
CPU time 67.21 seconds
Started Mar 14 12:55:49 PM PDT 24
Finished Mar 14 12:56:56 PM PDT 24
Peak memory 245292 kb
Host smart-4cc87eca-4188-4e15-8882-48cc2020366e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=201910833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.201910833
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sideload.587190909
Short name T3
Test name
Test status
Simulation time 323232383 ps
CPU time 4.49 seconds
Started Mar 14 12:55:42 PM PDT 24
Finished Mar 14 12:55:47 PM PDT 24
Peak memory 207308 kb
Host smart-a2c1732c-1309-4910-8054-5140a9e36b0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587190909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.587190909
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.1021097767
Short name T546
Test name
Test status
Simulation time 804555564 ps
CPU time 9.41 seconds
Started Mar 14 12:55:38 PM PDT 24
Finished Mar 14 12:55:48 PM PDT 24
Peak memory 208772 kb
Host smart-6b0ca418-0adf-451a-b242-d2c17a12be90
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021097767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.1021097767
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.2389463587
Short name T670
Test name
Test status
Simulation time 57567848 ps
CPU time 3.06 seconds
Started Mar 14 12:55:41 PM PDT 24
Finished Mar 14 12:55:45 PM PDT 24
Peak memory 208836 kb
Host smart-a4bad180-eb13-4f17-a618-f599127d9c39
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389463587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.2389463587
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.1975542270
Short name T306
Test name
Test status
Simulation time 96436653 ps
CPU time 3.66 seconds
Started Mar 14 12:55:38 PM PDT 24
Finished Mar 14 12:55:42 PM PDT 24
Peak memory 207040 kb
Host smart-fd4df7da-95ec-4c5b-a3b7-f2c2ffc6d4e1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1975542270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.1975542270
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.958673633
Short name T613
Test name
Test status
Simulation time 359571931 ps
CPU time 2.55 seconds
Started Mar 14 12:55:48 PM PDT 24
Finished Mar 14 12:55:50 PM PDT 24
Peak memory 214608 kb
Host smart-aad2b6dc-1026-453a-9ea9-a5884f165dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958673633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.958673633
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.3007047280
Short name T496
Test name
Test status
Simulation time 104485348 ps
CPU time 2.16 seconds
Started Mar 14 12:55:39 PM PDT 24
Finished Mar 14 12:55:41 PM PDT 24
Peak memory 209040 kb
Host smart-b05a8bb8-9470-4505-b929-11fce02726d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3007047280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.3007047280
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.2874717448
Short name T663
Test name
Test status
Simulation time 984679182 ps
CPU time 22.96 seconds
Started Mar 14 12:55:47 PM PDT 24
Finished Mar 14 12:56:10 PM PDT 24
Peak memory 217288 kb
Host smart-2b450f79-24fa-425d-a619-49ab0019c482
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2874717448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.2874717448
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.242111311
Short name T592
Test name
Test status
Simulation time 45765588 ps
CPU time 3.3 seconds
Started Mar 14 12:55:49 PM PDT 24
Finished Mar 14 12:55:52 PM PDT 24
Peak memory 218800 kb
Host smart-330529b3-b368-4757-be01-2417cf637fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=242111311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.242111311
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.256040719
Short name T553
Test name
Test status
Simulation time 1049070862 ps
CPU time 8.96 seconds
Started Mar 14 12:55:47 PM PDT 24
Finished Mar 14 12:55:56 PM PDT 24
Peak memory 210952 kb
Host smart-eacb39ba-a3c8-45b3-bc34-923398cd381f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256040719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.256040719
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.1082464532
Short name T532
Test name
Test status
Simulation time 34103725 ps
CPU time 0.99 seconds
Started Mar 14 12:58:20 PM PDT 24
Finished Mar 14 12:58:21 PM PDT 24
Peak memory 206372 kb
Host smart-8c3996a7-d7b0-453d-b51b-b44ee5175f89
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1082464532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.1082464532
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.2504697316
Short name T389
Test name
Test status
Simulation time 615419308 ps
CPU time 30.02 seconds
Started Mar 14 12:58:07 PM PDT 24
Finished Mar 14 12:58:38 PM PDT 24
Peak memory 214752 kb
Host smart-cc3f1baa-f6b3-4c33-9f03-c23c67787cc4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2504697316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.2504697316
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.2497808779
Short name T852
Test name
Test status
Simulation time 206016181 ps
CPU time 3.55 seconds
Started Mar 14 12:58:10 PM PDT 24
Finished Mar 14 12:58:14 PM PDT 24
Peak memory 219832 kb
Host smart-88efa191-e927-4342-8bb9-b6336eb8af27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497808779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.2497808779
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.1774027044
Short name T564
Test name
Test status
Simulation time 43712965 ps
CPU time 2.53 seconds
Started Mar 14 12:58:08 PM PDT 24
Finished Mar 14 12:58:12 PM PDT 24
Peak memory 210172 kb
Host smart-2980ba8c-99e9-4cf6-99e8-15f5a4edce2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1774027044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.1774027044
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.3911963281
Short name T855
Test name
Test status
Simulation time 1320656114 ps
CPU time 8.85 seconds
Started Mar 14 12:58:09 PM PDT 24
Finished Mar 14 12:58:19 PM PDT 24
Peak memory 222772 kb
Host smart-0f412fa5-43d2-402c-8c15-b386a0243f78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911963281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.3911963281
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.506914851
Short name T430
Test name
Test status
Simulation time 290605957 ps
CPU time 8.41 seconds
Started Mar 14 12:58:10 PM PDT 24
Finished Mar 14 12:58:19 PM PDT 24
Peak memory 214636 kb
Host smart-c55862c5-f3ea-4df2-8dc5-debcdbb5c110
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506914851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.506914851
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.3785615063
Short name T649
Test name
Test status
Simulation time 2023576501 ps
CPU time 26.97 seconds
Started Mar 14 12:58:10 PM PDT 24
Finished Mar 14 12:58:37 PM PDT 24
Peak memory 209612 kb
Host smart-c5d1c11b-b27e-4374-bfce-2ba59623193a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3785615063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.3785615063
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.4033211205
Short name T718
Test name
Test status
Simulation time 1796220852 ps
CPU time 3.95 seconds
Started Mar 14 12:58:05 PM PDT 24
Finished Mar 14 12:58:10 PM PDT 24
Peak memory 206944 kb
Host smart-283dc39c-f3e2-47ed-b20c-d6a3e9f938e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033211205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.4033211205
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.1590794540
Short name T517
Test name
Test status
Simulation time 491786974 ps
CPU time 7.52 seconds
Started Mar 14 12:58:00 PM PDT 24
Finished Mar 14 12:58:08 PM PDT 24
Peak memory 208916 kb
Host smart-1942f05f-cd83-4b5b-bfba-9bbe760c2934
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590794540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.1590794540
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.3442488301
Short name T473
Test name
Test status
Simulation time 3929860394 ps
CPU time 32.85 seconds
Started Mar 14 12:58:07 PM PDT 24
Finished Mar 14 12:58:41 PM PDT 24
Peak memory 208548 kb
Host smart-e06f77e3-3b01-457c-824b-14bb632d919e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442488301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.3442488301
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.415736362
Short name T778
Test name
Test status
Simulation time 749528245 ps
CPU time 2.78 seconds
Started Mar 14 12:58:04 PM PDT 24
Finished Mar 14 12:58:08 PM PDT 24
Peak memory 207212 kb
Host smart-3608149f-c4a6-4829-aac6-35e679987c03
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=415736362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.415736362
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.1424815201
Short name T537
Test name
Test status
Simulation time 158045602 ps
CPU time 3.34 seconds
Started Mar 14 12:58:12 PM PDT 24
Finished Mar 14 12:58:15 PM PDT 24
Peak memory 208820 kb
Host smart-1c9cee91-a82b-4216-a28c-c54f2007a91c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424815201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.1424815201
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.1337986603
Short name T843
Test name
Test status
Simulation time 94570737 ps
CPU time 3.35 seconds
Started Mar 14 12:58:02 PM PDT 24
Finished Mar 14 12:58:05 PM PDT 24
Peak memory 206976 kb
Host smart-6abf1a91-3d26-41e9-8c39-e2eeadab1731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337986603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.1337986603
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.2215565279
Short name T326
Test name
Test status
Simulation time 2015279681 ps
CPU time 22.28 seconds
Started Mar 14 12:58:19 PM PDT 24
Finished Mar 14 12:58:42 PM PDT 24
Peak memory 215196 kb
Host smart-cd8bdfc1-2fb9-4ebd-b191-72f33c74b246
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215565279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.2215565279
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.2159845676
Short name T440
Test name
Test status
Simulation time 196521208 ps
CPU time 6.18 seconds
Started Mar 14 12:58:02 PM PDT 24
Finished Mar 14 12:58:10 PM PDT 24
Peak memory 209412 kb
Host smart-c06ebe16-2f76-40cd-bd84-9340339b609f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2159845676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.2159845676
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.2204773162
Short name T570
Test name
Test status
Simulation time 22025558 ps
CPU time 0.71 seconds
Started Mar 14 12:58:13 PM PDT 24
Finished Mar 14 12:58:15 PM PDT 24
Peak memory 206300 kb
Host smart-08b454a1-3b4d-4798-b3e9-7942e5eeb2d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2204773162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.2204773162
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.1333812040
Short name T629
Test name
Test status
Simulation time 319446633 ps
CPU time 4.76 seconds
Started Mar 14 12:58:21 PM PDT 24
Finished Mar 14 12:58:26 PM PDT 24
Peak memory 217376 kb
Host smart-092f89dd-6021-4af0-af59-7ed6a44f3058
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333812040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.1333812040
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.97875668
Short name T780
Test name
Test status
Simulation time 265931936 ps
CPU time 3.57 seconds
Started Mar 14 12:58:14 PM PDT 24
Finished Mar 14 12:58:19 PM PDT 24
Peak memory 209868 kb
Host smart-666b3f54-7bea-4f23-a8ea-6a948d143c65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97875668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.97875668
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.156278080
Short name T19
Test name
Test status
Simulation time 1696442669 ps
CPU time 35.88 seconds
Started Mar 14 12:58:10 PM PDT 24
Finished Mar 14 12:58:47 PM PDT 24
Peak memory 214516 kb
Host smart-ad03fe81-c594-4c32-8068-f24b4f42569e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156278080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.156278080
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.1395593875
Short name T768
Test name
Test status
Simulation time 404829666 ps
CPU time 4.39 seconds
Started Mar 14 12:58:12 PM PDT 24
Finished Mar 14 12:58:17 PM PDT 24
Peak memory 209420 kb
Host smart-e83f3df0-15f5-4608-bb34-70c9e076241e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395593875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.1395593875
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.2464467745
Short name T340
Test name
Test status
Simulation time 198700877 ps
CPU time 3.57 seconds
Started Mar 14 12:58:13 PM PDT 24
Finished Mar 14 12:58:17 PM PDT 24
Peak memory 208564 kb
Host smart-3477f699-e619-4a99-b95f-3971263a6cd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2464467745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.2464467745
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.1592998965
Short name T838
Test name
Test status
Simulation time 82100622 ps
CPU time 3.68 seconds
Started Mar 14 12:58:10 PM PDT 24
Finished Mar 14 12:58:15 PM PDT 24
Peak memory 208708 kb
Host smart-d7937868-8f57-41a4-ba56-6020617ee030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592998965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.1592998965
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.2786893395
Short name T734
Test name
Test status
Simulation time 176172071 ps
CPU time 5.18 seconds
Started Mar 14 12:58:10 PM PDT 24
Finished Mar 14 12:58:15 PM PDT 24
Peak memory 208740 kb
Host smart-c30e2b4b-8efa-4879-a640-6cba35ae7205
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786893395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.2786893395
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.273428584
Short name T641
Test name
Test status
Simulation time 167705653 ps
CPU time 2.77 seconds
Started Mar 14 12:58:11 PM PDT 24
Finished Mar 14 12:58:14 PM PDT 24
Peak memory 209264 kb
Host smart-c736ea1f-f210-4231-a1dd-5c0e2e0a483d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273428584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.273428584
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.919615057
Short name T786
Test name
Test status
Simulation time 594520729 ps
CPU time 3.98 seconds
Started Mar 14 12:58:11 PM PDT 24
Finished Mar 14 12:58:15 PM PDT 24
Peak memory 207772 kb
Host smart-00f90f37-b7ec-4a58-b7fd-61847818f66f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919615057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.919615057
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.1817199024
Short name T902
Test name
Test status
Simulation time 96383627 ps
CPU time 3.83 seconds
Started Mar 14 12:58:14 PM PDT 24
Finished Mar 14 12:58:18 PM PDT 24
Peak memory 210500 kb
Host smart-2f468ba0-f4fb-45f5-8656-bad5e7c02a6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817199024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.1817199024
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.114796490
Short name T482
Test name
Test status
Simulation time 1141554796 ps
CPU time 8.38 seconds
Started Mar 14 12:58:13 PM PDT 24
Finished Mar 14 12:58:21 PM PDT 24
Peak memory 208352 kb
Host smart-509900a3-c469-4e90-908e-479d2d5ba42e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114796490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.114796490
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.1345897464
Short name T256
Test name
Test status
Simulation time 925195859 ps
CPU time 32.28 seconds
Started Mar 14 12:58:11 PM PDT 24
Finished Mar 14 12:58:43 PM PDT 24
Peak memory 217372 kb
Host smart-ef722d42-a52e-47c8-9fdf-fd244f646642
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1345897464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.1345897464
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.1358270609
Short name T747
Test name
Test status
Simulation time 223233376 ps
CPU time 3.6 seconds
Started Mar 14 12:58:11 PM PDT 24
Finished Mar 14 12:58:15 PM PDT 24
Peak memory 207560 kb
Host smart-0444b923-af21-408f-a913-1cc69da8e3bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358270609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.1358270609
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.3997918180
Short name T596
Test name
Test status
Simulation time 49279294 ps
CPU time 2.91 seconds
Started Mar 14 12:58:19 PM PDT 24
Finished Mar 14 12:58:22 PM PDT 24
Peak memory 210256 kb
Host smart-1c517d9a-11db-4a3b-ae13-092902d1e48c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3997918180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.3997918180
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.535391754
Short name T634
Test name
Test status
Simulation time 45774158 ps
CPU time 0.72 seconds
Started Mar 14 12:58:11 PM PDT 24
Finished Mar 14 12:58:12 PM PDT 24
Peak memory 206200 kb
Host smart-f660b48a-f953-4584-98dc-7a89c2d5d9e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=535391754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.535391754
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.2928486287
Short name T403
Test name
Test status
Simulation time 57807287 ps
CPU time 2.59 seconds
Started Mar 14 12:58:10 PM PDT 24
Finished Mar 14 12:58:13 PM PDT 24
Peak memory 214576 kb
Host smart-164966eb-5a71-4f00-b50e-f8a5290bb91f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2928486287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.2928486287
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.303958540
Short name T9
Test name
Test status
Simulation time 120308723 ps
CPU time 5.48 seconds
Started Mar 14 12:58:10 PM PDT 24
Finished Mar 14 12:58:16 PM PDT 24
Peak memory 210824 kb
Host smart-da6b718b-65ee-45fb-b298-930439bb0a70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=303958540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.303958540
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.798877373
Short name T469
Test name
Test status
Simulation time 45065091 ps
CPU time 2.27 seconds
Started Mar 14 12:58:10 PM PDT 24
Finished Mar 14 12:58:13 PM PDT 24
Peak memory 209044 kb
Host smart-a115755a-36a1-4ef6-9420-cb1eb20c8183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=798877373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.798877373
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.3559022957
Short name T834
Test name
Test status
Simulation time 5038224589 ps
CPU time 46.82 seconds
Started Mar 14 12:58:21 PM PDT 24
Finished Mar 14 12:59:08 PM PDT 24
Peak memory 214612 kb
Host smart-f366817f-a1e4-452e-abd8-75da189386ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559022957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.3559022957
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.2327622415
Short name T208
Test name
Test status
Simulation time 14457947244 ps
CPU time 57.13 seconds
Started Mar 14 12:58:12 PM PDT 24
Finished Mar 14 12:59:10 PM PDT 24
Peak memory 224296 kb
Host smart-672558e2-d8fa-4fe2-8995-444eac0badd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2327622415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.2327622415
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.540525118
Short name T548
Test name
Test status
Simulation time 109307123 ps
CPU time 2.56 seconds
Started Mar 14 12:58:15 PM PDT 24
Finished Mar 14 12:58:17 PM PDT 24
Peak memory 210096 kb
Host smart-f82fe7cd-f021-425e-955a-853566c3d233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=540525118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.540525118
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.3631924783
Short name T870
Test name
Test status
Simulation time 101219885 ps
CPU time 3.6 seconds
Started Mar 14 12:58:10 PM PDT 24
Finished Mar 14 12:58:14 PM PDT 24
Peak memory 218624 kb
Host smart-6c423173-63db-4ebb-a799-c9e92789b939
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631924783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.3631924783
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.1932481460
Short name T206
Test name
Test status
Simulation time 181593030 ps
CPU time 2.71 seconds
Started Mar 14 12:58:10 PM PDT 24
Finished Mar 14 12:58:13 PM PDT 24
Peak memory 207420 kb
Host smart-3212a21d-e095-4637-b10d-a9f2dad6fcd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1932481460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.1932481460
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.3144202033
Short name T523
Test name
Test status
Simulation time 308007308 ps
CPU time 10.35 seconds
Started Mar 14 12:58:14 PM PDT 24
Finished Mar 14 12:58:24 PM PDT 24
Peak memory 209036 kb
Host smart-3d401316-c128-4a49-8e45-0d40e6d19a45
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144202033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.3144202033
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.3527435057
Short name T472
Test name
Test status
Simulation time 154925041 ps
CPU time 2.68 seconds
Started Mar 14 12:58:11 PM PDT 24
Finished Mar 14 12:58:14 PM PDT 24
Peak memory 208704 kb
Host smart-8e84d83f-ac04-4c1b-a489-2932b8dfe6f3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3527435057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.3527435057
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.940431511
Short name T295
Test name
Test status
Simulation time 241817963 ps
CPU time 6.7 seconds
Started Mar 14 12:58:09 PM PDT 24
Finished Mar 14 12:58:16 PM PDT 24
Peak memory 208872 kb
Host smart-402be89d-f787-46b5-b6a0-8d7102704486
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=940431511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.940431511
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.637755672
Short name T531
Test name
Test status
Simulation time 101799066 ps
CPU time 3.8 seconds
Started Mar 14 12:58:21 PM PDT 24
Finished Mar 14 12:58:25 PM PDT 24
Peak memory 214620 kb
Host smart-58195c46-5f7e-4436-8b30-71e87598e231
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=637755672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.637755672
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.1151253224
Short name T554
Test name
Test status
Simulation time 57080471 ps
CPU time 2.85 seconds
Started Mar 14 12:58:19 PM PDT 24
Finished Mar 14 12:58:22 PM PDT 24
Peak memory 208472 kb
Host smart-d25a8fca-a674-4ff5-8f46-288b6a96ad87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151253224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.1151253224
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all_with_rand_reset.1562554163
Short name T127
Test name
Test status
Simulation time 198451481 ps
CPU time 8.36 seconds
Started Mar 14 12:58:21 PM PDT 24
Finished Mar 14 12:58:30 PM PDT 24
Peak memory 222044 kb
Host smart-c1f0a194-3cff-4950-bfb9-9a5d0c5db7a3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562554163 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all_with_rand_reset.1562554163
Directory /workspace/32.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.1717913295
Short name T851
Test name
Test status
Simulation time 2018114183 ps
CPU time 15.26 seconds
Started Mar 14 12:58:10 PM PDT 24
Finished Mar 14 12:58:26 PM PDT 24
Peak memory 209700 kb
Host smart-e3c6f082-b497-4b25-91ea-900c6b66a94f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1717913295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.1717913295
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.2512944623
Short name T56
Test name
Test status
Simulation time 112733532 ps
CPU time 2.06 seconds
Started Mar 14 12:58:09 PM PDT 24
Finished Mar 14 12:58:12 PM PDT 24
Peak memory 210016 kb
Host smart-17e56428-4df0-47f3-82c4-19ce215b484b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512944623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.2512944623
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.361234699
Short name T479
Test name
Test status
Simulation time 66920683 ps
CPU time 0.79 seconds
Started Mar 14 12:58:19 PM PDT 24
Finished Mar 14 12:58:20 PM PDT 24
Peak memory 206204 kb
Host smart-e26768dc-b740-46f5-b234-f341bb2d670e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=361234699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.361234699
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.4196760644
Short name T287
Test name
Test status
Simulation time 142887285 ps
CPU time 3.35 seconds
Started Mar 14 12:58:20 PM PDT 24
Finished Mar 14 12:58:23 PM PDT 24
Peak memory 214560 kb
Host smart-f1ab4b80-548a-4619-ade0-433c2ab3df6d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4196760644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.4196760644
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.1568318574
Short name T599
Test name
Test status
Simulation time 157794585 ps
CPU time 3.77 seconds
Started Mar 14 12:58:18 PM PDT 24
Finished Mar 14 12:58:22 PM PDT 24
Peak memory 220528 kb
Host smart-27fd8544-db57-4774-9161-c885f612cfa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568318574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.1568318574
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.119098736
Short name T567
Test name
Test status
Simulation time 29363540 ps
CPU time 1.68 seconds
Started Mar 14 12:58:20 PM PDT 24
Finished Mar 14 12:58:21 PM PDT 24
Peak memory 207808 kb
Host smart-b387c5a5-efcd-4020-9c94-0cac13c36709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119098736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.119098736
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.694801616
Short name T93
Test name
Test status
Simulation time 224578071 ps
CPU time 5.92 seconds
Started Mar 14 12:58:20 PM PDT 24
Finished Mar 14 12:58:26 PM PDT 24
Peak memory 209488 kb
Host smart-a0e495ac-bec5-47ad-ba61-e67a9f9e2be3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694801616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.694801616
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.3072296757
Short name T232
Test name
Test status
Simulation time 350684791 ps
CPU time 4.27 seconds
Started Mar 14 12:58:18 PM PDT 24
Finished Mar 14 12:58:22 PM PDT 24
Peak memory 220588 kb
Host smart-658934af-1470-45e8-a6b5-ed096e590c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3072296757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.3072296757
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_sideload.658223714
Short name T766
Test name
Test status
Simulation time 128104933 ps
CPU time 2.34 seconds
Started Mar 14 12:58:19 PM PDT 24
Finished Mar 14 12:58:21 PM PDT 24
Peak memory 207032 kb
Host smart-e0621846-dd51-4aa8-b944-b852375b71f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658223714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.658223714
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.2086597032
Short name T635
Test name
Test status
Simulation time 50578103 ps
CPU time 2.61 seconds
Started Mar 14 12:58:24 PM PDT 24
Finished Mar 14 12:58:27 PM PDT 24
Peak memory 206900 kb
Host smart-d9e28f57-d526-4e83-8068-afcf5c9fb014
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086597032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.2086597032
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.217030355
Short name T683
Test name
Test status
Simulation time 113716422 ps
CPU time 3.62 seconds
Started Mar 14 12:58:19 PM PDT 24
Finished Mar 14 12:58:23 PM PDT 24
Peak memory 207000 kb
Host smart-417165e2-a315-40d4-a630-ab2492cbfb89
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=217030355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.217030355
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.2438596752
Short name T839
Test name
Test status
Simulation time 221815634 ps
CPU time 3.25 seconds
Started Mar 14 12:58:22 PM PDT 24
Finished Mar 14 12:58:26 PM PDT 24
Peak memory 209076 kb
Host smart-4dedfbb9-c316-4c66-a5c2-37232087676d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438596752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.2438596752
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.1495534015
Short name T744
Test name
Test status
Simulation time 27339031 ps
CPU time 2.04 seconds
Started Mar 14 12:58:18 PM PDT 24
Finished Mar 14 12:58:20 PM PDT 24
Peak memory 209956 kb
Host smart-5bc91faa-1360-4fee-bbb8-3c2ab7eb5dac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1495534015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.1495534015
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.728129802
Short name T109
Test name
Test status
Simulation time 515316276 ps
CPU time 6.58 seconds
Started Mar 14 12:58:21 PM PDT 24
Finished Mar 14 12:58:27 PM PDT 24
Peak memory 208512 kb
Host smart-3fe18919-fdc7-4b6b-b44f-4d83f8a95e62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=728129802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.728129802
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.1592018464
Short name T72
Test name
Test status
Simulation time 8327943070 ps
CPU time 139.6 seconds
Started Mar 14 12:58:22 PM PDT 24
Finished Mar 14 01:00:42 PM PDT 24
Peak memory 222900 kb
Host smart-de3066e0-b608-46aa-9623-2e6a0c375749
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1592018464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.1592018464
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_stress_all_with_rand_reset.2896230378
Short name T178
Test name
Test status
Simulation time 352249221 ps
CPU time 13.99 seconds
Started Mar 14 12:58:19 PM PDT 24
Finished Mar 14 12:58:33 PM PDT 24
Peak memory 222972 kb
Host smart-82cd7001-268e-4fd6-88aa-a341687569a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2896230378 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all_with_rand_reset.2896230378
Directory /workspace/33.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.951388107
Short name T202
Test name
Test status
Simulation time 3939024802 ps
CPU time 29.34 seconds
Started Mar 14 12:58:21 PM PDT 24
Finished Mar 14 12:58:51 PM PDT 24
Peak memory 209348 kb
Host smart-e78c47fc-64e9-4392-98c2-9b5c84322094
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=951388107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.951388107
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.2565041963
Short name T518
Test name
Test status
Simulation time 712702981 ps
CPU time 7.37 seconds
Started Mar 14 12:58:19 PM PDT 24
Finished Mar 14 12:58:27 PM PDT 24
Peak memory 211000 kb
Host smart-537e1ac0-98f6-4654-91c1-0b0ee830ed3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565041963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.2565041963
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.1274697350
Short name T491
Test name
Test status
Simulation time 22662693 ps
CPU time 0.86 seconds
Started Mar 14 12:58:20 PM PDT 24
Finished Mar 14 12:58:21 PM PDT 24
Peak memory 206204 kb
Host smart-4260d217-6175-4d65-8d66-a6f8c8a068b2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274697350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.1274697350
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.243914190
Short name T297
Test name
Test status
Simulation time 34849792 ps
CPU time 2.9 seconds
Started Mar 14 12:58:18 PM PDT 24
Finished Mar 14 12:58:21 PM PDT 24
Peak memory 214620 kb
Host smart-680865d2-7096-48b1-9bd6-ab1121e7f50e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=243914190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.243914190
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.3150996739
Short name T64
Test name
Test status
Simulation time 967330030 ps
CPU time 8.92 seconds
Started Mar 14 12:58:19 PM PDT 24
Finished Mar 14 12:58:28 PM PDT 24
Peak memory 209812 kb
Host smart-89d034ce-4866-441c-8cdd-064c0388619a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3150996739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.3150996739
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.3532555244
Short name T750
Test name
Test status
Simulation time 89328525 ps
CPU time 1.56 seconds
Started Mar 14 12:58:21 PM PDT 24
Finished Mar 14 12:58:23 PM PDT 24
Peak memory 209380 kb
Host smart-5f775517-6459-47be-9010-b55e5a6bc21e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532555244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.3532555244
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.446187273
Short name T525
Test name
Test status
Simulation time 567670493 ps
CPU time 6.84 seconds
Started Mar 14 12:58:20 PM PDT 24
Finished Mar 14 12:58:27 PM PDT 24
Peak memory 222836 kb
Host smart-9f021cb1-718d-402c-a577-d860b5d974c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=446187273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.446187273
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.394828028
Short name T890
Test name
Test status
Simulation time 185634118 ps
CPU time 6.01 seconds
Started Mar 14 12:58:25 PM PDT 24
Finished Mar 14 12:58:31 PM PDT 24
Peak memory 211436 kb
Host smart-ed01c517-4053-41e4-b529-5dc1a401da06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394828028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.394828028
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.2780346445
Short name T272
Test name
Test status
Simulation time 231889445 ps
CPU time 4.97 seconds
Started Mar 14 12:58:20 PM PDT 24
Finished Mar 14 12:58:25 PM PDT 24
Peak memory 210496 kb
Host smart-60adebe9-fbad-4fe6-b35e-a2641f981d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2780346445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.2780346445
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.754765495
Short name T818
Test name
Test status
Simulation time 8380272441 ps
CPU time 46.77 seconds
Started Mar 14 12:58:19 PM PDT 24
Finished Mar 14 12:59:06 PM PDT 24
Peak memory 210268 kb
Host smart-a936fd7e-7cad-46a9-97b6-e4931b100fbe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754765495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.754765495
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.3518053191
Short name T880
Test name
Test status
Simulation time 268755460 ps
CPU time 3.29 seconds
Started Mar 14 12:58:18 PM PDT 24
Finished Mar 14 12:58:22 PM PDT 24
Peak memory 208596 kb
Host smart-6c72fd4e-43b9-4f64-8c02-7d64a7f273b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518053191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.3518053191
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.3845886136
Short name T475
Test name
Test status
Simulation time 311736409 ps
CPU time 5.22 seconds
Started Mar 14 12:58:19 PM PDT 24
Finished Mar 14 12:58:24 PM PDT 24
Peak memory 207164 kb
Host smart-1e31ce07-f7e7-49f5-bc82-cac134167dae
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3845886136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.3845886136
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.1960924173
Short name T14
Test name
Test status
Simulation time 715366098 ps
CPU time 4.31 seconds
Started Mar 14 12:58:19 PM PDT 24
Finished Mar 14 12:58:24 PM PDT 24
Peak memory 207096 kb
Host smart-0ceae0d7-d62d-4668-b822-4dc4941dc803
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960924173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.1960924173
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.2164893978
Short name T653
Test name
Test status
Simulation time 161460038 ps
CPU time 3.19 seconds
Started Mar 14 12:58:19 PM PDT 24
Finished Mar 14 12:58:23 PM PDT 24
Peak memory 207152 kb
Host smart-bba2d129-229a-4427-9e11-f70f0c88d22b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2164893978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.2164893978
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.3910186662
Short name T862
Test name
Test status
Simulation time 595234120 ps
CPU time 5.71 seconds
Started Mar 14 12:58:21 PM PDT 24
Finished Mar 14 12:58:27 PM PDT 24
Peak memory 208952 kb
Host smart-70bf452c-5cb5-4251-955a-49cf503c1b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3910186662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.3910186662
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.104431360
Short name T383
Test name
Test status
Simulation time 244361794 ps
CPU time 3.27 seconds
Started Mar 14 12:58:19 PM PDT 24
Finished Mar 14 12:58:22 PM PDT 24
Peak memory 208588 kb
Host smart-c7ae7cb7-4357-4f58-bcb2-f219b01ce410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104431360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.104431360
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.4141983388
Short name T301
Test name
Test status
Simulation time 120877502 ps
CPU time 5.71 seconds
Started Mar 14 12:58:25 PM PDT 24
Finished Mar 14 12:58:31 PM PDT 24
Peak memory 210480 kb
Host smart-3279ed12-f069-4e42-af75-52eef1f0b636
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141983388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.4141983388
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.306154419
Short name T612
Test name
Test status
Simulation time 41450328 ps
CPU time 1.81 seconds
Started Mar 14 12:58:18 PM PDT 24
Finished Mar 14 12:58:20 PM PDT 24
Peak memory 209712 kb
Host smart-5409f3dc-0e9a-457b-a8ca-2d9d737471e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306154419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.306154419
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.2902723997
Short name T582
Test name
Test status
Simulation time 107620874 ps
CPU time 0.82 seconds
Started Mar 14 12:58:30 PM PDT 24
Finished Mar 14 12:58:31 PM PDT 24
Peak memory 206204 kb
Host smart-08a740e8-b015-4603-9e74-a5c30d295dc3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902723997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.2902723997
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.3943835177
Short name T280
Test name
Test status
Simulation time 334974403 ps
CPU time 4.22 seconds
Started Mar 14 12:58:28 PM PDT 24
Finished Mar 14 12:58:33 PM PDT 24
Peak memory 215812 kb
Host smart-ae8c25b6-fea1-4eff-ba5a-68b68253331d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3943835177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.3943835177
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.3361594128
Short name T560
Test name
Test status
Simulation time 1217208656 ps
CPU time 4.15 seconds
Started Mar 14 12:58:31 PM PDT 24
Finished Mar 14 12:58:35 PM PDT 24
Peak memory 218804 kb
Host smart-09cff7a1-b524-4dfe-a153-e5912710325c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3361594128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.3361594128
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.2409472637
Short name T95
Test name
Test status
Simulation time 231609678 ps
CPU time 3.24 seconds
Started Mar 14 12:58:31 PM PDT 24
Finished Mar 14 12:58:34 PM PDT 24
Peak memory 214624 kb
Host smart-f7332ea6-f2b6-4b97-8c4a-eb84966ddebe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2409472637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.2409472637
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.1219404735
Short name T632
Test name
Test status
Simulation time 103886728 ps
CPU time 4.88 seconds
Started Mar 14 12:58:30 PM PDT 24
Finished Mar 14 12:58:35 PM PDT 24
Peak memory 210428 kb
Host smart-b6ae0e7b-4758-4a2e-98f1-0f01a15e451f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219404735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.1219404735
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.3975463450
Short name T640
Test name
Test status
Simulation time 236640801 ps
CPU time 2.86 seconds
Started Mar 14 12:58:29 PM PDT 24
Finished Mar 14 12:58:32 PM PDT 24
Peak memory 207876 kb
Host smart-a6fd0ebe-32fd-4283-87ec-3a2b5bdfb5ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3975463450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.3975463450
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.3331648187
Short name T303
Test name
Test status
Simulation time 178274837 ps
CPU time 3.43 seconds
Started Mar 14 12:58:20 PM PDT 24
Finished Mar 14 12:58:23 PM PDT 24
Peak memory 208760 kb
Host smart-7a036f75-0329-4335-9610-6140d490dc04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3331648187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.3331648187
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.2055671766
Short name T423
Test name
Test status
Simulation time 1256682741 ps
CPU time 12.74 seconds
Started Mar 14 12:58:19 PM PDT 24
Finished Mar 14 12:58:32 PM PDT 24
Peak memory 208420 kb
Host smart-b27fcfd0-dc1c-4620-bd21-545f665551b4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055671766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.2055671766
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.2498699332
Short name T527
Test name
Test status
Simulation time 31626222 ps
CPU time 2.23 seconds
Started Mar 14 12:58:21 PM PDT 24
Finished Mar 14 12:58:23 PM PDT 24
Peak memory 209024 kb
Host smart-6a6a93b1-93b6-4d8c-a960-4091389306eb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498699332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.2498699332
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.4253669805
Short name T441
Test name
Test status
Simulation time 39133549 ps
CPU time 2.34 seconds
Started Mar 14 12:58:29 PM PDT 24
Finished Mar 14 12:58:32 PM PDT 24
Peak memory 208128 kb
Host smart-f795f238-cd2e-4926-86d0-3d79acc78f04
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253669805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.4253669805
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.994355716
Short name T565
Test name
Test status
Simulation time 89724620 ps
CPU time 2.88 seconds
Started Mar 14 12:58:30 PM PDT 24
Finished Mar 14 12:58:33 PM PDT 24
Peak memory 218628 kb
Host smart-554bab3b-24ba-48d6-a34a-7108c8fd27d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=994355716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.994355716
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.1058206286
Short name T883
Test name
Test status
Simulation time 4815410020 ps
CPU time 15.1 seconds
Started Mar 14 12:58:19 PM PDT 24
Finished Mar 14 12:58:34 PM PDT 24
Peak memory 209220 kb
Host smart-a1466eca-5e20-4cf1-9b5e-8d20a1466dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058206286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.1058206286
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.2083514106
Short name T49
Test name
Test status
Simulation time 8873947538 ps
CPU time 59.12 seconds
Started Mar 14 12:58:29 PM PDT 24
Finished Mar 14 12:59:29 PM PDT 24
Peak memory 217124 kb
Host smart-760b70c2-bcac-421e-ba47-706977c416e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2083514106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.2083514106
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.1746571101
Short name T356
Test name
Test status
Simulation time 1255208218 ps
CPU time 31.97 seconds
Started Mar 14 12:58:30 PM PDT 24
Finished Mar 14 12:59:02 PM PDT 24
Peak memory 218572 kb
Host smart-08d205a8-f4bc-4165-893f-0d61bf1f591a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746571101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.1746571101
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.3920189226
Short name T124
Test name
Test status
Simulation time 95377495 ps
CPU time 3.13 seconds
Started Mar 14 12:58:28 PM PDT 24
Finished Mar 14 12:58:32 PM PDT 24
Peak memory 210460 kb
Host smart-68619a27-01f3-4b09-940f-5ed900532254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920189226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.3920189226
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.179049027
Short name T664
Test name
Test status
Simulation time 22319854 ps
CPU time 0.72 seconds
Started Mar 14 12:58:40 PM PDT 24
Finished Mar 14 12:58:41 PM PDT 24
Peak memory 206204 kb
Host smart-2213d068-d35f-49f7-adfa-91adadb8e3a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=179049027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.179049027
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.3609835758
Short name T279
Test name
Test status
Simulation time 41087798 ps
CPU time 3.13 seconds
Started Mar 14 12:58:30 PM PDT 24
Finished Mar 14 12:58:33 PM PDT 24
Peak memory 215624 kb
Host smart-0b3dd274-ce93-4cff-83ac-bc0798005008
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3609835758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.3609835758
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.1116092525
Short name T29
Test name
Test status
Simulation time 94245198 ps
CPU time 4.81 seconds
Started Mar 14 12:58:30 PM PDT 24
Finished Mar 14 12:58:35 PM PDT 24
Peak memory 220368 kb
Host smart-7725215e-4297-4b4c-a5b1-668e53c41e40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116092525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.1116092525
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.649817373
Short name T495
Test name
Test status
Simulation time 193655531 ps
CPU time 2.27 seconds
Started Mar 14 12:58:30 PM PDT 24
Finished Mar 14 12:58:32 PM PDT 24
Peak memory 208820 kb
Host smart-4a7576f3-c83b-42bc-930e-c83fa01846b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=649817373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.649817373
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.1778041966
Short name T217
Test name
Test status
Simulation time 469215509 ps
CPU time 3.98 seconds
Started Mar 14 12:58:30 PM PDT 24
Finished Mar 14 12:58:35 PM PDT 24
Peak memory 222800 kb
Host smart-fd06ef46-b2e0-42f6-9293-a21313fa72dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778041966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.1778041966
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.3489247583
Short name T650
Test name
Test status
Simulation time 41478820 ps
CPU time 3.04 seconds
Started Mar 14 12:58:30 PM PDT 24
Finished Mar 14 12:58:33 PM PDT 24
Peak memory 210264 kb
Host smart-0dfb140b-0937-4cdf-b226-9454d91c2445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489247583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.3489247583
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.2992705675
Short name T802
Test name
Test status
Simulation time 148322608 ps
CPU time 2.8 seconds
Started Mar 14 12:58:37 PM PDT 24
Finished Mar 14 12:58:40 PM PDT 24
Peak memory 208808 kb
Host smart-83926713-8653-4603-9b40-5c4d4b0b7821
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2992705675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.2992705675
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.3151613228
Short name T471
Test name
Test status
Simulation time 247270004 ps
CPU time 7.29 seconds
Started Mar 14 12:58:30 PM PDT 24
Finished Mar 14 12:58:38 PM PDT 24
Peak memory 209008 kb
Host smart-0d248dc7-a49e-4e73-a828-cdfa48056022
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151613228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.3151613228
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.3120182155
Short name T129
Test name
Test status
Simulation time 257561613 ps
CPU time 2.94 seconds
Started Mar 14 12:58:29 PM PDT 24
Finished Mar 14 12:58:32 PM PDT 24
Peak memory 207076 kb
Host smart-fb55c9bd-6a72-43f7-af36-04c3064b4662
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120182155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.3120182155
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.3461569650
Short name T669
Test name
Test status
Simulation time 65816136 ps
CPU time 3.47 seconds
Started Mar 14 12:58:30 PM PDT 24
Finished Mar 14 12:58:34 PM PDT 24
Peak memory 206976 kb
Host smart-e41f9977-eb9f-4ab8-afaf-7fed024e5137
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3461569650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.3461569650
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.1981032223
Short name T740
Test name
Test status
Simulation time 70169346 ps
CPU time 1.95 seconds
Started Mar 14 12:58:31 PM PDT 24
Finished Mar 14 12:58:33 PM PDT 24
Peak memory 209124 kb
Host smart-a4b4657d-c4ea-4c02-999e-0c35bdf97b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1981032223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.1981032223
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.2964489710
Short name T464
Test name
Test status
Simulation time 209360835 ps
CPU time 5.34 seconds
Started Mar 14 12:58:31 PM PDT 24
Finished Mar 14 12:58:36 PM PDT 24
Peak memory 208636 kb
Host smart-63065e0e-caf9-4862-a16c-1a47dcc4503a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2964489710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.2964489710
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.1390501079
Short name T219
Test name
Test status
Simulation time 8470579304 ps
CPU time 258.47 seconds
Started Mar 14 12:58:47 PM PDT 24
Finished Mar 14 01:03:06 PM PDT 24
Peak memory 219208 kb
Host smart-705e0eaa-8afb-4875-a0dd-cb71356b3b8a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390501079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.1390501079
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_stress_all_with_rand_reset.3005660637
Short name T177
Test name
Test status
Simulation time 235906127 ps
CPU time 8.82 seconds
Started Mar 14 12:58:42 PM PDT 24
Finished Mar 14 12:58:51 PM PDT 24
Peak memory 222856 kb
Host smart-27ccfc14-443f-44e2-bc95-0de3762681a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005660637 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all_with_rand_reset.3005660637
Directory /workspace/36.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.2805468450
Short name T708
Test name
Test status
Simulation time 173540479 ps
CPU time 6.74 seconds
Started Mar 14 12:58:32 PM PDT 24
Finished Mar 14 12:58:38 PM PDT 24
Peak memory 208260 kb
Host smart-75def7ca-0d0f-4e67-8d85-93541db5f2b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805468450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.2805468450
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.621645306
Short name T594
Test name
Test status
Simulation time 218671785 ps
CPU time 1.99 seconds
Started Mar 14 12:58:45 PM PDT 24
Finished Mar 14 12:58:47 PM PDT 24
Peak memory 210236 kb
Host smart-294c4809-7119-496c-aa21-420f8624a062
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621645306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.621645306
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.2709898132
Short name T506
Test name
Test status
Simulation time 28624545 ps
CPU time 0.78 seconds
Started Mar 14 12:58:43 PM PDT 24
Finished Mar 14 12:58:44 PM PDT 24
Peak memory 206288 kb
Host smart-36fd6a28-984b-4f29-955c-ea5609ac56b6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709898132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.2709898132
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.1296575717
Short name T204
Test name
Test status
Simulation time 21138381 ps
CPU time 1.99 seconds
Started Mar 14 12:58:42 PM PDT 24
Finished Mar 14 12:58:44 PM PDT 24
Peak memory 216540 kb
Host smart-fa0e2afe-0ae0-49aa-a298-cb03af5ce8cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296575717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.1296575717
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.775564533
Short name T859
Test name
Test status
Simulation time 2325489779 ps
CPU time 74.97 seconds
Started Mar 14 12:58:46 PM PDT 24
Finished Mar 14 01:00:01 PM PDT 24
Peak memory 214680 kb
Host smart-c1dececd-ca77-4621-82be-2c4d0705bed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775564533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.775564533
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.422909045
Short name T331
Test name
Test status
Simulation time 438995104 ps
CPU time 8.56 seconds
Started Mar 14 12:58:42 PM PDT 24
Finished Mar 14 12:58:51 PM PDT 24
Peak memory 214728 kb
Host smart-10cd3e26-903a-44ff-85d9-3d97f8cad316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=422909045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.422909045
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.569138365
Short name T551
Test name
Test status
Simulation time 244559233 ps
CPU time 3.02 seconds
Started Mar 14 12:58:40 PM PDT 24
Finished Mar 14 12:58:43 PM PDT 24
Peak memory 209756 kb
Host smart-279a44bb-67ba-4884-b396-b6e94ad18302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=569138365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.569138365
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.1865371108
Short name T552
Test name
Test status
Simulation time 69261243 ps
CPU time 2.62 seconds
Started Mar 14 12:58:43 PM PDT 24
Finished Mar 14 12:58:45 PM PDT 24
Peak memory 210124 kb
Host smart-bd99794c-aab4-45ad-9d63-365f3c791672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1865371108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.1865371108
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.1838255489
Short name T270
Test name
Test status
Simulation time 586961761 ps
CPU time 4.92 seconds
Started Mar 14 12:58:42 PM PDT 24
Finished Mar 14 12:58:47 PM PDT 24
Peak memory 207068 kb
Host smart-c7a46d5c-1ff0-46e5-8fe8-8b34f4697c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838255489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.1838255489
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.3805413499
Short name T357
Test name
Test status
Simulation time 126934062 ps
CPU time 4.95 seconds
Started Mar 14 12:58:42 PM PDT 24
Finished Mar 14 12:58:47 PM PDT 24
Peak memory 208800 kb
Host smart-8067cb84-68ff-4f50-990a-a398d87efec8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3805413499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.3805413499
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.2823515168
Short name T787
Test name
Test status
Simulation time 768089456 ps
CPU time 8.14 seconds
Started Mar 14 12:58:42 PM PDT 24
Finished Mar 14 12:58:50 PM PDT 24
Peak memory 208976 kb
Host smart-995047cc-e86d-4d98-8b0f-e01524a02662
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823515168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.2823515168
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.196394352
Short name T210
Test name
Test status
Simulation time 93378154 ps
CPU time 2.48 seconds
Started Mar 14 12:58:45 PM PDT 24
Finished Mar 14 12:58:47 PM PDT 24
Peak memory 207064 kb
Host smart-9caa8d01-8678-4948-a99d-ce5a177e9aea
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=196394352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.196394352
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.3341218576
Short name T79
Test name
Test status
Simulation time 1149698893 ps
CPU time 14.54 seconds
Started Mar 14 12:58:44 PM PDT 24
Finished Mar 14 12:58:58 PM PDT 24
Peak memory 218572 kb
Host smart-92aaa919-5660-4fe5-8c0c-84c5a96721e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341218576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.3341218576
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.921383825
Short name T412
Test name
Test status
Simulation time 67655886 ps
CPU time 3.25 seconds
Started Mar 14 12:58:42 PM PDT 24
Finished Mar 14 12:58:45 PM PDT 24
Peak memory 208644 kb
Host smart-cb154d64-019e-4937-9cc6-03f3d249a950
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921383825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.921383825
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.3368431648
Short name T813
Test name
Test status
Simulation time 4776179923 ps
CPU time 43.12 seconds
Started Mar 14 12:58:45 PM PDT 24
Finished Mar 14 12:59:28 PM PDT 24
Peak memory 222068 kb
Host smart-d02055ec-691b-4d7e-b95c-fcc6dc7cb553
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368431648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.3368431648
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.2231691472
Short name T273
Test name
Test status
Simulation time 163960215 ps
CPU time 2.84 seconds
Started Mar 14 12:58:40 PM PDT 24
Finished Mar 14 12:58:43 PM PDT 24
Peak memory 214548 kb
Host smart-5a94c640-508b-44bf-b1e8-9d4932edddcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2231691472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.2231691472
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.3717961134
Short name T60
Test name
Test status
Simulation time 47377139 ps
CPU time 2.46 seconds
Started Mar 14 12:58:44 PM PDT 24
Finished Mar 14 12:58:47 PM PDT 24
Peak memory 210248 kb
Host smart-27f7eaa3-f355-44a6-ada5-95742b11667e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717961134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.3717961134
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.354135414
Short name T817
Test name
Test status
Simulation time 96363027 ps
CPU time 0.91 seconds
Started Mar 14 12:58:48 PM PDT 24
Finished Mar 14 12:58:49 PM PDT 24
Peak memory 206332 kb
Host smart-bdca33bd-a505-457b-9188-3e3893dbbadd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354135414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.354135414
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.4260938356
Short name T296
Test name
Test status
Simulation time 289764953 ps
CPU time 4.45 seconds
Started Mar 14 12:58:43 PM PDT 24
Finished Mar 14 12:58:48 PM PDT 24
Peak memory 214524 kb
Host smart-df5a116c-0a68-46ca-bb76-42b7df91a898
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4260938356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.4260938356
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.3830785385
Short name T639
Test name
Test status
Simulation time 2256953552 ps
CPU time 7.95 seconds
Started Mar 14 12:58:47 PM PDT 24
Finished Mar 14 12:58:55 PM PDT 24
Peak memory 221368 kb
Host smart-4a604c35-4587-4719-8e0b-05f5b0430f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3830785385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.3830785385
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.3970244224
Short name T848
Test name
Test status
Simulation time 223287675 ps
CPU time 4.23 seconds
Started Mar 14 12:58:42 PM PDT 24
Finished Mar 14 12:58:47 PM PDT 24
Peak memory 214588 kb
Host smart-0fa8f532-2002-4b77-92ae-9cdd81234e59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970244224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.3970244224
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.2300814220
Short name T504
Test name
Test status
Simulation time 300244913 ps
CPU time 2.8 seconds
Started Mar 14 12:58:47 PM PDT 24
Finished Mar 14 12:58:50 PM PDT 24
Peak memory 215004 kb
Host smart-ce96afd4-cb01-4d71-95fd-e03c425552ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300814220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.2300814220
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.1615013287
Short name T528
Test name
Test status
Simulation time 1368311621 ps
CPU time 9.4 seconds
Started Mar 14 12:58:44 PM PDT 24
Finished Mar 14 12:58:54 PM PDT 24
Peak memory 208780 kb
Host smart-af56a61c-f618-4fe5-8600-7d18535047e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1615013287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.1615013287
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.3310902291
Short name T800
Test name
Test status
Simulation time 183630295 ps
CPU time 2.88 seconds
Started Mar 14 12:58:45 PM PDT 24
Finished Mar 14 12:58:48 PM PDT 24
Peak memory 207640 kb
Host smart-082559b2-5036-47ab-909c-540df8eb43f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310902291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.3310902291
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.2528899080
Short name T379
Test name
Test status
Simulation time 54178125 ps
CPU time 2.9 seconds
Started Mar 14 12:58:41 PM PDT 24
Finished Mar 14 12:58:44 PM PDT 24
Peak memory 207132 kb
Host smart-4039b17e-43c4-4b18-9cbe-20c165d5617b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2528899080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.2528899080
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.1977525830
Short name T131
Test name
Test status
Simulation time 263099593 ps
CPU time 3.46 seconds
Started Mar 14 12:58:45 PM PDT 24
Finished Mar 14 12:58:49 PM PDT 24
Peak memory 207132 kb
Host smart-23940e7b-b869-458b-9e9d-99cea2e19250
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977525830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.1977525830
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.3643057795
Short name T481
Test name
Test status
Simulation time 383731183 ps
CPU time 5.79 seconds
Started Mar 14 12:58:45 PM PDT 24
Finished Mar 14 12:58:51 PM PDT 24
Peak memory 209064 kb
Host smart-6dd57a44-9043-48cd-a37c-885636c7eedf
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643057795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.3643057795
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.3131689140
Short name T810
Test name
Test status
Simulation time 318044359 ps
CPU time 6.07 seconds
Started Mar 14 12:58:43 PM PDT 24
Finished Mar 14 12:58:49 PM PDT 24
Peak memory 209044 kb
Host smart-1692a403-24f8-4e32-939b-43291dfd123e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3131689140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.3131689140
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.893858381
Short name T622
Test name
Test status
Simulation time 70347473 ps
CPU time 1.76 seconds
Started Mar 14 12:58:45 PM PDT 24
Finished Mar 14 12:58:47 PM PDT 24
Peak memory 206828 kb
Host smart-b3e33db0-698e-416e-8a02-63f5c260555e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=893858381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.893858381
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.4136605073
Short name T73
Test name
Test status
Simulation time 1494626741 ps
CPU time 49.62 seconds
Started Mar 14 12:58:45 PM PDT 24
Finished Mar 14 12:59:35 PM PDT 24
Peak memory 221604 kb
Host smart-7bc035e1-93d5-4c63-a5a8-0ae41ee6a523
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136605073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.4136605073
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_stress_all_with_rand_reset.1815697887
Short name T781
Test name
Test status
Simulation time 1089180095 ps
CPU time 20.39 seconds
Started Mar 14 12:58:42 PM PDT 24
Finished Mar 14 12:59:02 PM PDT 24
Peak memory 222984 kb
Host smart-db80feab-193d-456a-95b8-a305bf6a5f78
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815697887 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all_with_rand_reset.1815697887
Directory /workspace/38.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.3300099509
Short name T336
Test name
Test status
Simulation time 564423312 ps
CPU time 12.6 seconds
Started Mar 14 12:58:43 PM PDT 24
Finished Mar 14 12:58:56 PM PDT 24
Peak memory 214560 kb
Host smart-3cb3d451-5c6a-4428-a2f8-ae71b67a83e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3300099509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.3300099509
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.3211552817
Short name T512
Test name
Test status
Simulation time 576497093 ps
CPU time 2.27 seconds
Started Mar 14 12:58:42 PM PDT 24
Finished Mar 14 12:58:44 PM PDT 24
Peak memory 210544 kb
Host smart-491ed420-15e6-4b14-8feb-323fe25092a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3211552817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.3211552817
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.277054538
Short name T732
Test name
Test status
Simulation time 10455671 ps
CPU time 0.89 seconds
Started Mar 14 12:58:59 PM PDT 24
Finished Mar 14 12:59:00 PM PDT 24
Peak memory 206280 kb
Host smart-27a67565-2711-4616-ae16-4ddeb30de818
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277054538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.277054538
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.3775439185
Short name T401
Test name
Test status
Simulation time 50884984 ps
CPU time 3.92 seconds
Started Mar 14 12:58:47 PM PDT 24
Finished Mar 14 12:58:51 PM PDT 24
Peak memory 215220 kb
Host smart-c5316095-5b2f-4aa3-8acb-be2e7cc8fcec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3775439185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.3775439185
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.1162036631
Short name T47
Test name
Test status
Simulation time 53941590 ps
CPU time 2.84 seconds
Started Mar 14 12:58:42 PM PDT 24
Finished Mar 14 12:58:45 PM PDT 24
Peak memory 209740 kb
Host smart-37fe11a0-7c44-49b8-9b4a-bfa4ebc7bd85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162036631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.1162036631
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.1046944643
Short name T362
Test name
Test status
Simulation time 223542574 ps
CPU time 5.62 seconds
Started Mar 14 12:58:43 PM PDT 24
Finished Mar 14 12:58:49 PM PDT 24
Peak memory 214632 kb
Host smart-3dbf85c7-9438-4a8a-977e-9b1c9d38afca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1046944643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.1046944643
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_random.650848399
Short name T882
Test name
Test status
Simulation time 86666551 ps
CPU time 3.3 seconds
Started Mar 14 12:58:41 PM PDT 24
Finished Mar 14 12:58:45 PM PDT 24
Peak memory 207908 kb
Host smart-7cad8084-ce51-430e-b2d8-a58802945376
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650848399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.650848399
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.1040855664
Short name T557
Test name
Test status
Simulation time 199553337 ps
CPU time 2.86 seconds
Started Mar 14 12:58:44 PM PDT 24
Finished Mar 14 12:58:47 PM PDT 24
Peak memory 207024 kb
Host smart-1c5fc77f-1db0-43e8-abcc-d7a4e9674781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040855664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.1040855664
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.2066341436
Short name T779
Test name
Test status
Simulation time 591357814 ps
CPU time 15.12 seconds
Started Mar 14 12:58:46 PM PDT 24
Finished Mar 14 12:59:01 PM PDT 24
Peak memory 208240 kb
Host smart-e3ba405a-ff22-47b2-8c75-563c27c15572
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2066341436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.2066341436
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.3107727678
Short name T660
Test name
Test status
Simulation time 244433138 ps
CPU time 3.18 seconds
Started Mar 14 12:58:45 PM PDT 24
Finished Mar 14 12:58:48 PM PDT 24
Peak memory 209104 kb
Host smart-dcffbc41-18df-4017-a004-4698c8fdffb8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3107727678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.3107727678
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.453090265
Short name T614
Test name
Test status
Simulation time 659451367 ps
CPU time 2.9 seconds
Started Mar 14 12:58:46 PM PDT 24
Finished Mar 14 12:58:49 PM PDT 24
Peak memory 207056 kb
Host smart-e276d6fb-503c-41bc-b59e-8fe6623b004f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453090265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.453090265
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.1732956086
Short name T745
Test name
Test status
Simulation time 138743322 ps
CPU time 4.47 seconds
Started Mar 14 12:58:56 PM PDT 24
Finished Mar 14 12:59:00 PM PDT 24
Peak memory 214548 kb
Host smart-941e79c0-c020-4a75-97e0-d51bfdaf3dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1732956086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.1732956086
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.1481485801
Short name T84
Test name
Test status
Simulation time 1250460668 ps
CPU time 3.49 seconds
Started Mar 14 12:58:43 PM PDT 24
Finished Mar 14 12:58:47 PM PDT 24
Peak memory 207036 kb
Host smart-7ac4c3d9-ea83-4d17-b630-b7ee3cff632a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1481485801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.1481485801
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.3742051575
Short name T333
Test name
Test status
Simulation time 22164398613 ps
CPU time 138.37 seconds
Started Mar 14 12:58:58 PM PDT 24
Finished Mar 14 01:01:16 PM PDT 24
Peak memory 215332 kb
Host smart-20eb60f8-3b2a-499c-a73d-893b335aca82
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742051575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.3742051575
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.3606762105
Short name T355
Test name
Test status
Simulation time 4955395356 ps
CPU time 72.63 seconds
Started Mar 14 12:58:44 PM PDT 24
Finished Mar 14 12:59:57 PM PDT 24
Peak memory 209944 kb
Host smart-ff2032fe-8093-46d4-93a3-9e7ac0942388
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3606762105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.3606762105
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.2043732567
Short name T844
Test name
Test status
Simulation time 67041976 ps
CPU time 2.96 seconds
Started Mar 14 12:58:56 PM PDT 24
Finished Mar 14 12:58:59 PM PDT 24
Peak memory 210540 kb
Host smart-84c5e60f-9d6f-4017-a590-94e949394e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043732567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.2043732567
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.2913209638
Short name T493
Test name
Test status
Simulation time 49439368 ps
CPU time 1.03 seconds
Started Mar 14 12:56:00 PM PDT 24
Finished Mar 14 12:56:01 PM PDT 24
Peak memory 206360 kb
Host smart-772c5163-3d42-4e28-b743-c223334fa830
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2913209638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.2913209638
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.3420234760
Short name T26
Test name
Test status
Simulation time 150640087 ps
CPU time 3.48 seconds
Started Mar 14 12:56:00 PM PDT 24
Finished Mar 14 12:56:04 PM PDT 24
Peak memory 221952 kb
Host smart-a499c79a-8d36-4f59-a32c-5236f4c1a1ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420234760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.3420234760
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.700826603
Short name T459
Test name
Test status
Simulation time 231246343 ps
CPU time 2.47 seconds
Started Mar 14 12:55:59 PM PDT 24
Finished Mar 14 12:56:02 PM PDT 24
Peak memory 210136 kb
Host smart-fe92a1ed-eb15-4d7b-b1e6-346c1a0e4766
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=700826603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.700826603
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.4099272008
Short name T83
Test name
Test status
Simulation time 287697425 ps
CPU time 9.1 seconds
Started Mar 14 12:55:58 PM PDT 24
Finished Mar 14 12:56:07 PM PDT 24
Peak memory 214696 kb
Host smart-475ffde6-2ea1-44b5-a296-2b9fa0bdf9ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4099272008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.4099272008
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.1268598729
Short name T687
Test name
Test status
Simulation time 1164526446 ps
CPU time 11.38 seconds
Started Mar 14 12:56:00 PM PDT 24
Finished Mar 14 12:56:12 PM PDT 24
Peak memory 214500 kb
Host smart-0fc589ab-2f3c-4fd3-aa50-89049b7b6752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268598729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.1268598729
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.2993831679
Short name T223
Test name
Test status
Simulation time 34398515 ps
CPU time 2.6 seconds
Started Mar 14 12:55:58 PM PDT 24
Finished Mar 14 12:56:01 PM PDT 24
Peak memory 219732 kb
Host smart-103c766b-a49e-41de-b34d-79b8d9925d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2993831679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.2993831679
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.2344265941
Short name T751
Test name
Test status
Simulation time 435886410 ps
CPU time 10.06 seconds
Started Mar 14 12:55:47 PM PDT 24
Finished Mar 14 12:55:57 PM PDT 24
Peak memory 214692 kb
Host smart-121eec33-17a8-4586-81e1-5d64326e34e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344265941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.2344265941
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sideload.2428764622
Short name T593
Test name
Test status
Simulation time 1791958020 ps
CPU time 7.59 seconds
Started Mar 14 12:55:48 PM PDT 24
Finished Mar 14 12:55:56 PM PDT 24
Peak memory 208152 kb
Host smart-b0191b72-a1d0-4d6b-80db-e0616d1a496c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428764622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.2428764622
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.3497896554
Short name T727
Test name
Test status
Simulation time 71859490 ps
CPU time 3.09 seconds
Started Mar 14 12:55:48 PM PDT 24
Finished Mar 14 12:55:51 PM PDT 24
Peak memory 208200 kb
Host smart-87cc89e2-50a3-4b19-9bea-7bf7a40163b8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497896554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.3497896554
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.3214465696
Short name T541
Test name
Test status
Simulation time 98906777 ps
CPU time 2.83 seconds
Started Mar 14 12:55:47 PM PDT 24
Finished Mar 14 12:55:50 PM PDT 24
Peak memory 207828 kb
Host smart-b7d6ff8d-2b59-4264-9aad-363a5c0f0f4b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214465696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.3214465696
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.3139515060
Short name T722
Test name
Test status
Simulation time 54400228 ps
CPU time 2.94 seconds
Started Mar 14 12:55:48 PM PDT 24
Finished Mar 14 12:55:51 PM PDT 24
Peak memory 208288 kb
Host smart-59e96096-a981-4658-a0b2-719bc135b654
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139515060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.3139515060
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.1554659022
Short name T77
Test name
Test status
Simulation time 57471275 ps
CPU time 2.57 seconds
Started Mar 14 12:56:00 PM PDT 24
Finished Mar 14 12:56:02 PM PDT 24
Peak memory 215808 kb
Host smart-8b5899f7-0b46-43f6-88b0-d107f4edc5db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554659022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.1554659022
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.3260326028
Short name T845
Test name
Test status
Simulation time 199044988 ps
CPU time 2.59 seconds
Started Mar 14 12:55:47 PM PDT 24
Finished Mar 14 12:55:50 PM PDT 24
Peak memory 206836 kb
Host smart-93040536-30b3-45c9-ae78-abbe02106eaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260326028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.3260326028
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.3671068052
Short name T860
Test name
Test status
Simulation time 6640634785 ps
CPU time 48.59 seconds
Started Mar 14 12:55:58 PM PDT 24
Finished Mar 14 12:56:47 PM PDT 24
Peak memory 216180 kb
Host smart-0c2b75f8-2a87-4412-984d-3a5ac1078e6e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3671068052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.3671068052
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.202468693
Short name T23
Test name
Test status
Simulation time 2990382388 ps
CPU time 42.94 seconds
Started Mar 14 12:55:58 PM PDT 24
Finished Mar 14 12:56:41 PM PDT 24
Peak memory 208772 kb
Host smart-539237bc-753c-44e1-8ed4-ee8c79f9e0ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202468693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.202468693
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.330471051
Short name T163
Test name
Test status
Simulation time 170008007 ps
CPU time 4.13 seconds
Started Mar 14 12:55:59 PM PDT 24
Finished Mar 14 12:56:03 PM PDT 24
Peak memory 210600 kb
Host smart-286723f7-00c7-408f-af12-cc566569d4d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330471051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.330471051
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.1204666034
Short name T450
Test name
Test status
Simulation time 62938831 ps
CPU time 0.98 seconds
Started Mar 14 12:58:57 PM PDT 24
Finished Mar 14 12:58:58 PM PDT 24
Peak memory 206408 kb
Host smart-9c64b23c-26e7-450a-8cf6-c62002ecc804
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1204666034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.1204666034
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.1075953115
Short name T393
Test name
Test status
Simulation time 354259686 ps
CPU time 5.75 seconds
Started Mar 14 12:58:56 PM PDT 24
Finished Mar 14 12:59:01 PM PDT 24
Peak memory 214612 kb
Host smart-4a9dd248-22e4-4b57-bb7b-eec6f11f0ff6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1075953115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.1075953115
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.3727617214
Short name T176
Test name
Test status
Simulation time 95543646 ps
CPU time 4.32 seconds
Started Mar 14 12:58:59 PM PDT 24
Finished Mar 14 12:59:03 PM PDT 24
Peak memory 218336 kb
Host smart-adb07058-2d0c-49f2-b47a-aa60d4ac7720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3727617214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.3727617214
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.3084613550
Short name T854
Test name
Test status
Simulation time 531687013 ps
CPU time 16.88 seconds
Started Mar 14 12:59:02 PM PDT 24
Finished Mar 14 12:59:19 PM PDT 24
Peak memory 208536 kb
Host smart-76e95e6a-7df8-4c8d-b330-2354bfe37fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3084613550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.3084613550
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.4026051690
Short name T24
Test name
Test status
Simulation time 553483064 ps
CPU time 9.01 seconds
Started Mar 14 12:58:59 PM PDT 24
Finished Mar 14 12:59:08 PM PDT 24
Peak memory 222712 kb
Host smart-3ba7b0cd-ae8e-4b53-be7e-29dcf617ea48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4026051690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.4026051690
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.4262806966
Short name T793
Test name
Test status
Simulation time 260607197 ps
CPU time 3.53 seconds
Started Mar 14 12:59:02 PM PDT 24
Finished Mar 14 12:59:05 PM PDT 24
Peak memory 209488 kb
Host smart-afb193d6-2560-4b8f-8046-0754a25c5e52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4262806966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.4262806966
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.2995430437
Short name T626
Test name
Test status
Simulation time 261911338 ps
CPU time 7.57 seconds
Started Mar 14 12:59:01 PM PDT 24
Finished Mar 14 12:59:08 PM PDT 24
Peak memory 218532 kb
Host smart-d80c98be-29f5-4170-8e4a-287fa0820ed8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995430437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.2995430437
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.2712687491
Short name T783
Test name
Test status
Simulation time 201746939 ps
CPU time 5.63 seconds
Started Mar 14 12:58:57 PM PDT 24
Finished Mar 14 12:59:03 PM PDT 24
Peak memory 208216 kb
Host smart-5884139d-8f5e-4c7d-9249-98dd9b66bac8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712687491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.2712687491
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.2261994640
Short name T699
Test name
Test status
Simulation time 134194295 ps
CPU time 4.27 seconds
Started Mar 14 12:58:58 PM PDT 24
Finished Mar 14 12:59:03 PM PDT 24
Peak memory 208132 kb
Host smart-a949d37b-4f48-4d6b-b1d3-303fc9e6fbef
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2261994640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.2261994640
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.3082736701
Short name T693
Test name
Test status
Simulation time 639633429 ps
CPU time 7.31 seconds
Started Mar 14 12:58:59 PM PDT 24
Finished Mar 14 12:59:07 PM PDT 24
Peak memory 209364 kb
Host smart-1fab2d71-7c6d-4a09-8411-df07b053050e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3082736701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.3082736701
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.3490290722
Short name T694
Test name
Test status
Simulation time 39704532 ps
CPU time 2.62 seconds
Started Mar 14 12:59:02 PM PDT 24
Finished Mar 14 12:59:05 PM PDT 24
Peak memory 208964 kb
Host smart-c5729dac-e561-432e-9793-39620bad72d6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490290722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.3490290722
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.1504091212
Short name T309
Test name
Test status
Simulation time 33526209 ps
CPU time 2.4 seconds
Started Mar 14 12:59:02 PM PDT 24
Finished Mar 14 12:59:04 PM PDT 24
Peak memory 209456 kb
Host smart-e4ae84cd-363a-48f9-af47-027fb4eb3a39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504091212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.1504091212
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.1642627229
Short name T530
Test name
Test status
Simulation time 97374740 ps
CPU time 2.01 seconds
Started Mar 14 12:58:59 PM PDT 24
Finished Mar 14 12:59:01 PM PDT 24
Peak memory 208764 kb
Host smart-cee6e6f7-14ac-4ece-9137-faa80e0e99b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642627229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.1642627229
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.1841763703
Short name T218
Test name
Test status
Simulation time 255042267 ps
CPU time 10.54 seconds
Started Mar 14 12:58:57 PM PDT 24
Finished Mar 14 12:59:08 PM PDT 24
Peak memory 215608 kb
Host smart-52bcd800-89c1-4bb1-a3f6-9f4c85339399
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841763703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.1841763703
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_stress_all_with_rand_reset.1997713238
Short name T179
Test name
Test status
Simulation time 361467654 ps
CPU time 15.55 seconds
Started Mar 14 12:58:57 PM PDT 24
Finished Mar 14 12:59:13 PM PDT 24
Peak memory 222820 kb
Host smart-bf79002f-4bb6-44a7-821c-6e01f5621f1f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1997713238 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all_with_rand_reset.1997713238
Directory /workspace/40.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.4025260865
Short name T749
Test name
Test status
Simulation time 41672458 ps
CPU time 2.89 seconds
Started Mar 14 12:58:58 PM PDT 24
Finished Mar 14 12:59:01 PM PDT 24
Peak memory 214660 kb
Host smart-40ff6cbc-bd70-4a2e-9c9b-73182b73ed3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025260865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.4025260865
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.947670346
Short name T671
Test name
Test status
Simulation time 503243343 ps
CPU time 2.97 seconds
Started Mar 14 12:58:57 PM PDT 24
Finished Mar 14 12:59:00 PM PDT 24
Peak memory 210040 kb
Host smart-150b57a5-5404-4fe3-b8ff-f837065e685f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947670346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.947670346
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.176149775
Short name T451
Test name
Test status
Simulation time 194335365 ps
CPU time 0.86 seconds
Started Mar 14 12:58:58 PM PDT 24
Finished Mar 14 12:58:59 PM PDT 24
Peak memory 206248 kb
Host smart-bdb8f409-f233-4f74-b97a-177adfdb746b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176149775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.176149775
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.354634987
Short name T281
Test name
Test status
Simulation time 392355739 ps
CPU time 4.76 seconds
Started Mar 14 12:58:58 PM PDT 24
Finished Mar 14 12:59:03 PM PDT 24
Peak memory 214620 kb
Host smart-404d0359-1427-4a6f-ab30-b8248b40253a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=354634987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.354634987
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.4289214687
Short name T824
Test name
Test status
Simulation time 362973882 ps
CPU time 4.31 seconds
Started Mar 14 12:58:57 PM PDT 24
Finished Mar 14 12:59:01 PM PDT 24
Peak memory 210228 kb
Host smart-324cdb1b-e47e-4a1f-8032-cd4ed9d50622
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289214687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.4289214687
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.2250500539
Short name T873
Test name
Test status
Simulation time 2710844247 ps
CPU time 34.89 seconds
Started Mar 14 12:59:02 PM PDT 24
Finished Mar 14 12:59:37 PM PDT 24
Peak memory 209736 kb
Host smart-1e370f3e-546c-49f2-b6a4-caa714490b4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250500539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.2250500539
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.1837811174
Short name T892
Test name
Test status
Simulation time 336349785 ps
CPU time 6.03 seconds
Started Mar 14 12:59:00 PM PDT 24
Finished Mar 14 12:59:07 PM PDT 24
Peak memory 222700 kb
Host smart-ed5e06c3-c205-4c47-be59-af07d664c822
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1837811174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.1837811174
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.3773194599
Short name T646
Test name
Test status
Simulation time 24453216 ps
CPU time 1.72 seconds
Started Mar 14 12:58:58 PM PDT 24
Finished Mar 14 12:58:59 PM PDT 24
Peak memory 214536 kb
Host smart-10cf9ef1-5c49-4c48-9e7b-b907fcd7b0c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773194599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.3773194599
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.563769944
Short name T631
Test name
Test status
Simulation time 153349168 ps
CPU time 6.2 seconds
Started Mar 14 12:59:01 PM PDT 24
Finished Mar 14 12:59:07 PM PDT 24
Peak memory 208064 kb
Host smart-7250f426-3e2d-487a-9b62-8d2a85efb80f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563769944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.563769944
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.3478989619
Short name T863
Test name
Test status
Simulation time 211282617 ps
CPU time 2.92 seconds
Started Mar 14 12:58:57 PM PDT 24
Finished Mar 14 12:59:00 PM PDT 24
Peak memory 208944 kb
Host smart-09e93294-21f7-4794-b7d4-e2dde1769a54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478989619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.3478989619
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.1147022397
Short name T312
Test name
Test status
Simulation time 106386979 ps
CPU time 2.97 seconds
Started Mar 14 12:58:57 PM PDT 24
Finished Mar 14 12:59:00 PM PDT 24
Peak memory 207760 kb
Host smart-ada6101e-2354-4071-ba30-8b0fd723770e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1147022397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.1147022397
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.3278776025
Short name T509
Test name
Test status
Simulation time 552801733 ps
CPU time 20.34 seconds
Started Mar 14 12:58:58 PM PDT 24
Finished Mar 14 12:59:18 PM PDT 24
Peak memory 208952 kb
Host smart-79fcb301-59cf-4eb8-8f39-23bebde2399c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3278776025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.3278776025
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.4129554253
Short name T433
Test name
Test status
Simulation time 1965451007 ps
CPU time 19.01 seconds
Started Mar 14 12:58:59 PM PDT 24
Finished Mar 14 12:59:18 PM PDT 24
Peak memory 208644 kb
Host smart-858e6572-780a-4dbf-b33e-b9d671dd733d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129554253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.4129554253
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.2973107306
Short name T769
Test name
Test status
Simulation time 76054177 ps
CPU time 2.77 seconds
Started Mar 14 12:59:00 PM PDT 24
Finished Mar 14 12:59:03 PM PDT 24
Peak memory 218296 kb
Host smart-33c4df16-b183-4099-8d97-954487afc7b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973107306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.2973107306
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.3771764740
Short name T721
Test name
Test status
Simulation time 632346070 ps
CPU time 19.13 seconds
Started Mar 14 12:59:01 PM PDT 24
Finished Mar 14 12:59:20 PM PDT 24
Peak memory 208592 kb
Host smart-c8e5fc0c-93a9-434e-8aed-71a6d8376aaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771764740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.3771764740
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.3224044160
Short name T667
Test name
Test status
Simulation time 19180852515 ps
CPU time 116.23 seconds
Started Mar 14 12:59:01 PM PDT 24
Finished Mar 14 01:00:58 PM PDT 24
Peak memory 222824 kb
Host smart-8bd6557c-f229-4be6-a60c-b9add3dfaaff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224044160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.3224044160
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_stress_all_with_rand_reset.3777291381
Short name T790
Test name
Test status
Simulation time 682815086 ps
CPU time 20.65 seconds
Started Mar 14 12:58:56 PM PDT 24
Finished Mar 14 12:59:17 PM PDT 24
Peak memory 222872 kb
Host smart-78c117ea-4b29-4c57-b076-a45a6ef2137b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3777291381 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all_with_rand_reset.3777291381
Directory /workspace/41.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.457042801
Short name T739
Test name
Test status
Simulation time 83054518 ps
CPU time 4.3 seconds
Started Mar 14 12:58:58 PM PDT 24
Finished Mar 14 12:59:03 PM PDT 24
Peak memory 214636 kb
Host smart-bcb1433b-ba42-4eca-858a-eb910a22851b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=457042801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.457042801
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.3926888751
Short name T366
Test name
Test status
Simulation time 173257998 ps
CPU time 3.36 seconds
Started Mar 14 12:59:00 PM PDT 24
Finished Mar 14 12:59:03 PM PDT 24
Peak memory 210716 kb
Host smart-7b8fb752-7fb9-46e2-a027-c55cb3b7e088
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926888751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.3926888751
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.1071093981
Short name T789
Test name
Test status
Simulation time 37618301 ps
CPU time 0.82 seconds
Started Mar 14 12:59:00 PM PDT 24
Finished Mar 14 12:59:00 PM PDT 24
Peak memory 206200 kb
Host smart-16b37040-f81e-4bbf-9ed4-ee75ff660a92
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1071093981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.1071093981
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.2489836097
Short name T318
Test name
Test status
Simulation time 444918493 ps
CPU time 7.04 seconds
Started Mar 14 12:58:58 PM PDT 24
Finished Mar 14 12:59:05 PM PDT 24
Peak memory 215320 kb
Host smart-c4e8b55f-0dc3-444d-9a37-9a7d07893b51
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2489836097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.2489836097
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.4081689889
Short name T507
Test name
Test status
Simulation time 533144737 ps
CPU time 5.16 seconds
Started Mar 14 12:58:57 PM PDT 24
Finished Mar 14 12:59:02 PM PDT 24
Peak memory 219376 kb
Host smart-9786e088-8444-4757-acaf-545d323a8789
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081689889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.4081689889
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.217636379
Short name T697
Test name
Test status
Simulation time 1015521140 ps
CPU time 2.6 seconds
Started Mar 14 12:58:57 PM PDT 24
Finished Mar 14 12:58:59 PM PDT 24
Peak memory 207408 kb
Host smart-842cffc5-c04c-472a-837a-e264d23c1bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=217636379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.217636379
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.1135924246
Short name T88
Test name
Test status
Simulation time 831637003 ps
CPU time 5.63 seconds
Started Mar 14 12:58:57 PM PDT 24
Finished Mar 14 12:59:03 PM PDT 24
Peak memory 209736 kb
Host smart-b8feaa29-1e73-4517-b6cb-a59e48285a05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135924246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.1135924246
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.3951731186
Short name T215
Test name
Test status
Simulation time 282161329 ps
CPU time 2.54 seconds
Started Mar 14 12:58:59 PM PDT 24
Finished Mar 14 12:59:02 PM PDT 24
Peak memory 209736 kb
Host smart-c7a15fef-cee7-4dcc-a1a7-3f0f79c99615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3951731186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.3951731186
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.615489623
Short name T606
Test name
Test status
Simulation time 394558319 ps
CPU time 4.59 seconds
Started Mar 14 12:58:59 PM PDT 24
Finished Mar 14 12:59:03 PM PDT 24
Peak memory 209220 kb
Host smart-baef75f2-4050-4a7f-8412-8759369cf935
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=615489623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.615489623
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.3008304890
Short name T248
Test name
Test status
Simulation time 165162632 ps
CPU time 4.54 seconds
Started Mar 14 12:58:57 PM PDT 24
Finished Mar 14 12:59:01 PM PDT 24
Peak memory 208648 kb
Host smart-fdceddb7-d76e-4927-92ca-0b836ef60ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3008304890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.3008304890
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.1255757787
Short name T516
Test name
Test status
Simulation time 3354604656 ps
CPU time 41.91 seconds
Started Mar 14 12:58:57 PM PDT 24
Finished Mar 14 12:59:39 PM PDT 24
Peak memory 208972 kb
Host smart-f507f897-7478-4fc0-a203-6cafb8d6449e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255757787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.1255757787
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.665756757
Short name T659
Test name
Test status
Simulation time 274472425 ps
CPU time 3.66 seconds
Started Mar 14 12:58:58 PM PDT 24
Finished Mar 14 12:59:02 PM PDT 24
Peak memory 206880 kb
Host smart-1d8e1902-c999-4fa7-a8c8-d76b37183f2e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665756757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.665756757
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.3163119506
Short name T497
Test name
Test status
Simulation time 35973546 ps
CPU time 1.69 seconds
Started Mar 14 12:58:57 PM PDT 24
Finished Mar 14 12:58:59 PM PDT 24
Peak memory 207116 kb
Host smart-1ed4bc09-7a1a-4f41-a1e1-4e04227e9e6a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3163119506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.3163119506
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.494204020
Short name T868
Test name
Test status
Simulation time 627049732 ps
CPU time 7.06 seconds
Started Mar 14 12:59:01 PM PDT 24
Finished Mar 14 12:59:09 PM PDT 24
Peak memory 215860 kb
Host smart-5fa1459b-acb9-4d28-a8c6-c8acadd5d5c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=494204020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.494204020
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.4178569258
Short name T406
Test name
Test status
Simulation time 1147462692 ps
CPU time 8.03 seconds
Started Mar 14 12:58:59 PM PDT 24
Finished Mar 14 12:59:07 PM PDT 24
Peak memory 208416 kb
Host smart-6d1d8e5c-33c5-4aee-956e-dd4dbc439ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4178569258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.4178569258
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.28603284
Short name T67
Test name
Test status
Simulation time 9794121469 ps
CPU time 20.83 seconds
Started Mar 14 12:58:59 PM PDT 24
Finished Mar 14 12:59:20 PM PDT 24
Peak memory 217300 kb
Host smart-c5bdef49-f65b-4b0b-b103-0db212274f37
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28603284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.28603284
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_stress_all_with_rand_reset.546253795
Short name T638
Test name
Test status
Simulation time 1708768806 ps
CPU time 18.03 seconds
Started Mar 14 12:59:02 PM PDT 24
Finished Mar 14 12:59:20 PM PDT 24
Peak memory 223000 kb
Host smart-8ad090a4-19f4-4f91-8987-88925fa9651f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=546253795 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all_with_rand_reset.546253795
Directory /workspace/42.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.2791270849
Short name T795
Test name
Test status
Simulation time 1168894063 ps
CPU time 4.78 seconds
Started Mar 14 12:59:01 PM PDT 24
Finished Mar 14 12:59:06 PM PDT 24
Peak memory 218588 kb
Host smart-fa459b7e-6c93-43e8-8c6f-059f8ee27946
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791270849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.2791270849
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.2226319988
Short name T99
Test name
Test status
Simulation time 36045134 ps
CPU time 0.87 seconds
Started Mar 14 12:59:08 PM PDT 24
Finished Mar 14 12:59:10 PM PDT 24
Peak memory 206276 kb
Host smart-d583c55d-eed6-4baf-af35-4f8fc7737bda
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226319988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.2226319988
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.1520683839
Short name T372
Test name
Test status
Simulation time 51368426 ps
CPU time 3.47 seconds
Started Mar 14 12:59:01 PM PDT 24
Finished Mar 14 12:59:04 PM PDT 24
Peak memory 214644 kb
Host smart-ccc0f44e-8d6d-4db7-993a-cbf55a517f43
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1520683839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.1520683839
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.1589054607
Short name T25
Test name
Test status
Simulation time 47427429 ps
CPU time 2.91 seconds
Started Mar 14 12:59:08 PM PDT 24
Finished Mar 14 12:59:11 PM PDT 24
Peak memory 222024 kb
Host smart-b70e7188-7667-4330-96dd-bf57fb8ce2ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1589054607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.1589054607
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.1941270845
Short name T676
Test name
Test status
Simulation time 119684997 ps
CPU time 2.22 seconds
Started Mar 14 12:59:01 PM PDT 24
Finished Mar 14 12:59:03 PM PDT 24
Peak memory 218652 kb
Host smart-a6dbd6b3-78c4-426c-a054-0e0f6c85a98a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941270845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.1941270845
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.4037394099
Short name T364
Test name
Test status
Simulation time 853705404 ps
CPU time 6.04 seconds
Started Mar 14 12:59:00 PM PDT 24
Finished Mar 14 12:59:06 PM PDT 24
Peak memory 209412 kb
Host smart-140c1bd2-f1a1-48f9-a551-458746a58873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037394099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.4037394099
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.2323694477
Short name T819
Test name
Test status
Simulation time 223893239 ps
CPU time 6.75 seconds
Started Mar 14 12:59:14 PM PDT 24
Finished Mar 14 12:59:22 PM PDT 24
Peak memory 222860 kb
Host smart-f7e1761e-9b43-40e5-a897-fd2f447307a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323694477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.2323694477
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.1673565152
Short name T52
Test name
Test status
Simulation time 76068752 ps
CPU time 2.86 seconds
Started Mar 14 12:59:00 PM PDT 24
Finished Mar 14 12:59:03 PM PDT 24
Peak memory 207644 kb
Host smart-656e1783-5003-47e9-a8aa-9223285934c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673565152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.1673565152
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.2054847626
Short name T807
Test name
Test status
Simulation time 1120925576 ps
CPU time 8.89 seconds
Started Mar 14 12:59:00 PM PDT 24
Finished Mar 14 12:59:09 PM PDT 24
Peak memory 208416 kb
Host smart-ba24bcb1-8cba-4fe4-bd3b-a42636645a88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054847626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.2054847626
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.1015008628
Short name T15
Test name
Test status
Simulation time 80740931 ps
CPU time 3.68 seconds
Started Mar 14 12:59:00 PM PDT 24
Finished Mar 14 12:59:03 PM PDT 24
Peak memory 208872 kb
Host smart-5df5bb67-a604-4396-96ba-8b6d4444f114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015008628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.1015008628
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.4257836773
Short name T610
Test name
Test status
Simulation time 391598145 ps
CPU time 3.73 seconds
Started Mar 14 12:58:59 PM PDT 24
Finished Mar 14 12:59:03 PM PDT 24
Peak memory 207124 kb
Host smart-ff42588a-ace9-4114-8a8f-bedcdaaa80f0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4257836773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.4257836773
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.1318430411
Short name T332
Test name
Test status
Simulation time 266743414 ps
CPU time 3.55 seconds
Started Mar 14 12:59:01 PM PDT 24
Finished Mar 14 12:59:05 PM PDT 24
Peak memory 207632 kb
Host smart-fca7efab-439d-4922-b7b8-7a32afc08504
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1318430411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.1318430411
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.2156621529
Short name T330
Test name
Test status
Simulation time 1615526207 ps
CPU time 7.44 seconds
Started Mar 14 12:59:01 PM PDT 24
Finished Mar 14 12:59:08 PM PDT 24
Peak memory 208596 kb
Host smart-767ab7e0-1ce5-4a33-965b-0584f10a9cbd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2156621529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.2156621529
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.2805202776
Short name T540
Test name
Test status
Simulation time 552285623 ps
CPU time 1.98 seconds
Started Mar 14 12:59:11 PM PDT 24
Finished Mar 14 12:59:14 PM PDT 24
Peak memory 222636 kb
Host smart-b5b01123-4fc2-43e7-8aea-a1bde4444631
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2805202776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.2805202776
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.3179128130
Short name T106
Test name
Test status
Simulation time 229958292 ps
CPU time 8.7 seconds
Started Mar 14 12:59:04 PM PDT 24
Finished Mar 14 12:59:13 PM PDT 24
Peak memory 208996 kb
Host smart-dc0df24f-2a8c-41c2-9f3f-62e00e897b58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3179128130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.3179128130
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.1100634593
Short name T857
Test name
Test status
Simulation time 413392930 ps
CPU time 5.24 seconds
Started Mar 14 12:58:59 PM PDT 24
Finished Mar 14 12:59:04 PM PDT 24
Peak memory 207792 kb
Host smart-73ffb807-b29c-4089-80ac-105e579bb0fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1100634593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.1100634593
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.2973825153
Short name T154
Test name
Test status
Simulation time 779553496 ps
CPU time 7.26 seconds
Started Mar 14 12:59:08 PM PDT 24
Finished Mar 14 12:59:15 PM PDT 24
Peak memory 210996 kb
Host smart-7d8206cf-8729-4652-ad32-948144a171a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2973825153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.2973825153
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.2379117837
Short name T761
Test name
Test status
Simulation time 23435282 ps
CPU time 1.03 seconds
Started Mar 14 12:59:12 PM PDT 24
Finished Mar 14 12:59:13 PM PDT 24
Peak memory 206372 kb
Host smart-a856d8d9-4953-4a2c-b678-1ace70bf2406
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379117837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.2379117837
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.3917550252
Short name T35
Test name
Test status
Simulation time 557062482 ps
CPU time 17.45 seconds
Started Mar 14 12:59:13 PM PDT 24
Finished Mar 14 12:59:30 PM PDT 24
Peak memory 221776 kb
Host smart-1c651f7a-cb2c-47ff-b7a9-80b953be9eca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3917550252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.3917550252
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.3497317416
Short name T329
Test name
Test status
Simulation time 91123861 ps
CPU time 1.87 seconds
Started Mar 14 12:59:10 PM PDT 24
Finished Mar 14 12:59:12 PM PDT 24
Peak memory 214580 kb
Host smart-43fc4251-b5ac-4de6-8149-f554b422ddbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497317416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.3497317416
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.3301640021
Short name T602
Test name
Test status
Simulation time 159768500 ps
CPU time 3.61 seconds
Started Mar 14 12:59:18 PM PDT 24
Finished Mar 14 12:59:21 PM PDT 24
Peak memory 209768 kb
Host smart-7b5f5aa1-1ed2-4373-9ac2-8f92ff332772
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301640021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.3301640021
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.541310579
Short name T87
Test name
Test status
Simulation time 2660411522 ps
CPU time 37.99 seconds
Started Mar 14 12:59:07 PM PDT 24
Finished Mar 14 12:59:45 PM PDT 24
Peak memory 222836 kb
Host smart-5dafb044-8619-44f2-8a16-9d1263e4c7fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541310579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.541310579
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.3977968511
Short name T756
Test name
Test status
Simulation time 48700057 ps
CPU time 3.39 seconds
Started Mar 14 12:59:08 PM PDT 24
Finished Mar 14 12:59:11 PM PDT 24
Peak memory 214580 kb
Host smart-6a9cccda-c95c-4fda-8e12-39a51e61e386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977968511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.3977968511
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.4117436312
Short name T286
Test name
Test status
Simulation time 637970026 ps
CPU time 4.55 seconds
Started Mar 14 12:59:07 PM PDT 24
Finished Mar 14 12:59:12 PM PDT 24
Peak memory 207196 kb
Host smart-1dd8a4f5-fdc3-4301-bc6a-c49b73cdf9c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4117436312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.4117436312
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.153612550
Short name T673
Test name
Test status
Simulation time 79435456 ps
CPU time 3.33 seconds
Started Mar 14 12:59:09 PM PDT 24
Finished Mar 14 12:59:13 PM PDT 24
Peak memory 208816 kb
Host smart-3cfd27ff-c565-49c8-8706-b659a30d978f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153612550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.153612550
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.2274971742
Short name T679
Test name
Test status
Simulation time 1326962505 ps
CPU time 9.62 seconds
Started Mar 14 12:59:10 PM PDT 24
Finished Mar 14 12:59:20 PM PDT 24
Peak memory 208068 kb
Host smart-2f7056ab-59fb-43d9-bbda-01078581d208
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274971742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.2274971742
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.558375521
Short name T668
Test name
Test status
Simulation time 334039527 ps
CPU time 3.31 seconds
Started Mar 14 12:59:11 PM PDT 24
Finished Mar 14 12:59:15 PM PDT 24
Peak memory 208848 kb
Host smart-a758b9f4-538b-4781-9884-bfb96b335547
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558375521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.558375521
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.1598213092
Short name T730
Test name
Test status
Simulation time 152678819 ps
CPU time 4.89 seconds
Started Mar 14 12:59:16 PM PDT 24
Finished Mar 14 12:59:21 PM PDT 24
Peak memory 207796 kb
Host smart-9929717c-7bfe-499b-89e5-f0f1f736e6a7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1598213092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.1598213092
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.9151230
Short name T578
Test name
Test status
Simulation time 5036742306 ps
CPU time 30.92 seconds
Started Mar 14 12:59:09 PM PDT 24
Finished Mar 14 12:59:41 PM PDT 24
Peak memory 214692 kb
Host smart-39ae6016-b95d-4a1a-8e05-81b38d33192e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=9151230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.9151230
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.3546489970
Short name T415
Test name
Test status
Simulation time 99094314 ps
CPU time 2.68 seconds
Started Mar 14 12:59:08 PM PDT 24
Finished Mar 14 12:59:11 PM PDT 24
Peak memory 207096 kb
Host smart-eb10c132-b13e-4a2a-a154-b15135e89253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546489970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.3546489970
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.508832536
Short name T310
Test name
Test status
Simulation time 1670862676 ps
CPU time 58.58 seconds
Started Mar 14 12:59:14 PM PDT 24
Finished Mar 14 01:00:14 PM PDT 24
Peak memory 215420 kb
Host smart-e8608879-0fa1-4abe-96a1-a63a8ca21bf1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508832536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.508832536
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_stress_all_with_rand_reset.448393284
Short name T625
Test name
Test status
Simulation time 418886132 ps
CPU time 8.61 seconds
Started Mar 14 12:59:11 PM PDT 24
Finished Mar 14 12:59:21 PM PDT 24
Peak memory 220440 kb
Host smart-dc1819d6-0272-429a-ba55-2095e8912a9e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448393284 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all_with_rand_reset.448393284
Directory /workspace/44.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.39285015
Short name T397
Test name
Test status
Simulation time 740360132 ps
CPU time 5.71 seconds
Started Mar 14 12:59:06 PM PDT 24
Finished Mar 14 12:59:12 PM PDT 24
Peak memory 209916 kb
Host smart-4bed1fce-1075-4ba0-8cc3-5262d573ede1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39285015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.39285015
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.806030413
Short name T511
Test name
Test status
Simulation time 141718848 ps
CPU time 3.49 seconds
Started Mar 14 12:59:08 PM PDT 24
Finished Mar 14 12:59:12 PM PDT 24
Peak memory 210240 kb
Host smart-109f37d6-2925-4d74-8c79-fea9322cbcaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=806030413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.806030413
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.2092758519
Short name T731
Test name
Test status
Simulation time 20997530 ps
CPU time 0.91 seconds
Started Mar 14 12:59:15 PM PDT 24
Finished Mar 14 12:59:17 PM PDT 24
Peak memory 206212 kb
Host smart-115133c6-a451-4c08-b40a-c49f4728b5f2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2092758519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.2092758519
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.1622786557
Short name T134
Test name
Test status
Simulation time 269356910 ps
CPU time 7.7 seconds
Started Mar 14 12:59:09 PM PDT 24
Finished Mar 14 12:59:17 PM PDT 24
Peak memory 214632 kb
Host smart-4da48ec3-af98-4f48-b3d6-48fc01606e15
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1622786557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.1622786557
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.2577603970
Short name T28
Test name
Test status
Simulation time 103704121 ps
CPU time 3.42 seconds
Started Mar 14 12:59:08 PM PDT 24
Finished Mar 14 12:59:12 PM PDT 24
Peak memory 219240 kb
Host smart-40cf6d88-cf77-4e85-b300-b921deb7bade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2577603970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.2577603970
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.2013544657
Short name T81
Test name
Test status
Simulation time 832835772 ps
CPU time 2.93 seconds
Started Mar 14 12:59:09 PM PDT 24
Finished Mar 14 12:59:12 PM PDT 24
Peak memory 214584 kb
Host smart-e81a9c83-7394-4ee5-a239-53b59f7eece0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013544657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.2013544657
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.3229396606
Short name T278
Test name
Test status
Simulation time 78066740 ps
CPU time 3.33 seconds
Started Mar 14 12:59:09 PM PDT 24
Finished Mar 14 12:59:12 PM PDT 24
Peak memory 222780 kb
Host smart-1d850b90-6569-4774-95fc-616389ba2f5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229396606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.3229396606
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.1958918464
Short name T233
Test name
Test status
Simulation time 283538223 ps
CPU time 4.6 seconds
Started Mar 14 12:59:16 PM PDT 24
Finished Mar 14 12:59:21 PM PDT 24
Peak memory 222732 kb
Host smart-ff3a3360-270f-448e-a8fb-4dfe7007fca7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958918464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.1958918464
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.1741293258
Short name T618
Test name
Test status
Simulation time 239817652 ps
CPU time 3.95 seconds
Started Mar 14 12:59:10 PM PDT 24
Finished Mar 14 12:59:14 PM PDT 24
Peak memory 208672 kb
Host smart-3140d2a0-c622-4cf3-93a4-75e2683f00ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1741293258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.1741293258
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.1930516635
Short name T603
Test name
Test status
Simulation time 160331479 ps
CPU time 2.71 seconds
Started Mar 14 12:59:15 PM PDT 24
Finished Mar 14 12:59:19 PM PDT 24
Peak memory 208424 kb
Host smart-34d5279c-d2ff-4e06-93ed-ef2841f9d849
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930516635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.1930516635
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.2363591295
Short name T661
Test name
Test status
Simulation time 7708153956 ps
CPU time 51.12 seconds
Started Mar 14 12:59:13 PM PDT 24
Finished Mar 14 01:00:05 PM PDT 24
Peak memory 209448 kb
Host smart-c017c924-2816-4f21-9f97-536902b36451
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2363591295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.2363591295
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.4098640890
Short name T470
Test name
Test status
Simulation time 143819100 ps
CPU time 3.57 seconds
Started Mar 14 12:59:15 PM PDT 24
Finished Mar 14 12:59:20 PM PDT 24
Peak memory 209088 kb
Host smart-6dff7f56-7ba1-4300-9514-9e17c716fa2d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4098640890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.4098640890
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.2033199635
Short name T351
Test name
Test status
Simulation time 198844766 ps
CPU time 7.96 seconds
Started Mar 14 12:59:10 PM PDT 24
Finished Mar 14 12:59:18 PM PDT 24
Peak memory 209040 kb
Host smart-1cdb9f5a-0089-4096-90ad-118b94931c55
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033199635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.2033199635
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.2643175197
Short name T773
Test name
Test status
Simulation time 131986612 ps
CPU time 2.89 seconds
Started Mar 14 12:59:13 PM PDT 24
Finished Mar 14 12:59:17 PM PDT 24
Peak memory 216048 kb
Host smart-73a0504a-0284-425f-8222-2046ee128133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643175197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.2643175197
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.4038846087
Short name T743
Test name
Test status
Simulation time 8560384399 ps
CPU time 56.89 seconds
Started Mar 14 12:59:08 PM PDT 24
Finished Mar 14 01:00:05 PM PDT 24
Peak memory 208064 kb
Host smart-428fe033-b0e7-4827-a09f-85371677662d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038846087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.4038846087
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.2026531072
Short name T76
Test name
Test status
Simulation time 9020868099 ps
CPU time 61.38 seconds
Started Mar 14 12:59:10 PM PDT 24
Finished Mar 14 01:00:13 PM PDT 24
Peak memory 216364 kb
Host smart-cac3c239-c0f3-447d-b2a4-7b1468b8d7b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026531072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.2026531072
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_stress_all_with_rand_reset.1344883225
Short name T125
Test name
Test status
Simulation time 457436244 ps
CPU time 15.86 seconds
Started Mar 14 12:59:11 PM PDT 24
Finished Mar 14 12:59:27 PM PDT 24
Peak memory 222940 kb
Host smart-9f564ff0-0a9e-4933-85fd-9296700e2533
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1344883225 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all_with_rand_reset.1344883225
Directory /workspace/45.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.2109817713
Short name T595
Test name
Test status
Simulation time 68703847 ps
CPU time 2.66 seconds
Started Mar 14 12:59:09 PM PDT 24
Finished Mar 14 12:59:12 PM PDT 24
Peak memory 208064 kb
Host smart-a20810b8-d251-499e-b945-1504b460d63f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2109817713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.2109817713
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.105941790
Short name T160
Test name
Test status
Simulation time 94665283 ps
CPU time 1.8 seconds
Started Mar 14 12:59:09 PM PDT 24
Finished Mar 14 12:59:11 PM PDT 24
Peak memory 210360 kb
Host smart-2974bf71-3851-46c2-8c9d-5194c75f6886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=105941790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.105941790
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.492282077
Short name T581
Test name
Test status
Simulation time 39363416 ps
CPU time 0.74 seconds
Started Mar 14 12:59:20 PM PDT 24
Finished Mar 14 12:59:21 PM PDT 24
Peak memory 206328 kb
Host smart-83731fc0-527f-481a-bba4-bd50d01caea0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=492282077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.492282077
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.1183131399
Short name T388
Test name
Test status
Simulation time 143884818 ps
CPU time 4.47 seconds
Started Mar 14 12:59:14 PM PDT 24
Finished Mar 14 12:59:19 PM PDT 24
Peak memory 215216 kb
Host smart-d514c48e-fa96-42a4-9bfb-91499202536b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1183131399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.1183131399
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.2425777124
Short name T18
Test name
Test status
Simulation time 160426949 ps
CPU time 3.19 seconds
Started Mar 14 12:59:15 PM PDT 24
Finished Mar 14 12:59:20 PM PDT 24
Peak memory 209256 kb
Host smart-43beb098-8982-414f-8206-325cdf9cef1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2425777124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.2425777124
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.1489067894
Short name T416
Test name
Test status
Simulation time 214638962 ps
CPU time 1.79 seconds
Started Mar 14 12:59:11 PM PDT 24
Finished Mar 14 12:59:14 PM PDT 24
Peak memory 207500 kb
Host smart-fba98887-5ad5-4b88-ac33-cf0cdac0c5b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489067894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.1489067894
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.1563085940
Short name T865
Test name
Test status
Simulation time 13651861843 ps
CPU time 54.41 seconds
Started Mar 14 12:59:17 PM PDT 24
Finished Mar 14 01:00:12 PM PDT 24
Peak memory 209940 kb
Host smart-cb95160d-ace6-43cd-a97d-b17b7eaf01ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1563085940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.1563085940
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.3143120614
Short name T222
Test name
Test status
Simulation time 44522434 ps
CPU time 2.61 seconds
Started Mar 14 12:59:16 PM PDT 24
Finished Mar 14 12:59:19 PM PDT 24
Peak memory 217776 kb
Host smart-b6506e28-4d1d-4302-be73-5bfcd5261b3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3143120614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.3143120614
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.40978893
Short name T288
Test name
Test status
Simulation time 271620522 ps
CPU time 4.78 seconds
Started Mar 14 12:59:18 PM PDT 24
Finished Mar 14 12:59:23 PM PDT 24
Peak memory 209276 kb
Host smart-8634939d-f0cb-48e6-8e0b-90e2a67c6925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=40978893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.40978893
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.3282170445
Short name T822
Test name
Test status
Simulation time 310766159 ps
CPU time 3.59 seconds
Started Mar 14 12:59:15 PM PDT 24
Finished Mar 14 12:59:19 PM PDT 24
Peak memory 208788 kb
Host smart-7a84bc82-2513-468c-8894-86d1500e5113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3282170445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.3282170445
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.4074448412
Short name T542
Test name
Test status
Simulation time 499126527 ps
CPU time 5.92 seconds
Started Mar 14 12:59:13 PM PDT 24
Finished Mar 14 12:59:19 PM PDT 24
Peak memory 208816 kb
Host smart-3ffa11be-6ddf-4a92-b296-8f4c7abc3f20
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074448412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.4074448412
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.2493728720
Short name T249
Test name
Test status
Simulation time 341785891 ps
CPU time 3.07 seconds
Started Mar 14 12:59:14 PM PDT 24
Finished Mar 14 12:59:18 PM PDT 24
Peak memory 207728 kb
Host smart-7b71a623-b149-47b7-99ea-0084b80e2b7a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2493728720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.2493728720
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.811826465
Short name T651
Test name
Test status
Simulation time 28940732 ps
CPU time 1.85 seconds
Started Mar 14 12:59:13 PM PDT 24
Finished Mar 14 12:59:16 PM PDT 24
Peak memory 208220 kb
Host smart-04353fab-1800-46c8-9b1d-0ee05f6c9535
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811826465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.811826465
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.3450430155
Short name T547
Test name
Test status
Simulation time 231296586 ps
CPU time 3.16 seconds
Started Mar 14 12:59:09 PM PDT 24
Finished Mar 14 12:59:13 PM PDT 24
Peak memory 208148 kb
Host smart-df4d60bc-48e8-4aa4-928d-9a0f2e912f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3450430155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.3450430155
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.3822597785
Short name T662
Test name
Test status
Simulation time 363221292 ps
CPU time 5.29 seconds
Started Mar 14 12:59:10 PM PDT 24
Finished Mar 14 12:59:17 PM PDT 24
Peak memory 208476 kb
Host smart-afdd3db4-5fc4-49eb-8873-899852469e14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822597785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.3822597785
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.3669784443
Short name T853
Test name
Test status
Simulation time 1473814917 ps
CPU time 7.14 seconds
Started Mar 14 12:59:14 PM PDT 24
Finished Mar 14 12:59:24 PM PDT 24
Peak memory 210508 kb
Host smart-675b2003-e517-45a8-add4-5ad5f1937255
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3669784443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.3669784443
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.3046086481
Short name T32
Test name
Test status
Simulation time 115773276 ps
CPU time 2.94 seconds
Started Mar 14 12:59:11 PM PDT 24
Finished Mar 14 12:59:15 PM PDT 24
Peak memory 210572 kb
Host smart-47143d20-8d64-4d45-9bf3-995e2c3b02a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046086481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.3046086481
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.3219627168
Short name T501
Test name
Test status
Simulation time 28751590 ps
CPU time 1.26 seconds
Started Mar 14 12:59:14 PM PDT 24
Finished Mar 14 12:59:17 PM PDT 24
Peak memory 206432 kb
Host smart-8b81221b-92dc-44cf-8077-7b0b0c23f20a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3219627168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.3219627168
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.2930969148
Short name T513
Test name
Test status
Simulation time 1003346164 ps
CPU time 5.06 seconds
Started Mar 14 12:59:20 PM PDT 24
Finished Mar 14 12:59:25 PM PDT 24
Peak memory 208240 kb
Host smart-f7d5d8da-dc40-47cb-b246-5230d3bce9df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2930969148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.2930969148
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.2559714371
Short name T867
Test name
Test status
Simulation time 505227913 ps
CPU time 4.42 seconds
Started Mar 14 12:59:14 PM PDT 24
Finished Mar 14 12:59:19 PM PDT 24
Peak memory 218024 kb
Host smart-9e950244-3e85-49af-9839-409f35adbb08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559714371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.2559714371
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.1311656851
Short name T881
Test name
Test status
Simulation time 1633785756 ps
CPU time 17.71 seconds
Started Mar 14 12:59:13 PM PDT 24
Finished Mar 14 12:59:31 PM PDT 24
Peak memory 210504 kb
Host smart-69eca0b7-186b-4c30-a3bf-f0aefc46acba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311656851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.1311656851
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.3603696024
Short name T588
Test name
Test status
Simulation time 1331932046 ps
CPU time 5.06 seconds
Started Mar 14 12:59:15 PM PDT 24
Finished Mar 14 12:59:21 PM PDT 24
Peak memory 222688 kb
Host smart-9bbbf9cb-d872-4dd5-8e98-fd5a8a246b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603696024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.3603696024
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.767042595
Short name T825
Test name
Test status
Simulation time 386133838 ps
CPU time 4.34 seconds
Started Mar 14 12:59:17 PM PDT 24
Finished Mar 14 12:59:21 PM PDT 24
Peak memory 208688 kb
Host smart-2cb0cc04-b5bd-4dcb-9243-ba56cc88eb74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767042595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.767042595
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.1541237638
Short name T583
Test name
Test status
Simulation time 66782375 ps
CPU time 3.57 seconds
Started Mar 14 12:59:09 PM PDT 24
Finished Mar 14 12:59:14 PM PDT 24
Peak memory 208956 kb
Host smart-4473938e-40c1-4f6c-9d59-a6e71f30ac9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541237638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.1541237638
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.3038951505
Short name T246
Test name
Test status
Simulation time 517535793 ps
CPU time 7.33 seconds
Started Mar 14 12:59:20 PM PDT 24
Finished Mar 14 12:59:27 PM PDT 24
Peak memory 209092 kb
Host smart-7ad19d53-3161-40c8-98be-51ae75b9a36a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038951505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.3038951505
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.3445678461
Short name T771
Test name
Test status
Simulation time 710261692 ps
CPU time 3.79 seconds
Started Mar 14 12:59:20 PM PDT 24
Finished Mar 14 12:59:24 PM PDT 24
Peak memory 208740 kb
Host smart-0fd26273-2f74-4d3e-87e1-f815cb35be8e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445678461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.3445678461
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.1223177013
Short name T11
Test name
Test status
Simulation time 68998078 ps
CPU time 3.44 seconds
Started Mar 14 12:59:13 PM PDT 24
Finished Mar 14 12:59:16 PM PDT 24
Peak memory 206948 kb
Host smart-85fc9252-1b5d-4589-a13d-1db627d0cfa5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1223177013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.1223177013
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.581860876
Short name T904
Test name
Test status
Simulation time 2947305493 ps
CPU time 28.2 seconds
Started Mar 14 12:59:20 PM PDT 24
Finished Mar 14 12:59:48 PM PDT 24
Peak memory 208620 kb
Host smart-a701b7ea-91f5-4e42-b788-b7a05320a1ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581860876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.581860876
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.2335143647
Short name T413
Test name
Test status
Simulation time 250326896 ps
CPU time 3.26 seconds
Started Mar 14 12:59:11 PM PDT 24
Finished Mar 14 12:59:15 PM PDT 24
Peak memory 207028 kb
Host smart-433afb47-ac77-4280-933a-f66300c9bd92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2335143647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.2335143647
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.3820424366
Short name T191
Test name
Test status
Simulation time 532337110 ps
CPU time 19.01 seconds
Started Mar 14 12:59:13 PM PDT 24
Finished Mar 14 12:59:33 PM PDT 24
Peak memory 220676 kb
Host smart-7d2b4b47-23f0-415d-82cd-207745cf3718
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3820424366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.3820424366
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.1152408004
Short name T752
Test name
Test status
Simulation time 353754863 ps
CPU time 8.19 seconds
Started Mar 14 12:59:14 PM PDT 24
Finished Mar 14 12:59:22 PM PDT 24
Peak memory 210304 kb
Host smart-c351bb17-9c15-445d-b6e9-129de1828f57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152408004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.1152408004
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.3220884340
Short name T535
Test name
Test status
Simulation time 44311970 ps
CPU time 0.75 seconds
Started Mar 14 12:59:23 PM PDT 24
Finished Mar 14 12:59:23 PM PDT 24
Peak memory 206268 kb
Host smart-6f5cd059-a782-4cf4-80ff-159a8759b924
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220884340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.3220884340
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.2206092292
Short name T395
Test name
Test status
Simulation time 759845569 ps
CPU time 10.46 seconds
Started Mar 14 12:59:19 PM PDT 24
Finished Mar 14 12:59:30 PM PDT 24
Peak memory 214644 kb
Host smart-98944ce1-02d7-44e5-90fb-c2138f080a24
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2206092292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.2206092292
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.425581712
Short name T584
Test name
Test status
Simulation time 41742040 ps
CPU time 1.76 seconds
Started Mar 14 12:59:19 PM PDT 24
Finished Mar 14 12:59:22 PM PDT 24
Peak memory 208384 kb
Host smart-8b1a4a9b-441f-4160-a000-aa0ef02476db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425581712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.425581712
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.3717113508
Short name T86
Test name
Test status
Simulation time 176424743 ps
CPU time 2.72 seconds
Started Mar 14 12:59:22 PM PDT 24
Finished Mar 14 12:59:25 PM PDT 24
Peak memory 214616 kb
Host smart-ed67ce72-cf1a-4d62-9535-626775650bb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717113508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.3717113508
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.522679602
Short name T292
Test name
Test status
Simulation time 2060909159 ps
CPU time 51.71 seconds
Started Mar 14 12:59:25 PM PDT 24
Finished Mar 14 01:00:16 PM PDT 24
Peak memory 221296 kb
Host smart-c5176830-dda3-4877-8d7e-b7b8a7b41aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522679602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.522679602
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.271813203
Short name T820
Test name
Test status
Simulation time 60062942 ps
CPU time 3.63 seconds
Started Mar 14 12:59:20 PM PDT 24
Finished Mar 14 12:59:24 PM PDT 24
Peak memory 220496 kb
Host smart-bb3c84c7-badf-4809-9217-203de857a456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=271813203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.271813203
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.1914959269
Short name T240
Test name
Test status
Simulation time 94875764 ps
CPU time 3.17 seconds
Started Mar 14 12:59:21 PM PDT 24
Finished Mar 14 12:59:24 PM PDT 24
Peak memory 208340 kb
Host smart-3b3c026f-b33f-4494-8595-0c75f2ea43ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914959269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.1914959269
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.1359037375
Short name T324
Test name
Test status
Simulation time 470540632 ps
CPU time 9.71 seconds
Started Mar 14 12:59:12 PM PDT 24
Finished Mar 14 12:59:22 PM PDT 24
Peak memory 208020 kb
Host smart-08b545b0-52c4-4adb-8f88-18c9a1368fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359037375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.1359037375
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.2727296506
Short name T767
Test name
Test status
Simulation time 19246250632 ps
CPU time 66.13 seconds
Started Mar 14 12:59:26 PM PDT 24
Finished Mar 14 01:00:32 PM PDT 24
Peak memory 209152 kb
Host smart-4c0dccba-ad4c-4360-a26f-a95111b5ea7c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2727296506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.2727296506
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.2202348431
Short name T794
Test name
Test status
Simulation time 93334634 ps
CPU time 1.98 seconds
Started Mar 14 12:59:23 PM PDT 24
Finished Mar 14 12:59:25 PM PDT 24
Peak memory 208880 kb
Host smart-acdae351-cbf1-4785-86bb-7425ef63c999
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2202348431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.2202348431
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.3006617633
Short name T538
Test name
Test status
Simulation time 21447076 ps
CPU time 1.83 seconds
Started Mar 14 12:59:20 PM PDT 24
Finished Mar 14 12:59:22 PM PDT 24
Peak memory 207728 kb
Host smart-6f923f26-db55-4a7f-a0a8-184b7ee0b930
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006617633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.3006617633
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.2911807788
Short name T485
Test name
Test status
Simulation time 72589729 ps
CPU time 3.35 seconds
Started Mar 14 12:59:19 PM PDT 24
Finished Mar 14 12:59:23 PM PDT 24
Peak memory 209212 kb
Host smart-884f4d30-fcd1-4e54-94c4-81c4e4ea977c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911807788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.2911807788
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.377409796
Short name T762
Test name
Test status
Simulation time 50025029 ps
CPU time 2.67 seconds
Started Mar 14 12:59:11 PM PDT 24
Finished Mar 14 12:59:15 PM PDT 24
Peak memory 206804 kb
Host smart-c8022e8a-aa92-4087-a54f-c43368f94b94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377409796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.377409796
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.3555294667
Short name T656
Test name
Test status
Simulation time 1864016188 ps
CPU time 20.69 seconds
Started Mar 14 12:59:20 PM PDT 24
Finished Mar 14 12:59:41 PM PDT 24
Peak memory 216456 kb
Host smart-dcd157a1-4bb7-4564-9b93-d52c5261e6ac
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555294667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.3555294667
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.1095526059
Short name T746
Test name
Test status
Simulation time 302418903 ps
CPU time 9.3 seconds
Started Mar 14 12:59:22 PM PDT 24
Finished Mar 14 12:59:32 PM PDT 24
Peak memory 209228 kb
Host smart-e5107dac-15e0-477c-b77c-1f629f6e45f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1095526059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.1095526059
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.1123053291
Short name T370
Test name
Test status
Simulation time 65186619 ps
CPU time 1.92 seconds
Started Mar 14 12:59:26 PM PDT 24
Finished Mar 14 12:59:28 PM PDT 24
Peak memory 209972 kb
Host smart-c9a9f294-a7f4-4aee-8845-53db8b97cb0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123053291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.1123053291
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.2138910482
Short name T419
Test name
Test status
Simulation time 8969433 ps
CPU time 0.81 seconds
Started Mar 14 12:59:23 PM PDT 24
Finished Mar 14 12:59:24 PM PDT 24
Peak memory 206296 kb
Host smart-2bac8351-707e-419e-8746-1d49388a7cef
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138910482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.2138910482
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.386849606
Short name T258
Test name
Test status
Simulation time 2627620198 ps
CPU time 13.95 seconds
Started Mar 14 12:59:25 PM PDT 24
Finished Mar 14 12:59:39 PM PDT 24
Peak memory 214700 kb
Host smart-e8eea75b-b567-4014-8d37-5c2584fc4973
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=386849606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.386849606
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.246066123
Short name T66
Test name
Test status
Simulation time 59415835 ps
CPU time 1.55 seconds
Started Mar 14 12:59:28 PM PDT 24
Finished Mar 14 12:59:30 PM PDT 24
Peak memory 217320 kb
Host smart-162efbb4-7889-4dc9-b286-d0d300060505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=246066123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.246066123
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.1872316782
Short name T414
Test name
Test status
Simulation time 33791652 ps
CPU time 2.35 seconds
Started Mar 14 12:59:23 PM PDT 24
Finished Mar 14 12:59:25 PM PDT 24
Peak memory 207580 kb
Host smart-2dc9111f-ecd5-4bf5-8d0d-ce3147e48b15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872316782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.1872316782
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.3942316067
Short name T319
Test name
Test status
Simulation time 11579427738 ps
CPU time 37.48 seconds
Started Mar 14 12:59:19 PM PDT 24
Finished Mar 14 12:59:57 PM PDT 24
Peak memory 222812 kb
Host smart-77164a36-e85e-4d42-921a-ace877bf630e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3942316067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.3942316067
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.1834562253
Short name T850
Test name
Test status
Simulation time 112239375 ps
CPU time 5.06 seconds
Started Mar 14 12:59:26 PM PDT 24
Finished Mar 14 12:59:31 PM PDT 24
Peak memory 222740 kb
Host smart-2db4f7b7-8abc-45dc-a8a0-6e53a543285a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834562253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.1834562253
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_random.1849588067
Short name T654
Test name
Test status
Simulation time 47818113 ps
CPU time 3.28 seconds
Started Mar 14 12:59:20 PM PDT 24
Finished Mar 14 12:59:23 PM PDT 24
Peak memory 210120 kb
Host smart-a5b11abd-1085-4a22-bd62-05c6d7ce4b3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849588067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.1849588067
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.2043525326
Short name T711
Test name
Test status
Simulation time 182690061 ps
CPU time 5.88 seconds
Started Mar 14 12:59:26 PM PDT 24
Finished Mar 14 12:59:32 PM PDT 24
Peak memory 206880 kb
Host smart-e4e69913-3bc5-458f-90d1-aa981f2ce2da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043525326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.2043525326
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.2233404263
Short name T305
Test name
Test status
Simulation time 35408322 ps
CPU time 2.37 seconds
Started Mar 14 12:59:19 PM PDT 24
Finished Mar 14 12:59:21 PM PDT 24
Peak memory 207716 kb
Host smart-f25e6803-7ad4-438b-be61-c35d7bf273a6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2233404263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.2233404263
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.368304532
Short name T816
Test name
Test status
Simulation time 694653522 ps
CPU time 7.14 seconds
Started Mar 14 12:59:21 PM PDT 24
Finished Mar 14 12:59:28 PM PDT 24
Peak memory 208256 kb
Host smart-49b6929b-de03-4b54-9a5e-35820cb91a30
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=368304532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.368304532
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.3736884716
Short name T300
Test name
Test status
Simulation time 6981999209 ps
CPU time 18.26 seconds
Started Mar 14 12:59:28 PM PDT 24
Finished Mar 14 12:59:47 PM PDT 24
Peak memory 208788 kb
Host smart-95a80ec3-58e4-4ed4-be95-359491acc366
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736884716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.3736884716
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.622888883
Short name T886
Test name
Test status
Simulation time 19995650 ps
CPU time 1.61 seconds
Started Mar 14 12:59:26 PM PDT 24
Finished Mar 14 12:59:28 PM PDT 24
Peak memory 215696 kb
Host smart-7f3897ea-94ca-443e-9ca1-78877fd02c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622888883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.622888883
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.1103946438
Short name T455
Test name
Test status
Simulation time 63324128 ps
CPU time 3.11 seconds
Started Mar 14 12:59:23 PM PDT 24
Finished Mar 14 12:59:26 PM PDT 24
Peak memory 208472 kb
Host smart-5364da72-e458-47f1-8917-ca96f60c3fb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1103946438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.1103946438
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.1206569773
Short name T805
Test name
Test status
Simulation time 827636813 ps
CPU time 27.93 seconds
Started Mar 14 12:59:27 PM PDT 24
Finished Mar 14 12:59:55 PM PDT 24
Peak memory 222768 kb
Host smart-6a11eb34-a549-48bd-8160-41ce4b007f5e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206569773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.1206569773
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.1443635758
Short name T899
Test name
Test status
Simulation time 30183681 ps
CPU time 2.46 seconds
Started Mar 14 12:59:21 PM PDT 24
Finished Mar 14 12:59:23 PM PDT 24
Peak memory 214512 kb
Host smart-5a80c59b-b4e1-4348-bd84-21b2015b18af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1443635758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.1443635758
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.322959420
Short name T686
Test name
Test status
Simulation time 53723772 ps
CPU time 2.16 seconds
Started Mar 14 12:59:28 PM PDT 24
Finished Mar 14 12:59:31 PM PDT 24
Peak memory 210144 kb
Host smart-26c01d61-e61e-4193-a0bf-4641c3f119a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=322959420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.322959420
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.117591715
Short name T684
Test name
Test status
Simulation time 70324327 ps
CPU time 0.84 seconds
Started Mar 14 12:56:00 PM PDT 24
Finished Mar 14 12:56:00 PM PDT 24
Peak memory 206256 kb
Host smart-770dba14-c3dd-453e-944c-e28989b77f73
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117591715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.117591715
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.2584779116
Short name T133
Test name
Test status
Simulation time 39965730 ps
CPU time 3.15 seconds
Started Mar 14 12:55:57 PM PDT 24
Finished Mar 14 12:56:00 PM PDT 24
Peak memory 215608 kb
Host smart-3ac3c824-2e85-49da-ae87-0b6aba5a1122
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2584779116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.2584779116
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.2666322128
Short name T645
Test name
Test status
Simulation time 112777482 ps
CPU time 2.62 seconds
Started Mar 14 12:56:01 PM PDT 24
Finished Mar 14 12:56:04 PM PDT 24
Peak memory 208508 kb
Host smart-b4c13d54-9600-4aff-9d6b-f78e3d16307f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666322128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.2666322128
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.515089208
Short name T652
Test name
Test status
Simulation time 79221301 ps
CPU time 1.69 seconds
Started Mar 14 12:55:59 PM PDT 24
Finished Mar 14 12:56:00 PM PDT 24
Peak memory 208308 kb
Host smart-819d5780-ebd8-473d-9914-df6c92e92bfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=515089208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.515089208
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.1661035418
Short name T823
Test name
Test status
Simulation time 303561498 ps
CPU time 5.16 seconds
Started Mar 14 12:55:59 PM PDT 24
Finished Mar 14 12:56:04 PM PDT 24
Peak memory 214660 kb
Host smart-085f23af-ab59-4f55-bd0b-e2e95bef43f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661035418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.1661035418
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.3161277466
Short name T200
Test name
Test status
Simulation time 720746625 ps
CPU time 5.41 seconds
Started Mar 14 12:55:59 PM PDT 24
Finished Mar 14 12:56:04 PM PDT 24
Peak memory 222688 kb
Host smart-94af2730-f813-4c89-b669-a04d3936d78e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161277466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.3161277466
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.3514481745
Short name T585
Test name
Test status
Simulation time 58736948 ps
CPU time 3.05 seconds
Started Mar 14 12:55:58 PM PDT 24
Finished Mar 14 12:56:02 PM PDT 24
Peak memory 210028 kb
Host smart-dbf64582-6a4e-4325-af9e-0e60b723ca19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3514481745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.3514481745
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.2039387328
Short name T837
Test name
Test status
Simulation time 815790769 ps
CPU time 11.98 seconds
Started Mar 14 12:55:58 PM PDT 24
Finished Mar 14 12:56:10 PM PDT 24
Peak memory 210180 kb
Host smart-082d91f2-2915-4883-87e2-c4ea413d096c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039387328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.2039387328
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.2178154309
Short name T619
Test name
Test status
Simulation time 66602718 ps
CPU time 2.57 seconds
Started Mar 14 12:55:59 PM PDT 24
Finished Mar 14 12:56:02 PM PDT 24
Peak memory 207496 kb
Host smart-8e60f085-659f-4fcb-b11c-9612fb373fca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2178154309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.2178154309
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.2411205035
Short name T446
Test name
Test status
Simulation time 1047147133 ps
CPU time 6.24 seconds
Started Mar 14 12:56:00 PM PDT 24
Finished Mar 14 12:56:06 PM PDT 24
Peak memory 208296 kb
Host smart-a1fc65be-42d1-45b6-9e38-3a79b13f4b18
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411205035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.2411205035
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.3328841941
Short name T763
Test name
Test status
Simulation time 56084649 ps
CPU time 3.05 seconds
Started Mar 14 12:55:57 PM PDT 24
Finished Mar 14 12:56:00 PM PDT 24
Peak memory 209012 kb
Host smart-b54298eb-03a2-4c9f-bf0e-fa0a092851f5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3328841941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.3328841941
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.3130237217
Short name T522
Test name
Test status
Simulation time 90314255 ps
CPU time 3.26 seconds
Started Mar 14 12:56:01 PM PDT 24
Finished Mar 14 12:56:04 PM PDT 24
Peak memory 208792 kb
Host smart-ca6b1b4d-bb57-4eac-80c8-95ed02815b95
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130237217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.3130237217
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.4015366838
Short name T353
Test name
Test status
Simulation time 165508800 ps
CPU time 2.39 seconds
Started Mar 14 12:55:59 PM PDT 24
Finished Mar 14 12:56:01 PM PDT 24
Peak memory 218404 kb
Host smart-56f110ec-d282-40a5-a208-a161b89ba143
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015366838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.4015366838
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.4025276350
Short name T382
Test name
Test status
Simulation time 239354709 ps
CPU time 2.63 seconds
Started Mar 14 12:56:00 PM PDT 24
Finished Mar 14 12:56:02 PM PDT 24
Peak memory 206964 kb
Host smart-ed2093d3-9f47-4a77-b373-13da7b87c087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025276350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.4025276350
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.3736260752
Short name T590
Test name
Test status
Simulation time 420884468 ps
CPU time 12.36 seconds
Started Mar 14 12:55:58 PM PDT 24
Finished Mar 14 12:56:11 PM PDT 24
Peak memory 207568 kb
Host smart-cc03488b-7f6f-4e8f-9f49-1ea29dfc391d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736260752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.3736260752
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.3235708114
Short name T785
Test name
Test status
Simulation time 616824698 ps
CPU time 11.98 seconds
Started Mar 14 12:56:00 PM PDT 24
Finished Mar 14 12:56:12 PM PDT 24
Peak memory 211112 kb
Host smart-1382aea2-d539-43db-ab5e-57eb17d0dda5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235708114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.3235708114
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.3697179545
Short name T98
Test name
Test status
Simulation time 18779843 ps
CPU time 0.96 seconds
Started Mar 14 12:56:09 PM PDT 24
Finished Mar 14 12:56:11 PM PDT 24
Peak memory 206340 kb
Host smart-d113c93b-33d2-4750-aa4f-7444b57e65c7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697179545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.3697179545
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.2368330303
Short name T387
Test name
Test status
Simulation time 1338759329 ps
CPU time 8.37 seconds
Started Mar 14 12:56:08 PM PDT 24
Finished Mar 14 12:56:17 PM PDT 24
Peak memory 215708 kb
Host smart-1c52bb02-a9d8-4d24-b546-5425ae0bccd0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2368330303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.2368330303
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.3090620708
Short name T8
Test name
Test status
Simulation time 69796379 ps
CPU time 4.14 seconds
Started Mar 14 12:56:09 PM PDT 24
Finished Mar 14 12:56:13 PM PDT 24
Peak memory 223132 kb
Host smart-3722cb9e-a291-454e-a879-8e4f03107453
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090620708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.3090620708
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.1007759482
Short name T562
Test name
Test status
Simulation time 1352905035 ps
CPU time 12.84 seconds
Started Mar 14 12:56:09 PM PDT 24
Finished Mar 14 12:56:22 PM PDT 24
Peak memory 209932 kb
Host smart-46d4514b-3120-4519-b2eb-2aa7027139cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007759482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.1007759482
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.2350976503
Short name T728
Test name
Test status
Simulation time 214232608 ps
CPU time 3.69 seconds
Started Mar 14 12:56:10 PM PDT 24
Finished Mar 14 12:56:15 PM PDT 24
Peak memory 214636 kb
Host smart-43b0ed31-ee52-427c-9109-40fa39e0540a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350976503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.2350976503
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.58125450
Short name T263
Test name
Test status
Simulation time 817500732 ps
CPU time 7.79 seconds
Started Mar 14 12:56:11 PM PDT 24
Finished Mar 14 12:56:19 PM PDT 24
Peak memory 211424 kb
Host smart-10483bbc-635a-4b0b-a7bc-52c07e92c758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58125450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.58125450
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.710338082
Short name T510
Test name
Test status
Simulation time 796117350 ps
CPU time 3.89 seconds
Started Mar 14 12:56:10 PM PDT 24
Finished Mar 14 12:56:15 PM PDT 24
Peak memory 210120 kb
Host smart-27233542-c799-47b2-9127-f64c4d08eaac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=710338082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.710338082
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.296270919
Short name T836
Test name
Test status
Simulation time 735378630 ps
CPU time 5.86 seconds
Started Mar 14 12:56:10 PM PDT 24
Finished Mar 14 12:56:17 PM PDT 24
Peak memory 208664 kb
Host smart-59ff1a6a-8617-430c-bd89-35748086be31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296270919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.296270919
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.91262708
Short name T205
Test name
Test status
Simulation time 48559184 ps
CPU time 2.71 seconds
Started Mar 14 12:55:59 PM PDT 24
Finished Mar 14 12:56:02 PM PDT 24
Peak memory 206952 kb
Host smart-480da848-3742-429f-9617-25e91bdd3f62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91262708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.91262708
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.3963372043
Short name T666
Test name
Test status
Simulation time 120267701 ps
CPU time 3.87 seconds
Started Mar 14 12:56:11 PM PDT 24
Finished Mar 14 12:56:15 PM PDT 24
Peak memory 206932 kb
Host smart-f14d4dee-473c-4c77-8435-ddc871573afd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963372043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.3963372043
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.3880061351
Short name T490
Test name
Test status
Simulation time 398002579 ps
CPU time 2.27 seconds
Started Mar 14 12:56:09 PM PDT 24
Finished Mar 14 12:56:11 PM PDT 24
Peak memory 207108 kb
Host smart-cd59abb5-7307-4d78-999c-a21eb142a3f1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880061351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.3880061351
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.3058951691
Short name T384
Test name
Test status
Simulation time 42135066 ps
CPU time 1.74 seconds
Started Mar 14 12:56:09 PM PDT 24
Finished Mar 14 12:56:11 PM PDT 24
Peak memory 207244 kb
Host smart-866f08d3-6a0e-4209-904e-7da89ec2559d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3058951691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.3058951691
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.3101989648
Short name T680
Test name
Test status
Simulation time 43759759 ps
CPU time 1.9 seconds
Started Mar 14 12:56:12 PM PDT 24
Finished Mar 14 12:56:15 PM PDT 24
Peak memory 207384 kb
Host smart-6c640025-26c4-4d35-85de-7475b4e25930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101989648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.3101989648
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.3316267411
Short name T804
Test name
Test status
Simulation time 102150032 ps
CPU time 2.66 seconds
Started Mar 14 12:55:59 PM PDT 24
Finished Mar 14 12:56:02 PM PDT 24
Peak memory 208744 kb
Host smart-4208ce7a-2afb-4175-b63e-81964886b99d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316267411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.3316267411
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.2464706977
Short name T888
Test name
Test status
Simulation time 393362289 ps
CPU time 14.85 seconds
Started Mar 14 12:56:10 PM PDT 24
Finished Mar 14 12:56:25 PM PDT 24
Peak memory 208248 kb
Host smart-1fddb355-68f3-4793-a959-72937d80fbd8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464706977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.2464706977
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.1437159568
Short name T254
Test name
Test status
Simulation time 973482802 ps
CPU time 7.16 seconds
Started Mar 14 12:56:09 PM PDT 24
Finished Mar 14 12:56:17 PM PDT 24
Peak memory 218652 kb
Host smart-b424df02-ff39-4163-8a08-6edb12c8ed9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1437159568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.1437159568
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.348741944
Short name T738
Test name
Test status
Simulation time 263915171 ps
CPU time 2.25 seconds
Started Mar 14 12:56:09 PM PDT 24
Finished Mar 14 12:56:11 PM PDT 24
Peak memory 210248 kb
Host smart-9a78dee6-4cfd-4d47-90e5-fd155e47e87a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=348741944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.348741944
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.3801038534
Short name T409
Test name
Test status
Simulation time 12130634 ps
CPU time 0.86 seconds
Started Mar 14 12:56:21 PM PDT 24
Finished Mar 14 12:56:22 PM PDT 24
Peak memory 206536 kb
Host smart-5e5642a2-0207-4058-86b0-e33345302c5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3801038534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.3801038534
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.3191998957
Short name T400
Test name
Test status
Simulation time 1075773308 ps
CPU time 12.38 seconds
Started Mar 14 12:56:14 PM PDT 24
Finished Mar 14 12:56:26 PM PDT 24
Peak memory 214564 kb
Host smart-970927fb-e046-4389-a606-ae0e4bed5d81
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3191998957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.3191998957
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.3611491813
Short name T607
Test name
Test status
Simulation time 102181411 ps
CPU time 2.53 seconds
Started Mar 14 12:56:18 PM PDT 24
Finished Mar 14 12:56:21 PM PDT 24
Peak memory 209724 kb
Host smart-e4cf94ed-c13a-4d71-9c90-70ffd4e369aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3611491813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.3611491813
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.4037973506
Short name T91
Test name
Test status
Simulation time 1059493096 ps
CPU time 8.03 seconds
Started Mar 14 12:56:18 PM PDT 24
Finished Mar 14 12:56:26 PM PDT 24
Peak memory 221356 kb
Host smart-8286c273-c471-46c7-bb91-3a7a27e87fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037973506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.4037973506
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.1815653372
Short name T187
Test name
Test status
Simulation time 204172245 ps
CPU time 3.96 seconds
Started Mar 14 12:56:18 PM PDT 24
Finished Mar 14 12:56:22 PM PDT 24
Peak memory 210548 kb
Host smart-b1e0f61f-4d2f-4b79-96a2-2114127aece5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815653372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.1815653372
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.430098702
Short name T255
Test name
Test status
Simulation time 494778886 ps
CPU time 7.21 seconds
Started Mar 14 12:56:10 PM PDT 24
Finished Mar 14 12:56:17 PM PDT 24
Peak memory 207320 kb
Host smart-8b1ed5f2-a21d-469d-99c8-722395538cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430098702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.430098702
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.3077650338
Short name T758
Test name
Test status
Simulation time 33135444 ps
CPU time 2.15 seconds
Started Mar 14 12:56:11 PM PDT 24
Finished Mar 14 12:56:14 PM PDT 24
Peak memory 207052 kb
Host smart-65b9bc30-d20b-4865-88cc-b56287055213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3077650338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.3077650338
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.188434090
Short name T130
Test name
Test status
Simulation time 161930345 ps
CPU time 6.31 seconds
Started Mar 14 12:56:10 PM PDT 24
Finished Mar 14 12:56:17 PM PDT 24
Peak memory 209236 kb
Host smart-132b5d23-731f-4d5e-8bb9-5cfa91e053a9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=188434090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.188434090
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.3445940400
Short name T896
Test name
Test status
Simulation time 1868348867 ps
CPU time 42.27 seconds
Started Mar 14 12:56:09 PM PDT 24
Finished Mar 14 12:56:52 PM PDT 24
Peak memory 208396 kb
Host smart-7111262e-3670-44e1-94e4-5fe945094ab0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3445940400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.3445940400
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.1306412088
Short name T284
Test name
Test status
Simulation time 765014539 ps
CPU time 4.08 seconds
Started Mar 14 12:56:13 PM PDT 24
Finished Mar 14 12:56:18 PM PDT 24
Peak memory 206916 kb
Host smart-aa5e0608-a821-4f8a-a816-bbf029698fe2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1306412088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.1306412088
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.2849142225
Short name T760
Test name
Test status
Simulation time 138418747 ps
CPU time 2.25 seconds
Started Mar 14 12:56:24 PM PDT 24
Finished Mar 14 12:56:26 PM PDT 24
Peak memory 208156 kb
Host smart-1fde8c7c-7c1e-412d-9437-d257a88f19fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2849142225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.2849142225
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.3762170182
Short name T188
Test name
Test status
Simulation time 274480903 ps
CPU time 3.11 seconds
Started Mar 14 12:56:09 PM PDT 24
Finished Mar 14 12:56:12 PM PDT 24
Peak memory 207140 kb
Host smart-4501e32e-3805-429a-9131-50bc0c1102e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3762170182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.3762170182
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.1836414256
Short name T192
Test name
Test status
Simulation time 5090309561 ps
CPU time 36.66 seconds
Started Mar 14 12:56:23 PM PDT 24
Finished Mar 14 12:57:00 PM PDT 24
Peak memory 217476 kb
Host smart-7b21b9ca-ab4c-4ef5-a35c-5db77cbeb698
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836414256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.1836414256
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_stress_all_with_rand_reset.4019946450
Short name T797
Test name
Test status
Simulation time 239256697 ps
CPU time 7.39 seconds
Started Mar 14 12:56:23 PM PDT 24
Finished Mar 14 12:56:30 PM PDT 24
Peak memory 220420 kb
Host smart-a9cef965-e602-4483-a201-62eecfe1c794
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4019946450 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all_with_rand_reset.4019946450
Directory /workspace/7.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.4032153368
Short name T198
Test name
Test status
Simulation time 563697427 ps
CPU time 6.01 seconds
Started Mar 14 12:56:18 PM PDT 24
Finished Mar 14 12:56:24 PM PDT 24
Peak memory 209616 kb
Host smart-81b3aba3-6df3-4d9a-9b17-13f70b72add7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032153368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.4032153368
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.2157027627
Short name T128
Test name
Test status
Simulation time 255222417 ps
CPU time 2.05 seconds
Started Mar 14 12:56:19 PM PDT 24
Finished Mar 14 12:56:21 PM PDT 24
Peak memory 210336 kb
Host smart-83f3262a-9960-4d00-8a89-a972d4db11a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157027627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.2157027627
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.2234011417
Short name T900
Test name
Test status
Simulation time 58462682 ps
CPU time 0.83 seconds
Started Mar 14 12:56:31 PM PDT 24
Finished Mar 14 12:56:32 PM PDT 24
Peak memory 206252 kb
Host smart-545c3a78-ce9e-468d-afb8-283472f1db5c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2234011417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.2234011417
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.1050408642
Short name T405
Test name
Test status
Simulation time 60712078 ps
CPU time 4.18 seconds
Started Mar 14 12:56:19 PM PDT 24
Finished Mar 14 12:56:24 PM PDT 24
Peak memory 214740 kb
Host smart-e60a82e2-fd7c-4bec-ae3d-ba513b97707c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1050408642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.1050408642
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.1807381980
Short name T808
Test name
Test status
Simulation time 38014085 ps
CPU time 1.76 seconds
Started Mar 14 12:56:24 PM PDT 24
Finished Mar 14 12:56:26 PM PDT 24
Peak memory 208616 kb
Host smart-d664c67f-85e5-437a-82c1-ab536d6c41ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807381980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.1807381980
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.1861487409
Short name T648
Test name
Test status
Simulation time 1184378862 ps
CPU time 5.6 seconds
Started Mar 14 12:56:24 PM PDT 24
Finished Mar 14 12:56:31 PM PDT 24
Peak memory 209672 kb
Host smart-24be962c-038d-498a-ac68-71e2654b35ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861487409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.1861487409
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.2428023204
Short name T262
Test name
Test status
Simulation time 1550046341 ps
CPU time 12.93 seconds
Started Mar 14 12:56:19 PM PDT 24
Finished Mar 14 12:56:32 PM PDT 24
Peak memory 217688 kb
Host smart-f68bd131-75bb-45bf-be77-be825f630e5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428023204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.2428023204
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.4266389599
Short name T229
Test name
Test status
Simulation time 69964277 ps
CPU time 3.34 seconds
Started Mar 14 12:56:20 PM PDT 24
Finished Mar 14 12:56:24 PM PDT 24
Peak memory 218032 kb
Host smart-674a13da-3629-46cd-96c0-a1b356e89ced
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266389599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.4266389599
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.4237192859
Short name T193
Test name
Test status
Simulation time 416159252 ps
CPU time 4.81 seconds
Started Mar 14 12:56:21 PM PDT 24
Finished Mar 14 12:56:26 PM PDT 24
Peak memory 210364 kb
Host smart-b6d7a4a7-d5d5-42ce-b06d-1e63369da3de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4237192859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.4237192859
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.1652961838
Short name T608
Test name
Test status
Simulation time 460580915 ps
CPU time 5.25 seconds
Started Mar 14 12:56:19 PM PDT 24
Finished Mar 14 12:56:24 PM PDT 24
Peak memory 207136 kb
Host smart-ae5a66ca-0cbf-4415-8861-0fb708361272
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652961838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.1652961838
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.2734205159
Short name T591
Test name
Test status
Simulation time 157859127 ps
CPU time 2.52 seconds
Started Mar 14 12:56:18 PM PDT 24
Finished Mar 14 12:56:21 PM PDT 24
Peak memory 207036 kb
Host smart-08d02717-54e2-443a-988b-de11cec095cd
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2734205159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.2734205159
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.192743209
Short name T847
Test name
Test status
Simulation time 626620235 ps
CPU time 5.68 seconds
Started Mar 14 12:56:20 PM PDT 24
Finished Mar 14 12:56:26 PM PDT 24
Peak memory 207612 kb
Host smart-1c30305f-caee-4cca-9f66-d37ee986f229
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=192743209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.192743209
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.735792859
Short name T571
Test name
Test status
Simulation time 253409670 ps
CPU time 2.88 seconds
Started Mar 14 12:56:18 PM PDT 24
Finished Mar 14 12:56:21 PM PDT 24
Peak memory 206960 kb
Host smart-b488da6f-4d0a-4e99-b6e3-6005dcc00792
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735792859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.735792859
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.2099069902
Short name T712
Test name
Test status
Simulation time 155793034 ps
CPU time 3.3 seconds
Started Mar 14 12:56:19 PM PDT 24
Finished Mar 14 12:56:22 PM PDT 24
Peak memory 208648 kb
Host smart-56e63106-03c8-4664-a620-f803cf3c5731
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099069902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.2099069902
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.502032673
Short name T573
Test name
Test status
Simulation time 186903866 ps
CPU time 4.64 seconds
Started Mar 14 12:56:24 PM PDT 24
Finished Mar 14 12:56:29 PM PDT 24
Peak memory 208788 kb
Host smart-b9e7cecc-70ce-4441-a7fd-f04c5895cd54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502032673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.502032673
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.2724163374
Short name T556
Test name
Test status
Simulation time 2307363364 ps
CPU time 35.19 seconds
Started Mar 14 12:56:35 PM PDT 24
Finished Mar 14 12:57:10 PM PDT 24
Peak memory 216972 kb
Host smart-2bd1fd26-7466-4756-a2d0-33d310ba98e8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724163374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.2724163374
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_stress_all_with_rand_reset.1839248201
Short name T809
Test name
Test status
Simulation time 1162427720 ps
CPU time 11.27 seconds
Started Mar 14 12:56:35 PM PDT 24
Finished Mar 14 12:56:46 PM PDT 24
Peak memory 220088 kb
Host smart-ed2ee2c3-209d-4571-9a16-4ce015dd8eae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1839248201 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all_with_rand_reset.1839248201
Directory /workspace/8.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.2155990036
Short name T277
Test name
Test status
Simulation time 90770017 ps
CPU time 3.78 seconds
Started Mar 14 12:56:21 PM PDT 24
Finished Mar 14 12:56:25 PM PDT 24
Peak memory 218528 kb
Host smart-22283e1e-c1d4-4ddb-8dc1-f6e0750f0cc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155990036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.2155990036
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.3004718923
Short name T195
Test name
Test status
Simulation time 254341265 ps
CPU time 3.26 seconds
Started Mar 14 12:56:33 PM PDT 24
Finished Mar 14 12:56:36 PM PDT 24
Peak memory 210692 kb
Host smart-c9895008-2fa0-4786-871f-c9e285193cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004718923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.3004718923
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.886411354
Short name T519
Test name
Test status
Simulation time 42412845 ps
CPU time 0.84 seconds
Started Mar 14 12:56:32 PM PDT 24
Finished Mar 14 12:56:32 PM PDT 24
Peak memory 206284 kb
Host smart-a1cc922f-b715-4459-9123-4bae75872645
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=886411354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.886411354
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.3543115796
Short name T705
Test name
Test status
Simulation time 142958630 ps
CPU time 4.05 seconds
Started Mar 14 12:56:34 PM PDT 24
Finished Mar 14 12:56:38 PM PDT 24
Peak memory 209112 kb
Host smart-bd2000de-3ef6-4520-b2ef-a4f8d9f37f6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3543115796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.3543115796
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.2953383534
Short name T363
Test name
Test status
Simulation time 1629575885 ps
CPU time 7.13 seconds
Started Mar 14 12:56:32 PM PDT 24
Finished Mar 14 12:56:40 PM PDT 24
Peak memory 214560 kb
Host smart-ad241143-1757-434e-8272-b1e259497477
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2953383534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.2953383534
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.370058031
Short name T244
Test name
Test status
Simulation time 139094737 ps
CPU time 3.15 seconds
Started Mar 14 12:56:32 PM PDT 24
Finished Mar 14 12:56:35 PM PDT 24
Peak memory 211536 kb
Host smart-0e1d98cc-4cce-4e09-a330-4ee6fa9b8f4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=370058031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.370058031
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_random.3970554521
Short name T772
Test name
Test status
Simulation time 61329731 ps
CPU time 3.57 seconds
Started Mar 14 12:56:31 PM PDT 24
Finished Mar 14 12:56:35 PM PDT 24
Peak memory 209948 kb
Host smart-e0208435-ded8-4578-910b-8b4f6a35f018
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970554521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.3970554521
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.1087438911
Short name T716
Test name
Test status
Simulation time 667552230 ps
CPU time 5.28 seconds
Started Mar 14 12:56:32 PM PDT 24
Finished Mar 14 12:56:37 PM PDT 24
Peak memory 208888 kb
Host smart-43ce9cea-711f-4644-a3ac-aa7e10b9a74c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1087438911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.1087438911
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.622472437
Short name T411
Test name
Test status
Simulation time 33150931 ps
CPU time 2.31 seconds
Started Mar 14 12:56:33 PM PDT 24
Finished Mar 14 12:56:36 PM PDT 24
Peak memory 207096 kb
Host smart-ca315f79-f9bc-4d5f-a6ab-28a6daa7bb64
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=622472437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.622472437
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.473857990
Short name T615
Test name
Test status
Simulation time 269606716 ps
CPU time 3.52 seconds
Started Mar 14 12:56:32 PM PDT 24
Finished Mar 14 12:56:36 PM PDT 24
Peak memory 209164 kb
Host smart-d9e9c26c-783e-4df9-a908-29f9988fd132
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473857990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.473857990
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.3905537010
Short name T539
Test name
Test status
Simulation time 376698164 ps
CPU time 10.72 seconds
Started Mar 14 12:56:33 PM PDT 24
Finished Mar 14 12:56:43 PM PDT 24
Peak memory 207132 kb
Host smart-e6a4a77b-4dcc-4e72-ad56-299fc5da08c9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905537010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.3905537010
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.3343693662
Short name T827
Test name
Test status
Simulation time 143590204 ps
CPU time 3.39 seconds
Started Mar 14 12:56:34 PM PDT 24
Finished Mar 14 12:56:38 PM PDT 24
Peak memory 209360 kb
Host smart-26a5671f-e23b-4545-b8cd-41c1d44900a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3343693662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.3343693662
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.1417902681
Short name T520
Test name
Test status
Simulation time 53869270 ps
CPU time 2.68 seconds
Started Mar 14 12:56:34 PM PDT 24
Finished Mar 14 12:56:37 PM PDT 24
Peak memory 208684 kb
Host smart-d1fec610-853b-42bf-9fdf-ab73318ec135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1417902681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.1417902681
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.2405501425
Short name T236
Test name
Test status
Simulation time 1153958578 ps
CPU time 23.95 seconds
Started Mar 14 12:56:32 PM PDT 24
Finished Mar 14 12:56:56 PM PDT 24
Peak memory 216220 kb
Host smart-bc7a877b-8255-4e72-97f2-fab591080ade
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405501425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.2405501425
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.634370760
Short name T194
Test name
Test status
Simulation time 1120662992 ps
CPU time 7.88 seconds
Started Mar 14 12:56:33 PM PDT 24
Finished Mar 14 12:56:41 PM PDT 24
Peak memory 208820 kb
Host smart-0acf5f23-30c1-4703-80eb-3b940b4b05c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=634370760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.634370760
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.2078760779
Short name T55
Test name
Test status
Simulation time 211517651 ps
CPU time 2.61 seconds
Started Mar 14 12:56:31 PM PDT 24
Finished Mar 14 12:56:34 PM PDT 24
Peak memory 210076 kb
Host smart-462e3534-2262-4c20-bdfe-4536886c587d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2078760779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.2078760779
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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