Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
80.05	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	51	0	51	100.00
Crosses	330	76	254	76.97

Variables for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
aes_sl_avail	2	0	2	100.00	100	1	1	2
aes_sl_avail_cp	2	0	2	100.00	100	1	1	2
kmac_sl_avail	2	0	2	100.00	100	1	1	2
kmac_sl_avail_cp	2	0	2	100.00	100	1	1	2
op	5	0	5	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
otbn_sl_avail	2	0	2	100.00	100	1	1	2
otbn_sl_avail_cp	2	0	2	100.00	100	1	1	2
regwen_cp	2	0	2	100.00	100	1	1	2
sideload_clear	8	0	8	100.00	100	1	1	8
sideload_clear_cp	5	0	5	100.00	100	1	1	0
state	7	0	7	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sideload_clear_x_state_op_cross	280	57	223	79.64	100	1	1	0
sideload_clear_x_sl_avail_cross	40	19	21	52.50	100	1	1	0
sideload_clear_x_regwen_cross	10	0	10	100.00	100	1	1	0

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4805

1

T2

14

T3

8

T4

9

auto[1]

512

1

T2

2

T14

3

T84

6

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4805

1

T2

14

T3

8

T4

9

auto[1]

512

1

T2

2

T14

3

T84

6

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4820

1

T2

16

T3

8

T4

9

auto[1]

497

1

T5

1

T42

3

T206

1

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4820

1

T2

16

T3

8

T4

9

auto[1]

497

1

T5

1

T42

3

T206

1

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	402	1			T2	3		T21	1		T118	1
auto[OpGenId]	1110	1			T2	4		T5	1		T16	1
auto[OpGenSwOut]	1108	1			T2	6		T5	1		T15	3
auto[OpGenHwOut]	2626	1			T2	3		T3	8		T4	9
auto[OpDisable]	71	1			T47	1		T43	1		T48	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	402	1			T2	3		T21	1		T118	1
auto[OpGenId]	1110	1			T2	4		T5	1		T16	1
auto[OpGenSwOut]	1108	1			T2	6		T5	1		T15	3
auto[OpGenHwOut]	2626	1			T2	3		T3	8		T4	9
auto[OpDisable]	71	1			T47	1		T43	1		T48	1

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4753

1

T2

11

T3

5

T4

6

auto[1]

564

1

T2

5

T3

3

T4

3

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4753

1

T2

11

T3

5

T4

6

auto[1]

564

1

T2

5

T3

3

T4

3

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5062

1

T2

6

T3

8

T4

9

auto[1]

255

1

T2

10

T114

2

T148

12

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1846	1			T2	7		T3	2		T4	3
auto[1]	672	1			T3	1		T4	1		T5	1
auto[2]	676	1			T2	2		T3	1		T5	1
auto[3]	693	1			T2	5		T3	1		T4	3
auto[4]	345	1			T4	1		T5	1		T21	1
auto[5]	355	1			T2	1		T3	1		T4	1
auto[6]	338	1			T3	1		T14	1		T15	1
auto[7]	392	1			T2	1		T3	1		T15	1

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1430	1			T2	2		T3	3		T4	2
clear_one[1]	672	1			T3	1		T4	1		T5	1
clear_one[2]	676	1			T2	2		T3	1		T5	1
clear_one[3]	693	1			T2	5		T3	1		T4	3
clear_none	1846	1			T2	7		T3	2		T4	3

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1016	1			T4	1		T14	1		T15	1
auto[StInit]	752	1			T2	1		T3	1		T4	1
auto[StCreatorRootKey]	583	1			T2	2		T3	1		T4	1
auto[StOwnerIntKey]	495	1			T2	4		T3	1		T4	1
auto[StOwnerKey]	490	1			T2	2		T3	1		T4	1
auto[StDisabled]	1817	1			T2	7		T3	4		T4	4
auto[StInvalid]	164	1			T36	2		T39	3		T204	3

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1016	1			T4	1		T14	1		T15	1
auto[StInit]	752	1			T2	1		T3	1		T4	1
auto[StCreatorRootKey]	583	1			T2	2		T3	1		T4	1
auto[StOwnerIntKey]	495	1			T2	4		T3	1		T4	1
auto[StOwnerKey]	490	1			T2	2		T3	1		T4	1
auto[StDisabled]	1817	1			T2	7		T3	4		T4	4
auto[StInvalid]	164	1			T36	2		T39	3		T204	3

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	57	223	79.64	57

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[0]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[1] - auto[3]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	3
[auto[1] - auto[3]]	[auto[StReset]]	[auto[OpDisable]]	--	--	3
[auto[1] - auto[3]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	12
[auto[1] - auto[3]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	3
[auto[4]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[4]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[4]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[4]]	[auto[StInvalid]]	[auto[OpAdvance]]	0	1	1
[auto[4]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[5]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[5]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[5]]	[auto[StInit] , auto[StCreatorRootKey]]	[auto[OpDisable]]	--	--	2
[auto[5]]	[auto[StOwnerIntKey]]	[auto[OpAdvance]]	0	1	1
[auto[5]]	[auto[StOwnerIntKey]]	[auto[OpDisable]]	0	1	1
[auto[5]]	[auto[StOwnerKey]]	[auto[OpDisable]]	0	1	1
[auto[5]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[6] - auto[7]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	2
[auto[6] - auto[7]]	[auto[StReset]]	[auto[OpDisable]]	--	--	2
[auto[6] - auto[7]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	8
[auto[6] - auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	2

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpAdvance]	3	1			T237	1		T238	1		T239	1
auto[0]	auto[StReset]	auto[OpGenId]	159	1			T213	1		T43	3		T7	1
auto[0]	auto[StReset]	auto[OpGenSwOut]	156	1			T213	1		T216	1		T43	1
auto[0]	auto[StReset]	auto[OpGenHwOut]	282	1			T4	1		T14	1		T15	1
auto[0]	auto[StInit]	auto[OpAdvance]	48	1			T114	1		T49	1		T106	1
auto[0]	auto[StInit]	auto[OpGenId]	124	1			T2	1		T5	1		T21	1
auto[0]	auto[StInit]	auto[OpGenSwOut]	96	1			T16	1		T22	1		T53	1
auto[0]	auto[StInit]	auto[OpGenHwOut]	181	1			T3	1		T14	1		T17	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	19	1			T240	1		T68	1		T121	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	55	1			T25	1		T100	2		T7	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	47	1			T100	1		T7	1		T126	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	94	1			T4	1		T17	1		T118	1
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	13	1			T114	1		T59	1		T137	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	30	1			T208	1		T241	1		T50	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	39	1			T206	1		T205	1		T126	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	49	1			T84	1		T242	1		T104	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	11	1			T2	1		T243	1		T244	1
auto[0]	auto[StOwnerKey]	auto[OpGenId]	15	1			T2	1		T7	1		T101	1
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	18	1			T53	1		T245	1		T246	1
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	50	1			T43	1		T125	1		T247	1
auto[0]	auto[StDisabled]	auto[OpAdvance]	25	1			T2	1		T148	2		T55	1
auto[0]	auto[StDisabled]	auto[OpGenId]	54	1			T7	1		T53	1		T148	1
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	59	1			T2	1		T206	1		T148	2
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	158	1			T2	2		T3	1		T4	1
auto[0]	auto[StDisabled]	auto[OpDisable]	22	1			T48	1		T53	1		T248	1
auto[0]	auto[StInvalid]	auto[OpAdvance]	4	1			T249	1		T250	1		T251	1
auto[0]	auto[StInvalid]	auto[OpGenId]	10	1			T36	1		T252	1		T92	1
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	11	1			T39	2		T207	2		T253	1
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	14	1			T41	1		T207	1		T252	1
auto[1]	auto[StReset]	auto[OpGenId]	19	1			T8	1		T55	1		T50	1
auto[1]	auto[StReset]	auto[OpGenSwOut]	16	1			T7	1		T55	1		T254	1
auto[1]	auto[StReset]	auto[OpGenHwOut]	48	1			T219	1		T124	1		T49	1
auto[1]	auto[StInit]	auto[OpAdvance]	8	1			T249	1		T255	1		T256	1
auto[1]	auto[StInit]	auto[OpGenId]	12	1			T257	1		T258	1		T93	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	15	1			T209	1		T23	1		T108	1
auto[1]	auto[StInit]	auto[OpGenHwOut]	33	1			T21	1		T219	1		T124	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	6	1			T68	1		T251	1		T94	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	13	1			T59	1		T93	2		T259	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	13	1			T260	1		T261	1		T69	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	40	1			T42	1		T107	1		T190	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	7	1			T97	1		T233	1		T262	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	14	1			T54	1		T119	1		T96	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	11	1			T227	1		T222	1		T68	2
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	39	1			T118	1		T132	1		T263	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	2	1			T68	1		T264	1		-	-
auto[1]	auto[StOwnerKey]	auto[OpGenId]	9	1			T114	1		T222	1		T183	1
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	9	1			T265	1		T266	1		T69	1
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	42	1			T3	1		T4	1		T217	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	22	1			T118	1		T209	1		T43	1
auto[1]	auto[StDisabled]	auto[OpGenId]	47	1			T208	1		T205	1		T100	1
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	55	1			T212	1		T43	1		T7	1
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	159	1			T5	1		T14	2		T84	1
auto[1]	auto[StDisabled]	auto[OpDisable]	10	1			T49	1		T267	1		T227	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	3	1			T268	1		T269	1		T270	1
auto[1]	auto[StInvalid]	auto[OpGenId]	9	1			T207	1		T91	1		T271	1
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	7	1			T253	1		T272	1		T273	1
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	4	1			T207	1		T249	1		T251	1
auto[2]	auto[StReset]	auto[OpGenId]	15	1			T55	1		T274	1		T275	1
auto[2]	auto[StReset]	auto[OpGenSwOut]	26	1			T45	1		T87	1		T81	1
auto[2]	auto[StReset]	auto[OpGenHwOut]	43	1			T53	1		T276	1		T49	1
auto[2]	auto[StInit]	auto[OpAdvance]	7	1			T88	1		T277	1		T278	1
auto[2]	auto[StInit]	auto[OpGenId]	18	1			T23	1		T95	1		T89	1
auto[2]	auto[StInit]	auto[OpGenSwOut]	15	1			T21	1		T23	1		T24	1
auto[2]	auto[StInit]	auto[OpGenHwOut]	26	1			T42	1		T24	1		T133	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	6	1			T279	1		T280	1		T281	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	13	1			T43	1		T49	1		T93	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	17	1			T216	1		T245	1		T282	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	43	1			T3	1		T14	1		T15	1
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	7	1			T139	1		T283	1		T69	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	13	1			T284	1		T123	1		T285	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	11	1			T5	1		T15	1		T286	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	34	1			T14	1		T17	1		T42	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	6	1			T287	1		T288	1		T289	1
auto[2]	auto[StOwnerKey]	auto[OpGenId]	12	1			T206	1		T108	1		T135	1
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	11	1			T133	1		T225	1		T139	1
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	48	1			T42	1		T118	1		T132	1
auto[2]	auto[StDisabled]	auto[OpAdvance]	21	1			T43	1		T148	1		T149	1
auto[2]	auto[StDisabled]	auto[OpGenId]	58	1			T2	2		T216	1		T100	1
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	55	1			T208	1		T212	1		T43	1
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	140	1			T84	1		T42	1		T218	1
auto[2]	auto[StDisabled]	auto[OpDisable]	7	1			T59	1		T290	1		T258	1
auto[2]	auto[StInvalid]	auto[OpAdvance]	5	1			T268	1		T291	1		T292	1
auto[2]	auto[StInvalid]	auto[OpGenId]	5	1			T293	1		T271	1		T294	1
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	7	1			T36	1		T39	1		T211	1
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	7	1			T295	1		T268	1		T296	1
auto[3]	auto[StReset]	auto[OpGenId]	24	1			T209	1		T45	1		T133	1
auto[3]	auto[StReset]	auto[OpGenSwOut]	20	1			T56	1		T149	1		T86	1
auto[3]	auto[StReset]	auto[OpGenHwOut]	42	1			T219	2		T216	1		T43	1
auto[3]	auto[StInit]	auto[OpAdvance]	8	1			T21	1		T23	1		T138	1
auto[3]	auto[StInit]	auto[OpGenId]	12	1			T213	1		T86	1		T50	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	14	1			T129	2		T86	1		T297	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	31	1			T4	1		T27	1		T89	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	11	1			T2	1		T225	2		T183	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	11	1			T43	1		T135	1		T298	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	14	1			T148	1		T49	1		T54	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	34	1			T84	1		T148	1		T129	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T299	1		T255	1		T202	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	8	1			T100	1		T7	1		T55	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	20	1			T2	4		T49	1		T225	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	38	1			T212	1		T7	1		T276	1
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	8	1			T69	1		T121	1		T51	1
auto[3]	auto[StOwnerKey]	auto[OpGenId]	17	1			T205	1		T300	1		T227	1
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	14	1			T148	2		T129	1		T101	1
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	30	1			T84	1		T148	2		T129	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	24	1			T53	2		T134	1		T279	1
auto[3]	auto[StDisabled]	auto[OpGenId]	47	1			T43	2		T134	1		T54	2
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	51	1			T100	1		T129	2		T134	1
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	175	1			T3	1		T4	2		T14	1
auto[3]	auto[StDisabled]	auto[OpDisable]	15	1			T53	1		T59	1		T63	1
auto[3]	auto[StInvalid]	auto[OpAdvance]	4	1			T301	1		T291	1		T251	1
auto[3]	auto[StInvalid]	auto[OpGenId]	4	1			T91	1		T302	1		T303	1
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	7	1			T211	1		T41	1		T294	1
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	6	1			T207	1		T295	1		T304	1
auto[4]	auto[StReset]	auto[OpGenId]	7	1			T216	1		T43	1		T243	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	9	1			T49	1		T108	1		T55	1
auto[4]	auto[StReset]	auto[OpGenHwOut]	17	1			T56	1		T263	1		T305	1
auto[4]	auto[StInit]	auto[OpAdvance]	4	1			T306	1		T307	1		T308	1
auto[4]	auto[StInit]	auto[OpGenId]	8	1			T278	1		T309	1		T310	1
auto[4]	auto[StInit]	auto[OpGenSwOut]	7	1			T23	1		T311	1		T312	1
auto[4]	auto[StInit]	auto[OpGenHwOut]	10	1			T21	1		T43	1		T263	1
auto[4]	auto[StCreatorRootKey]	auto[OpAdvance]	5	1			T136	1		T275	1		T238	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	9	1			T101	1		T108	1		T313	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	6	1			T43	1		T314	1		T315	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	20	1			T316	1		T317	1		T318	1
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	7	1			T43	1		T237	1		T319	2
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	5	1			T225	1		T320	1		T237	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	6	1			T121	1		T234	1		T321	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	19	1			T53	1		T79	1		T322	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T43	1		T72	1		T323	1
auto[4]	auto[StOwnerKey]	auto[OpGenId]	12	1			T106	1		T286	1		T140	2
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	9	1			T22	1		T138	1		T140	1
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	21	1			T107	1		T324	1		T325	1
auto[4]	auto[StDisabled]	auto[OpAdvance]	12	1			T275	1		T243	1		T51	1
auto[4]	auto[StDisabled]	auto[OpGenId]	39	1			T53	1		T214	1		T54	3
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	25	1			T100	1		T215	1		T59	1
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	67	1			T4	1		T5	1		T217	1
auto[4]	auto[StDisabled]	auto[OpDisable]	6	1			T47	1		T287	1		T326	1
auto[4]	auto[StInvalid]	auto[OpGenId]	3	1			T301	1		T293	1		T327	1
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	5	1			T92	1		T272	1		T268	1
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	2	1			T204	1		T207	1		-	-
auto[5]	auto[StReset]	auto[OpGenId]	11	1			T328	1		T259	1		T51	1
auto[5]	auto[StReset]	auto[OpGenSwOut]	7	1			T279	1		T329	1		T291	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	28	1			T276	1		T263	1		T330	1
auto[5]	auto[StInit]	auto[OpAdvance]	3	1			T331	1		T332	1		T333	1
auto[5]	auto[StInit]	auto[OpGenId]	4	1			T69	1		T311	1		T334	1
auto[5]	auto[StInit]	auto[OpGenSwOut]	3	1			T335	1		T51	1		T236	1
auto[5]	auto[StInit]	auto[OpGenHwOut]	16	1			T43	1		T49	1		T105	1
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	2	1			T56	1		T336	1		-	-
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	8	1			T213	1		T68	1		T315	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	7	1			T209	1		T55	1		T337	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	19	1			T247	1		T105	1		T179	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	5	1			T338	1		T305	1		T339	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	8	1			T101	1		T340	1		T227	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	19	1			T4	1		T219	1		T100	1
auto[5]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T108	1		T341	1		T51	1
auto[5]	auto[StOwnerKey]	auto[OpGenId]	9	1			T342	1		T258	1		T343	1
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	9	1			T213	1		T340	1		T335	1
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	18	1			T17	1		T242	1		T189	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	13	1			T340	1		T55	1		T138	1
auto[5]	auto[StDisabled]	auto[OpGenId]	27	1			T216	1		T43	1		T100	1
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	23	1			T2	1		T100	1		T246	1
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	96	1			T3	1		T14	1		T17	2
auto[5]	auto[StDisabled]	auto[OpDisable]	1	1			T344	1		-	-		-	-
auto[5]	auto[StInvalid]	auto[OpAdvance]	1	1			T345	1		-	-		-	-
auto[5]	auto[StInvalid]	auto[OpGenId]	4	1			T204	1		T294	1		T346	1
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	5	1			T291	1		T347	1		T348	1
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	5	1			T204	1		T92	1		T291	1
auto[6]	auto[StReset]	auto[OpGenId]	11	1			T245	1		T254	1		T50	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	12	1			T129	1		T108	1		T254	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	21	1			T227	1		T318	1		T349	1
auto[6]	auto[StInit]	auto[OpAdvance]	3	1			T140	1		T350	1		T351	1
auto[6]	auto[StInit]	auto[OpGenId]	3	1			T328	1		T352	1		T353	1
auto[6]	auto[StInit]	auto[OpGenSwOut]	2	1			T354	2		-	-		-	-
auto[6]	auto[StInit]	auto[OpGenHwOut]	14	1			T330	1		T55	1		T355	1
auto[6]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T356	1		T357	1		T358	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	5	1			T16	1		T108	1		T359	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	6	1			T284	1		T300	1		T360	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	18	1			T263	1		T78	1		T305	1
auto[6]	auto[StOwnerIntKey]	auto[OpAdvance]	8	1			T186	1		T121	1		T361	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	10	1			T282	1		T63	1		T225	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	9	1			T176	1		T183	1		T362	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	18	1			T3	1		T218	1		T240	1
auto[6]	auto[StOwnerKey]	auto[OpAdvance]	3	1			T51	1		T357	1		T363	1
auto[6]	auto[StOwnerKey]	auto[OpGenId]	5	1			T216	1		T338	1		T123	1
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	9	1			T100	1		T49	1		T108	1
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	33	1			T14	1		T218	1		T53	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	6	1			T50	1		T139	1		T364	1
auto[6]	auto[StDisabled]	auto[OpGenId]	29	1			T100	1		T49	1		T54	1
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	16	1			T15	1		T114	1		T59	1
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	76	1			T276	1		T54	1		T324	3
auto[6]	auto[StDisabled]	auto[OpDisable]	4	1			T55	1		T365	1		T264	1
auto[6]	auto[StInvalid]	auto[OpAdvance]	2	1			T303	1		T366	1		-	-
auto[6]	auto[StInvalid]	auto[OpGenId]	5	1			T252	1		T92	1		T291	1
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	5	1			T253	1		T304	1		T367	1
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	1	1			T368	1		-	-		-	-
auto[7]	auto[StReset]	auto[OpGenId]	10	1			T248	1		T68	1		T280	1
auto[7]	auto[StReset]	auto[OpGenSwOut]	8	1			T86	1		T68	1		T369	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	22	1			T219	1		T276	1		T370	1
auto[7]	auto[StInit]	auto[OpAdvance]	8	1			T89	1		T274	1		T328	2
auto[7]	auto[StInit]	auto[OpGenId]	2	1			T371	1		T372	1		-	-
auto[7]	auto[StInit]	auto[OpGenSwOut]	5	1			T47	1		T43	1		T315	1
auto[7]	auto[StInit]	auto[OpGenHwOut]	12	1			T373	1		T196	1		T236	1
auto[7]	auto[StCreatorRootKey]	auto[OpAdvance]	2	1			T97	1		T236	1		-	-
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	5	1			T287	1		T374	1		T375	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	9	1			T43	1		T59	1		T376	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	22	1			T2	1		T217	1		T106	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T299	1		T280	1		T377	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	6	1			T374	1		T310	1		T233	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	7	1			T248	1		T378	1		T236	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	28	1			T217	1		T54	1		T135	1
auto[7]	auto[StOwnerKey]	auto[OpAdvance]	7	1			T379	1		T380	1		T381	1
auto[7]	auto[StOwnerKey]	auto[OpGenId]	7	1			T208	1		T43	1		T222	1
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	15	1			T100	1		T55	1		T137	1
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	22	1			T219	1		T43	1		T149	2
auto[7]	auto[StDisabled]	auto[OpAdvance]	17	1			T101	1		T140	2		T299	2
auto[7]	auto[StDisabled]	auto[OpGenId]	29	1			T7	1		T49	1		T108	1
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	36	1			T15	1		T43	1		T7	1
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	85	1			T3	1		T17	1		T217	1
auto[7]	auto[StDisabled]	auto[OpDisable]	6	1			T43	1		T53	1		T67	1
auto[7]	auto[StInvalid]	auto[OpAdvance]	1	1			T271	1		-	-		-	-
auto[7]	auto[StInvalid]	auto[OpGenId]	5	1			T252	2		T92	1		T273	1
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	6	1			T41	1		T295	1		T249	1
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	7	1			T211	1		T257	1		T249	1

---

Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1430

1

T2

2

T3

3

T4

2

clear_one[1]

auto[0]

auto[0]

auto[0]

408

1

T5

1

T14

2

T84

1

clear_one[1]

auto[0]

auto[0]

auto[1]

133

1

T3

1

T4

1

T114

2

clear_one[1]

auto[0]

auto[1]

auto[0]

101

1

T42

2

T276

1

T49

1

clear_one[1]

auto[0]

auto[1]

auto[1]

30

1

T118

2

T212

1

T279

1

clear_one[2]

auto[0]

auto[0]

auto[0]

382

1

T5

1

T15

2

T21

1

clear_one[2]

auto[0]

auto[0]

auto[1]

142

1

T3

1

T17

1

T118

1

clear_one[2]

auto[1]

auto[0]

auto[0]

122

1

T2

2

T14

2

T84

1

clear_one[2]

auto[1]

auto[0]

auto[1]

30

1

T212

1

T125

1

T48

1

clear_one[3]

auto[0]

auto[0]

auto[0]

415

1

T2

5

T3

1

T4

3

clear_one[3]

auto[0]

auto[1]

auto[0]

126

1

T42

1

T218

1

T212

1

clear_one[3]

auto[1]

auto[0]

auto[0]

120

1

T14

1

T84

3

T205

1

clear_one[3]

auto[1]

auto[1]

auto[0]

32

1

T209

1

T125

1

T49

1

clear_none

auto[0]

auto[0]

auto[0]

1336

1

T2

2

T3

1

T4

1

clear_none

auto[0]

auto[0]

auto[1]

145

1

T2

5

T3

1

T4

2

clear_none

auto[0]

auto[1]

auto[0]

134

1

T5

1

T218

1

T219

2

clear_none

auto[0]

auto[1]

auto[1]

23

1

T212

1

T100

1

T7

1

clear_none

auto[1]

auto[0]

auto[0]

121

1

T84

2

T217

1

T205

1

clear_none

auto[1]

auto[0]

auto[1]

36

1

T118

1

T48

1

T104

1

clear_none

auto[1]

auto[1]

auto[0]

26

1

T206

1

T54

1

T382

1

clear_none

auto[1]

auto[1]

auto[1]

25

1

T186

1

T267

1

T383

1

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1368	1			T2	2		T3	3		T4	2
clear_all	auto[1]	62	1			T149	1		T137	1		T360	3
clear_one[1]	auto[0]	651	1			T3	1		T4	1		T5	1
clear_one[1]	auto[1]	21	1			T114	1		T148	2		T137	8
clear_one[2]	auto[0]	641	1			T2	1		T3	1		T5	1
clear_one[2]	auto[1]	35	1			T2	1		T149	2		T136	2
clear_one[3]	auto[0]	650	1			T2	1		T3	1		T4	3
clear_one[3]	auto[1]	43	1			T2	4		T148	5		T129	6
clear_none	auto[0]	1752	1			T2	2		T3	2		T4	3
clear_none	auto[1]	94	1			T2	5		T114	1		T148	5