Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
43.16	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	360	216	144	40.00

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	168	112	40.00	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11818

1

T2

14

T3

7

T4

6

auto[Attestation]

8357

1

T2

14

T3

1

T4

5

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2981	1			T2	8		T6	4		T15	4
auto[Aes]	3596	1			T2	1		T5	2		T14	9
auto[Kmac]	3581	1			T2	2		T5	3		T6	6
auto[Otbn]	3661	1			T2	4		T3	8		T4	11

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	8008	1			T2	8		T3	8		T4	8
auto[OpGenId]	6356	1			T2	13		T5	3		T6	4
auto[OpGenSwOut]	6377	1			T2	9		T5	2		T6	6
auto[OpGenHwOut]	7442	1			T2	6		T3	8		T4	11
auto[OpDisable]	134	1			T47	1		T43	2		T48	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10548

1

T2

16

T3

8

T4

8

auto[OpDoneFail]

17769

1

T2

20

T3

8

T4

11

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6360	1			T2	1		T3	1		T4	4
auto[StInit]	4413	1			T2	6		T3	2		T4	2
auto[StCreatorRootKey]	3176	1			T2	3		T3	2		T4	2
auto[StOwnerIntKey]	2794	1			T2	6		T3	2		T4	2
auto[StOwnerKey]	2456	1			T2	5		T3	2		T4	2
auto[StDisabled]	8009	1			T2	15		T3	7		T4	7
auto[StInvalid]	1109	1			T36	35		T39	25		T204	23

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	168	112	40.00	168

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	322	1			T6	1		T15	1		T26	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	135	1			T21	2		T205	1		T43	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	77	1			T206	1		T43	1		T100	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	71	1			T2	1		T118	1		T53	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	71	1			T2	1		T43	1		T133	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	221	1			T15	1		T47	1		T118	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	35	1			T204	1		T41	3		T207	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	322	1			T15	1		T47	1		T26	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	117	1			T21	1		T47	2		T22	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	92	1			T25	1		T208	1		T43	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	84	1			T5	1		T118	1		T209	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	67	1			T100	1		T49	1		T54	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	234	1			T15	1		T85	1		T210	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	38	1			T36	1		T39	3		T211	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	306	1			T6	2		T43	3		T35	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	110	1			T21	1		T88	1		T54	4
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	94	1			T25	1		T212	2		T125	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	61	1			T2	1		T213	1		T43	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	55	1			T5	1		T210	1		T53	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	218	1			T208	1		T205	1		T7	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	35	1			T36	2		T204	1		T211	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	323	1			T6	1		T15	1		T213	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	117	1			T15	1		T22	2		T43	3
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	91	1			T213	1		T43	1		T148	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	66	1			T2	1		T16	1		T212	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	65	1			T6	1		T43	1		T45	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	218	1			T210	1		T22	1		T114	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	45	1			T36	1		T39	1		T41	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	74	1			T43	1		T7	1		T53	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	116	1			T2	1		T21	1		T43	5
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	72	1			T43	2		T35	1		T125	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	78	1			T6	1		T213	1		T43	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	56	1			T22	1		T100	1		T148	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	225	1			T2	2		T16	2		T114	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	41	1			T36	2		T39	2		T204	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	71	1			T43	1		T7	1		T101	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	124	1			T21	1		T209	2		T43	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	76	1			T7	1		T49	2		T214	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	78	1			T213	1		T7	1		T149	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	53	1			T118	1		T205	1		T212	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	212	1			T208	1		T22	1		T209	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	39	1			T36	1		T39	1		T211	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	75	1			T43	4		T7	1		T53	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	132	1			T21	1		T23	1		T53	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	79	1			T85	1		T209	1		T43	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	51	1			T100	1		T53	2		T215	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	58	1			T213	1		T49	1		T101	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	236	1			T15	1		T118	1		T209	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	31	1			T36	5		T204	1		T211	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	70	1			T43	2		T7	1		T53	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	134	1			T16	1		T21	1		T205	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	95	1			T205	1		T216	1		T43	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	70	1			T15	1		T206	1		T43	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	62	1			T16	1		T100	2		T7	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	247	1			T2	2		T15	1		T206	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	32	1			T39	4		T41	1		T207	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	274	1			T47	2		T45	1		T56	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	140	1			T21	1		T205	1		T212	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	78	1			T2	1		T6	1		T209	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	57	1			T149	1		T215	1		T108	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	45	1			T22	1		T213	1		T43	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	171	1			T15	1		T16	1		T118	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	37	1			T36	1		T39	1		T211	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	411	1			T14	1		T6	1		T209	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	137	1			T14	1		T15	1		T84	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	115	1			T14	1		T217	1		T205	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	119	1			T84	1		T217	1		T43	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	87	1			T217	1		T22	1		T114	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	283	1			T2	1		T14	1		T15	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	30	1			T36	3		T204	2		T211	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	497	1			T6	1		T15	1		T42	3
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	138	1			T2	1		T6	2		T114	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	104	1			T218	1		T219	1		T43	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	90	1			T42	1		T22	1		T213	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	94	1			T6	1		T118	1		T213	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	288	1			T5	1		T15	1		T42	3
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	32	1			T36	2		T41	4		T207	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	418	1			T4	3		T15	1		T47	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	143	1			T3	1		T15	1		T21	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	114	1			T3	1		T25	1		T118	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	104	1			T3	1		T17	1		T212	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	77	1			T3	1		T213	1		T114	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	306	1			T3	3		T4	3		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	35	1			T39	2		T204	2		T211	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	67	1			T43	2		T7	1		T53	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	108	1			T2	1		T21	1		T208	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	70	1			T6	1		T15	1		T134	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	69	1			T216	1		T212	1		T100	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	61	1			T43	1		T53	1		T54	4
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	176	1			T2	1		T47	1		T118	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	34	1			T36	2		T39	1		T204	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	71	1			T43	3		T7	1		T53	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	132	1			T15	1		T21	1		T22	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	98	1			T25	1		T84	1		T118	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	96	1			T14	1		T22	1		T100	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	97	1			T14	1		T84	1		T213	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	273	1			T5	1		T14	3		T15	3
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	40	1			T36	1		T211	3		T41	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	59	1			T43	4		T7	2		T53	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	117	1			T21	1		T42	1		T219	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	119	1			T25	2		T42	1		T212	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	95	1			T118	1		T22	1		T219	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	89	1			T42	1		T118	1		T149	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	281	1			T5	1		T42	1		T218	3
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	37	1			T36	1		T204	1		T207	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	66	1			T43	2		T7	1		T101	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	130	1			T4	1		T17	1		T209	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	114	1			T4	1		T6	1		T17	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	105	1			T4	1		T100	1		T124	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	96	1			T2	1		T4	1		T17	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	282	1			T3	1		T4	1		T17	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	36	1			T39	1		T204	2		T211	3

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	200	1			T2	2		T206	1		T43	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	732	1			T6	1		T15	2		T21	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	223	1			T5	1		T25	1		T118	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	731	1			T15	2		T21	1		T47	3
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	196	1			T2	1		T5	1		T25	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	683	1			T6	2		T21	1		T208	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	204	1			T2	1		T6	1		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	721	1			T6	1		T15	2		T210	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	191	1			T6	1		T22	1		T213	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	471	1			T2	3		T16	2		T21	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	190	1			T213	1		T212	1		T7	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	463	1			T21	1		T118	1		T208	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	175	1			T85	1		T213	1		T209	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	487	1			T15	1		T21	1		T118	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	206	1			T15	1		T16	1		T206	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	504	1			T2	2		T15	1		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	162	1			T2	1		T6	1		T213	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	640	1			T15	1		T16	1		T21	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	301	1			T14	1		T84	1		T217	3
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	881	1			T2	1		T14	3		T6	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	266	1			T6	1		T42	1		T118	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	977	1			T2	1		T5	1		T6	3
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	285	1			T3	3		T17	1		T25	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	912	1			T3	4		T4	6		T15	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	185	1			T6	1		T216	1		T212	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	400	1			T2	2		T15	1		T21	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	276	1			T14	2		T25	1		T84	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	531	1			T5	1		T14	3		T15	4
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	281	1			T25	2		T42	2		T118	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	516	1			T5	1		T21	1		T42	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	299	1			T2	1		T4	3		T6	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	530	1			T3	1		T4	2		T17	3