Unified Coverage Report :: Group Instance : attest_sw_binding

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32396

auto[1]

290

T114

T148

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
auto[0:134217727]	32408	1		T2	39	T3	19	T4	22
auto[134217728:268435455]	12	1		T2	1	T129	1	T139	1
auto[268435456:402653183]	10	1		T137	1	T283	1	T356	1
auto[402653184:536870911]	6	1		T383	1	T357	1	T319	1
auto[536870912:671088639]	14	1		T2	3	T136	1	T137	1
auto[671088640:805306367]	9	1		T129	1	T136	1	T356	2
auto[805306368:939524095]	6	1		T129	1	T136	1	T299	1
auto[939524096:1073741823]	9	1		T2	1	T148	1	T136	1
auto[1073741824:1207959551]	10	1		T2	1	T148	1	T129	1
auto[1207959552:1342177279]	8	1		T2	1	T137	1	T319	1
auto[1342177280:1476395007]	7	1		T129	1	T136	1	T137	1
auto[1476395008:1610612735]	10	1		T2	2	T149	1	T137	1
auto[1610612736:1744830463]	8	1		T139	1	T140	1	T393	1
auto[1744830464:1879048191]	12	1		T140	1	T356	1	T298	1
auto[1879048192:2013265919]	6	1		T356	1	T357	1	T407	1
auto[2013265920:2147483647]	8	1		T137	1	T371	1	T298	1
auto[2147483648:2281701375]	8	1		T137	1	T408	1	T409	1
auto[2281701376:2415919103]	10	1		T137	1	T299	1	T371	1
auto[2415919104:2550136831]	4	1		T140	1	T319	1	T410	1
auto[2550136832:2684354559]	8	1		T136	1	T391	1	T237	1
auto[2684354560:2818572287]	13	1		T148	1	T129	1	T136	1
auto[2818572288:2952790015]	6	1		T114	1	T129	1	T407	1
auto[2952790016:3087007743]	12	1		T129	1	T134	1	T137	1
auto[3087007744:3221225471]	11	1		T383	1	T140	1	T356	2
auto[3221225472:3355443199]	13	1		T148	2	T379	1	T356	1
auto[3355443200:3489660927]	6	1		T129	1	T371	1	T411	1
auto[3489660928:3623878655]	14	1		T148	1	T136	1	T328	1
auto[3623878656:3758096383]	8	1		T2	1	T129	1	T140	3
auto[3758096384:3892314111]	8	1		T139	1	T140	1	T237	1
auto[3892314112:4026531839]	7	1		T148	1	T371	1	T198	1
auto[4026531840:4160749567]	10	1		T149	1	T139	1	T140	2
auto[4160749568:4294967295]	5	1		T383	1	T139	1	T283	1

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
auto[0:134217727]	auto[0]	32396	1		T2	39	T3	19	T4	22
auto[0:134217727]	auto[1]	12	1		T129	1	T412	1	T393	2
auto[134217728:268435455]	auto[1]	12	1		T2	1	T129	1	T139	1
auto[268435456:402653183]	auto[1]	10	1		T137	1	T283	1	T356	1
auto[402653184:536870911]	auto[1]	6	1		T383	1	T357	1	T319	1
auto[536870912:671088639]	auto[1]	14	1		T2	3	T136	1	T137	1
auto[671088640:805306367]	auto[1]	9	1		T129	1	T136	1	T356	2
auto[805306368:939524095]	auto[1]	6	1		T129	1	T136	1	T299	1
auto[939524096:1073741823]	auto[1]	9	1		T2	1	T148	1	T136	1
auto[1073741824:1207959551]	auto[1]	10	1		T2	1	T148	1	T129	1
auto[1207959552:1342177279]	auto[1]	8	1		T2	1	T137	1	T319	1
auto[1342177280:1476395007]	auto[1]	7	1		T129	1	T136	1	T137	1
auto[1476395008:1610612735]	auto[1]	10	1		T2	2	T149	1	T137	1
auto[1610612736:1744830463]	auto[1]	8	1		T139	1	T140	1	T393	1
auto[1744830464:1879048191]	auto[1]	12	1		T140	1	T356	1	T298	1
auto[1879048192:2013265919]	auto[1]	6	1		T356	1	T357	1	T407	1
auto[2013265920:2147483647]	auto[1]	8	1		T137	1	T371	1	T298	1
auto[2147483648:2281701375]	auto[1]	8	1		T137	1	T408	1	T409	1
auto[2281701376:2415919103]	auto[1]	10	1		T137	1	T299	1	T371	1
auto[2415919104:2550136831]	auto[1]	4	1		T140	1	T319	1	T410	1
auto[2550136832:2684354559]	auto[1]	8	1		T136	1	T391	1	T237	1
auto[2684354560:2818572287]	auto[1]	13	1		T148	1	T129	1	T136	1
auto[2818572288:2952790015]	auto[1]	6	1		T114	1	T129	1	T407	1
auto[2952790016:3087007743]	auto[1]	12	1		T129	1	T134	1	T137	1
auto[3087007744:3221225471]	auto[1]	11	1		T383	1	T140	1	T356	2
auto[3221225472:3355443199]	auto[1]	13	1		T148	2	T379	1	T356	1
auto[3355443200:3489660927]	auto[1]	6	1		T129	1	T371	1	T411	1
auto[3489660928:3623878655]	auto[1]	14	1		T148	1	T136	1	T328	1
auto[3623878656:3758096383]	auto[1]	8	1		T2	1	T129	1	T140	3
auto[3758096384:3892314111]	auto[1]	8	1		T139	1	T140	1	T237	1
auto[3892314112:4026531839]	auto[1]	7	1		T148	1	T371	1	T198	1
auto[4026531840:4160749567]	auto[1]	10	1		T149	1	T139	1	T140	2
auto[4160749568:4294967295]	auto[1]	5	1		T383	1	T139	1	T283	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1596

T15

T21

auto[1]

1811

T15

T25

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
auto[0:134217727]	98	1		T15	1	T43	1	T7	1
auto[134217728:268435455]	107	1		T15	1	T25	1	T7	1
auto[268435456:402653183]	108	1		T100	1	T125	1	T7	1
auto[402653184:536870911]	124	1		T15	1	T21	1	T43	1
auto[536870912:671088639]	90	1		T118	1	T45	1	T133	1
auto[671088640:805306367]	105	1		T22	1	T205	1	T126	1
auto[805306368:939524095]	106	1		T21	2	T114	1	T100	1
auto[939524096:1073741823]	120	1		T2	1	T43	2	T7	1
auto[1073741824:1207959551]	106	1		T43	1	T100	2	T148	1
auto[1207959552:1342177279]	100	1		T43	2	T7	2	T56	1
auto[1342177280:1476395007]	113	1		T43	3	T100	1	T23	1
auto[1476395008:1610612735]	109	1		T43	2	T53	1	T36	1
auto[1610612736:1744830463]	91	1		T125	1	T56	1	T24	1
auto[1744830464:1879048191]	121	1		T21	1	T212	1	T43	1
auto[1879048192:2013265919]	84	1		T118	1	T22	1	T43	2
auto[2013265920:2147483647]	98	1		T21	1	T148	1	T149	1
auto[2147483648:2281701375]	104	1		T209	1	T43	2	T7	1
auto[2281701376:2415919103]	109	1		T15	1	T213	1	T205	1
auto[2415919104:2550136831]	111	1		T114	1	T43	3	T56	1
auto[2550136832:2684354559]	123	1		T2	1	T15	1	T43	1
auto[2684354560:2818572287]	112	1		T22	1	T23	1	T44	1
auto[2818572288:2952790015]	90	1		T2	1	T114	2	T7	1
auto[2952790016:3087007743]	113	1		T15	1	T118	1	T53	1
auto[3087007744:3221225471]	105	1		T25	1	T100	2	T126	1
auto[3221225472:3355443199]	98	1		T47	1	T43	2	T53	1
auto[3355443200:3489660927]	106	1		T209	1	T43	1	T7	1
auto[3489660928:3623878655]	125	1		T212	1	T100	1	T7	1
auto[3623878656:3758096383]	105	1		T43	1	T100	1	T53	1
auto[3758096384:3892314111]	108	1		T43	1	T100	1	T130	1
auto[3892314112:4026531839]	110	1		T15	1	T26	1	T118	1
auto[4026531840:4160749567]	101	1		T118	1	T22	1	T43	2
auto[4160749568:4294967295]	107	1		T2	1	T205	1	T212	1

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
auto[0:134217727]	auto[0]	43	1		T15	1	T95	1	T413	1
auto[0:134217727]	auto[1]	55	1		T43	1	T7	1	T44	1
auto[134217728:268435455]	auto[0]	51	1		T15	1	T7	1	T45	1
auto[134217728:268435455]	auto[1]	56	1		T25	1	T130	1	T104	1
auto[268435456:402653183]	auto[0]	59	1		T100	1	T7	1	T104	1
auto[268435456:402653183]	auto[1]	49	1		T125	1	T67	1	T54	1
auto[402653184:536870911]	auto[0]	54	1		T15	1	T21	1	T43	1
auto[402653184:536870911]	auto[1]	70	1		T129	1	T49	1	T108	1
auto[536870912:671088639]	auto[0]	43	1		T118	1	T101	1	T54	1
auto[536870912:671088639]	auto[1]	47	1		T45	1	T133	1	T134	1
auto[671088640:805306367]	auto[0]	45	1		T205	1	T126	1	T86	1
auto[671088640:805306367]	auto[1]	60	1		T22	1	T31	1	T52	1
auto[805306368:939524095]	auto[0]	54	1		T21	2	T114	1	T100	1
auto[805306368:939524095]	auto[1]	52	1		T126	1	T148	1	T214	1
auto[939524096:1073741823]	auto[0]	54	1		T43	2	T95	1	T54	1
auto[939524096:1073741823]	auto[1]	66	1		T2	1	T7	1	T56	1
auto[1073741824:1207959551]	auto[0]	46	1		T43	1	T100	1	T49	1
auto[1073741824:1207959551]	auto[1]	60	1		T100	1	T148	1	T88	1
auto[1207959552:1342177279]	auto[0]	43	1		T43	1	T7	1	T214	1
auto[1207959552:1342177279]	auto[1]	57	1		T43	1	T7	1	T56	1
auto[1342177280:1476395007]	auto[0]	54	1		T43	1	T148	1	T45	1
auto[1342177280:1476395007]	auto[1]	59	1		T43	2	T100	1	T23	1
auto[1476395008:1610612735]	auto[0]	56	1		T43	1	T54	1	T59	2
auto[1476395008:1610612735]	auto[1]	53	1		T43	1	T53	1	T36	1
auto[1610612736:1744830463]	auto[0]	39	1		T125	1	T56	1	T24	1
auto[1610612736:1744830463]	auto[1]	52	1		T215	1	T8	1	T104	1
auto[1744830464:1879048191]	auto[0]	55	1		T21	1	T212	1	T53	2
auto[1744830464:1879048191]	auto[1]	66	1		T43	1	T53	1	T88	1
auto[1879048192:2013265919]	auto[0]	33	1		T22	1	T43	1	T44	1
auto[1879048192:2013265919]	auto[1]	51	1		T118	1	T43	1	T100	1
auto[2013265920:2147483647]	auto[0]	45	1		T21	1	T149	1	T52	1
auto[2013265920:2147483647]	auto[1]	53	1		T148	1	T49	1	T59	1
auto[2147483648:2281701375]	auto[0]	46	1		T209	1	T86	2	T204	1
auto[2147483648:2281701375]	auto[1]	58	1		T43	2	T7	1	T133	1
auto[2281701376:2415919103]	auto[0]	48	1		T49	1	T8	1	T59	1
auto[2281701376:2415919103]	auto[1]	61	1		T15	1	T213	1	T205	1
auto[2415919104:2550136831]	auto[0]	54	1		T114	1	T43	3	T88	1
auto[2415919104:2550136831]	auto[1]	57	1		T56	1	T8	1	T101	1
auto[2550136832:2684354559]	auto[0]	66	1		T15	1	T43	1	T23	1
auto[2550136832:2684354559]	auto[1]	57	1		T2	1	T125	1	T7	2
auto[2684354560:2818572287]	auto[0]	58	1		T23	1	T59	1	T188	1
auto[2684354560:2818572287]	auto[1]	54	1		T22	1	T44	1	T56	1
auto[2818572288:2952790015]	auto[0]	41	1		T134	1	T108	1	T59	1
auto[2818572288:2952790015]	auto[1]	49	1		T2	1	T114	2	T7	1
auto[2952790016:3087007743]	auto[0]	54	1		T129	1	T49	1	T95	1
auto[2952790016:3087007743]	auto[1]	59	1		T15	1	T118	1	T53	1
auto[3087007744:3221225471]	auto[0]	56	1		T100	1	T126	1	T130	1
auto[3087007744:3221225471]	auto[1]	49	1		T25	1	T100	1	T45	1
auto[3221225472:3355443199]	auto[0]	41	1		T43	1	T24	1	T52	1
auto[3221225472:3355443199]	auto[1]	57	1		T47	1	T43	1	T53	1
auto[3355443200:3489660927]	auto[0]	44	1		T209	1	T129	1	T101	1
auto[3355443200:3489660927]	auto[1]	62	1		T43	1	T7	1	T149	1
auto[3489660928:3623878655]	auto[0]	60	1		T7	1	T36	1	T130	1
auto[3489660928:3623878655]	auto[1]	65	1		T212	1	T100	1	T129	1
auto[3623878656:3758096383]	auto[0]	55	1		T43	1	T53	1	T45	1
auto[3623878656:3758096383]	auto[1]	50	1		T100	1	T104	1	T54	1
auto[3758096384:3892314111]	auto[0]	50	1		T43	1	T130	1	T24	1
auto[3758096384:3892314111]	auto[1]	58	1		T100	1	T134	1	T8	1
auto[3892314112:4026531839]	auto[0]	50	1		T43	1	T100	1	T149	1
auto[3892314112:4026531839]	auto[1]	60	1		T15	1	T26	1	T118	1
auto[4026531840:4160749567]	auto[0]	54	1		T22	1	T43	1	T53	1
auto[4026531840:4160749567]	auto[1]	47	1		T118	1	T43	1	T100	2
auto[4160749568:4294967295]	auto[0]	45	1		T2	1	T23	1	T27	1
auto[4160749568:4294967295]	auto[1]	62	1		T205	1	T212	1	T100	2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1573

T15

T21

auto[1]

1834

T15

T25

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
auto[0:134217727]	99	1		T43	1	T100	1	T45	1
auto[134217728:268435455]	99	1		T7	1	T27	1	T36	1
auto[268435456:402653183]	121	1		T15	1	T25	1	T21	1
auto[402653184:536870911]	106	1		T25	1	T205	1	T100	1
auto[536870912:671088639]	115	1		T22	1	T114	1	T43	1
auto[671088640:805306367]	95	1		T21	1	T43	1	T126	1
auto[805306368:939524095]	123	1		T21	1	T43	1	T125	1
auto[939524096:1073741823]	109	1		T26	1	T114	1	T43	1
auto[1073741824:1207959551]	103	1		T47	1	T213	1	T7	1
auto[1207959552:1342177279]	99	1		T22	1	T43	3	T53	1
auto[1342177280:1476395007]	109	1		T209	1	T125	1	T49	1
auto[1476395008:1610612735]	140	1		T2	2	T21	1	T118	1
auto[1610612736:1744830463]	84	1		T15	1	T209	1	T100	1
auto[1744830464:1879048191]	103	1		T22	1	T43	4	T100	2
auto[1879048192:2013265919]	107	1		T114	1	T212	1	T7	1
auto[2013265920:2147483647]	103	1		T114	1	T209	1	T212	1
auto[2147483648:2281701375]	123	1		T205	1	T43	1	T53	2
auto[2281701376:2415919103]	114	1		T43	1	T100	1	T23	1
auto[2415919104:2550136831]	111	1		T43	1	T100	1	T56	1
auto[2550136832:2684354559]	88	1		T118	2	T53	1	T149	1
auto[2684354560:2818572287]	87	1		T15	2	T22	1	T43	1
auto[2818572288:2952790015]	124	1		T15	1	T43	3	T100	1
auto[2952790016:3087007743]	104	1		T7	1	T23	1	T53	1
auto[3087007744:3221225471]	108	1		T100	1	T49	1	T106	1
auto[3221225472:3355443199]	90	1		T2	1	T7	1	T148	1
auto[3355443200:3489660927]	105	1		T15	1	T43	2	T100	1
auto[3489660928:3623878655]	94	1		T100	1	T7	1	T49	1
auto[3623878656:3758096383]	101	1		T15	1	T118	1	T43	1
auto[3758096384:3892314111]	108	1		T43	1	T53	1	T49	2
auto[3892314112:4026531839]	111	1		T21	1	T100	1	T125	1
auto[4026531840:4160749567]	107	1		T212	1	T100	1	T7	3
auto[4160749568:4294967295]	117	1		T2	1	T43	4	T100	1

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
auto[0:134217727]	auto[0]	51	1		T43	1	T45	1	T108	1
auto[0:134217727]	auto[1]	48	1		T100	1	T56	1	T54	1
auto[134217728:268435455]	auto[0]	52	1		T7	1	T8	1	T188	1
auto[134217728:268435455]	auto[1]	47	1		T27	1	T36	1	T104	1
auto[268435456:402653183]	auto[0]	55	1		T15	1	T21	1	T43	1
auto[268435456:402653183]	auto[1]	66	1		T25	1	T118	1	T212	1
auto[402653184:536870911]	auto[0]	51	1		T126	1	T24	1	T95	1
auto[402653184:536870911]	auto[1]	55	1		T25	1	T205	1	T100	1
auto[536870912:671088639]	auto[0]	50	1		T22	1	T43	1	T45	1
auto[536870912:671088639]	auto[1]	65	1		T114	1	T100	1	T56	1
auto[671088640:805306367]	auto[0]	48	1		T21	1	T43	1	T44	1
auto[671088640:805306367]	auto[1]	47	1		T126	1	T44	1	T54	1
auto[805306368:939524095]	auto[0]	63	1		T21	1	T125	1	T24	1
auto[805306368:939524095]	auto[1]	60	1		T43	1	T8	1	T101	1
auto[939524096:1073741823]	auto[0]	46	1		T129	1	T95	1	T101	1
auto[939524096:1073741823]	auto[1]	63	1		T26	1	T114	1	T43	1
auto[1073741824:1207959551]	auto[0]	43	1		T7	1	T59	1	T61	1
auto[1073741824:1207959551]	auto[1]	60	1		T47	1	T213	1	T53	1
auto[1207959552:1342177279]	auto[0]	48	1		T22	1	T43	1	T53	1
auto[1207959552:1342177279]	auto[1]	51	1		T43	2	T45	1	T133	1
auto[1342177280:1476395007]	auto[0]	52	1		T209	1	T49	1	T101	1
auto[1342177280:1476395007]	auto[1]	57	1		T125	1	T101	1	T108	1
auto[1476395008:1610612735]	auto[0]	72	1		T21	1	T205	1	T43	2
auto[1476395008:1610612735]	auto[1]	68	1		T2	2	T118	1	T149	2
auto[1610612736:1744830463]	auto[0]	46	1		T23	1	T148	1	T130	2
auto[1610612736:1744830463]	auto[1]	38	1		T15	1	T209	1	T100	1
auto[1744830464:1879048191]	auto[0]	45	1		T43	2	T36	1	T129	2
auto[1744830464:1879048191]	auto[1]	58	1		T22	1	T43	2	T100	2
auto[1879048192:2013265919]	auto[0]	49	1		T114	1	T52	1	T86	1
auto[1879048192:2013265919]	auto[1]	58	1		T212	1	T7	1	T53	1
auto[2013265920:2147483647]	auto[0]	47	1		T114	1	T209	1	T126	1
auto[2013265920:2147483647]	auto[1]	56	1		T212	1	T125	1	T7	1
auto[2147483648:2281701375]	auto[0]	57	1		T205	1	T59	1	T204	1
auto[2147483648:2281701375]	auto[1]	66	1		T43	1	T53	2	T148	1
auto[2281701376:2415919103]	auto[0]	48	1		T43	1	T45	1	T52	1
auto[2281701376:2415919103]	auto[1]	66	1		T100	1	T23	1	T56	1
auto[2415919104:2550136831]	auto[0]	44	1		T43	1	T149	1	T106	2
auto[2415919104:2550136831]	auto[1]	67	1		T100	1	T56	1	T88	2
auto[2550136832:2684354559]	auto[0]	45	1		T118	1	T149	1	T49	1
auto[2550136832:2684354559]	auto[1]	43	1		T118	1	T53	1	T54	1
auto[2684354560:2818572287]	auto[0]	50	1		T15	2	T43	1	T54	1
auto[2684354560:2818572287]	auto[1]	37	1		T22	1	T148	1	T45	1
auto[2818572288:2952790015]	auto[0]	57	1		T43	2	T100	1	T36	1
auto[2818572288:2952790015]	auto[1]	67	1		T15	1	T43	1	T129	1
auto[2952790016:3087007743]	auto[0]	50	1		T23	1	T101	1	T54	1
auto[2952790016:3087007743]	auto[1]	54	1		T7	1	T53	1	T49	1
auto[3087007744:3221225471]	auto[0]	43	1		T49	1	T89	1	T54	1
auto[3087007744:3221225471]	auto[1]	65	1		T100	1	T106	1	T54	2
auto[3221225472:3355443199]	auto[0]	26	1		T7	1	T279	1	T287	1
auto[3221225472:3355443199]	auto[1]	64	1		T2	1	T148	1	T56	1
auto[3355443200:3489660927]	auto[0]	54	1		T15	1	T43	2	T100	1
auto[3355443200:3489660927]	auto[1]	51	1		T56	1	T49	1	T134	1
auto[3489660928:3623878655]	auto[0]	40	1		T49	1	T52	1	T106	1
auto[3489660928:3623878655]	auto[1]	54	1		T100	1	T7	1	T214	1
auto[3623878656:3758096383]	auto[0]	38	1		T15	1	T149	1	T54	1
auto[3623878656:3758096383]	auto[1]	63	1		T118	1	T43	1	T126	1
auto[3758096384:3892314111]	auto[0]	53	1		T49	1	T108	1	T86	1
auto[3758096384:3892314111]	auto[1]	55	1		T43	1	T53	1	T49	1
auto[3892314112:4026531839]	auto[0]	51	1		T21	1	T125	1	T45	1
auto[3892314112:4026531839]	auto[1]	60	1		T100	1	T133	1	T215	1
auto[4026531840:4160749567]	auto[0]	54	1		T7	1	T45	1	T56	1
auto[4026531840:4160749567]	auto[1]	53	1		T212	1	T100	1	T7	2
auto[4160749568:4294967295]	auto[0]	45	1		T2	1	T43	2	T100	1
auto[4160749568:4294967295]	auto[1]	72	1		T43	2	T126	1	T149	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1626

T15

T21

auto[1]

1781

T15

T25

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
auto[0:134217727]	109	1		T2	1	T21	1	T118	1
auto[134217728:268435455]	111	1		T114	1	T209	1	T43	1
auto[268435456:402653183]	96	1		T15	1	T49	3	T101	2
auto[402653184:536870911]	114	1		T43	1	T125	1	T23	1
auto[536870912:671088639]	121	1		T25	1	T118	1	T43	2
auto[671088640:805306367]	113	1		T21	1	T43	1	T7	1
auto[805306368:939524095]	114	1		T118	1	T43	1	T126	1
auto[939524096:1073741823]	100	1		T22	1	T43	1	T100	1
auto[1073741824:1207959551]	87	1		T212	1	T43	1	T125	1
auto[1207959552:1342177279]	113	1		T100	1	T88	1	T54	4
auto[1342177280:1476395007]	105	1		T15	1	T21	1	T213	1
auto[1476395008:1610612735]	121	1		T205	1	T43	2	T100	1
auto[1610612736:1744830463]	112	1		T15	1	T47	1	T125	1
auto[1744830464:1879048191]	99	1		T2	1	T15	1	T205	1
auto[1879048192:2013265919]	116	1		T114	1	T43	2	T7	1
auto[2013265920:2147483647]	105	1		T43	1	T100	2	T126	1
auto[2147483648:2281701375]	102	1		T2	1	T15	1	T36	1
auto[2281701376:2415919103]	111	1		T2	1	T26	1	T212	1
auto[2415919104:2550136831]	104	1		T209	1	T43	1	T129	1
auto[2550136832:2684354559]	104	1		T43	1	T7	1	T45	1
auto[2684354560:2818572287]	118	1		T15	1	T212	1	T43	1
auto[2818572288:2952790015]	109	1		T7	1	T53	2	T56	2
auto[2952790016:3087007743]	107	1		T118	1	T22	1	T212	1
auto[3087007744:3221225471]	101	1		T43	2	T100	1	T7	1
auto[3221225472:3355443199]	94	1		T22	2	T43	2	T100	1
auto[3355443200:3489660927]	99	1		T25	1	T21	1	T43	1
auto[3489660928:3623878655]	107	1		T15	1	T209	1	T100	2
auto[3623878656:3758096383]	90	1		T100	2	T45	1	T129	1
auto[3758096384:3892314111]	102	1		T21	1	T118	1	T43	2
auto[3892314112:4026531839]	123	1		T205	1	T43	2	T7	1
auto[4026531840:4160749567]	94	1		T100	3	T129	1	T52	1
auto[4160749568:4294967295]	106	1		T43	1	T125	1	T7	1

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS	TEST	COUNT	TEST	COUNT	TEST	COUNT
auto[0:134217727]	auto[0]	53	1		T21	1	T114	1	T43	1
auto[0:134217727]	auto[1]	56	1		T2	1	T118	1	T114	1
auto[134217728:268435455]	auto[0]	49	1		T209	1	T43	1	T53	1
auto[134217728:268435455]	auto[1]	62	1		T114	1	T7	1	T56	1
auto[268435456:402653183]	auto[0]	42	1		T49	1	T54	1	T240	1
auto[268435456:402653183]	auto[1]	54	1		T15	1	T49	2	T101	2
auto[402653184:536870911]	auto[0]	61	1		T43	1	T23	1	T49	1
auto[402653184:536870911]	auto[1]	53	1		T125	1	T53	1	T8	1
auto[536870912:671088639]	auto[0]	58	1		T43	1	T7	1	T148	1
auto[536870912:671088639]	auto[1]	63	1		T25	1	T118	1	T43	1
auto[671088640:805306367]	auto[0]	47	1		T21	1	T8	1	T89	1
auto[671088640:805306367]	auto[1]	66	1		T43	1	T7	1	T49	1
auto[805306368:939524095]	auto[0]	50	1		T118	1	T43	1	T126	1
auto[805306368:939524095]	auto[1]	64	1		T53	1	T67	1	T106	2
auto[939524096:1073741823]	auto[0]	44	1		T43	1	T53	1	T45	1
auto[939524096:1073741823]	auto[1]	56	1		T22	1	T100	1	T148	1
auto[1073741824:1207959551]	auto[0]	47	1		T101	1	T86	2	T240	1
auto[1073741824:1207959551]	auto[1]	40	1		T212	1	T43	1	T125	1
auto[1207959552:1342177279]	auto[0]	50	1		T86	1	T211	2	T225	1
auto[1207959552:1342177279]	auto[1]	63	1		T100	1	T88	1	T54	4
auto[1342177280:1476395007]	auto[0]	49	1		T15	1	T21	1	T24	1
auto[1342177280:1476395007]	auto[1]	56	1		T213	1	T148	1	T56	1
auto[1476395008:1610612735]	auto[0]	62	1		T205	1	T43	2	T100	1
auto[1476395008:1610612735]	auto[1]	59	1		T45	1	T31	1	T134	2
auto[1610612736:1744830463]	auto[0]	48	1		T15	1	T54	1	T108	1
auto[1610612736:1744830463]	auto[1]	64	1		T47	1	T125	1	T7	1
auto[1744830464:1879048191]	auto[0]	49	1		T2	1	T15	1	T43	1
auto[1744830464:1879048191]	auto[1]	50	1		T205	1	T54	1	T59	1
auto[1879048192:2013265919]	auto[0]	56	1		T43	2	T23	1	T126	1
auto[1879048192:2013265919]	auto[1]	60	1		T114	1	T7	1	T148	1
auto[2013265920:2147483647]	auto[0]	51	1		T43	1	T48	1	T54	1
auto[2013265920:2147483647]	auto[1]	54	1		T100	2	T126	1	T53	1
auto[2147483648:2281701375]	auto[0]	48	1		T15	1	T36	1	T45	1
auto[2147483648:2281701375]	auto[1]	54	1		T2	1	T49	1	T54	1
auto[2281701376:2415919103]	auto[0]	47	1		T2	1	T212	1	T43	1
auto[2281701376:2415919103]	auto[1]	64	1		T26	1	T7	1	T126	1
auto[2415919104:2550136831]	auto[0]	46	1		T209	1	T43	1	T130	1
auto[2415919104:2550136831]	auto[1]	58	1		T129	1	T214	1	T54	1
auto[2550136832:2684354559]	auto[0]	49	1		T7	1	T45	1	T129	1
auto[2550136832:2684354559]	auto[1]	55	1		T43	1	T133	1	T8	1
auto[2684354560:2818572287]	auto[0]	69	1		T15	1	T7	1	T36	1
auto[2684354560:2818572287]	auto[1]	49	1		T212	1	T43	1	T106	1
auto[2818572288:2952790015]	auto[0]	53	1		T129	1	T86	1	T282	1
auto[2818572288:2952790015]	auto[1]	56	1		T7	1	T53	2	T56	2
auto[2952790016:3087007743]	auto[0]	61	1		T22	1	T149	1	T49	1
auto[2952790016:3087007743]	auto[1]	46	1		T118	1	T212	1	T44	2
auto[3087007744:3221225471]	auto[0]	52	1		T43	2	T53	1	T106	1
auto[3087007744:3221225471]	auto[1]	49	1		T100	1	T7	1	T126	1
auto[3221225472:3355443199]	auto[0]	45	1		T22	1	T100	1	T130	1
auto[3221225472:3355443199]	auto[1]	49	1		T22	1	T43	2	T7	1
auto[3355443200:3489660927]	auto[0]	53	1		T21	1	T7	1	T49	1
auto[3355443200:3489660927]	auto[1]	46	1		T25	1	T43	1	T100	1
auto[3489660928:3623878655]	auto[0]	53	1		T15	1	T209	1	T44	1
auto[3489660928:3623878655]	auto[1]	54	1		T100	2	T56	1	T149	1
auto[3623878656:3758096383]	auto[0]	40	1		T45	1	T129	1	T240	1
auto[3623878656:3758096383]	auto[1]	50	1		T100	2	T133	1	T49	1
auto[3758096384:3892314111]	auto[0]	46	1		T21	1	T43	2	T53	1
auto[3758096384:3892314111]	auto[1]	56	1		T118	1	T100	1	T53	1
auto[3892314112:4026531839]	auto[0]	45	1		T205	1	T7	1	T56	1
auto[3892314112:4026531839]	auto[1]	78	1		T43	2	T23	1	T56	1
auto[4026531840:4160749567]	auto[0]	43	1		T100	2	T129	1	T54	1
auto[4026531840:4160749567]	auto[1]	51	1		T100	1	T52	1	T135	1
auto[4160749568:4294967295]	auto[0]	60	1		T125	1	T45	1	T130	1
auto[4160749568:4294967295]	auto[1]	46	1		T43	1	T7	1	T49	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1595

T15

T25

auto[1]

1812

T15

T25