Unified Coverage Report :: Group Instance : salt_0

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2967

1

T2

4

T15

7

T25

2

auto[1]

289

1

T2

6

T148

9

T149

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	114	1			T114	1		T212	2		T7	1
auto[134217728:268435455]	101	1			T2	1		T100	1		T7	1
auto[268435456:402653183]	91	1			T2	1		T21	1		T43	1
auto[402653184:536870911]	121	1			T43	1		T100	1		T53	1
auto[536870912:671088639]	110	1			T43	1		T23	1		T126	1
auto[671088640:805306367]	90	1			T118	1		T7	1		T23	1
auto[805306368:939524095]	104	1			T22	1		T100	1		T53	1
auto[939524096:1073741823]	102	1			T15	1		T21	1		T43	1
auto[1073741824:1207959551]	109	1			T2	1		T100	1		T125	1
auto[1207959552:1342177279]	98	1			T118	1		T212	1		T7	1
auto[1342177280:1476395007]	95	1			T100	3		T53	2		T149	1
auto[1476395008:1610612735]	117	1			T2	1		T15	1		T212	1
auto[1610612736:1744830463]	100	1			T26	1		T209	1		T43	2
auto[1744830464:1879048191]	109	1			T25	1		T43	1		T53	2
auto[1879048192:2013265919]	103	1			T2	1		T43	2		T100	2
auto[2013265920:2147483647]	90	1			T22	1		T114	1		T43	1
auto[2147483648:2281701375]	105	1			T2	1		T21	1		T118	1
auto[2281701376:2415919103]	93	1			T2	1		T15	1		T21	1
auto[2415919104:2550136831]	90	1			T118	1		T100	1		T7	1
auto[2550136832:2684354559]	100	1			T22	1		T43	1		T148	1
auto[2684354560:2818572287]	88	1			T209	1		T43	1		T100	1
auto[2818572288:2952790015]	103	1			T114	1		T43	2		T7	1
auto[2952790016:3087007743]	93	1			T25	1		T205	1		T126	1
auto[3087007744:3221225471]	110	1			T15	1		T125	1		T45	2
auto[3221225472:3355443199]	109	1			T2	1		T15	1		T43	1
auto[3355443200:3489660927]	106	1			T43	3		T23	1		T126	1
auto[3489660928:3623878655]	91	1			T7	1		T53	2		T148	1
auto[3623878656:3758096383]	103	1			T209	1		T43	2		T100	1
auto[3758096384:3892314111]	117	1			T2	1		T205	1		T43	1
auto[3892314112:4026531839]	105	1			T15	1		T21	1		T47	1
auto[4026531840:4160749567]	88	1			T15	1		T22	1		T129	1
auto[4160749568:4294967295]	101	1			T2	1		T118	1		T205	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	107	1			T114	1		T212	2		T7	1
auto[0:134217727]	auto[1]	7	1			T139	2		T371	1		T369	1
auto[134217728:268435455]	auto[0]	92	1			T2	1		T100	1		T7	1
auto[134217728:268435455]	auto[1]	9	1			T148	1		T137	1		T140	1
auto[268435456:402653183]	auto[0]	85	1			T21	1		T43	1		T100	1
auto[268435456:402653183]	auto[1]	6	1			T2	1		T137	1		T407	1
auto[402653184:536870911]	auto[0]	106	1			T43	1		T100	1		T53	1
auto[402653184:536870911]	auto[1]	15	1			T148	1		T136	2		T360	1
auto[536870912:671088639]	auto[0]	102	1			T43	1		T23	1		T126	1
auto[536870912:671088639]	auto[1]	8	1			T371	1		T298	1		T319	1
auto[671088640:805306367]	auto[0]	82	1			T118	1		T7	1		T23	1
auto[671088640:805306367]	auto[1]	8	1			T237	1		T319	1		T407	1
auto[805306368:939524095]	auto[0]	96	1			T22	1		T100	1		T53	1
auto[805306368:939524095]	auto[1]	8	1			T360	1		T391	1		T369	1
auto[939524096:1073741823]	auto[0]	92	1			T15	1		T21	1		T43	1
auto[939524096:1073741823]	auto[1]	10	1			T148	1		T137	1		T356	2
auto[1073741824:1207959551]	auto[0]	94	1			T100	1		T125	1		T44	1
auto[1073741824:1207959551]	auto[1]	15	1			T2	1		T137	2		T360	1
auto[1207959552:1342177279]	auto[0]	84	1			T118	1		T212	1		T7	1
auto[1207959552:1342177279]	auto[1]	14	1			T137	1		T140	1		T356	1
auto[1342177280:1476395007]	auto[0]	87	1			T100	3		T53	2		T149	1
auto[1342177280:1476395007]	auto[1]	8	1			T137	1		T140	1		T379	1
auto[1476395008:1610612735]	auto[0]	108	1			T15	1		T212	1		T53	1
auto[1476395008:1610612735]	auto[1]	9	1			T2	1		T129	1		T356	1
auto[1610612736:1744830463]	auto[0]	96	1			T26	1		T209	1		T43	2
auto[1610612736:1744830463]	auto[1]	4	1			T139	1		T298	1		T411	1
auto[1744830464:1879048191]	auto[0]	97	1			T25	1		T43	1		T53	2
auto[1744830464:1879048191]	auto[1]	12	1			T148	1		T134	1		T299	2
auto[1879048192:2013265919]	auto[0]	95	1			T2	1		T43	2		T100	2
auto[1879048192:2013265919]	auto[1]	8	1			T148	1		T379	1		T357	1
auto[2013265920:2147483647]	auto[0]	82	1			T22	1		T114	1		T43	1
auto[2013265920:2147483647]	auto[1]	8	1			T149	1		T360	1		T418	1
auto[2147483648:2281701375]	auto[0]	99	1			T21	1		T118	1		T213	1
auto[2147483648:2281701375]	auto[1]	6	1			T2	1		T129	1		T134	1
auto[2281701376:2415919103]	auto[0]	84	1			T15	1		T21	1		T43	1
auto[2281701376:2415919103]	auto[1]	9	1			T2	1		T137	1		T371	1
auto[2415919104:2550136831]	auto[0]	85	1			T118	1		T100	1		T7	1
auto[2415919104:2550136831]	auto[1]	5	1			T391	1		T407	1		T411	1
auto[2550136832:2684354559]	auto[0]	93	1			T22	1		T43	1		T148	1
auto[2550136832:2684354559]	auto[1]	7	1			T283	1		T356	1		T412	1
auto[2684354560:2818572287]	auto[0]	77	1			T209	1		T43	1		T100	1
auto[2684354560:2818572287]	auto[1]	11	1			T148	1		T136	1		T356	1
auto[2818572288:2952790015]	auto[0]	88	1			T114	1		T43	2		T7	1
auto[2818572288:2952790015]	auto[1]	15	1			T134	3		T140	1		T283	1
auto[2952790016:3087007743]	auto[0]	83	1			T25	1		T205	1		T126	1
auto[2952790016:3087007743]	auto[1]	10	1			T137	2		T383	1		T140	1
auto[3087007744:3221225471]	auto[0]	100	1			T15	1		T125	1		T45	2
auto[3087007744:3221225471]	auto[1]	10	1			T137	1		T328	1		T299	1
auto[3221225472:3355443199]	auto[0]	97	1			T15	1		T43	1		T7	1
auto[3221225472:3355443199]	auto[1]	12	1			T2	1		T139	1		T140	1
auto[3355443200:3489660927]	auto[0]	97	1			T43	3		T23	1		T126	1
auto[3355443200:3489660927]	auto[1]	9	1			T148	2		T135	1		T383	1
auto[3489660928:3623878655]	auto[0]	83	1			T7	1		T53	2		T27	1
auto[3489660928:3623878655]	auto[1]	8	1			T148	1		T137	1		T360	1
auto[3623878656:3758096383]	auto[0]	93	1			T209	1		T43	2		T100	1
auto[3623878656:3758096383]	auto[1]	10	1			T139	2		T198	1		T412	1
auto[3758096384:3892314111]	auto[0]	108	1			T2	1		T205	1		T43	1
auto[3758096384:3892314111]	auto[1]	9	1			T135	1		T379	2		T356	2
auto[3892314112:4026531839]	auto[0]	95	1			T15	1		T21	1		T47	1
auto[3892314112:4026531839]	auto[1]	10	1			T134	1		T137	1		T360	1
auto[4026531840:4160749567]	auto[0]	86	1			T15	1		T22	1		T133	1
auto[4026531840:4160749567]	auto[1]	2	1			T129	1		T137	1		-	-
auto[4160749568:4294967295]	auto[0]	94	1			T2	1		T118	1		T205	1
auto[4160749568:4294967295]	auto[1]	7	1			T140	1		T356	1		T412	1