Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.94 99.07 97.99 99.36 100.00 99.11 98.41 91.63


Total test records in report: 1074
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T1005 /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.3430443690 Mar 17 02:12:09 PM PDT 24 Mar 17 02:12:40 PM PDT 24 2099992415 ps
T1006 /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.1778844227 Mar 17 02:12:51 PM PDT 24 Mar 17 02:13:00 PM PDT 24 1594997391 ps
T1007 /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.2497387410 Mar 17 02:12:55 PM PDT 24 Mar 17 02:12:59 PM PDT 24 144739170 ps
T1008 /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.3657742197 Mar 17 02:12:30 PM PDT 24 Mar 17 02:12:32 PM PDT 24 83763546 ps
T1009 /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.4002486448 Mar 17 02:12:19 PM PDT 24 Mar 17 02:12:21 PM PDT 24 99032129 ps
T1010 /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.1560936357 Mar 17 02:12:58 PM PDT 24 Mar 17 02:13:01 PM PDT 24 189215404 ps
T1011 /workspace/coverage/cover_reg_top/35.keymgr_intr_test.273297607 Mar 17 02:13:21 PM PDT 24 Mar 17 02:13:23 PM PDT 24 15895984 ps
T1012 /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.2141858102 Mar 17 02:13:03 PM PDT 24 Mar 17 02:13:06 PM PDT 24 76154520 ps
T1013 /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.921028235 Mar 17 02:12:48 PM PDT 24 Mar 17 02:12:53 PM PDT 24 119903436 ps
T1014 /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.1282118746 Mar 17 02:13:02 PM PDT 24 Mar 17 02:13:05 PM PDT 24 328439886 ps
T1015 /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.1941258692 Mar 17 02:12:57 PM PDT 24 Mar 17 02:12:58 PM PDT 24 106943254 ps
T1016 /workspace/coverage/cover_reg_top/0.keymgr_intr_test.1809975567 Mar 17 02:12:09 PM PDT 24 Mar 17 02:12:11 PM PDT 24 9749313 ps
T1017 /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.4146286959 Mar 17 02:12:58 PM PDT 24 Mar 17 02:13:00 PM PDT 24 209768285 ps
T1018 /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.345425128 Mar 17 02:13:13 PM PDT 24 Mar 17 02:13:14 PM PDT 24 25477196 ps
T1019 /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.1090940625 Mar 17 02:12:12 PM PDT 24 Mar 17 02:12:13 PM PDT 24 17894750 ps
T160 /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.3168261489 Mar 17 02:12:19 PM PDT 24 Mar 17 02:12:26 PM PDT 24 251985125 ps
T1020 /workspace/coverage/cover_reg_top/12.keymgr_intr_test.3960168169 Mar 17 02:12:57 PM PDT 24 Mar 17 02:12:57 PM PDT 24 34127172 ps
T164 /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.2524650997 Mar 17 02:12:56 PM PDT 24 Mar 17 02:13:04 PM PDT 24 379331402 ps
T1021 /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.1840136646 Mar 17 02:12:40 PM PDT 24 Mar 17 02:12:43 PM PDT 24 133239032 ps
T1022 /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.1599616851 Mar 17 02:12:09 PM PDT 24 Mar 17 02:12:21 PM PDT 24 496189553 ps
T1023 /workspace/coverage/cover_reg_top/32.keymgr_intr_test.2853038009 Mar 17 02:13:21 PM PDT 24 Mar 17 02:13:23 PM PDT 24 15186590 ps
T1024 /workspace/coverage/cover_reg_top/34.keymgr_intr_test.3282014465 Mar 17 02:13:27 PM PDT 24 Mar 17 02:13:28 PM PDT 24 31974255 ps
T1025 /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.1326061548 Mar 17 02:12:58 PM PDT 24 Mar 17 02:12:59 PM PDT 24 78689421 ps
T1026 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.3721241247 Mar 17 02:12:58 PM PDT 24 Mar 17 02:13:08 PM PDT 24 911431397 ps
T1027 /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.958147176 Mar 17 02:13:14 PM PDT 24 Mar 17 02:13:16 PM PDT 24 60349175 ps
T1028 /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.3730483959 Mar 17 02:12:54 PM PDT 24 Mar 17 02:12:56 PM PDT 24 31941104 ps
T1029 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.2506707463 Mar 17 02:12:34 PM PDT 24 Mar 17 02:12:41 PM PDT 24 222242520 ps
T1030 /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.3193834836 Mar 17 02:13:14 PM PDT 24 Mar 17 02:13:16 PM PDT 24 42095782 ps
T1031 /workspace/coverage/cover_reg_top/14.keymgr_intr_test.125184957 Mar 17 02:13:05 PM PDT 24 Mar 17 02:13:06 PM PDT 24 12255899 ps
T1032 /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.2123648464 Mar 17 02:12:08 PM PDT 24 Mar 17 02:12:10 PM PDT 24 128569345 ps
T1033 /workspace/coverage/cover_reg_top/26.keymgr_intr_test.1360290493 Mar 17 02:13:22 PM PDT 24 Mar 17 02:13:23 PM PDT 24 35485844 ps
T1034 /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.1162475936 Mar 17 02:12:18 PM PDT 24 Mar 17 02:12:20 PM PDT 24 26533210 ps
T1035 /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.4166523045 Mar 17 02:13:03 PM PDT 24 Mar 17 02:13:05 PM PDT 24 106904217 ps
T1036 /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.2516918476 Mar 17 02:12:25 PM PDT 24 Mar 17 02:12:26 PM PDT 24 143984358 ps
T1037 /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.2062168678 Mar 17 02:13:07 PM PDT 24 Mar 17 02:13:10 PM PDT 24 557677648 ps
T158 /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.2596300749 Mar 17 02:12:57 PM PDT 24 Mar 17 02:13:09 PM PDT 24 768762439 ps
T1038 /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.4011033497 Mar 17 02:12:58 PM PDT 24 Mar 17 02:13:03 PM PDT 24 558786969 ps
T1039 /workspace/coverage/cover_reg_top/20.keymgr_intr_test.2081267841 Mar 17 02:13:15 PM PDT 24 Mar 17 02:13:16 PM PDT 24 9223835 ps
T1040 /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.2432500708 Mar 17 02:13:13 PM PDT 24 Mar 17 02:13:18 PM PDT 24 1177772107 ps
T1041 /workspace/coverage/cover_reg_top/18.keymgr_intr_test.1339632568 Mar 17 02:13:16 PM PDT 24 Mar 17 02:13:16 PM PDT 24 15225410 ps
T1042 /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.519305696 Mar 17 02:12:59 PM PDT 24 Mar 17 02:13:01 PM PDT 24 71624240 ps
T1043 /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.1969881800 Mar 17 02:12:51 PM PDT 24 Mar 17 02:12:52 PM PDT 24 24254433 ps
T1044 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.4106235109 Mar 17 02:12:40 PM PDT 24 Mar 17 02:12:47 PM PDT 24 185749014 ps
T1045 /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.1303163868 Mar 17 02:12:30 PM PDT 24 Mar 17 02:12:34 PM PDT 24 168155211 ps
T1046 /workspace/coverage/cover_reg_top/31.keymgr_intr_test.846694191 Mar 17 02:13:23 PM PDT 24 Mar 17 02:13:24 PM PDT 24 40754591 ps
T1047 /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.1145201571 Mar 17 02:13:10 PM PDT 24 Mar 17 02:13:12 PM PDT 24 36911558 ps
T165 /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.1451346932 Mar 17 02:13:16 PM PDT 24 Mar 17 02:13:20 PM PDT 24 246062550 ps
T1048 /workspace/coverage/cover_reg_top/21.keymgr_intr_test.1433167853 Mar 17 02:13:17 PM PDT 24 Mar 17 02:13:18 PM PDT 24 10894129 ps
T1049 /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.3963629861 Mar 17 02:13:04 PM PDT 24 Mar 17 02:13:07 PM PDT 24 60908441 ps
T1050 /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.4158652348 Mar 17 02:12:12 PM PDT 24 Mar 17 02:12:20 PM PDT 24 572730483 ps
T1051 /workspace/coverage/cover_reg_top/1.keymgr_intr_test.2513286341 Mar 17 02:12:15 PM PDT 24 Mar 17 02:12:16 PM PDT 24 18973276 ps
T1052 /workspace/coverage/cover_reg_top/9.keymgr_intr_test.2122904412 Mar 17 02:12:53 PM PDT 24 Mar 17 02:12:54 PM PDT 24 10455098 ps
T1053 /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.327110749 Mar 17 02:12:35 PM PDT 24 Mar 17 02:12:37 PM PDT 24 22941773 ps
T1054 /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.4187393517 Mar 17 02:12:47 PM PDT 24 Mar 17 02:12:52 PM PDT 24 344440446 ps
T1055 /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.1566211015 Mar 17 02:12:13 PM PDT 24 Mar 17 02:12:18 PM PDT 24 134511544 ps
T1056 /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.2800886338 Mar 17 02:12:18 PM PDT 24 Mar 17 02:12:19 PM PDT 24 47392177 ps
T1057 /workspace/coverage/cover_reg_top/5.keymgr_intr_test.4260794485 Mar 17 02:12:35 PM PDT 24 Mar 17 02:12:36 PM PDT 24 39832710 ps
T1058 /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.4069428524 Mar 17 02:12:57 PM PDT 24 Mar 17 02:12:59 PM PDT 24 155242770 ps
T1059 /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.592966347 Mar 17 02:12:36 PM PDT 24 Mar 17 02:12:42 PM PDT 24 1107986970 ps
T1060 /workspace/coverage/cover_reg_top/17.keymgr_intr_test.1017332385 Mar 17 02:13:13 PM PDT 24 Mar 17 02:13:14 PM PDT 24 33892879 ps
T1061 /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.2255002986 Mar 17 02:13:17 PM PDT 24 Mar 17 02:13:20 PM PDT 24 115095261 ps
T1062 /workspace/coverage/cover_reg_top/4.keymgr_intr_test.3546422527 Mar 17 02:12:29 PM PDT 24 Mar 17 02:12:29 PM PDT 24 47400849 ps
T1063 /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.2945521140 Mar 17 02:12:51 PM PDT 24 Mar 17 02:12:52 PM PDT 24 39715608 ps
T1064 /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.809525168 Mar 17 02:12:01 PM PDT 24 Mar 17 02:12:04 PM PDT 24 98278808 ps
T1065 /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.160159130 Mar 17 02:12:47 PM PDT 24 Mar 17 02:12:55 PM PDT 24 615676396 ps
T1066 /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.22593178 Mar 17 02:12:06 PM PDT 24 Mar 17 02:12:08 PM PDT 24 24268039 ps
T1067 /workspace/coverage/cover_reg_top/48.keymgr_intr_test.2376483985 Mar 17 02:13:30 PM PDT 24 Mar 17 02:13:31 PM PDT 24 14552931 ps
T1068 /workspace/coverage/cover_reg_top/13.keymgr_intr_test.3665778557 Mar 17 02:13:07 PM PDT 24 Mar 17 02:13:08 PM PDT 24 12931496 ps
T1069 /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.3127755882 Mar 17 02:12:18 PM PDT 24 Mar 17 02:12:20 PM PDT 24 48267489 ps
T1070 /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.195652642 Mar 17 02:12:36 PM PDT 24 Mar 17 02:12:38 PM PDT 24 206430232 ps
T1071 /workspace/coverage/cover_reg_top/27.keymgr_intr_test.3297767003 Mar 17 02:13:20 PM PDT 24 Mar 17 02:13:21 PM PDT 24 23853067 ps
T1072 /workspace/coverage/cover_reg_top/44.keymgr_intr_test.3424792408 Mar 17 02:13:27 PM PDT 24 Mar 17 02:13:28 PM PDT 24 84297806 ps
T1073 /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.1855956907 Mar 17 02:13:03 PM PDT 24 Mar 17 02:13:05 PM PDT 24 187067406 ps
T1074 /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.11370978 Mar 17 02:12:30 PM PDT 24 Mar 17 02:12:38 PM PDT 24 713996694 ps

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.525350892
Short name T15
Test name
Test status
Simulation time 803039490 ps
CPU time 9.09 seconds
Started Mar 17 02:43:50 PM PDT 24
Finished Mar 17 02:43:59 PM PDT 24
Peak memory 210180 kb
Host smart-55103316-876a-4e73-8dad-a0472132a204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=525350892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.525350892
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.2051894263
Short name T43
Test name
Test status
Simulation time 1510305284 ps
CPU time 44.83 seconds
Started Mar 17 02:44:28 PM PDT 24
Finished Mar 17 02:45:14 PM PDT 24
Peak memory 222648 kb
Host smart-eef70f10-5034-44c4-b50c-0da29f38c5fa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2051894263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.2051894263
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.1060661419
Short name T59
Test name
Test status
Simulation time 1565420717 ps
CPU time 44 seconds
Started Mar 17 02:43:17 PM PDT 24
Finished Mar 17 02:44:01 PM PDT 24
Peak memory 215632 kb
Host smart-f9ce1086-0929-41a2-aaa3-eb0a3672b0be
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1060661419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.1060661419
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.2814122175
Short name T9
Test name
Test status
Simulation time 561100479 ps
CPU time 10.64 seconds
Started Mar 17 02:42:36 PM PDT 24
Finished Mar 17 02:42:46 PM PDT 24
Peak memory 231308 kb
Host smart-96a17560-216b-4210-9047-daed76f1c599
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814122175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.2814122175
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.1044770105
Short name T54
Test name
Test status
Simulation time 3160163917 ps
CPU time 35.04 seconds
Started Mar 17 02:44:22 PM PDT 24
Finished Mar 17 02:44:57 PM PDT 24
Peak memory 223108 kb
Host smart-9b3c4eca-24b4-4fa3-8dfd-fba48b2d2909
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044770105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.1044770105
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_stress_all_with_rand_reset.2497338078
Short name T122
Test name
Test status
Simulation time 584177748 ps
CPU time 20.75 seconds
Started Mar 17 02:43:55 PM PDT 24
Finished Mar 17 02:44:16 PM PDT 24
Peak memory 223132 kb
Host smart-075f5ac4-2788-4e80-89e1-dcd7cd3996ee
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497338078 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all_with_rand_reset.2497338078
Directory /workspace/21.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.1088437873
Short name T2
Test name
Test status
Simulation time 633882385 ps
CPU time 8.75 seconds
Started Mar 17 02:43:59 PM PDT 24
Finished Mar 17 02:44:08 PM PDT 24
Peak memory 214680 kb
Host smart-6bf22bb1-0b94-4b8c-a763-6ffc6a6743d0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1088437873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.1088437873
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.4198099818
Short name T49
Test name
Test status
Simulation time 1744653183 ps
CPU time 19.52 seconds
Started Mar 17 02:44:16 PM PDT 24
Finished Mar 17 02:44:36 PM PDT 24
Peak memory 216908 kb
Host smart-7a184d20-0c5d-43fe-aff9-607793124da2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198099818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.4198099818
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.807731379
Short name T109
Test name
Test status
Simulation time 554486142 ps
CPU time 8.08 seconds
Started Mar 17 02:12:18 PM PDT 24
Finished Mar 17 02:12:27 PM PDT 24
Peak memory 214344 kb
Host smart-083695f3-b9fb-4f7b-8df2-6de883314221
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807731379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.k
eymgr_shadow_reg_errors_with_csr_rw.807731379
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.2133256780
Short name T55
Test name
Test status
Simulation time 4723487735 ps
CPU time 70.12 seconds
Started Mar 17 02:42:57 PM PDT 24
Finished Mar 17 02:44:07 PM PDT 24
Peak memory 223060 kb
Host smart-cf683f41-99dd-4557-bb88-1e2c17d39282
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133256780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.2133256780
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.2371896970
Short name T11
Test name
Test status
Simulation time 1185257741 ps
CPU time 5.78 seconds
Started Mar 17 02:42:28 PM PDT 24
Finished Mar 17 02:42:34 PM PDT 24
Peak memory 223312 kb
Host smart-b5089789-3785-4e0c-878b-33722bdaabc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371896970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.2371896970
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.2179105598
Short name T356
Test name
Test status
Simulation time 2706062143 ps
CPU time 38.61 seconds
Started Mar 17 02:45:10 PM PDT 24
Finished Mar 17 02:45:49 PM PDT 24
Peak memory 215464 kb
Host smart-78affbaa-0812-4091-bab6-eb5f5b958c89
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2179105598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.2179105598
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.2623378018
Short name T21
Test name
Test status
Simulation time 376083533 ps
CPU time 5.75 seconds
Started Mar 17 02:42:58 PM PDT 24
Finished Mar 17 02:43:04 PM PDT 24
Peak memory 209716 kb
Host smart-9e65aed5-7d32-4ae8-a1f4-5aa21b32321b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623378018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.2623378018
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_stress_all_with_rand_reset.326516842
Short name T7
Test name
Test status
Simulation time 1690336341 ps
CPU time 21.48 seconds
Started Mar 17 02:43:20 PM PDT 24
Finished Mar 17 02:43:42 PM PDT 24
Peak memory 223004 kb
Host smart-2f4b499b-9400-4e24-a64b-295e5275ed0b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=326516842 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all_with_rand_reset.326516842
Directory /workspace/11.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.1826927103
Short name T140
Test name
Test status
Simulation time 1818558592 ps
CPU time 21.93 seconds
Started Mar 17 02:43:55 PM PDT 24
Finished Mar 17 02:44:17 PM PDT 24
Peak memory 222980 kb
Host smart-0d2cd397-67c6-400a-9725-1199a23a383d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1826927103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.1826927103
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.289273924
Short name T168
Test name
Test status
Simulation time 98814264 ps
CPU time 4.32 seconds
Started Mar 17 02:45:00 PM PDT 24
Finished Mar 17 02:45:04 PM PDT 24
Peak memory 215876 kb
Host smart-ead86033-c899-4018-87c5-ec4c15b29f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289273924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.289273924
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.1839219367
Short name T211
Test name
Test status
Simulation time 189210297 ps
CPU time 9.05 seconds
Started Mar 17 02:44:11 PM PDT 24
Finished Mar 17 02:44:20 PM PDT 24
Peak memory 222884 kb
Host smart-cd0a00df-689a-4ce8-809e-48accec47895
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1839219367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.1839219367
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.1820095029
Short name T238
Test name
Test status
Simulation time 1023580412 ps
CPU time 12.67 seconds
Started Mar 17 02:45:22 PM PDT 24
Finished Mar 17 02:45:35 PM PDT 24
Peak memory 214688 kb
Host smart-a5309150-588f-4492-9777-86baf8177f76
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1820095029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.1820095029
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.1307340533
Short name T148
Test name
Test status
Simulation time 232849368 ps
CPU time 12.82 seconds
Started Mar 17 02:43:32 PM PDT 24
Finished Mar 17 02:43:45 PM PDT 24
Peak memory 215340 kb
Host smart-62553e7a-4409-4c7b-8726-c8e4f14a6023
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1307340533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.1307340533
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.205220179
Short name T68
Test name
Test status
Simulation time 1279767035 ps
CPU time 33.83 seconds
Started Mar 17 02:42:44 PM PDT 24
Finished Mar 17 02:43:18 PM PDT 24
Peak memory 223092 kb
Host smart-e2cc9ee9-ed38-4836-8640-5703496c8e3c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=205220179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.205220179
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.3477087827
Short name T26
Test name
Test status
Simulation time 140469705 ps
CPU time 3.46 seconds
Started Mar 17 02:42:39 PM PDT 24
Finished Mar 17 02:42:42 PM PDT 24
Peak memory 214788 kb
Host smart-d0dc9d4f-18a2-4d41-b9f2-26441d3fd7cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3477087827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.3477087827
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.2643948291
Short name T137
Test name
Test status
Simulation time 166742322 ps
CPU time 9.14 seconds
Started Mar 17 02:44:13 PM PDT 24
Finished Mar 17 02:44:23 PM PDT 24
Peak memory 215280 kb
Host smart-5027787a-c367-4b45-a3de-9c0222567a9a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2643948291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.2643948291
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_stress_all_with_rand_reset.1642168772
Short name T108
Test name
Test status
Simulation time 1059170107 ps
CPU time 25.9 seconds
Started Mar 17 02:44:25 PM PDT 24
Finished Mar 17 02:44:51 PM PDT 24
Peak memory 222972 kb
Host smart-07c76719-8611-4a6c-bb3d-d88be1b7b7cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642168772 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all_with_rand_reset.1642168772
Directory /workspace/31.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.3216316231
Short name T88
Test name
Test status
Simulation time 3980979617 ps
CPU time 44.99 seconds
Started Mar 17 02:42:47 PM PDT 24
Finished Mar 17 02:43:33 PM PDT 24
Peak memory 214892 kb
Host smart-fd1adb30-110a-4ab5-9558-6489d9c79283
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216316231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.3216316231
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.2335574423
Short name T111
Test name
Test status
Simulation time 814010610 ps
CPU time 5.9 seconds
Started Mar 17 02:12:36 PM PDT 24
Finished Mar 17 02:12:42 PM PDT 24
Peak memory 214348 kb
Host smart-c67b3589-d7d4-4462-986a-9ec1fe031ae5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2335574423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.2335574423
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.3776754107
Short name T129
Test name
Test status
Simulation time 1232960012 ps
CPU time 14.95 seconds
Started Mar 17 02:43:52 PM PDT 24
Finished Mar 17 02:44:07 PM PDT 24
Peak memory 216176 kb
Host smart-174d1ed0-3f74-4e49-b532-a4418eb648fe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3776754107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.3776754107
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.2537700625
Short name T207
Test name
Test status
Simulation time 208533881 ps
CPU time 3.74 seconds
Started Mar 17 02:45:19 PM PDT 24
Finished Mar 17 02:45:23 PM PDT 24
Peak memory 214676 kb
Host smart-5886db4a-16a5-44b4-8cbc-aef51f410ba4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537700625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.2537700625
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.1395866556
Short name T32
Test name
Test status
Simulation time 303340375 ps
CPU time 3.42 seconds
Started Mar 17 02:43:24 PM PDT 24
Finished Mar 17 02:43:28 PM PDT 24
Peak memory 214768 kb
Host smart-b1694750-a096-4dcc-adfe-ef8026b1aefd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1395866556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.1395866556
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.2183045892
Short name T411
Test name
Test status
Simulation time 9570914011 ps
CPU time 106.21 seconds
Started Mar 17 02:44:15 PM PDT 24
Finished Mar 17 02:46:01 PM PDT 24
Peak memory 222976 kb
Host smart-3836e99a-1d7d-41ac-bd99-8b40cc022869
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2183045892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.2183045892
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.1666657208
Short name T51
Test name
Test status
Simulation time 109130496871 ps
CPU time 701.21 seconds
Started Mar 17 02:45:19 PM PDT 24
Finished Mar 17 02:57:01 PM PDT 24
Peak memory 218828 kb
Host smart-961fb96a-5e5b-44ef-a34d-c24a74ba54b5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666657208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.1666657208
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.3250937230
Short name T18
Test name
Test status
Simulation time 146214000 ps
CPU time 2.22 seconds
Started Mar 17 02:44:05 PM PDT 24
Finished Mar 17 02:44:07 PM PDT 24
Peak memory 210316 kb
Host smart-7beb77b9-3089-4a9e-a17a-b8c3771a0cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250937230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.3250937230
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.1796365358
Short name T86
Test name
Test status
Simulation time 4107377093 ps
CPU time 29.68 seconds
Started Mar 17 02:45:03 PM PDT 24
Finished Mar 17 02:45:33 PM PDT 24
Peak memory 220784 kb
Host smart-40394ad1-5496-4951-a63a-33afa7963832
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1796365358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.1796365358
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.2905758573
Short name T227
Test name
Test status
Simulation time 748330314 ps
CPU time 30.05 seconds
Started Mar 17 02:44:46 PM PDT 24
Finished Mar 17 02:45:16 PM PDT 24
Peak memory 222900 kb
Host smart-42f59962-b3b3-44ea-acb4-c9b8cfebd6b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905758573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.2905758573
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.1879719407
Short name T371
Test name
Test status
Simulation time 1073741173 ps
CPU time 12.1 seconds
Started Mar 17 02:44:49 PM PDT 24
Finished Mar 17 02:45:01 PM PDT 24
Peak memory 215708 kb
Host smart-1609190a-7bf7-4190-b0fe-cd32d992f767
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1879719407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.1879719407
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.1109709613
Short name T92
Test name
Test status
Simulation time 195712670 ps
CPU time 8.11 seconds
Started Mar 17 02:45:08 PM PDT 24
Finished Mar 17 02:45:18 PM PDT 24
Peak memory 214736 kb
Host smart-51b8fca7-64aa-4e90-8559-bd28a1238ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1109709613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.1109709613
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.1475840752
Short name T131
Test name
Test status
Simulation time 10042988 ps
CPU time 0.7 seconds
Started Mar 17 02:43:11 PM PDT 24
Finished Mar 17 02:43:12 PM PDT 24
Peak memory 206464 kb
Host smart-53c8c2b0-2b51-4be4-9e3d-0cdab8ea3d7d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1475840752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.1475840752
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.3456127915
Short name T40
Test name
Test status
Simulation time 224938543 ps
CPU time 4.74 seconds
Started Mar 17 02:44:10 PM PDT 24
Finished Mar 17 02:44:15 PM PDT 24
Peak memory 210776 kb
Host smart-6095532c-e382-4c0d-b951-6e0a13db5989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456127915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.3456127915
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.2614758594
Short name T42
Test name
Test status
Simulation time 100406158 ps
CPU time 2.8 seconds
Started Mar 17 02:43:27 PM PDT 24
Finished Mar 17 02:43:30 PM PDT 24
Peak memory 209188 kb
Host smart-7dcef558-20ab-4660-b5af-42492555aa4a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2614758594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.2614758594
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.4081702746
Short name T150
Test name
Test status
Simulation time 2399093122 ps
CPU time 9.33 seconds
Started Mar 17 02:13:17 PM PDT 24
Finished Mar 17 02:13:27 PM PDT 24
Peak memory 214248 kb
Host smart-5d9adcea-5535-4aae-b118-c0a8ca31934c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4081702746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.4081702746
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.2727949855
Short name T393
Test name
Test status
Simulation time 2010158837 ps
CPU time 27.48 seconds
Started Mar 17 02:43:16 PM PDT 24
Finished Mar 17 02:43:45 PM PDT 24
Peak memory 215192 kb
Host smart-cb51591d-82bd-4020-ab19-fa2c25854f93
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2727949855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.2727949855
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.1961320074
Short name T74
Test name
Test status
Simulation time 615485996 ps
CPU time 27.15 seconds
Started Mar 17 02:44:55 PM PDT 24
Finished Mar 17 02:45:23 PM PDT 24
Peak memory 217176 kb
Host smart-93d09b6b-722f-4477-86fa-abc5571ab49c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961320074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.1961320074
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.3747571417
Short name T233
Test name
Test status
Simulation time 1733742909 ps
CPU time 49.32 seconds
Started Mar 17 02:42:58 PM PDT 24
Finished Mar 17 02:43:47 PM PDT 24
Peak memory 215136 kb
Host smart-30d50204-b686-4207-9757-eac3baea83fc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3747571417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.3747571417
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.3247876356
Short name T156
Test name
Test status
Simulation time 296516513 ps
CPU time 9.42 seconds
Started Mar 17 02:13:05 PM PDT 24
Finished Mar 17 02:13:15 PM PDT 24
Peak memory 209584 kb
Host smart-717ae19d-a698-4470-a320-a5c3a21e55dd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247876356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.3247876356
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.428277388
Short name T154
Test name
Test status
Simulation time 1470247096 ps
CPU time 33.13 seconds
Started Mar 17 02:12:47 PM PDT 24
Finished Mar 17 02:13:20 PM PDT 24
Peak memory 214008 kb
Host smart-ebf84fc0-e9ac-4e7f-bf3b-7318721ddc2b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428277388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err.
428277388
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.451191398
Short name T408
Test name
Test status
Simulation time 1989525726 ps
CPU time 108.46 seconds
Started Mar 17 02:43:21 PM PDT 24
Finished Mar 17 02:45:10 PM PDT 24
Peak memory 215368 kb
Host smart-9f41c3ac-5a31-46d4-a78e-b079e10a71f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=451191398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.451191398
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.2934254638
Short name T72
Test name
Test status
Simulation time 2280013485 ps
CPU time 46.99 seconds
Started Mar 17 02:43:36 PM PDT 24
Finished Mar 17 02:44:23 PM PDT 24
Peak memory 223128 kb
Host smart-0401de15-bcd0-4c33-85e9-12383d7dc4b4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934254638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.2934254638
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.3247917885
Short name T287
Test name
Test status
Simulation time 407063091 ps
CPU time 21.17 seconds
Started Mar 17 02:44:49 PM PDT 24
Finished Mar 17 02:45:10 PM PDT 24
Peak memory 216260 kb
Host smart-c7615984-a9cc-4465-9564-8fbfaac3b18a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247917885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.3247917885
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_stress_all_with_rand_reset.1603124352
Short name T100
Test name
Test status
Simulation time 399910336 ps
CPU time 9.33 seconds
Started Mar 17 02:45:17 PM PDT 24
Finished Mar 17 02:45:26 PM PDT 24
Peak memory 222920 kb
Host smart-cf6d117a-0bc1-4d8e-a6b3-9e2af2e23798
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1603124352 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all_with_rand_reset.1603124352
Directory /workspace/49.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.11394668
Short name T139
Test name
Test status
Simulation time 63132438 ps
CPU time 4.21 seconds
Started Mar 17 02:43:32 PM PDT 24
Finished Mar 17 02:43:36 PM PDT 24
Peak memory 215648 kb
Host smart-73c1b926-a99a-4a54-9b36-0532dfe3be93
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=11394668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.11394668
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.3965198834
Short name T236
Test name
Test status
Simulation time 691448352 ps
CPU time 36.37 seconds
Started Mar 17 02:44:06 PM PDT 24
Finished Mar 17 02:44:42 PM PDT 24
Peak memory 221412 kb
Host smart-f71d9855-f7b1-4555-b154-45e7f7277a32
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3965198834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.3965198834
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.508581217
Short name T748
Test name
Test status
Simulation time 53329364 ps
CPU time 3.78 seconds
Started Mar 17 02:44:25 PM PDT 24
Finished Mar 17 02:44:29 PM PDT 24
Peak memory 222976 kb
Host smart-27d89cce-2b63-4f31-8ce9-c2fad5770fab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508581217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.508581217
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.790635428
Short name T270
Test name
Test status
Simulation time 57046228 ps
CPU time 3.87 seconds
Started Mar 17 02:44:38 PM PDT 24
Finished Mar 17 02:44:42 PM PDT 24
Peak memory 222868 kb
Host smart-d7fd674d-96f1-4ab7-a6a4-a686a5222c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=790635428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.790635428
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.3123525911
Short name T350
Test name
Test status
Simulation time 725677196 ps
CPU time 3.06 seconds
Started Mar 17 02:44:11 PM PDT 24
Finished Mar 17 02:44:14 PM PDT 24
Peak memory 214800 kb
Host smart-bb102458-081e-4e33-9ae9-b14321780c8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123525911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.3123525911
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.497227039
Short name T157
Test name
Test status
Simulation time 499583215 ps
CPU time 6.17 seconds
Started Mar 17 02:12:08 PM PDT 24
Finished Mar 17 02:12:14 PM PDT 24
Peak memory 214020 kb
Host smart-63d61b2a-3ba3-4553-9de6-9c7734c9e330
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497227039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err.
497227039
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.2596300749
Short name T158
Test name
Test status
Simulation time 768762439 ps
CPU time 11.75 seconds
Started Mar 17 02:12:57 PM PDT 24
Finished Mar 17 02:13:09 PM PDT 24
Peak memory 209296 kb
Host smart-ae3cb260-1a68-4443-823f-d3ee34858abf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596300749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.2596300749
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.2756936817
Short name T152
Test name
Test status
Simulation time 1402927509 ps
CPU time 9.22 seconds
Started Mar 17 02:12:50 PM PDT 24
Finished Mar 17 02:12:59 PM PDT 24
Peak memory 214228 kb
Host smart-d76b4a60-86be-4c01-9463-93e4e8c87256
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2756936817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.2756936817
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.2632686921
Short name T30
Test name
Test status
Simulation time 1448781795 ps
CPU time 5.27 seconds
Started Mar 17 02:44:50 PM PDT 24
Finished Mar 17 02:44:55 PM PDT 24
Peak memory 222384 kb
Host smart-1eec1a56-7585-40c8-8ee6-ca96e2074dcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632686921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.2632686921
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.335932395
Short name T76
Test name
Test status
Simulation time 3850158909 ps
CPU time 42.57 seconds
Started Mar 17 02:43:33 PM PDT 24
Finished Mar 17 02:44:16 PM PDT 24
Peak memory 223088 kb
Host smart-0f1a6877-ace5-4795-99ee-e7580d66600c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=335932395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.335932395
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.490102202
Short name T299
Test name
Test status
Simulation time 70686281 ps
CPU time 4.47 seconds
Started Mar 17 02:44:20 PM PDT 24
Finished Mar 17 02:44:25 PM PDT 24
Peak memory 216140 kb
Host smart-c3e8e4e8-48d6-4b63-aeac-8de4f5a12b9d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=490102202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.490102202
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.3002908592
Short name T234
Test name
Test status
Simulation time 2642004647 ps
CPU time 31.96 seconds
Started Mar 17 02:42:48 PM PDT 24
Finished Mar 17 02:43:21 PM PDT 24
Peak memory 215680 kb
Host smart-b4baf630-a919-48d5-988e-6976ffd02585
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3002908592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.3002908592
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.1131996466
Short name T253
Test name
Test status
Simulation time 82296653 ps
CPU time 4.84 seconds
Started Mar 17 02:42:55 PM PDT 24
Finished Mar 17 02:43:00 PM PDT 24
Peak memory 210776 kb
Host smart-929a0767-8347-4f4e-9f34-3e68f5ede687
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1131996466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.1131996466
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.29999610
Short name T167
Test name
Test status
Simulation time 905066646 ps
CPU time 6.33 seconds
Started Mar 17 02:43:59 PM PDT 24
Finished Mar 17 02:44:06 PM PDT 24
Peak memory 217908 kb
Host smart-73d7e207-5ab0-4a09-9a08-285495329324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29999610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.29999610
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.2923727368
Short name T170
Test name
Test status
Simulation time 188152235 ps
CPU time 3.26 seconds
Started Mar 17 02:45:00 PM PDT 24
Finished Mar 17 02:45:04 PM PDT 24
Peak memory 223120 kb
Host smart-3541db11-58c6-4762-9c4a-d2c06b5d4b1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2923727368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.2923727368
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.282459635
Short name T149
Test name
Test status
Simulation time 52330243 ps
CPU time 3.61 seconds
Started Mar 17 02:42:30 PM PDT 24
Finished Mar 17 02:42:34 PM PDT 24
Peak memory 222904 kb
Host smart-f7cc2f39-4b85-48cf-bc21-ac244609da38
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=282459635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.282459635
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.4067969557
Short name T249
Test name
Test status
Simulation time 444498348 ps
CPU time 5.58 seconds
Started Mar 17 02:42:28 PM PDT 24
Finished Mar 17 02:42:34 PM PDT 24
Peak memory 222916 kb
Host smart-1160d403-c7b4-41a0-aca1-3ec397d484fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4067969557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.4067969557
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_random.2166327147
Short name T176
Test name
Test status
Simulation time 1418385638 ps
CPU time 8.7 seconds
Started Mar 17 02:42:32 PM PDT 24
Finished Mar 17 02:42:41 PM PDT 24
Peak memory 210356 kb
Host smart-b932f003-02c8-4be6-84fc-bf2f4b60b209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166327147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.2166327147
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.4293655307
Short name T317
Test name
Test status
Simulation time 37804687 ps
CPU time 1.82 seconds
Started Mar 17 02:43:49 PM PDT 24
Finished Mar 17 02:43:51 PM PDT 24
Peak memory 207096 kb
Host smart-9a60f7b0-6d33-410e-97e1-c6d7823eed9b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4293655307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.4293655307
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.251618205
Short name T569
Test name
Test status
Simulation time 1112711301 ps
CPU time 10.36 seconds
Started Mar 17 02:44:15 PM PDT 24
Finished Mar 17 02:44:26 PM PDT 24
Peak memory 210948 kb
Host smart-5b18c161-236a-40da-a7aa-cafa9e7c2e67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251618205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.251618205
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.3963355029
Short name T222
Test name
Test status
Simulation time 15183496001 ps
CPU time 235.47 seconds
Started Mar 17 02:42:41 PM PDT 24
Finished Mar 17 02:46:36 PM PDT 24
Peak memory 218592 kb
Host smart-f6ce1da7-a9ab-4e49-a523-a6312101413f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963355029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.3963355029
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.3554482434
Short name T91
Test name
Test status
Simulation time 449378210 ps
CPU time 4.42 seconds
Started Mar 17 02:44:23 PM PDT 24
Finished Mar 17 02:44:28 PM PDT 24
Peak memory 222836 kb
Host smart-d7bff332-b965-4708-8623-6a08008eae9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554482434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.3554482434
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.1589139143
Short name T328
Test name
Test status
Simulation time 44649517 ps
CPU time 3.65 seconds
Started Mar 17 02:43:00 PM PDT 24
Finished Mar 17 02:43:03 PM PDT 24
Peak memory 222964 kb
Host smart-11c8054c-a8ad-4254-83f9-81c73d9125f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1589139143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.1589139143
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.3090171404
Short name T151
Test name
Test status
Simulation time 111650157 ps
CPU time 2.59 seconds
Started Mar 17 02:43:21 PM PDT 24
Finished Mar 17 02:43:24 PM PDT 24
Peak memory 210184 kb
Host smart-80c937ee-6740-46f1-88b8-90af2b167732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090171404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.3090171404
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.2648459439
Short name T169
Test name
Test status
Simulation time 144198253 ps
CPU time 2.37 seconds
Started Mar 17 02:43:36 PM PDT 24
Finished Mar 17 02:43:39 PM PDT 24
Peak memory 217492 kb
Host smart-6adb5316-2b83-4950-9807-661e1388bfee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2648459439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.2648459439
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.847458732
Short name T387
Test name
Test status
Simulation time 292811534 ps
CPU time 4.88 seconds
Started Mar 17 02:12:14 PM PDT 24
Finished Mar 17 02:12:19 PM PDT 24
Peak memory 209416 kb
Host smart-51d8909b-03b4-453c-95b6-d1459a4518c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=847458732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err.
847458732
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.1892448670
Short name T296
Test name
Test status
Simulation time 2193379336 ps
CPU time 10.69 seconds
Started Mar 17 02:42:19 PM PDT 24
Finished Mar 17 02:42:31 PM PDT 24
Peak memory 223044 kb
Host smart-8411a2af-bd41-40c6-a075-4c3ea5c67549
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892448670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.1892448670
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.735022329
Short name T505
Test name
Test status
Simulation time 290011383 ps
CPU time 3.43 seconds
Started Mar 17 02:42:20 PM PDT 24
Finished Mar 17 02:42:24 PM PDT 24
Peak memory 209092 kb
Host smart-d123ac39-3422-4110-8244-2eb01976e3ee
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=735022329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.735022329
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.4165805163
Short name T452
Test name
Test status
Simulation time 417180403 ps
CPU time 11.41 seconds
Started Mar 17 02:42:30 PM PDT 24
Finished Mar 17 02:42:41 PM PDT 24
Peak memory 221760 kb
Host smart-2557efd2-4035-484a-b2be-c702e9a51742
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4165805163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.4165805163
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_stress_all_with_rand_reset.1136772273
Short name T119
Test name
Test status
Simulation time 657986728 ps
CPU time 13.28 seconds
Started Mar 17 02:42:33 PM PDT 24
Finished Mar 17 02:42:46 PM PDT 24
Peak memory 222964 kb
Host smart-055db500-d9bd-4842-adcc-4f1b340e283c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1136772273 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all_with_rand_reset.1136772273
Directory /workspace/1.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.2131162635
Short name T90
Test name
Test status
Simulation time 2967651488 ps
CPU time 18.03 seconds
Started Mar 17 02:43:10 PM PDT 24
Finished Mar 17 02:43:29 PM PDT 24
Peak memory 223124 kb
Host smart-4832dfdd-7386-485c-bb27-19683801f808
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2131162635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.2131162635
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.3617103052
Short name T368
Test name
Test status
Simulation time 127572388 ps
CPU time 2.69 seconds
Started Mar 17 02:43:15 PM PDT 24
Finished Mar 17 02:43:18 PM PDT 24
Peak memory 214816 kb
Host smart-d2af8829-d718-4f71-84ac-f11fb514390d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3617103052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.3617103052
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.1337662726
Short name T62
Test name
Test status
Simulation time 286724353 ps
CPU time 5.34 seconds
Started Mar 17 02:43:19 PM PDT 24
Finished Mar 17 02:43:25 PM PDT 24
Peak memory 210976 kb
Host smart-cec9421e-5c3c-4408-85c5-08e64cb728f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337662726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.1337662726
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.3744134241
Short name T80
Test name
Test status
Simulation time 91910056 ps
CPU time 3.06 seconds
Started Mar 17 02:43:10 PM PDT 24
Finished Mar 17 02:43:13 PM PDT 24
Peak memory 208304 kb
Host smart-f8e3280c-33fc-411b-912e-fe6c28a4959f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3744134241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.3744134241
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.3974373039
Short name T336
Test name
Test status
Simulation time 978123964 ps
CPU time 7.78 seconds
Started Mar 17 02:43:21 PM PDT 24
Finished Mar 17 02:43:29 PM PDT 24
Peak memory 222884 kb
Host smart-3dcacf0d-89e6-4191-aacc-94bdc6f15278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974373039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.3974373039
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.1782978428
Short name T796
Test name
Test status
Simulation time 828349723 ps
CPU time 21.44 seconds
Started Mar 17 02:43:22 PM PDT 24
Finished Mar 17 02:43:44 PM PDT 24
Peak memory 209424 kb
Host smart-b08d4c0c-db3f-4d48-9559-5aab25d46f44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1782978428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.1782978428
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.2304543269
Short name T6
Test name
Test status
Simulation time 81682147 ps
CPU time 3.43 seconds
Started Mar 17 02:43:20 PM PDT 24
Finished Mar 17 02:43:24 PM PDT 24
Peak memory 210676 kb
Host smart-4fdae154-8bf5-4a9e-bc52-c9877a214c85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304543269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.2304543269
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_sideload.1912699531
Short name T457
Test name
Test status
Simulation time 354409678 ps
CPU time 3.39 seconds
Started Mar 17 02:43:25 PM PDT 24
Finished Mar 17 02:43:28 PM PDT 24
Peak memory 208472 kb
Host smart-93d9ab93-039c-41ea-b2a1-1adf818bb314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912699531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.1912699531
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.3158046028
Short name T307
Test name
Test status
Simulation time 6590964532 ps
CPU time 72.23 seconds
Started Mar 17 02:43:39 PM PDT 24
Finished Mar 17 02:44:52 PM PDT 24
Peak memory 214876 kb
Host smart-2a76c76f-eb4a-457b-9c12-3de94c09097e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3158046028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.3158046028
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.809218577
Short name T185
Test name
Test status
Simulation time 1156515675 ps
CPU time 42.78 seconds
Started Mar 17 02:43:44 PM PDT 24
Finished Mar 17 02:44:27 PM PDT 24
Peak memory 222932 kb
Host smart-2a4ed194-dbd6-4aa4-b346-238ea52857ae
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809218577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.809218577
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.2826616930
Short name T354
Test name
Test status
Simulation time 242984103 ps
CPU time 6.81 seconds
Started Mar 17 02:43:59 PM PDT 24
Finished Mar 17 02:44:06 PM PDT 24
Peak memory 214748 kb
Host smart-eda29413-d030-4e48-8127-a8940d6f536b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826616930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.2826616930
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_random.1297537258
Short name T332
Test name
Test status
Simulation time 859155300 ps
CPU time 3.46 seconds
Started Mar 17 02:44:03 PM PDT 24
Finished Mar 17 02:44:06 PM PDT 24
Peak memory 210008 kb
Host smart-110b6d64-be87-4552-9416-9c0847a04736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297537258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.1297537258
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.1906384088
Short name T421
Test name
Test status
Simulation time 75422759 ps
CPU time 3.41 seconds
Started Mar 17 02:44:11 PM PDT 24
Finished Mar 17 02:44:14 PM PDT 24
Peak memory 214644 kb
Host smart-a3d73277-5923-475c-9474-21cee498d9c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1906384088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.1906384088
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.1090561934
Short name T224
Test name
Test status
Simulation time 138925070 ps
CPU time 4.25 seconds
Started Mar 17 02:44:16 PM PDT 24
Finished Mar 17 02:44:20 PM PDT 24
Peak memory 214736 kb
Host smart-c6042164-8dfd-4fab-968e-81c8aae66589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1090561934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.1090561934
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.399524233
Short name T345
Test name
Test status
Simulation time 1117962681 ps
CPU time 4.57 seconds
Started Mar 17 02:44:17 PM PDT 24
Finished Mar 17 02:44:22 PM PDT 24
Peak memory 209860 kb
Host smart-9a1ed23b-f451-4259-bc66-830a7080f873
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399524233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.399524233
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.1902783269
Short name T293
Test name
Test status
Simulation time 797000373 ps
CPU time 7.9 seconds
Started Mar 17 02:44:26 PM PDT 24
Finished Mar 17 02:44:34 PM PDT 24
Peak memory 222940 kb
Host smart-a1dacc79-6079-4fe2-be10-2723f8465682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902783269 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.1902783269
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_sideload.2045155450
Short name T834
Test name
Test status
Simulation time 232285481 ps
CPU time 3.29 seconds
Started Mar 17 02:44:52 PM PDT 24
Finished Mar 17 02:44:55 PM PDT 24
Peak memory 207020 kb
Host smart-6d8f3e84-b6a0-4f53-803e-07bc9eb927e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045155450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.2045155450
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.4030041179
Short name T303
Test name
Test status
Simulation time 166654145 ps
CPU time 3.52 seconds
Started Mar 17 02:45:05 PM PDT 24
Finished Mar 17 02:45:08 PM PDT 24
Peak memory 222944 kb
Host smart-af1eda92-4dbc-4102-b12d-7ab08fac7c57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4030041179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.4030041179
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.630199739
Short name T344
Test name
Test status
Simulation time 176942882 ps
CPU time 2.45 seconds
Started Mar 17 02:45:00 PM PDT 24
Finished Mar 17 02:45:03 PM PDT 24
Peak memory 208508 kb
Host smart-ea552a62-02c2-4e6d-b7f7-110e22c26b4c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630199739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.630199739
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.3594752832
Short name T271
Test name
Test status
Simulation time 190761182 ps
CPU time 4.34 seconds
Started Mar 17 02:42:58 PM PDT 24
Finished Mar 17 02:43:02 PM PDT 24
Peak memory 210260 kb
Host smart-37aac82c-99bd-4ea0-966a-0cd4d3875359
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3594752832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.3594752832
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.718772305
Short name T171
Test name
Test status
Simulation time 1639533650 ps
CPU time 30.59 seconds
Started Mar 17 02:44:36 PM PDT 24
Finished Mar 17 02:45:07 PM PDT 24
Peak memory 217756 kb
Host smart-c98f8e96-3b7f-4c70-bc4f-3005317e7269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718772305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.718772305
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.1599616851
Short name T1022
Test name
Test status
Simulation time 496189553 ps
CPU time 11.21 seconds
Started Mar 17 02:12:09 PM PDT 24
Finished Mar 17 02:12:21 PM PDT 24
Peak memory 205796 kb
Host smart-fab718fc-9fc1-4e3c-a2d1-da0d9cb5f261
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1599616851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.1
599616851
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.3430443690
Short name T1005
Test name
Test status
Simulation time 2099992415 ps
CPU time 29.66 seconds
Started Mar 17 02:12:09 PM PDT 24
Finished Mar 17 02:12:40 PM PDT 24
Peak memory 205800 kb
Host smart-5f7b73d7-4a0b-434f-ae0a-6ea7c30a76f5
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3430443690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.3
430443690
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.22593178
Short name T1066
Test name
Test status
Simulation time 24268039 ps
CPU time 0.94 seconds
Started Mar 17 02:12:06 PM PDT 24
Finished Mar 17 02:12:08 PM PDT 24
Peak memory 205748 kb
Host smart-c4ade29f-fbba-4a91-b810-a09b6f421c00
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22593178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.22593178
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.2323680939
Short name T921
Test name
Test status
Simulation time 37881141 ps
CPU time 1.76 seconds
Started Mar 17 02:12:07 PM PDT 24
Finished Mar 17 02:12:10 PM PDT 24
Peak memory 214016 kb
Host smart-3e82a426-3739-4c14-abcf-4f338666c94f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2323680939 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.2323680939
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.2123648464
Short name T1032
Test name
Test status
Simulation time 128569345 ps
CPU time 1.23 seconds
Started Mar 17 02:12:08 PM PDT 24
Finished Mar 17 02:12:10 PM PDT 24
Peak memory 205976 kb
Host smart-b4dbacf8-70e5-4061-9f26-8f9ede585f7b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2123648464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.2123648464
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.1809975567
Short name T1016
Test name
Test status
Simulation time 9749313 ps
CPU time 0.72 seconds
Started Mar 17 02:12:09 PM PDT 24
Finished Mar 17 02:12:11 PM PDT 24
Peak memory 205572 kb
Host smart-37bf0ea8-9ec1-4313-b45b-6f8fa28277f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1809975567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.1809975567
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.2353166457
Short name T946
Test name
Test status
Simulation time 440679775 ps
CPU time 3.32 seconds
Started Mar 17 02:12:09 PM PDT 24
Finished Mar 17 02:12:12 PM PDT 24
Peak memory 205876 kb
Host smart-614232d2-5ebe-46b9-b040-856bb320c7cb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353166457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.2353166457
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.809525168
Short name T1064
Test name
Test status
Simulation time 98278808 ps
CPU time 2.42 seconds
Started Mar 17 02:12:01 PM PDT 24
Finished Mar 17 02:12:04 PM PDT 24
Peak memory 214456 kb
Host smart-4267112f-67e3-44dd-8bb1-f37614e4f085
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809525168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shadow
_reg_errors.809525168
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.943595325
Short name T1002
Test name
Test status
Simulation time 346972872 ps
CPU time 10.28 seconds
Started Mar 17 02:12:02 PM PDT 24
Finished Mar 17 02:12:12 PM PDT 24
Peak memory 214436 kb
Host smart-da24f6fd-5d8d-4f9d-97a0-104c65d67036
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=943595325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.k
eymgr_shadow_reg_errors_with_csr_rw.943595325
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.2034146617
Short name T970
Test name
Test status
Simulation time 25319880 ps
CPU time 1.76 seconds
Started Mar 17 02:12:08 PM PDT 24
Finished Mar 17 02:12:10 PM PDT 24
Peak memory 215096 kb
Host smart-b2ddfd98-8812-4f9a-be12-e1fd5288f7fd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034146617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.2034146617
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.1566211015
Short name T1055
Test name
Test status
Simulation time 134511544 ps
CPU time 4.71 seconds
Started Mar 17 02:12:13 PM PDT 24
Finished Mar 17 02:12:18 PM PDT 24
Peak memory 206004 kb
Host smart-24e2bd6a-1576-4536-8241-761ed6e3381c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566211015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.1
566211015
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.3333938162
Short name T173
Test name
Test status
Simulation time 1111912767 ps
CPU time 30.91 seconds
Started Mar 17 02:12:12 PM PDT 24
Finished Mar 17 02:12:43 PM PDT 24
Peak memory 205812 kb
Host smart-51e74f0a-908a-47fe-82b9-badcb0322456
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3333938162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.3
333938162
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.1090940625
Short name T1019
Test name
Test status
Simulation time 17894750 ps
CPU time 1.03 seconds
Started Mar 17 02:12:12 PM PDT 24
Finished Mar 17 02:12:13 PM PDT 24
Peak memory 205856 kb
Host smart-d684fe53-e7a5-430e-a4e1-2d76da9be95e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090940625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.1
090940625
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.611966664
Short name T979
Test name
Test status
Simulation time 140957031 ps
CPU time 2.09 seconds
Started Mar 17 02:12:19 PM PDT 24
Finished Mar 17 02:12:22 PM PDT 24
Peak memory 214208 kb
Host smart-0395d487-6578-4238-a932-c6558c9e67e6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=611966664 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.611966664
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.2151800208
Short name T146
Test name
Test status
Simulation time 95033826 ps
CPU time 1.43 seconds
Started Mar 17 02:12:12 PM PDT 24
Finished Mar 17 02:12:14 PM PDT 24
Peak memory 205940 kb
Host smart-551bbafd-9753-465a-a3d6-94c2f39a9f90
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2151800208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.2151800208
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.2513286341
Short name T1051
Test name
Test status
Simulation time 18973276 ps
CPU time 0.77 seconds
Started Mar 17 02:12:15 PM PDT 24
Finished Mar 17 02:12:16 PM PDT 24
Peak memory 205636 kb
Host smart-9b95320d-7cec-4f47-99fb-c1bd08a97140
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2513286341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.2513286341
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.4002486448
Short name T1009
Test name
Test status
Simulation time 99032129 ps
CPU time 1.68 seconds
Started Mar 17 02:12:19 PM PDT 24
Finished Mar 17 02:12:21 PM PDT 24
Peak memory 205828 kb
Host smart-6b423271-09df-46b4-aa75-963078f3c4c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002486448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sa
me_csr_outstanding.4002486448
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.2845805087
Short name T117
Test name
Test status
Simulation time 101970710 ps
CPU time 3.16 seconds
Started Mar 17 02:12:12 PM PDT 24
Finished Mar 17 02:12:16 PM PDT 24
Peak memory 214480 kb
Host smart-4fec1afb-4817-41bb-b748-46fd9c0424e4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845805087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.2845805087
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.4158652348
Short name T1050
Test name
Test status
Simulation time 572730483 ps
CPU time 8.09 seconds
Started Mar 17 02:12:12 PM PDT 24
Finished Mar 17 02:12:20 PM PDT 24
Peak memory 214324 kb
Host smart-df878c90-3c20-4b32-a3b7-cc8b4a9efadc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4158652348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.4158652348
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.3931455678
Short name T929
Test name
Test status
Simulation time 35873370 ps
CPU time 2.45 seconds
Started Mar 17 02:12:11 PM PDT 24
Finished Mar 17 02:12:14 PM PDT 24
Peak memory 216384 kb
Host smart-ba16b482-ffd6-47f2-8c32-8fa67467f308
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931455678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.3931455678
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.2945521140
Short name T1063
Test name
Test status
Simulation time 39715608 ps
CPU time 1.38 seconds
Started Mar 17 02:12:51 PM PDT 24
Finished Mar 17 02:12:52 PM PDT 24
Peak memory 214216 kb
Host smart-e5b6db25-f88c-4ea0-a951-6b07efd4ccb4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945521140 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.2945521140
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.1969881800
Short name T1043
Test name
Test status
Simulation time 24254433 ps
CPU time 1.05 seconds
Started Mar 17 02:12:51 PM PDT 24
Finished Mar 17 02:12:52 PM PDT 24
Peak memory 205876 kb
Host smart-90b8e9aa-5bd0-420a-94e8-99ba6d490bbd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969881800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.1969881800
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.559174609
Short name T911
Test name
Test status
Simulation time 14594331 ps
CPU time 0.73 seconds
Started Mar 17 02:12:54 PM PDT 24
Finished Mar 17 02:12:55 PM PDT 24
Peak memory 205584 kb
Host smart-6fc9fa16-2939-4852-81cc-08181bf7429b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559174609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.559174609
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.4256248043
Short name T964
Test name
Test status
Simulation time 957598498 ps
CPU time 3.72 seconds
Started Mar 17 02:12:53 PM PDT 24
Finished Mar 17 02:12:57 PM PDT 24
Peak memory 205944 kb
Host smart-d936ceb0-6707-4f97-b272-85f364f292f4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4256248043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.4256248043
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.712916721
Short name T936
Test name
Test status
Simulation time 178491737 ps
CPU time 4.04 seconds
Started Mar 17 02:12:53 PM PDT 24
Finished Mar 17 02:12:57 PM PDT 24
Peak memory 219192 kb
Host smart-c2ff58bc-d04b-49ab-a5bc-ac86aa71fabe
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=712916721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shado
w_reg_errors.712916721
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.1778844227
Short name T1006
Test name
Test status
Simulation time 1594997391 ps
CPU time 9.34 seconds
Started Mar 17 02:12:51 PM PDT 24
Finished Mar 17 02:13:00 PM PDT 24
Peak memory 214396 kb
Host smart-7a170a30-209b-447a-9f3a-99971f7beb6d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778844227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.keymgr_shadow_reg_errors_with_csr_rw.1778844227
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.519245674
Short name T952
Test name
Test status
Simulation time 85721010 ps
CPU time 1.89 seconds
Started Mar 17 02:12:51 PM PDT 24
Finished Mar 17 02:12:53 PM PDT 24
Peak memory 214072 kb
Host smart-81cd23a3-045f-4df1-9fe8-830ccf808076
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519245674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.519245674
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.3007069315
Short name T159
Test name
Test status
Simulation time 2122903104 ps
CPU time 59.44 seconds
Started Mar 17 02:12:51 PM PDT 24
Finished Mar 17 02:13:50 PM PDT 24
Peak memory 222272 kb
Host smart-ca329e52-01d0-4105-bd93-ccb2d1ec56bc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007069315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_er
r.3007069315
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.1841082326
Short name T174
Test name
Test status
Simulation time 41428548 ps
CPU time 1.46 seconds
Started Mar 17 02:12:58 PM PDT 24
Finished Mar 17 02:12:59 PM PDT 24
Peak memory 205960 kb
Host smart-5652a6b8-ed96-49d3-b5f8-782bbfe3631d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1841082326 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.1841082326
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.4141369947
Short name T974
Test name
Test status
Simulation time 26235586 ps
CPU time 1.19 seconds
Started Mar 17 02:12:58 PM PDT 24
Finished Mar 17 02:12:59 PM PDT 24
Peak memory 205900 kb
Host smart-4bea573d-2e53-4759-a793-dfe8325c00ad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4141369947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.4141369947
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.1945100279
Short name T916
Test name
Test status
Simulation time 19788331 ps
CPU time 0.72 seconds
Started Mar 17 02:13:07 PM PDT 24
Finished Mar 17 02:13:08 PM PDT 24
Peak memory 205584 kb
Host smart-c6b831e4-5dcf-4715-8c8b-1b24108dc780
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1945100279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.1945100279
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.1326061548
Short name T1025
Test name
Test status
Simulation time 78689421 ps
CPU time 1.59 seconds
Started Mar 17 02:12:58 PM PDT 24
Finished Mar 17 02:12:59 PM PDT 24
Peak memory 205880 kb
Host smart-4c42e9d0-e549-4ef7-bbbe-c82059594f32
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1326061548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s
ame_csr_outstanding.1326061548
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.388268934
Short name T115
Test name
Test status
Simulation time 333448902 ps
CPU time 2.87 seconds
Started Mar 17 02:12:51 PM PDT 24
Finished Mar 17 02:12:53 PM PDT 24
Peak memory 214396 kb
Host smart-b0c0e7cf-86af-437d-9974-020483aa12f7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388268934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shado
w_reg_errors.388268934
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.399113103
Short name T947
Test name
Test status
Simulation time 216795762 ps
CPU time 7.31 seconds
Started Mar 17 02:12:50 PM PDT 24
Finished Mar 17 02:12:58 PM PDT 24
Peak memory 214460 kb
Host smart-046459c5-a309-4c9a-b9a7-63c2f1d57258
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399113103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.
keymgr_shadow_reg_errors_with_csr_rw.399113103
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.4146286959
Short name T1017
Test name
Test status
Simulation time 209768285 ps
CPU time 1.9 seconds
Started Mar 17 02:12:58 PM PDT 24
Finished Mar 17 02:13:00 PM PDT 24
Peak memory 214052 kb
Host smart-1f6f3dd8-ccbe-49f4-9484-5c2f2d773224
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4146286959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.4146286959
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.2062168678
Short name T1037
Test name
Test status
Simulation time 557677648 ps
CPU time 2.46 seconds
Started Mar 17 02:13:07 PM PDT 24
Finished Mar 17 02:13:10 PM PDT 24
Peak memory 214092 kb
Host smart-74a2bf20-69c3-4b6d-845a-6d0dc111ed54
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062168678 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.2062168678
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.519305696
Short name T1042
Test name
Test status
Simulation time 71624240 ps
CPU time 1.17 seconds
Started Mar 17 02:12:59 PM PDT 24
Finished Mar 17 02:13:01 PM PDT 24
Peak memory 205876 kb
Host smart-17497742-761e-40c6-9bd3-f984bdf9c255
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=519305696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.519305696
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.3960168169
Short name T1020
Test name
Test status
Simulation time 34127172 ps
CPU time 0.71 seconds
Started Mar 17 02:12:57 PM PDT 24
Finished Mar 17 02:12:57 PM PDT 24
Peak memory 205648 kb
Host smart-7778f219-4efa-4220-bb28-62a5bf23a059
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3960168169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.3960168169
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.3618405971
Short name T992
Test name
Test status
Simulation time 149561322 ps
CPU time 2.1 seconds
Started Mar 17 02:12:59 PM PDT 24
Finished Mar 17 02:13:02 PM PDT 24
Peak memory 206044 kb
Host smart-163d0304-6b0d-44f6-9489-eff19e0b82a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3618405971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.3618405971
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.4011033497
Short name T1038
Test name
Test status
Simulation time 558786969 ps
CPU time 4.59 seconds
Started Mar 17 02:12:58 PM PDT 24
Finished Mar 17 02:13:03 PM PDT 24
Peak memory 222636 kb
Host smart-d0c82fcb-e2cd-45e8-b0af-fb3820c0dcc4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4011033497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.4011033497
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.2846480240
Short name T110
Test name
Test status
Simulation time 462183280 ps
CPU time 7.48 seconds
Started Mar 17 02:13:07 PM PDT 24
Finished Mar 17 02:13:15 PM PDT 24
Peak memory 214412 kb
Host smart-c59c8484-a947-4754-a077-a9d6e3e561da
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846480240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.2846480240
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.172887953
Short name T994
Test name
Test status
Simulation time 33241405 ps
CPU time 2.22 seconds
Started Mar 17 02:12:58 PM PDT 24
Finished Mar 17 02:13:01 PM PDT 24
Peak memory 214008 kb
Host smart-65604c06-15d9-4841-9eda-0984f569df07
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172887953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.172887953
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.2524650997
Short name T164
Test name
Test status
Simulation time 379331402 ps
CPU time 7.92 seconds
Started Mar 17 02:12:56 PM PDT 24
Finished Mar 17 02:13:04 PM PDT 24
Peak memory 209500 kb
Host smart-63669fd7-0e3b-4ac7-9363-66e217cd0272
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2524650997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_er
r.2524650997
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.1560936357
Short name T1010
Test name
Test status
Simulation time 189215404 ps
CPU time 2.36 seconds
Started Mar 17 02:12:58 PM PDT 24
Finished Mar 17 02:13:01 PM PDT 24
Peak memory 214224 kb
Host smart-5447dd1b-1755-4c30-9db6-6eab0062aad0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560936357 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.1560936357
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.4069428524
Short name T1058
Test name
Test status
Simulation time 155242770 ps
CPU time 0.97 seconds
Started Mar 17 02:12:57 PM PDT 24
Finished Mar 17 02:12:59 PM PDT 24
Peak memory 205616 kb
Host smart-cbbfa057-c961-4153-8564-42aa142d4e4f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069428524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.4069428524
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.3665778557
Short name T1068
Test name
Test status
Simulation time 12931496 ps
CPU time 0.69 seconds
Started Mar 17 02:13:07 PM PDT 24
Finished Mar 17 02:13:08 PM PDT 24
Peak memory 205584 kb
Host smart-03fd9bb0-2a9c-4f4d-a7c2-91898e34eb51
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3665778557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.3665778557
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.1941258692
Short name T1015
Test name
Test status
Simulation time 106943254 ps
CPU time 1.52 seconds
Started Mar 17 02:12:57 PM PDT 24
Finished Mar 17 02:12:58 PM PDT 24
Peak memory 205864 kb
Host smart-19d60d1b-2106-49c7-b42b-ff1551bb91f0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1941258692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.1941258692
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.1833579462
Short name T969
Test name
Test status
Simulation time 438167882 ps
CPU time 2.65 seconds
Started Mar 17 02:13:01 PM PDT 24
Finished Mar 17 02:13:04 PM PDT 24
Peak memory 214472 kb
Host smart-9346392e-ec0b-4a22-950b-860bcae4afdc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1833579462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.1833579462
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.1146836973
Short name T949
Test name
Test status
Simulation time 553596172 ps
CPU time 4.71 seconds
Started Mar 17 02:12:57 PM PDT 24
Finished Mar 17 02:13:02 PM PDT 24
Peak memory 214328 kb
Host smart-21ff3e45-2f18-4b7e-bfd3-e4d26012e550
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146836973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.1146836973
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.2497387410
Short name T1007
Test name
Test status
Simulation time 144739170 ps
CPU time 3.88 seconds
Started Mar 17 02:12:55 PM PDT 24
Finished Mar 17 02:12:59 PM PDT 24
Peak memory 213920 kb
Host smart-4cb7befb-a1f5-4fc8-b2bf-7ef642c877fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497387410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.2497387410
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.3634385686
Short name T163
Test name
Test status
Simulation time 897490222 ps
CPU time 25.13 seconds
Started Mar 17 02:13:07 PM PDT 24
Finished Mar 17 02:13:33 PM PDT 24
Peak memory 209124 kb
Host smart-050e0c7b-ad7c-481e-a3fe-1d4cad3d2168
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634385686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er
r.3634385686
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.2141858102
Short name T1012
Test name
Test status
Simulation time 76154520 ps
CPU time 1.9 seconds
Started Mar 17 02:13:03 PM PDT 24
Finished Mar 17 02:13:06 PM PDT 24
Peak memory 217068 kb
Host smart-2fa5c293-23a8-43a5-8ec4-be175f25affe
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2141858102 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.2141858102
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.1145201571
Short name T1047
Test name
Test status
Simulation time 36911558 ps
CPU time 0.92 seconds
Started Mar 17 02:13:10 PM PDT 24
Finished Mar 17 02:13:12 PM PDT 24
Peak memory 205716 kb
Host smart-814fb212-d9b5-4245-a74a-28c848884ba9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1145201571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.1145201571
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.125184957
Short name T1031
Test name
Test status
Simulation time 12255899 ps
CPU time 0.72 seconds
Started Mar 17 02:13:05 PM PDT 24
Finished Mar 17 02:13:06 PM PDT 24
Peak memory 205572 kb
Host smart-e85ddc97-0397-4aeb-9234-b59477ddacac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=125184957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.125184957
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.1875667343
Short name T958
Test name
Test status
Simulation time 76351577 ps
CPU time 1.32 seconds
Started Mar 17 02:13:11 PM PDT 24
Finished Mar 17 02:13:12 PM PDT 24
Peak memory 205916 kb
Host smart-bf65e1ad-ddd7-4c42-a96b-e6514e6fae85
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1875667343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s
ame_csr_outstanding.1875667343
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.3721241247
Short name T1026
Test name
Test status
Simulation time 911431397 ps
CPU time 9.76 seconds
Started Mar 17 02:12:58 PM PDT 24
Finished Mar 17 02:13:08 PM PDT 24
Peak memory 214424 kb
Host smart-9b90a8ae-c39f-4222-b41d-6b2429e13f18
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721241247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.3721241247
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.763133673
Short name T934
Test name
Test status
Simulation time 614586469 ps
CPU time 4.16 seconds
Started Mar 17 02:13:03 PM PDT 24
Finished Mar 17 02:13:08 PM PDT 24
Peak memory 214128 kb
Host smart-cf754a07-9adc-4132-a48f-17073336e68b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=763133673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.
keymgr_shadow_reg_errors_with_csr_rw.763133673
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.1282118746
Short name T1014
Test name
Test status
Simulation time 328439886 ps
CPU time 2.4 seconds
Started Mar 17 02:13:02 PM PDT 24
Finished Mar 17 02:13:05 PM PDT 24
Peak memory 217092 kb
Host smart-3219ee10-405d-4c91-823b-8c739f13c3bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1282118746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.1282118746
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.1732157503
Short name T999
Test name
Test status
Simulation time 139980866 ps
CPU time 4.68 seconds
Started Mar 17 02:13:03 PM PDT 24
Finished Mar 17 02:13:08 PM PDT 24
Peak memory 214068 kb
Host smart-d1ae17c3-bb4c-4276-829e-7d6db8a2cab4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732157503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.1732157503
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.3963629861
Short name T1049
Test name
Test status
Simulation time 60908441 ps
CPU time 2.33 seconds
Started Mar 17 02:13:04 PM PDT 24
Finished Mar 17 02:13:07 PM PDT 24
Peak memory 214220 kb
Host smart-0500fcba-bb22-4ca4-9228-97c506812b06
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963629861 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.3963629861
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.938485885
Short name T143
Test name
Test status
Simulation time 377600282 ps
CPU time 1.52 seconds
Started Mar 17 02:13:02 PM PDT 24
Finished Mar 17 02:13:04 PM PDT 24
Peak memory 205804 kb
Host smart-6b972376-db47-4ac4-92d8-4a40d5354584
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938485885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.938485885
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.2724848899
Short name T986
Test name
Test status
Simulation time 44649445 ps
CPU time 0.72 seconds
Started Mar 17 02:13:03 PM PDT 24
Finished Mar 17 02:13:04 PM PDT 24
Peak memory 205608 kb
Host smart-b8f826be-967a-43da-ace8-38ea3338628c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724848899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.2724848899
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.1855956907
Short name T1073
Test name
Test status
Simulation time 187067406 ps
CPU time 1.61 seconds
Started Mar 17 02:13:03 PM PDT 24
Finished Mar 17 02:13:05 PM PDT 24
Peak memory 205956 kb
Host smart-3ba3c496-3faf-4507-9514-2125b6d349e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1855956907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.1855956907
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.4166523045
Short name T1035
Test name
Test status
Simulation time 106904217 ps
CPU time 1.99 seconds
Started Mar 17 02:13:03 PM PDT 24
Finished Mar 17 02:13:05 PM PDT 24
Peak memory 222552 kb
Host smart-b00fdef4-2184-4d5a-9fbb-b8738427b84a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4166523045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.4166523045
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.3905854172
Short name T988
Test name
Test status
Simulation time 1341253206 ps
CPU time 8.76 seconds
Started Mar 17 02:13:02 PM PDT 24
Finished Mar 17 02:13:11 PM PDT 24
Peak memory 214464 kb
Host smart-b1d1a76f-45bb-45ee-afd3-e2aee1e430c5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905854172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.3905854172
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.2232176502
Short name T990
Test name
Test status
Simulation time 977029938 ps
CPU time 2.41 seconds
Started Mar 17 02:13:04 PM PDT 24
Finished Mar 17 02:13:07 PM PDT 24
Peak memory 214032 kb
Host smart-01f07f66-3397-4de1-a572-5328f9217d09
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2232176502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.2232176502
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.1505337527
Short name T924
Test name
Test status
Simulation time 4918356598 ps
CPU time 17.93 seconds
Started Mar 17 02:13:10 PM PDT 24
Finished Mar 17 02:13:28 PM PDT 24
Peak memory 209544 kb
Host smart-074319ec-5e4b-44ae-b69b-a1fd5d8c87a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1505337527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.1505337527
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.3795838264
Short name T155
Test name
Test status
Simulation time 145575774 ps
CPU time 2.7 seconds
Started Mar 17 02:13:14 PM PDT 24
Finished Mar 17 02:13:18 PM PDT 24
Peak memory 214176 kb
Host smart-abacf884-71f0-4324-ad84-c02148ab365c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3795838264 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.3795838264
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.345425128
Short name T1018
Test name
Test status
Simulation time 25477196 ps
CPU time 1.45 seconds
Started Mar 17 02:13:13 PM PDT 24
Finished Mar 17 02:13:14 PM PDT 24
Peak memory 205908 kb
Host smart-b5fcaa8a-5aee-41d5-b98d-01c423216458
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345425128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.345425128
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.2979926579
Short name T918
Test name
Test status
Simulation time 8745835 ps
CPU time 0.82 seconds
Started Mar 17 02:13:02 PM PDT 24
Finished Mar 17 02:13:03 PM PDT 24
Peak memory 205564 kb
Host smart-778fcc52-7a67-405d-9e27-5f997c481caf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2979926579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.2979926579
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.1542148494
Short name T144
Test name
Test status
Simulation time 172485557 ps
CPU time 1.81 seconds
Started Mar 17 02:13:12 PM PDT 24
Finished Mar 17 02:13:14 PM PDT 24
Peak memory 205924 kb
Host smart-05d1543f-0dc6-48c8-a3d0-4c9f98b8734e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1542148494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.1542148494
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.4208822611
Short name T1001
Test name
Test status
Simulation time 2685101160 ps
CPU time 8.79 seconds
Started Mar 17 02:13:03 PM PDT 24
Finished Mar 17 02:13:13 PM PDT 24
Peak memory 220360 kb
Host smart-4566df2b-b947-460e-91a1-ffb776c8dc3d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4208822611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.4208822611
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.244664250
Short name T967
Test name
Test status
Simulation time 281054318 ps
CPU time 3.61 seconds
Started Mar 17 02:13:04 PM PDT 24
Finished Mar 17 02:13:08 PM PDT 24
Peak memory 214488 kb
Host smart-016e5b3e-bfdd-45b3-838b-fc792cb401d5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=244664250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
keymgr_shadow_reg_errors_with_csr_rw.244664250
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.900207169
Short name T981
Test name
Test status
Simulation time 20262462 ps
CPU time 1.66 seconds
Started Mar 17 02:13:02 PM PDT 24
Finished Mar 17 02:13:04 PM PDT 24
Peak memory 214064 kb
Host smart-f3fb46b1-b9a4-42fa-9190-48e190c6a143
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=900207169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.900207169
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.3351870114
Short name T987
Test name
Test status
Simulation time 43873876 ps
CPU time 1.48 seconds
Started Mar 17 02:13:14 PM PDT 24
Finished Mar 17 02:13:15 PM PDT 24
Peak memory 216092 kb
Host smart-c0ef2282-8a51-43d1-a6f7-a766c2fd362c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3351870114 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.3351870114
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.856926787
Short name T940
Test name
Test status
Simulation time 17454617 ps
CPU time 0.95 seconds
Started Mar 17 02:13:12 PM PDT 24
Finished Mar 17 02:13:13 PM PDT 24
Peak memory 205708 kb
Host smart-d432aa15-5682-4b50-a994-198f27c329fa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856926787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.856926787
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.1017332385
Short name T1060
Test name
Test status
Simulation time 33892879 ps
CPU time 0.81 seconds
Started Mar 17 02:13:13 PM PDT 24
Finished Mar 17 02:13:14 PM PDT 24
Peak memory 205572 kb
Host smart-d9f17b1a-8820-41f0-b51d-47a258189a88
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1017332385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.1017332385
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.508255227
Short name T965
Test name
Test status
Simulation time 454559983 ps
CPU time 4.03 seconds
Started Mar 17 02:13:11 PM PDT 24
Finished Mar 17 02:13:15 PM PDT 24
Peak memory 205924 kb
Host smart-e19154c9-9884-45d9-a8da-6fdb3e891efd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508255227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_sa
me_csr_outstanding.508255227
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.3895583074
Short name T997
Test name
Test status
Simulation time 152443236 ps
CPU time 4.09 seconds
Started Mar 17 02:13:12 PM PDT 24
Finished Mar 17 02:13:16 PM PDT 24
Peak memory 214464 kb
Host smart-7086c73a-99e1-4bf0-9738-8db48fa72bb2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3895583074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.3895583074
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.3892647529
Short name T954
Test name
Test status
Simulation time 272245261 ps
CPU time 3.57 seconds
Started Mar 17 02:13:13 PM PDT 24
Finished Mar 17 02:13:17 PM PDT 24
Peak memory 220488 kb
Host smart-b06e7557-1676-4e23-ae82-7fd379d4ef62
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892647529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.keymgr_shadow_reg_errors_with_csr_rw.3892647529
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.1115915203
Short name T907
Test name
Test status
Simulation time 143688164 ps
CPU time 2.15 seconds
Started Mar 17 02:13:15 PM PDT 24
Finished Mar 17 02:13:17 PM PDT 24
Peak memory 214068 kb
Host smart-32dfe1c1-6da9-47f6-b52c-a6863e8e8db1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115915203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.1115915203
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.689122547
Short name T162
Test name
Test status
Simulation time 394945957 ps
CPU time 5.43 seconds
Started Mar 17 02:13:12 PM PDT 24
Finished Mar 17 02:13:18 PM PDT 24
Peak memory 222224 kb
Host smart-aafe07fc-6e5c-499b-a946-d9f4fe77b76f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=689122547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_err
.689122547
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.1888110831
Short name T989
Test name
Test status
Simulation time 29442017 ps
CPU time 1.25 seconds
Started Mar 17 02:13:16 PM PDT 24
Finished Mar 17 02:13:17 PM PDT 24
Peak memory 214104 kb
Host smart-7e64b975-bb1e-45c8-8d0b-427179066167
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1888110831 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.1888110831
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.3637122894
Short name T145
Test name
Test status
Simulation time 35962135 ps
CPU time 0.85 seconds
Started Mar 17 02:13:14 PM PDT 24
Finished Mar 17 02:13:16 PM PDT 24
Peak memory 205688 kb
Host smart-7dfae57e-2db1-4de4-9585-7291a50630b7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637122894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.3637122894
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.1339632568
Short name T1041
Test name
Test status
Simulation time 15225410 ps
CPU time 0.7 seconds
Started Mar 17 02:13:16 PM PDT 24
Finished Mar 17 02:13:16 PM PDT 24
Peak memory 205568 kb
Host smart-145e192c-fef7-4338-a3e8-543062e089f8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1339632568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.1339632568
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.1324606642
Short name T142
Test name
Test status
Simulation time 90782794 ps
CPU time 3.83 seconds
Started Mar 17 02:13:20 PM PDT 24
Finished Mar 17 02:13:24 PM PDT 24
Peak memory 205908 kb
Host smart-5f13ae75-51df-4b5a-8432-e6b50187d54b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324606642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.1324606642
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.2432500708
Short name T1040
Test name
Test status
Simulation time 1177772107 ps
CPU time 5.3 seconds
Started Mar 17 02:13:13 PM PDT 24
Finished Mar 17 02:13:18 PM PDT 24
Peak memory 214320 kb
Host smart-f353c43f-5407-46f2-8a02-3c7fb60be361
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432500708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.2432500708
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.3891386513
Short name T978
Test name
Test status
Simulation time 406112579 ps
CPU time 9.71 seconds
Started Mar 17 02:13:18 PM PDT 24
Finished Mar 17 02:13:28 PM PDT 24
Peak memory 214412 kb
Host smart-504499b3-bb15-4e43-b968-abbbae7157d5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891386513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.3891386513
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.2255002986
Short name T1061
Test name
Test status
Simulation time 115095261 ps
CPU time 2.4 seconds
Started Mar 17 02:13:17 PM PDT 24
Finished Mar 17 02:13:20 PM PDT 24
Peak memory 214768 kb
Host smart-0e36b9b8-627e-4f9f-8e3e-833d90a173cf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2255002986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.2255002986
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.1451346932
Short name T165
Test name
Test status
Simulation time 246062550 ps
CPU time 3.3 seconds
Started Mar 17 02:13:16 PM PDT 24
Finished Mar 17 02:13:20 PM PDT 24
Peak memory 209612 kb
Host smart-33538018-39bc-4ba0-bb87-2d2e9a2f402e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1451346932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.1451346932
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.2619608756
Short name T993
Test name
Test status
Simulation time 77684292 ps
CPU time 1.69 seconds
Started Mar 17 02:13:15 PM PDT 24
Finished Mar 17 02:13:17 PM PDT 24
Peak memory 214232 kb
Host smart-e8cf4c49-f3d5-4229-bdf2-f1afc2706749
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619608756 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.2619608756
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.608741827
Short name T943
Test name
Test status
Simulation time 41192867 ps
CPU time 0.89 seconds
Started Mar 17 02:13:17 PM PDT 24
Finished Mar 17 02:13:18 PM PDT 24
Peak memory 205644 kb
Host smart-a41044f1-8098-4809-b7aa-405a66338a8b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608741827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.608741827
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.20935693
Short name T944
Test name
Test status
Simulation time 112007615 ps
CPU time 0.73 seconds
Started Mar 17 02:13:15 PM PDT 24
Finished Mar 17 02:13:16 PM PDT 24
Peak memory 205620 kb
Host smart-fd5aba60-a823-446e-bb7d-4342005f9e7f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20935693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.20935693
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.958147176
Short name T1027
Test name
Test status
Simulation time 60349175 ps
CPU time 1.5 seconds
Started Mar 17 02:13:14 PM PDT 24
Finished Mar 17 02:13:16 PM PDT 24
Peak memory 205908 kb
Host smart-268b0ca9-a3af-4aa3-b23d-96cd7bb35b63
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=958147176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_sa
me_csr_outstanding.958147176
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.1611804711
Short name T933
Test name
Test status
Simulation time 229241622 ps
CPU time 4.94 seconds
Started Mar 17 02:13:18 PM PDT 24
Finished Mar 17 02:13:23 PM PDT 24
Peak memory 219320 kb
Host smart-aa29ecd8-073a-440a-9329-650eed0ee2e3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1611804711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.1611804711
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.1185555338
Short name T931
Test name
Test status
Simulation time 74148763 ps
CPU time 3.6 seconds
Started Mar 17 02:13:15 PM PDT 24
Finished Mar 17 02:13:19 PM PDT 24
Peak memory 214324 kb
Host smart-6edd40af-d068-418e-acee-45abe7791f33
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1185555338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.1185555338
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.3193834836
Short name T1030
Test name
Test status
Simulation time 42095782 ps
CPU time 1.41 seconds
Started Mar 17 02:13:14 PM PDT 24
Finished Mar 17 02:13:16 PM PDT 24
Peak memory 205916 kb
Host smart-6757d241-9cfc-4ce1-8e51-9196579891aa
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3193834836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.3193834836
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.203098616
Short name T996
Test name
Test status
Simulation time 185799048 ps
CPU time 7.06 seconds
Started Mar 17 02:12:18 PM PDT 24
Finished Mar 17 02:12:26 PM PDT 24
Peak memory 205908 kb
Host smart-176a26b8-9774-4a23-a1cc-02f3d6519ac6
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=203098616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.203098616
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.2208781960
Short name T909
Test name
Test status
Simulation time 1723356938 ps
CPU time 8.31 seconds
Started Mar 17 02:12:19 PM PDT 24
Finished Mar 17 02:12:28 PM PDT 24
Peak memory 205956 kb
Host smart-5d0625ec-2a16-44bd-ba17-d4759e07371b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208781960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.2
208781960
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.1162475936
Short name T1034
Test name
Test status
Simulation time 26533210 ps
CPU time 1.01 seconds
Started Mar 17 02:12:18 PM PDT 24
Finished Mar 17 02:12:20 PM PDT 24
Peak memory 205696 kb
Host smart-35e92a2e-45bd-45c8-9027-021d89cc3326
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1162475936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.1
162475936
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.913037919
Short name T961
Test name
Test status
Simulation time 792370061 ps
CPU time 2.06 seconds
Started Mar 17 02:12:25 PM PDT 24
Finished Mar 17 02:12:28 PM PDT 24
Peak memory 216576 kb
Host smart-681e30be-5d07-410e-9995-3eebd3b7be73
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=913037919 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.913037919
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.2800886338
Short name T1056
Test name
Test status
Simulation time 47392177 ps
CPU time 1.16 seconds
Started Mar 17 02:12:18 PM PDT 24
Finished Mar 17 02:12:19 PM PDT 24
Peak memory 206008 kb
Host smart-86780588-78cd-4313-a82f-451a2bba1d93
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2800886338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.2800886338
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.471650786
Short name T922
Test name
Test status
Simulation time 24421401 ps
CPU time 0.74 seconds
Started Mar 17 02:12:19 PM PDT 24
Finished Mar 17 02:12:20 PM PDT 24
Peak memory 205640 kb
Host smart-c2db0d41-e2b1-4376-9805-0cdc2b9b2fb8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=471650786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.471650786
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.3127755882
Short name T1069
Test name
Test status
Simulation time 48267489 ps
CPU time 1.41 seconds
Started Mar 17 02:12:18 PM PDT 24
Finished Mar 17 02:12:20 PM PDT 24
Peak memory 205944 kb
Host smart-8ff4368a-c785-433f-aab8-4a366193d60d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127755882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.3127755882
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.3178710462
Short name T953
Test name
Test status
Simulation time 556091725 ps
CPU time 9.07 seconds
Started Mar 17 02:12:20 PM PDT 24
Finished Mar 17 02:12:29 PM PDT 24
Peak memory 214348 kb
Host smart-fb74c1ee-e450-475e-bbb2-278a8ef97bed
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178710462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.3178710462
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.136743348
Short name T926
Test name
Test status
Simulation time 764290675 ps
CPU time 4.19 seconds
Started Mar 17 02:12:17 PM PDT 24
Finished Mar 17 02:12:21 PM PDT 24
Peak memory 214164 kb
Host smart-c96da50f-9436-4254-80d3-7f1c53a4c366
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136743348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.136743348
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.3168261489
Short name T160
Test name
Test status
Simulation time 251985125 ps
CPU time 6.61 seconds
Started Mar 17 02:12:19 PM PDT 24
Finished Mar 17 02:12:26 PM PDT 24
Peak memory 209420 kb
Host smart-c337793c-6d1b-490d-852f-7958d61bb596
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168261489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.3168261489
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.2081267841
Short name T1039
Test name
Test status
Simulation time 9223835 ps
CPU time 0.72 seconds
Started Mar 17 02:13:15 PM PDT 24
Finished Mar 17 02:13:16 PM PDT 24
Peak memory 205576 kb
Host smart-fcfbd0b4-99dc-4723-a8a5-b0983fcee869
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2081267841 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.2081267841
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.1433167853
Short name T1048
Test name
Test status
Simulation time 10894129 ps
CPU time 0.85 seconds
Started Mar 17 02:13:17 PM PDT 24
Finished Mar 17 02:13:18 PM PDT 24
Peak memory 205620 kb
Host smart-bcf85618-742f-4770-a29a-8c7083a13da7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433167853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.1433167853
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.2484373993
Short name T980
Test name
Test status
Simulation time 33111865 ps
CPU time 0.81 seconds
Started Mar 17 02:13:18 PM PDT 24
Finished Mar 17 02:13:19 PM PDT 24
Peak memory 205588 kb
Host smart-ad64b695-d14b-4f76-bf51-bf6f39c24903
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484373993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.2484373993
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.626304781
Short name T908
Test name
Test status
Simulation time 8380477 ps
CPU time 0.8 seconds
Started Mar 17 02:13:15 PM PDT 24
Finished Mar 17 02:13:16 PM PDT 24
Peak memory 205568 kb
Host smart-c37e1166-1f67-40f6-a54c-8f637f2a3f50
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=626304781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.626304781
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.363410176
Short name T942
Test name
Test status
Simulation time 47084465 ps
CPU time 0.8 seconds
Started Mar 17 02:13:16 PM PDT 24
Finished Mar 17 02:13:17 PM PDT 24
Peak memory 205636 kb
Host smart-c3a9d3f0-baa4-4138-b9ac-1b904d6e433f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363410176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.363410176
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.1881085545
Short name T1003
Test name
Test status
Simulation time 9248563 ps
CPU time 0.72 seconds
Started Mar 17 02:13:21 PM PDT 24
Finished Mar 17 02:13:23 PM PDT 24
Peak memory 205624 kb
Host smart-48d64ff1-7586-4cfb-aaf0-afd206707668
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881085545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.1881085545
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.1360290493
Short name T1033
Test name
Test status
Simulation time 35485844 ps
CPU time 0.69 seconds
Started Mar 17 02:13:22 PM PDT 24
Finished Mar 17 02:13:23 PM PDT 24
Peak memory 205540 kb
Host smart-3626cd44-6368-4ef4-a50e-cf94c748f843
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1360290493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.1360290493
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.3297767003
Short name T1071
Test name
Test status
Simulation time 23853067 ps
CPU time 0.87 seconds
Started Mar 17 02:13:20 PM PDT 24
Finished Mar 17 02:13:21 PM PDT 24
Peak memory 205808 kb
Host smart-02349f3a-4981-498b-a2f9-0e855bcc24cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297767003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.3297767003
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.1901792920
Short name T959
Test name
Test status
Simulation time 34475987 ps
CPU time 0.74 seconds
Started Mar 17 02:13:22 PM PDT 24
Finished Mar 17 02:13:24 PM PDT 24
Peak memory 205560 kb
Host smart-ee3b6d6a-7bdc-4844-a314-0d6ba671c141
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901792920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.1901792920
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.1332155389
Short name T915
Test name
Test status
Simulation time 27109787 ps
CPU time 0.73 seconds
Started Mar 17 02:13:21 PM PDT 24
Finished Mar 17 02:13:22 PM PDT 24
Peak memory 205540 kb
Host smart-38e566d4-e1ff-475b-a5e0-e95ddd13a2e2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332155389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.1332155389
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.370682543
Short name T937
Test name
Test status
Simulation time 126557940 ps
CPU time 8.29 seconds
Started Mar 17 02:12:24 PM PDT 24
Finished Mar 17 02:12:32 PM PDT 24
Peak memory 205924 kb
Host smart-8c309a2e-c549-43c5-b550-b30626bab328
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=370682543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.370682543
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.2991903489
Short name T927
Test name
Test status
Simulation time 578614489 ps
CPU time 12.44 seconds
Started Mar 17 02:12:25 PM PDT 24
Finished Mar 17 02:12:38 PM PDT 24
Peak memory 205956 kb
Host smart-26ce2232-7bd6-4d3f-9a50-ed1ae1b4ea7a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2991903489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.2
991903489
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.1969287631
Short name T930
Test name
Test status
Simulation time 56815079 ps
CPU time 0.89 seconds
Started Mar 17 02:12:25 PM PDT 24
Finished Mar 17 02:12:26 PM PDT 24
Peak memory 205736 kb
Host smart-86d3d5e7-ab8b-45a7-82e8-30c2a9e049dc
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1969287631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.1
969287631
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.3798438806
Short name T920
Test name
Test status
Simulation time 54135014 ps
CPU time 1.25 seconds
Started Mar 17 02:12:23 PM PDT 24
Finished Mar 17 02:12:25 PM PDT 24
Peak memory 214176 kb
Host smart-dcb3b0c4-3f7a-4e96-8cfe-29e9717f0304
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3798438806 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.3798438806
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.2516918476
Short name T1036
Test name
Test status
Simulation time 143984358 ps
CPU time 1.13 seconds
Started Mar 17 02:12:25 PM PDT 24
Finished Mar 17 02:12:26 PM PDT 24
Peak memory 205824 kb
Host smart-f0902c70-d050-4a6b-8020-4280e342dfdb
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2516918476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.2516918476
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.1454303467
Short name T982
Test name
Test status
Simulation time 214740117 ps
CPU time 0.78 seconds
Started Mar 17 02:12:25 PM PDT 24
Finished Mar 17 02:12:26 PM PDT 24
Peak memory 205492 kb
Host smart-57f30df4-1848-4358-9e3c-b7b80cc55785
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454303467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.1454303467
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.1092313560
Short name T983
Test name
Test status
Simulation time 324811125 ps
CPU time 2.51 seconds
Started Mar 17 02:12:24 PM PDT 24
Finished Mar 17 02:12:27 PM PDT 24
Peak memory 214152 kb
Host smart-53ddbbe6-6efc-4be6-9ad0-0ea7dcd399a3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092313560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.1092313560
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.3146156851
Short name T113
Test name
Test status
Simulation time 289557024 ps
CPU time 6.26 seconds
Started Mar 17 02:12:26 PM PDT 24
Finished Mar 17 02:12:32 PM PDT 24
Peak memory 214436 kb
Host smart-bb150037-c9ae-424e-96ba-f47d1bf7ffcf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3146156851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.3146156851
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.1207514731
Short name T1004
Test name
Test status
Simulation time 1479578772 ps
CPU time 11.29 seconds
Started Mar 17 02:12:24 PM PDT 24
Finished Mar 17 02:12:35 PM PDT 24
Peak memory 221604 kb
Host smart-94c19324-84bb-4de1-b0b1-e422947b4628
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207514731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.1207514731
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.2682450248
Short name T957
Test name
Test status
Simulation time 416793381 ps
CPU time 3.59 seconds
Started Mar 17 02:12:25 PM PDT 24
Finished Mar 17 02:12:29 PM PDT 24
Peak memory 216272 kb
Host smart-cb3250e3-cee9-4c33-92af-737924ffdf13
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2682450248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.2682450248
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.4217709583
Short name T925
Test name
Test status
Simulation time 784001840 ps
CPU time 5.96 seconds
Started Mar 17 02:12:26 PM PDT 24
Finished Mar 17 02:12:32 PM PDT 24
Peak memory 214148 kb
Host smart-af0d3e9b-226a-48b4-a936-45573a006089
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217709583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err
.4217709583
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.493267289
Short name T963
Test name
Test status
Simulation time 38836640 ps
CPU time 0.8 seconds
Started Mar 17 02:13:20 PM PDT 24
Finished Mar 17 02:13:21 PM PDT 24
Peak memory 205428 kb
Host smart-6243a5f1-df03-4a15-b5fc-0c7d029419c8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493267289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.493267289
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.846694191
Short name T1046
Test name
Test status
Simulation time 40754591 ps
CPU time 0.72 seconds
Started Mar 17 02:13:23 PM PDT 24
Finished Mar 17 02:13:24 PM PDT 24
Peak memory 205524 kb
Host smart-8a4304c4-a96f-4dca-907b-628c8754bc65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=846694191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.846694191
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.2853038009
Short name T1023
Test name
Test status
Simulation time 15186590 ps
CPU time 0.92 seconds
Started Mar 17 02:13:21 PM PDT 24
Finished Mar 17 02:13:23 PM PDT 24
Peak memory 205740 kb
Host smart-d5c9d186-e724-42ca-a78c-551838b860ee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2853038009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.2853038009
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.1782648670
Short name T910
Test name
Test status
Simulation time 54330960 ps
CPU time 0.79 seconds
Started Mar 17 02:13:23 PM PDT 24
Finished Mar 17 02:13:25 PM PDT 24
Peak memory 205616 kb
Host smart-3d09fff5-8708-4baa-91c9-3a8b1604df97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1782648670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.1782648670
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.3282014465
Short name T1024
Test name
Test status
Simulation time 31974255 ps
CPU time 0.75 seconds
Started Mar 17 02:13:27 PM PDT 24
Finished Mar 17 02:13:28 PM PDT 24
Peak memory 205604 kb
Host smart-e71d1cb9-0ddc-4e38-ac55-c90fd8238507
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3282014465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.3282014465
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.273297607
Short name T1011
Test name
Test status
Simulation time 15895984 ps
CPU time 0.77 seconds
Started Mar 17 02:13:21 PM PDT 24
Finished Mar 17 02:13:23 PM PDT 24
Peak memory 205648 kb
Host smart-fb5e1351-b2ad-42ff-858b-9042a2ef154d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273297607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.273297607
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.1499894263
Short name T914
Test name
Test status
Simulation time 45501416 ps
CPU time 0.67 seconds
Started Mar 17 02:13:20 PM PDT 24
Finished Mar 17 02:13:21 PM PDT 24
Peak memory 205656 kb
Host smart-60040500-b10a-45ec-b3e0-9fe5b99d5572
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499894263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.1499894263
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.2439092419
Short name T919
Test name
Test status
Simulation time 39917373 ps
CPU time 0.69 seconds
Started Mar 17 02:13:20 PM PDT 24
Finished Mar 17 02:13:21 PM PDT 24
Peak memory 205500 kb
Host smart-3be6c902-9650-4ed2-a380-d58eaf4c78b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2439092419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.2439092419
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.1594746624
Short name T971
Test name
Test status
Simulation time 12120423 ps
CPU time 0.85 seconds
Started Mar 17 02:13:22 PM PDT 24
Finished Mar 17 02:13:24 PM PDT 24
Peak memory 205624 kb
Host smart-98a68ec6-6a91-4db0-809d-ef38d00770a9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1594746624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.1594746624
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.921539208
Short name T955
Test name
Test status
Simulation time 11692398 ps
CPU time 0.88 seconds
Started Mar 17 02:13:22 PM PDT 24
Finished Mar 17 02:13:23 PM PDT 24
Peak memory 205540 kb
Host smart-bb377a81-9ae3-4e8a-94c9-1b81d05f5f29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921539208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.921539208
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.778912963
Short name T976
Test name
Test status
Simulation time 524441957 ps
CPU time 18.1 seconds
Started Mar 17 02:12:33 PM PDT 24
Finished Mar 17 02:12:51 PM PDT 24
Peak memory 205812 kb
Host smart-d54b1474-d1fd-4ce4-8f26-4f4ba1ad9164
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=778912963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.778912963
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.2093015318
Short name T913
Test name
Test status
Simulation time 1046625425 ps
CPU time 12.13 seconds
Started Mar 17 02:12:30 PM PDT 24
Finished Mar 17 02:12:42 PM PDT 24
Peak memory 205884 kb
Host smart-f1de2340-0907-4995-90c0-50c55e4c916c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093015318 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.2
093015318
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.2062973527
Short name T960
Test name
Test status
Simulation time 146123272 ps
CPU time 1.45 seconds
Started Mar 17 02:12:30 PM PDT 24
Finished Mar 17 02:12:32 PM PDT 24
Peak memory 205832 kb
Host smart-9ebc1773-64a9-4bd7-a83d-07bf5c6f08b9
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2062973527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.2
062973527
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.195652642
Short name T1070
Test name
Test status
Simulation time 206430232 ps
CPU time 1.7 seconds
Started Mar 17 02:12:36 PM PDT 24
Finished Mar 17 02:12:38 PM PDT 24
Peak memory 214244 kb
Host smart-5162a7a5-3566-4b61-a1ed-86d17bfa6f8b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195652642 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.195652642
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.176399032
Short name T984
Test name
Test status
Simulation time 39429050 ps
CPU time 1.24 seconds
Started Mar 17 02:12:33 PM PDT 24
Finished Mar 17 02:12:34 PM PDT 24
Peak memory 205952 kb
Host smart-5c36da15-7c74-4e7e-a27b-3aeeed3cc8c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176399032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.176399032
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.3546422527
Short name T1062
Test name
Test status
Simulation time 47400849 ps
CPU time 0.71 seconds
Started Mar 17 02:12:29 PM PDT 24
Finished Mar 17 02:12:29 PM PDT 24
Peak memory 205568 kb
Host smart-9ba7e21c-8ffc-4f68-a3e7-61e69a2236b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3546422527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.3546422527
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.1303163868
Short name T1045
Test name
Test status
Simulation time 168155211 ps
CPU time 3.73 seconds
Started Mar 17 02:12:30 PM PDT 24
Finished Mar 17 02:12:34 PM PDT 24
Peak memory 205932 kb
Host smart-728df475-1954-4301-8daa-898219dc6325
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303163868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.1303163868
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.3520231425
Short name T956
Test name
Test status
Simulation time 176461912 ps
CPU time 4.69 seconds
Started Mar 17 02:12:30 PM PDT 24
Finished Mar 17 02:12:35 PM PDT 24
Peak memory 222540 kb
Host smart-c35fb8c8-2a6b-4760-ace5-1d86b6de4cdd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520231425 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.3520231425
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.11370978
Short name T1074
Test name
Test status
Simulation time 713996694 ps
CPU time 7.53 seconds
Started Mar 17 02:12:30 PM PDT 24
Finished Mar 17 02:12:38 PM PDT 24
Peak memory 214392 kb
Host smart-064b0d25-a2cb-45f5-9dd7-7b9d87ae5f20
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11370978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_
SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.ke
ymgr_shadow_reg_errors_with_csr_rw.11370978
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.3657742197
Short name T1008
Test name
Test status
Simulation time 83763546 ps
CPU time 1.86 seconds
Started Mar 17 02:12:30 PM PDT 24
Finished Mar 17 02:12:32 PM PDT 24
Peak memory 214080 kb
Host smart-c796632e-3048-4828-b22b-6348e4484b67
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657742197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.3657742197
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.945699194
Short name T166
Test name
Test status
Simulation time 654162145 ps
CPU time 9.13 seconds
Started Mar 17 02:12:30 PM PDT 24
Finished Mar 17 02:12:39 PM PDT 24
Peak memory 209116 kb
Host smart-2f8ac5e5-f36d-4d89-a188-20e1725fd608
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=945699194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err.
945699194
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.1298628300
Short name T906
Test name
Test status
Simulation time 25633759 ps
CPU time 0.85 seconds
Started Mar 17 02:13:21 PM PDT 24
Finished Mar 17 02:13:23 PM PDT 24
Peak memory 205544 kb
Host smart-f5c176bf-f627-4e20-ad62-d184def1f7f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1298628300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.1298628300
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.80555530
Short name T905
Test name
Test status
Simulation time 24534820 ps
CPU time 0.77 seconds
Started Mar 17 02:13:21 PM PDT 24
Finished Mar 17 02:13:23 PM PDT 24
Peak memory 205632 kb
Host smart-f3fa5b16-d6aa-46c6-ae38-613581f4befa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80555530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.80555530
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.399048832
Short name T928
Test name
Test status
Simulation time 14995915 ps
CPU time 0.83 seconds
Started Mar 17 02:13:21 PM PDT 24
Finished Mar 17 02:13:23 PM PDT 24
Peak memory 205584 kb
Host smart-ee53139b-dc23-45c9-8850-c63e799472f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=399048832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.399048832
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.4087386853
Short name T917
Test name
Test status
Simulation time 34414823 ps
CPU time 0.71 seconds
Started Mar 17 02:13:27 PM PDT 24
Finished Mar 17 02:13:28 PM PDT 24
Peak memory 205568 kb
Host smart-e9156b75-ab5a-406f-a15d-a75f5ac20396
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087386853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.4087386853
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.3424792408
Short name T1072
Test name
Test status
Simulation time 84297806 ps
CPU time 0.78 seconds
Started Mar 17 02:13:27 PM PDT 24
Finished Mar 17 02:13:28 PM PDT 24
Peak memory 205624 kb
Host smart-66136d93-cc6d-45b6-b2aa-6fae1646c5bd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424792408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.3424792408
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.3494371698
Short name T985
Test name
Test status
Simulation time 9108507 ps
CPU time 0.73 seconds
Started Mar 17 02:13:27 PM PDT 24
Finished Mar 17 02:13:28 PM PDT 24
Peak memory 205564 kb
Host smart-801a45f8-958f-4e69-a97f-81d6f264d9e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494371698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.3494371698
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.1835380182
Short name T1000
Test name
Test status
Simulation time 11232064 ps
CPU time 0.88 seconds
Started Mar 17 02:13:27 PM PDT 24
Finished Mar 17 02:13:28 PM PDT 24
Peak memory 205556 kb
Host smart-1eabaa33-48fa-4dcc-a019-9220ccbd1aeb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1835380182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.1835380182
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.2586956091
Short name T941
Test name
Test status
Simulation time 18669629 ps
CPU time 0.8 seconds
Started Mar 17 02:13:29 PM PDT 24
Finished Mar 17 02:13:30 PM PDT 24
Peak memory 205560 kb
Host smart-d642c905-e834-4b24-9b03-ece550cbd51f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586956091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.2586956091
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.2376483985
Short name T1067
Test name
Test status
Simulation time 14552931 ps
CPU time 0.91 seconds
Started Mar 17 02:13:30 PM PDT 24
Finished Mar 17 02:13:31 PM PDT 24
Peak memory 205780 kb
Host smart-d4ca093b-b9a2-43d1-bf52-fa859bb11015
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376483985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.2376483985
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.104644319
Short name T923
Test name
Test status
Simulation time 31562118 ps
CPU time 0.8 seconds
Started Mar 17 02:13:29 PM PDT 24
Finished Mar 17 02:13:30 PM PDT 24
Peak memory 205444 kb
Host smart-173ffd32-e990-4458-a554-71be2b5ad9c7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104644319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.104644319
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.4126368429
Short name T972
Test name
Test status
Simulation time 440013089 ps
CPU time 1.64 seconds
Started Mar 17 02:12:37 PM PDT 24
Finished Mar 17 02:12:38 PM PDT 24
Peak memory 214092 kb
Host smart-0d571745-bfce-403e-9650-24a1c9175dd9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126368429 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.4126368429
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.327110749
Short name T1053
Test name
Test status
Simulation time 22941773 ps
CPU time 1.46 seconds
Started Mar 17 02:12:35 PM PDT 24
Finished Mar 17 02:12:37 PM PDT 24
Peak memory 205864 kb
Host smart-c884f793-ff46-4fc8-b4ad-2992fe1a9be7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=327110749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.327110749
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.4260794485
Short name T1057
Test name
Test status
Simulation time 39832710 ps
CPU time 0.77 seconds
Started Mar 17 02:12:35 PM PDT 24
Finished Mar 17 02:12:36 PM PDT 24
Peak memory 205600 kb
Host smart-2631c921-6955-47cc-847b-6b0c1db5fcda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260794485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.4260794485
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.1063519180
Short name T147
Test name
Test status
Simulation time 40292182 ps
CPU time 1.54 seconds
Started Mar 17 02:12:33 PM PDT 24
Finished Mar 17 02:12:35 PM PDT 24
Peak memory 205996 kb
Host smart-7444ddc4-e63e-4bb4-bf51-d212dc9d3c26
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063519180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.1063519180
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.2072965881
Short name T938
Test name
Test status
Simulation time 575909744 ps
CPU time 6.82 seconds
Started Mar 17 02:12:34 PM PDT 24
Finished Mar 17 02:12:41 PM PDT 24
Peak memory 220580 kb
Host smart-bfe35978-2147-4b3d-b73c-c37a7faac9a4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2072965881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
keymgr_shadow_reg_errors_with_csr_rw.2072965881
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.592966347
Short name T1059
Test name
Test status
Simulation time 1107986970 ps
CPU time 6.21 seconds
Started Mar 17 02:12:36 PM PDT 24
Finished Mar 17 02:12:42 PM PDT 24
Peak memory 214072 kb
Host smart-bc5bab50-330a-4a23-b158-d307751e7086
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592966347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.592966347
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.1882421486
Short name T995
Test name
Test status
Simulation time 767401569 ps
CPU time 18.84 seconds
Started Mar 17 02:12:35 PM PDT 24
Finished Mar 17 02:12:53 PM PDT 24
Peak memory 209544 kb
Host smart-21e2d3ec-f11f-46a5-a826-b47870b94d41
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1882421486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.1882421486
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.856696639
Short name T392
Test name
Test status
Simulation time 30828067 ps
CPU time 1.81 seconds
Started Mar 17 02:12:41 PM PDT 24
Finished Mar 17 02:12:43 PM PDT 24
Peak memory 214096 kb
Host smart-4b265e80-75fa-4bcb-96e5-4d985df22f47
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856696639 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.856696639
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.1582918694
Short name T932
Test name
Test status
Simulation time 33709100 ps
CPU time 1.19 seconds
Started Mar 17 02:12:39 PM PDT 24
Finished Mar 17 02:12:41 PM PDT 24
Peak memory 206084 kb
Host smart-ee1809d5-1de2-40e7-ac69-1b65fe071269
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1582918694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.1582918694
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.872590123
Short name T912
Test name
Test status
Simulation time 46823088 ps
CPU time 0.88 seconds
Started Mar 17 02:12:41 PM PDT 24
Finished Mar 17 02:12:42 PM PDT 24
Peak memory 205568 kb
Host smart-bf984c5c-e103-438e-be90-fe239464619f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=872590123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.872590123
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.278821519
Short name T948
Test name
Test status
Simulation time 469871462 ps
CPU time 4.6 seconds
Started Mar 17 02:12:41 PM PDT 24
Finished Mar 17 02:12:45 PM PDT 24
Peak memory 205872 kb
Host smart-d6d1dd43-9343-4ff5-8b40-5223edead063
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=278821519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sam
e_csr_outstanding.278821519
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.2506707463
Short name T1029
Test name
Test status
Simulation time 222242520 ps
CPU time 6.69 seconds
Started Mar 17 02:12:34 PM PDT 24
Finished Mar 17 02:12:41 PM PDT 24
Peak memory 222532 kb
Host smart-206aa490-4f7f-4141-9743-ef1aae49c23c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2506707463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.2506707463
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.4106235109
Short name T1044
Test name
Test status
Simulation time 185749014 ps
CPU time 7.33 seconds
Started Mar 17 02:12:40 PM PDT 24
Finished Mar 17 02:12:47 PM PDT 24
Peak memory 220304 kb
Host smart-3d7d5f12-c7e2-46f9-998f-b3054ec571bb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106235109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
keymgr_shadow_reg_errors_with_csr_rw.4106235109
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.1445088699
Short name T945
Test name
Test status
Simulation time 140644952 ps
CPU time 2.61 seconds
Started Mar 17 02:12:43 PM PDT 24
Finished Mar 17 02:12:46 PM PDT 24
Peak memory 213968 kb
Host smart-f9b7b216-0626-4244-a6f0-1a9f92708ce3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445088699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.1445088699
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.2424033724
Short name T153
Test name
Test status
Simulation time 804919545 ps
CPU time 18.12 seconds
Started Mar 17 02:12:42 PM PDT 24
Finished Mar 17 02:13:00 PM PDT 24
Peak memory 209308 kb
Host smart-7bdd5029-10fd-41df-b839-c493611c1498
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2424033724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.2424033724
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.1272389155
Short name T935
Test name
Test status
Simulation time 89875958 ps
CPU time 2.03 seconds
Started Mar 17 02:12:46 PM PDT 24
Finished Mar 17 02:12:48 PM PDT 24
Peak memory 214128 kb
Host smart-cc56f7ff-ea3e-4086-95fa-5292f9520c57
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1272389155 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.1272389155
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.1122542661
Short name T141
Test name
Test status
Simulation time 54847080 ps
CPU time 1.25 seconds
Started Mar 17 02:12:47 PM PDT 24
Finished Mar 17 02:12:48 PM PDT 24
Peak memory 205904 kb
Host smart-f84cb2f8-4a8e-4e24-9458-0010ffe9053b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1122542661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.1122542661
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.2272633613
Short name T950
Test name
Test status
Simulation time 8293637 ps
CPU time 0.74 seconds
Started Mar 17 02:12:46 PM PDT 24
Finished Mar 17 02:12:47 PM PDT 24
Peak memory 205612 kb
Host smart-7e4437d2-c43b-4076-90bc-4e78987a538d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272633613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.2272633613
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.2583772191
Short name T966
Test name
Test status
Simulation time 144063157 ps
CPU time 2.8 seconds
Started Mar 17 02:12:46 PM PDT 24
Finished Mar 17 02:12:48 PM PDT 24
Peak memory 205900 kb
Host smart-0a7a7729-5a30-465c-a13a-8857c91b333d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583772191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.2583772191
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.1840136646
Short name T1021
Test name
Test status
Simulation time 133239032 ps
CPU time 2.52 seconds
Started Mar 17 02:12:40 PM PDT 24
Finished Mar 17 02:12:43 PM PDT 24
Peak memory 214508 kb
Host smart-717a56eb-7402-4fe4-b6f6-bc1a1912946a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1840136646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.1840136646
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.160159130
Short name T1065
Test name
Test status
Simulation time 615676396 ps
CPU time 7.25 seconds
Started Mar 17 02:12:47 PM PDT 24
Finished Mar 17 02:12:55 PM PDT 24
Peak memory 214376 kb
Host smart-edd6dcbc-1e8b-4b34-a1c7-90632011ce8a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160159130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.k
eymgr_shadow_reg_errors_with_csr_rw.160159130
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.921028235
Short name T1013
Test name
Test status
Simulation time 119903436 ps
CPU time 4.62 seconds
Started Mar 17 02:12:48 PM PDT 24
Finished Mar 17 02:12:53 PM PDT 24
Peak memory 214076 kb
Host smart-ba2ea3c0-8375-4a92-ad16-42ab092c488d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=921028235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.921028235
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.2418683012
Short name T951
Test name
Test status
Simulation time 84371889 ps
CPU time 1.53 seconds
Started Mar 17 02:12:46 PM PDT 24
Finished Mar 17 02:12:48 PM PDT 24
Peak memory 214184 kb
Host smart-8af50e45-f65d-4462-a687-06b3a8e719ab
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2418683012 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.2418683012
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.1793137554
Short name T998
Test name
Test status
Simulation time 12855271 ps
CPU time 0.92 seconds
Started Mar 17 02:12:48 PM PDT 24
Finished Mar 17 02:12:49 PM PDT 24
Peak memory 205620 kb
Host smart-8c91e540-586d-4a89-9ea8-7b9eafb77834
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1793137554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.1793137554
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.3833134130
Short name T968
Test name
Test status
Simulation time 11704706 ps
CPU time 0.76 seconds
Started Mar 17 02:12:45 PM PDT 24
Finished Mar 17 02:12:46 PM PDT 24
Peak memory 205560 kb
Host smart-f71d7a5f-1ce1-4daa-bf4d-6e8a283f0a65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833134130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.3833134130
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.4187393517
Short name T1054
Test name
Test status
Simulation time 344440446 ps
CPU time 4.28 seconds
Started Mar 17 02:12:47 PM PDT 24
Finished Mar 17 02:12:52 PM PDT 24
Peak memory 205924 kb
Host smart-381f1646-c2ea-492c-bb24-62d7687afe6c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187393517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.4187393517
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.3363061271
Short name T112
Test name
Test status
Simulation time 86103816 ps
CPU time 2.98 seconds
Started Mar 17 02:12:46 PM PDT 24
Finished Mar 17 02:12:49 PM PDT 24
Peak memory 214404 kb
Host smart-b8fec5fe-542d-42af-bd38-f641e2855cad
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3363061271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.3363061271
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.2142595015
Short name T962
Test name
Test status
Simulation time 414562257 ps
CPU time 9.25 seconds
Started Mar 17 02:12:47 PM PDT 24
Finished Mar 17 02:12:56 PM PDT 24
Peak memory 214420 kb
Host smart-34f4baf1-36f6-441a-95f0-6c380d199955
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2142595015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
keymgr_shadow_reg_errors_with_csr_rw.2142595015
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.3818145668
Short name T991
Test name
Test status
Simulation time 148552965 ps
CPU time 1.48 seconds
Started Mar 17 02:12:50 PM PDT 24
Finished Mar 17 02:12:51 PM PDT 24
Peak memory 214084 kb
Host smart-37b9e743-bc4c-4a97-b4a8-f6239ab1e394
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818145668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.3818145668
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.3730483959
Short name T1028
Test name
Test status
Simulation time 31941104 ps
CPU time 1.89 seconds
Started Mar 17 02:12:54 PM PDT 24
Finished Mar 17 02:12:56 PM PDT 24
Peak memory 214140 kb
Host smart-6bf64a13-a3c1-4b77-a7a6-56592da6f0f3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730483959 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.3730483959
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.2459437835
Short name T975
Test name
Test status
Simulation time 11677734 ps
CPU time 1.07 seconds
Started Mar 17 02:12:51 PM PDT 24
Finished Mar 17 02:12:53 PM PDT 24
Peak memory 205668 kb
Host smart-b7a0cf30-2b9a-4c80-b8c5-c4c0255795dc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2459437835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.2459437835
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.2122904412
Short name T1052
Test name
Test status
Simulation time 10455098 ps
CPU time 0.71 seconds
Started Mar 17 02:12:53 PM PDT 24
Finished Mar 17 02:12:54 PM PDT 24
Peak memory 205600 kb
Host smart-33bb85a1-1b04-458b-a92b-1fe47ac8be41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122904412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.2122904412
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.868974688
Short name T939
Test name
Test status
Simulation time 61263510 ps
CPU time 1.98 seconds
Started Mar 17 02:12:54 PM PDT 24
Finished Mar 17 02:12:56 PM PDT 24
Peak memory 205952 kb
Host smart-90f3432d-7932-4d8b-8fb0-03d7a72aa890
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=868974688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sam
e_csr_outstanding.868974688
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.3066711194
Short name T977
Test name
Test status
Simulation time 564410399 ps
CPU time 3.37 seconds
Started Mar 17 02:12:45 PM PDT 24
Finished Mar 17 02:12:48 PM PDT 24
Peak memory 219204 kb
Host smart-2c5d76a5-1f42-49e4-a223-7cd8675454f8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3066711194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.3066711194
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.1845194948
Short name T116
Test name
Test status
Simulation time 333742479 ps
CPU time 6.44 seconds
Started Mar 17 02:12:48 PM PDT 24
Finished Mar 17 02:12:54 PM PDT 24
Peak memory 220124 kb
Host smart-f97c45d4-2414-49b2-ad23-547eddfba915
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1845194948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.1845194948
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.2901967119
Short name T973
Test name
Test status
Simulation time 150121119 ps
CPU time 5.28 seconds
Started Mar 17 02:12:52 PM PDT 24
Finished Mar 17 02:12:57 PM PDT 24
Peak memory 213896 kb
Host smart-76c1734b-2924-4b9c-a863-57427c086ae9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2901967119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.2901967119
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.698957345
Short name T161
Test name
Test status
Simulation time 368408765 ps
CPU time 4.24 seconds
Started Mar 17 02:12:54 PM PDT 24
Finished Mar 17 02:12:58 PM PDT 24
Peak memory 209556 kb
Host smart-6b724cd5-b047-434a-8560-28272f52a5d1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698957345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err.
698957345
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.1409740460
Short name T705
Test name
Test status
Simulation time 13686883 ps
CPU time 0.89 seconds
Started Mar 17 02:42:28 PM PDT 24
Finished Mar 17 02:42:29 PM PDT 24
Peak memory 206460 kb
Host smart-1369dd07-813f-4582-a243-aad66bb81577
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409740460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.1409740460
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.398393322
Short name T114
Test name
Test status
Simulation time 114872830 ps
CPU time 2.62 seconds
Started Mar 17 02:42:22 PM PDT 24
Finished Mar 17 02:42:25 PM PDT 24
Peak memory 214792 kb
Host smart-0d4d9c48-501b-4a1d-9f8d-618f4b0f375c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=398393322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.398393322
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.2350618369
Short name T19
Test name
Test status
Simulation time 147517435 ps
CPU time 3.14 seconds
Started Mar 17 02:42:28 PM PDT 24
Finished Mar 17 02:42:31 PM PDT 24
Peak memory 219924 kb
Host smart-e3ff6013-10b4-4819-873a-b245ee9dde9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2350618369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.2350618369
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.3939705303
Short name T791
Test name
Test status
Simulation time 217150801 ps
CPU time 2.55 seconds
Started Mar 17 02:42:21 PM PDT 24
Finished Mar 17 02:42:24 PM PDT 24
Peak memory 209664 kb
Host smart-7a3c8263-5bbc-4be5-8d95-80eaf54a8cf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3939705303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.3939705303
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.3986349366
Short name T353
Test name
Test status
Simulation time 98452307 ps
CPU time 4.15 seconds
Started Mar 17 02:42:19 PM PDT 24
Finished Mar 17 02:42:23 PM PDT 24
Peak memory 219888 kb
Host smart-26d28c9f-4f16-4c25-82ef-58e74648adcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986349366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.3986349366
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.1302282602
Short name T734
Test name
Test status
Simulation time 52211953 ps
CPU time 2.35 seconds
Started Mar 17 02:42:19 PM PDT 24
Finished Mar 17 02:42:22 PM PDT 24
Peak memory 222260 kb
Host smart-b9d10e5c-bebd-4d6a-93fe-0a6a24176b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1302282602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.1302282602
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.2317571244
Short name T202
Test name
Test status
Simulation time 178726638 ps
CPU time 3.34 seconds
Started Mar 17 02:42:19 PM PDT 24
Finished Mar 17 02:42:23 PM PDT 24
Peak memory 208348 kb
Host smart-6ba36b7e-e6eb-4bcc-908a-9e1e73724ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317571244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.2317571244
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.2525216085
Short name T12
Test name
Test status
Simulation time 1089871309 ps
CPU time 11.13 seconds
Started Mar 17 02:42:28 PM PDT 24
Finished Mar 17 02:42:39 PM PDT 24
Peak memory 235084 kb
Host smart-9ac11a5d-cd5d-4d5d-8577-b39ba50d10f4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525216085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.2525216085
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload.3547744694
Short name T208
Test name
Test status
Simulation time 28476118 ps
CPU time 2.13 seconds
Started Mar 17 02:42:21 PM PDT 24
Finished Mar 17 02:42:23 PM PDT 24
Peak memory 207192 kb
Host smart-9baa915f-abc4-48c4-9c2a-3fca416d1f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3547744694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.3547744694
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.3785146169
Short name T825
Test name
Test status
Simulation time 91977622 ps
CPU time 2.75 seconds
Started Mar 17 02:42:20 PM PDT 24
Finished Mar 17 02:42:23 PM PDT 24
Peak memory 207216 kb
Host smart-fb85ee46-46c1-4078-a12f-8d9119362f57
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785146169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.3785146169
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.3826374421
Short name T681
Test name
Test status
Simulation time 933589515 ps
CPU time 31.33 seconds
Started Mar 17 02:42:19 PM PDT 24
Finished Mar 17 02:42:51 PM PDT 24
Peak memory 208896 kb
Host smart-933a2dc8-5f3b-4216-b425-a474cf72007d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826374421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.3826374421
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.357053266
Short name T130
Test name
Test status
Simulation time 259548350 ps
CPU time 4.14 seconds
Started Mar 17 02:42:29 PM PDT 24
Finished Mar 17 02:42:33 PM PDT 24
Peak memory 210124 kb
Host smart-cbb4be63-9223-4da1-8f29-10fa5f7b8daf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357053266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.357053266
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.2810121132
Short name T903
Test name
Test status
Simulation time 172765979 ps
CPU time 4.6 seconds
Started Mar 17 02:42:19 PM PDT 24
Finished Mar 17 02:42:25 PM PDT 24
Peak memory 209044 kb
Host smart-040af55e-1988-458c-93f1-dc5d9d7669db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2810121132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.2810121132
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.1550602185
Short name T228
Test name
Test status
Simulation time 788209797 ps
CPU time 14.89 seconds
Started Mar 17 02:42:27 PM PDT 24
Finished Mar 17 02:42:42 PM PDT 24
Peak memory 218028 kb
Host smart-dc943e56-6fc1-4e44-8896-7a4eefa70762
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550602185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.1550602185
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.3251767863
Short name T476
Test name
Test status
Simulation time 519733068 ps
CPU time 5.99 seconds
Started Mar 17 02:42:22 PM PDT 24
Finished Mar 17 02:42:28 PM PDT 24
Peak memory 218860 kb
Host smart-a24b2adc-7176-4773-9cc3-30ce74dccbdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251767863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.3251767863
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.3194531640
Short name T598
Test name
Test status
Simulation time 80690469 ps
CPU time 2.41 seconds
Started Mar 17 02:42:30 PM PDT 24
Finished Mar 17 02:42:32 PM PDT 24
Peak memory 210180 kb
Host smart-6a8bd4ba-e94e-4147-a9a3-5b2042028ebd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3194531640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.3194531640
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.2730241448
Short name T571
Test name
Test status
Simulation time 30305610 ps
CPU time 0.74 seconds
Started Mar 17 02:42:33 PM PDT 24
Finished Mar 17 02:42:34 PM PDT 24
Peak memory 206248 kb
Host smart-bb6d7dd1-039d-46cd-8a9c-82e269107540
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2730241448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.2730241448
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.351990710
Short name T248
Test name
Test status
Simulation time 1187440639 ps
CPU time 35.58 seconds
Started Mar 17 02:42:28 PM PDT 24
Finished Mar 17 02:43:03 PM PDT 24
Peak memory 210744 kb
Host smart-c7e6d4fe-eb85-42dc-b512-bd1193e26195
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=351990710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.351990710
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.1928036239
Short name T751
Test name
Test status
Simulation time 2863347196 ps
CPU time 14.31 seconds
Started Mar 17 02:42:29 PM PDT 24
Finished Mar 17 02:42:43 PM PDT 24
Peak memory 221672 kb
Host smart-7f1ddc95-003c-4aca-a462-7028f6ba6e69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1928036239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.1928036239
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_random.3641312008
Short name T857
Test name
Test status
Simulation time 31114073061 ps
CPU time 72.7 seconds
Started Mar 17 02:42:29 PM PDT 24
Finished Mar 17 02:43:42 PM PDT 24
Peak memory 210824 kb
Host smart-b6206b06-382a-4e5a-bf80-844a45b4e8ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3641312008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.3641312008
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.2958721062
Short name T103
Test name
Test status
Simulation time 547606647 ps
CPU time 9.2 seconds
Started Mar 17 02:42:35 PM PDT 24
Finished Mar 17 02:42:44 PM PDT 24
Peak memory 234996 kb
Host smart-00f2ce85-1efc-4767-9024-23e7190f2c95
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958721062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.2958721062
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload.3059440250
Short name T785
Test name
Test status
Simulation time 18161363971 ps
CPU time 80.96 seconds
Started Mar 17 02:42:29 PM PDT 24
Finished Mar 17 02:43:50 PM PDT 24
Peak memory 209076 kb
Host smart-352202b4-a323-46cc-9884-a55b1625f4d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059440250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.3059440250
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.387056940
Short name T373
Test name
Test status
Simulation time 44990500 ps
CPU time 1.96 seconds
Started Mar 17 02:42:29 PM PDT 24
Finished Mar 17 02:42:31 PM PDT 24
Peak memory 207700 kb
Host smart-ba7a3c8a-fb42-4c30-8c75-cbd2ac2c7acf
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387056940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.387056940
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.3754438407
Short name T804
Test name
Test status
Simulation time 63539478 ps
CPU time 3.33 seconds
Started Mar 17 02:42:27 PM PDT 24
Finished Mar 17 02:42:31 PM PDT 24
Peak memory 209168 kb
Host smart-48232552-e746-491c-8cb5-1946509a97a6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3754438407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.3754438407
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.3590525499
Short name T349
Test name
Test status
Simulation time 1967855910 ps
CPU time 4.95 seconds
Started Mar 17 02:42:28 PM PDT 24
Finished Mar 17 02:42:33 PM PDT 24
Peak memory 209244 kb
Host smart-a7e47fe9-333c-4dc4-8624-3ea7f276bbce
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3590525499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.3590525499
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.599723108
Short name T823
Test name
Test status
Simulation time 518287368 ps
CPU time 4.27 seconds
Started Mar 17 02:42:29 PM PDT 24
Finished Mar 17 02:42:33 PM PDT 24
Peak memory 210104 kb
Host smart-7eb20ecc-d140-4127-a8b9-4692d64dcccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=599723108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.599723108
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.1643506486
Short name T848
Test name
Test status
Simulation time 849169145 ps
CPU time 3.1 seconds
Started Mar 17 02:42:29 PM PDT 24
Finished Mar 17 02:42:32 PM PDT 24
Peak memory 208860 kb
Host smart-423d6b09-346e-48f0-897d-9ccd8c90d66f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643506486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.1643506486
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.3643479955
Short name T305
Test name
Test status
Simulation time 926198721 ps
CPU time 7.14 seconds
Started Mar 17 02:42:35 PM PDT 24
Finished Mar 17 02:42:42 PM PDT 24
Peak memory 218724 kb
Host smart-f2f4bbfe-951e-4219-b464-d54114d26ffd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3643479955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.3643479955
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.2857887173
Short name T205
Test name
Test status
Simulation time 155485639 ps
CPU time 6.2 seconds
Started Mar 17 02:42:28 PM PDT 24
Finished Mar 17 02:42:34 PM PDT 24
Peak memory 209204 kb
Host smart-4b200463-e3c8-49e7-b34d-ed66fa28997f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2857887173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.2857887173
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.1012097697
Short name T128
Test name
Test status
Simulation time 3683191327 ps
CPU time 25.82 seconds
Started Mar 17 02:42:34 PM PDT 24
Finished Mar 17 02:43:00 PM PDT 24
Peak memory 211736 kb
Host smart-3e6dfae6-9385-4b17-9a0c-804857ea2fbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1012097697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.1012097697
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.3381320547
Short name T198
Test name
Test status
Simulation time 30870406 ps
CPU time 2.61 seconds
Started Mar 17 02:43:12 PM PDT 24
Finished Mar 17 02:43:16 PM PDT 24
Peak memory 214808 kb
Host smart-68a0efa5-0d49-4b11-88ee-bd9c706ea54c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3381320547 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.3381320547
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.1900154176
Short name T10
Test name
Test status
Simulation time 207738002 ps
CPU time 8.11 seconds
Started Mar 17 02:43:10 PM PDT 24
Finished Mar 17 02:43:18 PM PDT 24
Peak memory 221808 kb
Host smart-265d1885-dadc-4e1b-a352-90b57fba3f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1900154176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.1900154176
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.2954389552
Short name T258
Test name
Test status
Simulation time 98478147 ps
CPU time 4.39 seconds
Started Mar 17 02:43:11 PM PDT 24
Finished Mar 17 02:43:16 PM PDT 24
Peak memory 218568 kb
Host smart-b1641e9c-9a57-4307-b6d4-b390bb07b188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2954389552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.2954389552
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.1390039951
Short name T269
Test name
Test status
Simulation time 737160179 ps
CPU time 8.12 seconds
Started Mar 17 02:43:10 PM PDT 24
Finished Mar 17 02:43:18 PM PDT 24
Peak memory 210452 kb
Host smart-a24a8b80-9b48-4b39-aa30-0f079f5041c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390039951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.1390039951
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.2856010771
Short name T329
Test name
Test status
Simulation time 242946250 ps
CPU time 4.25 seconds
Started Mar 17 02:43:13 PM PDT 24
Finished Mar 17 02:43:19 PM PDT 24
Peak memory 207136 kb
Host smart-0792c13b-667b-4dfd-ba53-f71443c874a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2856010771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.2856010771
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.2022138391
Short name T870
Test name
Test status
Simulation time 389439692 ps
CPU time 10.28 seconds
Started Mar 17 02:43:12 PM PDT 24
Finished Mar 17 02:43:23 PM PDT 24
Peak memory 208068 kb
Host smart-8bd45817-f2ab-4aa2-bc88-9dbd99a1dd08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022138391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.2022138391
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.2401953354
Short name T487
Test name
Test status
Simulation time 134686566 ps
CPU time 3.77 seconds
Started Mar 17 02:43:06 PM PDT 24
Finished Mar 17 02:43:09 PM PDT 24
Peak memory 208440 kb
Host smart-9dc6fd27-ce99-4716-b158-feb0417f43cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2401953354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.2401953354
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.620070740
Short name T481
Test name
Test status
Simulation time 316384405 ps
CPU time 3.62 seconds
Started Mar 17 02:43:11 PM PDT 24
Finished Mar 17 02:43:16 PM PDT 24
Peak memory 207212 kb
Host smart-2f292b3d-6145-4174-bd8a-caf879cfb265
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620070740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.620070740
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.737737167
Short name T820
Test name
Test status
Simulation time 1223137590 ps
CPU time 18.22 seconds
Started Mar 17 02:43:10 PM PDT 24
Finished Mar 17 02:43:28 PM PDT 24
Peak memory 208584 kb
Host smart-b896c3ca-d2a9-4979-9a42-257e20fd99ae
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=737737167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.737737167
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.2745805695
Short name T434
Test name
Test status
Simulation time 204727641 ps
CPU time 2.72 seconds
Started Mar 17 02:43:12 PM PDT 24
Finished Mar 17 02:43:16 PM PDT 24
Peak memory 207772 kb
Host smart-f8276974-9b53-48eb-bf1d-6305ea0430f7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2745805695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.2745805695
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.694967107
Short name T721
Test name
Test status
Simulation time 92763133 ps
CPU time 1.61 seconds
Started Mar 17 02:43:12 PM PDT 24
Finished Mar 17 02:43:15 PM PDT 24
Peak memory 209156 kb
Host smart-83b9d1d4-49f0-4002-9486-afb6c55fc228
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694967107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.694967107
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.1458091142
Short name T467
Test name
Test status
Simulation time 36207861 ps
CPU time 2.3 seconds
Started Mar 17 02:43:07 PM PDT 24
Finished Mar 17 02:43:09 PM PDT 24
Peak memory 206956 kb
Host smart-e0dab6ed-e1db-4a07-8e41-d222447d31e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1458091142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.1458091142
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.3607500402
Short name T313
Test name
Test status
Simulation time 4816711835 ps
CPU time 32.26 seconds
Started Mar 17 02:43:11 PM PDT 24
Finished Mar 17 02:43:43 PM PDT 24
Peak memory 220576 kb
Host smart-df6befa4-bbf7-4241-a9fa-9ca1d85ac759
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3607500402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.3607500402
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.3532591171
Short name T746
Test name
Test status
Simulation time 1129296089 ps
CPU time 12.77 seconds
Started Mar 17 02:43:09 PM PDT 24
Finished Mar 17 02:43:22 PM PDT 24
Peak memory 209268 kb
Host smart-b7f57789-3166-490d-aa2f-95dfe2b62861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3532591171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.3532591171
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.2187846734
Short name T589
Test name
Test status
Simulation time 93238648 ps
CPU time 2.67 seconds
Started Mar 17 02:43:11 PM PDT 24
Finished Mar 17 02:43:16 PM PDT 24
Peak memory 211260 kb
Host smart-a19a1fee-7d46-449c-ba3c-718987345563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187846734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.2187846734
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.3973921188
Short name T432
Test name
Test status
Simulation time 28062360 ps
CPU time 0.95 seconds
Started Mar 17 02:43:15 PM PDT 24
Finished Mar 17 02:43:17 PM PDT 24
Peak memory 206616 kb
Host smart-eae86519-6fea-4516-9501-4924320ba8d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973921188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.3973921188
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.3573317890
Short name T28
Test name
Test status
Simulation time 546686413 ps
CPU time 4.56 seconds
Started Mar 17 02:43:17 PM PDT 24
Finished Mar 17 02:43:22 PM PDT 24
Peak memory 209632 kb
Host smart-1cf7d489-e60d-4351-b97a-a661dbea57b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573317890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.3573317890
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.2501284119
Short name T592
Test name
Test status
Simulation time 1341363003 ps
CPU time 25.65 seconds
Started Mar 17 02:43:15 PM PDT 24
Finished Mar 17 02:43:42 PM PDT 24
Peak memory 210276 kb
Host smart-cd99c26f-355f-4851-bb44-c6fcfc4e0752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2501284119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.2501284119
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.3137587227
Short name T612
Test name
Test status
Simulation time 54444010 ps
CPU time 3.13 seconds
Started Mar 17 02:43:14 PM PDT 24
Finished Mar 17 02:43:18 PM PDT 24
Peak memory 209536 kb
Host smart-25f0953e-8a2b-49fd-a630-2447365648bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3137587227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.3137587227
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_random.4091343044
Short name T740
Test name
Test status
Simulation time 1365880306 ps
CPU time 10.85 seconds
Started Mar 17 02:43:10 PM PDT 24
Finished Mar 17 02:43:21 PM PDT 24
Peak memory 214800 kb
Host smart-42df2918-4efe-4395-9e61-484d3bceb69d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4091343044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.4091343044
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.4124941751
Short name T321
Test name
Test status
Simulation time 120543880 ps
CPU time 2 seconds
Started Mar 17 02:43:12 PM PDT 24
Finished Mar 17 02:43:16 PM PDT 24
Peak memory 208824 kb
Host smart-6c90ee6e-875a-4e2d-b0b0-b934cedb8056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4124941751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.4124941751
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.2282908261
Short name T616
Test name
Test status
Simulation time 498598625 ps
CPU time 9.33 seconds
Started Mar 17 02:43:10 PM PDT 24
Finished Mar 17 02:43:20 PM PDT 24
Peak memory 209296 kb
Host smart-692f972a-b4f2-44aa-ae58-1e3e80248efa
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282908261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.2282908261
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.3145110885
Short name T525
Test name
Test status
Simulation time 74839561 ps
CPU time 3.33 seconds
Started Mar 17 02:43:12 PM PDT 24
Finished Mar 17 02:43:17 PM PDT 24
Peak memory 207216 kb
Host smart-15bfa4da-b098-4323-b13c-eb817d461804
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3145110885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.3145110885
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.3553598546
Short name T320
Test name
Test status
Simulation time 482601591 ps
CPU time 4.07 seconds
Started Mar 17 02:43:23 PM PDT 24
Finished Mar 17 02:43:27 PM PDT 24
Peak memory 208840 kb
Host smart-fd2d1507-e6fc-4787-bc5e-f928a208c4d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553598546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.3553598546
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.699141350
Short name T573
Test name
Test status
Simulation time 236319029 ps
CPU time 2.58 seconds
Started Mar 17 02:43:09 PM PDT 24
Finished Mar 17 02:43:12 PM PDT 24
Peak memory 208816 kb
Host smart-347e7b48-5169-4930-a440-b2d954d1d990
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=699141350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.699141350
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.2053836682
Short name T362
Test name
Test status
Simulation time 254431643 ps
CPU time 5.85 seconds
Started Mar 17 02:43:18 PM PDT 24
Finished Mar 17 02:43:24 PM PDT 24
Peak memory 208668 kb
Host smart-89db43b4-8334-4d45-9104-f02ceae627a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053836682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.2053836682
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.3025534326
Short name T904
Test name
Test status
Simulation time 59727132 ps
CPU time 2.34 seconds
Started Mar 17 02:43:20 PM PDT 24
Finished Mar 17 02:43:22 PM PDT 24
Peak memory 210304 kb
Host smart-3c1665b0-a1a4-414a-b976-952459403c1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025534326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.3025534326
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.1446207117
Short name T798
Test name
Test status
Simulation time 18739137 ps
CPU time 1.04 seconds
Started Mar 17 02:43:19 PM PDT 24
Finished Mar 17 02:43:21 PM PDT 24
Peak memory 206472 kb
Host smart-d2e2d9b9-0519-49e3-9c3d-b3d06fb6ebe4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1446207117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.1446207117
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.3688586563
Short name T374
Test name
Test status
Simulation time 204300592 ps
CPU time 2.6 seconds
Started Mar 17 02:43:17 PM PDT 24
Finished Mar 17 02:43:20 PM PDT 24
Peak memory 218760 kb
Host smart-1fbd09c1-e4e3-46f7-a4b2-e154ce24eb67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3688586563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.3688586563
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.1875965287
Short name T394
Test name
Test status
Simulation time 451910340 ps
CPU time 4.49 seconds
Started Mar 17 02:43:19 PM PDT 24
Finished Mar 17 02:43:24 PM PDT 24
Peak memory 209916 kb
Host smart-6d09defa-8bbe-41f0-85bf-cd96ed5c018c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1875965287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.1875965287
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.280419839
Short name T347
Test name
Test status
Simulation time 608391511 ps
CPU time 6.74 seconds
Started Mar 17 02:43:19 PM PDT 24
Finished Mar 17 02:43:26 PM PDT 24
Peak memory 222896 kb
Host smart-c84b6206-85f6-40f4-a827-0798f8cbb280
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=280419839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.280419839
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_random.4186777157
Short name T284
Test name
Test status
Simulation time 474816084 ps
CPU time 5.46 seconds
Started Mar 17 02:43:23 PM PDT 24
Finished Mar 17 02:43:28 PM PDT 24
Peak memory 218664 kb
Host smart-f8b07a36-e920-430d-a2cf-442ad62133eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186777157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.4186777157
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.324541836
Short name T889
Test name
Test status
Simulation time 223146099 ps
CPU time 2.97 seconds
Started Mar 17 02:43:21 PM PDT 24
Finished Mar 17 02:43:24 PM PDT 24
Peak memory 208992 kb
Host smart-e0890c38-23b7-412a-8942-c49f2b261a41
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324541836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.324541836
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.1038799656
Short name T515
Test name
Test status
Simulation time 93241268 ps
CPU time 4.23 seconds
Started Mar 17 02:43:16 PM PDT 24
Finished Mar 17 02:43:21 PM PDT 24
Peak memory 208880 kb
Host smart-c447b907-1b1a-4b18-be31-7b5892a257b7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1038799656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.1038799656
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.1237926273
Short name T611
Test name
Test status
Simulation time 122562372 ps
CPU time 3.98 seconds
Started Mar 17 02:43:17 PM PDT 24
Finished Mar 17 02:43:21 PM PDT 24
Peak memory 207280 kb
Host smart-7f4276d1-bb5e-4ee9-9e61-e1fa08e2f0a9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237926273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.1237926273
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.1397354762
Short name T490
Test name
Test status
Simulation time 162695428 ps
CPU time 4.88 seconds
Started Mar 17 02:43:22 PM PDT 24
Finished Mar 17 02:43:27 PM PDT 24
Peak memory 208288 kb
Host smart-e4182494-53af-4d8d-9ee9-c85704e3b561
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1397354762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.1397354762
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.1190975244
Short name T572
Test name
Test status
Simulation time 45821596 ps
CPU time 2.41 seconds
Started Mar 17 02:43:23 PM PDT 24
Finished Mar 17 02:43:26 PM PDT 24
Peak memory 209792 kb
Host smart-2f41379b-53a8-47cd-b945-358409c062b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190975244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.1190975244
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.2223987110
Short name T441
Test name
Test status
Simulation time 38354357 ps
CPU time 2.27 seconds
Started Mar 17 02:43:16 PM PDT 24
Finished Mar 17 02:43:19 PM PDT 24
Peak memory 207180 kb
Host smart-062b6957-63a8-4bb1-9222-04561bdfdc2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223987110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.2223987110
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.2924930994
Short name T600
Test name
Test status
Simulation time 2925190234 ps
CPU time 28.58 seconds
Started Mar 17 02:43:21 PM PDT 24
Finished Mar 17 02:43:50 PM PDT 24
Peak memory 209492 kb
Host smart-1e0ea100-144a-4a3b-9478-43c111b61510
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924930994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.2924930994
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_stress_all_with_rand_reset.2492355147
Short name T752
Test name
Test status
Simulation time 403232885 ps
CPU time 9.74 seconds
Started Mar 17 02:43:19 PM PDT 24
Finished Mar 17 02:43:30 PM PDT 24
Peak memory 223008 kb
Host smart-6dee6f65-c062-45f1-826d-c0a401389dd7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2492355147 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all_with_rand_reset.2492355147
Directory /workspace/12.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.1778100292
Short name T574
Test name
Test status
Simulation time 412002919 ps
CPU time 4.76 seconds
Started Mar 17 02:43:21 PM PDT 24
Finished Mar 17 02:43:26 PM PDT 24
Peak memory 209584 kb
Host smart-23d2a0af-fe10-4487-a214-363ee91009cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778100292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.1778100292
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.773842537
Short name T777
Test name
Test status
Simulation time 79020300 ps
CPU time 0.75 seconds
Started Mar 17 02:43:24 PM PDT 24
Finished Mar 17 02:43:25 PM PDT 24
Peak memory 206412 kb
Host smart-c5593e06-4107-4b03-bc20-8199ad9bafb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=773842537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.773842537
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.2886618327
Short name T424
Test name
Test status
Simulation time 216784550 ps
CPU time 4.11 seconds
Started Mar 17 02:43:19 PM PDT 24
Finished Mar 17 02:43:23 PM PDT 24
Peak memory 215780 kb
Host smart-656d2f8c-8f24-45af-a1ad-e21c60e3fe95
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2886618327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.2886618327
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.1014593912
Short name T231
Test name
Test status
Simulation time 534046584 ps
CPU time 13.25 seconds
Started Mar 17 02:43:20 PM PDT 24
Finished Mar 17 02:43:35 PM PDT 24
Peak memory 219540 kb
Host smart-0b3cb69c-af1b-4edb-8bf5-9d847355af01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1014593912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.1014593912
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.1549779196
Short name T679
Test name
Test status
Simulation time 105905013 ps
CPU time 2.2 seconds
Started Mar 17 02:43:21 PM PDT 24
Finished Mar 17 02:43:24 PM PDT 24
Peak memory 207848 kb
Host smart-1b3d5c98-0cec-499b-b14d-e77e50e22c5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549779196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.1549779196
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.1292859325
Short name T638
Test name
Test status
Simulation time 757668567 ps
CPU time 10.16 seconds
Started Mar 17 02:43:22 PM PDT 24
Finished Mar 17 02:43:32 PM PDT 24
Peak memory 214808 kb
Host smart-06ccc72e-240c-42dc-b8e0-9d3c080b3afc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292859325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.1292859325
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.2393639382
Short name T36
Test name
Test status
Simulation time 51701947 ps
CPU time 3.17 seconds
Started Mar 17 02:43:22 PM PDT 24
Finished Mar 17 02:43:26 PM PDT 24
Peak memory 209492 kb
Host smart-614c9662-09ee-413b-9708-50e28104ec36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2393639382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.2393639382
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.972350683
Short name T52
Test name
Test status
Simulation time 197962570 ps
CPU time 3.05 seconds
Started Mar 17 02:43:25 PM PDT 24
Finished Mar 17 02:43:28 PM PDT 24
Peak memory 209428 kb
Host smart-50f308f0-bf4f-422c-a500-dec1612a21dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972350683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.972350683
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.2998806062
Short name T620
Test name
Test status
Simulation time 77025627 ps
CPU time 3.76 seconds
Started Mar 17 02:43:20 PM PDT 24
Finished Mar 17 02:43:24 PM PDT 24
Peak memory 209764 kb
Host smart-2a9a54db-e74d-49fe-aae4-c535e31fde83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2998806062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.2998806062
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.2229933036
Short name T337
Test name
Test status
Simulation time 213318173 ps
CPU time 6.6 seconds
Started Mar 17 02:43:23 PM PDT 24
Finished Mar 17 02:43:30 PM PDT 24
Peak memory 207784 kb
Host smart-7b795176-0c02-4816-99d8-e279e0572500
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229933036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.2229933036
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.198087177
Short name T672
Test name
Test status
Simulation time 234391236 ps
CPU time 6.27 seconds
Started Mar 17 02:43:23 PM PDT 24
Finished Mar 17 02:43:29 PM PDT 24
Peak memory 209016 kb
Host smart-dc773d3b-07dc-4793-9aae-eaade140acc0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=198087177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.198087177
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.1859799970
Short name T478
Test name
Test status
Simulation time 116751903 ps
CPU time 3.34 seconds
Started Mar 17 02:43:21 PM PDT 24
Finished Mar 17 02:43:25 PM PDT 24
Peak memory 208936 kb
Host smart-4bd3f77f-f5c8-43a4-800a-9a965530d239
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859799970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.1859799970
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.1172341623
Short name T553
Test name
Test status
Simulation time 3254124734 ps
CPU time 33.31 seconds
Started Mar 17 02:43:20 PM PDT 24
Finished Mar 17 02:43:54 PM PDT 24
Peak memory 208472 kb
Host smart-e39daef5-0e55-4ba0-9079-3bb511d09816
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1172341623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.1172341623
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.1381526430
Short name T484
Test name
Test status
Simulation time 59135281 ps
CPU time 3.35 seconds
Started Mar 17 02:43:20 PM PDT 24
Finished Mar 17 02:43:23 PM PDT 24
Peak memory 208744 kb
Host smart-6df30eff-5ebe-436e-aaf0-30d44750fd79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1381526430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.1381526430
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.497868309
Short name T540
Test name
Test status
Simulation time 79956380 ps
CPU time 3.6 seconds
Started Mar 17 02:43:20 PM PDT 24
Finished Mar 17 02:43:24 PM PDT 24
Peak memory 208996 kb
Host smart-0b2300ee-ea6e-4221-a9cc-7b5e5b1e9ea6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497868309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.497868309
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.718608762
Short name T183
Test name
Test status
Simulation time 5535920942 ps
CPU time 34.33 seconds
Started Mar 17 02:43:21 PM PDT 24
Finished Mar 17 02:43:56 PM PDT 24
Peak memory 221724 kb
Host smart-24537fb0-07e7-4df1-9c1a-8969ae7625ef
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718608762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.718608762
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_stress_all_with_rand_reset.739671244
Short name T628
Test name
Test status
Simulation time 388160880 ps
CPU time 7.3 seconds
Started Mar 17 02:43:22 PM PDT 24
Finished Mar 17 02:43:29 PM PDT 24
Peak memory 223068 kb
Host smart-68f9035d-3ff9-4331-b484-56bd909e10fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739671244 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all_with_rand_reset.739671244
Directory /workspace/13.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.2834725921
Short name T674
Test name
Test status
Simulation time 20837701 ps
CPU time 1.05 seconds
Started Mar 17 02:43:30 PM PDT 24
Finished Mar 17 02:43:31 PM PDT 24
Peak memory 206576 kb
Host smart-5924ec02-4089-4892-a585-72d9be445989
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2834725921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.2834725921
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.3009706652
Short name T409
Test name
Test status
Simulation time 176367237 ps
CPU time 8.91 seconds
Started Mar 17 02:43:24 PM PDT 24
Finished Mar 17 02:43:33 PM PDT 24
Peak memory 214756 kb
Host smart-2332fb6d-ad4c-440f-917d-158fd63423e3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3009706652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.3009706652
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.3037254358
Short name T29
Test name
Test status
Simulation time 445851420 ps
CPU time 3.02 seconds
Started Mar 17 02:43:26 PM PDT 24
Finished Mar 17 02:43:29 PM PDT 24
Peak memory 223180 kb
Host smart-5491afeb-949a-4301-bb88-54f615e3bcc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3037254358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.3037254358
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.1330943550
Short name T413
Test name
Test status
Simulation time 74077622 ps
CPU time 2.3 seconds
Started Mar 17 02:43:26 PM PDT 24
Finished Mar 17 02:43:29 PM PDT 24
Peak memory 210296 kb
Host smart-bc4ec51c-b99b-493c-a6fd-ea3f008fa286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1330943550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.1330943550
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.1544316761
Short name T352
Test name
Test status
Simulation time 312632993 ps
CPU time 6.57 seconds
Started Mar 17 02:43:24 PM PDT 24
Finished Mar 17 02:43:31 PM PDT 24
Peak memory 214752 kb
Host smart-43a7d0ed-b55f-413e-95e3-5ec18717d758
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1544316761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.1544316761
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.3612113952
Short name T530
Test name
Test status
Simulation time 283823403 ps
CPU time 4 seconds
Started Mar 17 02:43:26 PM PDT 24
Finished Mar 17 02:43:30 PM PDT 24
Peak memory 210972 kb
Host smart-f6ebe04b-f2bc-41c7-b448-6421c19b7905
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612113952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.3612113952
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.3546706267
Short name T689
Test name
Test status
Simulation time 167507258 ps
CPU time 3.01 seconds
Started Mar 17 02:43:28 PM PDT 24
Finished Mar 17 02:43:31 PM PDT 24
Peak memory 216480 kb
Host smart-55db60bb-4d58-4d4f-9970-0326b6f2dabf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3546706267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.3546706267
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.1126632012
Short name T286
Test name
Test status
Simulation time 1024660415 ps
CPU time 10.81 seconds
Started Mar 17 02:43:27 PM PDT 24
Finished Mar 17 02:43:38 PM PDT 24
Peak memory 208488 kb
Host smart-93269c02-26ab-4882-b3b7-f80e4cd3bbc6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126632012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.1126632012
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.3340160482
Short name T829
Test name
Test status
Simulation time 60898572 ps
CPU time 1.96 seconds
Started Mar 17 02:43:27 PM PDT 24
Finished Mar 17 02:43:29 PM PDT 24
Peak memory 207988 kb
Host smart-a072f164-aa54-406a-80ba-d1e59a3bc03e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340160482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.3340160482
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.3991527754
Short name T370
Test name
Test status
Simulation time 277577687 ps
CPU time 3.59 seconds
Started Mar 17 02:43:27 PM PDT 24
Finished Mar 17 02:43:30 PM PDT 24
Peak memory 209216 kb
Host smart-050a4975-a72b-430e-b590-2526b3573269
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991527754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.3991527754
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.1529380082
Short name T497
Test name
Test status
Simulation time 341238511 ps
CPU time 4.86 seconds
Started Mar 17 02:43:25 PM PDT 24
Finished Mar 17 02:43:30 PM PDT 24
Peak memory 220836 kb
Host smart-12146301-0e33-4478-9474-e92490d41325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1529380082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.1529380082
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.2377784782
Short name T802
Test name
Test status
Simulation time 261229059 ps
CPU time 3.04 seconds
Started Mar 17 02:43:24 PM PDT 24
Finished Mar 17 02:43:27 PM PDT 24
Peak memory 207036 kb
Host smart-7ab0ab1d-7e64-4f40-87a6-ae4de79ac516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2377784782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.2377784782
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.3650483254
Short name T200
Test name
Test status
Simulation time 595951135 ps
CPU time 9.64 seconds
Started Mar 17 02:43:27 PM PDT 24
Finished Mar 17 02:43:37 PM PDT 24
Peak memory 216028 kb
Host smart-f4c937a9-54e8-40f4-98a4-e098b53d4a7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3650483254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.3650483254
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_stress_all_with_rand_reset.104240900
Short name T398
Test name
Test status
Simulation time 1158506532 ps
CPU time 13.24 seconds
Started Mar 17 02:43:32 PM PDT 24
Finished Mar 17 02:43:45 PM PDT 24
Peak memory 220704 kb
Host smart-80c0a636-2c0d-48d2-8cb9-814bda81d677
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104240900 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all_with_rand_reset.104240900
Directory /workspace/14.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.3862046431
Short name T627
Test name
Test status
Simulation time 413955633 ps
CPU time 5.6 seconds
Started Mar 17 02:43:25 PM PDT 24
Finished Mar 17 02:43:31 PM PDT 24
Peak memory 209852 kb
Host smart-f39bf063-c1a3-41a8-981a-183b99645065
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862046431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.3862046431
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.2939072766
Short name T60
Test name
Test status
Simulation time 82369030 ps
CPU time 3.73 seconds
Started Mar 17 02:43:25 PM PDT 24
Finished Mar 17 02:43:29 PM PDT 24
Peak memory 210856 kb
Host smart-dae1f071-c14d-491c-a301-eb548e125914
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2939072766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.2939072766
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.3933320954
Short name T686
Test name
Test status
Simulation time 20315407 ps
CPU time 0.88 seconds
Started Mar 17 02:43:34 PM PDT 24
Finished Mar 17 02:43:35 PM PDT 24
Peak memory 206388 kb
Host smart-56a8c846-41da-42d7-9942-c6591c6e4ccb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3933320954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.3933320954
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.4120968656
Short name T633
Test name
Test status
Simulation time 65530098 ps
CPU time 4.4 seconds
Started Mar 17 02:43:31 PM PDT 24
Finished Mar 17 02:43:36 PM PDT 24
Peak memory 215120 kb
Host smart-dc50fb38-41b9-499e-b1e6-d88c2b4eb5c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4120968656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.4120968656
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.2288749121
Short name T691
Test name
Test status
Simulation time 223843509 ps
CPU time 3.74 seconds
Started Mar 17 02:43:32 PM PDT 24
Finished Mar 17 02:43:36 PM PDT 24
Peak memory 208836 kb
Host smart-af415b27-b2aa-46f8-b99a-5127ea9f3b7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288749121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.2288749121
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.4260965597
Short name T177
Test name
Test status
Simulation time 456345552 ps
CPU time 3.22 seconds
Started Mar 17 02:43:36 PM PDT 24
Finished Mar 17 02:43:39 PM PDT 24
Peak memory 209460 kb
Host smart-b2521321-6ef5-49ac-b681-562a3da592c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4260965597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.4260965597
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.120520497
Short name T789
Test name
Test status
Simulation time 231294720 ps
CPU time 4.06 seconds
Started Mar 17 02:43:31 PM PDT 24
Finished Mar 17 02:43:35 PM PDT 24
Peak memory 215448 kb
Host smart-9fcc93e3-778b-43bd-8696-4dc33cb0ca2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120520497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.120520497
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.981129864
Short name T696
Test name
Test status
Simulation time 83273499 ps
CPU time 3.89 seconds
Started Mar 17 02:43:33 PM PDT 24
Finished Mar 17 02:43:36 PM PDT 24
Peak memory 209084 kb
Host smart-bd913891-4448-46c3-8e56-f28601fcdb7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=981129864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.981129864
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.3726199357
Short name T526
Test name
Test status
Simulation time 255782537 ps
CPU time 3.38 seconds
Started Mar 17 02:43:33 PM PDT 24
Finished Mar 17 02:43:36 PM PDT 24
Peak memory 207260 kb
Host smart-fead51d4-d5de-46ca-95ca-753a61911db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726199357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.3726199357
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.1919324907
Short name T665
Test name
Test status
Simulation time 134563394 ps
CPU time 5.18 seconds
Started Mar 17 02:43:31 PM PDT 24
Finished Mar 17 02:43:36 PM PDT 24
Peak memory 207184 kb
Host smart-e4fe52a5-3b45-4f11-89be-80b40c16df66
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1919324907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.1919324907
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.3531560151
Short name T730
Test name
Test status
Simulation time 2360943069 ps
CPU time 26.77 seconds
Started Mar 17 02:43:32 PM PDT 24
Finished Mar 17 02:43:59 PM PDT 24
Peak memory 209052 kb
Host smart-515f2b69-2308-4526-af62-4b49318a2589
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531560151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.3531560151
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.2543905219
Short name T447
Test name
Test status
Simulation time 54203642 ps
CPU time 2.9 seconds
Started Mar 17 02:43:31 PM PDT 24
Finished Mar 17 02:43:34 PM PDT 24
Peak memory 208816 kb
Host smart-d08acb20-e950-4ba1-868f-bdc0b5e1a74b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2543905219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.2543905219
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.1501223430
Short name T458
Test name
Test status
Simulation time 40942163 ps
CPU time 1.55 seconds
Started Mar 17 02:43:34 PM PDT 24
Finished Mar 17 02:43:36 PM PDT 24
Peak memory 208216 kb
Host smart-90240a17-d7d3-45da-bcde-bd436197864b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1501223430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.1501223430
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.3598707396
Short name T641
Test name
Test status
Simulation time 55702496 ps
CPU time 2.78 seconds
Started Mar 17 02:43:31 PM PDT 24
Finished Mar 17 02:43:34 PM PDT 24
Peak memory 209012 kb
Host smart-89e61905-61d6-433f-b638-9af147cee0ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3598707396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.3598707396
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.197513856
Short name T342
Test name
Test status
Simulation time 65462722 ps
CPU time 4.19 seconds
Started Mar 17 02:43:32 PM PDT 24
Finished Mar 17 02:43:36 PM PDT 24
Peak memory 210388 kb
Host smart-4225da11-3d74-4643-b2cd-f82ab4156c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197513856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.197513856
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.3284385777
Short name T680
Test name
Test status
Simulation time 121526418 ps
CPU time 1.85 seconds
Started Mar 17 02:43:32 PM PDT 24
Finished Mar 17 02:43:34 PM PDT 24
Peak memory 210052 kb
Host smart-b8aa4ccd-8efc-45d6-9ed2-6e849ec076e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3284385777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.3284385777
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.1699425514
Short name T853
Test name
Test status
Simulation time 56852682 ps
CPU time 0.94 seconds
Started Mar 17 02:43:38 PM PDT 24
Finished Mar 17 02:43:39 PM PDT 24
Peak memory 206512 kb
Host smart-0593586f-804c-469a-9292-2950fe74dcdc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1699425514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.1699425514
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.773195146
Short name T27
Test name
Test status
Simulation time 448181164 ps
CPU time 5.73 seconds
Started Mar 17 02:43:36 PM PDT 24
Finished Mar 17 02:43:42 PM PDT 24
Peak memory 210920 kb
Host smart-1e371d0a-6d53-4874-84f0-9f2a2fd43682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=773195146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.773195146
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.704023276
Short name T898
Test name
Test status
Simulation time 311832198 ps
CPU time 4.22 seconds
Started Mar 17 02:43:32 PM PDT 24
Finished Mar 17 02:43:37 PM PDT 24
Peak memory 209632 kb
Host smart-b20bcffa-88d6-4f23-8617-40a1c3eb4f43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704023276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.704023276
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.456051941
Short name T866
Test name
Test status
Simulation time 136680181 ps
CPU time 4.81 seconds
Started Mar 17 02:43:36 PM PDT 24
Finished Mar 17 02:43:41 PM PDT 24
Peak memory 209712 kb
Host smart-ef08c6db-07f6-479b-be7a-90286ae03b42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456051941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.456051941
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.718875152
Short name T302
Test name
Test status
Simulation time 1073049427 ps
CPU time 7.44 seconds
Started Mar 17 02:43:38 PM PDT 24
Finished Mar 17 02:43:45 PM PDT 24
Peak memory 211076 kb
Host smart-8da4c7a3-61e5-4e22-a3bd-2ac1def98a53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718875152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.718875152
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.1242305604
Short name T749
Test name
Test status
Simulation time 131927475 ps
CPU time 3.53 seconds
Started Mar 17 02:43:37 PM PDT 24
Finished Mar 17 02:43:40 PM PDT 24
Peak memory 209948 kb
Host smart-eeb23480-f55b-4273-82a8-089f41fad116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1242305604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.1242305604
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.430356371
Short name T240
Test name
Test status
Simulation time 958254853 ps
CPU time 6.93 seconds
Started Mar 17 02:43:31 PM PDT 24
Finished Mar 17 02:43:38 PM PDT 24
Peak memory 210032 kb
Host smart-be638da9-eb03-41cb-9fb0-43745f91c85b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=430356371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.430356371
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.2720916902
Short name T442
Test name
Test status
Simulation time 79182936 ps
CPU time 2.53 seconds
Started Mar 17 02:43:32 PM PDT 24
Finished Mar 17 02:43:35 PM PDT 24
Peak memory 207296 kb
Host smart-e245f17b-43be-4f0b-a6f5-9801bfdfbc66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720916902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.2720916902
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.1602880885
Short name T247
Test name
Test status
Simulation time 4033265728 ps
CPU time 6.48 seconds
Started Mar 17 02:43:31 PM PDT 24
Finished Mar 17 02:43:38 PM PDT 24
Peak memory 208452 kb
Host smart-18150cbd-9cf6-4147-97e1-de1799e2d8db
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1602880885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.1602880885
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.476049871
Short name T325
Test name
Test status
Simulation time 95682109 ps
CPU time 2.09 seconds
Started Mar 17 02:43:34 PM PDT 24
Finished Mar 17 02:43:36 PM PDT 24
Peak memory 209040 kb
Host smart-b76341f6-a556-47b1-8260-b8478924585b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=476049871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.476049871
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.1442984105
Short name T570
Test name
Test status
Simulation time 183537743 ps
CPU time 5.46 seconds
Started Mar 17 02:43:33 PM PDT 24
Finished Mar 17 02:43:39 PM PDT 24
Peak memory 208384 kb
Host smart-f440b940-6160-441c-8eac-8d95146432f2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442984105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.1442984105
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.1367627537
Short name T213
Test name
Test status
Simulation time 51127695 ps
CPU time 3.34 seconds
Started Mar 17 02:43:36 PM PDT 24
Finished Mar 17 02:43:39 PM PDT 24
Peak memory 209624 kb
Host smart-d82a2798-07aa-49fa-972d-e7d5544e09a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367627537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.1367627537
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.681298769
Short name T473
Test name
Test status
Simulation time 469224115 ps
CPU time 6.14 seconds
Started Mar 17 02:43:33 PM PDT 24
Finished Mar 17 02:43:39 PM PDT 24
Peak memory 208996 kb
Host smart-4c0b7701-b8eb-4653-aec2-3f1c14deb33c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=681298769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.681298769
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all_with_rand_reset.1254091201
Short name T101
Test name
Test status
Simulation time 565136444 ps
CPU time 18.02 seconds
Started Mar 17 02:43:38 PM PDT 24
Finished Mar 17 02:43:56 PM PDT 24
Peak memory 223028 kb
Host smart-45844b3e-6545-4ffa-bc4e-823f676ef692
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1254091201 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all_with_rand_reset.1254091201
Directory /workspace/16.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.1959220414
Short name T539
Test name
Test status
Simulation time 396677040 ps
CPU time 5.47 seconds
Started Mar 17 02:43:39 PM PDT 24
Finished Mar 17 02:43:45 PM PDT 24
Peak memory 208608 kb
Host smart-1f8bfa7c-6e96-404b-b0e7-4e8c9c9d9ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959220414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.1959220414
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.2517539935
Short name T192
Test name
Test status
Simulation time 406645003 ps
CPU time 2.63 seconds
Started Mar 17 02:43:41 PM PDT 24
Finished Mar 17 02:43:44 PM PDT 24
Peak memory 210232 kb
Host smart-0b8bc47b-9bc9-4a1c-9d5a-8461d8a2d4a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2517539935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.2517539935
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.4271308666
Short name T824
Test name
Test status
Simulation time 35926682 ps
CPU time 0.76 seconds
Started Mar 17 02:43:39 PM PDT 24
Finished Mar 17 02:43:40 PM PDT 24
Peak memory 206356 kb
Host smart-6b7544b4-82f1-4500-9918-b33c38379e9f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271308666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.4271308666
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.3616243898
Short name T416
Test name
Test status
Simulation time 117859288 ps
CPU time 3.35 seconds
Started Mar 17 02:43:40 PM PDT 24
Finished Mar 17 02:43:43 PM PDT 24
Peak memory 214708 kb
Host smart-e9518ec3-4c76-42a3-a711-2f62184403dd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3616243898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.3616243898
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.4109044531
Short name T502
Test name
Test status
Simulation time 848224835 ps
CPU time 6.21 seconds
Started Mar 17 02:43:36 PM PDT 24
Finished Mar 17 02:43:42 PM PDT 24
Peak memory 208456 kb
Host smart-742a7408-6d58-423d-9cf0-4f5e5dd9d963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4109044531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.4109044531
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.3311587581
Short name T295
Test name
Test status
Simulation time 1755417895 ps
CPU time 7.25 seconds
Started Mar 17 02:43:35 PM PDT 24
Finished Mar 17 02:43:42 PM PDT 24
Peak memory 222828 kb
Host smart-1d707f6b-2fca-4e2f-8901-7406ddf9140c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3311587581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.3311587581
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.2397224182
Short name T769
Test name
Test status
Simulation time 75198112 ps
CPU time 3.64 seconds
Started Mar 17 02:43:41 PM PDT 24
Finished Mar 17 02:43:45 PM PDT 24
Peak memory 210720 kb
Host smart-a3b7e5dc-9e15-4598-a68f-1a530138e86b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397224182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.2397224182
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.2814335789
Short name T678
Test name
Test status
Simulation time 1219290183 ps
CPU time 4.75 seconds
Started Mar 17 02:43:36 PM PDT 24
Finished Mar 17 02:43:41 PM PDT 24
Peak memory 208268 kb
Host smart-5633acba-6bfa-4806-951e-fedafe3df38d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814335789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.2814335789
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.3260984584
Short name T206
Test name
Test status
Simulation time 1376954615 ps
CPU time 19 seconds
Started Mar 17 02:43:36 PM PDT 24
Finished Mar 17 02:43:55 PM PDT 24
Peak memory 208404 kb
Host smart-e7eb34ab-04df-4dc7-949c-2ac916fd295b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260984584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.3260984584
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.834533001
Short name T322
Test name
Test status
Simulation time 194110779 ps
CPU time 5.96 seconds
Started Mar 17 02:43:36 PM PDT 24
Finished Mar 17 02:43:42 PM PDT 24
Peak memory 208644 kb
Host smart-c62ffc28-0141-4111-9817-44549fba64e5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=834533001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.834533001
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.2477274826
Short name T511
Test name
Test status
Simulation time 5783531244 ps
CPU time 13.94 seconds
Started Mar 17 02:43:36 PM PDT 24
Finished Mar 17 02:43:50 PM PDT 24
Peak memory 208464 kb
Host smart-12fbbe94-36c1-4c29-9f40-dbbc8868ffde
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477274826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.2477274826
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.1961572070
Short name T781
Test name
Test status
Simulation time 439054323 ps
CPU time 3.46 seconds
Started Mar 17 02:43:41 PM PDT 24
Finished Mar 17 02:43:45 PM PDT 24
Peak memory 208948 kb
Host smart-ab733f5e-6ab2-4118-9c09-949fbe860b49
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1961572070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.1961572070
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.373461970
Short name T845
Test name
Test status
Simulation time 298603024 ps
CPU time 2.72 seconds
Started Mar 17 02:43:38 PM PDT 24
Finished Mar 17 02:43:41 PM PDT 24
Peak memory 214672 kb
Host smart-7cd8324b-be45-4f37-8083-678402a60513
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=373461970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.373461970
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.861483649
Short name T875
Test name
Test status
Simulation time 1011810703 ps
CPU time 2.8 seconds
Started Mar 17 02:43:37 PM PDT 24
Finished Mar 17 02:43:40 PM PDT 24
Peak memory 207068 kb
Host smart-03b23fc3-7357-4023-9878-b40d08ab8181
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=861483649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.861483649
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.794911408
Short name T53
Test name
Test status
Simulation time 2407152652 ps
CPU time 9.21 seconds
Started Mar 17 02:43:38 PM PDT 24
Finished Mar 17 02:43:48 PM PDT 24
Peak memory 216556 kb
Host smart-0f6869f9-acae-4eea-9b85-fedfb741a176
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794911408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.794911408
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.1385646670
Short name T289
Test name
Test status
Simulation time 50036743 ps
CPU time 3.13 seconds
Started Mar 17 02:43:38 PM PDT 24
Finished Mar 17 02:43:42 PM PDT 24
Peak memory 208536 kb
Host smart-14c911f2-d043-49e3-8dfa-540e838e709b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385646670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.1385646670
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.263663447
Short name T203
Test name
Test status
Simulation time 295684464 ps
CPU time 2.67 seconds
Started Mar 17 02:43:35 PM PDT 24
Finished Mar 17 02:43:38 PM PDT 24
Peak memory 210364 kb
Host smart-b34b5f57-2673-4147-a9ef-fee80894d9b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=263663447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.263663447
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.1279987268
Short name T517
Test name
Test status
Simulation time 23903271 ps
CPU time 0.79 seconds
Started Mar 17 02:43:43 PM PDT 24
Finished Mar 17 02:43:44 PM PDT 24
Peak memory 206444 kb
Host smart-7a3b84fb-f6a9-422d-97dc-95826d846a4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1279987268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.1279987268
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.508796735
Short name T360
Test name
Test status
Simulation time 217527547 ps
CPU time 4.54 seconds
Started Mar 17 02:43:36 PM PDT 24
Finished Mar 17 02:43:41 PM PDT 24
Peak memory 214820 kb
Host smart-5e0d4bed-5ffb-45d1-b9ae-24c180c3833f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=508796735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.508796735
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.4172355358
Short name T38
Test name
Test status
Simulation time 656172997 ps
CPU time 1.9 seconds
Started Mar 17 02:43:41 PM PDT 24
Finished Mar 17 02:43:43 PM PDT 24
Peak memory 209356 kb
Host smart-249c9e74-d10c-4984-a9a5-9ed433001174
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172355358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.4172355358
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.4102313036
Short name T694
Test name
Test status
Simulation time 82576512 ps
CPU time 1.51 seconds
Started Mar 17 02:43:36 PM PDT 24
Finished Mar 17 02:43:38 PM PDT 24
Peak memory 207540 kb
Host smart-5aafd351-9612-4a79-8e21-7fbbfdf67237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102313036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.4102313036
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.1997476728
Short name T764
Test name
Test status
Simulation time 1813587283 ps
CPU time 8.35 seconds
Started Mar 17 02:43:41 PM PDT 24
Finished Mar 17 02:43:49 PM PDT 24
Peak memory 214772 kb
Host smart-a6400685-5fb1-4ab9-a2ef-34d80c085d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1997476728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.1997476728
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.2649066047
Short name T882
Test name
Test status
Simulation time 722698468 ps
CPU time 4.43 seconds
Started Mar 17 02:43:38 PM PDT 24
Finished Mar 17 02:43:43 PM PDT 24
Peak memory 211824 kb
Host smart-e1dd574c-6098-43d8-a038-6cce20d93040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2649066047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.2649066047
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.1338969975
Short name T885
Test name
Test status
Simulation time 56350891 ps
CPU time 2.3 seconds
Started Mar 17 02:43:39 PM PDT 24
Finished Mar 17 02:43:42 PM PDT 24
Peak memory 215764 kb
Host smart-88963e4d-b1c7-44d0-878b-8ff9c12a2ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338969975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.1338969975
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.651601709
Short name T126
Test name
Test status
Simulation time 2107095885 ps
CPU time 11.53 seconds
Started Mar 17 02:43:36 PM PDT 24
Finished Mar 17 02:43:48 PM PDT 24
Peak memory 207764 kb
Host smart-c83675de-8dac-42a1-8695-1bb300f6a316
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651601709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.651601709
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.2914711461
Short name T819
Test name
Test status
Simulation time 112806324 ps
CPU time 4.5 seconds
Started Mar 17 02:43:38 PM PDT 24
Finished Mar 17 02:43:43 PM PDT 24
Peak memory 207080 kb
Host smart-28c95534-9bc1-4ff5-9e4b-ed4bb0fe6b6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2914711461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.2914711461
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.1355790917
Short name T84
Test name
Test status
Simulation time 1876200318 ps
CPU time 34.82 seconds
Started Mar 17 02:43:37 PM PDT 24
Finished Mar 17 02:44:12 PM PDT 24
Peak memory 208776 kb
Host smart-8ec6b10f-11aa-4271-b11d-d2f5645f6536
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355790917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.1355790917
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.4271183802
Short name T867
Test name
Test status
Simulation time 97818844 ps
CPU time 2.82 seconds
Started Mar 17 02:43:38 PM PDT 24
Finished Mar 17 02:43:41 PM PDT 24
Peak memory 207092 kb
Host smart-21ed8fde-9fe4-4406-a0e4-31258213bb7d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4271183802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.4271183802
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.2246484715
Short name T700
Test name
Test status
Simulation time 231734436 ps
CPU time 2.63 seconds
Started Mar 17 02:43:39 PM PDT 24
Finished Mar 17 02:43:41 PM PDT 24
Peak memory 208440 kb
Host smart-c04dcfc9-233e-4d8e-8686-18e325bf0211
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246484715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.2246484715
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.1963328624
Short name T653
Test name
Test status
Simulation time 46250973 ps
CPU time 2.96 seconds
Started Mar 17 02:43:36 PM PDT 24
Finished Mar 17 02:43:39 PM PDT 24
Peak memory 210688 kb
Host smart-12ba6466-7bfe-45be-9456-b93bfa070f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963328624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.1963328624
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.2232098515
Short name T741
Test name
Test status
Simulation time 132360026 ps
CPU time 2.99 seconds
Started Mar 17 02:43:35 PM PDT 24
Finished Mar 17 02:43:38 PM PDT 24
Peak memory 207152 kb
Host smart-9960e66d-9a09-460e-9e09-53b802c8bd81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232098515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.2232098515
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.733556298
Short name T516
Test name
Test status
Simulation time 664974653 ps
CPU time 6.57 seconds
Started Mar 17 02:43:37 PM PDT 24
Finished Mar 17 02:43:44 PM PDT 24
Peak memory 210620 kb
Host smart-d0bdc4a4-b00c-4be3-9b5d-4d6addf22711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=733556298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.733556298
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.620528802
Short name T57
Test name
Test status
Simulation time 196784111 ps
CPU time 2.62 seconds
Started Mar 17 02:43:37 PM PDT 24
Finished Mar 17 02:43:40 PM PDT 24
Peak memory 210860 kb
Host smart-32ef2ccc-a8e3-48a7-8408-a311bcb9d1af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620528802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.620528802
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.1858075585
Short name T815
Test name
Test status
Simulation time 181065190 ps
CPU time 0.84 seconds
Started Mar 17 02:43:47 PM PDT 24
Finished Mar 17 02:43:48 PM PDT 24
Peak memory 206360 kb
Host smart-7fe328e3-3c4d-4024-9692-231f4e62575c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1858075585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.1858075585
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.3722895712
Short name T135
Test name
Test status
Simulation time 64754603 ps
CPU time 2.86 seconds
Started Mar 17 02:43:44 PM PDT 24
Finished Mar 17 02:43:47 PM PDT 24
Peak memory 215484 kb
Host smart-5095669d-63b9-4f87-9f57-1136fa8f93c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3722895712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.3722895712
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.4048744015
Short name T220
Test name
Test status
Simulation time 1535741603 ps
CPU time 14.61 seconds
Started Mar 17 02:43:43 PM PDT 24
Finished Mar 17 02:43:58 PM PDT 24
Peak memory 222884 kb
Host smart-8d7958e9-32f4-4e65-ad21-d4c56fbc5493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4048744015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.4048744015
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.2787898350
Short name T405
Test name
Test status
Simulation time 415093659 ps
CPU time 3.15 seconds
Started Mar 17 02:43:43 PM PDT 24
Finished Mar 17 02:43:47 PM PDT 24
Peak memory 207976 kb
Host smart-ca141423-d752-4cca-a4fc-d6fc5cbb81c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2787898350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.2787898350
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.4044857857
Short name T586
Test name
Test status
Simulation time 243023615 ps
CPU time 7.5 seconds
Started Mar 17 02:43:42 PM PDT 24
Finished Mar 17 02:43:51 PM PDT 24
Peak memory 210264 kb
Host smart-f5311087-a3fa-4b42-805a-d8bf3665a27a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4044857857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.4044857857
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.2836475396
Short name T304
Test name
Test status
Simulation time 420722082 ps
CPU time 5.74 seconds
Started Mar 17 02:43:41 PM PDT 24
Finished Mar 17 02:43:48 PM PDT 24
Peak memory 210632 kb
Host smart-1ef7c4c7-9442-4994-967b-d9c03f500b8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2836475396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.2836475396
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.1522652109
Short name T46
Test name
Test status
Simulation time 257835966 ps
CPU time 2.46 seconds
Started Mar 17 02:43:45 PM PDT 24
Finished Mar 17 02:43:48 PM PDT 24
Peak memory 215980 kb
Host smart-4183d2a6-57cf-4544-81b9-1f0ccc310d35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522652109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.1522652109
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.3938367471
Short name T758
Test name
Test status
Simulation time 65085987 ps
CPU time 2.71 seconds
Started Mar 17 02:43:43 PM PDT 24
Finished Mar 17 02:43:46 PM PDT 24
Peak memory 208444 kb
Host smart-ec556364-aeca-41f7-bf32-3c46054048bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938367471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.3938367471
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.47056803
Short name T382
Test name
Test status
Simulation time 5469497586 ps
CPU time 30.5 seconds
Started Mar 17 02:43:45 PM PDT 24
Finished Mar 17 02:44:16 PM PDT 24
Peak memory 208640 kb
Host smart-70afb167-a14e-4c6c-8671-fb2aff2b19fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=47056803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.47056803
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.1274053640
Short name T78
Test name
Test status
Simulation time 55700199 ps
CPU time 3.02 seconds
Started Mar 17 02:43:42 PM PDT 24
Finished Mar 17 02:43:46 PM PDT 24
Peak memory 207264 kb
Host smart-141ba909-3dce-4996-bda1-ba7265ddc187
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274053640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.1274053640
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.4253374523
Short name T868
Test name
Test status
Simulation time 46444884 ps
CPU time 2.66 seconds
Started Mar 17 02:43:42 PM PDT 24
Finished Mar 17 02:43:45 PM PDT 24
Peak memory 208620 kb
Host smart-c7c6294f-e7ec-4dd7-9e60-b268a5254200
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253374523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.4253374523
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.3658638075
Short name T107
Test name
Test status
Simulation time 736634268 ps
CPU time 6.9 seconds
Started Mar 17 02:43:42 PM PDT 24
Finished Mar 17 02:43:49 PM PDT 24
Peak memory 208600 kb
Host smart-8e9ac6e2-3baa-46f1-b1cb-2320d1b9eade
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3658638075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.3658638075
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.1977565967
Short name T613
Test name
Test status
Simulation time 62827143 ps
CPU time 2.02 seconds
Started Mar 17 02:43:43 PM PDT 24
Finished Mar 17 02:43:46 PM PDT 24
Peak memory 207960 kb
Host smart-12154fb7-a875-4d9b-80fd-bfe55b131d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1977565967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.1977565967
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.3078045999
Short name T427
Test name
Test status
Simulation time 251284829 ps
CPU time 6.62 seconds
Started Mar 17 02:43:42 PM PDT 24
Finished Mar 17 02:43:49 PM PDT 24
Peak memory 208276 kb
Host smart-b33a35f0-2fa1-4eda-a128-4cbb50a826dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078045999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.3078045999
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.2628868039
Short name T264
Test name
Test status
Simulation time 2896758809 ps
CPU time 70.06 seconds
Started Mar 17 02:43:43 PM PDT 24
Finished Mar 17 02:44:54 PM PDT 24
Peak memory 221908 kb
Host smart-542dae42-1d24-455a-9251-ac76d26ae4eb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628868039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.2628868039
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.2671317252
Short name T773
Test name
Test status
Simulation time 1105010637 ps
CPU time 12.19 seconds
Started Mar 17 02:43:45 PM PDT 24
Finished Mar 17 02:43:58 PM PDT 24
Peak memory 214676 kb
Host smart-2a2a1ebd-9697-4acb-8c66-5dc232cfeb7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671317252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.2671317252
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.1386709338
Short name T651
Test name
Test status
Simulation time 76606010 ps
CPU time 1.58 seconds
Started Mar 17 02:43:43 PM PDT 24
Finished Mar 17 02:43:45 PM PDT 24
Peak memory 210148 kb
Host smart-282951ef-fcb6-4154-9e06-91e00adfcc5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1386709338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.1386709338
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.3564147330
Short name T568
Test name
Test status
Simulation time 14960077 ps
CPU time 0.74 seconds
Started Mar 17 02:42:33 PM PDT 24
Finished Mar 17 02:42:34 PM PDT 24
Peak memory 206452 kb
Host smart-5e48e735-74fd-42b1-8d7f-fdca468354e8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564147330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.3564147330
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.3658846985
Short name T418
Test name
Test status
Simulation time 57475048 ps
CPU time 4.13 seconds
Started Mar 17 02:42:34 PM PDT 24
Finished Mar 17 02:42:39 PM PDT 24
Peak memory 214776 kb
Host smart-2702f3d6-42b7-47ee-a8ea-9ea2016505b3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3658846985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.3658846985
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.2432814902
Short name T485
Test name
Test status
Simulation time 318985485 ps
CPU time 2.72 seconds
Started Mar 17 02:42:33 PM PDT 24
Finished Mar 17 02:42:36 PM PDT 24
Peak memory 218760 kb
Host smart-d9d6bf85-44dd-4ba5-b321-d7495ed9f9f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432814902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.2432814902
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.2250649633
Short name T631
Test name
Test status
Simulation time 90365015 ps
CPU time 4.04 seconds
Started Mar 17 02:42:33 PM PDT 24
Finished Mar 17 02:42:37 PM PDT 24
Peak memory 208088 kb
Host smart-4550a578-da24-4feb-b99c-7ce3a79bc756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250649633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.2250649633
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.3571206323
Short name T278
Test name
Test status
Simulation time 512384623 ps
CPU time 4.67 seconds
Started Mar 17 02:42:34 PM PDT 24
Finished Mar 17 02:42:39 PM PDT 24
Peak memory 214804 kb
Host smart-bbe77523-2e26-4492-bbd8-aad176a978c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3571206323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.3571206323
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.2933305038
Short name T8
Test name
Test status
Simulation time 606454995 ps
CPU time 9.62 seconds
Started Mar 17 02:42:33 PM PDT 24
Finished Mar 17 02:42:43 PM PDT 24
Peak memory 220736 kb
Host smart-81218dbc-aa53-4d2b-ab66-bb61026f893b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933305038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.2933305038
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_sideload.2636014572
Short name T865
Test name
Test status
Simulation time 239620012 ps
CPU time 5.55 seconds
Started Mar 17 02:42:35 PM PDT 24
Finished Mar 17 02:42:41 PM PDT 24
Peak memory 208992 kb
Host smart-f68fa89a-f6da-4f89-a37e-44c94c069823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636014572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.2636014572
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.1531043653
Short name T316
Test name
Test status
Simulation time 686853564 ps
CPU time 9.66 seconds
Started Mar 17 02:42:35 PM PDT 24
Finished Mar 17 02:42:45 PM PDT 24
Peak memory 208980 kb
Host smart-a6a43bab-d2b7-41d6-8fb0-09933560d838
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1531043653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.1531043653
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.2764319091
Short name T276
Test name
Test status
Simulation time 129759590 ps
CPU time 4.71 seconds
Started Mar 17 02:42:32 PM PDT 24
Finished Mar 17 02:42:37 PM PDT 24
Peak memory 209248 kb
Host smart-75c52294-ce4f-4a33-a0b5-e637f0063cdd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2764319091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.2764319091
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.1359737140
Short name T783
Test name
Test status
Simulation time 1948687376 ps
CPU time 25.14 seconds
Started Mar 17 02:42:33 PM PDT 24
Finished Mar 17 02:42:58 PM PDT 24
Peak memory 208868 kb
Host smart-0f19fa2d-4dd3-41d9-9d36-97092082887b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1359737140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.1359737140
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.4021156199
Short name T277
Test name
Test status
Simulation time 1544359737 ps
CPU time 3.58 seconds
Started Mar 17 02:42:34 PM PDT 24
Finished Mar 17 02:42:37 PM PDT 24
Peak memory 209992 kb
Host smart-57e77513-3c80-4dae-ac08-0998f4da8b05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021156199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.4021156199
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.1696838112
Short name T475
Test name
Test status
Simulation time 57179000 ps
CPU time 2.89 seconds
Started Mar 17 02:42:36 PM PDT 24
Finished Mar 17 02:42:39 PM PDT 24
Peak memory 209028 kb
Host smart-cd169817-55dd-48de-9f1a-59515bc285f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1696838112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.1696838112
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.2712837159
Short name T280
Test name
Test status
Simulation time 1243026032 ps
CPU time 25.62 seconds
Started Mar 17 02:42:33 PM PDT 24
Finished Mar 17 02:42:59 PM PDT 24
Peak memory 221536 kb
Host smart-b27607cb-3d63-4fb1-bfea-00a4927814b8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2712837159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.2712837159
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.993971513
Short name T897
Test name
Test status
Simulation time 163343323 ps
CPU time 5.2 seconds
Started Mar 17 02:42:33 PM PDT 24
Finished Mar 17 02:42:38 PM PDT 24
Peak memory 214820 kb
Host smart-5505d2d9-7a45-4209-8d46-609d9942f996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=993971513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.993971513
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.890274868
Short name T637
Test name
Test status
Simulation time 65746927 ps
CPU time 2.28 seconds
Started Mar 17 02:42:33 PM PDT 24
Finished Mar 17 02:42:36 PM PDT 24
Peak memory 209960 kb
Host smart-f4171892-0f8a-48c8-8652-0378d866a4a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890274868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.890274868
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.608080106
Short name T127
Test name
Test status
Simulation time 110222014 ps
CPU time 0.82 seconds
Started Mar 17 02:43:48 PM PDT 24
Finished Mar 17 02:43:50 PM PDT 24
Peak memory 206376 kb
Host smart-06a39c68-16ae-487a-9270-7eab204c0fcd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=608080106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.608080106
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.1958129496
Short name T298
Test name
Test status
Simulation time 303508930 ps
CPU time 2.95 seconds
Started Mar 17 02:43:49 PM PDT 24
Finished Mar 17 02:43:52 PM PDT 24
Peak memory 215436 kb
Host smart-762af383-996d-494f-9854-f56ba1c53797
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1958129496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.1958129496
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.2417894361
Short name T879
Test name
Test status
Simulation time 75900819 ps
CPU time 4.29 seconds
Started Mar 17 02:43:48 PM PDT 24
Finished Mar 17 02:43:53 PM PDT 24
Peak memory 211016 kb
Host smart-b4e4e678-9cb9-415c-9d1f-2c494920e4f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2417894361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.2417894361
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.1877524118
Short name T625
Test name
Test status
Simulation time 104761204 ps
CPU time 1.83 seconds
Started Mar 17 02:43:49 PM PDT 24
Finished Mar 17 02:43:52 PM PDT 24
Peak memory 209680 kb
Host smart-567336e8-3146-40cd-ac3e-5bcc33b26cf0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877524118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.1877524118
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.2034548613
Short name T372
Test name
Test status
Simulation time 406300265 ps
CPU time 8.6 seconds
Started Mar 17 02:43:47 PM PDT 24
Finished Mar 17 02:43:56 PM PDT 24
Peak memory 214776 kb
Host smart-e4c69c71-c980-4ecf-8576-b7b0bf4cae4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034548613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.2034548613
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.713010558
Short name T39
Test name
Test status
Simulation time 80867039 ps
CPU time 4.62 seconds
Started Mar 17 02:43:49 PM PDT 24
Finished Mar 17 02:43:54 PM PDT 24
Peak memory 214628 kb
Host smart-2518e20d-c0bc-4452-8cd8-ad25e0082209
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713010558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.713010558
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.2319002924
Short name T61
Test name
Test status
Simulation time 92241707 ps
CPU time 4.11 seconds
Started Mar 17 02:43:47 PM PDT 24
Finished Mar 17 02:43:51 PM PDT 24
Peak memory 219292 kb
Host smart-156eb7a5-e885-4d51-b6cf-cc76c5cf4eb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319002924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.2319002924
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.299371326
Short name T884
Test name
Test status
Simulation time 411387334 ps
CPU time 8.43 seconds
Started Mar 17 02:43:48 PM PDT 24
Finished Mar 17 02:43:57 PM PDT 24
Peak memory 209660 kb
Host smart-1b01f2e6-b63a-4cd4-819b-ba3b1d08a8b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299371326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.299371326
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.1170353489
Short name T775
Test name
Test status
Simulation time 2086748005 ps
CPU time 30.18 seconds
Started Mar 17 02:43:48 PM PDT 24
Finished Mar 17 02:44:19 PM PDT 24
Peak memory 208992 kb
Host smart-490234e5-4e31-4530-b8d0-2a4d60052a25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1170353489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.1170353489
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.3265490068
Short name T737
Test name
Test status
Simulation time 396860479 ps
CPU time 13.03 seconds
Started Mar 17 02:43:48 PM PDT 24
Finished Mar 17 02:44:02 PM PDT 24
Peak memory 208552 kb
Host smart-a781c448-e8fe-4f51-92de-bbd2437f602e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265490068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.3265490068
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.2928604229
Short name T17
Test name
Test status
Simulation time 658953744 ps
CPU time 5.01 seconds
Started Mar 17 02:43:51 PM PDT 24
Finished Mar 17 02:43:56 PM PDT 24
Peak memory 208440 kb
Host smart-fb3d57cc-cea3-49a8-9292-79e6b44e6a1d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928604229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.2928604229
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.4266923582
Short name T133
Test name
Test status
Simulation time 204496978 ps
CPU time 3.65 seconds
Started Mar 17 02:43:47 PM PDT 24
Finished Mar 17 02:43:51 PM PDT 24
Peak memory 218904 kb
Host smart-4bb50d91-d84d-49be-8c85-caba6e4a309d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266923582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.4266923582
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.3214946857
Short name T667
Test name
Test status
Simulation time 424135050 ps
CPU time 3.76 seconds
Started Mar 17 02:43:46 PM PDT 24
Finished Mar 17 02:43:51 PM PDT 24
Peak memory 207060 kb
Host smart-46e5379f-8ffd-4c9d-b1d1-83e939aa55dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214946857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.3214946857
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.446484069
Short name T75
Test name
Test status
Simulation time 5955933930 ps
CPU time 40.17 seconds
Started Mar 17 02:43:48 PM PDT 24
Finished Mar 17 02:44:29 PM PDT 24
Peak memory 217068 kb
Host smart-95e8b67b-ce26-469c-8570-a8dd31424470
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=446484069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.446484069
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_stress_all_with_rand_reset.4072991658
Short name T831
Test name
Test status
Simulation time 570585820 ps
CPU time 11.88 seconds
Started Mar 17 02:43:48 PM PDT 24
Finished Mar 17 02:44:01 PM PDT 24
Peak memory 223088 kb
Host smart-ac19d0b6-3021-432f-a9d4-c1cc07a8ab13
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072991658 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all_with_rand_reset.4072991658
Directory /workspace/20.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.1389024666
Short name T891
Test name
Test status
Simulation time 194779401 ps
CPU time 3.07 seconds
Started Mar 17 02:43:48 PM PDT 24
Finished Mar 17 02:43:52 PM PDT 24
Peak memory 210744 kb
Host smart-e87c478c-ea20-4687-bcbe-a5f1811d4a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389024666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.1389024666
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.2846267755
Short name T702
Test name
Test status
Simulation time 9292294 ps
CPU time 0.75 seconds
Started Mar 17 02:43:56 PM PDT 24
Finished Mar 17 02:43:57 PM PDT 24
Peak memory 206464 kb
Host smart-5e23fab6-a670-46eb-a8b9-c0104015ed14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846267755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.2846267755
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.1344656322
Short name T64
Test name
Test status
Simulation time 232243879 ps
CPU time 5.38 seconds
Started Mar 17 02:43:55 PM PDT 24
Finished Mar 17 02:44:00 PM PDT 24
Peak memory 209632 kb
Host smart-3f8d86cf-d4e5-466a-b55e-3641680eccd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344656322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.1344656322
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.2633382557
Short name T181
Test name
Test status
Simulation time 218279619 ps
CPU time 3.05 seconds
Started Mar 17 02:43:52 PM PDT 24
Finished Mar 17 02:43:55 PM PDT 24
Peak memory 214864 kb
Host smart-ba8221af-772f-4c15-9805-aad1474c149c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633382557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.2633382557
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.3003917292
Short name T308
Test name
Test status
Simulation time 2132418680 ps
CPU time 17.7 seconds
Started Mar 17 02:43:54 PM PDT 24
Finished Mar 17 02:44:11 PM PDT 24
Peak memory 219564 kb
Host smart-603ea875-addc-4fc0-bfd5-b91d6373b968
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3003917292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.3003917292
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.2160564288
Short name T348
Test name
Test status
Simulation time 148952301 ps
CPU time 3.26 seconds
Started Mar 17 02:43:53 PM PDT 24
Finished Mar 17 02:43:56 PM PDT 24
Peak memory 209028 kb
Host smart-14901894-b40c-481f-bae1-14893e4b9a84
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160564288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.2160564288
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.201147688
Short name T673
Test name
Test status
Simulation time 696384230 ps
CPU time 3.79 seconds
Started Mar 17 02:43:55 PM PDT 24
Finished Mar 17 02:43:59 PM PDT 24
Peak memory 214900 kb
Host smart-7dd1e5a4-4a53-4918-9536-8f554e27ee9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=201147688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.201147688
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.3667022379
Short name T196
Test name
Test status
Simulation time 597906194 ps
CPU time 6.19 seconds
Started Mar 17 02:43:54 PM PDT 24
Finished Mar 17 02:44:00 PM PDT 24
Peak memory 211012 kb
Host smart-0314b321-8065-41bf-89a5-18c1dc1026ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3667022379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.3667022379
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.3649454873
Short name T430
Test name
Test status
Simulation time 659949657 ps
CPU time 3.2 seconds
Started Mar 17 02:43:46 PM PDT 24
Finished Mar 17 02:43:50 PM PDT 24
Peak memory 207064 kb
Host smart-4676a2e8-ff7a-4e03-af23-c2648aaf641a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649454873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.3649454873
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.3489985428
Short name T506
Test name
Test status
Simulation time 50270258 ps
CPU time 2.89 seconds
Started Mar 17 02:43:53 PM PDT 24
Finished Mar 17 02:43:56 PM PDT 24
Peak memory 208636 kb
Host smart-91da569d-fea5-4641-b156-b0841030f737
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3489985428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.3489985428
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.3284606236
Short name T324
Test name
Test status
Simulation time 545645010 ps
CPU time 6.86 seconds
Started Mar 17 02:43:47 PM PDT 24
Finished Mar 17 02:43:54 PM PDT 24
Peak memory 208992 kb
Host smart-332e6206-bf8c-479c-838a-b8dafd8738a8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3284606236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.3284606236
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.348314122
Short name T902
Test name
Test status
Simulation time 47385649 ps
CPU time 2.58 seconds
Started Mar 17 02:43:55 PM PDT 24
Finished Mar 17 02:43:58 PM PDT 24
Peak memory 207336 kb
Host smart-552d07f8-1440-4007-8bee-00f53b1ac126
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=348314122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.348314122
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.3984687855
Short name T463
Test name
Test status
Simulation time 284829874 ps
CPU time 3.37 seconds
Started Mar 17 02:43:53 PM PDT 24
Finished Mar 17 02:43:56 PM PDT 24
Peak memory 216156 kb
Host smart-5f6b3828-4cb8-42f4-b01c-d50e6d9d4a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3984687855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.3984687855
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.1692354716
Short name T197
Test name
Test status
Simulation time 88665540 ps
CPU time 2.88 seconds
Started Mar 17 02:43:47 PM PDT 24
Finished Mar 17 02:43:50 PM PDT 24
Peak memory 208988 kb
Host smart-e7f0378c-9171-4ef5-87d0-c7e59fb754e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692354716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.1692354716
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.2974699448
Short name T243
Test name
Test status
Simulation time 428768500 ps
CPU time 11.46 seconds
Started Mar 17 02:43:57 PM PDT 24
Finished Mar 17 02:44:08 PM PDT 24
Peak memory 210032 kb
Host smart-629624a5-ab55-420a-8538-73e706330405
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2974699448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.2974699448
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.2363748218
Short name T125
Test name
Test status
Simulation time 71818883 ps
CPU time 2.95 seconds
Started Mar 17 02:43:52 PM PDT 24
Finished Mar 17 02:43:55 PM PDT 24
Peak memory 207784 kb
Host smart-2cc4a636-f7bf-4f59-95e4-a3221b102dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2363748218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.2363748218
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.1962812749
Short name T733
Test name
Test status
Simulation time 44471844 ps
CPU time 1.52 seconds
Started Mar 17 02:43:52 PM PDT 24
Finished Mar 17 02:43:54 PM PDT 24
Peak memory 209968 kb
Host smart-f9a8869e-7af4-462f-a48e-ea9047c28166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1962812749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.1962812749
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.4005479034
Short name T648
Test name
Test status
Simulation time 23107476 ps
CPU time 0.74 seconds
Started Mar 17 02:44:00 PM PDT 24
Finished Mar 17 02:44:01 PM PDT 24
Peak memory 206692 kb
Host smart-e170a07c-926f-4889-84e2-3aef114e5243
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4005479034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.4005479034
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.3996470527
Short name T744
Test name
Test status
Simulation time 86385829 ps
CPU time 3.9 seconds
Started Mar 17 02:44:00 PM PDT 24
Finished Mar 17 02:44:04 PM PDT 24
Peak memory 209276 kb
Host smart-8af00335-93ac-432c-bc2c-f339b9d75ac9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996470527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.3996470527
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.1392248044
Short name T48
Test name
Test status
Simulation time 97762580 ps
CPU time 2.6 seconds
Started Mar 17 02:43:56 PM PDT 24
Finished Mar 17 02:43:59 PM PDT 24
Peak memory 207952 kb
Host smart-81039456-6e42-4b35-b8e2-6bf74e31c5e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1392248044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.1392248044
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.912721594
Short name T555
Test name
Test status
Simulation time 606570029 ps
CPU time 3.98 seconds
Started Mar 17 02:44:04 PM PDT 24
Finished Mar 17 02:44:08 PM PDT 24
Peak memory 209572 kb
Host smart-22ef2c38-166b-4e39-9dfb-ae9c330d2d8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912721594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.912721594
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.191512343
Short name T701
Test name
Test status
Simulation time 1045430110 ps
CPU time 8.4 seconds
Started Mar 17 02:43:53 PM PDT 24
Finished Mar 17 02:44:02 PM PDT 24
Peak memory 208060 kb
Host smart-ae99abcd-2114-434e-bc8f-933f6d39d0bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191512343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.191512343
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.1728732145
Short name T335
Test name
Test status
Simulation time 836073803 ps
CPU time 9.57 seconds
Started Mar 17 02:43:54 PM PDT 24
Finished Mar 17 02:44:04 PM PDT 24
Peak memory 208928 kb
Host smart-6be1fbf3-badf-4af2-8ccb-23f416de2e85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728732145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.1728732145
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.1387861934
Short name T397
Test name
Test status
Simulation time 167049845 ps
CPU time 2.38 seconds
Started Mar 17 02:43:54 PM PDT 24
Finished Mar 17 02:43:57 PM PDT 24
Peak memory 207280 kb
Host smart-03cfae8c-ee37-41ee-9b67-23dfe8de59c2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387861934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.1387861934
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.3366866025
Short name T431
Test name
Test status
Simulation time 42951924 ps
CPU time 1.82 seconds
Started Mar 17 02:43:53 PM PDT 24
Finished Mar 17 02:43:55 PM PDT 24
Peak memory 207156 kb
Host smart-31626f8d-3c4d-4b3e-9df9-fe606baf5cec
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3366866025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.3366866025
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.1190069669
Short name T3
Test name
Test status
Simulation time 79768648 ps
CPU time 1.92 seconds
Started Mar 17 02:43:55 PM PDT 24
Finished Mar 17 02:43:57 PM PDT 24
Peak memory 207304 kb
Host smart-a4accd6f-cc3a-436c-b284-36f60b36cb9d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1190069669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.1190069669
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.1623218596
Short name T541
Test name
Test status
Simulation time 220543739 ps
CPU time 3.76 seconds
Started Mar 17 02:43:58 PM PDT 24
Finished Mar 17 02:44:02 PM PDT 24
Peak memory 210804 kb
Host smart-e6801177-3da5-4986-88b3-3663ea14e33a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1623218596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.1623218596
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.4177685802
Short name T649
Test name
Test status
Simulation time 20901707 ps
CPU time 1.8 seconds
Started Mar 17 02:43:52 PM PDT 24
Finished Mar 17 02:43:54 PM PDT 24
Peak memory 207244 kb
Host smart-b14a746d-71ed-42e7-9541-0f0512e64e4d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4177685802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.4177685802
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.1530581889
Short name T259
Test name
Test status
Simulation time 333981590 ps
CPU time 7.57 seconds
Started Mar 17 02:43:59 PM PDT 24
Finished Mar 17 02:44:07 PM PDT 24
Peak memory 215712 kb
Host smart-e4a731f2-19ac-40fd-9159-126e96689cf3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530581889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.1530581889
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.3591537526
Short name T414
Test name
Test status
Simulation time 175466738 ps
CPU time 3.13 seconds
Started Mar 17 02:44:04 PM PDT 24
Finished Mar 17 02:44:08 PM PDT 24
Peak memory 207980 kb
Host smart-245e341c-f549-4e22-8cdc-2031cd800858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591537526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.3591537526
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.2514906794
Short name T182
Test name
Test status
Simulation time 126223591 ps
CPU time 2.88 seconds
Started Mar 17 02:44:00 PM PDT 24
Finished Mar 17 02:44:03 PM PDT 24
Peak memory 210424 kb
Host smart-99fc3838-4a12-4b48-a305-70f20b8d4083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2514906794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.2514906794
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.1434952009
Short name T1
Test name
Test status
Simulation time 14662512 ps
CPU time 0.93 seconds
Started Mar 17 02:44:01 PM PDT 24
Finished Mar 17 02:44:02 PM PDT 24
Peak memory 206504 kb
Host smart-8e0f9650-2aaf-49b1-a90c-75505b3bbc9d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1434952009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.1434952009
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.2463283451
Short name T864
Test name
Test status
Simulation time 158681168 ps
CPU time 2.47 seconds
Started Mar 17 02:44:01 PM PDT 24
Finished Mar 17 02:44:03 PM PDT 24
Peak memory 210184 kb
Host smart-ab81e346-ec9e-4a6f-b8cf-3f6c37df74ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463283451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.2463283451
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.1432436307
Short name T23
Test name
Test status
Simulation time 641994967 ps
CPU time 8.81 seconds
Started Mar 17 02:44:01 PM PDT 24
Finished Mar 17 02:44:10 PM PDT 24
Peak memory 209516 kb
Host smart-310360c8-5f87-4113-9e07-9d7e0394e0cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432436307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.1432436307
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.3990313305
Short name T291
Test name
Test status
Simulation time 625110852 ps
CPU time 6.9 seconds
Started Mar 17 02:44:01 PM PDT 24
Finished Mar 17 02:44:08 PM PDT 24
Peak memory 222904 kb
Host smart-c2781482-15ea-490b-918c-bb9e084ddde9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3990313305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.3990313305
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.2463126161
Short name T795
Test name
Test status
Simulation time 69379285 ps
CPU time 2.55 seconds
Started Mar 17 02:44:05 PM PDT 24
Finished Mar 17 02:44:08 PM PDT 24
Peak memory 216284 kb
Host smart-d1924f5d-1bf9-4123-b089-8b56c1a16c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463126161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.2463126161
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.3364204830
Short name T894
Test name
Test status
Simulation time 295617393 ps
CPU time 9.78 seconds
Started Mar 17 02:44:02 PM PDT 24
Finished Mar 17 02:44:12 PM PDT 24
Peak memory 207588 kb
Host smart-f580639d-65b8-48a7-9509-0c1bdcf5f49e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364204830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.3364204830
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.1489393010
Short name T863
Test name
Test status
Simulation time 39113762 ps
CPU time 2.02 seconds
Started Mar 17 02:44:00 PM PDT 24
Finished Mar 17 02:44:02 PM PDT 24
Peak memory 209004 kb
Host smart-86943882-5d5f-4750-ae82-a05800c6d1a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1489393010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.1489393010
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.2714946635
Short name T729
Test name
Test status
Simulation time 2004947440 ps
CPU time 9.49 seconds
Started Mar 17 02:44:02 PM PDT 24
Finished Mar 17 02:44:12 PM PDT 24
Peak memory 208504 kb
Host smart-5c1b93b2-aebf-4c1f-a338-5ed58c279975
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2714946635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.2714946635
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.575037738
Short name T330
Test name
Test status
Simulation time 78406883 ps
CPU time 2.54 seconds
Started Mar 17 02:43:57 PM PDT 24
Finished Mar 17 02:44:00 PM PDT 24
Peak memory 207932 kb
Host smart-57e04ac7-90e6-4c2a-a3fb-6a52f17cd1c3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=575037738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.575037738
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.377102044
Short name T606
Test name
Test status
Simulation time 192826855 ps
CPU time 2.76 seconds
Started Mar 17 02:43:59 PM PDT 24
Finished Mar 17 02:44:02 PM PDT 24
Peak memory 207952 kb
Host smart-dbe75fb3-e9b5-4e69-837b-f78b6192e90e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377102044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.377102044
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.91464992
Short name T533
Test name
Test status
Simulation time 176212790 ps
CPU time 2.8 seconds
Started Mar 17 02:44:00 PM PDT 24
Finished Mar 17 02:44:03 PM PDT 24
Peak memory 208820 kb
Host smart-cc021469-acd4-4acb-ba1b-d52edcf1400d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91464992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.91464992
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.1391128128
Short name T693
Test name
Test status
Simulation time 282700641 ps
CPU time 4.4 seconds
Started Mar 17 02:43:58 PM PDT 24
Finished Mar 17 02:44:02 PM PDT 24
Peak memory 209048 kb
Host smart-6d5f9fe0-e205-4e3d-a336-d9ed891c4b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1391128128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.1391128128
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.1596650880
Short name T363
Test name
Test status
Simulation time 30391384326 ps
CPU time 685.98 seconds
Started Mar 17 02:43:58 PM PDT 24
Finished Mar 17 02:55:25 PM PDT 24
Peak memory 223048 kb
Host smart-597e49f8-f448-4ef1-8fcc-36e654af5178
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1596650880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.1596650880
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_stress_all_with_rand_reset.2425015942
Short name T888
Test name
Test status
Simulation time 1086882727 ps
CPU time 19.26 seconds
Started Mar 17 02:44:00 PM PDT 24
Finished Mar 17 02:44:19 PM PDT 24
Peak memory 223192 kb
Host smart-55ebb519-0ec9-458a-8cd2-d9895e2e9f4a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425015942 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all_with_rand_reset.2425015942
Directory /workspace/23.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.1929890904
Short name T817
Test name
Test status
Simulation time 421739013 ps
CPU time 5.17 seconds
Started Mar 17 02:43:59 PM PDT 24
Finished Mar 17 02:44:04 PM PDT 24
Peak memory 209744 kb
Host smart-9dcb32cd-cbaa-428f-a167-dd45006fc43e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1929890904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.1929890904
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.3095779597
Short name T386
Test name
Test status
Simulation time 59085708 ps
CPU time 2.31 seconds
Started Mar 17 02:43:58 PM PDT 24
Finished Mar 17 02:44:01 PM PDT 24
Peak memory 210112 kb
Host smart-659a2fda-bbb8-46ae-ad77-c107856f2078
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3095779597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.3095779597
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.472263626
Short name T636
Test name
Test status
Simulation time 30418201 ps
CPU time 0.99 seconds
Started Mar 17 02:44:06 PM PDT 24
Finished Mar 17 02:44:07 PM PDT 24
Peak memory 206504 kb
Host smart-38f8ea98-7a7e-415b-9fcd-266912997e95
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472263626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.472263626
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.3160909061
Short name T377
Test name
Test status
Simulation time 119711588 ps
CPU time 4.74 seconds
Started Mar 17 02:43:58 PM PDT 24
Finished Mar 17 02:44:03 PM PDT 24
Peak memory 214796 kb
Host smart-51e3846e-07a4-4b49-bdd9-c16777bb2ac5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3160909061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.3160909061
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.145475620
Short name T677
Test name
Test status
Simulation time 453015797 ps
CPU time 3.98 seconds
Started Mar 17 02:44:06 PM PDT 24
Finished Mar 17 02:44:10 PM PDT 24
Peak memory 209996 kb
Host smart-366d4cc0-4cf5-41ef-bec6-ae9d05cd571e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=145475620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.145475620
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.2135815789
Short name T326
Test name
Test status
Simulation time 70576231 ps
CPU time 2.96 seconds
Started Mar 17 02:44:04 PM PDT 24
Finished Mar 17 02:44:08 PM PDT 24
Peak memory 218648 kb
Host smart-297dca23-7ca7-407b-8dea-76a160af1804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135815789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.2135815789
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.2791399266
Short name T380
Test name
Test status
Simulation time 462627511 ps
CPU time 9.09 seconds
Started Mar 17 02:44:06 PM PDT 24
Finished Mar 17 02:44:16 PM PDT 24
Peak memory 209096 kb
Host smart-5c706dcf-e5e0-4483-a668-90fd603b0555
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2791399266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.2791399266
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.4089290872
Short name T268
Test name
Test status
Simulation time 236635955 ps
CPU time 6.21 seconds
Started Mar 17 02:44:06 PM PDT 24
Finished Mar 17 02:44:12 PM PDT 24
Peak memory 222928 kb
Host smart-42aebb2b-baf9-4b13-89b0-39fa17db254f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089290872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.4089290872
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.841782585
Short name T138
Test name
Test status
Simulation time 45678758 ps
CPU time 3.11 seconds
Started Mar 17 02:44:04 PM PDT 24
Finished Mar 17 02:44:07 PM PDT 24
Peak memory 211008 kb
Host smart-553daa34-2ba0-451f-b8ea-54ebd029979c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841782585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.841782585
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.2520860658
Short name T275
Test name
Test status
Simulation time 337017402 ps
CPU time 9.83 seconds
Started Mar 17 02:43:58 PM PDT 24
Finished Mar 17 02:44:08 PM PDT 24
Peak memory 214828 kb
Host smart-1097d2ce-6d8f-42f6-b110-9aaf4e91499e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2520860658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.2520860658
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.4164658127
Short name T646
Test name
Test status
Simulation time 210290337 ps
CPU time 5.67 seconds
Started Mar 17 02:43:58 PM PDT 24
Finished Mar 17 02:44:04 PM PDT 24
Peak memory 207092 kb
Host smart-e384eec8-1f13-4230-80e3-7aa5962373d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4164658127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.4164658127
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.718218808
Short name T584
Test name
Test status
Simulation time 187830704 ps
CPU time 3.03 seconds
Started Mar 17 02:43:59 PM PDT 24
Finished Mar 17 02:44:02 PM PDT 24
Peak memory 207160 kb
Host smart-0490a249-b0d9-45d2-9d82-42c06f76ccbc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=718218808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.718218808
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.2677333137
Short name T542
Test name
Test status
Simulation time 798439913 ps
CPU time 7.17 seconds
Started Mar 17 02:43:59 PM PDT 24
Finished Mar 17 02:44:06 PM PDT 24
Peak memory 208272 kb
Host smart-3946e6e6-65b3-4ad7-a6c6-3ff9f0585d76
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677333137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.2677333137
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.3054668015
Short name T560
Test name
Test status
Simulation time 146238576 ps
CPU time 2.79 seconds
Started Mar 17 02:44:02 PM PDT 24
Finished Mar 17 02:44:05 PM PDT 24
Peak memory 209260 kb
Host smart-ce4c4a6f-f46f-4774-b880-db866de36e72
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3054668015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.3054668015
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.1738340000
Short name T403
Test name
Test status
Simulation time 195639647 ps
CPU time 2.21 seconds
Started Mar 17 02:44:05 PM PDT 24
Finished Mar 17 02:44:07 PM PDT 24
Peak memory 214788 kb
Host smart-2c09cff2-eab6-4e85-b820-b0b177e70e19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1738340000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.1738340000
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.3582747459
Short name T814
Test name
Test status
Simulation time 716591071 ps
CPU time 21.69 seconds
Started Mar 17 02:44:02 PM PDT 24
Finished Mar 17 02:44:24 PM PDT 24
Peak memory 209216 kb
Host smart-957cc3e6-11f0-4347-b4fd-e7b91e8051e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582747459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.3582747459
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.4008866222
Short name T306
Test name
Test status
Simulation time 169822202 ps
CPU time 5.73 seconds
Started Mar 17 02:44:02 PM PDT 24
Finished Mar 17 02:44:08 PM PDT 24
Peak memory 214804 kb
Host smart-64fa450c-62dc-4d5c-8034-8a68d4e7a7d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008866222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.4008866222
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.3508109866
Short name T821
Test name
Test status
Simulation time 1840880402 ps
CPU time 9.86 seconds
Started Mar 17 02:44:08 PM PDT 24
Finished Mar 17 02:44:18 PM PDT 24
Peak memory 211284 kb
Host smart-6440ec7d-4783-405f-af44-dc49f15bcffa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508109866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.3508109866
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.4187926285
Short name T425
Test name
Test status
Simulation time 58877388 ps
CPU time 0.98 seconds
Started Mar 17 02:44:06 PM PDT 24
Finished Mar 17 02:44:07 PM PDT 24
Peak memory 206520 kb
Host smart-6187d8df-31ef-4b36-97a8-381123379241
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4187926285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.4187926285
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.3776265410
Short name T420
Test name
Test status
Simulation time 548496639 ps
CPU time 7.83 seconds
Started Mar 17 02:44:04 PM PDT 24
Finished Mar 17 02:44:12 PM PDT 24
Peak memory 214784 kb
Host smart-b095837b-8091-4a99-a8ab-10539a09a188
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3776265410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.3776265410
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.2084728306
Short name T460
Test name
Test status
Simulation time 397452654 ps
CPU time 2.02 seconds
Started Mar 17 02:44:05 PM PDT 24
Finished Mar 17 02:44:07 PM PDT 24
Peak memory 209280 kb
Host smart-39cc7ebf-d343-4c3f-a355-cd848f0e6f68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2084728306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.2084728306
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.964013962
Short name T24
Test name
Test status
Simulation time 86235176 ps
CPU time 3.14 seconds
Started Mar 17 02:44:06 PM PDT 24
Finished Mar 17 02:44:09 PM PDT 24
Peak memory 209416 kb
Host smart-410c76ef-0743-4d66-a02c-59052aefa8f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964013962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.964013962
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.920097376
Short name T367
Test name
Test status
Simulation time 842701405 ps
CPU time 25.35 seconds
Started Mar 17 02:44:08 PM PDT 24
Finished Mar 17 02:44:33 PM PDT 24
Peak memory 211792 kb
Host smart-4393cea3-e4e2-4faf-bacc-236e0ceb9cf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=920097376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.920097376
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.418128752
Short name T56
Test name
Test status
Simulation time 78807871 ps
CPU time 3.26 seconds
Started Mar 17 02:44:08 PM PDT 24
Finished Mar 17 02:44:12 PM PDT 24
Peak memory 222956 kb
Host smart-83881a3f-6964-4ec6-9cb2-ad3b18f297d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=418128752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.418128752
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_sideload.2012767155
Short name T81
Test name
Test status
Simulation time 2258856875 ps
CPU time 29.28 seconds
Started Mar 17 02:44:03 PM PDT 24
Finished Mar 17 02:44:33 PM PDT 24
Peak memory 208996 kb
Host smart-38f24f77-9b03-4ec0-9d8f-6d074014e721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012767155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.2012767155
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.3072592494
Short name T509
Test name
Test status
Simulation time 561802392 ps
CPU time 7.19 seconds
Started Mar 17 02:44:06 PM PDT 24
Finished Mar 17 02:44:14 PM PDT 24
Peak memory 208304 kb
Host smart-ddd67973-d6cf-4fb7-b910-79a39757cb81
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3072592494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.3072592494
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.2890208737
Short name T626
Test name
Test status
Simulation time 818054527 ps
CPU time 9.92 seconds
Started Mar 17 02:44:06 PM PDT 24
Finished Mar 17 02:44:16 PM PDT 24
Peak memory 208788 kb
Host smart-040a9d24-b4aa-4552-ae10-25ef180bdbb3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890208737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.2890208737
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.673218353
Short name T695
Test name
Test status
Simulation time 2974643715 ps
CPU time 31.67 seconds
Started Mar 17 02:44:05 PM PDT 24
Finished Mar 17 02:44:37 PM PDT 24
Peak memory 208748 kb
Host smart-b8a1e6c0-b83c-4687-868a-3b6c403b2589
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673218353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.673218353
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.485347287
Short name T900
Test name
Test status
Simulation time 1467368431 ps
CPU time 10.43 seconds
Started Mar 17 02:44:07 PM PDT 24
Finished Mar 17 02:44:17 PM PDT 24
Peak memory 209948 kb
Host smart-0e991d6e-11d3-4d8e-a27f-933ae36ee324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=485347287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.485347287
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.3221356347
Short name T402
Test name
Test status
Simulation time 54986211 ps
CPU time 2.59 seconds
Started Mar 17 02:44:03 PM PDT 24
Finished Mar 17 02:44:06 PM PDT 24
Peak memory 207160 kb
Host smart-7b74de6b-7530-495f-a9d0-2f50a4bf33a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221356347 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.3221356347
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.2978051690
Short name T532
Test name
Test status
Simulation time 116756697 ps
CPU time 6.04 seconds
Started Mar 17 02:44:06 PM PDT 24
Finished Mar 17 02:44:12 PM PDT 24
Peak memory 214712 kb
Host smart-283e1d96-2043-4306-9a57-2e914b11a956
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2978051690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.2978051690
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.2431569299
Short name T261
Test name
Test status
Simulation time 2636211216 ps
CPU time 28.71 seconds
Started Mar 17 02:44:05 PM PDT 24
Finished Mar 17 02:44:34 PM PDT 24
Peak memory 220256 kb
Host smart-4a790ba4-6327-4ac8-80ed-f471063a902f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2431569299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.2431569299
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.2598785744
Short name T193
Test name
Test status
Simulation time 113915335 ps
CPU time 2.57 seconds
Started Mar 17 02:44:05 PM PDT 24
Finished Mar 17 02:44:08 PM PDT 24
Peak memory 210500 kb
Host smart-bf910c0a-1b58-4a61-af48-3f89b90d441a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598785744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.2598785744
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.1167849725
Short name T486
Test name
Test status
Simulation time 50861821 ps
CPU time 0.96 seconds
Started Mar 17 02:44:10 PM PDT 24
Finished Mar 17 02:44:11 PM PDT 24
Peak memory 206544 kb
Host smart-3fa2065c-2622-4cf0-9c8d-f1dab59e065f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1167849725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.1167849725
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.4004551149
Short name T412
Test name
Test status
Simulation time 59271548 ps
CPU time 3.62 seconds
Started Mar 17 02:44:10 PM PDT 24
Finished Mar 17 02:44:14 PM PDT 24
Peak memory 214828 kb
Host smart-2d0602b2-d2c4-4934-9d47-29555a5910f9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4004551149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.4004551149
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.4148464752
Short name T37
Test name
Test status
Simulation time 216411802 ps
CPU time 3.41 seconds
Started Mar 17 02:44:10 PM PDT 24
Finished Mar 17 02:44:14 PM PDT 24
Peak memory 219200 kb
Host smart-4067f429-65cf-4e82-be56-8f79d36fa2f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148464752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.4148464752
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.2247649760
Short name T588
Test name
Test status
Simulation time 96298562 ps
CPU time 2.58 seconds
Started Mar 17 02:44:10 PM PDT 24
Finished Mar 17 02:44:13 PM PDT 24
Peak memory 210928 kb
Host smart-9bfd18b6-9209-4351-90da-a603484b5ff4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247649760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.2247649760
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.403169729
Short name T401
Test name
Test status
Simulation time 62552202 ps
CPU time 3.61 seconds
Started Mar 17 02:44:11 PM PDT 24
Finished Mar 17 02:44:14 PM PDT 24
Peak memory 209288 kb
Host smart-625c1811-b3e6-4b21-b705-10117b41bb53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=403169729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.403169729
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.2817727178
Short name T262
Test name
Test status
Simulation time 1798542528 ps
CPU time 23.43 seconds
Started Mar 17 02:44:08 PM PDT 24
Finished Mar 17 02:44:31 PM PDT 24
Peak memory 210880 kb
Host smart-8288c1e9-ceca-4f3e-b850-93b1396d1c20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817727178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.2817727178
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.2144629710
Short name T559
Test name
Test status
Simulation time 302950965 ps
CPU time 4.02 seconds
Started Mar 17 02:44:05 PM PDT 24
Finished Mar 17 02:44:09 PM PDT 24
Peak memory 207240 kb
Host smart-36d98302-3f92-4e8a-80af-84b5da7fbba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144629710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.2144629710
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.2378778908
Short name T828
Test name
Test status
Simulation time 645655847 ps
CPU time 6.71 seconds
Started Mar 17 02:44:11 PM PDT 24
Finished Mar 17 02:44:18 PM PDT 24
Peak memory 209064 kb
Host smart-ef0609eb-9649-4458-a3c3-6657fcbd1250
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2378778908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.2378778908
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.3596648889
Short name T512
Test name
Test status
Simulation time 170277841 ps
CPU time 5.22 seconds
Started Mar 17 02:44:11 PM PDT 24
Finished Mar 17 02:44:16 PM PDT 24
Peak memory 208764 kb
Host smart-64bd78e4-f4ca-44f6-b70f-259f4e37489e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596648889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.3596648889
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.3142413934
Short name T761
Test name
Test status
Simulation time 898147049 ps
CPU time 23.44 seconds
Started Mar 17 02:44:08 PM PDT 24
Finished Mar 17 02:44:32 PM PDT 24
Peak memory 208328 kb
Host smart-f59c00a1-b9e8-46ec-9e3c-a6b4d67f0f40
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142413934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.3142413934
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.1620067721
Short name T361
Test name
Test status
Simulation time 64713051 ps
CPU time 2.1 seconds
Started Mar 17 02:44:12 PM PDT 24
Finished Mar 17 02:44:14 PM PDT 24
Peak memory 215952 kb
Host smart-8cb1b878-19cd-4f94-a9ed-4dcf019cbfa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1620067721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.1620067721
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.1861698870
Short name T554
Test name
Test status
Simulation time 823277997 ps
CPU time 21.43 seconds
Started Mar 17 02:44:07 PM PDT 24
Finished Mar 17 02:44:29 PM PDT 24
Peak memory 209192 kb
Host smart-c71a9dce-ae3a-456b-971d-2b3394a0f8da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1861698870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.1861698870
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.2052423244
Short name T310
Test name
Test status
Simulation time 544021675 ps
CPU time 20.24 seconds
Started Mar 17 02:44:11 PM PDT 24
Finished Mar 17 02:44:32 PM PDT 24
Peak memory 216680 kb
Host smart-96e19ed0-8ecb-4690-ba2b-e173bde3f697
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2052423244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.2052423244
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.2527358003
Short name T869
Test name
Test status
Simulation time 93485861 ps
CPU time 4.49 seconds
Started Mar 17 02:44:10 PM PDT 24
Finished Mar 17 02:44:14 PM PDT 24
Peak memory 210156 kb
Host smart-efc2028d-c0a4-4cba-828d-852d66aaaf24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2527358003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.2527358003
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.767572014
Short name T859
Test name
Test status
Simulation time 63855117 ps
CPU time 0.84 seconds
Started Mar 17 02:44:17 PM PDT 24
Finished Mar 17 02:44:18 PM PDT 24
Peak memory 206288 kb
Host smart-e6ffb2bd-b461-48de-bf0c-431a2e51dea4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=767572014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.767572014
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.2338832623
Short name T668
Test name
Test status
Simulation time 217009608 ps
CPU time 2.82 seconds
Started Mar 17 02:44:19 PM PDT 24
Finished Mar 17 02:44:22 PM PDT 24
Peak memory 217296 kb
Host smart-ffe337d4-267c-4ea3-9473-f2adf48ce34a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2338832623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.2338832623
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.376200722
Short name T520
Test name
Test status
Simulation time 708293546 ps
CPU time 2.45 seconds
Started Mar 17 02:44:12 PM PDT 24
Finished Mar 17 02:44:14 PM PDT 24
Peak memory 218716 kb
Host smart-f8141419-06e1-49cc-ad33-4d702967cf2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376200722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.376200722
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.2912706956
Short name T563
Test name
Test status
Simulation time 164255124 ps
CPU time 4.55 seconds
Started Mar 17 02:44:10 PM PDT 24
Finished Mar 17 02:44:14 PM PDT 24
Peak memory 208996 kb
Host smart-376f9631-bfc8-4292-ae75-db5503397df5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912706956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.2912706956
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.1604998246
Short name T480
Test name
Test status
Simulation time 1199796568 ps
CPU time 10.4 seconds
Started Mar 17 02:44:11 PM PDT 24
Finished Mar 17 02:44:21 PM PDT 24
Peak memory 222928 kb
Host smart-d7238251-50a5-4418-a5d7-56d28d27b94d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604998246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.1604998246
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.3387041626
Short name T671
Test name
Test status
Simulation time 430172758 ps
CPU time 4.56 seconds
Started Mar 17 02:44:12 PM PDT 24
Finished Mar 17 02:44:16 PM PDT 24
Peak memory 220924 kb
Host smart-657cdb8a-84d8-4712-95b8-37e49e6e5ae3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387041626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.3387041626
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.1868329513
Short name T711
Test name
Test status
Simulation time 109091511 ps
CPU time 4.87 seconds
Started Mar 17 02:44:12 PM PDT 24
Finished Mar 17 02:44:17 PM PDT 24
Peak memory 218856 kb
Host smart-2b19f2ee-2060-4d2c-b119-8cf296fef364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868329513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.1868329513
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.3415936022
Short name T782
Test name
Test status
Simulation time 244670430 ps
CPU time 3.52 seconds
Started Mar 17 02:44:11 PM PDT 24
Finished Mar 17 02:44:15 PM PDT 24
Peak memory 208984 kb
Host smart-f169fff5-7295-46b5-a88a-f8eadace4c2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3415936022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.3415936022
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.1023668245
Short name T456
Test name
Test status
Simulation time 962240135 ps
CPU time 3.4 seconds
Started Mar 17 02:44:13 PM PDT 24
Finished Mar 17 02:44:17 PM PDT 24
Peak memory 207108 kb
Host smart-0d5c3ce9-cd82-4b2f-8154-d64365c2fec0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023668245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.1023668245
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.4274386083
Short name T507
Test name
Test status
Simulation time 368167839 ps
CPU time 8.25 seconds
Started Mar 17 02:44:10 PM PDT 24
Finished Mar 17 02:44:19 PM PDT 24
Peak memory 209272 kb
Host smart-b0b671bc-4bf6-4736-b881-0ff91ce4c163
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274386083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.4274386083
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.4110358514
Short name T860
Test name
Test status
Simulation time 44590874 ps
CPU time 2.8 seconds
Started Mar 17 02:44:10 PM PDT 24
Finished Mar 17 02:44:13 PM PDT 24
Peak memory 209060 kb
Host smart-65c0179a-61d8-40d0-a639-58416ad2c6fa
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4110358514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.4110358514
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.2571346689
Short name T449
Test name
Test status
Simulation time 318621189 ps
CPU time 2.4 seconds
Started Mar 17 02:44:17 PM PDT 24
Finished Mar 17 02:44:20 PM PDT 24
Peak memory 210524 kb
Host smart-1e8da8bf-ab0f-43ba-9d72-0f15ceb41dc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2571346689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.2571346689
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.836476330
Short name T635
Test name
Test status
Simulation time 50263367 ps
CPU time 2.46 seconds
Started Mar 17 02:44:11 PM PDT 24
Finished Mar 17 02:44:14 PM PDT 24
Peak memory 208196 kb
Host smart-06bd4394-43c9-4880-bf00-582b42a493e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=836476330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.836476330
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.1850764049
Short name T184
Test name
Test status
Simulation time 7742006863 ps
CPU time 189.97 seconds
Started Mar 17 02:44:18 PM PDT 24
Finished Mar 17 02:47:28 PM PDT 24
Peak memory 219284 kb
Host smart-4e012f94-67c8-4875-9b1f-943c24acc991
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1850764049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.1850764049
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.3473214189
Short name T856
Test name
Test status
Simulation time 143243314 ps
CPU time 5.31 seconds
Started Mar 17 02:44:12 PM PDT 24
Finished Mar 17 02:44:17 PM PDT 24
Peak memory 209032 kb
Host smart-8f7e6080-085d-4263-b286-1d004e08b87b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473214189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.3473214189
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.453541418
Short name T805
Test name
Test status
Simulation time 57823588 ps
CPU time 2.74 seconds
Started Mar 17 02:44:15 PM PDT 24
Finished Mar 17 02:44:17 PM PDT 24
Peak memory 210284 kb
Host smart-d289117e-94a1-4a61-a28b-81294f3b5fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=453541418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.453541418
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.3399372512
Short name T602
Test name
Test status
Simulation time 39379327 ps
CPU time 0.73 seconds
Started Mar 17 02:44:15 PM PDT 24
Finished Mar 17 02:44:15 PM PDT 24
Peak memory 206396 kb
Host smart-7ff75c0c-c8bd-472b-935e-9ef810583371
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3399372512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.3399372512
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.377453358
Short name T732
Test name
Test status
Simulation time 1024313877 ps
CPU time 9.4 seconds
Started Mar 17 02:44:21 PM PDT 24
Finished Mar 17 02:44:30 PM PDT 24
Peak memory 209480 kb
Host smart-d00b1dd8-d56a-4c0d-9b4a-b755aa023ad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=377453358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.377453358
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.936515065
Short name T846
Test name
Test status
Simulation time 282238938 ps
CPU time 2.87 seconds
Started Mar 17 02:44:18 PM PDT 24
Finished Mar 17 02:44:21 PM PDT 24
Peak memory 218760 kb
Host smart-07256a01-08e1-432e-a6c7-1d301374f04f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936515065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.936515065
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.3221945153
Short name T89
Test name
Test status
Simulation time 3630095740 ps
CPU time 37.82 seconds
Started Mar 17 02:44:13 PM PDT 24
Finished Mar 17 02:44:51 PM PDT 24
Peak memory 210052 kb
Host smart-dc7f3630-f9ea-4691-90fb-808982da4531
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3221945153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.3221945153
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.3618170111
Short name T292
Test name
Test status
Simulation time 62212072 ps
CPU time 4.53 seconds
Started Mar 17 02:44:15 PM PDT 24
Finished Mar 17 02:44:19 PM PDT 24
Peak memory 220904 kb
Host smart-8425ee32-c5a1-4cd5-86ba-b6d300d43cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618170111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.3618170111
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.1801672980
Short name T790
Test name
Test status
Simulation time 98987148 ps
CPU time 3.49 seconds
Started Mar 17 02:44:14 PM PDT 24
Finished Mar 17 02:44:17 PM PDT 24
Peak memory 214868 kb
Host smart-8741b355-d701-4170-a28d-f487b482c482
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1801672980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.1801672980
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.1469429395
Short name T106
Test name
Test status
Simulation time 58339158 ps
CPU time 2.84 seconds
Started Mar 17 02:44:15 PM PDT 24
Finished Mar 17 02:44:17 PM PDT 24
Peak memory 208088 kb
Host smart-1d31f258-80ab-4d50-9d7d-7a3c7986399a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1469429395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.1469429395
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.855709163
Short name T5
Test name
Test status
Simulation time 60969326 ps
CPU time 3.3 seconds
Started Mar 17 02:44:17 PM PDT 24
Finished Mar 17 02:44:20 PM PDT 24
Peak memory 207124 kb
Host smart-833c49d5-bb54-441a-8830-b2145b21bbdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=855709163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.855709163
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.1461407599
Short name T79
Test name
Test status
Simulation time 81109236 ps
CPU time 2.84 seconds
Started Mar 17 02:44:21 PM PDT 24
Finished Mar 17 02:44:24 PM PDT 24
Peak memory 209612 kb
Host smart-6d16fea2-2f7f-418b-b23f-c6633b1295c2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461407599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.1461407599
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.3199331706
Short name T728
Test name
Test status
Simulation time 275104132 ps
CPU time 3.33 seconds
Started Mar 17 02:44:21 PM PDT 24
Finished Mar 17 02:44:25 PM PDT 24
Peak memory 209296 kb
Host smart-220055af-d58b-485a-b68b-8afeb177c70b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199331706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.3199331706
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.1207872433
Short name T355
Test name
Test status
Simulation time 1685544487 ps
CPU time 22.51 seconds
Started Mar 17 02:44:15 PM PDT 24
Finished Mar 17 02:44:37 PM PDT 24
Peak memory 208792 kb
Host smart-88d65a32-855c-41e3-8403-e9c2d563f679
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1207872433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.1207872433
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.691445875
Short name T435
Test name
Test status
Simulation time 619846023 ps
CPU time 6.22 seconds
Started Mar 17 02:44:16 PM PDT 24
Finished Mar 17 02:44:22 PM PDT 24
Peak memory 209116 kb
Host smart-fbd07d9f-3d7b-47c4-87ef-796c8fb03213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691445875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.691445875
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.1279442554
Short name T82
Test name
Test status
Simulation time 160269128 ps
CPU time 2.54 seconds
Started Mar 17 02:44:17 PM PDT 24
Finished Mar 17 02:44:19 PM PDT 24
Peak memory 209064 kb
Host smart-8d2867da-bdd6-4510-bf81-a380919a0fa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1279442554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.1279442554
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.296019806
Short name T579
Test name
Test status
Simulation time 114946753 ps
CPU time 2.63 seconds
Started Mar 17 02:44:14 PM PDT 24
Finished Mar 17 02:44:17 PM PDT 24
Peak memory 207656 kb
Host smart-fc6495e6-709c-47bc-b839-b58114060899
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296019806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.296019806
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.2129701711
Short name T537
Test name
Test status
Simulation time 11300896 ps
CPU time 0.87 seconds
Started Mar 17 02:44:22 PM PDT 24
Finished Mar 17 02:44:23 PM PDT 24
Peak memory 206336 kb
Host smart-803db45a-d4da-463d-b17b-672a4fda6018
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2129701711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.2129701711
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.841496372
Short name T267
Test name
Test status
Simulation time 269404831 ps
CPU time 2.59 seconds
Started Mar 17 02:44:18 PM PDT 24
Finished Mar 17 02:44:21 PM PDT 24
Peak memory 207740 kb
Host smart-21e5ade1-d8c7-4a1f-8c49-180ec1ff2796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=841496372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.841496372
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.1037872390
Short name T375
Test name
Test status
Simulation time 110529656 ps
CPU time 5.21 seconds
Started Mar 17 02:44:20 PM PDT 24
Finished Mar 17 02:44:26 PM PDT 24
Peak memory 208932 kb
Host smart-46ae59cd-aa97-407b-9e7e-f8904fac1d7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1037872390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.1037872390
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.3100583287
Short name T451
Test name
Test status
Simulation time 28713781 ps
CPU time 1.63 seconds
Started Mar 17 02:44:14 PM PDT 24
Finished Mar 17 02:44:15 PM PDT 24
Peak memory 206592 kb
Host smart-abcf09bc-836c-42a3-8716-a7169488cfed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3100583287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.3100583287
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.2753776793
Short name T209
Test name
Test status
Simulation time 208790396 ps
CPU time 3.73 seconds
Started Mar 17 02:44:15 PM PDT 24
Finished Mar 17 02:44:19 PM PDT 24
Peak memory 208528 kb
Host smart-02ec84b1-6561-40a5-a147-e64b23480a7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753776793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.2753776793
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.2617251086
Short name T16
Test name
Test status
Simulation time 51669973 ps
CPU time 2.93 seconds
Started Mar 17 02:44:17 PM PDT 24
Finished Mar 17 02:44:20 PM PDT 24
Peak memory 207188 kb
Host smart-8676faef-bbf6-4fc9-a50a-1898afc0dbdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2617251086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.2617251086
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.3037160899
Short name T640
Test name
Test status
Simulation time 53860439 ps
CPU time 2.21 seconds
Started Mar 17 02:44:16 PM PDT 24
Finished Mar 17 02:44:18 PM PDT 24
Peak memory 209092 kb
Host smart-678efa30-c506-49d7-b487-95485f248087
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037160899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.3037160899
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.88895285
Short name T438
Test name
Test status
Simulation time 99605441 ps
CPU time 2.87 seconds
Started Mar 17 02:44:17 PM PDT 24
Finished Mar 17 02:44:20 PM PDT 24
Peak memory 207188 kb
Host smart-56f5a529-63fd-4171-8d31-f36a8be4cbf1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88895285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.88895285
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.1695563702
Short name T446
Test name
Test status
Simulation time 173140177 ps
CPU time 3.36 seconds
Started Mar 17 02:44:17 PM PDT 24
Finished Mar 17 02:44:21 PM PDT 24
Peak memory 207364 kb
Host smart-0f9462d2-8a77-4201-8e58-08771ff1a0ff
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1695563702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.1695563702
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.538974283
Short name T496
Test name
Test status
Simulation time 50190829 ps
CPU time 2.78 seconds
Started Mar 17 02:44:21 PM PDT 24
Finished Mar 17 02:44:24 PM PDT 24
Peak memory 209736 kb
Host smart-c8eed6e3-8575-436c-9ec8-029b3877a245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538974283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.538974283
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.2620041938
Short name T436
Test name
Test status
Simulation time 133154444 ps
CPU time 4.72 seconds
Started Mar 17 02:44:13 PM PDT 24
Finished Mar 17 02:44:18 PM PDT 24
Peak memory 208260 kb
Host smart-d5f6c5bf-e391-470f-b3f9-e80d1d2655e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620041938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.2620041938
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.2548246331
Short name T50
Test name
Test status
Simulation time 925051573 ps
CPU time 33.94 seconds
Started Mar 17 02:44:20 PM PDT 24
Finished Mar 17 02:44:54 PM PDT 24
Peak memory 222944 kb
Host smart-f77fb9c1-0ffb-416a-860e-c3338155a4b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2548246331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.2548246331
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_stress_all_with_rand_reset.3137701217
Short name T121
Test name
Test status
Simulation time 1510326500 ps
CPU time 23.63 seconds
Started Mar 17 02:44:20 PM PDT 24
Finished Mar 17 02:44:43 PM PDT 24
Peak memory 223500 kb
Host smart-336c1fa5-f6d0-4242-92d8-084292a398c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3137701217 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all_with_rand_reset.3137701217
Directory /workspace/29.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.3506148504
Short name T454
Test name
Test status
Simulation time 17200754881 ps
CPU time 45.93 seconds
Started Mar 17 02:44:16 PM PDT 24
Finished Mar 17 02:45:02 PM PDT 24
Peak memory 209152 kb
Host smart-135ea4a5-d962-4b33-ba8a-6567941b286c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506148504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.3506148504
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.2144194451
Short name T35
Test name
Test status
Simulation time 47095514 ps
CPU time 2.63 seconds
Started Mar 17 02:44:21 PM PDT 24
Finished Mar 17 02:44:24 PM PDT 24
Peak memory 210300 kb
Host smart-824a65c7-c223-49a1-9d9e-9b38c4130d17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144194451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.2144194451
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.1799433409
Short name T469
Test name
Test status
Simulation time 13862862 ps
CPU time 0.93 seconds
Started Mar 17 02:42:45 PM PDT 24
Finished Mar 17 02:42:46 PM PDT 24
Peak memory 206396 kb
Host smart-31e4a46e-5ae1-40ae-8a1a-2ef494975482
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1799433409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.1799433409
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.1516127275
Short name T379
Test name
Test status
Simulation time 53732816 ps
CPU time 3.8 seconds
Started Mar 17 02:42:38 PM PDT 24
Finished Mar 17 02:42:42 PM PDT 24
Peak memory 215824 kb
Host smart-b436d162-b4c5-44c8-baf0-c25afae84395
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1516127275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.1516127275
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.2598980554
Short name T194
Test name
Test status
Simulation time 356889540 ps
CPU time 1.87 seconds
Started Mar 17 02:42:41 PM PDT 24
Finished Mar 17 02:42:43 PM PDT 24
Peak memory 207960 kb
Host smart-8a96f139-cf93-4620-83df-6a8e3c50d9b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598980554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.2598980554
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.1577164000
Short name T675
Test name
Test status
Simulation time 199675630 ps
CPU time 5.89 seconds
Started Mar 17 02:42:41 PM PDT 24
Finished Mar 17 02:42:47 PM PDT 24
Peak memory 214884 kb
Host smart-ec61c5a2-c8bd-4957-b578-440a2909e023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577164000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.1577164000
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.3527924300
Short name T252
Test name
Test status
Simulation time 1448138184 ps
CPU time 13.85 seconds
Started Mar 17 02:42:40 PM PDT 24
Finished Mar 17 02:42:54 PM PDT 24
Peak memory 214744 kb
Host smart-452ab0dc-fd8e-4551-acba-32fba4933385
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527924300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.3527924300
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.2323692218
Short name T235
Test name
Test status
Simulation time 562266760 ps
CPU time 5.68 seconds
Started Mar 17 02:42:40 PM PDT 24
Finished Mar 17 02:42:46 PM PDT 24
Peak memory 220784 kb
Host smart-cba1936f-dd4a-4ad9-91e8-2c43c5d0a18d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2323692218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.2323692218
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.2614048978
Short name T527
Test name
Test status
Simulation time 144064290 ps
CPU time 3.06 seconds
Started Mar 17 02:42:40 PM PDT 24
Finished Mar 17 02:42:44 PM PDT 24
Peak memory 214676 kb
Host smart-245ab615-2e6c-4161-93be-2b281912ef0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614048978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.2614048978
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.3083780921
Short name T13
Test name
Test status
Simulation time 746213893 ps
CPU time 15.69 seconds
Started Mar 17 02:42:47 PM PDT 24
Finished Mar 17 02:43:04 PM PDT 24
Peak memory 240600 kb
Host smart-4d5487cd-df91-42c7-9b3a-28852bd5e139
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3083780921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.3083780921
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sideload.1118748558
Short name T601
Test name
Test status
Simulation time 85290488 ps
CPU time 3.63 seconds
Started Mar 17 02:42:34 PM PDT 24
Finished Mar 17 02:42:38 PM PDT 24
Peak memory 206536 kb
Host smart-ed1624e9-094a-42e6-89fe-641d3d0774b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118748558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.1118748558
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.4077402513
Short name T190
Test name
Test status
Simulation time 292522685 ps
CPU time 3 seconds
Started Mar 17 02:42:39 PM PDT 24
Finished Mar 17 02:42:43 PM PDT 24
Peak memory 208936 kb
Host smart-4f59a8f3-72e6-4cf2-b16d-d6e4f8ee25eb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4077402513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.4077402513
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.2330677685
Short name T603
Test name
Test status
Simulation time 135467659 ps
CPU time 2.43 seconds
Started Mar 17 02:42:40 PM PDT 24
Finished Mar 17 02:42:42 PM PDT 24
Peak memory 207384 kb
Host smart-1002371f-e99f-4e03-90b7-2e9e3f74e826
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330677685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.2330677685
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.171639572
Short name T682
Test name
Test status
Simulation time 220289589 ps
CPU time 2.99 seconds
Started Mar 17 02:42:40 PM PDT 24
Finished Mar 17 02:42:43 PM PDT 24
Peak memory 208916 kb
Host smart-d157da87-900b-4055-99fb-c762ac4cc3a4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=171639572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.171639572
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.162994651
Short name T676
Test name
Test status
Simulation time 145130204 ps
CPU time 2.82 seconds
Started Mar 17 02:42:41 PM PDT 24
Finished Mar 17 02:42:44 PM PDT 24
Peak memory 208292 kb
Host smart-542b4257-7cc2-4689-8286-afa53997773a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162994651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.162994651
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.2146939745
Short name T723
Test name
Test status
Simulation time 554333135 ps
CPU time 3.98 seconds
Started Mar 17 02:42:37 PM PDT 24
Finished Mar 17 02:42:41 PM PDT 24
Peak memory 209132 kb
Host smart-f6c7afed-7c90-4a58-b5e3-6937f460d752
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146939745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.2146939745
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all_with_rand_reset.2241397392
Short name T719
Test name
Test status
Simulation time 138722097 ps
CPU time 10.51 seconds
Started Mar 17 02:42:44 PM PDT 24
Finished Mar 17 02:42:54 PM PDT 24
Peak memory 223152 kb
Host smart-50f226f6-95a1-4461-a2f5-43401b7756db
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241397392 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all_with_rand_reset.2241397392
Directory /workspace/3.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.1009916194
Short name T585
Test name
Test status
Simulation time 185133814 ps
CPU time 4.63 seconds
Started Mar 17 02:42:41 PM PDT 24
Finished Mar 17 02:42:46 PM PDT 24
Peak memory 210496 kb
Host smart-1f80c4fd-923d-4a87-9243-d47fc8c66707
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009916194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.1009916194
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.499089065
Short name T384
Test name
Test status
Simulation time 101775130 ps
CPU time 1.99 seconds
Started Mar 17 02:42:40 PM PDT 24
Finished Mar 17 02:42:42 PM PDT 24
Peak memory 210560 kb
Host smart-cb1b244b-b9be-4945-a3d0-04eafcfc8bf5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=499089065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.499089065
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.2593995611
Short name T849
Test name
Test status
Simulation time 35344532 ps
CPU time 0.75 seconds
Started Mar 17 02:44:20 PM PDT 24
Finished Mar 17 02:44:21 PM PDT 24
Peak memory 206436 kb
Host smart-d6f15461-0ba4-41f4-acc6-3eb18da94322
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593995611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.2593995611
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.1538473388
Short name T65
Test name
Test status
Simulation time 849492538 ps
CPU time 12.14 seconds
Started Mar 17 02:44:20 PM PDT 24
Finished Mar 17 02:44:32 PM PDT 24
Peak memory 211240 kb
Host smart-38819b0e-4333-4a05-b8cb-22af7ca44bc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538473388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.1538473388
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.1828285775
Short name T290
Test name
Test status
Simulation time 173678749 ps
CPU time 4.08 seconds
Started Mar 17 02:44:19 PM PDT 24
Finished Mar 17 02:44:24 PM PDT 24
Peak memory 218816 kb
Host smart-bee06992-54ee-4b14-b3f6-0abc6823c610
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828285775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.1828285775
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.452011738
Short name T793
Test name
Test status
Simulation time 233132431 ps
CPU time 4.22 seconds
Started Mar 17 02:44:20 PM PDT 24
Finished Mar 17 02:44:24 PM PDT 24
Peak memory 222824 kb
Host smart-b02ff085-ef8f-40e5-a783-afd97b82514f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=452011738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.452011738
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.3704829538
Short name T260
Test name
Test status
Simulation time 2127266029 ps
CPU time 8.72 seconds
Started Mar 17 02:44:20 PM PDT 24
Finished Mar 17 02:44:29 PM PDT 24
Peak memory 220572 kb
Host smart-f3415e33-fbb2-4395-88f6-0353e62b817e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704829538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.3704829538
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.1190912344
Short name T282
Test name
Test status
Simulation time 2964826552 ps
CPU time 20.57 seconds
Started Mar 17 02:44:22 PM PDT 24
Finished Mar 17 02:44:43 PM PDT 24
Peak memory 210376 kb
Host smart-9d4ab97c-74c3-4f60-8b29-d2adb505d769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190912344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.1190912344
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.1964158907
Short name T314
Test name
Test status
Simulation time 315879654 ps
CPU time 5.31 seconds
Started Mar 17 02:44:22 PM PDT 24
Finished Mar 17 02:44:28 PM PDT 24
Peak memory 207128 kb
Host smart-ed925a03-bf5f-4bd6-b6a7-2736c4362d03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964158907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.1964158907
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.739037848
Short name T807
Test name
Test status
Simulation time 59119101 ps
CPU time 2.33 seconds
Started Mar 17 02:44:21 PM PDT 24
Finished Mar 17 02:44:23 PM PDT 24
Peak memory 207308 kb
Host smart-8bb0d4df-0ba2-4516-a1d1-16215168f592
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=739037848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.739037848
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.1563181735
Short name T242
Test name
Test status
Simulation time 88987679 ps
CPU time 2.55 seconds
Started Mar 17 02:44:19 PM PDT 24
Finished Mar 17 02:44:22 PM PDT 24
Peak memory 208920 kb
Host smart-e23f89e3-5cc3-4776-af56-ead437b8e483
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1563181735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.1563181735
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.1635350987
Short name T896
Test name
Test status
Simulation time 153122809 ps
CPU time 3.67 seconds
Started Mar 17 02:44:21 PM PDT 24
Finished Mar 17 02:44:25 PM PDT 24
Peak memory 209288 kb
Host smart-2b95d5dd-9be4-475a-9f3a-b9b524c92192
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1635350987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.1635350987
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.997384818
Short name T692
Test name
Test status
Simulation time 149715890 ps
CPU time 3.09 seconds
Started Mar 17 02:44:22 PM PDT 24
Finished Mar 17 02:44:26 PM PDT 24
Peak memory 214848 kb
Host smart-cd504540-3872-4362-a20d-4c8d5130386e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=997384818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.997384818
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.3006421750
Short name T587
Test name
Test status
Simulation time 1558537676 ps
CPU time 24.99 seconds
Started Mar 17 02:44:22 PM PDT 24
Finished Mar 17 02:44:47 PM PDT 24
Peak memory 208860 kb
Host smart-aa297dcd-8b52-46fc-aef9-db69550bda9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006421750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.3006421750
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all_with_rand_reset.2726334460
Short name T323
Test name
Test status
Simulation time 1973036100 ps
CPU time 16.48 seconds
Started Mar 17 02:44:21 PM PDT 24
Finished Mar 17 02:44:38 PM PDT 24
Peak memory 223068 kb
Host smart-fbaadac8-9b0c-48f0-a049-2acee1f3ac30
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726334460 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all_with_rand_reset.2726334460
Directory /workspace/30.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.461977382
Short name T364
Test name
Test status
Simulation time 259225760 ps
CPU time 8.64 seconds
Started Mar 17 02:44:22 PM PDT 24
Finished Mar 17 02:44:31 PM PDT 24
Peak memory 208132 kb
Host smart-9c51e678-4071-46d2-ad3d-5ed0abb98a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461977382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.461977382
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.3966333532
Short name T562
Test name
Test status
Simulation time 87669575 ps
CPU time 2.63 seconds
Started Mar 17 02:44:22 PM PDT 24
Finished Mar 17 02:44:25 PM PDT 24
Peak memory 210548 kb
Host smart-b7e324a0-f7f6-4696-b744-1403123bad56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966333532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.3966333532
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.2912299006
Short name T724
Test name
Test status
Simulation time 22573654 ps
CPU time 0.8 seconds
Started Mar 17 02:44:25 PM PDT 24
Finished Mar 17 02:44:26 PM PDT 24
Peak memory 206312 kb
Host smart-90da982c-1025-40ed-b91d-8d0d3e9ce6dd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2912299006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.2912299006
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.1509841848
Short name T369
Test name
Test status
Simulation time 734974435 ps
CPU time 3.54 seconds
Started Mar 17 02:44:22 PM PDT 24
Finished Mar 17 02:44:26 PM PDT 24
Peak memory 215972 kb
Host smart-8f743413-30bb-4eae-9ce4-ddda07f9ef00
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1509841848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.1509841848
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.3326017919
Short name T605
Test name
Test status
Simulation time 96239751 ps
CPU time 4.32 seconds
Started Mar 17 02:44:31 PM PDT 24
Finished Mar 17 02:44:35 PM PDT 24
Peak memory 221080 kb
Host smart-dfe08af7-84e7-415c-abb7-cf5b2042b03d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3326017919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.3326017919
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.3886126661
Short name T334
Test name
Test status
Simulation time 128523607 ps
CPU time 2.54 seconds
Started Mar 17 02:44:21 PM PDT 24
Finished Mar 17 02:44:24 PM PDT 24
Peak memory 210304 kb
Host smart-45bc8c27-ab72-4354-9c4e-03c52dda475a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886126661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.3886126661
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.2354248494
Short name T22
Test name
Test status
Simulation time 86931157 ps
CPU time 4.63 seconds
Started Mar 17 02:44:24 PM PDT 24
Finished Mar 17 02:44:29 PM PDT 24
Peak memory 220912 kb
Host smart-06a6cc23-ea8d-429a-ba7c-7e20f93f1ae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2354248494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.2354248494
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.522554056
Short name T599
Test name
Test status
Simulation time 133598646 ps
CPU time 2.28 seconds
Started Mar 17 02:44:30 PM PDT 24
Finished Mar 17 02:44:32 PM PDT 24
Peak memory 214832 kb
Host smart-13f00507-39bd-4ce0-b958-42aa1c34a46f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522554056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.522554056
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.1878626107
Short name T770
Test name
Test status
Simulation time 112637696 ps
CPU time 3.86 seconds
Started Mar 17 02:44:22 PM PDT 24
Finished Mar 17 02:44:26 PM PDT 24
Peak memory 214884 kb
Host smart-1557505f-e84f-440a-bebc-0d29f95778ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1878626107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.1878626107
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.3118481050
Short name T594
Test name
Test status
Simulation time 520188677 ps
CPU time 4.64 seconds
Started Mar 17 02:44:22 PM PDT 24
Finished Mar 17 02:44:26 PM PDT 24
Peak memory 209164 kb
Host smart-c348a4d7-f786-4470-9186-f692f63400d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3118481050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.3118481050
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.4107218905
Short name T466
Test name
Test status
Simulation time 727117673 ps
CPU time 8.7 seconds
Started Mar 17 02:44:23 PM PDT 24
Finished Mar 17 02:44:32 PM PDT 24
Peak memory 208516 kb
Host smart-2b0fb9bf-eae3-4444-9afa-77592848d00c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107218905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.4107218905
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.2318252501
Short name T428
Test name
Test status
Simulation time 47761426 ps
CPU time 3.05 seconds
Started Mar 17 02:44:22 PM PDT 24
Finished Mar 17 02:44:25 PM PDT 24
Peak memory 209056 kb
Host smart-7141b678-4551-4668-a39f-f5e2a264f9f1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2318252501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.2318252501
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.3248962291
Short name T564
Test name
Test status
Simulation time 73371269 ps
CPU time 3.3 seconds
Started Mar 17 02:44:20 PM PDT 24
Finished Mar 17 02:44:23 PM PDT 24
Peak memory 208332 kb
Host smart-de6aff9d-981e-407f-96b3-157c541a29cc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248962291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.3248962291
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.444236006
Short name T778
Test name
Test status
Simulation time 136838905 ps
CPU time 2.77 seconds
Started Mar 17 02:44:26 PM PDT 24
Finished Mar 17 02:44:28 PM PDT 24
Peak memory 216224 kb
Host smart-dae9aff5-2a9a-4d6c-83ed-a5985ea9fc1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444236006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.444236006
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.1655838213
Short name T85
Test name
Test status
Simulation time 79052346 ps
CPU time 3.43 seconds
Started Mar 17 02:44:22 PM PDT 24
Finished Mar 17 02:44:26 PM PDT 24
Peak memory 208332 kb
Host smart-601c8514-419c-4ed8-819e-e6e0e3f1a92a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655838213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.1655838213
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.2534825439
Short name T654
Test name
Test status
Simulation time 278782822 ps
CPU time 5.87 seconds
Started Mar 17 02:44:28 PM PDT 24
Finished Mar 17 02:44:34 PM PDT 24
Peak memory 211084 kb
Host smart-45a13b15-b683-434a-ae40-243fc95d4fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2534825439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.2534825439
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.497314104
Short name T199
Test name
Test status
Simulation time 216578376 ps
CPU time 2.53 seconds
Started Mar 17 02:44:29 PM PDT 24
Finished Mar 17 02:44:32 PM PDT 24
Peak memory 210216 kb
Host smart-667b5ea6-5992-43af-8f4d-1b40b3afea01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=497314104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.497314104
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.1792738667
Short name T714
Test name
Test status
Simulation time 46652823 ps
CPU time 0.78 seconds
Started Mar 17 02:44:29 PM PDT 24
Finished Mar 17 02:44:30 PM PDT 24
Peak memory 206436 kb
Host smart-02b109d1-7fc7-443e-b9c7-fb7f9c184e43
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1792738667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.1792738667
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.3572883024
Short name T417
Test name
Test status
Simulation time 47104328 ps
CPU time 3.79 seconds
Started Mar 17 02:44:25 PM PDT 24
Finished Mar 17 02:44:29 PM PDT 24
Peak memory 214736 kb
Host smart-bbe1c582-1f7f-4485-8bdd-aa813e1907b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3572883024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.3572883024
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.4266404999
Short name T660
Test name
Test status
Simulation time 187319817 ps
CPU time 7.41 seconds
Started Mar 17 02:44:25 PM PDT 24
Finished Mar 17 02:44:33 PM PDT 24
Peak memory 222252 kb
Host smart-e3e6c03f-1e09-432b-bffd-06947293d305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4266404999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.4266404999
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.2385233890
Short name T214
Test name
Test status
Simulation time 163690011 ps
CPU time 4.22 seconds
Started Mar 17 02:44:26 PM PDT 24
Finished Mar 17 02:44:30 PM PDT 24
Peak memory 210344 kb
Host smart-331110f9-2a37-4ac5-a4ec-f73699abdf8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385233890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.2385233890
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.1068465974
Short name T94
Test name
Test status
Simulation time 105708330 ps
CPU time 4.52 seconds
Started Mar 17 02:44:27 PM PDT 24
Finished Mar 17 02:44:32 PM PDT 24
Peak memory 214792 kb
Host smart-a1c2dddb-3176-4182-bec1-c96f7e240e08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068465974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.1068465974
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.947291548
Short name T597
Test name
Test status
Simulation time 86376223 ps
CPU time 4.32 seconds
Started Mar 17 02:44:27 PM PDT 24
Finished Mar 17 02:44:31 PM PDT 24
Peak memory 210000 kb
Host smart-30feb99a-ca20-430b-aa2a-00891be45b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=947291548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.947291548
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.2956097563
Short name T604
Test name
Test status
Simulation time 395233354 ps
CPU time 12.96 seconds
Started Mar 17 02:44:27 PM PDT 24
Finished Mar 17 02:44:40 PM PDT 24
Peak memory 210008 kb
Host smart-93c7fdec-ffbe-456b-a876-dc7518471be0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2956097563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.2956097563
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.3005655934
Short name T566
Test name
Test status
Simulation time 22427779 ps
CPU time 1.9 seconds
Started Mar 17 02:44:25 PM PDT 24
Finished Mar 17 02:44:27 PM PDT 24
Peak memory 207204 kb
Host smart-e70943e7-78ed-43ee-88b3-ca2ef3fcdfa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3005655934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.3005655934
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.510674493
Short name T132
Test name
Test status
Simulation time 74047230 ps
CPU time 3.27 seconds
Started Mar 17 02:44:24 PM PDT 24
Finished Mar 17 02:44:27 PM PDT 24
Peak memory 208456 kb
Host smart-7b384b19-3563-4a25-8422-f11eae838213
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510674493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.510674493
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.1667456617
Short name T179
Test name
Test status
Simulation time 182590467 ps
CPU time 2.18 seconds
Started Mar 17 02:44:25 PM PDT 24
Finished Mar 17 02:44:28 PM PDT 24
Peak memory 208924 kb
Host smart-2ee3cf08-9c73-45e1-ae32-2a562e37e332
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667456617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.1667456617
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.677550089
Short name T175
Test name
Test status
Simulation time 134546384 ps
CPU time 1.89 seconds
Started Mar 17 02:44:26 PM PDT 24
Finished Mar 17 02:44:28 PM PDT 24
Peak memory 207312 kb
Host smart-fb85c1ad-b3b5-4d48-8893-31e78d10ffa2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677550089 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.677550089
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.2385968085
Short name T718
Test name
Test status
Simulation time 192484743 ps
CPU time 2.3 seconds
Started Mar 17 02:44:26 PM PDT 24
Finished Mar 17 02:44:28 PM PDT 24
Peak memory 208620 kb
Host smart-b982b32d-8850-4ca3-9444-4b3bae4a2c38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385968085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.2385968085
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.1728936498
Short name T534
Test name
Test status
Simulation time 518983346 ps
CPU time 2.82 seconds
Started Mar 17 02:44:28 PM PDT 24
Finished Mar 17 02:44:31 PM PDT 24
Peak memory 208036 kb
Host smart-cb686f77-ac55-40d5-b53a-b7626fb44116
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1728936498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.1728936498
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.1228302446
Short name T381
Test name
Test status
Simulation time 1516567347 ps
CPU time 21 seconds
Started Mar 17 02:44:25 PM PDT 24
Finished Mar 17 02:44:46 PM PDT 24
Peak memory 215764 kb
Host smart-dd0c2d77-31f8-443a-b82a-6b7da8843632
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1228302446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.1228302446
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.3217420371
Short name T188
Test name
Test status
Simulation time 625038944 ps
CPU time 7.2 seconds
Started Mar 17 02:44:30 PM PDT 24
Finished Mar 17 02:44:37 PM PDT 24
Peak memory 214832 kb
Host smart-d0c47d17-3fb3-414e-9ac6-0b33c6ee2be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217420371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.3217420371
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.2569931579
Short name T58
Test name
Test status
Simulation time 170244077 ps
CPU time 2.79 seconds
Started Mar 17 02:44:29 PM PDT 24
Finished Mar 17 02:44:32 PM PDT 24
Peak memory 210432 kb
Host smart-0e9b0170-ecbd-4378-82a2-52d31a20e147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569931579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.2569931579
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.1450473928
Short name T500
Test name
Test status
Simulation time 42145217 ps
CPU time 0.76 seconds
Started Mar 17 02:44:33 PM PDT 24
Finished Mar 17 02:44:34 PM PDT 24
Peak memory 206364 kb
Host smart-6e8a3531-e6a2-4207-9898-15dd393f8e4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450473928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.1450473928
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.810831555
Short name T237
Test name
Test status
Simulation time 95168493 ps
CPU time 3.58 seconds
Started Mar 17 02:44:34 PM PDT 24
Finished Mar 17 02:44:38 PM PDT 24
Peak memory 216056 kb
Host smart-025ac08e-0ade-4d25-b3b2-b64455e76599
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=810831555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.810831555
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.2801241985
Short name T241
Test name
Test status
Simulation time 68834087 ps
CPU time 2.93 seconds
Started Mar 17 02:44:34 PM PDT 24
Finished Mar 17 02:44:37 PM PDT 24
Peak memory 210184 kb
Host smart-d637d856-22a2-4df4-a058-1be924f3132d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2801241985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.2801241985
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.3850048764
Short name T754
Test name
Test status
Simulation time 179068812 ps
CPU time 4.44 seconds
Started Mar 17 02:44:33 PM PDT 24
Finished Mar 17 02:44:38 PM PDT 24
Peak memory 210136 kb
Host smart-3148ead2-bccf-4dc8-a7a2-bfe155e3194f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850048764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.3850048764
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.2270925322
Short name T195
Test name
Test status
Simulation time 286957860 ps
CPU time 9.56 seconds
Started Mar 17 02:44:32 PM PDT 24
Finished Mar 17 02:44:42 PM PDT 24
Peak memory 214760 kb
Host smart-7e0bca54-596f-4504-b697-6e8f434658f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270925322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.2270925322
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.63768890
Short name T521
Test name
Test status
Simulation time 392950219 ps
CPU time 3.46 seconds
Started Mar 17 02:44:32 PM PDT 24
Finished Mar 17 02:44:36 PM PDT 24
Peak memory 220660 kb
Host smart-39d88321-ed82-48a1-aded-5f016aa9ab48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=63768890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.63768890
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.3635734237
Short name T212
Test name
Test status
Simulation time 1163990111 ps
CPU time 30.09 seconds
Started Mar 17 02:44:33 PM PDT 24
Finished Mar 17 02:45:03 PM PDT 24
Peak memory 209088 kb
Host smart-df54cf0d-b0d8-41c1-bc2b-1e62fce53bdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635734237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.3635734237
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.721848216
Short name T786
Test name
Test status
Simulation time 34440916 ps
CPU time 2.38 seconds
Started Mar 17 02:44:24 PM PDT 24
Finished Mar 17 02:44:27 PM PDT 24
Peak memory 207148 kb
Host smart-f6ab14d4-26ed-4003-b334-2b4bfd975cea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=721848216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.721848216
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.181856129
Short name T474
Test name
Test status
Simulation time 51351429 ps
CPU time 2.89 seconds
Started Mar 17 02:44:31 PM PDT 24
Finished Mar 17 02:44:34 PM PDT 24
Peak memory 207388 kb
Host smart-cd1b2bac-5ef1-4f3f-8524-b985e8df3648
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181856129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.181856129
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.4072985887
Short name T551
Test name
Test status
Simulation time 1315125913 ps
CPU time 10.55 seconds
Started Mar 17 02:44:26 PM PDT 24
Finished Mar 17 02:44:37 PM PDT 24
Peak memory 209128 kb
Host smart-4b8dec32-8ea6-453b-b67d-9b91132338a9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072985887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.4072985887
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.21245636
Short name T549
Test name
Test status
Simulation time 36190513 ps
CPU time 2.86 seconds
Started Mar 17 02:44:31 PM PDT 24
Finished Mar 17 02:44:34 PM PDT 24
Peak memory 209328 kb
Host smart-3704644e-23ee-48d4-96fa-106aa48ddecb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21245636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.21245636
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.4081402245
Short name T518
Test name
Test status
Simulation time 232632339 ps
CPU time 5.7 seconds
Started Mar 17 02:44:33 PM PDT 24
Finished Mar 17 02:44:39 PM PDT 24
Peak memory 218744 kb
Host smart-d4554794-ed0b-43a1-98f3-eaaf4c2c3559
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081402245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.4081402245
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.1809594082
Short name T810
Test name
Test status
Simulation time 1011925897 ps
CPU time 3.31 seconds
Started Mar 17 02:44:27 PM PDT 24
Finished Mar 17 02:44:30 PM PDT 24
Peak memory 208904 kb
Host smart-8f607a11-78ac-479d-9c89-d3f7713429c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1809594082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.1809594082
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.1265734675
Short name T226
Test name
Test status
Simulation time 1058555721 ps
CPU time 9.85 seconds
Started Mar 17 02:44:31 PM PDT 24
Finished Mar 17 02:44:41 PM PDT 24
Peak memory 222892 kb
Host smart-355884fe-4ff5-480a-8690-fa7bc1781536
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1265734675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.1265734675
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.945657680
Short name T880
Test name
Test status
Simulation time 197588724 ps
CPU time 4.34 seconds
Started Mar 17 02:44:31 PM PDT 24
Finished Mar 17 02:44:36 PM PDT 24
Peak memory 210764 kb
Host smart-cd545bb5-3e23-44c0-9acc-1a97d66a0207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945657680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.945657680
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.1820934427
Short name T406
Test name
Test status
Simulation time 323955795 ps
CPU time 8.64 seconds
Started Mar 17 02:44:35 PM PDT 24
Finished Mar 17 02:44:44 PM PDT 24
Peak memory 211388 kb
Host smart-c95c57b0-393f-446d-8217-fceee8ea1f5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1820934427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.1820934427
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.2569790714
Short name T547
Test name
Test status
Simulation time 26010004 ps
CPU time 0.79 seconds
Started Mar 17 02:44:41 PM PDT 24
Finished Mar 17 02:44:42 PM PDT 24
Peak memory 206428 kb
Host smart-3106e746-8b14-46c5-a2db-81d5f86eb6e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2569790714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.2569790714
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.3572531886
Short name T136
Test name
Test status
Simulation time 316127450 ps
CPU time 3.62 seconds
Started Mar 17 02:44:33 PM PDT 24
Finished Mar 17 02:44:37 PM PDT 24
Peak memory 215820 kb
Host smart-9c626c68-3f43-46ea-97c2-49048562e341
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3572531886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.3572531886
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.3803553669
Short name T552
Test name
Test status
Simulation time 81811632 ps
CPU time 2.75 seconds
Started Mar 17 02:44:38 PM PDT 24
Finished Mar 17 02:44:40 PM PDT 24
Peak memory 208768 kb
Host smart-5b29ee58-dde8-466b-8d1f-05e88c882b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3803553669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.3803553669
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.1922529604
Short name T73
Test name
Test status
Simulation time 238411051 ps
CPU time 2.83 seconds
Started Mar 17 02:44:32 PM PDT 24
Finished Mar 17 02:44:35 PM PDT 24
Peak memory 218600 kb
Host smart-3bac5b81-a240-45bb-ae3c-0ee1a3ae92c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1922529604 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.1922529604
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.2230081930
Short name T96
Test name
Test status
Simulation time 83991177 ps
CPU time 3.33 seconds
Started Mar 17 02:44:31 PM PDT 24
Finished Mar 17 02:44:35 PM PDT 24
Peak memory 214728 kb
Host smart-3edc4606-9390-4078-bd2d-1f5541e6675c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2230081930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.2230081930
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.4281176399
Short name T482
Test name
Test status
Simulation time 476600220 ps
CPU time 3.15 seconds
Started Mar 17 02:44:34 PM PDT 24
Finished Mar 17 02:44:38 PM PDT 24
Peak memory 215564 kb
Host smart-d942b2ed-c359-4252-9024-d856f84d38e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4281176399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.4281176399
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.2687472169
Short name T582
Test name
Test status
Simulation time 719700829 ps
CPU time 15.56 seconds
Started Mar 17 02:44:32 PM PDT 24
Finished Mar 17 02:44:48 PM PDT 24
Peak memory 214692 kb
Host smart-4ce75cd7-18b6-402b-b80e-537750b9c133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687472169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.2687472169
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.1250402966
Short name T189
Test name
Test status
Simulation time 341554263 ps
CPU time 2.79 seconds
Started Mar 17 02:44:31 PM PDT 24
Finished Mar 17 02:44:34 PM PDT 24
Peak memory 207320 kb
Host smart-14d7c950-845a-4feb-966f-f62f972a6543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250402966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.1250402966
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.484532678
Short name T501
Test name
Test status
Simulation time 91433945 ps
CPU time 2.88 seconds
Started Mar 17 02:44:32 PM PDT 24
Finished Mar 17 02:44:36 PM PDT 24
Peak memory 208896 kb
Host smart-e0bc52fc-5e7d-41c5-ad87-3a1df74f5411
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484532678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.484532678
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.4288965247
Short name T760
Test name
Test status
Simulation time 208874298 ps
CPU time 2.99 seconds
Started Mar 17 02:44:32 PM PDT 24
Finished Mar 17 02:44:35 PM PDT 24
Peak memory 207200 kb
Host smart-89d7d00a-4f92-41ee-abd0-4d79657de3b2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288965247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.4288965247
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.109171585
Short name T444
Test name
Test status
Simulation time 35878448 ps
CPU time 2.36 seconds
Started Mar 17 02:44:32 PM PDT 24
Finished Mar 17 02:44:35 PM PDT 24
Peak memory 207168 kb
Host smart-85afd3e5-1fed-466d-9232-caeba7c05030
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=109171585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.109171585
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.3650622592
Short name T536
Test name
Test status
Simulation time 533464976 ps
CPU time 9.63 seconds
Started Mar 17 02:44:37 PM PDT 24
Finished Mar 17 02:44:47 PM PDT 24
Peak memory 209344 kb
Host smart-7cdb185c-8c8c-4924-95d0-091dc8c2cfa6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650622592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.3650622592
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.1091074177
Short name T429
Test name
Test status
Simulation time 73568694 ps
CPU time 3.25 seconds
Started Mar 17 02:44:32 PM PDT 24
Finished Mar 17 02:44:35 PM PDT 24
Peak memory 208900 kb
Host smart-92c9c020-2971-4a73-94e6-d85b7dc21f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1091074177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.1091074177
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.944696490
Short name T710
Test name
Test status
Simulation time 589662932 ps
CPU time 8.77 seconds
Started Mar 17 02:44:37 PM PDT 24
Finished Mar 17 02:44:46 PM PDT 24
Peak memory 215496 kb
Host smart-ff0f89c6-5e1a-4b16-8007-c6af50af4cb3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=944696490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.944696490
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_stress_all_with_rand_reset.3304215840
Short name T847
Test name
Test status
Simulation time 386730092 ps
CPU time 7.97 seconds
Started Mar 17 02:44:38 PM PDT 24
Finished Mar 17 02:44:47 PM PDT 24
Peak memory 223144 kb
Host smart-b4429c02-6760-4bac-96e3-89ab6017e467
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3304215840 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all_with_rand_reset.3304215840
Directory /workspace/34.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.3856040065
Short name T644
Test name
Test status
Simulation time 575043043 ps
CPU time 13.64 seconds
Started Mar 17 02:44:35 PM PDT 24
Finished Mar 17 02:44:49 PM PDT 24
Peak memory 218864 kb
Host smart-86821c78-58ea-4ee9-82dc-091963f2809f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856040065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.3856040065
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.188418736
Short name T643
Test name
Test status
Simulation time 251336841 ps
CPU time 3.06 seconds
Started Mar 17 02:44:37 PM PDT 24
Finished Mar 17 02:44:41 PM PDT 24
Peak memory 210308 kb
Host smart-6d8518b5-356d-4e41-8dad-8d30e9532249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=188418736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.188418736
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.2148956539
Short name T462
Test name
Test status
Simulation time 8281731 ps
CPU time 0.75 seconds
Started Mar 17 02:44:38 PM PDT 24
Finished Mar 17 02:44:38 PM PDT 24
Peak memory 206428 kb
Host smart-7de2de00-fe8e-4183-afbd-b81fa0ca9335
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148956539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.2148956539
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.1989818177
Short name T858
Test name
Test status
Simulation time 167513591 ps
CPU time 3.29 seconds
Started Mar 17 02:44:42 PM PDT 24
Finished Mar 17 02:44:46 PM PDT 24
Peak memory 209444 kb
Host smart-ce961394-e6af-4cec-ad92-ba3e5a746084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1989818177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.1989818177
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.138223401
Short name T765
Test name
Test status
Simulation time 121162039 ps
CPU time 3.91 seconds
Started Mar 17 02:44:37 PM PDT 24
Finished Mar 17 02:44:42 PM PDT 24
Peak memory 209380 kb
Host smart-851e8616-9c83-49bf-8459-cbc3f80c0237
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138223401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.138223401
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.3055828049
Short name T95
Test name
Test status
Simulation time 268465716 ps
CPU time 6.25 seconds
Started Mar 17 02:44:37 PM PDT 24
Finished Mar 17 02:44:44 PM PDT 24
Peak memory 214796 kb
Host smart-44dd808c-6442-4850-8e7e-398c1b646711
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3055828049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.3055828049
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.536440955
Short name T45
Test name
Test status
Simulation time 148964483 ps
CPU time 3.95 seconds
Started Mar 17 02:44:40 PM PDT 24
Finished Mar 17 02:44:44 PM PDT 24
Peak memory 222904 kb
Host smart-49c2758f-cf96-4666-9bb3-1a92111f1249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536440955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.536440955
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.802000882
Short name T726
Test name
Test status
Simulation time 271503145 ps
CPU time 5.08 seconds
Started Mar 17 02:44:39 PM PDT 24
Finished Mar 17 02:44:45 PM PDT 24
Peak memory 208644 kb
Host smart-4c3b922f-09d1-450d-8a9c-bbabd31e86b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=802000882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.802000882
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.2578343221
Short name T757
Test name
Test status
Simulation time 111016471 ps
CPU time 3.88 seconds
Started Mar 17 02:44:41 PM PDT 24
Finished Mar 17 02:44:45 PM PDT 24
Peak memory 208904 kb
Host smart-c2105735-6529-49de-a76e-6326b540211b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578343221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.2578343221
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.1153296660
Short name T712
Test name
Test status
Simulation time 2916339306 ps
CPU time 13.82 seconds
Started Mar 17 02:44:37 PM PDT 24
Finished Mar 17 02:44:51 PM PDT 24
Peak memory 208276 kb
Host smart-aba4f3c7-9673-4e09-a3bf-3542556b35b6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153296660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.1153296660
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.4079804180
Short name T219
Test name
Test status
Simulation time 7295774902 ps
CPU time 77.18 seconds
Started Mar 17 02:44:38 PM PDT 24
Finished Mar 17 02:45:56 PM PDT 24
Peak memory 209200 kb
Host smart-eeb1404d-93db-480f-a393-d7a617590f01
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4079804180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.4079804180
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.3187337916
Short name T558
Test name
Test status
Simulation time 249172798 ps
CPU time 4.08 seconds
Started Mar 17 02:44:42 PM PDT 24
Finished Mar 17 02:44:47 PM PDT 24
Peak memory 208816 kb
Host smart-8f085a0d-63ed-4371-bb06-fd755eb7fc62
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3187337916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.3187337916
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.3046683612
Short name T801
Test name
Test status
Simulation time 144395094 ps
CPU time 4.98 seconds
Started Mar 17 02:44:43 PM PDT 24
Finished Mar 17 02:44:49 PM PDT 24
Peak memory 216188 kb
Host smart-a19705e8-59df-445f-8a6a-e429ce50ef79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3046683612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.3046683612
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.1726780202
Short name T661
Test name
Test status
Simulation time 150293217 ps
CPU time 3.43 seconds
Started Mar 17 02:44:40 PM PDT 24
Finished Mar 17 02:44:44 PM PDT 24
Peak memory 208988 kb
Host smart-843e13ab-2625-400d-9a6f-41b5a35d1d3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1726780202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.1726780202
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.1044225945
Short name T735
Test name
Test status
Simulation time 2921592550 ps
CPU time 39.47 seconds
Started Mar 17 02:44:41 PM PDT 24
Finished Mar 17 02:45:21 PM PDT 24
Peak memory 223076 kb
Host smart-1e1417e0-a465-44a7-9e27-faf9b06cc185
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1044225945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.1044225945
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.21103608
Short name T683
Test name
Test status
Simulation time 56292058 ps
CPU time 3.85 seconds
Started Mar 17 02:44:40 PM PDT 24
Finished Mar 17 02:44:44 PM PDT 24
Peak memory 210752 kb
Host smart-316f96b4-ab86-4274-b42a-922f9dd4c12d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=21103608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.21103608
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.1753798904
Short name T720
Test name
Test status
Simulation time 1173449093 ps
CPU time 2.91 seconds
Started Mar 17 02:44:42 PM PDT 24
Finished Mar 17 02:44:45 PM PDT 24
Peak memory 210184 kb
Host smart-b61293c7-57cc-4fec-93e2-b6344bb2f2b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1753798904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.1753798904
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.3516530472
Short name T83
Test name
Test status
Simulation time 14666300 ps
CPU time 0.74 seconds
Started Mar 17 02:44:44 PM PDT 24
Finished Mar 17 02:44:46 PM PDT 24
Peak memory 206412 kb
Host smart-888a1115-c196-4a4d-af21-6ec9a69abc5d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516530472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.3516530472
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.2461285878
Short name T410
Test name
Test status
Simulation time 2666584739 ps
CPU time 139.53 seconds
Started Mar 17 02:44:37 PM PDT 24
Finished Mar 17 02:46:57 PM PDT 24
Peak memory 223048 kb
Host smart-bcdf8309-5db0-4b2f-a6c9-cb0cd637e070
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2461285878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.2461285878
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.1733806457
Short name T583
Test name
Test status
Simulation time 176919580 ps
CPU time 2.75 seconds
Started Mar 17 02:44:49 PM PDT 24
Finished Mar 17 02:44:52 PM PDT 24
Peak memory 218840 kb
Host smart-1dd88026-0b39-4100-8eb9-cf874e638963
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1733806457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.1733806457
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.2994316440
Short name T519
Test name
Test status
Simulation time 55758924 ps
CPU time 3 seconds
Started Mar 17 02:44:46 PM PDT 24
Finished Mar 17 02:44:49 PM PDT 24
Peak memory 209664 kb
Host smart-3442a3a8-9f74-48ae-ae85-199ff311ea77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994316440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.2994316440
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.109416805
Short name T836
Test name
Test status
Simulation time 1137717749 ps
CPU time 6.57 seconds
Started Mar 17 02:44:45 PM PDT 24
Finished Mar 17 02:44:52 PM PDT 24
Peak memory 209768 kb
Host smart-55ba53e2-3d25-42ad-bcaf-cb345bd0e801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=109416805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.109416805
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.2374265127
Short name T273
Test name
Test status
Simulation time 2488585132 ps
CPU time 11.44 seconds
Started Mar 17 02:44:43 PM PDT 24
Finished Mar 17 02:44:56 PM PDT 24
Peak memory 222968 kb
Host smart-98d584c9-a852-42ea-bf4e-5fbf62d1a838
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374265127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.2374265127
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.816396941
Short name T523
Test name
Test status
Simulation time 481061184 ps
CPU time 4.33 seconds
Started Mar 17 02:44:44 PM PDT 24
Finished Mar 17 02:44:49 PM PDT 24
Peak memory 209928 kb
Host smart-f2b1aa15-86db-4ccb-ba2c-c5eced50ee9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816396941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.816396941
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.158909232
Short name T878
Test name
Test status
Simulation time 72802747 ps
CPU time 3.05 seconds
Started Mar 17 02:44:40 PM PDT 24
Finished Mar 17 02:44:44 PM PDT 24
Peak memory 214776 kb
Host smart-cd8ceba6-182c-453b-b852-e7df1ede6d28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158909232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.158909232
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.737854115
Short name T578
Test name
Test status
Simulation time 862124651 ps
CPU time 2.57 seconds
Started Mar 17 02:44:40 PM PDT 24
Finished Mar 17 02:44:43 PM PDT 24
Peak memory 208428 kb
Host smart-4099909e-b146-4cd0-9f0a-0000c94a4299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737854115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.737854115
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.2534134655
Short name T575
Test name
Test status
Simulation time 39886837 ps
CPU time 1.89 seconds
Started Mar 17 02:44:41 PM PDT 24
Finished Mar 17 02:44:43 PM PDT 24
Peak memory 207176 kb
Host smart-75de92df-50ed-4c86-9583-c4faf9e6e340
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2534134655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.2534134655
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.990555647
Short name T899
Test name
Test status
Simulation time 56517727 ps
CPU time 3.01 seconds
Started Mar 17 02:44:40 PM PDT 24
Finished Mar 17 02:44:43 PM PDT 24
Peak memory 207156 kb
Host smart-f7cf8a63-d0fe-4bbf-820b-12e09bf7a7a8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=990555647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.990555647
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.2260534251
Short name T763
Test name
Test status
Simulation time 51238070 ps
CPU time 2.4 seconds
Started Mar 17 02:44:42 PM PDT 24
Finished Mar 17 02:44:45 PM PDT 24
Peak memory 207172 kb
Host smart-22e7ddfd-8a64-4924-8ee3-9cf76e7a9564
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2260534251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.2260534251
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.3026883751
Short name T461
Test name
Test status
Simulation time 1621257749 ps
CPU time 13.97 seconds
Started Mar 17 02:44:46 PM PDT 24
Finished Mar 17 02:45:00 PM PDT 24
Peak memory 208524 kb
Host smart-f18f5113-e03d-4d2d-9913-b3819a1f5160
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3026883751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.3026883751
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.1401515943
Short name T663
Test name
Test status
Simulation time 48059750 ps
CPU time 2.69 seconds
Started Mar 17 02:44:37 PM PDT 24
Finished Mar 17 02:44:40 PM PDT 24
Peak memory 207304 kb
Host smart-6e550ecf-659c-449f-b7af-009c3bbc1af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1401515943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.1401515943
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.243667859
Short name T470
Test name
Test status
Simulation time 178485437 ps
CPU time 5.76 seconds
Started Mar 17 02:44:44 PM PDT 24
Finished Mar 17 02:44:51 PM PDT 24
Peak memory 207664 kb
Host smart-e4c65eaf-4855-4efa-adca-c0ea28c44ff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=243667859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.243667859
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.2267617633
Short name T784
Test name
Test status
Simulation time 36249742 ps
CPU time 1.85 seconds
Started Mar 17 02:44:46 PM PDT 24
Finished Mar 17 02:44:48 PM PDT 24
Peak memory 210076 kb
Host smart-700bd0ea-3ebf-415b-9628-109f5a70578a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267617633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.2267617633
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.134210586
Short name T830
Test name
Test status
Simulation time 49284612 ps
CPU time 0.77 seconds
Started Mar 17 02:44:42 PM PDT 24
Finished Mar 17 02:44:44 PM PDT 24
Peak memory 206436 kb
Host smart-98d66849-e35c-48cd-a31f-7a6350041b93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134210586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.134210586
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.4044138947
Short name T422
Test name
Test status
Simulation time 217641676 ps
CPU time 11.67 seconds
Started Mar 17 02:44:46 PM PDT 24
Finished Mar 17 02:44:58 PM PDT 24
Peak memory 216120 kb
Host smart-055b32ad-73b5-4352-aff0-c978c753c7fb
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4044138947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.4044138947
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.2774503874
Short name T399
Test name
Test status
Simulation time 86388684 ps
CPU time 3.89 seconds
Started Mar 17 02:44:44 PM PDT 24
Finished Mar 17 02:44:49 PM PDT 24
Peak memory 223296 kb
Host smart-f03779f4-93dc-4a9a-8329-f208776f5057
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774503874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.2774503874
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.2543833651
Short name T47
Test name
Test status
Simulation time 172598529 ps
CPU time 2.37 seconds
Started Mar 17 02:44:42 PM PDT 24
Finished Mar 17 02:44:45 PM PDT 24
Peak memory 210276 kb
Host smart-14dea7ca-f2bc-4c11-b770-629a7e20e3fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2543833651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.2543833651
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.612020789
Short name T104
Test name
Test status
Simulation time 145039446 ps
CPU time 4.77 seconds
Started Mar 17 02:44:42 PM PDT 24
Finished Mar 17 02:44:48 PM PDT 24
Peak memory 209656 kb
Host smart-d43e2b31-de3a-4505-a6e9-7a92607dbf2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612020789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.612020789
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.3742449025
Short name T272
Test name
Test status
Simulation time 2779764766 ps
CPU time 30.42 seconds
Started Mar 17 02:44:45 PM PDT 24
Finished Mar 17 02:45:17 PM PDT 24
Peak memory 222956 kb
Host smart-c072108c-8c93-4444-89b8-052cb63ce8dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742449025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.3742449025
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.2432671046
Short name T514
Test name
Test status
Simulation time 1211783983 ps
CPU time 4.54 seconds
Started Mar 17 02:44:45 PM PDT 24
Finished Mar 17 02:44:51 PM PDT 24
Peak memory 211056 kb
Host smart-4ee45ae9-fa79-4398-bcec-f262195def8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2432671046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.2432671046
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.4228135134
Short name T716
Test name
Test status
Simulation time 401368442 ps
CPU time 4.4 seconds
Started Mar 17 02:44:46 PM PDT 24
Finished Mar 17 02:44:51 PM PDT 24
Peak memory 207332 kb
Host smart-937e6bee-40f5-408a-b4c0-981067826148
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228135134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.4228135134
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.3788315730
Short name T850
Test name
Test status
Simulation time 25906903 ps
CPU time 2.13 seconds
Started Mar 17 02:44:43 PM PDT 24
Finished Mar 17 02:44:46 PM PDT 24
Peak memory 208824 kb
Host smart-4a31da76-a441-4b71-a1e4-92685fdca8cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3788315730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.3788315730
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.977946435
Short name T495
Test name
Test status
Simulation time 131514707 ps
CPU time 5.49 seconds
Started Mar 17 02:44:46 PM PDT 24
Finished Mar 17 02:44:52 PM PDT 24
Peak memory 208912 kb
Host smart-69ce1277-7627-4dd4-a7e1-91a1df313903
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977946435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.977946435
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.3606971469
Short name T766
Test name
Test status
Simulation time 625321788 ps
CPU time 5.41 seconds
Started Mar 17 02:44:47 PM PDT 24
Finished Mar 17 02:44:52 PM PDT 24
Peak memory 208308 kb
Host smart-bc2c9f9a-d7e1-4f4a-a553-dba0fe074dd9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3606971469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.3606971469
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.3772097327
Short name T650
Test name
Test status
Simulation time 3405888297 ps
CPU time 38.58 seconds
Started Mar 17 02:44:48 PM PDT 24
Finished Mar 17 02:45:26 PM PDT 24
Peak memory 209060 kb
Host smart-ba3764bb-ab56-4c5a-9e32-de31f576db94
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3772097327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.3772097327
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.3453094056
Short name T244
Test name
Test status
Simulation time 1292915427 ps
CPU time 8.44 seconds
Started Mar 17 02:44:49 PM PDT 24
Finished Mar 17 02:44:57 PM PDT 24
Peak memory 209632 kb
Host smart-9ee19601-b377-4e30-9794-706e313dbc46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453094056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.3453094056
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.2391461625
Short name T645
Test name
Test status
Simulation time 1415076014 ps
CPU time 32.4 seconds
Started Mar 17 02:44:46 PM PDT 24
Finished Mar 17 02:45:19 PM PDT 24
Peak memory 208720 kb
Host smart-f0416139-dfd7-4500-9186-26b71b56a136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391461625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.2391461625
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.218368113
Short name T833
Test name
Test status
Simulation time 172899333 ps
CPU time 5.78 seconds
Started Mar 17 02:44:49 PM PDT 24
Finished Mar 17 02:44:55 PM PDT 24
Peak memory 209144 kb
Host smart-9fd81708-bbc7-46d4-9717-bfa46b18e2ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=218368113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.218368113
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.2410506190
Short name T813
Test name
Test status
Simulation time 75202727 ps
CPU time 2.43 seconds
Started Mar 17 02:44:44 PM PDT 24
Finished Mar 17 02:44:47 PM PDT 24
Peak memory 210272 kb
Host smart-39a73ce8-6412-4746-a291-93ff7be511bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410506190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.2410506190
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.3234190027
Short name T596
Test name
Test status
Simulation time 28869437 ps
CPU time 0.77 seconds
Started Mar 17 02:44:50 PM PDT 24
Finished Mar 17 02:44:51 PM PDT 24
Peak memory 206424 kb
Host smart-65b90d39-59b3-4748-8a6c-04fdda9bcc81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234190027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.3234190027
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.564588074
Short name T134
Test name
Test status
Simulation time 109851753 ps
CPU time 2.71 seconds
Started Mar 17 02:44:49 PM PDT 24
Finished Mar 17 02:44:52 PM PDT 24
Peak memory 214744 kb
Host smart-d6843778-6252-4e9b-b6f5-2c06d77481d5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=564588074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.564588074
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.2364923444
Short name T20
Test name
Test status
Simulation time 226320012 ps
CPU time 3.32 seconds
Started Mar 17 02:44:49 PM PDT 24
Finished Mar 17 02:44:52 PM PDT 24
Peak memory 210244 kb
Host smart-ccc40944-0567-4889-8e06-1e85ff5a33a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2364923444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.2364923444
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.2772577333
Short name T621
Test name
Test status
Simulation time 1953775925 ps
CPU time 4.94 seconds
Started Mar 17 02:44:53 PM PDT 24
Finished Mar 17 02:44:58 PM PDT 24
Peak memory 209024 kb
Host smart-898b1f75-38e7-44c5-9328-dd04e9832717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772577333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.2772577333
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.3060660173
Short name T87
Test name
Test status
Simulation time 110396983 ps
CPU time 5.06 seconds
Started Mar 17 02:44:53 PM PDT 24
Finished Mar 17 02:44:58 PM PDT 24
Peak memory 214732 kb
Host smart-5ebe1876-f73b-414f-b7e3-a4909c06f0a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060660173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.3060660173
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.3183564258
Short name T301
Test name
Test status
Simulation time 505325463 ps
CPU time 6.03 seconds
Started Mar 17 02:44:54 PM PDT 24
Finished Mar 17 02:45:01 PM PDT 24
Peak memory 222860 kb
Host smart-5586d600-211e-4e5c-af05-01b4963fa472
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183564258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.3183564258
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.2985150019
Short name T44
Test name
Test status
Simulation time 76289921 ps
CPU time 2.79 seconds
Started Mar 17 02:44:54 PM PDT 24
Finished Mar 17 02:44:57 PM PDT 24
Peak memory 215312 kb
Host smart-84c961a4-93b4-4367-a634-821fd1414d32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985150019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.2985150019
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.278500454
Short name T792
Test name
Test status
Simulation time 376898515 ps
CPU time 3.88 seconds
Started Mar 17 02:44:49 PM PDT 24
Finished Mar 17 02:44:53 PM PDT 24
Peak memory 207476 kb
Host smart-d3538640-9f87-43a4-9736-eeeb5a5bbee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=278500454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.278500454
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.1371846296
Short name T753
Test name
Test status
Simulation time 1409357896 ps
CPU time 4.4 seconds
Started Mar 17 02:44:45 PM PDT 24
Finished Mar 17 02:44:51 PM PDT 24
Peak memory 206484 kb
Host smart-b592951b-df66-4b9b-a24b-55ff53eaca1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371846296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.1371846296
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.2760130381
Short name T472
Test name
Test status
Simulation time 71885595 ps
CPU time 3.26 seconds
Started Mar 17 02:44:47 PM PDT 24
Finished Mar 17 02:44:51 PM PDT 24
Peak memory 207312 kb
Host smart-8aca3efd-2632-4f3c-b541-b5e9ca9bee20
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760130381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.2760130381
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.74178863
Short name T890
Test name
Test status
Simulation time 227173770 ps
CPU time 6.19 seconds
Started Mar 17 02:44:43 PM PDT 24
Finished Mar 17 02:44:50 PM PDT 24
Peak memory 208432 kb
Host smart-a1ac1874-d916-460b-8eac-11336a212450
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74178863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.74178863
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.1814020082
Short name T504
Test name
Test status
Simulation time 836378831 ps
CPU time 22.25 seconds
Started Mar 17 02:44:52 PM PDT 24
Finished Mar 17 02:45:15 PM PDT 24
Peak memory 208368 kb
Host smart-34e6ab7d-84c0-4463-a153-ecea09b271c0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1814020082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.1814020082
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.1541387715
Short name T639
Test name
Test status
Simulation time 115269221 ps
CPU time 2.25 seconds
Started Mar 17 02:44:50 PM PDT 24
Finished Mar 17 02:44:52 PM PDT 24
Peak memory 216144 kb
Host smart-412ab00a-5d93-461b-9387-0b3405b72508
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1541387715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.1541387715
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.1457636086
Short name T762
Test name
Test status
Simulation time 134246168 ps
CPU time 2.5 seconds
Started Mar 17 02:44:45 PM PDT 24
Finished Mar 17 02:44:49 PM PDT 24
Peak memory 207692 kb
Host smart-34a1d5a7-2272-41aa-9f47-7f23e918d8f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457636086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.1457636086
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.828727858
Short name T658
Test name
Test status
Simulation time 3372910218 ps
CPU time 36.79 seconds
Started Mar 17 02:44:56 PM PDT 24
Finished Mar 17 02:45:33 PM PDT 24
Peak memory 215948 kb
Host smart-c21f91da-6cfb-45c0-b13b-c525683b75f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=828727858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.828727858
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.3497841271
Short name T854
Test name
Test status
Simulation time 134812128 ps
CPU time 5.43 seconds
Started Mar 17 02:44:56 PM PDT 24
Finished Mar 17 02:45:01 PM PDT 24
Peak memory 208388 kb
Host smart-af176957-d0d4-4402-8497-a01aa0a74e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3497841271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.3497841271
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.2069143904
Short name T385
Test name
Test status
Simulation time 111308747 ps
CPU time 3.82 seconds
Started Mar 17 02:44:55 PM PDT 24
Finished Mar 17 02:44:59 PM PDT 24
Peak memory 210576 kb
Host smart-21c3b46c-2cdf-4548-891f-7c5406d052cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2069143904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.2069143904
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.4132266673
Short name T619
Test name
Test status
Simulation time 12594515 ps
CPU time 0.77 seconds
Started Mar 17 02:44:54 PM PDT 24
Finished Mar 17 02:44:55 PM PDT 24
Peak memory 206460 kb
Host smart-84a59640-be22-4c06-93a2-62708ffbdcf6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4132266673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.4132266673
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.3214158945
Short name T861
Test name
Test status
Simulation time 373619619 ps
CPU time 2.9 seconds
Started Mar 17 02:44:53 PM PDT 24
Finished Mar 17 02:44:56 PM PDT 24
Peak memory 208928 kb
Host smart-d913083e-f528-47c7-aba4-022505eb847f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3214158945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.3214158945
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.1781877065
Short name T545
Test name
Test status
Simulation time 778924649 ps
CPU time 7.63 seconds
Started Mar 17 02:44:50 PM PDT 24
Finished Mar 17 02:44:58 PM PDT 24
Peak memory 214772 kb
Host smart-f133976e-d91f-4bfc-ab60-29517448da0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781877065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.1781877065
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.3419200020
Short name T251
Test name
Test status
Simulation time 127535362 ps
CPU time 5.92 seconds
Started Mar 17 02:44:49 PM PDT 24
Finished Mar 17 02:44:55 PM PDT 24
Peak memory 222852 kb
Host smart-595f9c61-ed48-42fd-b006-834ace70a8ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419200020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.3419200020
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.12502164
Short name T706
Test name
Test status
Simulation time 489577033 ps
CPU time 2.63 seconds
Started Mar 17 02:44:51 PM PDT 24
Finished Mar 17 02:44:53 PM PDT 24
Peak memory 214832 kb
Host smart-d3116405-13b1-4b56-aa7e-8e76e3c7aa5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=12502164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.12502164
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.2349505253
Short name T524
Test name
Test status
Simulation time 144147908 ps
CPU time 6.65 seconds
Started Mar 17 02:44:55 PM PDT 24
Finished Mar 17 02:45:02 PM PDT 24
Peak memory 210156 kb
Host smart-825bebac-15a4-4941-888d-e5c43ece78d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349505253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.2349505253
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.3162455868
Short name T443
Test name
Test status
Simulation time 58750653 ps
CPU time 2.85 seconds
Started Mar 17 02:44:49 PM PDT 24
Finished Mar 17 02:44:52 PM PDT 24
Peak memory 207160 kb
Host smart-cbfca016-4dac-4835-9dcc-8e7c87f93fe2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3162455868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.3162455868
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.1910550629
Short name T707
Test name
Test status
Simulation time 371767464 ps
CPU time 4.56 seconds
Started Mar 17 02:44:54 PM PDT 24
Finished Mar 17 02:44:59 PM PDT 24
Peak memory 209012 kb
Host smart-942863fa-0147-4e2b-9a29-2e5ca8bb4854
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910550629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.1910550629
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.4104322242
Short name T688
Test name
Test status
Simulation time 751879247 ps
CPU time 6.31 seconds
Started Mar 17 02:44:50 PM PDT 24
Finished Mar 17 02:44:57 PM PDT 24
Peak memory 208252 kb
Host smart-176e522c-3ec8-45e0-8f66-a0c3b29cb558
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4104322242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.4104322242
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.557541361
Short name T750
Test name
Test status
Simulation time 223726416 ps
CPU time 3.01 seconds
Started Mar 17 02:44:50 PM PDT 24
Finished Mar 17 02:44:53 PM PDT 24
Peak memory 207708 kb
Host smart-fb56f499-bde1-4696-a047-29241763f069
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=557541361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.557541361
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.3109672658
Short name T622
Test name
Test status
Simulation time 635783443 ps
CPU time 18.3 seconds
Started Mar 17 02:44:49 PM PDT 24
Finished Mar 17 02:45:07 PM PDT 24
Peak memory 209856 kb
Host smart-d5ef7825-8c5c-4718-9039-11b2f9a60db0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109672658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.3109672658
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.2270289694
Short name T544
Test name
Test status
Simulation time 47993448 ps
CPU time 2.12 seconds
Started Mar 17 02:44:51 PM PDT 24
Finished Mar 17 02:44:53 PM PDT 24
Peak memory 207456 kb
Host smart-e8119a93-bb29-444d-b29c-fc62fb9a7e1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270289694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.2270289694
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.342461506
Short name T225
Test name
Test status
Simulation time 1733584516 ps
CPU time 20.99 seconds
Started Mar 17 02:44:54 PM PDT 24
Finished Mar 17 02:45:15 PM PDT 24
Peak memory 220320 kb
Host smart-66d1f5b9-ccda-4cc8-8770-4d37d6789936
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=342461506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.342461506
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.3673918064
Short name T666
Test name
Test status
Simulation time 1623575346 ps
CPU time 12.59 seconds
Started Mar 17 02:44:50 PM PDT 24
Finished Mar 17 02:45:03 PM PDT 24
Peak memory 208560 kb
Host smart-dbe0997b-6cc4-4b9c-8113-7da72736c05b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673918064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.3673918064
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.3510092440
Short name T483
Test name
Test status
Simulation time 65372719 ps
CPU time 1.94 seconds
Started Mar 17 02:44:49 PM PDT 24
Finished Mar 17 02:44:51 PM PDT 24
Peak memory 210404 kb
Host smart-426d976d-77ea-4da3-914e-3d912fb76ae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510092440 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.3510092440
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.134270726
Short name T657
Test name
Test status
Simulation time 14026434 ps
CPU time 0.95 seconds
Started Mar 17 02:42:47 PM PDT 24
Finished Mar 17 02:42:48 PM PDT 24
Peak memory 206632 kb
Host smart-d31877e7-7c29-4bb4-a4da-292e1732cc81
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134270726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.134270726
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.4009222843
Short name T415
Test name
Test status
Simulation time 186086570 ps
CPU time 9.66 seconds
Started Mar 17 02:42:45 PM PDT 24
Finished Mar 17 02:42:55 PM PDT 24
Peak memory 214812 kb
Host smart-3e3ac77d-20b7-4952-bfef-1e4f3623b22c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4009222843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.4009222843
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.1724621133
Short name T565
Test name
Test status
Simulation time 81086082 ps
CPU time 5.25 seconds
Started Mar 17 02:42:45 PM PDT 24
Finished Mar 17 02:42:51 PM PDT 24
Peak memory 211236 kb
Host smart-f5e62571-68a1-48ad-8f47-4e460cbf0823
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1724621133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.1724621133
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.2639643713
Short name T548
Test name
Test status
Simulation time 223755163 ps
CPU time 2.05 seconds
Started Mar 17 02:42:45 PM PDT 24
Finished Mar 17 02:42:47 PM PDT 24
Peak memory 209592 kb
Host smart-027614a0-021c-48c8-8fbf-80f46a069dc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639643713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.2639643713
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.1550073599
Short name T787
Test name
Test status
Simulation time 617731497 ps
CPU time 6.17 seconds
Started Mar 17 02:42:44 PM PDT 24
Finished Mar 17 02:42:51 PM PDT 24
Peak memory 214680 kb
Host smart-cb5c134b-11fc-4203-95b8-e696d2fb26ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550073599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.1550073599
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.744806167
Short name T771
Test name
Test status
Simulation time 89336203 ps
CPU time 1.72 seconds
Started Mar 17 02:42:43 PM PDT 24
Finished Mar 17 02:42:45 PM PDT 24
Peak memory 206588 kb
Host smart-9812e2d1-ba84-4023-aaf1-28fc4f72a512
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744806167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.744806167
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.2745218209
Short name T835
Test name
Test status
Simulation time 66337462 ps
CPU time 4.05 seconds
Started Mar 17 02:42:48 PM PDT 24
Finished Mar 17 02:42:52 PM PDT 24
Peak memory 209764 kb
Host smart-af85f48e-f4fc-4ca9-bac6-74f353accacb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2745218209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.2745218209
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.3782180746
Short name T102
Test name
Test status
Simulation time 2353834344 ps
CPU time 19.11 seconds
Started Mar 17 02:42:47 PM PDT 24
Finished Mar 17 02:43:07 PM PDT 24
Peak memory 240704 kb
Host smart-86955016-b01e-445d-97ea-16ae15527cf9
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3782180746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.3782180746
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.3733090421
Short name T440
Test name
Test status
Simulation time 4120864595 ps
CPU time 29.3 seconds
Started Mar 17 02:42:45 PM PDT 24
Finished Mar 17 02:43:14 PM PDT 24
Peak memory 208496 kb
Host smart-f3546b60-7494-49ef-8935-8b8840626faa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733090421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.3733090421
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.360330659
Short name T893
Test name
Test status
Simulation time 111612540 ps
CPU time 2.32 seconds
Started Mar 17 02:42:47 PM PDT 24
Finished Mar 17 02:42:50 PM PDT 24
Peak memory 207240 kb
Host smart-1d7245cd-4e6a-4da0-a1bd-cd8f61113365
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=360330659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.360330659
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.841179166
Short name T883
Test name
Test status
Simulation time 36891215 ps
CPU time 2.46 seconds
Started Mar 17 02:42:44 PM PDT 24
Finished Mar 17 02:42:47 PM PDT 24
Peak memory 207104 kb
Host smart-db3c9040-aa90-4be7-a6d4-a06befcc051e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=841179166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.841179166
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.4064362239
Short name T871
Test name
Test status
Simulation time 45012856 ps
CPU time 2.74 seconds
Started Mar 17 02:42:48 PM PDT 24
Finished Mar 17 02:42:51 PM PDT 24
Peak memory 208920 kb
Host smart-8532afbb-9c84-4154-a8a1-837f37a2155c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4064362239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.4064362239
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.274739788
Short name T797
Test name
Test status
Simulation time 101801144 ps
CPU time 2.75 seconds
Started Mar 17 02:42:45 PM PDT 24
Finished Mar 17 02:42:48 PM PDT 24
Peak memory 209276 kb
Host smart-ac4c31dc-d6ea-48ca-8723-f9465436ef9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274739788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.274739788
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.1147389536
Short name T561
Test name
Test status
Simulation time 985296911 ps
CPU time 10.17 seconds
Started Mar 17 02:42:45 PM PDT 24
Finished Mar 17 02:42:55 PM PDT 24
Peak memory 208972 kb
Host smart-08fccb14-397c-49ef-9435-3a4260327f80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1147389536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.1147389536
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.3773929244
Short name T632
Test name
Test status
Simulation time 109478222 ps
CPU time 3.72 seconds
Started Mar 17 02:42:45 PM PDT 24
Finished Mar 17 02:42:49 PM PDT 24
Peak memory 208412 kb
Host smart-8c997da1-f76e-48f4-a044-26cd0626ddbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773929244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.3773929244
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.3573411570
Short name T659
Test name
Test status
Simulation time 191096030 ps
CPU time 2.15 seconds
Started Mar 17 02:42:43 PM PDT 24
Finished Mar 17 02:42:45 PM PDT 24
Peak memory 210352 kb
Host smart-9d2c45c0-e9c8-4cc3-9fa7-601c4c0aea42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573411570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.3573411570
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.602211758
Short name T98
Test name
Test status
Simulation time 189088566 ps
CPU time 0.86 seconds
Started Mar 17 02:44:56 PM PDT 24
Finished Mar 17 02:44:57 PM PDT 24
Peak memory 206320 kb
Host smart-b4d11962-22c0-4e8d-81bb-0458a924aafa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=602211758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.602211758
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.82024511
Short name T319
Test name
Test status
Simulation time 9190339368 ps
CPU time 91.28 seconds
Started Mar 17 02:44:51 PM PDT 24
Finished Mar 17 02:46:23 PM PDT 24
Peak memory 218300 kb
Host smart-2383bea4-6d80-4d8c-b3f1-3798df3d763e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=82024511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.82024511
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.2536761470
Short name T31
Test name
Test status
Simulation time 118359664 ps
CPU time 2.04 seconds
Started Mar 17 02:44:50 PM PDT 24
Finished Mar 17 02:44:52 PM PDT 24
Peak memory 209420 kb
Host smart-b1b69357-a48c-4a10-85f8-8fb968b42a98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2536761470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.2536761470
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.2135270156
Short name T655
Test name
Test status
Simulation time 37005923 ps
CPU time 1.72 seconds
Started Mar 17 02:44:49 PM PDT 24
Finished Mar 17 02:44:51 PM PDT 24
Peak memory 208648 kb
Host smart-33d5d616-3632-44da-b237-0db1b7b2b4e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135270156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.2135270156
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.1958752418
Short name T358
Test name
Test status
Simulation time 95491935 ps
CPU time 4.57 seconds
Started Mar 17 02:44:54 PM PDT 24
Finished Mar 17 02:44:59 PM PDT 24
Peak memory 219372 kb
Host smart-1ebfad71-99b4-41ad-9fe0-45860b70425a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1958752418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.1958752418
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.1815772941
Short name T250
Test name
Test status
Simulation time 325147410 ps
CPU time 9.94 seconds
Started Mar 17 02:44:51 PM PDT 24
Finished Mar 17 02:45:01 PM PDT 24
Peak memory 222872 kb
Host smart-bfc36d1d-f6a0-42c2-a8bb-6dc7fc1c8e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1815772941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.1815772941
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.1006287365
Short name T221
Test name
Test status
Simulation time 240049265 ps
CPU time 2.69 seconds
Started Mar 17 02:44:54 PM PDT 24
Finished Mar 17 02:44:57 PM PDT 24
Peak memory 214756 kb
Host smart-9a536e66-325e-46bd-9b57-781d14fee3b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006287365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.1006287365
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.2049339613
Short name T647
Test name
Test status
Simulation time 374247973 ps
CPU time 6.45 seconds
Started Mar 17 02:44:56 PM PDT 24
Finished Mar 17 02:45:02 PM PDT 24
Peak memory 209040 kb
Host smart-0856070d-9f6a-4052-8cff-50a86f63fa27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2049339613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.2049339613
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.1429110889
Short name T669
Test name
Test status
Simulation time 1046906337 ps
CPU time 26.35 seconds
Started Mar 17 02:44:56 PM PDT 24
Finished Mar 17 02:45:22 PM PDT 24
Peak memory 208564 kb
Host smart-1b8a1b62-71d9-4e2f-9eef-187481252237
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1429110889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.1429110889
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.167447810
Short name T263
Test name
Test status
Simulation time 2110505612 ps
CPU time 72.95 seconds
Started Mar 17 02:44:54 PM PDT 24
Finished Mar 17 02:46:07 PM PDT 24
Peak memory 209328 kb
Host smart-ef7d9004-632b-45ff-bf86-17f9484c9c38
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167447810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.167447810
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.1519688213
Short name T717
Test name
Test status
Simulation time 188026317 ps
CPU time 3.06 seconds
Started Mar 17 02:44:54 PM PDT 24
Finished Mar 17 02:44:58 PM PDT 24
Peak memory 207732 kb
Host smart-ad4b77b4-38af-4589-aba7-a55e9385f1d1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1519688213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.1519688213
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.254146186
Short name T256
Test name
Test status
Simulation time 530656718 ps
CPU time 4.16 seconds
Started Mar 17 02:44:55 PM PDT 24
Finished Mar 17 02:45:00 PM PDT 24
Peak memory 210276 kb
Host smart-1e48a9ce-cd93-495b-9b73-8a76eb489377
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=254146186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.254146186
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.873701297
Short name T426
Test name
Test status
Simulation time 153813052 ps
CPU time 2.23 seconds
Started Mar 17 02:44:49 PM PDT 24
Finished Mar 17 02:44:52 PM PDT 24
Peak memory 207100 kb
Host smart-ee71631f-580c-484a-abec-9228c56ca8ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873701297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.873701297
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.119875084
Short name T312
Test name
Test status
Simulation time 4005596646 ps
CPU time 61.37 seconds
Started Mar 17 02:45:02 PM PDT 24
Finished Mar 17 02:46:03 PM PDT 24
Peak memory 223108 kb
Host smart-0f18d186-712c-449b-9b08-d628381cf418
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119875084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.119875084
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.2508382688
Short name T468
Test name
Test status
Simulation time 879366170 ps
CPU time 23.66 seconds
Started Mar 17 02:44:53 PM PDT 24
Finished Mar 17 02:45:17 PM PDT 24
Peak memory 209688 kb
Host smart-61b75907-682c-4de7-8394-afeb9c5853d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508382688 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.2508382688
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.988105259
Short name T895
Test name
Test status
Simulation time 34821791 ps
CPU time 2.37 seconds
Started Mar 17 02:44:58 PM PDT 24
Finished Mar 17 02:45:00 PM PDT 24
Peak memory 210380 kb
Host smart-4e139bad-e741-4205-88dc-1d4ad518f21b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988105259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.988105259
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.3181880190
Short name T743
Test name
Test status
Simulation time 7175245 ps
CPU time 0.82 seconds
Started Mar 17 02:44:59 PM PDT 24
Finished Mar 17 02:45:00 PM PDT 24
Peak memory 206388 kb
Host smart-e217a038-ef4e-461b-b644-99de0237976a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181880190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.3181880190
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.3785260244
Short name T407
Test name
Test status
Simulation time 255851379 ps
CPU time 4.24 seconds
Started Mar 17 02:44:56 PM PDT 24
Finished Mar 17 02:45:01 PM PDT 24
Peak memory 215472 kb
Host smart-08845222-f0cb-4441-a598-bcfe95de57c0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3785260244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.3785260244
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.2868948727
Short name T799
Test name
Test status
Simulation time 122680288 ps
CPU time 3.28 seconds
Started Mar 17 02:44:59 PM PDT 24
Finished Mar 17 02:45:02 PM PDT 24
Peak memory 219656 kb
Host smart-a0aec699-d150-42fa-8c80-2a7d77f75484
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2868948727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.2868948727
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.2144783362
Short name T338
Test name
Test status
Simulation time 1844170384 ps
CPU time 5.14 seconds
Started Mar 17 02:44:55 PM PDT 24
Finished Mar 17 02:45:01 PM PDT 24
Peak memory 210348 kb
Host smart-9bd59922-19db-4407-bba2-a3f795ad6235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144783362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.2144783362
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.478815391
Short name T624
Test name
Test status
Simulation time 151035640 ps
CPU time 3.08 seconds
Started Mar 17 02:45:02 PM PDT 24
Finished Mar 17 02:45:05 PM PDT 24
Peak memory 221500 kb
Host smart-c1243234-e64c-4794-858f-229c3df913ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478815391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.478815391
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.2728665763
Short name T346
Test name
Test status
Simulation time 152715475 ps
CPU time 6.7 seconds
Started Mar 17 02:44:54 PM PDT 24
Finished Mar 17 02:45:01 PM PDT 24
Peak memory 214744 kb
Host smart-50b81f45-922d-4b32-8630-3f481e4ca877
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2728665763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.2728665763
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.1251282858
Short name T739
Test name
Test status
Simulation time 86383711 ps
CPU time 4.14 seconds
Started Mar 17 02:44:58 PM PDT 24
Finished Mar 17 02:45:02 PM PDT 24
Peak memory 222888 kb
Host smart-ac2a8ecf-ecb5-4bd1-b78f-3198d2dace4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251282858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.1251282858
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.3564728859
Short name T340
Test name
Test status
Simulation time 1912927001 ps
CPU time 8.52 seconds
Started Mar 17 02:44:56 PM PDT 24
Finished Mar 17 02:45:05 PM PDT 24
Peak memory 208316 kb
Host smart-f42d12a7-9f44-41cc-ae91-9983e853aab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564728859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.3564728859
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.2170859036
Short name T493
Test name
Test status
Simulation time 252472831 ps
CPU time 2.86 seconds
Started Mar 17 02:44:55 PM PDT 24
Finished Mar 17 02:44:59 PM PDT 24
Peak memory 208876 kb
Host smart-6928aa40-5e09-475e-8da6-efa270ff7bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170859036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.2170859036
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.679088304
Short name T105
Test name
Test status
Simulation time 46475281 ps
CPU time 2.2 seconds
Started Mar 17 02:44:57 PM PDT 24
Finished Mar 17 02:45:00 PM PDT 24
Peak memory 209252 kb
Host smart-c1da3da5-c123-4d04-a503-3e03e5321ceb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=679088304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.679088304
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.1323550241
Short name T664
Test name
Test status
Simulation time 101054113 ps
CPU time 2.46 seconds
Started Mar 17 02:44:57 PM PDT 24
Finished Mar 17 02:45:00 PM PDT 24
Peak memory 207660 kb
Host smart-50eb342e-6b5e-435c-9c4b-7e18701f7906
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1323550241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.1323550241
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.1214595182
Short name T503
Test name
Test status
Simulation time 276181572 ps
CPU time 4.52 seconds
Started Mar 17 02:44:57 PM PDT 24
Finished Mar 17 02:45:02 PM PDT 24
Peak memory 208964 kb
Host smart-3ba3507b-2030-4ede-a6fc-cb5c3fc14007
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1214595182 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.1214595182
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.180440131
Short name T617
Test name
Test status
Simulation time 464495259 ps
CPU time 4.33 seconds
Started Mar 17 02:44:58 PM PDT 24
Finished Mar 17 02:45:02 PM PDT 24
Peak memory 216124 kb
Host smart-bd3e45df-5dd0-4812-9084-0509faf4b76d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=180440131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.180440131
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.4195845603
Short name T210
Test name
Test status
Simulation time 87097002 ps
CPU time 3.53 seconds
Started Mar 17 02:44:58 PM PDT 24
Finished Mar 17 02:45:01 PM PDT 24
Peak memory 208876 kb
Host smart-efe1c840-4c28-44db-ae90-3ae1e21f55c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4195845603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.4195845603
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.3932397858
Short name T630
Test name
Test status
Simulation time 42738895 ps
CPU time 2.17 seconds
Started Mar 17 02:44:58 PM PDT 24
Finished Mar 17 02:45:00 PM PDT 24
Peak memory 210556 kb
Host smart-455adb7d-d995-48ae-9d77-69b6ce5216d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932397858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.3932397858
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.3859987312
Short name T838
Test name
Test status
Simulation time 29761501 ps
CPU time 0.83 seconds
Started Mar 17 02:44:59 PM PDT 24
Finished Mar 17 02:45:01 PM PDT 24
Peak memory 206472 kb
Host smart-3670ce3e-6232-467a-86f9-58a0702bb193
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859987312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.3859987312
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.570166739
Short name T351
Test name
Test status
Simulation time 75013119 ps
CPU time 4.43 seconds
Started Mar 17 02:44:57 PM PDT 24
Finished Mar 17 02:45:02 PM PDT 24
Peak memory 215888 kb
Host smart-ea75ab16-0fa4-4997-880a-59f7377c7229
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=570166739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.570166739
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.2995488464
Short name T67
Test name
Test status
Simulation time 36764325 ps
CPU time 1.98 seconds
Started Mar 17 02:45:02 PM PDT 24
Finished Mar 17 02:45:04 PM PDT 24
Peak memory 209044 kb
Host smart-599b36b1-46fa-4739-8da6-99452d7dfbb0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995488464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.2995488464
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.669056426
Short name T311
Test name
Test status
Simulation time 10345460273 ps
CPU time 40.3 seconds
Started Mar 17 02:44:58 PM PDT 24
Finished Mar 17 02:45:38 PM PDT 24
Peak memory 214916 kb
Host smart-b2cb1215-c1a4-4c12-8f33-d9a0f4646db9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669056426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.669056426
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.1341764931
Short name T204
Test name
Test status
Simulation time 345067792 ps
CPU time 5.73 seconds
Started Mar 17 02:44:56 PM PDT 24
Finished Mar 17 02:45:02 PM PDT 24
Peak memory 222128 kb
Host smart-b47bc261-0fb4-4154-9603-7d33a09390a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1341764931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.1341764931
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.853814923
Short name T742
Test name
Test status
Simulation time 129591815 ps
CPU time 4.94 seconds
Started Mar 17 02:44:56 PM PDT 24
Finished Mar 17 02:45:01 PM PDT 24
Peak memory 220744 kb
Host smart-9f80a1c9-15e3-4c07-ba13-21ed592a79f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853814923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.853814923
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.103612311
Short name T755
Test name
Test status
Simulation time 171370855 ps
CPU time 3.17 seconds
Started Mar 17 02:44:57 PM PDT 24
Finished Mar 17 02:45:00 PM PDT 24
Peak memory 218728 kb
Host smart-54f37848-e693-4405-a44d-3bc604b8e9f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103612311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.103612311
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.2260454833
Short name T265
Test name
Test status
Simulation time 2446391775 ps
CPU time 12.46 seconds
Started Mar 17 02:44:58 PM PDT 24
Finished Mar 17 02:45:11 PM PDT 24
Peak memory 207224 kb
Host smart-ddc20e60-2362-41d8-b83a-922cfca930e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2260454833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.2260454833
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.2022880232
Short name T489
Test name
Test status
Simulation time 260819364 ps
CPU time 4.47 seconds
Started Mar 17 02:44:57 PM PDT 24
Finished Mar 17 02:45:02 PM PDT 24
Peak memory 207132 kb
Host smart-3a455bcc-9d68-4bac-bfd7-b75f7f8f4a5a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2022880232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.2022880232
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.4010159797
Short name T513
Test name
Test status
Simulation time 324270143 ps
CPU time 4.28 seconds
Started Mar 17 02:45:03 PM PDT 24
Finished Mar 17 02:45:08 PM PDT 24
Peak memory 208016 kb
Host smart-b5c04ef5-848b-4eb5-a25e-2dcf6b298974
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4010159797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.4010159797
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.824685806
Short name T522
Test name
Test status
Simulation time 55158600 ps
CPU time 2.89 seconds
Started Mar 17 02:44:55 PM PDT 24
Finished Mar 17 02:44:59 PM PDT 24
Peak memory 209144 kb
Host smart-9d961196-abe7-47ef-9eec-dee4ad8e889f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824685806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.824685806
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.3151587684
Short name T285
Test name
Test status
Simulation time 991076653 ps
CPU time 6.54 seconds
Started Mar 17 02:45:00 PM PDT 24
Finished Mar 17 02:45:07 PM PDT 24
Peak memory 210820 kb
Host smart-0ef3705b-c5ad-4bb0-894f-84ce5ae9c279
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3151587684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.3151587684
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.3330358117
Short name T400
Test name
Test status
Simulation time 137021310 ps
CPU time 4.02 seconds
Started Mar 17 02:44:58 PM PDT 24
Finished Mar 17 02:45:03 PM PDT 24
Peak memory 208544 kb
Host smart-2a64fe59-165a-4449-b0fb-54cb6b32773b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3330358117 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.3330358117
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.3499238297
Short name T725
Test name
Test status
Simulation time 847363580 ps
CPU time 35.37 seconds
Started Mar 17 02:45:00 PM PDT 24
Finished Mar 17 02:45:35 PM PDT 24
Peak memory 215516 kb
Host smart-6dbea742-94c5-460c-b98a-9185996c2407
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3499238297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.3499238297
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_stress_all_with_rand_reset.4152545391
Short name T232
Test name
Test status
Simulation time 157793233 ps
CPU time 7.21 seconds
Started Mar 17 02:45:00 PM PDT 24
Finished Mar 17 02:45:07 PM PDT 24
Peak memory 219932 kb
Host smart-43dbb0e8-4c0d-4f0c-9c45-e7d546fe1c48
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4152545391 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all_with_rand_reset.4152545391
Directory /workspace/42.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.2503708227
Short name T736
Test name
Test status
Simulation time 64008103 ps
CPU time 3.74 seconds
Started Mar 17 02:44:57 PM PDT 24
Finished Mar 17 02:45:01 PM PDT 24
Peak memory 214824 kb
Host smart-f6724782-492f-4ddf-80c2-79a834305421
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503708227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.2503708227
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.2944231685
Short name T538
Test name
Test status
Simulation time 217870736 ps
CPU time 4.59 seconds
Started Mar 17 02:45:02 PM PDT 24
Finished Mar 17 02:45:06 PM PDT 24
Peak memory 211188 kb
Host smart-70085500-c3df-408f-902e-081277863745
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944231685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.2944231685
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.3321570256
Short name T433
Test name
Test status
Simulation time 32947232 ps
CPU time 0.75 seconds
Started Mar 17 02:45:07 PM PDT 24
Finished Mar 17 02:45:08 PM PDT 24
Peak memory 206392 kb
Host smart-a5d62edb-20eb-456f-9974-55361adc4082
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3321570256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.3321570256
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.627337392
Short name T239
Test name
Test status
Simulation time 2199560478 ps
CPU time 116.05 seconds
Started Mar 17 02:45:07 PM PDT 24
Finished Mar 17 02:47:04 PM PDT 24
Peak memory 220628 kb
Host smart-0f92c4b4-57b4-4bea-86d7-999419b42237
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=627337392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.627337392
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.3089741860
Short name T608
Test name
Test status
Simulation time 191682763 ps
CPU time 2.78 seconds
Started Mar 17 02:45:04 PM PDT 24
Finished Mar 17 02:45:07 PM PDT 24
Peak memory 208972 kb
Host smart-c79b1519-19e9-4e7c-a50f-c9c21fd1e6a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3089741860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.3089741860
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.2734846022
Short name T803
Test name
Test status
Simulation time 1086822899 ps
CPU time 6.8 seconds
Started Mar 17 02:45:00 PM PDT 24
Finished Mar 17 02:45:07 PM PDT 24
Peak memory 214820 kb
Host smart-017cebed-07a0-4d8c-8cde-ecf89a3a9f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734846022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.2734846022
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.2951692564
Short name T331
Test name
Test status
Simulation time 290537430 ps
CPU time 3.82 seconds
Started Mar 17 02:45:05 PM PDT 24
Finished Mar 17 02:45:09 PM PDT 24
Peak memory 220812 kb
Host smart-5ef95764-1906-42c4-ac3a-c38717ac216a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951692564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.2951692564
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.2838559173
Short name T839
Test name
Test status
Simulation time 413887867 ps
CPU time 5.3 seconds
Started Mar 17 02:45:00 PM PDT 24
Finished Mar 17 02:45:05 PM PDT 24
Peak memory 209832 kb
Host smart-e79d291f-c37a-4a91-bf7d-c479774767fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2838559173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.2838559173
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.1577130444
Short name T300
Test name
Test status
Simulation time 72643752 ps
CPU time 1.83 seconds
Started Mar 17 02:45:07 PM PDT 24
Finished Mar 17 02:45:10 PM PDT 24
Peak memory 207124 kb
Host smart-f85bb119-deaa-4545-80f6-d4e0f64487b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577130444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.1577130444
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.1978136742
Short name T14
Test name
Test status
Simulation time 159092958 ps
CPU time 4.63 seconds
Started Mar 17 02:45:03 PM PDT 24
Finished Mar 17 02:45:08 PM PDT 24
Peak memory 208808 kb
Host smart-9738934d-4ae9-4b03-8f62-e87e7a5bb8a8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1978136742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.1978136742
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.1462836581
Short name T886
Test name
Test status
Simulation time 85484991 ps
CPU time 2.12 seconds
Started Mar 17 02:45:00 PM PDT 24
Finished Mar 17 02:45:03 PM PDT 24
Peak memory 209036 kb
Host smart-97da610a-d9fb-465b-bc5b-9c0178dfbf1c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462836581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.1462836581
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.475422555
Short name T4
Test name
Test status
Simulation time 894411709 ps
CPU time 8.82 seconds
Started Mar 17 02:45:01 PM PDT 24
Finished Mar 17 02:45:10 PM PDT 24
Peak memory 208992 kb
Host smart-608adcbc-bf7e-4e06-8a0a-17e92897d00c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475422555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.475422555
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.1007321587
Short name T901
Test name
Test status
Simulation time 88607705 ps
CPU time 2.51 seconds
Started Mar 17 02:45:07 PM PDT 24
Finished Mar 17 02:45:11 PM PDT 24
Peak memory 210380 kb
Host smart-3d0ee0d2-dc0c-477b-9dd3-0ed3d3c93f2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007321587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.1007321587
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.3578812411
Short name T827
Test name
Test status
Simulation time 63560652 ps
CPU time 3.1 seconds
Started Mar 17 02:45:00 PM PDT 24
Finished Mar 17 02:45:03 PM PDT 24
Peak memory 208764 kb
Host smart-ed687837-673c-4a5e-b88d-6e603dcfed6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3578812411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.3578812411
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.3700485507
Short name T70
Test name
Test status
Simulation time 4636560647 ps
CPU time 30.36 seconds
Started Mar 17 02:45:02 PM PDT 24
Finished Mar 17 02:45:32 PM PDT 24
Peak memory 223112 kb
Host smart-e56374d6-6f7c-497e-a426-9f9816184c8f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3700485507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.3700485507
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.2611161327
Short name T593
Test name
Test status
Simulation time 913168172 ps
CPU time 29.17 seconds
Started Mar 17 02:45:01 PM PDT 24
Finished Mar 17 02:45:30 PM PDT 24
Peak memory 214724 kb
Host smart-651d5839-7c19-46e0-bc95-ac0be31b2a39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2611161327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.2611161327
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.3890408017
Short name T535
Test name
Test status
Simulation time 334570884 ps
CPU time 2.16 seconds
Started Mar 17 02:45:07 PM PDT 24
Finished Mar 17 02:45:10 PM PDT 24
Peak memory 210272 kb
Host smart-79ef9537-d921-4cb1-bf3e-16bbcd6235cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890408017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.3890408017
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.2801696598
Short name T841
Test name
Test status
Simulation time 17660691 ps
CPU time 0.83 seconds
Started Mar 17 02:45:07 PM PDT 24
Finished Mar 17 02:45:09 PM PDT 24
Peak memory 206392 kb
Host smart-c5030d5b-3b6b-4edc-a46a-30c76d6ea020
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2801696598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.2801696598
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.1872808549
Short name T357
Test name
Test status
Simulation time 213989181 ps
CPU time 10.53 seconds
Started Mar 17 02:45:04 PM PDT 24
Finished Mar 17 02:45:14 PM PDT 24
Peak memory 214760 kb
Host smart-a72cf05e-0a0b-4238-8896-064ede739b58
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1872808549 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.1872808549
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.3971003763
Short name T180
Test name
Test status
Simulation time 23041601 ps
CPU time 1.32 seconds
Started Mar 17 02:45:01 PM PDT 24
Finished Mar 17 02:45:02 PM PDT 24
Peak memory 207148 kb
Host smart-81256b0e-b6cf-4a11-9dc2-42452d8d441f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3971003763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.3971003763
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.1015881583
Short name T747
Test name
Test status
Simulation time 478895425 ps
CPU time 9.66 seconds
Started Mar 17 02:45:02 PM PDT 24
Finished Mar 17 02:45:12 PM PDT 24
Peak memory 222280 kb
Host smart-02e8ed64-f9ef-4bca-a748-0c14cfe71225
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1015881583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.1015881583
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.2591116752
Short name T698
Test name
Test status
Simulation time 56212785 ps
CPU time 2.39 seconds
Started Mar 17 02:45:06 PM PDT 24
Finished Mar 17 02:45:08 PM PDT 24
Peak memory 214708 kb
Host smart-9ceb4a7d-8f63-4c6c-821d-c441babc9bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2591116752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.2591116752
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.2243367842
Short name T499
Test name
Test status
Simulation time 406886442 ps
CPU time 4.96 seconds
Started Mar 17 02:45:02 PM PDT 24
Finished Mar 17 02:45:07 PM PDT 24
Peak memory 209744 kb
Host smart-f98516bd-8aa1-4ab4-9ae3-59447fee0454
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2243367842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.2243367842
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.3212783222
Short name T479
Test name
Test status
Simulation time 664144908 ps
CPU time 5.87 seconds
Started Mar 17 02:45:04 PM PDT 24
Finished Mar 17 02:45:10 PM PDT 24
Peak memory 208412 kb
Host smart-b4d3d508-b04d-446a-bb96-633c0ea5df27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3212783222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.3212783222
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.3036907933
Short name T629
Test name
Test status
Simulation time 278115626 ps
CPU time 3.62 seconds
Started Mar 17 02:45:05 PM PDT 24
Finished Mar 17 02:45:09 PM PDT 24
Peak memory 209008 kb
Host smart-f210d406-9659-48cc-80f6-d998405315cf
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3036907933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.3036907933
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.3013084228
Short name T623
Test name
Test status
Simulation time 55474908 ps
CPU time 2.96 seconds
Started Mar 17 02:45:01 PM PDT 24
Finished Mar 17 02:45:04 PM PDT 24
Peak memory 208736 kb
Host smart-b21eedca-62bd-4cc0-9aa8-922b74a5eb64
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013084228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.3013084228
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.3201874525
Short name T708
Test name
Test status
Simulation time 10028110019 ps
CPU time 68.29 seconds
Started Mar 17 02:45:01 PM PDT 24
Finished Mar 17 02:46:09 PM PDT 24
Peak memory 208756 kb
Host smart-313b1632-f363-43d8-85a4-33a5454b4f77
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201874525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.3201874525
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.3856662609
Short name T715
Test name
Test status
Simulation time 607582385 ps
CPU time 5.75 seconds
Started Mar 17 02:45:01 PM PDT 24
Finished Mar 17 02:45:07 PM PDT 24
Peak memory 210244 kb
Host smart-e8ec599e-4e5a-443b-bdb4-ee6e42cb3400
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856662609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.3856662609
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.1887296116
Short name T556
Test name
Test status
Simulation time 70264873 ps
CPU time 1.95 seconds
Started Mar 17 02:45:03 PM PDT 24
Finished Mar 17 02:45:05 PM PDT 24
Peak memory 207528 kb
Host smart-b67cbcde-73b2-4057-b3fe-67bff180735e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1887296116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.1887296116
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.3437498312
Short name T508
Test name
Test status
Simulation time 240142661 ps
CPU time 4.18 seconds
Started Mar 17 02:45:05 PM PDT 24
Finished Mar 17 02:45:09 PM PDT 24
Peak memory 207428 kb
Host smart-19eb554a-0085-4810-a1a5-f68320875064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437498312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.3437498312
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.3993312683
Short name T811
Test name
Test status
Simulation time 41065329 ps
CPU time 1.85 seconds
Started Mar 17 02:45:07 PM PDT 24
Finished Mar 17 02:45:10 PM PDT 24
Peak memory 209964 kb
Host smart-bc5ecce0-3868-426f-b63e-7d21e32635c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993312683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.3993312683
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.2263352122
Short name T99
Test name
Test status
Simulation time 40083800 ps
CPU time 0.77 seconds
Started Mar 17 02:45:07 PM PDT 24
Finished Mar 17 02:45:08 PM PDT 24
Peak memory 206328 kb
Host smart-fa071e4b-820f-47a5-b7b7-926ff7a2aa4c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2263352122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.2263352122
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.2519867493
Short name T383
Test name
Test status
Simulation time 154646825 ps
CPU time 3.41 seconds
Started Mar 17 02:45:07 PM PDT 24
Finished Mar 17 02:45:11 PM PDT 24
Peak memory 215668 kb
Host smart-ca2fd037-2ad4-43c6-b1e0-c55efb8ca36a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2519867493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.2519867493
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.3723108724
Short name T684
Test name
Test status
Simulation time 153855848 ps
CPU time 2.39 seconds
Started Mar 17 02:45:06 PM PDT 24
Finished Mar 17 02:45:08 PM PDT 24
Peak memory 208700 kb
Host smart-7b8e6986-cc2f-4cd1-8004-69525071e8be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723108724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.3723108724
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.888840538
Short name T297
Test name
Test status
Simulation time 232302977 ps
CPU time 4.44 seconds
Started Mar 17 02:45:06 PM PDT 24
Finished Mar 17 02:45:10 PM PDT 24
Peak memory 214772 kb
Host smart-5c7a7e66-cb21-4942-ab74-f535a8eb4b53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888840538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.888840538
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.1902915515
Short name T806
Test name
Test status
Simulation time 1190287050 ps
CPU time 8.58 seconds
Started Mar 17 02:45:11 PM PDT 24
Finished Mar 17 02:45:20 PM PDT 24
Peak memory 221784 kb
Host smart-5233b80e-2fd5-4a42-b83f-2f7a73e6c62b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902915515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.1902915515
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.3754236789
Short name T491
Test name
Test status
Simulation time 39409723 ps
CPU time 2.23 seconds
Started Mar 17 02:45:10 PM PDT 24
Finished Mar 17 02:45:12 PM PDT 24
Peak memory 206668 kb
Host smart-45bec1a3-8490-4b27-9d70-ddf74b7fab03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3754236789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.3754236789
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.182489464
Short name T246
Test name
Test status
Simulation time 192896066 ps
CPU time 5.22 seconds
Started Mar 17 02:45:07 PM PDT 24
Finished Mar 17 02:45:12 PM PDT 24
Peak memory 208144 kb
Host smart-48fa02a0-7968-4ea7-a83b-904e14670988
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182489464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.182489464
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.345262418
Short name T687
Test name
Test status
Simulation time 306145894 ps
CPU time 3.58 seconds
Started Mar 17 02:45:03 PM PDT 24
Finished Mar 17 02:45:07 PM PDT 24
Peak memory 207244 kb
Host smart-e19e571e-868f-4bdd-b442-8e9e7220dfc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345262418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.345262418
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.3752771121
Short name T618
Test name
Test status
Simulation time 169173797 ps
CPU time 4.67 seconds
Started Mar 17 02:45:08 PM PDT 24
Finished Mar 17 02:45:13 PM PDT 24
Peak memory 209128 kb
Host smart-f6940d2f-ae21-416f-83a6-f516e0c20ee0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3752771121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.3752771121
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.2337546612
Short name T529
Test name
Test status
Simulation time 35282204 ps
CPU time 2.52 seconds
Started Mar 17 02:45:08 PM PDT 24
Finished Mar 17 02:45:12 PM PDT 24
Peak memory 207268 kb
Host smart-856409ca-b420-4a47-b3a1-045887809dd4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337546612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.2337546612
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.3408055825
Short name T607
Test name
Test status
Simulation time 145308437 ps
CPU time 4.74 seconds
Started Mar 17 02:45:08 PM PDT 24
Finished Mar 17 02:45:14 PM PDT 24
Peak memory 208024 kb
Host smart-4de25b50-2a9d-4460-9753-08b29d96d4fa
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3408055825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.3408055825
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.3429522537
Short name T25
Test name
Test status
Simulation time 350076881 ps
CPU time 2.83 seconds
Started Mar 17 02:45:08 PM PDT 24
Finished Mar 17 02:45:13 PM PDT 24
Peak memory 209376 kb
Host smart-40edf12f-bea8-499f-a3c4-9110047f56f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429522537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.3429522537
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.2800236113
Short name T396
Test name
Test status
Simulation time 61692306 ps
CPU time 2.3 seconds
Started Mar 17 02:45:02 PM PDT 24
Finished Mar 17 02:45:04 PM PDT 24
Peak memory 207616 kb
Host smart-3e5fe1d2-07d4-4525-8ba8-e77644cb1892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2800236113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.2800236113
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.922945529
Short name T69
Test name
Test status
Simulation time 12580198426 ps
CPU time 63.3 seconds
Started Mar 17 02:45:07 PM PDT 24
Finished Mar 17 02:46:12 PM PDT 24
Peak memory 217064 kb
Host smart-db1c10e2-a500-4f80-98b3-f76b02cc2dcb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=922945529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.922945529
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_stress_all_with_rand_reset.1884812591
Short name T123
Test name
Test status
Simulation time 1989647512 ps
CPU time 17.22 seconds
Started Mar 17 02:45:10 PM PDT 24
Finished Mar 17 02:45:28 PM PDT 24
Peak memory 223088 kb
Host smart-bc3af61e-35b7-4c8c-8a8d-c541aeabbd4a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884812591 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all_with_rand_reset.1884812591
Directory /workspace/45.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.2457537443
Short name T439
Test name
Test status
Simulation time 66392678 ps
CPU time 3.78 seconds
Started Mar 17 02:45:07 PM PDT 24
Finished Mar 17 02:45:11 PM PDT 24
Peak memory 207928 kb
Host smart-1ce98b40-110b-4b86-b5fd-99a246de32ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2457537443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.2457537443
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.1171168038
Short name T862
Test name
Test status
Simulation time 338093022 ps
CPU time 3.5 seconds
Started Mar 17 02:45:08 PM PDT 24
Finished Mar 17 02:45:13 PM PDT 24
Peak memory 210252 kb
Host smart-adef2489-8a0b-4f19-8ce7-976738221394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1171168038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.1171168038
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.199049474
Short name T670
Test name
Test status
Simulation time 12309100 ps
CPU time 0.78 seconds
Started Mar 17 02:45:13 PM PDT 24
Finished Mar 17 02:45:15 PM PDT 24
Peak memory 206356 kb
Host smart-277b67c3-c07e-4daf-9a83-a404dacf40a9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199049474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.199049474
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.948761570
Short name T876
Test name
Test status
Simulation time 2113117481 ps
CPU time 32.22 seconds
Started Mar 17 02:45:07 PM PDT 24
Finished Mar 17 02:45:40 PM PDT 24
Peak memory 223272 kb
Host smart-b76559be-8b0d-4a3a-8308-99abbf925bee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=948761570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.948761570
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.1440614482
Short name T445
Test name
Test status
Simulation time 111006775 ps
CPU time 4.37 seconds
Started Mar 17 02:45:06 PM PDT 24
Finished Mar 17 02:45:11 PM PDT 24
Peak memory 210636 kb
Host smart-6fb8cf1b-82b8-4141-8a50-b15353990ed5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1440614482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.1440614482
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.287594006
Short name T309
Test name
Test status
Simulation time 515301606 ps
CPU time 3.28 seconds
Started Mar 17 02:45:06 PM PDT 24
Finished Mar 17 02:45:09 PM PDT 24
Peak memory 209556 kb
Host smart-142773e2-26c5-4110-b2d3-0f65e88a1e2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=287594006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.287594006
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.1193207730
Short name T327
Test name
Test status
Simulation time 79576415 ps
CPU time 2.21 seconds
Started Mar 17 02:45:08 PM PDT 24
Finished Mar 17 02:45:12 PM PDT 24
Peak memory 211224 kb
Host smart-0ae8a876-a682-44da-aac2-bbb533f52be2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193207730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.1193207730
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.3684508817
Short name T767
Test name
Test status
Simulation time 124587643 ps
CPU time 3.88 seconds
Started Mar 17 02:45:07 PM PDT 24
Finished Mar 17 02:45:12 PM PDT 24
Peak memory 220464 kb
Host smart-8ecdb755-bf15-48f2-94ac-6298edfc780f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684508817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.3684508817
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.3697644211
Short name T685
Test name
Test status
Simulation time 223278408 ps
CPU time 6.67 seconds
Started Mar 17 02:45:09 PM PDT 24
Finished Mar 17 02:45:16 PM PDT 24
Peak memory 218792 kb
Host smart-88e08ebe-8877-44cd-b3e2-f75d48166c63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697644211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.3697644211
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.3693841587
Short name T201
Test name
Test status
Simulation time 31467669 ps
CPU time 2.18 seconds
Started Mar 17 02:45:07 PM PDT 24
Finished Mar 17 02:45:10 PM PDT 24
Peak memory 209120 kb
Host smart-4879eda5-2f3d-43b7-8fd6-76d30b2af2c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3693841587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.3693841587
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.4209385715
Short name T722
Test name
Test status
Simulation time 108539431 ps
CPU time 2.73 seconds
Started Mar 17 02:45:09 PM PDT 24
Finished Mar 17 02:45:12 PM PDT 24
Peak memory 208384 kb
Host smart-0d9de8c7-6f9a-416b-b1ea-8fa14a576f98
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4209385715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.4209385715
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.2610190689
Short name T318
Test name
Test status
Simulation time 100995556 ps
CPU time 2.01 seconds
Started Mar 17 02:45:08 PM PDT 24
Finished Mar 17 02:45:11 PM PDT 24
Peak memory 207896 kb
Host smart-d842c5ea-2658-4f0c-aa9e-5749dcf38465
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610190689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.2610190689
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.3201876003
Short name T464
Test name
Test status
Simulation time 392055767 ps
CPU time 3.64 seconds
Started Mar 17 02:45:06 PM PDT 24
Finished Mar 17 02:45:10 PM PDT 24
Peak memory 207328 kb
Host smart-19ebca3f-594e-411a-bd0c-6360af4f5992
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3201876003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.3201876003
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.2281453252
Short name T892
Test name
Test status
Simulation time 35415625 ps
CPU time 2.05 seconds
Started Mar 17 02:45:06 PM PDT 24
Finished Mar 17 02:45:09 PM PDT 24
Peak memory 209644 kb
Host smart-23fc7bf5-5af8-4ab6-9fb1-6e9e6f1169a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281453252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.2281453252
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.3960730328
Short name T699
Test name
Test status
Simulation time 12298601413 ps
CPU time 59.5 seconds
Started Mar 17 02:45:11 PM PDT 24
Finished Mar 17 02:46:11 PM PDT 24
Peak memory 208612 kb
Host smart-b4d1ad29-2003-440e-8da6-0ea00704914a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3960730328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.3960730328
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.3585337799
Short name T281
Test name
Test status
Simulation time 7025613394 ps
CPU time 53.43 seconds
Started Mar 17 02:45:15 PM PDT 24
Finished Mar 17 02:46:09 PM PDT 24
Peak memory 216604 kb
Host smart-bf5a37ed-2799-4a61-8e43-3fa3973a79ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3585337799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.3585337799
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_stress_all_with_rand_reset.2489743989
Short name T71
Test name
Test status
Simulation time 307933685 ps
CPU time 12.6 seconds
Started Mar 17 02:45:15 PM PDT 24
Finished Mar 17 02:45:28 PM PDT 24
Peak memory 220488 kb
Host smart-1f79cc9a-465b-45be-b711-63df9039c6e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489743989 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all_with_rand_reset.2489743989
Directory /workspace/46.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.2361331208
Short name T872
Test name
Test status
Simulation time 663693712 ps
CPU time 6.1 seconds
Started Mar 17 02:45:06 PM PDT 24
Finished Mar 17 02:45:13 PM PDT 24
Peak memory 210704 kb
Host smart-52e8b3fc-bb28-4478-9a11-d9ac04c2539f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361331208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.2361331208
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.1899837767
Short name T404
Test name
Test status
Simulation time 136046027 ps
CPU time 3.12 seconds
Started Mar 17 02:45:07 PM PDT 24
Finished Mar 17 02:45:11 PM PDT 24
Peak memory 210500 kb
Host smart-327c1cd3-c507-4a69-8119-0f0e98f52889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899837767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.1899837767
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.57178477
Short name T634
Test name
Test status
Simulation time 14162706 ps
CPU time 0.85 seconds
Started Mar 17 02:45:13 PM PDT 24
Finished Mar 17 02:45:15 PM PDT 24
Peak memory 206452 kb
Host smart-63a59f0c-a6ba-4a49-9b8e-272aa665f1ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57178477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.57178477
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.378765250
Short name T419
Test name
Test status
Simulation time 76998666 ps
CPU time 3.21 seconds
Started Mar 17 02:45:15 PM PDT 24
Finished Mar 17 02:45:19 PM PDT 24
Peak memory 214916 kb
Host smart-5dd02217-b3be-4dff-b8e0-6b15cc39d803
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=378765250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.378765250
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.2858793085
Short name T34
Test name
Test status
Simulation time 1263287805 ps
CPU time 10.1 seconds
Started Mar 17 02:45:15 PM PDT 24
Finished Mar 17 02:45:26 PM PDT 24
Peak memory 222384 kb
Host smart-865c3900-088d-4447-8ff9-1d357b7de7d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2858793085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.2858793085
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.1816460736
Short name T874
Test name
Test status
Simulation time 81448441 ps
CPU time 3.29 seconds
Started Mar 17 02:45:15 PM PDT 24
Finished Mar 17 02:45:19 PM PDT 24
Peak memory 214804 kb
Host smart-402d4fe4-0356-4009-8c2d-9d2a499dc24c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1816460736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.1816460736
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.1744926613
Short name T97
Test name
Test status
Simulation time 179096166 ps
CPU time 3.16 seconds
Started Mar 17 02:45:13 PM PDT 24
Finished Mar 17 02:45:18 PM PDT 24
Peak memory 219196 kb
Host smart-45499dd1-adbe-4aec-9446-a8cf8f7fd0ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1744926613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.1744926613
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.2459473242
Short name T366
Test name
Test status
Simulation time 74535059 ps
CPU time 2.74 seconds
Started Mar 17 02:45:16 PM PDT 24
Finished Mar 17 02:45:19 PM PDT 24
Peak memory 209124 kb
Host smart-1700e4c1-afca-4d82-8a80-344174af4bbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2459473242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.2459473242
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.664142900
Short name T230
Test name
Test status
Simulation time 110189200 ps
CPU time 3.51 seconds
Started Mar 17 02:45:14 PM PDT 24
Finished Mar 17 02:45:19 PM PDT 24
Peak memory 220336 kb
Host smart-ac027ecd-1d25-49ec-b013-81862b2e3ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664142900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.664142900
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.1964533236
Short name T215
Test name
Test status
Simulation time 95216267 ps
CPU time 4.66 seconds
Started Mar 17 02:45:15 PM PDT 24
Finished Mar 17 02:45:20 PM PDT 24
Peak memory 207844 kb
Host smart-d88b90b8-d56f-4941-b7d8-de81733a966e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964533236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.1964533236
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.99235354
Short name T697
Test name
Test status
Simulation time 209408662 ps
CPU time 6.03 seconds
Started Mar 17 02:45:16 PM PDT 24
Finished Mar 17 02:45:23 PM PDT 24
Peak memory 209092 kb
Host smart-43c7bed2-2302-4ec4-b6b9-033311c58cc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=99235354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.99235354
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.3270739768
Short name T614
Test name
Test status
Simulation time 45629215 ps
CPU time 1.9 seconds
Started Mar 17 02:45:12 PM PDT 24
Finished Mar 17 02:45:15 PM PDT 24
Peak memory 207180 kb
Host smart-0a9ecfb6-dd3f-4045-98d2-ce88fb7d0fe5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3270739768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.3270739768
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.1831232073
Short name T459
Test name
Test status
Simulation time 5893947830 ps
CPU time 60.47 seconds
Started Mar 17 02:45:14 PM PDT 24
Finished Mar 17 02:46:16 PM PDT 24
Peak memory 209592 kb
Host smart-f8a6519b-0390-4648-9b58-b64e55e60e6f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831232073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.1831232073
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.2673379742
Short name T887
Test name
Test status
Simulation time 12835703001 ps
CPU time 27.35 seconds
Started Mar 17 02:45:13 PM PDT 24
Finished Mar 17 02:45:42 PM PDT 24
Peak memory 208568 kb
Host smart-46e803c1-ed44-477f-aad1-96d1a38f610d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673379742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.2673379742
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.2511178233
Short name T528
Test name
Test status
Simulation time 122244640 ps
CPU time 3.56 seconds
Started Mar 17 02:45:13 PM PDT 24
Finished Mar 17 02:45:18 PM PDT 24
Peak memory 210628 kb
Host smart-0f46aef8-494d-4762-832f-d31e9ee6d191
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2511178233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.2511178233
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.3633170613
Short name T794
Test name
Test status
Simulation time 183316085 ps
CPU time 6 seconds
Started Mar 17 02:45:15 PM PDT 24
Finished Mar 17 02:45:22 PM PDT 24
Peak memory 207240 kb
Host smart-5e391be9-3f50-400c-b899-cdcf828eae7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3633170613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.3633170613
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.677040343
Short name T877
Test name
Test status
Simulation time 3757881934 ps
CPU time 16.29 seconds
Started Mar 17 02:45:13 PM PDT 24
Finished Mar 17 02:45:31 PM PDT 24
Peak memory 222356 kb
Host smart-9b309fe1-3473-4e8b-afbb-55cb80a748e0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=677040343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.677040343
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.3603736862
Short name T120
Test name
Test status
Simulation time 83218802 ps
CPU time 5.6 seconds
Started Mar 17 02:45:12 PM PDT 24
Finished Mar 17 02:45:19 PM PDT 24
Peak memory 223076 kb
Host smart-42bfa345-971b-4093-bf02-6f2dd6946e6d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3603736862 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all_with_rand_reset.3603736862
Directory /workspace/47.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.962582900
Short name T118
Test name
Test status
Simulation time 390750755 ps
CPU time 10.34 seconds
Started Mar 17 02:45:15 PM PDT 24
Finished Mar 17 02:45:26 PM PDT 24
Peak memory 208912 kb
Host smart-92173db5-428a-4f66-b284-30a9dadd5a2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=962582900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.962582900
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.2166212257
Short name T690
Test name
Test status
Simulation time 281548041 ps
CPU time 2.5 seconds
Started Mar 17 02:45:16 PM PDT 24
Finished Mar 17 02:45:19 PM PDT 24
Peak memory 209996 kb
Host smart-eaec034e-67ec-4600-9599-9f58ce060843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2166212257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.2166212257
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.3810244599
Short name T709
Test name
Test status
Simulation time 122269857 ps
CPU time 0.85 seconds
Started Mar 17 02:45:18 PM PDT 24
Finished Mar 17 02:45:19 PM PDT 24
Peak memory 206396 kb
Host smart-793fa108-b1f7-4865-9250-93b6065d359b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3810244599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.3810244599
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.621763204
Short name T832
Test name
Test status
Simulation time 1800536319 ps
CPU time 24.43 seconds
Started Mar 17 02:45:15 PM PDT 24
Finished Mar 17 02:45:41 PM PDT 24
Peak memory 214836 kb
Host smart-f6c96b84-9ec8-45f9-92e9-26860ff4f83d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=621763204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.621763204
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.796837761
Short name T223
Test name
Test status
Simulation time 512903615 ps
CPU time 5.68 seconds
Started Mar 17 02:45:20 PM PDT 24
Finished Mar 17 02:45:25 PM PDT 24
Peak memory 214908 kb
Host smart-257ca238-a04d-4873-a382-a031547dbc54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796837761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.796837761
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.3312822369
Short name T812
Test name
Test status
Simulation time 1391698754 ps
CPU time 14.47 seconds
Started Mar 17 02:45:13 PM PDT 24
Finished Mar 17 02:45:30 PM PDT 24
Peak memory 218868 kb
Host smart-c57208a3-456f-4e8f-9dc6-6ef759f22fc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312822369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.3312822369
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.3010784872
Short name T93
Test name
Test status
Simulation time 565073477 ps
CPU time 5.71 seconds
Started Mar 17 02:45:16 PM PDT 24
Finished Mar 17 02:45:22 PM PDT 24
Peak memory 214656 kb
Host smart-62fe1787-73b2-401d-a2c0-dea60bb73c5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3010784872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.3010784872
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.953599912
Short name T41
Test name
Test status
Simulation time 261367086 ps
CPU time 8.87 seconds
Started Mar 17 02:45:22 PM PDT 24
Finished Mar 17 02:45:31 PM PDT 24
Peak memory 222408 kb
Host smart-41bcd771-1c37-4364-aca4-8c56ab54ddf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=953599912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.953599912
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.376905789
Short name T713
Test name
Test status
Simulation time 245847396 ps
CPU time 3.79 seconds
Started Mar 17 02:45:13 PM PDT 24
Finished Mar 17 02:45:18 PM PDT 24
Peak memory 214728 kb
Host smart-18a100eb-5064-4571-a029-c4a914aa6ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376905789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.376905789
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.395958228
Short name T274
Test name
Test status
Simulation time 148555169 ps
CPU time 6.98 seconds
Started Mar 17 02:45:14 PM PDT 24
Finished Mar 17 02:45:22 PM PDT 24
Peak memory 210168 kb
Host smart-26341235-1ec9-44d3-bb44-d5fa7c0b2726
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395958228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.395958228
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.3504125910
Short name T840
Test name
Test status
Simulation time 61623959 ps
CPU time 3.39 seconds
Started Mar 17 02:45:15 PM PDT 24
Finished Mar 17 02:45:19 PM PDT 24
Peak memory 207260 kb
Host smart-fab65252-37ad-4c63-9f96-2fb1307eb02e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3504125910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.3504125910
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.4145610266
Short name T465
Test name
Test status
Simulation time 8415433483 ps
CPU time 91.81 seconds
Started Mar 17 02:45:16 PM PDT 24
Finished Mar 17 02:46:48 PM PDT 24
Peak memory 208984 kb
Host smart-221d0c21-e9a7-480c-9590-f2937dbb3580
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4145610266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.4145610266
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.1421951552
Short name T218
Test name
Test status
Simulation time 243939565 ps
CPU time 3.31 seconds
Started Mar 17 02:45:13 PM PDT 24
Finished Mar 17 02:45:18 PM PDT 24
Peak memory 207208 kb
Host smart-a729ad62-1d2a-4798-8e80-ea2def39f340
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1421951552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.1421951552
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.3368313480
Short name T745
Test name
Test status
Simulation time 34743366 ps
CPU time 2.24 seconds
Started Mar 17 02:45:12 PM PDT 24
Finished Mar 17 02:45:15 PM PDT 24
Peak memory 209144 kb
Host smart-e693996f-3bdf-44be-8e42-645da7d0a401
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368313480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.3368313480
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.2187686429
Short name T580
Test name
Test status
Simulation time 50915322 ps
CPU time 2.19 seconds
Started Mar 17 02:45:20 PM PDT 24
Finished Mar 17 02:45:22 PM PDT 24
Peak memory 209860 kb
Host smart-f723fb59-3604-4b0f-946c-3eb738394425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187686429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.2187686429
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.18618626
Short name T576
Test name
Test status
Simulation time 114591900 ps
CPU time 3.92 seconds
Started Mar 17 02:45:16 PM PDT 24
Finished Mar 17 02:45:21 PM PDT 24
Peak memory 209140 kb
Host smart-2635edfa-4c6c-474e-a711-13ebc0b5d9b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=18618626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.18618626
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.3725159181
Short name T577
Test name
Test status
Simulation time 2827588460 ps
CPU time 13.1 seconds
Started Mar 17 02:45:15 PM PDT 24
Finished Mar 17 02:45:29 PM PDT 24
Peak memory 209628 kb
Host smart-d2fd44cc-6258-411c-9910-ff1d7f9d28c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725159181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.3725159181
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.4010459336
Short name T388
Test name
Test status
Simulation time 205112928 ps
CPU time 2.24 seconds
Started Mar 17 02:45:19 PM PDT 24
Finished Mar 17 02:45:21 PM PDT 24
Peak memory 210484 kb
Host smart-703aee24-c403-4ab6-9691-0b93137388e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010459336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.4010459336
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.4136731206
Short name T609
Test name
Test status
Simulation time 40939669 ps
CPU time 0.89 seconds
Started Mar 17 02:45:22 PM PDT 24
Finished Mar 17 02:45:23 PM PDT 24
Peak memory 206136 kb
Host smart-52b3abe0-1bd3-49c1-a54a-7b0f59a293a6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136731206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.4136731206
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.58313608
Short name T531
Test name
Test status
Simulation time 111252710 ps
CPU time 4.89 seconds
Started Mar 17 02:45:20 PM PDT 24
Finished Mar 17 02:45:24 PM PDT 24
Peak memory 209408 kb
Host smart-8467839d-1764-4d91-a281-c5ea91e41911
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=58313608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.58313608
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.65151955
Short name T365
Test name
Test status
Simulation time 113412195 ps
CPU time 3.9 seconds
Started Mar 17 02:45:19 PM PDT 24
Finished Mar 17 02:45:23 PM PDT 24
Peak memory 208772 kb
Host smart-3f7999b2-6541-4188-87ee-4702666a0357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=65151955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.65151955
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.4008915898
Short name T855
Test name
Test status
Simulation time 4248510957 ps
CPU time 7.68 seconds
Started Mar 17 02:45:21 PM PDT 24
Finished Mar 17 02:45:28 PM PDT 24
Peak memory 221252 kb
Host smart-4b114805-283e-4624-8ae4-fc010e0b109c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008915898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.4008915898
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.225819749
Short name T591
Test name
Test status
Simulation time 101864256 ps
CPU time 3.53 seconds
Started Mar 17 02:45:19 PM PDT 24
Finished Mar 17 02:45:22 PM PDT 24
Peak memory 210544 kb
Host smart-b3bca461-8968-465f-8c5c-4891c62d648a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225819749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.225819749
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.225591804
Short name T488
Test name
Test status
Simulation time 83198842 ps
CPU time 4.41 seconds
Started Mar 17 02:45:21 PM PDT 24
Finished Mar 17 02:45:25 PM PDT 24
Peak memory 209268 kb
Host smart-e267b800-f055-4767-8922-d5ad94967463
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225591804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.225591804
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.1660744168
Short name T339
Test name
Test status
Simulation time 239340988 ps
CPU time 6.84 seconds
Started Mar 17 02:45:20 PM PDT 24
Finished Mar 17 02:45:27 PM PDT 24
Peak memory 209044 kb
Host smart-2412f181-ed08-4c00-b7ed-08b2d39cf1a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660744168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.1660744168
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.1168107800
Short name T217
Test name
Test status
Simulation time 535897907 ps
CPU time 4.92 seconds
Started Mar 17 02:45:20 PM PDT 24
Finished Mar 17 02:45:25 PM PDT 24
Peak memory 207192 kb
Host smart-18d1b222-e97b-45fa-bcd8-1ee9588a5930
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1168107800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.1168107800
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.3142737174
Short name T455
Test name
Test status
Simulation time 5480949630 ps
CPU time 19.61 seconds
Started Mar 17 02:45:19 PM PDT 24
Finished Mar 17 02:45:39 PM PDT 24
Peak memory 208384 kb
Host smart-94159900-9be5-47e5-a0a0-0a4d307c6706
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142737174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.3142737174
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.4276966853
Short name T471
Test name
Test status
Simulation time 79471676 ps
CPU time 2.59 seconds
Started Mar 17 02:45:17 PM PDT 24
Finished Mar 17 02:45:19 PM PDT 24
Peak memory 207696 kb
Host smart-d12296dc-cfa4-49c4-9b84-3a344e870cf8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4276966853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.4276966853
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.1516560973
Short name T376
Test name
Test status
Simulation time 60573547 ps
CPU time 2.46 seconds
Started Mar 17 02:45:21 PM PDT 24
Finished Mar 17 02:45:23 PM PDT 24
Peak memory 218740 kb
Host smart-fffe0cea-3a2f-4121-acd6-870b771f7e0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1516560973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.1516560973
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.2105632052
Short name T826
Test name
Test status
Simulation time 77047266 ps
CPU time 3.04 seconds
Started Mar 17 02:45:23 PM PDT 24
Finished Mar 17 02:45:26 PM PDT 24
Peak memory 207200 kb
Host smart-f5a4da0b-c629-44d5-87c7-947cd9a21ed3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105632052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.2105632052
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.2093669399
Short name T315
Test name
Test status
Simulation time 2827114132 ps
CPU time 97.37 seconds
Started Mar 17 02:45:19 PM PDT 24
Finished Mar 17 02:46:56 PM PDT 24
Peak memory 217496 kb
Host smart-a13262d2-019c-48d7-ab77-4d620781b672
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2093669399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.2093669399
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.288305717
Short name T245
Test name
Test status
Simulation time 183421112 ps
CPU time 4.08 seconds
Started Mar 17 02:45:18 PM PDT 24
Finished Mar 17 02:45:23 PM PDT 24
Peak memory 218672 kb
Host smart-0d411a86-2d3b-4ad6-8dc2-e2925e4476b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288305717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.288305717
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.1149407083
Short name T788
Test name
Test status
Simulation time 93541335 ps
CPU time 1.73 seconds
Started Mar 17 02:45:17 PM PDT 24
Finished Mar 17 02:45:19 PM PDT 24
Peak memory 210320 kb
Host smart-8d1171c9-ea02-4013-bc8f-0107342b8928
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149407083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.1149407083
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.939484580
Short name T448
Test name
Test status
Simulation time 27844611 ps
CPU time 0.75 seconds
Started Mar 17 02:42:54 PM PDT 24
Finished Mar 17 02:42:54 PM PDT 24
Peak memory 206312 kb
Host smart-4a31953b-1432-4b97-aa76-56eaa53ef5c1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939484580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.939484580
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.3766329599
Short name T423
Test name
Test status
Simulation time 264510110 ps
CPU time 2.91 seconds
Started Mar 17 02:42:55 PM PDT 24
Finished Mar 17 02:42:58 PM PDT 24
Peak memory 215132 kb
Host smart-a67e79b0-4647-4c52-ae21-e43cd291c920
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3766329599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.3766329599
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.2738061016
Short name T851
Test name
Test status
Simulation time 36373597 ps
CPU time 2.59 seconds
Started Mar 17 02:42:49 PM PDT 24
Finished Mar 17 02:42:53 PM PDT 24
Peak memory 209284 kb
Host smart-880cec37-3595-409a-9d39-e2028077fce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738061016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.2738061016
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.508453390
Short name T494
Test name
Test status
Simulation time 26095687 ps
CPU time 1.67 seconds
Started Mar 17 02:42:50 PM PDT 24
Finished Mar 17 02:42:52 PM PDT 24
Peak memory 207564 kb
Host smart-7c979312-8759-4208-8c44-d0424310262f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=508453390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.508453390
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.880402240
Short name T333
Test name
Test status
Simulation time 146556537 ps
CPU time 3.72 seconds
Started Mar 17 02:42:54 PM PDT 24
Finished Mar 17 02:42:57 PM PDT 24
Peak memory 208796 kb
Host smart-043df8e9-b582-4dfd-8521-5843574f8154
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880402240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.880402240
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.2531919694
Short name T257
Test name
Test status
Simulation time 607856683 ps
CPU time 8.59 seconds
Started Mar 17 02:42:48 PM PDT 24
Finished Mar 17 02:42:56 PM PDT 24
Peak memory 212420 kb
Host smart-b7678518-3970-4c8d-b4db-ec438c2298e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2531919694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.2531919694
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.1045235447
Short name T595
Test name
Test status
Simulation time 182643841 ps
CPU time 4.97 seconds
Started Mar 17 02:42:49 PM PDT 24
Finished Mar 17 02:42:55 PM PDT 24
Peak memory 220772 kb
Host smart-2e4ff4d9-8324-4bad-9640-654f9453df5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045235447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.1045235447
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.3929954609
Short name T703
Test name
Test status
Simulation time 52822398 ps
CPU time 3.57 seconds
Started Mar 17 02:42:51 PM PDT 24
Finished Mar 17 02:42:55 PM PDT 24
Peak memory 210176 kb
Host smart-175017cf-25c1-4a23-9fc4-34b747915856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3929954609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.3929954609
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.972414593
Short name T378
Test name
Test status
Simulation time 129403332 ps
CPU time 2.43 seconds
Started Mar 17 02:42:50 PM PDT 24
Finished Mar 17 02:42:53 PM PDT 24
Peak memory 207072 kb
Host smart-bd2db226-61af-4bc5-ba53-84458ef9dfcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=972414593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.972414593
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.2369754726
Short name T610
Test name
Test status
Simulation time 136875759 ps
CPU time 5.44 seconds
Started Mar 17 02:42:49 PM PDT 24
Finished Mar 17 02:42:55 PM PDT 24
Peak memory 209008 kb
Host smart-25a1c9a4-68b4-4d38-9141-1218d76cd822
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369754726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.2369754726
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.1103798328
Short name T842
Test name
Test status
Simulation time 2379149289 ps
CPU time 13.81 seconds
Started Mar 17 02:42:55 PM PDT 24
Finished Mar 17 02:43:09 PM PDT 24
Peak memory 209220 kb
Host smart-30e39b5d-74c2-410c-a7d4-375995d77a0f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103798328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.1103798328
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.2707381409
Short name T124
Test name
Test status
Simulation time 1135191872 ps
CPU time 42.46 seconds
Started Mar 17 02:42:50 PM PDT 24
Finished Mar 17 02:43:33 PM PDT 24
Peak memory 209496 kb
Host smart-1d648378-09ce-4a42-8172-6395126ad14d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707381409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.2707381409
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.2717408922
Short name T873
Test name
Test status
Simulation time 42077165 ps
CPU time 2.43 seconds
Started Mar 17 02:42:50 PM PDT 24
Finished Mar 17 02:42:53 PM PDT 24
Peak memory 209304 kb
Host smart-1581cd62-3cf3-4fd7-9160-25411552a533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2717408922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.2717408922
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.193700292
Short name T437
Test name
Test status
Simulation time 142547094 ps
CPU time 3.05 seconds
Started Mar 17 02:42:56 PM PDT 24
Finished Mar 17 02:42:59 PM PDT 24
Peak memory 208680 kb
Host smart-a0590c1a-f6b9-40db-addb-d321af56dbc1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193700292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.193700292
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all_with_rand_reset.161934943
Short name T843
Test name
Test status
Simulation time 1420497767 ps
CPU time 16.56 seconds
Started Mar 17 02:42:54 PM PDT 24
Finished Mar 17 02:43:11 PM PDT 24
Peak memory 220248 kb
Host smart-270ab1fe-e324-4585-b5b3-af708eb6b2e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=161934943 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all_with_rand_reset.161934943
Directory /workspace/5.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.1337913342
Short name T852
Test name
Test status
Simulation time 370448497 ps
CPU time 4.6 seconds
Started Mar 17 02:42:48 PM PDT 24
Finished Mar 17 02:42:53 PM PDT 24
Peak memory 209328 kb
Host smart-d5e6eb51-e9ac-4753-9455-0aa094610830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337913342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.1337913342
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.977770876
Short name T759
Test name
Test status
Simulation time 220405328 ps
CPU time 3.97 seconds
Started Mar 17 02:42:50 PM PDT 24
Finished Mar 17 02:42:55 PM PDT 24
Peak memory 210720 kb
Host smart-dc1ce834-6a75-4a3f-b74c-b922f86fa72f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977770876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.977770876
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.3097213520
Short name T453
Test name
Test status
Simulation time 10805487 ps
CPU time 0.92 seconds
Started Mar 17 02:42:54 PM PDT 24
Finished Mar 17 02:42:55 PM PDT 24
Peak memory 206280 kb
Host smart-cb08f55c-5528-4f74-83c2-79ae2676c45b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3097213520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.3097213520
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.721388237
Short name T283
Test name
Test status
Simulation time 40789300 ps
CPU time 2.82 seconds
Started Mar 17 02:42:54 PM PDT 24
Finished Mar 17 02:42:57 PM PDT 24
Peak memory 214776 kb
Host smart-bbc7fc2a-0907-4847-9cbe-bf906b7b7e9a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=721388237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.721388237
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.961592080
Short name T844
Test name
Test status
Simulation time 87751413 ps
CPU time 4.28 seconds
Started Mar 17 02:42:54 PM PDT 24
Finished Mar 17 02:42:58 PM PDT 24
Peak memory 222316 kb
Host smart-f4b9916e-9538-43a7-80a7-810bfaa04493
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961592080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.961592080
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.2356466807
Short name T63
Test name
Test status
Simulation time 85848812 ps
CPU time 2.2 seconds
Started Mar 17 02:42:56 PM PDT 24
Finished Mar 17 02:42:58 PM PDT 24
Peak memory 218860 kb
Host smart-1dd6cfdf-db03-4294-b9bf-c02fb2f297e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356466807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.2356466807
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.4068199068
Short name T343
Test name
Test status
Simulation time 35799232 ps
CPU time 2.7 seconds
Started Mar 17 02:42:54 PM PDT 24
Finished Mar 17 02:42:57 PM PDT 24
Peak memory 209116 kb
Host smart-91eb2563-84c4-4117-ad23-d8175fc203a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068199068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.4068199068
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.3489813368
Short name T229
Test name
Test status
Simulation time 78621706 ps
CPU time 2.23 seconds
Started Mar 17 02:42:56 PM PDT 24
Finished Mar 17 02:42:59 PM PDT 24
Peak memory 216696 kb
Host smart-8a1debd1-f803-4f4c-aaa9-d49a53e817c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3489813368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.3489813368
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.2019381708
Short name T279
Test name
Test status
Simulation time 567903747 ps
CPU time 7.31 seconds
Started Mar 17 02:42:54 PM PDT 24
Finished Mar 17 02:43:02 PM PDT 24
Peak memory 210316 kb
Host smart-8ff93fab-2c91-4104-920c-79e0f51417c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019381708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.2019381708
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.3603678447
Short name T642
Test name
Test status
Simulation time 229675941 ps
CPU time 3.28 seconds
Started Mar 17 02:42:50 PM PDT 24
Finished Mar 17 02:42:54 PM PDT 24
Peak memory 207024 kb
Host smart-155f7001-1ea7-4512-9df0-b6391e65e99a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603678447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.3603678447
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.1517717441
Short name T546
Test name
Test status
Simulation time 8324448411 ps
CPU time 59.91 seconds
Started Mar 17 02:42:56 PM PDT 24
Finished Mar 17 02:43:56 PM PDT 24
Peak memory 209136 kb
Host smart-b5003894-d65c-4f40-8bf3-b36f693dcf80
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1517717441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.1517717441
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.674252668
Short name T652
Test name
Test status
Simulation time 273063557 ps
CPU time 3.8 seconds
Started Mar 17 02:42:50 PM PDT 24
Finished Mar 17 02:42:55 PM PDT 24
Peak memory 209168 kb
Host smart-6ecadb60-3b80-4683-8734-4a701f2d4ada
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674252668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.674252668
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.1760277709
Short name T477
Test name
Test status
Simulation time 60346413 ps
CPU time 3.09 seconds
Started Mar 17 02:42:54 PM PDT 24
Finished Mar 17 02:42:58 PM PDT 24
Peak memory 207724 kb
Host smart-777d3ef8-51f1-4a58-86da-f4d3241a4c5e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1760277709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.1760277709
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.3060400990
Short name T818
Test name
Test status
Simulation time 786719631 ps
CPU time 14.89 seconds
Started Mar 17 02:42:55 PM PDT 24
Finished Mar 17 02:43:10 PM PDT 24
Peak memory 209556 kb
Host smart-755b4c6f-7f03-4d38-a5e5-36bccf18484d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060400990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.3060400990
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.2875757484
Short name T567
Test name
Test status
Simulation time 37465726 ps
CPU time 2.06 seconds
Started Mar 17 02:42:47 PM PDT 24
Finished Mar 17 02:42:49 PM PDT 24
Peak memory 207020 kb
Host smart-a8eaa4b9-2420-4e5e-a60a-9b9a7762f709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2875757484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.2875757484
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.2791312281
Short name T288
Test name
Test status
Simulation time 4279792354 ps
CPU time 31.05 seconds
Started Mar 17 02:42:55 PM PDT 24
Finished Mar 17 02:43:26 PM PDT 24
Peak memory 215724 kb
Host smart-13c12c09-32bb-4b6d-966e-b359e8a4f9f2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791312281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.2791312281
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_stress_all_with_rand_reset.3204685087
Short name T172
Test name
Test status
Simulation time 408004170 ps
CPU time 15.2 seconds
Started Mar 17 02:42:53 PM PDT 24
Finished Mar 17 02:43:08 PM PDT 24
Peak memory 220824 kb
Host smart-cb9f7f75-ca99-4d0a-97ef-9e2cfcd87925
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3204685087 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all_with_rand_reset.3204685087
Directory /workspace/6.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.706400522
Short name T881
Test name
Test status
Simulation time 1479052499 ps
CPU time 4.46 seconds
Started Mar 17 02:42:55 PM PDT 24
Finished Mar 17 02:43:00 PM PDT 24
Peak memory 209832 kb
Host smart-77b44a63-9c6c-4000-a59d-659073b1040c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=706400522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.706400522
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.425521409
Short name T390
Test name
Test status
Simulation time 48733805 ps
CPU time 1.87 seconds
Started Mar 17 02:42:57 PM PDT 24
Finished Mar 17 02:42:59 PM PDT 24
Peak memory 210184 kb
Host smart-79a1aaf6-ef46-4cf8-a564-27b5eb5ca1f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=425521409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.425521409
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.3303116436
Short name T731
Test name
Test status
Simulation time 25688419 ps
CPU time 0.87 seconds
Started Mar 17 02:42:58 PM PDT 24
Finished Mar 17 02:42:58 PM PDT 24
Peak memory 206288 kb
Host smart-aa241e40-9e2c-43b1-b9e8-221957c1cabd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303116436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.3303116436
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.74935855
Short name T359
Test name
Test status
Simulation time 88297273 ps
CPU time 3.5 seconds
Started Mar 17 02:42:55 PM PDT 24
Finished Mar 17 02:42:58 PM PDT 24
Peak memory 215864 kb
Host smart-99cf1364-666f-4c85-ad1a-5530e81da7c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=74935855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.74935855
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.1390906477
Short name T66
Test name
Test status
Simulation time 183823732 ps
CPU time 3.25 seconds
Started Mar 17 02:42:55 PM PDT 24
Finished Mar 17 02:42:59 PM PDT 24
Peak memory 215068 kb
Host smart-5c9d13ff-6552-435d-93b7-5f5c366b1c49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1390906477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.1390906477
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.602050532
Short name T772
Test name
Test status
Simulation time 1105545705 ps
CPU time 32.42 seconds
Started Mar 17 02:42:57 PM PDT 24
Finished Mar 17 02:43:29 PM PDT 24
Peak memory 218852 kb
Host smart-5cf709b4-58ff-4755-b624-ef1a8b6ed5d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602050532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.602050532
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.3244168009
Short name T809
Test name
Test status
Simulation time 105352941 ps
CPU time 4.43 seconds
Started Mar 17 02:42:57 PM PDT 24
Finished Mar 17 02:43:02 PM PDT 24
Peak memory 220676 kb
Host smart-10ff4985-8d68-4c64-b55e-e5b4d25d97e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244168009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.3244168009
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.688065916
Short name T816
Test name
Test status
Simulation time 56414470 ps
CPU time 4.22 seconds
Started Mar 17 02:42:56 PM PDT 24
Finished Mar 17 02:43:00 PM PDT 24
Peak memory 221300 kb
Host smart-3d787253-226e-43ee-92b5-bdbdea0977f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688065916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.688065916
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.405449931
Short name T581
Test name
Test status
Simulation time 4174282934 ps
CPU time 14.23 seconds
Started Mar 17 02:42:54 PM PDT 24
Finished Mar 17 02:43:09 PM PDT 24
Peak memory 208544 kb
Host smart-3911bc7b-3749-4c8d-8f80-a7d3c4ac8d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=405449931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.405449931
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.856427426
Short name T191
Test name
Test status
Simulation time 133258990 ps
CPU time 2.91 seconds
Started Mar 17 02:42:54 PM PDT 24
Finished Mar 17 02:42:57 PM PDT 24
Peak memory 209164 kb
Host smart-f9b3b48e-b2ed-4531-9584-0951518a5fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856427426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.856427426
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.1171214784
Short name T774
Test name
Test status
Simulation time 109798370 ps
CPU time 2.93 seconds
Started Mar 17 02:42:56 PM PDT 24
Finished Mar 17 02:42:59 PM PDT 24
Peak memory 207112 kb
Host smart-299244c9-fa6c-4778-8535-c1520ae7d432
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171214784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.1171214784
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.1464955331
Short name T557
Test name
Test status
Simulation time 28752094391 ps
CPU time 102.95 seconds
Started Mar 17 02:42:57 PM PDT 24
Finished Mar 17 02:44:40 PM PDT 24
Peak memory 209168 kb
Host smart-77677cbb-61c7-443c-bcb1-87c09f5e88b0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464955331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.1464955331
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.1769024352
Short name T510
Test name
Test status
Simulation time 606001518 ps
CPU time 5.91 seconds
Started Mar 17 02:42:56 PM PDT 24
Finished Mar 17 02:43:02 PM PDT 24
Peak memory 207384 kb
Host smart-a67b3e71-9156-4f02-9302-a612482549d5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769024352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.1769024352
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.156381263
Short name T341
Test name
Test status
Simulation time 1115401914 ps
CPU time 15.03 seconds
Started Mar 17 02:42:55 PM PDT 24
Finished Mar 17 02:43:10 PM PDT 24
Peak memory 209152 kb
Host smart-4ae4e1ca-f38c-4e26-8859-400ba8f87beb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156381263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.156381263
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.3751376920
Short name T727
Test name
Test status
Simulation time 100284737 ps
CPU time 2.44 seconds
Started Mar 17 02:42:57 PM PDT 24
Finished Mar 17 02:42:59 PM PDT 24
Peak memory 208616 kb
Host smart-d30383b2-516b-4d83-9bee-c765b84bdd16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751376920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.3751376920
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.2463803706
Short name T779
Test name
Test status
Simulation time 753328027 ps
CPU time 9.01 seconds
Started Mar 17 02:42:55 PM PDT 24
Finished Mar 17 02:43:04 PM PDT 24
Peak memory 209024 kb
Host smart-ecbf1d46-20b2-4132-9f45-ba00c2d0e105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463803706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.2463803706
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.1555713317
Short name T178
Test name
Test status
Simulation time 1388028554 ps
CPU time 9.86 seconds
Started Mar 17 02:42:53 PM PDT 24
Finished Mar 17 02:43:03 PM PDT 24
Peak memory 211200 kb
Host smart-e2574a9a-d833-4c35-830b-778576f976be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555713317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.1555713317
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.2300713175
Short name T590
Test name
Test status
Simulation time 12677540 ps
CPU time 0.76 seconds
Started Mar 17 02:43:00 PM PDT 24
Finished Mar 17 02:43:01 PM PDT 24
Peak memory 206448 kb
Host smart-a6f32c46-123a-4fcc-9e13-3980a33e4856
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2300713175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.2300713175
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.142228972
Short name T615
Test name
Test status
Simulation time 1010965678 ps
CPU time 24.07 seconds
Started Mar 17 02:43:00 PM PDT 24
Finished Mar 17 02:43:24 PM PDT 24
Peak memory 221924 kb
Host smart-d4451c2e-bb89-4cbb-ac77-bd9ca0d35e80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=142228972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.142228972
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.3287716946
Short name T266
Test name
Test status
Simulation time 241982047 ps
CPU time 2.6 seconds
Started Mar 17 02:43:00 PM PDT 24
Finished Mar 17 02:43:03 PM PDT 24
Peak memory 208200 kb
Host smart-b73745c9-443b-4ee8-af1f-c122d8fff14e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3287716946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.3287716946
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.1503779636
Short name T77
Test name
Test status
Simulation time 232020910 ps
CPU time 4.28 seconds
Started Mar 17 02:42:59 PM PDT 24
Finished Mar 17 02:43:03 PM PDT 24
Peak memory 208376 kb
Host smart-a0d5deba-1817-49ae-865f-4a46e419268d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1503779636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.1503779636
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.2160474732
Short name T255
Test name
Test status
Simulation time 104017893 ps
CPU time 3.66 seconds
Started Mar 17 02:43:00 PM PDT 24
Finished Mar 17 02:43:04 PM PDT 24
Peak memory 219092 kb
Host smart-c62df8af-5e05-471f-ab67-055eaa9ec1f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160474732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.2160474732
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.2790172042
Short name T780
Test name
Test status
Simulation time 944710998 ps
CPU time 6.86 seconds
Started Mar 17 02:43:00 PM PDT 24
Finished Mar 17 02:43:07 PM PDT 24
Peak memory 208216 kb
Host smart-d85a42f2-69df-48f7-abe9-d44d5ccfdff0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2790172042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.2790172042
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.683651464
Short name T656
Test name
Test status
Simulation time 299380807 ps
CPU time 4.78 seconds
Started Mar 17 02:43:04 PM PDT 24
Finished Mar 17 02:43:10 PM PDT 24
Peak memory 209272 kb
Host smart-23eaef24-6c03-43a5-b6c9-661c111b2079
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=683651464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.683651464
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.686341172
Short name T738
Test name
Test status
Simulation time 50528898 ps
CPU time 2.39 seconds
Started Mar 17 02:42:59 PM PDT 24
Finished Mar 17 02:43:01 PM PDT 24
Peak memory 209200 kb
Host smart-75fdf1d2-c77d-4aa4-a1fb-eff7d3f30a00
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=686341172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.686341172
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.2179602292
Short name T550
Test name
Test status
Simulation time 146815139 ps
CPU time 4.41 seconds
Started Mar 17 02:43:04 PM PDT 24
Finished Mar 17 02:43:09 PM PDT 24
Peak memory 208876 kb
Host smart-8f5742ba-1c91-48cf-9dbb-248a40948382
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2179602292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.2179602292
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.2380527083
Short name T662
Test name
Test status
Simulation time 79139638 ps
CPU time 3.77 seconds
Started Mar 17 02:42:59 PM PDT 24
Finished Mar 17 02:43:02 PM PDT 24
Peak memory 209800 kb
Host smart-e441f0e3-713a-479d-abde-913ef2bba8ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2380527083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.2380527083
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.678615686
Short name T450
Test name
Test status
Simulation time 104501442 ps
CPU time 4.09 seconds
Started Mar 17 02:42:56 PM PDT 24
Finished Mar 17 02:43:00 PM PDT 24
Peak memory 208736 kb
Host smart-f8b30d98-a610-40b3-8757-08d7c15e4588
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678615686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.678615686
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.1766139108
Short name T498
Test name
Test status
Simulation time 283764425 ps
CPU time 5.49 seconds
Started Mar 17 02:43:00 PM PDT 24
Finished Mar 17 02:43:06 PM PDT 24
Peak memory 218664 kb
Host smart-41b83a42-e464-4361-a24f-4d6d91368b90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1766139108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.1766139108
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.919900711
Short name T389
Test name
Test status
Simulation time 1018204281 ps
CPU time 2.9 seconds
Started Mar 17 02:42:59 PM PDT 24
Finished Mar 17 02:43:02 PM PDT 24
Peak memory 210140 kb
Host smart-0bc04420-3797-4746-b484-23a80f7c4be3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919900711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.919900711
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.2189218247
Short name T837
Test name
Test status
Simulation time 16468055 ps
CPU time 0.75 seconds
Started Mar 17 02:43:06 PM PDT 24
Finished Mar 17 02:43:06 PM PDT 24
Peak memory 206320 kb
Host smart-4540dfed-d1e3-45c6-a199-6285200ad3d7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189218247 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.2189218247
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.3998342284
Short name T391
Test name
Test status
Simulation time 516746651 ps
CPU time 3.92 seconds
Started Mar 17 02:43:08 PM PDT 24
Finished Mar 17 02:43:12 PM PDT 24
Peak memory 214740 kb
Host smart-722e8dfb-5350-4b1f-9f02-a186b879047d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3998342284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.3998342284
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.78492487
Short name T33
Test name
Test status
Simulation time 126900182 ps
CPU time 3.19 seconds
Started Mar 17 02:43:07 PM PDT 24
Finished Mar 17 02:43:10 PM PDT 24
Peak memory 216448 kb
Host smart-95f69246-0a70-4db4-a681-e5444e294382
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=78492487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.78492487
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.2267858771
Short name T254
Test name
Test status
Simulation time 88844686 ps
CPU time 4.17 seconds
Started Mar 17 02:43:04 PM PDT 24
Finished Mar 17 02:43:09 PM PDT 24
Peak memory 219036 kb
Host smart-23bc7c9b-71f9-4af0-863f-3dcfdfe06f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2267858771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.2267858771
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.2374184624
Short name T395
Test name
Test status
Simulation time 55563529 ps
CPU time 2.93 seconds
Started Mar 17 02:43:05 PM PDT 24
Finished Mar 17 02:43:08 PM PDT 24
Peak memory 221136 kb
Host smart-dbb8d779-ee7a-4d2b-b9ec-145bb7f5e551
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2374184624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.2374184624
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.1673334550
Short name T294
Test name
Test status
Simulation time 815211107 ps
CPU time 13.45 seconds
Started Mar 17 02:43:04 PM PDT 24
Finished Mar 17 02:43:17 PM PDT 24
Peak memory 210612 kb
Host smart-af8c8ca0-5771-4976-8fa9-8256e3a4d18a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673334550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.1673334550
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.2137973722
Short name T543
Test name
Test status
Simulation time 591561210 ps
CPU time 4.85 seconds
Started Mar 17 02:43:05 PM PDT 24
Finished Mar 17 02:43:10 PM PDT 24
Peak memory 209232 kb
Host smart-2c54d8fd-785f-48ab-8653-e5cf2d7dad26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2137973722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.2137973722
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.988273639
Short name T186
Test name
Test status
Simulation time 117617737 ps
CPU time 5.19 seconds
Started Mar 17 02:43:04 PM PDT 24
Finished Mar 17 02:43:09 PM PDT 24
Peak memory 208232 kb
Host smart-2bfd3bf0-5bec-493f-ae8a-e49d6217b28e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=988273639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.988273639
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.1985018121
Short name T216
Test name
Test status
Simulation time 90662554 ps
CPU time 2.16 seconds
Started Mar 17 02:43:06 PM PDT 24
Finished Mar 17 02:43:09 PM PDT 24
Peak memory 209132 kb
Host smart-05ff2c11-f354-48b2-b9ea-899611d99a46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985018121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.1985018121
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.3454332359
Short name T756
Test name
Test status
Simulation time 141779475 ps
CPU time 3.66 seconds
Started Mar 17 02:43:07 PM PDT 24
Finished Mar 17 02:43:11 PM PDT 24
Peak memory 209296 kb
Host smart-8cdedba6-15ba-43d2-af98-96d671d42d00
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3454332359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.3454332359
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.2869676387
Short name T704
Test name
Test status
Simulation time 291916475 ps
CPU time 6.78 seconds
Started Mar 17 02:43:05 PM PDT 24
Finished Mar 17 02:43:12 PM PDT 24
Peak memory 208392 kb
Host smart-f343afbe-4cee-43e3-a0eb-907c44f75f92
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2869676387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.2869676387
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.3608381785
Short name T492
Test name
Test status
Simulation time 90148389 ps
CPU time 2.16 seconds
Started Mar 17 02:43:06 PM PDT 24
Finished Mar 17 02:43:09 PM PDT 24
Peak memory 209132 kb
Host smart-fabdb41a-7dff-406a-93e6-cab665b52e42
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608381785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.3608381785
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.3908646174
Short name T187
Test name
Test status
Simulation time 721191662 ps
CPU time 7.02 seconds
Started Mar 17 02:43:05 PM PDT 24
Finished Mar 17 02:43:12 PM PDT 24
Peak memory 214728 kb
Host smart-3019c314-5007-42a3-8ef2-ddfe0a10af27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3908646174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.3908646174
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.573586950
Short name T768
Test name
Test status
Simulation time 116169429 ps
CPU time 3.81 seconds
Started Mar 17 02:43:00 PM PDT 24
Finished Mar 17 02:43:04 PM PDT 24
Peak memory 207568 kb
Host smart-7e8a0041-2cd8-473a-910a-1acebf0b4100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573586950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.573586950
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.2811585057
Short name T822
Test name
Test status
Simulation time 1905382228 ps
CPU time 13.69 seconds
Started Mar 17 02:43:06 PM PDT 24
Finished Mar 17 02:43:20 PM PDT 24
Peak memory 221080 kb
Host smart-86513309-22de-40eb-9288-000be0a7bc8b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2811585057 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.2811585057
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_stress_all_with_rand_reset.1708501238
Short name T776
Test name
Test status
Simulation time 495139961 ps
CPU time 20.43 seconds
Started Mar 17 02:43:06 PM PDT 24
Finished Mar 17 02:43:26 PM PDT 24
Peak memory 220748 kb
Host smart-fbb4306d-389f-44d9-90c9-09eeb92663d6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708501238 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all_with_rand_reset.1708501238
Directory /workspace/9.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.3455447541
Short name T808
Test name
Test status
Simulation time 57899696 ps
CPU time 3.58 seconds
Started Mar 17 02:43:08 PM PDT 24
Finished Mar 17 02:43:12 PM PDT 24
Peak memory 210072 kb
Host smart-1101d6eb-167c-4fcc-b355-888848dba8b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455447541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.3455447541
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.2193811029
Short name T800
Test name
Test status
Simulation time 47525442 ps
CPU time 1.33 seconds
Started Mar 17 02:43:05 PM PDT 24
Finished Mar 17 02:43:07 PM PDT 24
Peak memory 210152 kb
Host smart-c585e25f-93cc-4725-8573-9b3305be6b96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2193811029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.2193811029
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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