Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

Group : keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
74.60	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	1	13	92.86
Crosses	49	15	34	69.39

Variables for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
op_cp	5	1	4	80.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0
wip_cp	2	0	2	100.00	100	1	1	2

Crosses for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
state_x_wip_cross	14	1	13	92.86	100	1	1	0
state_x_op_cross	35	14	21	60.00	100	1	1	0

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	1	4	80.00

Automatically Generated Bins for op_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[OpDisable]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	50	1			T2	1		T13	1		T38	1
auto[OpGenId]	9	1			T190	1		T60	1		T47	1
auto[OpGenSwOut]	15	1			T27	1		T54	1		T47	1
auto[OpGenHwOut]	19	1			T4	1		T6	1		T232	1

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1639	1			T27	1		T29	1		T4	1
auto[StInit]	91	1			T13	1		T27	1		T4	1
auto[StCreatorRootKey]	45	1			T18	1		T19	1		T43	1
auto[StOwnerIntKey]	48	1			T2	1		T15	1		T16	1
auto[StOwnerKey]	33	1			T38	1		T58	1		T54	2
auto[StDisabled]	426	1			T27	12		T4	8		T102	8
auto[StInvalid]	46	1			T1	1		T37	1		T51	1

---

Summary for Variable wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wip_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3310

1

T1

2

T2

1

T3

1

auto[1]

93

1

T2

1

T13

1

T27

1

---

Summary for Cross state_x_wip_cross

Samples crossed: state_cp wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	14	1	13	92.86	1

Automatically Generated Cross Bins for state_x_wip_cross

Uncovered bins

state_cp	wip_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	[auto[1]]	0	1	1

Covered bins

state_cp	wip_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[0]	1630	1			T27	1		T29	1		T4	1
auto[StReset]	auto[1]	9	1			T47	1		T48	1		T49	1
auto[StInit]	auto[0]	40	1			T101	1		T30	1		T59	1
auto[StInit]	auto[1]	51	1			T13	1		T27	1		T4	1
auto[StCreatorRootKey]	auto[0]	33	1			T18	1		T19	1		T115	1
auto[StCreatorRootKey]	auto[1]	12	1			T43	1		T46	1		T47	1
auto[StOwnerIntKey]	auto[0]	38	1			T15	1		T16	1		T36	1
auto[StOwnerIntKey]	auto[1]	10	1			T2	1		T42	1		T65	1
auto[StOwnerKey]	auto[0]	26	1			T58	1		T54	1		T56	1
auto[StOwnerKey]	auto[1]	7	1			T38	1		T54	1		T59	1
auto[StDisabled]	auto[0]	422	1			T27	12		T4	8		T102	8
auto[StDisabled]	auto[1]	4	1			T60	1		T61	1		T233	1
auto[StInvalid]	auto[0]	46	1			T1	1		T37	1		T51	1

---

Summary for Cross state_x_op_cross

Samples crossed: state_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	14	21	60.00	14

Automatically Generated Cross Bins for state_x_op_cross

Element holes

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	*	--	--	5

Uncovered bins

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StReset]]	[auto[OpGenSwOut]]	0	1	1
[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[StInit] , auto[StCreatorRootKey]]	[auto[OpDisable]]	--	--	2
[auto[StOwnerIntKey]]	[auto[OpGenSwOut]]	0	1	1
[auto[StOwnerIntKey]]	[auto[OpDisable]]	0	1	1
[auto[StOwnerKey]]	[auto[OpGenId]]	0	1	1
[auto[StOwnerKey]]	[auto[OpDisable]]	0	1	1
[auto[StDisabled]]	[auto[OpDisable]]	0	1	1

Covered bins

state_cp	op_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[OpAdvance]	7	1			T47	1		T48	1		T49	1
auto[StReset]	auto[OpGenId]	1	1			T28	1		-	-		-	-
auto[StReset]	auto[OpGenHwOut]	1	1			T234	1		-	-		-	-
auto[StInit]	auto[OpAdvance]	27	1			T13	1		T235	1		T191	1
auto[StInit]	auto[OpGenId]	4	1			T190	1		T236	1		T237	1
auto[StInit]	auto[OpGenSwOut]	9	1			T27	1		T47	1		T238	1
auto[StInit]	auto[OpGenHwOut]	11	1			T4	1		T6	1		T44	1
auto[StCreatorRootKey]	auto[OpAdvance]	6	1			T43	1		T46	1		T239	1
auto[StCreatorRootKey]	auto[OpGenId]	2	1			T47	1		T82	1		-	-
auto[StCreatorRootKey]	auto[OpGenSwOut]	2	1			T8	1		T74	1		-	-
auto[StCreatorRootKey]	auto[OpGenHwOut]	2	1			T71	1		T240	1		-	-
auto[StOwnerIntKey]	auto[OpAdvance]	6	1			T2	1		T42	1		T65	1
auto[StOwnerIntKey]	auto[OpGenId]	1	1			T74	1		-	-		-	-
auto[StOwnerIntKey]	auto[OpGenHwOut]	3	1			T232	1		T241	1		T242	1
auto[StOwnerKey]	auto[OpAdvance]	3	1			T38	1		T59	1		T243	1
auto[StOwnerKey]	auto[OpGenSwOut]	3	1			T54	1		T244	1		T245	1
auto[StOwnerKey]	auto[OpGenHwOut]	1	1			T201	1		-	-		-	-
auto[StDisabled]	auto[OpAdvance]	1	1			T233	1		-	-		-	-
auto[StDisabled]	auto[OpGenId]	1	1			T60	1		-	-		-	-
auto[StDisabled]	auto[OpGenSwOut]	1	1			T61	1		-	-		-	-
auto[StDisabled]	auto[OpGenHwOut]	1	1			T237	1		-	-		-	-