Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
43.16	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	360	216	144	40.00

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	168	112	40.00	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11960

1

T1

13

T2

6

T3

15

auto[Attestation]

8094

1

T1

10

T2

2

T3

7

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2997	1			T1	3		T2	3		T3	3
auto[Aes]	3554	1			T1	4		T2	2		T3	5
auto[Kmac]	3548	1			T1	3		T3	3		T15	3
auto[Otbn]	3599	1			T1	4		T2	1		T3	3

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7901	1			T1	8		T2	3		T3	8
auto[OpGenId]	6356	1			T1	9		T2	2		T3	8
auto[OpGenSwOut]	6357	1			T1	6		T2	3		T3	7
auto[OpGenHwOut]	7341	1			T1	8		T2	3		T3	7
auto[OpDisable]	141	1			T45	1		T4	5		T46	4

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10393

1

T1

2

T2

5

T3

7

auto[OpDoneFail]

17703

1

T1

29

T2

6

T3

23

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6431	1			T1	1		T2	5		T3	11
auto[StInit]	4473	1			T1	5		T2	3		T3	4
auto[StCreatorRootKey]	3098	1			T1	1		T2	1		T3	4
auto[StOwnerIntKey]	2747	1			T2	2		T3	2		T12	2
auto[StOwnerKey]	2427	1			T3	2		T12	2		T14	2
auto[StDisabled]	7807	1			T3	7		T12	7		T14	7
auto[StInvalid]	1113	1			T1	24		T37	16		T51	34

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	168	112	40.00	168

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	325	1			T2	1		T12	2		T41	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	139	1			T16	1		T27	2		T85	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	79	1			T12	1		T41	1		T37	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	74	1			T216	1		T102	2		T46	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	68	1			T27	1		T217	1		T109	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	211	1			T12	1		T27	5		T122	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	35	1			T37	1		T53	1		T103	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	339	1			T2	1		T3	2		T12	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	122	1			T27	4		T84	2		T218	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	95	1			T15	1		T18	1		T27	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	59	1			T27	1		T4	1		T102	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	44	1			T219	1		T102	1		T46	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	222	1			T41	1		T27	2		T4	3
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	50	1			T1	1		T37	1		T51	3
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	323	1			T41	1		T27	2		T85	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	124	1			T16	1		T27	1		T38	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	78	1			T1	1		T27	1		T103	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	68	1			T4	1		T220	1		T46	4
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	54	1			T3	1		T4	1		T102	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	206	1			T41	3		T27	1		T218	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	31	1			T1	2		T51	1		T53	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	353	1			T3	2		T12	1		T41	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	132	1			T27	1		T4	2		T23	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	86	1			T4	2		T102	1		T221	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	80	1			T27	1		T222	1		T216	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	56	1			T27	1		T218	1		T102	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	213	1			T27	3		T85	1		T219	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	34	1			T1	1		T51	2		T52	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	77	1			T27	4		T52	1		T4	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	112	1			T2	1		T223	1		T23	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	78	1			T222	1		T102	3		T46	3
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	66	1			T27	2		T85	1		T102	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	63	1			T224	1		T225	1		T150	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	221	1			T27	4		T85	1		T226	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	45	1			T37	1		T52	1		T103	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	65	1			T27	9		T52	1		T102	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	132	1			T218	1		T51	1		T4	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	76	1			T226	1		T4	1		T65	4
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	78	1			T16	1		T216	1		T4	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	70	1			T27	1		T216	1		T123	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	218	1			T3	1		T27	3		T84	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	33	1			T51	1		T52	2		T103	3
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	81	1			T27	5		T52	1		T4	3
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	133	1			T3	1		T27	1		T37	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	81	1			T15	1		T27	1		T36	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	72	1			T15	1		T223	1		T216	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	66	1			T27	3		T123	1		T220	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	207	1			T27	2		T85	2		T86	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	33	1			T37	1		T51	1		T52	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	68	1			T27	3		T52	2		T4	5
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	123	1			T19	1		T102	1		T220	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	84	1			T16	1		T27	3		T4	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	60	1			T86	1		T38	1		T46	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	64	1			T27	1		T45	1		T217	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	216	1			T27	4		T84	1		T85	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	35	1			T1	1		T37	1		T51	3
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	274	1			T41	1		T27	3		T86	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	120	1			T1	1		T4	1		T23	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	63	1			T27	2		T84	1		T102	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	67	1			T2	1		T36	1		T217	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	69	1			T218	1		T4	1		T102	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	203	1			T27	10		T84	1		T86	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	22	1			T37	1		T51	1		T52	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	468	1			T3	1		T41	1		T27	4
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	143	1			T15	1		T27	1		T226	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	105	1			T36	1		T19	1		T4	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	88	1			T27	1		T85	1		T130	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	95	1			T27	1		T85	1		T130	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	274	1			T3	1		T27	3		T85	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	39	1			T1	1		T51	2		T53	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	464	1			T3	1		T45	1		T4	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	139	1			T27	1		T4	2		T102	3
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	101	1			T16	1		T27	1		T226	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	89	1			T16	1		T27	1		T222	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	92	1			T217	2		T102	2		T227	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	296	1			T27	2		T85	1		T226	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	34	1			T37	1		T51	2		T53	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	461	1			T3	1		T14	3		T17	11
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	149	1			T2	1		T13	1		T14	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	120	1			T14	1		T17	1		T84	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	89	1			T14	1		T17	1		T87	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	72	1			T17	1		T84	1		T218	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	282	1			T14	4		T17	3		T27	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	31	1			T1	1		T37	2		T51	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	54	1			T52	1		T4	1		T102	3
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	128	1			T3	1		T16	1		T27	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	71	1			T3	1		T222	1		T102	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	61	1			T3	1		T27	1		T38	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	56	1			T85	1		T102	2		T91	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	186	1			T27	5		T85	1		T86	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	30	1			T1	2		T52	1		T53	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	37	1			T27	2		T4	2		T102	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	134	1			T16	1		T27	2		T130	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	103	1			T130	1		T223	1		T4	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	84	1			T2	1		T216	1		T228	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	72	1			T123	1		T229	1		T230	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	277	1			T41	1		T27	4		T85	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	32	1			T1	2		T51	2		T52	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	53	1			T27	5		T52	1		T102	3
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	145	1			T27	1		T36	1		T19	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	118	1			T15	1		T18	1		T41	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	79	1			T102	1		T221	2		T147	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	87	1			T41	1		T27	1		T217	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	259	1			T27	4		T86	1		T218	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	35	1			T51	1		T25	1		T26	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	60	1			T27	1		T4	1		T102	4
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	149	1			T27	1		T231	1		T216	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	95	1			T18	1		T41	1		T84	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	91	1			T27	1		T222	1		T45	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	98	1			T14	1		T27	2		T84	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	258	1			T17	1		T27	1		T85	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	40	1			T1	1		T51	3		T53	2

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	205	1			T12	1		T41	1		T27	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	726	1			T2	1		T12	3		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	181	1			T15	1		T18	1		T27	3
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	750	1			T1	1		T2	1		T3	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	180	1			T3	1		T27	1		T4	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	704	1			T1	3		T16	1		T41	4
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	204	1			T27	2		T222	1		T218	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	750	1			T1	1		T3	2		T12	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	190	1			T27	1		T85	1		T222	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	472	1			T2	1		T27	9		T85	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	212	1			T16	1		T27	1		T226	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	460	1			T3	1		T27	12		T84	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	200	1			T15	2		T27	4		T36	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	473	1			T3	1		T27	8		T85	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	194	1			T16	1		T27	3		T86	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	456	1			T1	1		T27	8		T84	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	181	1			T2	1		T27	1		T36	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	637	1			T1	1		T41	1		T27	14
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	273	1			T27	2		T36	1		T85	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	939	1			T1	1		T3	2		T15	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	264	1			T16	2		T27	2		T226	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	951	1			T3	1		T27	3		T85	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	265	1			T14	2		T17	3		T84	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	939	1			T1	1		T2	1		T3	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	178	1			T3	1		T27	1		T85	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	408	1			T1	2		T3	2		T16	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	246	1			T2	1		T130	1		T223	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	493	1			T1	2		T16	1		T41	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	264	1			T15	1		T18	1		T41	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	512	1			T27	10		T36	1		T86	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	272	1			T14	1		T18	1		T41	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	519	1			T1	1		T17	1		T27	3