Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32135

1

T1

35

T2

13

T3

33

auto[1]

257

1

T41

7

T122

3

T123

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	32142	1			T1	35		T2	13		T3	33
auto[134217728:268435455]	9	1			T109	1		T390	2		T324	1
auto[268435456:402653183]	9	1			T150	1		T398	1		T391	1
auto[402653184:536870911]	7	1			T324	1		T407	1		T408	1
auto[536870912:671088639]	9	1			T41	1		T391	1		T324	1
auto[671088640:805306367]	12	1			T41	2		T122	1		T408	2
auto[805306368:939524095]	12	1			T109	1		T265	1		T324	2
auto[939524096:1073741823]	8	1			T409	1		T399	1		T410	1
auto[1073741824:1207959551]	9	1			T109	1		T150	1		T398	1
auto[1207959552:1342177279]	7	1			T123	1		T399	1		T285	1
auto[1342177280:1476395007]	6	1			T411	1		T412	1		T288	1
auto[1476395008:1610612735]	10	1			T140	1		T154	1		T409	1
auto[1610612736:1744830463]	7	1			T109	1		T391	1		T324	1
auto[1744830464:1879048191]	12	1			T398	1		T409	1		T391	1
auto[1879048192:2013265919]	5	1			T389	1		T391	1		T413	1
auto[2013265920:2147483647]	6	1			T398	1		T399	1		T285	1
auto[2147483648:2281701375]	10	1			T109	1		T140	1		T389	1
auto[2281701376:2415919103]	10	1			T41	1		T140	1		T265	1
auto[2415919104:2550136831]	5	1			T413	1		T414	1		T247	1
auto[2550136832:2684354559]	10	1			T109	1		T150	2		T399	1
auto[2684354560:2818572287]	9	1			T150	1		T389	1		T399	1
auto[2818572288:2952790015]	7	1			T109	2		T324	1		T285	1
auto[2952790016:3087007743]	7	1			T389	1		T324	1		T413	1
auto[3087007744:3221225471]	8	1			T122	1		T109	1		T409	1
auto[3221225472:3355443199]	7	1			T41	1		T287	1		T314	1
auto[3355443200:3489660927]	10	1			T391	1		T399	1		T285	2
auto[3489660928:3623878655]	8	1			T140	1		T154	1		T399	1
auto[3623878656:3758096383]	6	1			T409	1		T247	2		T343	1
auto[3758096384:3892314111]	6	1			T123	1		T140	1		T324	1
auto[3892314112:4026531839]	6	1			T150	1		T324	1		T408	1
auto[4026531840:4160749567]	6	1			T41	2		T150	1		T283	1
auto[4160749568:4294967295]	7	1			T150	2		T140	1		T407	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	32135	1			T1	35		T2	13		T3	33
auto[0:134217727]	auto[1]	7	1			T122	1		T123	1		T409	1
auto[134217728:268435455]	auto[1]	9	1			T109	1		T390	2		T324	1
auto[268435456:402653183]	auto[1]	9	1			T150	1		T398	1		T391	1
auto[402653184:536870911]	auto[1]	7	1			T324	1		T407	1		T408	1
auto[536870912:671088639]	auto[1]	9	1			T41	1		T391	1		T324	1
auto[671088640:805306367]	auto[1]	12	1			T41	2		T122	1		T408	2
auto[805306368:939524095]	auto[1]	12	1			T109	1		T265	1		T324	2
auto[939524096:1073741823]	auto[1]	8	1			T409	1		T399	1		T410	1
auto[1073741824:1207959551]	auto[1]	9	1			T109	1		T150	1		T398	1
auto[1207959552:1342177279]	auto[1]	7	1			T123	1		T399	1		T285	1
auto[1342177280:1476395007]	auto[1]	6	1			T411	1		T412	1		T288	1
auto[1476395008:1610612735]	auto[1]	10	1			T140	1		T154	1		T409	1
auto[1610612736:1744830463]	auto[1]	7	1			T109	1		T391	1		T324	1
auto[1744830464:1879048191]	auto[1]	12	1			T398	1		T409	1		T391	1
auto[1879048192:2013265919]	auto[1]	5	1			T389	1		T391	1		T413	1
auto[2013265920:2147483647]	auto[1]	6	1			T398	1		T399	1		T285	1
auto[2147483648:2281701375]	auto[1]	10	1			T109	1		T140	1		T389	1
auto[2281701376:2415919103]	auto[1]	10	1			T41	1		T140	1		T265	1
auto[2415919104:2550136831]	auto[1]	5	1			T413	1		T414	1		T247	1
auto[2550136832:2684354559]	auto[1]	10	1			T109	1		T150	2		T399	1
auto[2684354560:2818572287]	auto[1]	9	1			T150	1		T389	1		T399	1
auto[2818572288:2952790015]	auto[1]	7	1			T109	2		T324	1		T285	1
auto[2952790016:3087007743]	auto[1]	7	1			T389	1		T324	1		T413	1
auto[3087007744:3221225471]	auto[1]	8	1			T122	1		T109	1		T409	1
auto[3221225472:3355443199]	auto[1]	7	1			T41	1		T287	1		T314	1
auto[3355443200:3489660927]	auto[1]	10	1			T391	1		T399	1		T285	2
auto[3489660928:3623878655]	auto[1]	8	1			T140	1		T154	1		T399	1
auto[3623878656:3758096383]	auto[1]	6	1			T409	1		T247	2		T343	1
auto[3758096384:3892314111]	auto[1]	6	1			T123	1		T140	1		T324	1
auto[3892314112:4026531839]	auto[1]	6	1			T150	1		T324	1		T408	1
auto[4026531840:4160749567]	auto[1]	6	1			T41	2		T150	1		T283	1
auto[4160749568:4294967295]	auto[1]	7	1			T150	2		T140	1		T407	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1616

1

T1

5

T2

3

T3

1

auto[1]

1749

1

T1

1

T2

2

T3

5

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	96	1			T27	1		T52	1		T23	1
auto[134217728:268435455]	85	1			T53	1		T4	2		T103	1
auto[268435456:402653183]	110	1			T27	1		T218	1		T122	1
auto[402653184:536870911]	103	1			T27	1		T217	1		T52	1
auto[536870912:671088639]	116	1			T1	1		T41	1		T27	3
auto[671088640:805306367]	102	1			T15	1		T102	2		T42	1
auto[805306368:939524095]	89	1			T37	1		T29	1		T4	2
auto[939524096:1073741823]	106	1			T85	1		T216	1		T4	1
auto[1073741824:1207959551]	110	1			T2	1		T15	1		T85	1
auto[1207959552:1342177279]	108	1			T27	2		T222	1		T4	3
auto[1342177280:1476395007]	110	1			T2	1		T13	1		T85	1
auto[1476395008:1610612735]	95	1			T3	1		T27	1		T51	1
auto[1610612736:1744830463]	122	1			T1	1		T16	1		T27	3
auto[1744830464:1879048191]	123	1			T3	1		T45	1		T53	1
auto[1879048192:2013265919]	106	1			T3	1		T41	1		T4	2
auto[2013265920:2147483647]	110	1			T27	1		T226	1		T52	1
auto[2147483648:2281701375]	100	1			T41	1		T27	2		T85	1
auto[2281701376:2415919103]	108	1			T27	1		T84	1		T45	1
auto[2415919104:2550136831]	114	1			T3	1		T27	1		T86	1
auto[2550136832:2684354559]	107	1			T1	1		T2	1		T27	1
auto[2684354560:2818572287]	96	1			T27	1		T218	1		T4	2
auto[2818572288:2952790015]	98	1			T85	1		T52	2		T216	1
auto[2952790016:3087007743]	87	1			T1	1		T37	1		T4	1
auto[3087007744:3221225471]	117	1			T1	1		T15	1		T86	1
auto[3221225472:3355443199]	92	1			T218	1		T53	1		T221	1
auto[3355443200:3489660927]	102	1			T2	1		T226	1		T218	1
auto[3489660928:3623878655]	113	1			T3	2		T41	1		T27	1
auto[3623878656:3758096383]	114	1			T2	1		T84	1		T102	2
auto[3758096384:3892314111]	112	1			T1	1		T27	1		T85	1
auto[3892314112:4026531839]	102	1			T27	1		T84	1		T217	1
auto[4026531840:4160749567]	110	1			T85	1		T222	1		T38	1
auto[4160749568:4294967295]	102	1			T15	1		T16	1		T41	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	44	1			T27	1		T23	1		T109	1
auto[0:134217727]	auto[1]	52	1			T52	1		T122	1		T46	2
auto[134217728:268435455]	auto[0]	41	1			T53	1		T4	2		T42	1
auto[134217728:268435455]	auto[1]	44	1			T103	1		T102	1		T228	1
auto[268435456:402653183]	auto[0]	45	1			T27	1		T123	1		T46	2
auto[268435456:402653183]	auto[1]	65	1			T218	1		T122	1		T109	1
auto[402653184:536870911]	auto[0]	46	1			T52	1		T102	1		T6	1
auto[402653184:536870911]	auto[1]	57	1			T27	1		T217	1		T46	1
auto[536870912:671088639]	auto[0]	59	1			T1	1		T41	1		T27	1
auto[536870912:671088639]	auto[1]	57	1			T27	2		T226	1		T37	1
auto[671088640:805306367]	auto[0]	48	1			T42	1		T6	1		T25	1
auto[671088640:805306367]	auto[1]	54	1			T15	1		T102	2		T64	1
auto[805306368:939524095]	auto[0]	42	1			T37	1		T29	1		T4	1
auto[805306368:939524095]	auto[1]	47	1			T4	1		T55	1		T94	1
auto[939524096:1073741823]	auto[0]	56	1			T85	1		T102	2		T46	1
auto[939524096:1073741823]	auto[1]	50	1			T216	1		T4	1		T102	1
auto[1073741824:1207959551]	auto[0]	53	1			T2	1		T15	1		T86	1
auto[1073741824:1207959551]	auto[1]	57	1			T85	1		T19	1		T4	1
auto[1207959552:1342177279]	auto[0]	46	1			T27	1		T222	1		T4	1
auto[1207959552:1342177279]	auto[1]	62	1			T27	1		T4	2		T102	1
auto[1342177280:1476395007]	auto[0]	59	1			T2	1		T13	1		T85	1
auto[1342177280:1476395007]	auto[1]	51	1			T4	1		T102	1		T46	2
auto[1476395008:1610612735]	auto[0]	44	1			T3	1		T4	1		T102	1
auto[1476395008:1610612735]	auto[1]	51	1			T27	1		T51	1		T102	1
auto[1610612736:1744830463]	auto[0]	61	1			T1	1		T27	2		T217	1
auto[1610612736:1744830463]	auto[1]	61	1			T16	1		T27	1		T226	1
auto[1744830464:1879048191]	auto[0]	64	1			T45	1		T53	1		T91	1
auto[1744830464:1879048191]	auto[1]	59	1			T3	1		T122	1		T102	2
auto[1879048192:2013265919]	auto[0]	52	1			T41	1		T4	2		T46	1
auto[1879048192:2013265919]	auto[1]	54	1			T3	1		T102	1		T43	1
auto[2013265920:2147483647]	auto[0]	60	1			T226	1		T221	1		T42	1
auto[2013265920:2147483647]	auto[1]	50	1			T27	1		T52	1		T216	1
auto[2147483648:2281701375]	auto[0]	47	1			T41	1		T218	1		T4	1
auto[2147483648:2281701375]	auto[1]	53	1			T27	2		T85	1		T51	1
auto[2281701376:2415919103]	auto[0]	55	1			T45	1		T4	1		T23	1
auto[2281701376:2415919103]	auto[1]	53	1			T27	1		T84	1		T4	2
auto[2415919104:2550136831]	auto[0]	65	1			T27	1		T45	1		T218	1
auto[2415919104:2550136831]	auto[1]	49	1			T3	1		T86	1		T4	1
auto[2550136832:2684354559]	auto[0]	40	1			T2	1		T216	1		T102	1
auto[2550136832:2684354559]	auto[1]	67	1			T1	1		T27	1		T85	1
auto[2684354560:2818572287]	auto[0]	44	1			T27	1		T25	1		T54	1
auto[2684354560:2818572287]	auto[1]	52	1			T218	1		T4	2		T293	1
auto[2818572288:2952790015]	auto[0]	50	1			T52	1		T23	1		T102	1
auto[2818572288:2952790015]	auto[1]	48	1			T85	1		T52	1		T216	1
auto[2952790016:3087007743]	auto[0]	40	1			T1	1		T102	1		T95	1
auto[2952790016:3087007743]	auto[1]	47	1			T37	1		T4	1		T65	1
auto[3087007744:3221225471]	auto[0]	59	1			T1	1		T15	1		T86	1
auto[3087007744:3221225471]	auto[1]	58	1			T102	1		T46	1		T65	2
auto[3221225472:3355443199]	auto[0]	33	1			T53	1		T150	1		T26	1
auto[3221225472:3355443199]	auto[1]	59	1			T218	1		T221	1		T228	1
auto[3355443200:3489660927]	auto[0]	58	1			T218	1		T102	2		T46	2
auto[3355443200:3489660927]	auto[1]	44	1			T2	1		T226	1		T96	1
auto[3489660928:3623878655]	auto[0]	56	1			T41	1		T216	1		T46	1
auto[3489660928:3623878655]	auto[1]	57	1			T3	2		T27	1		T226	1
auto[3623878656:3758096383]	auto[0]	40	1			T84	1		T102	1		T46	1
auto[3623878656:3758096383]	auto[1]	74	1			T2	1		T102	1		T46	1
auto[3758096384:3892314111]	auto[0]	54	1			T1	1		T52	1		T102	1
auto[3758096384:3892314111]	auto[1]	58	1			T27	1		T85	1		T37	1
auto[3892314112:4026531839]	auto[0]	56	1			T84	1		T217	1		T42	1
auto[3892314112:4026531839]	auto[1]	46	1			T27	1		T46	2		T26	1
auto[4026531840:4160749567]	auto[0]	52	1			T122	1		T102	1		T42	1
auto[4026531840:4160749567]	auto[1]	58	1			T85	1		T222	1		T38	1
auto[4160749568:4294967295]	auto[0]	47	1			T41	1		T4	1		T102	2
auto[4160749568:4294967295]	auto[1]	55	1			T15	1		T16	1		T4	2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1629

1

T1

5

T2

2

T3

2

auto[1]

1737

1

T1

1

T2

3

T3

4

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	101	1			T27	1		T85	1		T103	2
auto[134217728:268435455]	112	1			T15	1		T27	3		T84	1
auto[268435456:402653183]	112	1			T1	1		T3	1		T15	1
auto[402653184:536870911]	100	1			T27	1		T216	1		T102	1
auto[536870912:671088639]	103	1			T3	1		T41	1		T46	1
auto[671088640:805306367]	109	1			T4	1		T102	1		T228	1
auto[805306368:939524095]	110	1			T226	1		T217	1		T51	1
auto[939524096:1073741823]	127	1			T1	1		T2	1		T27	1
auto[1073741824:1207959551]	106	1			T27	1		T226	1		T217	1
auto[1207959552:1342177279]	113	1			T27	2		T37	1		T218	1
auto[1342177280:1476395007]	105	1			T41	1		T27	1		T37	1
auto[1476395008:1610612735]	102	1			T27	1		T85	1		T37	2
auto[1610612736:1744830463]	112	1			T1	1		T3	1		T102	2
auto[1744830464:1879048191]	101	1			T27	2		T84	1		T45	1
auto[1879048192:2013265919]	98	1			T3	1		T85	1		T45	1
auto[2013265920:2147483647]	96	1			T27	1		T226	1		T216	1
auto[2147483648:2281701375]	103	1			T85	1		T4	1		T102	2
auto[2281701376:2415919103]	114	1			T15	1		T85	1		T86	1
auto[2415919104:2550136831]	99	1			T1	1		T27	1		T4	1
auto[2550136832:2684354559]	98	1			T16	1		T4	1		T102	3
auto[2684354560:2818572287]	93	1			T27	1		T4	4		T123	1
auto[2818572288:2952790015]	97	1			T16	1		T4	1		T122	1
auto[2952790016:3087007743]	105	1			T85	1		T43	2		T55	1
auto[3087007744:3221225471]	121	1			T86	1		T226	1		T45	1
auto[3221225472:3355443199]	109	1			T1	1		T27	1		T222	1
auto[3355443200:3489660927]	103	1			T2	1		T226	1		T19	1
auto[3489660928:3623878655]	99	1			T15	1		T27	1		T85	1
auto[3623878656:3758096383]	85	1			T3	1		T41	1		T27	1
auto[3758096384:3892314111]	97	1			T1	1		T13	1		T52	1
auto[3892314112:4026531839]	111	1			T2	1		T27	1		T52	1
auto[4026531840:4160749567]	108	1			T2	1		T3	1		T41	1
auto[4160749568:4294967295]	117	1			T2	1		T41	1		T27	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	48	1			T103	1		T46	1		T65	1
auto[0:134217727]	auto[1]	53	1			T27	1		T85	1		T103	1
auto[134217728:268435455]	auto[0]	59	1			T27	1		T84	1		T52	1
auto[134217728:268435455]	auto[1]	53	1			T15	1		T27	2		T46	3
auto[268435456:402653183]	auto[0]	56	1			T1	1		T3	1		T15	1
auto[268435456:402653183]	auto[1]	56	1			T19	1		T4	2		T102	3
auto[402653184:536870911]	auto[0]	48	1			T27	1		T102	1		T46	2
auto[402653184:536870911]	auto[1]	52	1			T216	1		T94	1		T65	2
auto[536870912:671088639]	auto[0]	51	1			T3	1		T41	1		T150	1
auto[536870912:671088639]	auto[1]	52	1			T46	1		T65	1		T25	1
auto[671088640:805306367]	auto[0]	61	1			T102	1		T46	1		T143	1
auto[671088640:805306367]	auto[1]	48	1			T4	1		T228	1		T46	1
auto[805306368:939524095]	auto[0]	46	1			T217	1		T53	1		T102	1
auto[805306368:939524095]	auto[1]	64	1			T226	1		T51	1		T66	1
auto[939524096:1073741823]	auto[0]	61	1			T1	1		T27	1		T86	1
auto[939524096:1073741823]	auto[1]	66	1			T2	1		T222	1		T218	1
auto[1073741824:1207959551]	auto[0]	50	1			T217	1		T102	1		T42	2
auto[1073741824:1207959551]	auto[1]	56	1			T27	1		T226	1		T216	1
auto[1207959552:1342177279]	auto[0]	53	1			T37	1		T218	1		T216	1
auto[1207959552:1342177279]	auto[1]	60	1			T27	2		T221	1		T24	1
auto[1342177280:1476395007]	auto[0]	57	1			T41	1		T4	1		T46	1
auto[1342177280:1476395007]	auto[1]	48	1			T27	1		T37	1		T150	1
auto[1476395008:1610612735]	auto[0]	53	1			T37	1		T217	1		T4	1
auto[1476395008:1610612735]	auto[1]	49	1			T27	1		T85	1		T37	1
auto[1610612736:1744830463]	auto[0]	51	1			T1	1		T228	1		T46	3
auto[1610612736:1744830463]	auto[1]	61	1			T3	1		T102	2		T46	1
auto[1744830464:1879048191]	auto[0]	45	1			T27	1		T52	2		T53	1
auto[1744830464:1879048191]	auto[1]	56	1			T27	1		T84	1		T45	1
auto[1879048192:2013265919]	auto[0]	45	1			T85	1		T45	1		T90	1
auto[1879048192:2013265919]	auto[1]	53	1			T3	1		T4	2		T102	1
auto[2013265920:2147483647]	auto[0]	41	1			T27	1		T216	1		T102	1
auto[2013265920:2147483647]	auto[1]	55	1			T226	1		T102	2		T91	1
auto[2147483648:2281701375]	auto[0]	43	1			T102	1		T46	1		T111	1
auto[2147483648:2281701375]	auto[1]	60	1			T85	1		T4	1		T102	1
auto[2281701376:2415919103]	auto[0]	59	1			T85	1		T53	1		T4	1
auto[2281701376:2415919103]	auto[1]	55	1			T15	1		T86	1		T4	1
auto[2415919104:2550136831]	auto[0]	52	1			T1	1		T122	1		T6	1
auto[2415919104:2550136831]	auto[1]	47	1			T27	1		T4	1		T46	1
auto[2550136832:2684354559]	auto[0]	48	1			T16	1		T4	1		T102	2
auto[2550136832:2684354559]	auto[1]	50	1			T102	1		T46	1		T144	1
auto[2684354560:2818572287]	auto[0]	44	1			T27	1		T4	2		T102	1
auto[2684354560:2818572287]	auto[1]	49	1			T4	2		T123	1		T102	2
auto[2818572288:2952790015]	auto[0]	51	1			T4	1		T221	1		T46	2
auto[2818572288:2952790015]	auto[1]	46	1			T16	1		T122	1		T46	1
auto[2952790016:3087007743]	auto[0]	61	1			T43	1		T293	1		T270	1
auto[2952790016:3087007743]	auto[1]	44	1			T85	1		T43	1		T55	1
auto[3087007744:3221225471]	auto[0]	59	1			T45	1		T46	1		T65	1
auto[3087007744:3221225471]	auto[1]	62	1			T86	1		T226	1		T4	1
auto[3221225472:3355443199]	auto[0]	52	1			T222	1		T46	2		T65	1
auto[3221225472:3355443199]	auto[1]	57	1			T1	1		T27	1		T52	1
auto[3355443200:3489660927]	auto[0]	47	1			T2	1		T109	1		T54	1
auto[3355443200:3489660927]	auto[1]	56	1			T226	1		T19	1		T53	1
auto[3489660928:3623878655]	auto[0]	41	1			T15	1		T218	1		T52	1
auto[3489660928:3623878655]	auto[1]	58	1			T27	1		T85	1		T4	2
auto[3623878656:3758096383]	auto[0]	41	1			T41	1		T102	1		T6	1
auto[3623878656:3758096383]	auto[1]	44	1			T3	1		T27	1		T217	1
auto[3758096384:3892314111]	auto[0]	49	1			T1	1		T52	1		T4	2
auto[3758096384:3892314111]	auto[1]	48	1			T13	1		T102	1		T221	1
auto[3892314112:4026531839]	auto[0]	54	1			T4	1		T43	1		T95	1
auto[3892314112:4026531839]	auto[1]	57	1			T2	1		T27	1		T52	1
auto[4026531840:4160749567]	auto[0]	54	1			T41	1		T27	1		T84	1
auto[4026531840:4160749567]	auto[1]	54	1			T2	1		T3	1		T51	1
auto[4160749568:4294967295]	auto[0]	49	1			T2	1		T41	1		T46	2
auto[4160749568:4294967295]	auto[1]	68	1			T27	1		T85	1		T218	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1631

1

T1

5

T2

3

T3

1

auto[1]

1734

1

T1

1

T2

2

T3

5

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	98	1			T2	1		T3	1		T37	1
auto[134217728:268435455]	107	1			T3	1		T15	1		T84	1
auto[268435456:402653183]	109	1			T1	1		T27	1		T84	1
auto[402653184:536870911]	118	1			T84	1		T218	1		T122	1
auto[536870912:671088639]	115	1			T15	1		T41	1		T85	1
auto[671088640:805306367]	94	1			T27	1		T85	1		T4	1
auto[805306368:939524095]	121	1			T27	1		T85	1		T86	1
auto[939524096:1073741823]	113	1			T3	1		T102	3		T46	4
auto[1073741824:1207959551]	106	1			T27	2		T4	1		T23	1
auto[1207959552:1342177279]	91	1			T2	1		T51	1		T102	1
auto[1342177280:1476395007]	103	1			T1	2		T27	2		T218	1
auto[1476395008:1610612735]	103	1			T1	1		T45	1		T4	1
auto[1610612736:1744830463]	88	1			T27	2		T226	1		T38	1
auto[1744830464:1879048191]	117	1			T2	1		T27	1		T85	2
auto[1879048192:2013265919]	111	1			T41	1		T27	1		T45	1
auto[2013265920:2147483647]	86	1			T1	1		T45	1		T52	1
auto[2147483648:2281701375]	106	1			T2	1		T41	1		T4	2
auto[2281701376:2415919103]	114	1			T15	1		T16	1		T27	1
auto[2415919104:2550136831]	93	1			T27	2		T85	1		T4	1
auto[2550136832:2684354559]	114	1			T1	1		T13	1		T27	1
auto[2684354560:2818572287]	108	1			T86	1		T37	1		T53	1
auto[2818572288:2952790015]	100	1			T27	2		T217	1		T4	1
auto[2952790016:3087007743]	83	1			T4	1		T102	2		T46	2
auto[3087007744:3221225471]	99	1			T3	1		T226	1		T4	2
auto[3221225472:3355443199]	105	1			T27	3		T226	1		T51	1
auto[3355443200:3489660927]	112	1			T2	1		T15	1		T41	1
auto[3489660928:3623878655]	95	1			T4	2		T42	1		T46	2
auto[3623878656:3758096383]	102	1			T216	1		T102	2		T221	1
auto[3758096384:3892314111]	119	1			T3	1		T53	1		T102	3
auto[3892314112:4026531839]	115	1			T41	1		T19	1		T217	1
auto[4026531840:4160749567]	106	1			T3	1		T16	1		T85	2
auto[4160749568:4294967295]	114	1			T27	2		T222	1		T218	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	48	1			T218	1		T102	1		T150	1
auto[0:134217727]	auto[1]	50	1			T2	1		T3	1		T37	1
auto[134217728:268435455]	auto[0]	55	1			T15	1		T84	1		T4	2
auto[134217728:268435455]	auto[1]	52	1			T3	1		T52	1		T228	1
auto[268435456:402653183]	auto[0]	59	1			T1	1		T52	1		T29	1
auto[268435456:402653183]	auto[1]	50	1			T27	1		T84	1		T226	1
auto[402653184:536870911]	auto[0]	59	1			T84	1		T218	1		T102	1
auto[402653184:536870911]	auto[1]	59	1			T122	1		T102	4		T46	1
auto[536870912:671088639]	auto[0]	54	1			T15	1		T41	1		T4	1
auto[536870912:671088639]	auto[1]	61	1			T85	1		T226	1		T4	1
auto[671088640:805306367]	auto[0]	45	1			T27	1		T85	1		T4	1
auto[671088640:805306367]	auto[1]	49	1			T122	1		T46	1		T94	1
auto[805306368:939524095]	auto[0]	52	1			T27	1		T46	1		T24	1
auto[805306368:939524095]	auto[1]	69	1			T85	1		T86	1		T19	1
auto[939524096:1073741823]	auto[0]	61	1			T102	2		T46	2		T6	1
auto[939524096:1073741823]	auto[1]	52	1			T3	1		T102	1		T46	2
auto[1073741824:1207959551]	auto[0]	46	1			T27	1		T23	1		T221	1
auto[1073741824:1207959551]	auto[1]	60	1			T27	1		T4	1		T122	1
auto[1207959552:1342177279]	auto[0]	47	1			T2	1		T102	1		T46	1
auto[1207959552:1342177279]	auto[1]	44	1			T51	1		T91	1		T46	1
auto[1342177280:1476395007]	auto[0]	49	1			T1	2		T27	1		T218	1
auto[1342177280:1476395007]	auto[1]	54	1			T27	1		T4	1		T293	1
auto[1476395008:1610612735]	auto[0]	52	1			T45	1		T46	1		T235	1
auto[1476395008:1610612735]	auto[1]	51	1			T1	1		T4	1		T109	1
auto[1610612736:1744830463]	auto[0]	36	1			T27	1		T216	1		T46	1
auto[1610612736:1744830463]	auto[1]	52	1			T27	1		T226	1		T38	1
auto[1744830464:1879048191]	auto[0]	58	1			T2	1		T85	1		T102	1
auto[1744830464:1879048191]	auto[1]	59	1			T27	1		T85	1		T4	1
auto[1879048192:2013265919]	auto[0]	50	1			T41	1		T217	1		T102	1
auto[1879048192:2013265919]	auto[1]	61	1			T27	1		T45	1		T4	2
auto[2013265920:2147483647]	auto[0]	42	1			T1	1		T45	1		T52	1
auto[2013265920:2147483647]	auto[1]	44	1			T216	1		T122	1		T109	1
auto[2147483648:2281701375]	auto[0]	49	1			T41	1		T91	1		T42	1
auto[2147483648:2281701375]	auto[1]	57	1			T2	1		T4	2		T43	1
auto[2281701376:2415919103]	auto[0]	60	1			T27	1		T4	2		T23	1
auto[2281701376:2415919103]	auto[1]	54	1			T15	1		T16	1		T218	1
auto[2415919104:2550136831]	auto[0]	47	1			T27	1		T4	1		T102	1
auto[2415919104:2550136831]	auto[1]	46	1			T27	1		T85	1		T102	1
auto[2550136832:2684354559]	auto[0]	55	1			T1	1		T13	1		T27	1
auto[2550136832:2684354559]	auto[1]	59	1			T37	1		T216	2		T4	1
auto[2684354560:2818572287]	auto[0]	55	1			T86	1		T53	1		T43	1
auto[2684354560:2818572287]	auto[1]	53	1			T37	1		T123	1		T102	1
auto[2818572288:2952790015]	auto[0]	54	1			T27	1		T4	1		T109	1
auto[2818572288:2952790015]	auto[1]	46	1			T27	1		T217	1		T293	1
auto[2952790016:3087007743]	auto[0]	43	1			T102	2		T46	1		T25	1
auto[2952790016:3087007743]	auto[1]	40	1			T4	1		T46	1		T252	1
auto[3087007744:3221225471]	auto[0]	42	1			T46	1		T111	1		T26	1
auto[3087007744:3221225471]	auto[1]	57	1			T3	1		T226	1		T4	2
auto[3221225472:3355443199]	auto[0]	50	1			T52	1		T42	1		T293	1
auto[3221225472:3355443199]	auto[1]	55	1			T27	3		T226	1		T51	1
auto[3355443200:3489660927]	auto[0]	57	1			T2	1		T41	1		T103	1
auto[3355443200:3489660927]	auto[1]	55	1			T15	1		T222	1		T46	2
auto[3489660928:3623878655]	auto[0]	43	1			T4	1		T42	1		T65	1
auto[3489660928:3623878655]	auto[1]	52	1			T4	1		T46	2		T65	1
auto[3623878656:3758096383]	auto[0]	51	1			T216	1		T235	1		T88	2
auto[3623878656:3758096383]	auto[1]	51	1			T102	2		T221	1		T24	1
auto[3758096384:3892314111]	auto[0]	55	1			T3	1		T53	1		T46	2
auto[3758096384:3892314111]	auto[1]	64	1			T102	3		T46	1		T65	1
auto[3892314112:4026531839]	auto[0]	55	1			T41	1		T4	1		T228	1
auto[3892314112:4026531839]	auto[1]	60	1			T19	1		T217	1		T52	1
auto[4026531840:4160749567]	auto[0]	47	1			T16	1		T217	1		T52	2
auto[4026531840:4160749567]	auto[1]	59	1			T3	1		T85	2		T4	1
auto[4160749568:4294967295]	auto[0]	55	1			T222	1		T218	1		T4	1
auto[4160749568:4294967295]	auto[1]	59	1			T27	2		T218	1		T4	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1618

1

T1

4

T2

3

T3

1

auto[1]

1747

1

T1

2

T2

2

T3

5

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	99	1			T27	1		T37	1		T216	1
auto[134217728:268435455]	114	1			T27	1		T226	1		T52	1
auto[268435456:402653183]	99	1			T2	1		T84	1		T216	1
auto[402653184:536870911]	122	1			T1	2		T4	2		T122	1
auto[536870912:671088639]	118	1			T15	1		T27	2		T102	2
auto[671088640:805306367]	89	1			T41	1		T4	1		T109	1
auto[805306368:939524095]	100	1			T27	1		T85	1		T216	1
auto[939524096:1073741823]	118	1			T16	1		T84	1		T218	2
auto[1073741824:1207959551]	109	1			T15	1		T45	1		T52	2
auto[1207959552:1342177279]	116	1			T1	1		T27	1		T218	1
auto[1342177280:1476395007]	118	1			T15	1		T41	1		T27	2
auto[1476395008:1610612735]	107	1			T1	1		T3	1		T41	1
auto[1610612736:1744830463]	87	1			T19	1		T218	1		T29	1
auto[1744830464:1879048191]	114	1			T2	1		T27	1		T23	1
auto[1879048192:2013265919]	118	1			T37	2		T217	2		T4	1
auto[2013265920:2147483647]	100	1			T1	1		T85	1		T51	1
auto[2147483648:2281701375]	107	1			T226	1		T102	2		T42	1
auto[2281701376:2415919103]	92	1			T27	1		T85	2		T216	1
auto[2415919104:2550136831]	111	1			T3	1		T27	2		T37	1
auto[2550136832:2684354559]	118	1			T13	1		T85	1		T226	1
auto[2684354560:2818572287]	96	1			T27	1		T217	1		T123	1
auto[2818572288:2952790015]	113	1			T27	2		T85	2		T86	1
auto[2952790016:3087007743]	109	1			T2	1		T3	1		T16	1
auto[3087007744:3221225471]	77	1			T3	1		T52	1		T102	1
auto[3221225472:3355443199]	102	1			T4	2		T102	1		T46	2
auto[3355443200:3489660927]	83	1			T3	1		T226	1		T52	1
auto[3489660928:3623878655]	101	1			T15	1		T102	2		T109	1
auto[3623878656:3758096383]	105	1			T1	1		T41	1		T27	1
auto[3758096384:3892314111]	103	1			T2	1		T27	1		T222	1
auto[3892314112:4026531839]	115	1			T2	1		T3	1		T27	2
auto[4026531840:4160749567]	99	1			T41	1		T27	1		T222	1
auto[4160749568:4294967295]	106	1			T122	1		T91	1		T46	2