dashboard | hierarchy | modlist | groups | tests | asserts

Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2997 1 T1 6 T2 3 T3 6
auto[1] 233 1 T41 5 T123 7 T109 4


Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] 107 1 T4 1 T102 1 T46 2
auto[134217728:268435455] 95 1 T1 1 T3 1 T27 1
auto[268435456:402653183] 98 1 T1 1 T27 2 T85 1
auto[402653184:536870911] 105 1 T3 1 T15 1 T41 1
auto[536870912:671088639] 96 1 T41 1 T27 2 T85 1
auto[671088640:805306367] 125 1 T4 2 T122 2 T123 1
auto[805306368:939524095] 112 1 T3 1 T27 2 T86 1
auto[939524096:1073741823] 103 1 T27 1 T53 1 T111 1
auto[1073741824:1207959551] 100 1 T2 1 T3 1 T13 1
auto[1207959552:1342177279] 103 1 T41 2 T27 1 T37 1
auto[1342177280:1476395007] 94 1 T27 1 T4 1 T123 1
auto[1476395008:1610612735] 122 1 T1 1 T41 1 T27 1
auto[1610612736:1744830463] 100 1 T86 1 T218 1 T217 2
auto[1744830464:1879048191] 96 1 T1 1 T51 1 T53 1
auto[1879048192:2013265919] 110 1 T27 1 T85 1 T216 1
auto[2013265920:2147483647] 91 1 T85 1 T216 1 T4 2
auto[2147483648:2281701375] 92 1 T1 1 T41 1 T85 2
auto[2281701376:2415919103] 97 1 T15 1 T216 1 T123 1
auto[2415919104:2550136831] 104 1 T2 1 T102 2 T46 2
auto[2550136832:2684354559] 102 1 T4 1 T103 1 T102 1
auto[2684354560:2818572287] 99 1 T15 1 T85 2 T226 1
auto[2818572288:2952790015] 92 1 T84 1 T51 1 T52 1
auto[2952790016:3087007743] 89 1 T37 1 T222 1 T217 1
auto[3087007744:3221225471] 92 1 T3 1 T41 2 T52 1
auto[3221225472:3355443199] 96 1 T1 1 T41 1 T27 1
auto[3355443200:3489660927] 100 1 T52 1 T102 2 T109 1
auto[3489660928:3623878655] 102 1 T27 2 T37 1 T218 2
auto[3623878656:3758096383] 109 1 T84 1 T23 1 T221 1
auto[3758096384:3892314111] 100 1 T2 1 T217 1 T38 1
auto[3892314112:4026531839] 101 1 T41 1 T218 1 T53 1
auto[4026531840:4160749567] 98 1 T3 1 T226 1 T19 1
auto[4160749568:4294967295] 100 1 T27 1 T122 1 T102 3


Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cpregwen_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] auto[0] 100 1 T4 1 T102 1 T46 2
auto[0:134217727] auto[1] 7 1 T390 1 T310 1 T314 1
auto[134217728:268435455] auto[0] 92 1 T1 1 T3 1 T27 1
auto[134217728:268435455] auto[1] 3 1 T324 1 T423 2 - -
auto[268435456:402653183] auto[0] 86 1 T1 1 T27 2 T85 1
auto[268435456:402653183] auto[1] 12 1 T150 1 T265 1 T399 1
auto[402653184:536870911] auto[0] 90 1 T3 1 T15 1 T41 1
auto[402653184:536870911] auto[1] 15 1 T123 1 T150 1 T391 2
auto[536870912:671088639] auto[0] 92 1 T41 1 T27 2 T85 1
auto[536870912:671088639] auto[1] 4 1 T324 1 T415 2 T343 1
auto[671088640:805306367] auto[0] 120 1 T4 2 T122 2 T102 1
auto[671088640:805306367] auto[1] 5 1 T123 1 T154 1 T407 1
auto[805306368:939524095] auto[0] 104 1 T3 1 T27 2 T86 1
auto[805306368:939524095] auto[1] 8 1 T391 2 T287 1 T413 1
auto[939524096:1073741823] auto[0] 98 1 T27 1 T53 1 T111 1
auto[939524096:1073741823] auto[1] 5 1 T398 1 T324 1 T399 1
auto[1073741824:1207959551] auto[0] 91 1 T2 1 T3 1 T13 1
auto[1073741824:1207959551] auto[1] 9 1 T409 1 T391 2 T324 1
auto[1207959552:1342177279] auto[0] 97 1 T41 1 T27 1 T37 1
auto[1207959552:1342177279] auto[1] 6 1 T41 1 T324 1 T421 1
auto[1342177280:1476395007] auto[0] 84 1 T27 1 T4 1 T102 1
auto[1342177280:1476395007] auto[1] 10 1 T123 1 T150 1 T287 1
auto[1476395008:1610612735] auto[0] 108 1 T1 1 T27 1 T86 1
auto[1476395008:1610612735] auto[1] 14 1 T41 1 T152 1 T265 2
auto[1610612736:1744830463] auto[0] 97 1 T86 1 T218 1 T217 2
auto[1610612736:1744830463] auto[1] 3 1 T413 1 T288 1 T418 1
auto[1744830464:1879048191] auto[0] 90 1 T1 1 T51 1 T53 1
auto[1744830464:1879048191] auto[1] 6 1 T150 1 T407 1 T399 1
auto[1879048192:2013265919] auto[0] 103 1 T27 1 T85 1 T216 1
auto[1879048192:2013265919] auto[1] 7 1 T150 1 T391 2 T287 1
auto[2013265920:2147483647] auto[0] 87 1 T85 1 T216 1 T4 2
auto[2013265920:2147483647] auto[1] 4 1 T109 1 T426 1 T288 1
auto[2147483648:2281701375] auto[0] 89 1 T1 1 T41 1 T85 2
auto[2147483648:2281701375] auto[1] 3 1 T324 1 T410 1 T343 1
auto[2281701376:2415919103] auto[0] 89 1 T15 1 T216 1 T123 1
auto[2281701376:2415919103] auto[1] 8 1 T150 1 T249 1 T408 1
auto[2415919104:2550136831] auto[0] 100 1 T2 1 T102 2 T46 2
auto[2415919104:2550136831] auto[1] 4 1 T390 1 T314 1 T410 1
auto[2550136832:2684354559] auto[0] 94 1 T4 1 T103 1 T102 1
auto[2550136832:2684354559] auto[1] 8 1 T109 1 T389 1 T417 1
auto[2684354560:2818572287] auto[0] 86 1 T15 1 T85 2 T226 1
auto[2684354560:2818572287] auto[1] 13 1 T123 2 T151 1 T398 1
auto[2818572288:2952790015] auto[0] 85 1 T84 1 T51 1 T52 1
auto[2818572288:2952790015] auto[1] 7 1 T109 1 T391 1 T417 1
auto[2952790016:3087007743] auto[0] 84 1 T37 1 T222 1 T217 1
auto[2952790016:3087007743] auto[1] 5 1 T409 1 T413 1 T421 1
auto[3087007744:3221225471] auto[0] 90 1 T3 1 T41 1 T52 1
auto[3087007744:3221225471] auto[1] 2 1 T41 1 T314 1 - -
auto[3221225472:3355443199] auto[0] 90 1 T1 1 T27 1 T84 1
auto[3221225472:3355443199] auto[1] 6 1 T41 1 T417 1 T408 1
auto[3355443200:3489660927] auto[0] 94 1 T52 1 T102 2 T109 1
auto[3355443200:3489660927] auto[1] 6 1 T398 1 T391 1 T421 1
auto[3489660928:3623878655] auto[0] 94 1 T27 2 T37 1 T218 2
auto[3489660928:3623878655] auto[1] 8 1 T123 2 T398 1 T391 1
auto[3623878656:3758096383] auto[0] 103 1 T84 1 T23 1 T221 1
auto[3623878656:3758096383] auto[1] 6 1 T109 1 T409 1 T391 1
auto[3758096384:3892314111] auto[0] 90 1 T2 1 T217 1 T38 1
auto[3758096384:3892314111] auto[1] 10 1 T150 1 T265 1 T324 1
auto[3892314112:4026531839] auto[0] 92 1 T218 1 T53 1 T4 1
auto[3892314112:4026531839] auto[1] 9 1 T41 1 T391 1 T399 1
auto[4026531840:4160749567] auto[0] 90 1 T3 1 T226 1 T19 1
auto[4026531840:4160749567] auto[1] 8 1 T151 1 T283 1 T324 1
auto[4160749568:4294967295] auto[0] 88 1 T27 1 T122 1 T102 3
auto[4160749568:4294967295] auto[1] 12 1 T265 1 T391 1 T399 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%