Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.85 99.07 98.14 98.60 100.00 99.11 98.41 91.63


Total test records in report: 1075
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T1007 /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.2973458533 Mar 19 02:47:41 PM PDT 24 Mar 19 02:47:46 PM PDT 24 296500958 ps
T164 /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.531181344 Mar 19 02:47:50 PM PDT 24 Mar 19 02:48:34 PM PDT 24 7004642347 ps
T175 /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.3349049153 Mar 19 02:47:49 PM PDT 24 Mar 19 02:47:59 PM PDT 24 893058107 ps
T1008 /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.1497060820 Mar 19 02:48:08 PM PDT 24 Mar 19 02:48:10 PM PDT 24 35314362 ps
T1009 /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.2888515818 Mar 19 02:48:00 PM PDT 24 Mar 19 02:48:02 PM PDT 24 96058715 ps
T1010 /workspace/coverage/cover_reg_top/47.keymgr_intr_test.4155879720 Mar 19 02:48:15 PM PDT 24 Mar 19 02:48:16 PM PDT 24 33402728 ps
T1011 /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.3474495049 Mar 19 02:47:46 PM PDT 24 Mar 19 02:47:48 PM PDT 24 227190203 ps
T1012 /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.3970819910 Mar 19 02:47:48 PM PDT 24 Mar 19 02:47:51 PM PDT 24 109365385 ps
T1013 /workspace/coverage/cover_reg_top/32.keymgr_intr_test.3166278636 Mar 19 02:48:03 PM PDT 24 Mar 19 02:48:04 PM PDT 24 35394644 ps
T1014 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.2103538763 Mar 19 02:47:49 PM PDT 24 Mar 19 02:47:53 PM PDT 24 88810510 ps
T1015 /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.1685787012 Mar 19 02:48:26 PM PDT 24 Mar 19 02:48:28 PM PDT 24 39610676 ps
T177 /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.1349637194 Mar 19 02:47:37 PM PDT 24 Mar 19 02:47:42 PM PDT 24 87550085 ps
T1016 /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.2498520998 Mar 19 02:47:49 PM PDT 24 Mar 19 02:47:51 PM PDT 24 137901184 ps
T1017 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.2148014267 Mar 19 02:47:50 PM PDT 24 Mar 19 02:47:53 PM PDT 24 339622000 ps
T1018 /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.733230679 Mar 19 02:47:51 PM PDT 24 Mar 19 02:47:54 PM PDT 24 455956050 ps
T1019 /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.3257718098 Mar 19 02:48:08 PM PDT 24 Mar 19 02:48:10 PM PDT 24 35956765 ps
T1020 /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.3713267614 Mar 19 02:47:57 PM PDT 24 Mar 19 02:47:59 PM PDT 24 60337389 ps
T1021 /workspace/coverage/cover_reg_top/38.keymgr_intr_test.1085656283 Mar 19 02:48:09 PM PDT 24 Mar 19 02:48:11 PM PDT 24 9396679 ps
T1022 /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.890187639 Mar 19 02:47:52 PM PDT 24 Mar 19 02:47:58 PM PDT 24 159237678 ps
T169 /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.2478619773 Mar 19 02:47:49 PM PDT 24 Mar 19 02:48:04 PM PDT 24 2145907531 ps
T1023 /workspace/coverage/cover_reg_top/15.keymgr_intr_test.1041600709 Mar 19 02:48:13 PM PDT 24 Mar 19 02:48:14 PM PDT 24 14670029 ps
T1024 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.2403551946 Mar 19 02:47:57 PM PDT 24 Mar 19 02:48:02 PM PDT 24 277660115 ps
T1025 /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.2137192305 Mar 19 02:47:48 PM PDT 24 Mar 19 02:47:50 PM PDT 24 18736726 ps
T1026 /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.2037589248 Mar 19 02:48:14 PM PDT 24 Mar 19 02:48:16 PM PDT 24 23103073 ps
T1027 /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.266799340 Mar 19 02:48:06 PM PDT 24 Mar 19 02:48:10 PM PDT 24 51222600 ps
T1028 /workspace/coverage/cover_reg_top/0.keymgr_intr_test.3225184353 Mar 19 02:47:40 PM PDT 24 Mar 19 02:47:41 PM PDT 24 19014659 ps
T1029 /workspace/coverage/cover_reg_top/30.keymgr_intr_test.4235773120 Mar 19 02:48:14 PM PDT 24 Mar 19 02:48:16 PM PDT 24 14620198 ps
T1030 /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.3790752938 Mar 19 02:47:40 PM PDT 24 Mar 19 02:47:41 PM PDT 24 43933074 ps
T1031 /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.2208254981 Mar 19 02:48:03 PM PDT 24 Mar 19 02:48:06 PM PDT 24 218031508 ps
T1032 /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.3155235590 Mar 19 02:47:51 PM PDT 24 Mar 19 02:47:53 PM PDT 24 34830301 ps
T1033 /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.580661052 Mar 19 02:47:39 PM PDT 24 Mar 19 02:47:52 PM PDT 24 260681387 ps
T1034 /workspace/coverage/cover_reg_top/34.keymgr_intr_test.1192373072 Mar 19 02:48:10 PM PDT 24 Mar 19 02:48:12 PM PDT 24 35128396 ps
T1035 /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.570816705 Mar 19 02:47:51 PM PDT 24 Mar 19 02:47:53 PM PDT 24 29526700 ps
T1036 /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.3619161954 Mar 19 02:48:02 PM PDT 24 Mar 19 02:48:05 PM PDT 24 125976494 ps
T1037 /workspace/coverage/cover_reg_top/27.keymgr_intr_test.1551172562 Mar 19 02:48:08 PM PDT 24 Mar 19 02:48:10 PM PDT 24 13762684 ps
T1038 /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.3583107584 Mar 19 02:48:05 PM PDT 24 Mar 19 02:48:17 PM PDT 24 302892750 ps
T1039 /workspace/coverage/cover_reg_top/24.keymgr_intr_test.2357188400 Mar 19 02:48:02 PM PDT 24 Mar 19 02:48:04 PM PDT 24 43162018 ps
T1040 /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.181981433 Mar 19 02:47:55 PM PDT 24 Mar 19 02:47:57 PM PDT 24 32523576 ps
T1041 /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.1724862790 Mar 19 02:47:47 PM PDT 24 Mar 19 02:47:48 PM PDT 24 30717074 ps
T1042 /workspace/coverage/cover_reg_top/2.keymgr_intr_test.66328831 Mar 19 02:47:46 PM PDT 24 Mar 19 02:47:47 PM PDT 24 13997692 ps
T1043 /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.318274518 Mar 19 02:48:03 PM PDT 24 Mar 19 02:48:05 PM PDT 24 47140864 ps
T170 /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.938267816 Mar 19 02:48:04 PM PDT 24 Mar 19 02:48:23 PM PDT 24 775822727 ps
T1044 /workspace/coverage/cover_reg_top/7.keymgr_intr_test.242000730 Mar 19 02:47:53 PM PDT 24 Mar 19 02:47:54 PM PDT 24 40012267 ps
T1045 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.889890029 Mar 19 02:48:25 PM PDT 24 Mar 19 02:48:27 PM PDT 24 49701424 ps
T1046 /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.1625440788 Mar 19 02:48:09 PM PDT 24 Mar 19 02:48:14 PM PDT 24 265267581 ps
T1047 /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.2691170454 Mar 19 02:47:47 PM PDT 24 Mar 19 02:47:49 PM PDT 24 113276252 ps
T187 /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.2379557216 Mar 19 02:47:50 PM PDT 24 Mar 19 02:47:55 PM PDT 24 436669098 ps
T1048 /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.2773181121 Mar 19 02:47:52 PM PDT 24 Mar 19 02:47:54 PM PDT 24 59555105 ps
T1049 /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.2624418791 Mar 19 02:47:52 PM PDT 24 Mar 19 02:47:54 PM PDT 24 107289504 ps
T1050 /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.3729578661 Mar 19 02:47:57 PM PDT 24 Mar 19 02:48:00 PM PDT 24 145399127 ps
T1051 /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.3973975696 Mar 19 02:48:12 PM PDT 24 Mar 19 02:48:17 PM PDT 24 256003766 ps
T1052 /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.3773219606 Mar 19 02:47:39 PM PDT 24 Mar 19 02:47:41 PM PDT 24 53725791 ps
T1053 /workspace/coverage/cover_reg_top/19.keymgr_intr_test.2491916971 Mar 19 02:48:12 PM PDT 24 Mar 19 02:48:14 PM PDT 24 18163943 ps
T1054 /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.3604102277 Mar 19 02:47:52 PM PDT 24 Mar 19 02:48:00 PM PDT 24 1455867596 ps
T1055 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.2410688811 Mar 19 02:47:49 PM PDT 24 Mar 19 02:47:58 PM PDT 24 306273357 ps
T1056 /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.3518644232 Mar 19 02:47:48 PM PDT 24 Mar 19 02:47:51 PM PDT 24 441142293 ps
T1057 /workspace/coverage/cover_reg_top/41.keymgr_intr_test.681076641 Mar 19 02:48:14 PM PDT 24 Mar 19 02:48:15 PM PDT 24 53162406 ps
T1058 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.3326537768 Mar 19 02:47:48 PM PDT 24 Mar 19 02:47:54 PM PDT 24 300998768 ps
T1059 /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.3495857006 Mar 19 02:47:40 PM PDT 24 Mar 19 02:47:43 PM PDT 24 469874136 ps
T1060 /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.1216800920 Mar 19 02:48:06 PM PDT 24 Mar 19 02:48:09 PM PDT 24 121852903 ps
T1061 /workspace/coverage/cover_reg_top/43.keymgr_intr_test.1651310180 Mar 19 02:48:24 PM PDT 24 Mar 19 02:48:25 PM PDT 24 10693772 ps
T1062 /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.2554662745 Mar 19 02:48:12 PM PDT 24 Mar 19 02:48:14 PM PDT 24 106588635 ps
T1063 /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.3890609973 Mar 19 02:47:51 PM PDT 24 Mar 19 02:47:53 PM PDT 24 34660544 ps
T1064 /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.2326676556 Mar 19 02:47:54 PM PDT 24 Mar 19 02:47:57 PM PDT 24 46648505 ps
T1065 /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.4117469428 Mar 19 02:48:09 PM PDT 24 Mar 19 02:48:13 PM PDT 24 46612374 ps
T1066 /workspace/coverage/cover_reg_top/6.keymgr_intr_test.1984561295 Mar 19 02:47:51 PM PDT 24 Mar 19 02:47:52 PM PDT 24 9406822 ps
T1067 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.1255699980 Mar 19 02:48:07 PM PDT 24 Mar 19 02:48:11 PM PDT 24 267428887 ps
T1068 /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.964251025 Mar 19 02:47:48 PM PDT 24 Mar 19 02:47:53 PM PDT 24 750825456 ps
T1069 /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.3240138128 Mar 19 02:48:18 PM PDT 24 Mar 19 02:48:24 PM PDT 24 609301115 ps
T1070 /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.1049095051 Mar 19 02:47:41 PM PDT 24 Mar 19 02:47:47 PM PDT 24 973525774 ps
T1071 /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.2966870427 Mar 19 02:48:09 PM PDT 24 Mar 19 02:48:14 PM PDT 24 583686947 ps
T1072 /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.2968772071 Mar 19 02:47:50 PM PDT 24 Mar 19 02:47:52 PM PDT 24 58015927 ps
T1073 /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.1197286810 Mar 19 02:47:46 PM PDT 24 Mar 19 02:47:48 PM PDT 24 201115864 ps
T1074 /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.1208244055 Mar 19 02:47:54 PM PDT 24 Mar 19 02:47:56 PM PDT 24 52047827 ps
T1075 /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.1910344893 Mar 19 02:48:14 PM PDT 24 Mar 19 02:48:16 PM PDT 24 176145372 ps

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.3650827873
Short name T3
Test name
Test status
Simulation time 15117018830 ps
CPU time 62.67 seconds
Started Mar 19 03:22:28 PM PDT 24
Finished Mar 19 03:23:31 PM PDT 24
Peak memory 215032 kb
Host smart-fe514fa8-747c-416d-b9fa-7a80fc8cdecd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650827873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.3650827873
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.2815934722
Short name T4
Test name
Test status
Simulation time 973149603 ps
CPU time 23.44 seconds
Started Mar 19 03:21:49 PM PDT 24
Finished Mar 19 03:22:13 PM PDT 24
Peak memory 223028 kb
Host smart-45462d5c-fabc-402a-b855-bdb77e9f271c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815934722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.2815934722
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.3039241359
Short name T27
Test name
Test status
Simulation time 14991065827 ps
CPU time 450 seconds
Started Mar 19 03:22:33 PM PDT 24
Finished Mar 19 03:30:03 PM PDT 24
Peak memory 223084 kb
Host smart-3461801d-6b21-44a5-ae38-402336e36880
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3039241359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.3039241359
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_stress_all_with_rand_reset.3463129560
Short name T59
Test name
Test status
Simulation time 631428256 ps
CPU time 8.4 seconds
Started Mar 19 03:21:34 PM PDT 24
Finished Mar 19 03:21:42 PM PDT 24
Peak memory 223112 kb
Host smart-b84232b5-5425-4263-803c-22693173e97b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463129560 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all_with_rand_reset.3463129560
Directory /workspace/10.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.1658824921
Short name T46
Test name
Test status
Simulation time 3120938671 ps
CPU time 78.82 seconds
Started Mar 19 03:23:11 PM PDT 24
Finished Mar 19 03:24:30 PM PDT 24
Peak memory 223012 kb
Host smart-93ceb381-2e5d-4f0d-848e-aad227e53ea6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1658824921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.1658824921
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.4129541082
Short name T10
Test name
Test status
Simulation time 635113920 ps
CPU time 20.91 seconds
Started Mar 19 03:21:10 PM PDT 24
Finished Mar 19 03:21:31 PM PDT 24
Peak memory 241108 kb
Host smart-8809564b-ca9d-48cb-a663-28cc164532e7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4129541082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.4129541082
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.3285778488
Short name T8
Test name
Test status
Simulation time 451135761 ps
CPU time 5.85 seconds
Started Mar 19 03:23:10 PM PDT 24
Finished Mar 19 03:23:16 PM PDT 24
Peak memory 210628 kb
Host smart-3e93f65f-09a2-4e47-941a-0877841c16f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3285778488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.3285778488
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.2440985223
Short name T41
Test name
Test status
Simulation time 104411703 ps
CPU time 4.18 seconds
Started Mar 19 03:21:11 PM PDT 24
Finished Mar 19 03:21:16 PM PDT 24
Peak memory 216008 kb
Host smart-253b3563-597a-4e40-b15f-c92c675a7580
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2440985223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.2440985223
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.3171774569
Short name T47
Test name
Test status
Simulation time 11983305077 ps
CPU time 117.28 seconds
Started Mar 19 03:21:49 PM PDT 24
Finished Mar 19 03:23:47 PM PDT 24
Peak memory 223012 kb
Host smart-9ddfe58a-6ee4-4748-b536-63c121a9be39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3171774569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.3171774569
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.2114813483
Short name T117
Test name
Test status
Simulation time 727730433 ps
CPU time 6.37 seconds
Started Mar 19 02:47:50 PM PDT 24
Finished Mar 19 02:47:57 PM PDT 24
Peak memory 214692 kb
Host smart-3c277861-912b-4437-ba94-e1bae2632a33
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2114813483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.2114813483
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.3420809502
Short name T102
Test name
Test status
Simulation time 1534247796 ps
CPU time 53.17 seconds
Started Mar 19 03:23:21 PM PDT 24
Finished Mar 19 03:24:14 PM PDT 24
Peak memory 216000 kb
Host smart-ae87be06-07c2-4e7b-864a-b94612d7c1a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420809502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.3420809502
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.1115327028
Short name T324
Test name
Test status
Simulation time 239092977 ps
CPU time 13.09 seconds
Started Mar 19 03:21:18 PM PDT 24
Finished Mar 19 03:21:32 PM PDT 24
Peak memory 215284 kb
Host smart-998273f8-f1e8-4357-86d8-1a1d922c90ef
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1115327028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.1115327028
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_stress_all_with_rand_reset.340965831
Short name T112
Test name
Test status
Simulation time 640920127 ps
CPU time 11.42 seconds
Started Mar 19 03:23:25 PM PDT 24
Finished Mar 19 03:23:36 PM PDT 24
Peak memory 221108 kb
Host smart-a2974d2a-d610-4342-9228-7c711ef2525d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340965831 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all_with_rand_reset.340965831
Directory /workspace/49.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.1811154133
Short name T51
Test name
Test status
Simulation time 1103907243 ps
CPU time 6.66 seconds
Started Mar 19 03:22:00 PM PDT 24
Finished Mar 19 03:22:07 PM PDT 24
Peak memory 211632 kb
Host smart-255d6180-fa6f-445e-8bf3-88d786604351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1811154133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.1811154133
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.2640736285
Short name T23
Test name
Test status
Simulation time 78852731 ps
CPU time 3.66 seconds
Started Mar 19 03:21:39 PM PDT 24
Finished Mar 19 03:21:42 PM PDT 24
Peak memory 214800 kb
Host smart-75d292ba-846d-48bf-abcd-c60c48bb1b80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2640736285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.2640736285
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.2830003074
Short name T288
Test name
Test status
Simulation time 530769997 ps
CPU time 7.68 seconds
Started Mar 19 03:21:14 PM PDT 24
Finished Mar 19 03:21:22 PM PDT 24
Peak memory 215784 kb
Host smart-b30a044b-72d7-4b2e-8d50-02e201919f54
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2830003074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.2830003074
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.46337490
Short name T150
Test name
Test status
Simulation time 148052049 ps
CPU time 4.78 seconds
Started Mar 19 03:21:39 PM PDT 24
Finished Mar 19 03:21:44 PM PDT 24
Peak memory 214828 kb
Host smart-a0e1fb33-40aa-473a-b620-d731aac2614c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=46337490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.46337490
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.3234847653
Short name T65
Test name
Test status
Simulation time 3554784746 ps
CPU time 34.35 seconds
Started Mar 19 03:23:20 PM PDT 24
Finished Mar 19 03:23:55 PM PDT 24
Peak memory 221780 kb
Host smart-c51117a1-b176-4345-8557-d5689f523529
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234847653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.3234847653
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.103755426
Short name T427
Test name
Test status
Simulation time 4086800581 ps
CPU time 40.06 seconds
Started Mar 19 03:21:59 PM PDT 24
Finished Mar 19 03:22:39 PM PDT 24
Peak memory 214868 kb
Host smart-0b29f088-19ef-4e97-a067-677b77138a93
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=103755426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.103755426
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.4284214353
Short name T56
Test name
Test status
Simulation time 118716545 ps
CPU time 3.35 seconds
Started Mar 19 03:22:50 PM PDT 24
Finished Mar 19 03:22:54 PM PDT 24
Peak memory 211492 kb
Host smart-19a7f4dd-4237-4134-8fbf-e8c511736378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4284214353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.4284214353
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_stress_all_with_rand_reset.2035911799
Short name T68
Test name
Test status
Simulation time 167064001 ps
CPU time 8.96 seconds
Started Mar 19 03:23:13 PM PDT 24
Finished Mar 19 03:23:22 PM PDT 24
Peak memory 220572 kb
Host smart-9ce9b750-4c1a-41f2-99df-49de32434aaa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2035911799 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all_with_rand_reset.2035911799
Directory /workspace/40.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.2059459174
Short name T233
Test name
Test status
Simulation time 769124586 ps
CPU time 36.36 seconds
Started Mar 19 03:21:40 PM PDT 24
Finished Mar 19 03:22:17 PM PDT 24
Peak memory 216740 kb
Host smart-bd6d7d66-d6bf-420d-9444-cdf11a4299de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2059459174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.2059459174
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.2919456154
Short name T125
Test name
Test status
Simulation time 858128302 ps
CPU time 4.9 seconds
Started Mar 19 02:47:41 PM PDT 24
Finished Mar 19 02:47:47 PM PDT 24
Peak memory 214588 kb
Host smart-cc1c0c42-a8d9-4136-ba9a-91dc76b99282
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2919456154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.2919456154
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.2671758145
Short name T389
Test name
Test status
Simulation time 85463189 ps
CPU time 3.81 seconds
Started Mar 19 03:22:23 PM PDT 24
Finished Mar 19 03:22:27 PM PDT 24
Peak memory 214800 kb
Host smart-9558307d-e27d-4226-bfc4-5562ebb95320
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2671758145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.2671758145
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.1362791484
Short name T270
Test name
Test status
Simulation time 10685551804 ps
CPU time 109.72 seconds
Started Mar 19 03:22:54 PM PDT 24
Finished Mar 19 03:24:44 PM PDT 24
Peak memory 215616 kb
Host smart-f11413da-b0d4-451e-9138-3bde3e282aff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362791484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.1362791484
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.618288556
Short name T247
Test name
Test status
Simulation time 353665455 ps
CPU time 6.75 seconds
Started Mar 19 03:21:55 PM PDT 24
Finished Mar 19 03:22:02 PM PDT 24
Peak memory 214708 kb
Host smart-9e32b76a-fa8d-4d7b-b249-ce03330fea63
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=618288556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.618288556
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.3512834574
Short name T379
Test name
Test status
Simulation time 3062139697 ps
CPU time 23.47 seconds
Started Mar 19 03:22:49 PM PDT 24
Finished Mar 19 03:23:13 PM PDT 24
Peak memory 214972 kb
Host smart-2628ea4f-31ac-4fe4-8037-438c2b57f7c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512834574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.3512834574
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.128229303
Short name T39
Test name
Test status
Simulation time 119149912 ps
CPU time 3.13 seconds
Started Mar 19 03:21:11 PM PDT 24
Finished Mar 19 03:21:15 PM PDT 24
Peak memory 218256 kb
Host smart-cfc2795e-2904-4f52-a5b2-5f131a0a77f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128229303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.128229303
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.1756391535
Short name T232
Test name
Test status
Simulation time 343222207 ps
CPU time 2.81 seconds
Started Mar 19 03:22:45 PM PDT 24
Finished Mar 19 03:22:48 PM PDT 24
Peak memory 209404 kb
Host smart-568a8dfb-9466-4af4-96a9-da470d03ece0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1756391535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.1756391535
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.937672785
Short name T191
Test name
Test status
Simulation time 100727767 ps
CPU time 3.22 seconds
Started Mar 19 03:23:09 PM PDT 24
Finished Mar 19 03:23:12 PM PDT 24
Peak memory 216040 kb
Host smart-2bc783ee-5ac4-4b70-b1b2-a5e6de5f0c13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=937672785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.937672785
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.228675503
Short name T343
Test name
Test status
Simulation time 365852261 ps
CPU time 5.81 seconds
Started Mar 19 03:21:56 PM PDT 24
Finished Mar 19 03:22:02 PM PDT 24
Peak memory 215332 kb
Host smart-eb1ec8b9-b719-4447-b1f4-616286fcf0f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=228675503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.228675503
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.2870516753
Short name T49
Test name
Test status
Simulation time 2083734942 ps
CPU time 46.57 seconds
Started Mar 19 03:22:18 PM PDT 24
Finished Mar 19 03:23:04 PM PDT 24
Peak memory 222212 kb
Host smart-eda095ae-8578-45ff-86f6-5940d0b6f3c8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2870516753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.2870516753
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.2734919027
Short name T19
Test name
Test status
Simulation time 82425994 ps
CPU time 3.06 seconds
Started Mar 19 03:22:01 PM PDT 24
Finished Mar 19 03:22:04 PM PDT 24
Peak memory 220200 kb
Host smart-175bc67a-1bc8-4831-bdf1-49240834662b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2734919027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.2734919027
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.1765079698
Short name T416
Test name
Test status
Simulation time 54182297 ps
CPU time 3.89 seconds
Started Mar 19 03:21:44 PM PDT 24
Finished Mar 19 03:21:48 PM PDT 24
Peak memory 215740 kb
Host smart-f893e718-87de-4e99-8d11-938ca2266317
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1765079698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.1765079698
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.1432428578
Short name T108
Test name
Test status
Simulation time 49098176 ps
CPU time 0.93 seconds
Started Mar 19 03:22:00 PM PDT 24
Finished Mar 19 03:22:01 PM PDT 24
Peak memory 206436 kb
Host smart-6f288cad-f1da-44e3-b4ea-cdeec738880d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1432428578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.1432428578
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.23451032
Short name T52
Test name
Test status
Simulation time 507113603 ps
CPU time 4.9 seconds
Started Mar 19 03:22:15 PM PDT 24
Finished Mar 19 03:22:20 PM PDT 24
Peak memory 222916 kb
Host smart-0cd84c0a-fdc4-46f9-bc45-577fb5d21fd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=23451032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.23451032
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.2964466712
Short name T421
Test name
Test status
Simulation time 2595224197 ps
CPU time 7.85 seconds
Started Mar 19 03:22:26 PM PDT 24
Finished Mar 19 03:22:34 PM PDT 24
Peak memory 215048 kb
Host smart-c114bb91-6aec-46a6-ac45-9d80ec5bf721
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2964466712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.2964466712
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.2620202402
Short name T167
Test name
Test status
Simulation time 814037609 ps
CPU time 9.3 seconds
Started Mar 19 02:48:06 PM PDT 24
Finished Mar 19 02:48:15 PM PDT 24
Peak memory 209724 kb
Host smart-025634fe-3135-4e43-ba28-4c3e48b9bf8d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2620202402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.2620202402
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.1228470861
Short name T53
Test name
Test status
Simulation time 366756589 ps
CPU time 10.02 seconds
Started Mar 19 03:22:59 PM PDT 24
Finished Mar 19 03:23:09 PM PDT 24
Peak memory 214644 kb
Host smart-103fe772-f46e-465f-912f-25cbdeaeecdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228470861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.1228470861
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.3224537424
Short name T272
Test name
Test status
Simulation time 11085830607 ps
CPU time 66.02 seconds
Started Mar 19 03:22:03 PM PDT 24
Finished Mar 19 03:23:09 PM PDT 24
Peak memory 221648 kb
Host smart-21c596c3-fdc6-4647-b0b2-7c9693455c10
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3224537424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.3224537424
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.450616895
Short name T408
Test name
Test status
Simulation time 110409415 ps
CPU time 5.93 seconds
Started Mar 19 03:22:54 PM PDT 24
Finished Mar 19 03:23:00 PM PDT 24
Peak memory 214828 kb
Host smart-e01565b1-8af2-4a98-92ce-bcc4e47f7b97
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=450616895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.450616895
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.3192194797
Short name T124
Test name
Test status
Simulation time 82781338 ps
CPU time 2.81 seconds
Started Mar 19 02:47:50 PM PDT 24
Finished Mar 19 02:47:53 PM PDT 24
Peak memory 214596 kb
Host smart-3de13a5d-0244-40c7-8841-62e9dc4cb4cd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3192194797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.3192194797
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.1687484411
Short name T334
Test name
Test status
Simulation time 23091817457 ps
CPU time 740.48 seconds
Started Mar 19 03:21:21 PM PDT 24
Finished Mar 19 03:33:42 PM PDT 24
Peak memory 231360 kb
Host smart-b46a2476-eb3d-45b9-82f9-1e6bc223d235
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687484411 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.1687484411
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.2478619773
Short name T169
Test name
Test status
Simulation time 2145907531 ps
CPU time 14.99 seconds
Started Mar 19 02:47:49 PM PDT 24
Finished Mar 19 02:48:04 PM PDT 24
Peak memory 209736 kb
Host smart-234db7a8-5e6d-4ce6-a3a8-96c9a63a4bb1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478619773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.2478619773
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/41.keymgr_stress_all_with_rand_reset.104150893
Short name T171
Test name
Test status
Simulation time 1304707256 ps
CPU time 23.59 seconds
Started Mar 19 03:23:10 PM PDT 24
Finished Mar 19 03:23:34 PM PDT 24
Peak memory 223196 kb
Host smart-d583d8e4-41a6-4700-a7e7-53a041ee3506
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=104150893 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all_with_rand_reset.104150893
Directory /workspace/41.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.1358394091
Short name T20
Test name
Test status
Simulation time 367718779 ps
CPU time 4.08 seconds
Started Mar 19 03:22:43 PM PDT 24
Finished Mar 19 03:22:47 PM PDT 24
Peak memory 214824 kb
Host smart-c3b67d04-f333-4133-8686-0ee59b18530c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358394091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.1358394091
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.3564845367
Short name T92
Test name
Test status
Simulation time 84985644 ps
CPU time 4.07 seconds
Started Mar 19 03:21:57 PM PDT 24
Finished Mar 19 03:22:01 PM PDT 24
Peak memory 219624 kb
Host smart-87386e86-4a9c-4edb-a8f6-7ab7b0cf8043
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3564845367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.3564845367
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.1371235545
Short name T275
Test name
Test status
Simulation time 380482017 ps
CPU time 4.75 seconds
Started Mar 19 03:22:42 PM PDT 24
Finished Mar 19 03:22:47 PM PDT 24
Peak memory 222920 kb
Host smart-08e1c1ea-48de-4224-a933-6941d30910ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371235545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.1371235545
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.4294756929
Short name T320
Test name
Test status
Simulation time 48009922 ps
CPU time 3.27 seconds
Started Mar 19 03:23:37 PM PDT 24
Finished Mar 19 03:23:40 PM PDT 24
Peak memory 216128 kb
Host smart-7faf463f-5024-48bd-825e-475ce93f3dc8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4294756929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.4294756929
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.3349049153
Short name T175
Test name
Test status
Simulation time 893058107 ps
CPU time 9.72 seconds
Started Mar 19 02:47:49 PM PDT 24
Finished Mar 19 02:47:59 PM PDT 24
Peak memory 214296 kb
Host smart-b7615dd6-c6d2-4eae-b10b-a033c3ee4a5e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3349049153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.3349049153
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.531181344
Short name T164
Test name
Test status
Simulation time 7004642347 ps
CPU time 43.57 seconds
Started Mar 19 02:47:50 PM PDT 24
Finished Mar 19 02:48:34 PM PDT 24
Peak memory 216512 kb
Host smart-6ef9306f-6774-4494-8259-83a152ea8036
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=531181344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_err
.531181344
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.2361712766
Short name T182
Test name
Test status
Simulation time 85194645 ps
CPU time 3.09 seconds
Started Mar 19 03:22:54 PM PDT 24
Finished Mar 19 03:22:57 PM PDT 24
Peak memory 210448 kb
Host smart-18901c72-cadc-4fc2-93ea-1bd72e948aad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361712766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.2361712766
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.1349637194
Short name T177
Test name
Test status
Simulation time 87550085 ps
CPU time 3.6 seconds
Started Mar 19 02:47:37 PM PDT 24
Finished Mar 19 02:47:42 PM PDT 24
Peak memory 208660 kb
Host smart-8268601c-0a85-48e2-90cb-341ca2865b43
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1349637194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err
.1349637194
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.2239253769
Short name T196
Test name
Test status
Simulation time 230862431 ps
CPU time 4.01 seconds
Started Mar 19 03:23:13 PM PDT 24
Finished Mar 19 03:23:18 PM PDT 24
Peak memory 218836 kb
Host smart-4010b841-3cd9-447e-8da9-50850c455362
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2239253769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.2239253769
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.850674409
Short name T193
Test name
Test status
Simulation time 181543225 ps
CPU time 2.95 seconds
Started Mar 19 03:21:29 PM PDT 24
Finished Mar 19 03:21:32 PM PDT 24
Peak memory 218116 kb
Host smart-79739559-8701-48f1-aa55-07f9d8d622e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=850674409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.850674409
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.581775276
Short name T298
Test name
Test status
Simulation time 63000697 ps
CPU time 3.45 seconds
Started Mar 19 03:22:46 PM PDT 24
Finished Mar 19 03:22:51 PM PDT 24
Peak memory 211104 kb
Host smart-4f818f3e-4e35-4c0e-86c8-712d81d41420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=581775276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.581775276
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.403689852
Short name T123
Test name
Test status
Simulation time 4387844010 ps
CPU time 59.64 seconds
Started Mar 19 03:22:49 PM PDT 24
Finished Mar 19 03:23:49 PM PDT 24
Peak memory 216388 kb
Host smart-127bf790-2eec-4cec-ba2a-28edbedd1ea6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=403689852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.403689852
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.3627888879
Short name T60
Test name
Test status
Simulation time 190167330 ps
CPU time 3.85 seconds
Started Mar 19 03:22:51 PM PDT 24
Finished Mar 19 03:22:55 PM PDT 24
Peak memory 218152 kb
Host smart-119f6a9c-fc87-4fe0-84c2-61fc915d7fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3627888879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.3627888879
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.1661528218
Short name T190
Test name
Test status
Simulation time 51549332 ps
CPU time 3.72 seconds
Started Mar 19 03:22:45 PM PDT 24
Finished Mar 19 03:22:49 PM PDT 24
Peak memory 218648 kb
Host smart-4e0b2405-b700-4482-8a09-7b4326ace615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1661528218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.1661528218
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.90348516
Short name T258
Test name
Test status
Simulation time 236846604 ps
CPU time 7.68 seconds
Started Mar 19 03:22:32 PM PDT 24
Finished Mar 19 03:22:40 PM PDT 24
Peak memory 214728 kb
Host smart-eaad026f-c3aa-4697-a1c0-f450cb4f7e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90348516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.90348516
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.3971220974
Short name T314
Test name
Test status
Simulation time 82229605 ps
CPU time 5.24 seconds
Started Mar 19 03:23:00 PM PDT 24
Finished Mar 19 03:23:06 PM PDT 24
Peak memory 214828 kb
Host smart-eed2d62e-788a-405b-9e13-2aa71c5cc560
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3971220974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.3971220974
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_sideload.3080517084
Short name T141
Test name
Test status
Simulation time 1664922526 ps
CPU time 20.62 seconds
Started Mar 19 03:23:12 PM PDT 24
Finished Mar 19 03:23:33 PM PDT 24
Peak memory 209008 kb
Host smart-2d929cbb-f14f-4f63-a26b-108017251e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080517084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.3080517084
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.3166352551
Short name T318
Test name
Test status
Simulation time 198385131 ps
CPU time 2.8 seconds
Started Mar 19 03:23:35 PM PDT 24
Finished Mar 19 03:23:38 PM PDT 24
Peak memory 209304 kb
Host smart-19d2f55f-583e-4f00-83e8-82401b9c156b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166352551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.3166352551
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.1727995569
Short name T192
Test name
Test status
Simulation time 84837933 ps
CPU time 2.86 seconds
Started Mar 19 03:21:25 PM PDT 24
Finished Mar 19 03:21:28 PM PDT 24
Peak memory 223224 kb
Host smart-3b8a06c5-2fde-456d-9217-8403ee7861bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727995569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.1727995569
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.3544447914
Short name T15
Test name
Test status
Simulation time 65902948 ps
CPU time 3.7 seconds
Started Mar 19 03:21:35 PM PDT 24
Finished Mar 19 03:21:39 PM PDT 24
Peak memory 219056 kb
Host smart-dce8bb7d-4f94-44bf-820d-93bcbd497a04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544447914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.3544447914
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.225922600
Short name T194
Test name
Test status
Simulation time 244517214 ps
CPU time 4.87 seconds
Started Mar 19 03:23:09 PM PDT 24
Finished Mar 19 03:23:14 PM PDT 24
Peak memory 218608 kb
Host smart-bbcf3148-83e8-4cfd-a3e9-4be0bbab8851
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=225922600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.225922600
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.359731999
Short name T265
Test name
Test status
Simulation time 277878300 ps
CPU time 4.42 seconds
Started Mar 19 03:21:40 PM PDT 24
Finished Mar 19 03:21:45 PM PDT 24
Peak memory 214812 kb
Host smart-093e9a63-1c02-4006-9cca-ae561fc86acc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=359731999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.359731999
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.1979723825
Short name T209
Test name
Test status
Simulation time 9708226503 ps
CPU time 67.89 seconds
Started Mar 19 03:22:00 PM PDT 24
Finished Mar 19 03:23:08 PM PDT 24
Peak memory 239684 kb
Host smart-8c19f477-55b9-4d0e-8325-9412cb9e48cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1979723825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.1979723825
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.1419158337
Short name T724
Test name
Test status
Simulation time 85788419 ps
CPU time 2.49 seconds
Started Mar 19 03:21:48 PM PDT 24
Finished Mar 19 03:21:50 PM PDT 24
Peak memory 207260 kb
Host smart-92d1de20-2162-47f8-a545-e46ed8ce8c64
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1419158337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.1419158337
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload.4286451881
Short name T139
Test name
Test status
Simulation time 90201816 ps
CPU time 3.29 seconds
Started Mar 19 03:21:52 PM PDT 24
Finished Mar 19 03:21:55 PM PDT 24
Peak memory 207656 kb
Host smart-b76f1129-12f9-40a7-afd5-2df762642eb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286451881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.4286451881
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.2667868072
Short name T244
Test name
Test status
Simulation time 346314567 ps
CPU time 4.29 seconds
Started Mar 19 03:21:57 PM PDT 24
Finished Mar 19 03:22:01 PM PDT 24
Peak memory 209864 kb
Host smart-91ff62c8-73d2-436f-a401-bff13968b045
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2667868072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.2667868072
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.1155130015
Short name T307
Test name
Test status
Simulation time 1044202814 ps
CPU time 29.08 seconds
Started Mar 19 03:21:57 PM PDT 24
Finished Mar 19 03:22:27 PM PDT 24
Peak memory 222780 kb
Host smart-40f8fd1f-d79a-4057-b794-607bba63afc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1155130015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.1155130015
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.2738874793
Short name T96
Test name
Test status
Simulation time 427641774 ps
CPU time 12.73 seconds
Started Mar 19 03:21:12 PM PDT 24
Finished Mar 19 03:21:25 PM PDT 24
Peak memory 218940 kb
Host smart-b41f81d4-fe7d-4845-8d8b-43bcfcfc75fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2738874793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.2738874793
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.3989272114
Short name T392
Test name
Test status
Simulation time 122678219 ps
CPU time 3.51 seconds
Started Mar 19 03:21:24 PM PDT 24
Finished Mar 19 03:21:28 PM PDT 24
Peak memory 210688 kb
Host smart-951d1e43-cab7-4e35-871c-125330c7aa34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989272114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.3989272114
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.915412261
Short name T240
Test name
Test status
Simulation time 140657963 ps
CPU time 4.3 seconds
Started Mar 19 03:23:02 PM PDT 24
Finished Mar 19 03:23:06 PM PDT 24
Peak memory 222096 kb
Host smart-eb0cf6a7-1c0a-4c38-bf40-f7c5a525800b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915412261 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.915412261
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.110626831
Short name T306
Test name
Test status
Simulation time 56102691 ps
CPU time 3.1 seconds
Started Mar 19 03:21:21 PM PDT 24
Finished Mar 19 03:21:24 PM PDT 24
Peak memory 210388 kb
Host smart-9bbc96cc-0ae9-4926-a407-87615e2c44b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110626831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.110626831
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.3200671048
Short name T409
Test name
Test status
Simulation time 267775808 ps
CPU time 3.9 seconds
Started Mar 19 03:23:29 PM PDT 24
Finished Mar 19 03:23:33 PM PDT 24
Peak memory 214824 kb
Host smart-79f7d83c-4da5-4a5e-8dc5-3445e2782712
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3200671048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.3200671048
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.1087448619
Short name T172
Test name
Test status
Simulation time 378079418 ps
CPU time 7.15 seconds
Started Mar 19 02:47:50 PM PDT 24
Finished Mar 19 02:47:58 PM PDT 24
Peak memory 209488 kb
Host smart-c6b0754c-d05e-4319-a98b-f5c9cfb4438b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1087448619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.1087448619
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.4107387843
Short name T176
Test name
Test status
Simulation time 228077419 ps
CPU time 3.7 seconds
Started Mar 19 02:48:07 PM PDT 24
Finished Mar 19 02:48:11 PM PDT 24
Peak memory 209452 kb
Host smart-ee75b541-0a7e-4a7e-bb4e-ddfaef97dfe4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4107387843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.4107387843
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.3533279560
Short name T181
Test name
Test status
Simulation time 357191331 ps
CPU time 9.74 seconds
Started Mar 19 02:48:08 PM PDT 24
Finished Mar 19 02:48:19 PM PDT 24
Peak memory 209724 kb
Host smart-da52f14b-f7e3-4186-85e2-4ef953a739fb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3533279560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.3533279560
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.2551247227
Short name T186
Test name
Test status
Simulation time 685365848 ps
CPU time 3.8 seconds
Started Mar 19 02:47:47 PM PDT 24
Finished Mar 19 02:47:50 PM PDT 24
Peak memory 214268 kb
Host smart-44a3d941-58e0-466d-b35e-ce344dff0342
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2551247227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.2551247227
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.3657069746
Short name T165
Test name
Test status
Simulation time 12331629994 ps
CPU time 75.87 seconds
Started Mar 19 02:47:51 PM PDT 24
Finished Mar 19 02:49:07 PM PDT 24
Peak memory 227208 kb
Host smart-e1862d0c-6a3b-4ace-82af-d9025fe136bd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3657069746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.3657069746
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.2170812613
Short name T34
Test name
Test status
Simulation time 591432344 ps
CPU time 5.18 seconds
Started Mar 19 03:21:14 PM PDT 24
Finished Mar 19 03:21:19 PM PDT 24
Peak memory 216236 kb
Host smart-22f75d01-a6ff-4873-8cce-8f6dc7d208a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170812613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.2170812613
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.300030434
Short name T195
Test name
Test status
Simulation time 179708238 ps
CPU time 3.21 seconds
Started Mar 19 03:21:58 PM PDT 24
Finished Mar 19 03:22:06 PM PDT 24
Peak memory 223272 kb
Host smart-ee171937-9a86-4880-a925-1c5a57db6996
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300030434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.300030434
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.3694818958
Short name T197
Test name
Test status
Simulation time 117502383 ps
CPU time 5.47 seconds
Started Mar 19 03:22:58 PM PDT 24
Finished Mar 19 03:23:04 PM PDT 24
Peak memory 219108 kb
Host smart-180129c2-a97f-4a62-9dd7-3455b8e18251
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3694818958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.3694818958
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.691813892
Short name T362
Test name
Test status
Simulation time 365498922 ps
CPU time 4.82 seconds
Started Mar 19 03:21:11 PM PDT 24
Finished Mar 19 03:21:16 PM PDT 24
Peak memory 216160 kb
Host smart-19eea59d-a9fb-4b0a-bb7a-cb98a8f19c55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691813892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.691813892
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.2558696818
Short name T370
Test name
Test status
Simulation time 21967778598 ps
CPU time 510.19 seconds
Started Mar 19 03:21:09 PM PDT 24
Finished Mar 19 03:29:40 PM PDT 24
Peak memory 220616 kb
Host smart-de32b240-aca5-4e8e-9aee-c9d0c8353c73
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558696818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.2558696818
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.1945912402
Short name T290
Test name
Test status
Simulation time 271300828 ps
CPU time 4.3 seconds
Started Mar 19 03:21:11 PM PDT 24
Finished Mar 19 03:21:16 PM PDT 24
Peak memory 218676 kb
Host smart-889379c3-fa52-4992-98ec-e8927942d29a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945912402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.1945912402
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.2533302655
Short name T58
Test name
Test status
Simulation time 115311628 ps
CPU time 5.32 seconds
Started Mar 19 03:21:16 PM PDT 24
Finished Mar 19 03:21:22 PM PDT 24
Peak memory 210680 kb
Host smart-cae3f889-21e7-4c15-84bd-46e2edd24979
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2533302655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.2533302655
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.4060926467
Short name T26
Test name
Test status
Simulation time 151870725 ps
CPU time 6.39 seconds
Started Mar 19 03:21:42 PM PDT 24
Finished Mar 19 03:21:48 PM PDT 24
Peak memory 212296 kb
Host smart-3ddb5bd8-6e99-4a61-81fc-3e168403cafa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4060926467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.4060926467
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.3030292820
Short name T273
Test name
Test status
Simulation time 3256812922 ps
CPU time 23.94 seconds
Started Mar 19 03:21:47 PM PDT 24
Finished Mar 19 03:22:11 PM PDT 24
Peak memory 208852 kb
Host smart-ee08b351-7dd2-4f13-bbf2-54e5b8544c6b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3030292820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.3030292820
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.2007842868
Short name T317
Test name
Test status
Simulation time 608063212 ps
CPU time 7.95 seconds
Started Mar 19 03:21:54 PM PDT 24
Finished Mar 19 03:22:02 PM PDT 24
Peak memory 210076 kb
Host smart-6f64de18-a916-435d-8c50-ab6fe8812262
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007842868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.2007842868
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.1697992950
Short name T376
Test name
Test status
Simulation time 141659826 ps
CPU time 5.7 seconds
Started Mar 19 03:22:03 PM PDT 24
Finished Mar 19 03:22:09 PM PDT 24
Peak memory 210516 kb
Host smart-33d6f570-e2c1-4bee-a05e-3563341e8b3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697992950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.1697992950
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.437611914
Short name T28
Test name
Test status
Simulation time 230399188 ps
CPU time 6.16 seconds
Started Mar 19 03:21:58 PM PDT 24
Finished Mar 19 03:22:04 PM PDT 24
Peak memory 223316 kb
Host smart-54dc9d9f-80df-426e-9109-6a3fd90ea005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437611914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.437611914
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.2765860461
Short name T338
Test name
Test status
Simulation time 82590297 ps
CPU time 2.73 seconds
Started Mar 19 03:22:12 PM PDT 24
Finished Mar 19 03:22:15 PM PDT 24
Peak memory 220336 kb
Host smart-cc62edde-99e7-4ab9-9f09-29db7e24059b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765860461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.2765860461
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.1854892272
Short name T103
Test name
Test status
Simulation time 490447248 ps
CPU time 6.89 seconds
Started Mar 19 03:22:24 PM PDT 24
Finished Mar 19 03:22:30 PM PDT 24
Peak memory 211664 kb
Host smart-f92bd9f6-856e-414d-9b3e-949a9440c5da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854892272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.1854892272
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_random.1680483605
Short name T383
Test name
Test status
Simulation time 1083376350 ps
CPU time 5.98 seconds
Started Mar 19 03:22:16 PM PDT 24
Finished Mar 19 03:22:22 PM PDT 24
Peak memory 210352 kb
Host smart-d44224b5-56f5-4f5f-af34-1008af250b70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1680483605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.1680483605
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.1193648091
Short name T345
Test name
Test status
Simulation time 7445565637 ps
CPU time 169.28 seconds
Started Mar 19 03:22:28 PM PDT 24
Finished Mar 19 03:25:18 PM PDT 24
Peak memory 223084 kb
Host smart-32ebdc1e-57da-4ccd-9a9d-93ef8244025e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1193648091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.1193648091
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.3063914525
Short name T74
Test name
Test status
Simulation time 2853669685 ps
CPU time 67.89 seconds
Started Mar 19 03:22:37 PM PDT 24
Finished Mar 19 03:23:45 PM PDT 24
Peak memory 223388 kb
Host smart-8bb083ca-7228-446f-8cd2-e6dc676e5801
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3063914525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.3063914525
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.2167867997
Short name T285
Test name
Test status
Simulation time 85045546 ps
CPU time 5.17 seconds
Started Mar 19 03:22:49 PM PDT 24
Finished Mar 19 03:22:55 PM PDT 24
Peak memory 215612 kb
Host smart-131b5632-ed0a-4213-a765-f49e1e6b7964
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2167867997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.2167867997
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.1419598957
Short name T354
Test name
Test status
Simulation time 124599578 ps
CPU time 4.68 seconds
Started Mar 19 03:22:55 PM PDT 24
Finished Mar 19 03:23:00 PM PDT 24
Peak memory 210748 kb
Host smart-588b820c-4919-49b2-abc3-af3c8a3affae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1419598957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.1419598957
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.2427087623
Short name T237
Test name
Test status
Simulation time 3237162882 ps
CPU time 59.66 seconds
Started Mar 19 03:22:57 PM PDT 24
Finished Mar 19 03:23:57 PM PDT 24
Peak memory 223116 kb
Host smart-aa78dbb6-8340-4e84-92c3-7a0efd4cd37b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2427087623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.2427087623
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.705620077
Short name T234
Test name
Test status
Simulation time 283150709 ps
CPU time 2.96 seconds
Started Mar 19 03:22:46 PM PDT 24
Finished Mar 19 03:22:50 PM PDT 24
Peak memory 222932 kb
Host smart-681f18c1-8711-4cf7-b4db-84b9ab1c2ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=705620077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.705620077
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.1530192142
Short name T24
Test name
Test status
Simulation time 51517075 ps
CPU time 3.31 seconds
Started Mar 19 03:23:14 PM PDT 24
Finished Mar 19 03:23:18 PM PDT 24
Peak memory 209448 kb
Host smart-fc8a55ff-9fcb-4cf2-8737-bb5f39a310fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530192142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.1530192142
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.976738236
Short name T201
Test name
Test status
Simulation time 746757609 ps
CPU time 14.24 seconds
Started Mar 19 03:23:15 PM PDT 24
Finished Mar 19 03:23:30 PM PDT 24
Peak memory 223252 kb
Host smart-19d69adc-8d07-47f5-a559-79b824046fe7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976738236 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all_with_rand_reset.976738236
Directory /workspace/47.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.3225508451
Short name T61
Test name
Test status
Simulation time 236428527 ps
CPU time 3.71 seconds
Started Mar 19 03:23:36 PM PDT 24
Finished Mar 19 03:23:40 PM PDT 24
Peak memory 210200 kb
Host smart-e09c7166-a4c8-4094-8b12-354df1f22e89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3225508451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.3225508451
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.608738292
Short name T276
Test name
Test status
Simulation time 479948997 ps
CPU time 5.9 seconds
Started Mar 19 03:21:23 PM PDT 24
Finished Mar 19 03:21:30 PM PDT 24
Peak memory 222932 kb
Host smart-8ec51096-6752-42ce-a96b-135ffdb7bdd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=608738292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.608738292
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.1049095051
Short name T1070
Test name
Test status
Simulation time 973525774 ps
CPU time 5.73 seconds
Started Mar 19 02:47:41 PM PDT 24
Finished Mar 19 02:47:47 PM PDT 24
Peak memory 206160 kb
Host smart-a417be8c-43b4-46ec-bc85-024a60f7f9ac
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049095051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.1
049095051
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.580661052
Short name T1033
Test name
Test status
Simulation time 260681387 ps
CPU time 12.27 seconds
Started Mar 19 02:47:39 PM PDT 24
Finished Mar 19 02:47:52 PM PDT 24
Peak memory 206124 kb
Host smart-b8ad8217-37d3-4954-add8-e0199d72e534
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580661052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.580661052
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.4112989619
Short name T986
Test name
Test status
Simulation time 54942770 ps
CPU time 1.39 seconds
Started Mar 19 02:47:39 PM PDT 24
Finished Mar 19 02:47:42 PM PDT 24
Peak memory 206096 kb
Host smart-e8ca7e7a-4382-499d-8011-9fb9a07dc295
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4112989619 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.4
112989619
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.2860744466
Short name T202
Test name
Test status
Simulation time 114632860 ps
CPU time 1.69 seconds
Started Mar 19 02:47:42 PM PDT 24
Finished Mar 19 02:47:44 PM PDT 24
Peak memory 214212 kb
Host smart-c16ddaed-c321-4664-8481-67484f1d4911
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2860744466 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.2860744466
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.1445169205
Short name T158
Test name
Test status
Simulation time 76831692 ps
CPU time 1.02 seconds
Started Mar 19 02:47:40 PM PDT 24
Finished Mar 19 02:47:41 PM PDT 24
Peak memory 205908 kb
Host smart-c69e4a7f-529b-4dd1-a404-277377466c07
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445169205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.1445169205
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.3225184353
Short name T1028
Test name
Test status
Simulation time 19014659 ps
CPU time 0.86 seconds
Started Mar 19 02:47:40 PM PDT 24
Finished Mar 19 02:47:41 PM PDT 24
Peak memory 205776 kb
Host smart-67261490-a67a-4445-add7-5538f013baa7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225184353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.3225184353
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.3474495049
Short name T1011
Test name
Test status
Simulation time 227190203 ps
CPU time 2.66 seconds
Started Mar 19 02:47:46 PM PDT 24
Finished Mar 19 02:47:48 PM PDT 24
Peak memory 206100 kb
Host smart-9e533072-c87f-41c7-bd6e-f9d9a8efcf76
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3474495049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.3474495049
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.3495857006
Short name T1059
Test name
Test status
Simulation time 469874136 ps
CPU time 2.97 seconds
Started Mar 19 02:47:40 PM PDT 24
Finished Mar 19 02:47:43 PM PDT 24
Peak memory 214636 kb
Host smart-6cf08e3c-ca8a-4430-8cf5-a89c49909051
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495857006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.3495857006
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.3783798300
Short name T988
Test name
Test status
Simulation time 171109618 ps
CPU time 6.67 seconds
Started Mar 19 02:47:40 PM PDT 24
Finished Mar 19 02:47:47 PM PDT 24
Peak memory 214604 kb
Host smart-058d8a24-2fb1-40c7-94f7-64e0bf5cd6df
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783798300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
keymgr_shadow_reg_errors_with_csr_rw.3783798300
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.448103779
Short name T962
Test name
Test status
Simulation time 461826144 ps
CPU time 4.31 seconds
Started Mar 19 02:47:39 PM PDT 24
Finished Mar 19 02:47:43 PM PDT 24
Peak memory 214252 kb
Host smart-a325ca5a-6be0-451b-aaff-6c5b0d0db20a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448103779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.448103779
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.2138060806
Short name T156
Test name
Test status
Simulation time 72137510 ps
CPU time 4.34 seconds
Started Mar 19 02:47:49 PM PDT 24
Finished Mar 19 02:47:53 PM PDT 24
Peak memory 206116 kb
Host smart-d57f615a-1a93-4dfa-a251-e1ab85e8e6b4
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2138060806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.2
138060806
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.1026324451
Short name T921
Test name
Test status
Simulation time 644059063 ps
CPU time 16.46 seconds
Started Mar 19 02:47:49 PM PDT 24
Finished Mar 19 02:48:06 PM PDT 24
Peak memory 206016 kb
Host smart-3e60155d-6650-44f6-8a1f-fcf76af41550
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1026324451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.1
026324451
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.3790752938
Short name T1030
Test name
Test status
Simulation time 43933074 ps
CPU time 1.17 seconds
Started Mar 19 02:47:40 PM PDT 24
Finished Mar 19 02:47:41 PM PDT 24
Peak memory 206104 kb
Host smart-729ec31c-23c0-4dc4-a9aa-3e86b5263d26
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790752938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.3
790752938
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.3773219606
Short name T1052
Test name
Test status
Simulation time 53725791 ps
CPU time 1.31 seconds
Started Mar 19 02:47:39 PM PDT 24
Finished Mar 19 02:47:41 PM PDT 24
Peak memory 206012 kb
Host smart-aabc17f8-b71b-4b34-9feb-2735a081b402
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3773219606 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.3773219606
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.178783452
Short name T992
Test name
Test status
Simulation time 49428109 ps
CPU time 1.52 seconds
Started Mar 19 02:47:40 PM PDT 24
Finished Mar 19 02:47:42 PM PDT 24
Peak memory 206168 kb
Host smart-db704431-ccf2-48a4-a862-12267c58a290
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=178783452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.178783452
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.1908256650
Short name T1006
Test name
Test status
Simulation time 16338912 ps
CPU time 0.76 seconds
Started Mar 19 02:47:37 PM PDT 24
Finished Mar 19 02:47:39 PM PDT 24
Peak memory 205824 kb
Host smart-109f47a9-a37a-4667-9975-64b95d690c2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908256650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.1908256650
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.715338362
Short name T157
Test name
Test status
Simulation time 88581940 ps
CPU time 1.73 seconds
Started Mar 19 02:47:42 PM PDT 24
Finished Mar 19 02:47:44 PM PDT 24
Peak memory 206088 kb
Host smart-f6706157-8cb0-4226-bb25-c0ffcdd1a4e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=715338362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sam
e_csr_outstanding.715338362
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.2973458533
Short name T1007
Test name
Test status
Simulation time 296500958 ps
CPU time 4.52 seconds
Started Mar 19 02:47:41 PM PDT 24
Finished Mar 19 02:47:46 PM PDT 24
Peak memory 221116 kb
Host smart-86370328-5145-4b72-8d5e-dcea6bd86757
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2973458533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.2973458533
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.2197870798
Short name T967
Test name
Test status
Simulation time 1091922635 ps
CPU time 2.64 seconds
Started Mar 19 02:47:46 PM PDT 24
Finished Mar 19 02:47:49 PM PDT 24
Peak memory 215384 kb
Host smart-9fcc3033-eb72-41e5-a48c-555d5cb53b71
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2197870798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.2197870798
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.3815594201
Short name T951
Test name
Test status
Simulation time 71944298 ps
CPU time 2.56 seconds
Started Mar 19 02:47:49 PM PDT 24
Finished Mar 19 02:47:51 PM PDT 24
Peak memory 214280 kb
Host smart-f2f34975-599b-45ff-9ac1-225e553f6f97
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3815594201 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.3815594201
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.1208244055
Short name T1074
Test name
Test status
Simulation time 52047827 ps
CPU time 1.26 seconds
Started Mar 19 02:47:54 PM PDT 24
Finished Mar 19 02:47:56 PM PDT 24
Peak memory 206024 kb
Host smart-96674dd5-3ddc-4834-8222-91dd335a95aa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1208244055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.1208244055
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.176735369
Short name T995
Test name
Test status
Simulation time 20547874 ps
CPU time 0.84 seconds
Started Mar 19 02:47:50 PM PDT 24
Finished Mar 19 02:47:51 PM PDT 24
Peak memory 205804 kb
Host smart-5acbbc2f-f5a5-4df4-987b-5426fd1ac678
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=176735369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.176735369
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.1216800920
Short name T1060
Test name
Test status
Simulation time 121852903 ps
CPU time 2.44 seconds
Started Mar 19 02:48:06 PM PDT 24
Finished Mar 19 02:48:09 PM PDT 24
Peak memory 206088 kb
Host smart-4d75d118-3b6f-43d3-9480-c163ef651f13
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216800920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.1216800920
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.2744459370
Short name T980
Test name
Test status
Simulation time 306267592 ps
CPU time 2 seconds
Started Mar 19 02:47:51 PM PDT 24
Finished Mar 19 02:47:54 PM PDT 24
Peak memory 222716 kb
Host smart-c0d6e351-c49c-4a05-be90-805336b00559
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2744459370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.2744459370
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.3290818793
Short name T161
Test name
Test status
Simulation time 148607770 ps
CPU time 4.81 seconds
Started Mar 19 02:47:50 PM PDT 24
Finished Mar 19 02:47:55 PM PDT 24
Peak memory 214624 kb
Host smart-bdbf5114-812d-4046-938a-7067d57993fb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290818793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.keymgr_shadow_reg_errors_with_csr_rw.3290818793
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.2326676556
Short name T1064
Test name
Test status
Simulation time 46648505 ps
CPU time 3.07 seconds
Started Mar 19 02:47:54 PM PDT 24
Finished Mar 19 02:47:57 PM PDT 24
Peak memory 216764 kb
Host smart-1fdd6afb-555b-4f39-9ae0-cfd9f542d1b3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326676556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.2326676556
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.1332064348
Short name T179
Test name
Test status
Simulation time 999913607 ps
CPU time 11.63 seconds
Started Mar 19 02:47:54 PM PDT 24
Finished Mar 19 02:48:06 PM PDT 24
Peak memory 209308 kb
Host smart-435e62ae-dac8-4410-b995-c4fac19f59ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332064348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_er
r.1332064348
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.200229162
Short name T927
Test name
Test status
Simulation time 105702937 ps
CPU time 2.28 seconds
Started Mar 19 02:47:51 PM PDT 24
Finished Mar 19 02:47:54 PM PDT 24
Peak memory 214312 kb
Host smart-ba677d1c-87b4-4400-aa0d-6690a5c672ad
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=200229162 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.200229162
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.4023081299
Short name T977
Test name
Test status
Simulation time 24749687 ps
CPU time 1.3 seconds
Started Mar 19 02:47:49 PM PDT 24
Finished Mar 19 02:47:50 PM PDT 24
Peak memory 206084 kb
Host smart-83252177-5289-4a61-91a0-28ed86cdce6b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023081299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.4023081299
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.3476954713
Short name T933
Test name
Test status
Simulation time 40012535 ps
CPU time 0.72 seconds
Started Mar 19 02:48:05 PM PDT 24
Finished Mar 19 02:48:06 PM PDT 24
Peak memory 205684 kb
Host smart-54b25751-3089-47cc-b84f-5eae6da24f13
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3476954713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.3476954713
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.2624418791
Short name T1049
Test name
Test status
Simulation time 107289504 ps
CPU time 1.69 seconds
Started Mar 19 02:47:52 PM PDT 24
Finished Mar 19 02:47:54 PM PDT 24
Peak memory 206140 kb
Host smart-a5650a5a-fb97-4e63-9dd5-922a7e32890e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624418791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s
ame_csr_outstanding.2624418791
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.3761769689
Short name T964
Test name
Test status
Simulation time 756466810 ps
CPU time 7.04 seconds
Started Mar 19 02:47:53 PM PDT 24
Finished Mar 19 02:48:01 PM PDT 24
Peak memory 214604 kb
Host smart-8f664a16-4c80-41de-a2ed-58b2af1d2445
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3761769689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.3761769689
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.2302358539
Short name T935
Test name
Test status
Simulation time 81336746 ps
CPU time 2.37 seconds
Started Mar 19 02:47:51 PM PDT 24
Finished Mar 19 02:47:54 PM PDT 24
Peak memory 222448 kb
Host smart-80fa102a-aa08-4da0-aa11-57250da4e9d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2302358539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.2302358539
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.3257718098
Short name T1019
Test name
Test status
Simulation time 35956765 ps
CPU time 1.69 seconds
Started Mar 19 02:48:08 PM PDT 24
Finished Mar 19 02:48:10 PM PDT 24
Peak memory 214284 kb
Host smart-030d30f2-a43e-4c89-b2a2-f001fee104ba
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3257718098 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.3257718098
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.2888515818
Short name T1009
Test name
Test status
Simulation time 96058715 ps
CPU time 1.26 seconds
Started Mar 19 02:48:00 PM PDT 24
Finished Mar 19 02:48:02 PM PDT 24
Peak memory 206068 kb
Host smart-212b1aa7-985c-4a3b-9e7e-69f285223401
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2888515818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.2888515818
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.799327860
Short name T996
Test name
Test status
Simulation time 18261136 ps
CPU time 0.81 seconds
Started Mar 19 02:47:57 PM PDT 24
Finished Mar 19 02:47:58 PM PDT 24
Peak memory 205560 kb
Host smart-e531a4e1-8703-4ed5-ab07-565d9137837f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=799327860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.799327860
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.3729578661
Short name T1050
Test name
Test status
Simulation time 145399127 ps
CPU time 2.79 seconds
Started Mar 19 02:47:57 PM PDT 24
Finished Mar 19 02:48:00 PM PDT 24
Peak memory 206036 kb
Host smart-33a5be53-7849-4b6a-b3ee-c2e1e1237dad
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3729578661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.3729578661
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.1249390227
Short name T121
Test name
Test status
Simulation time 748234814 ps
CPU time 1.88 seconds
Started Mar 19 02:48:00 PM PDT 24
Finished Mar 19 02:48:03 PM PDT 24
Peak memory 214500 kb
Host smart-655b9ffa-26e2-4262-b0f8-bec7fb69e084
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249390227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.1249390227
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.3323252454
Short name T127
Test name
Test status
Simulation time 102291734 ps
CPU time 3.74 seconds
Started Mar 19 02:47:59 PM PDT 24
Finished Mar 19 02:48:03 PM PDT 24
Peak memory 214672 kb
Host smart-094c0508-913b-4cce-b07c-6087925905e1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3323252454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.3323252454
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.3645828184
Short name T928
Test name
Test status
Simulation time 30155762 ps
CPU time 1.94 seconds
Started Mar 19 02:47:54 PM PDT 24
Finished Mar 19 02:47:57 PM PDT 24
Peak memory 214300 kb
Host smart-3b15c05f-5296-4d1e-b783-7ee31f440931
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3645828184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.3645828184
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.3713267614
Short name T1020
Test name
Test status
Simulation time 60337389 ps
CPU time 1.38 seconds
Started Mar 19 02:47:57 PM PDT 24
Finished Mar 19 02:47:59 PM PDT 24
Peak memory 205864 kb
Host smart-9104a999-848b-48b5-9930-921812876ce8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3713267614 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.3713267614
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.181981433
Short name T1040
Test name
Test status
Simulation time 32523576 ps
CPU time 0.95 seconds
Started Mar 19 02:47:55 PM PDT 24
Finished Mar 19 02:47:57 PM PDT 24
Peak memory 205852 kb
Host smart-d412ab50-6ed4-4309-8789-2c093e35a119
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=181981433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.181981433
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.1796452941
Short name T944
Test name
Test status
Simulation time 109057964 ps
CPU time 0.8 seconds
Started Mar 19 02:48:03 PM PDT 24
Finished Mar 19 02:48:04 PM PDT 24
Peak memory 205784 kb
Host smart-c4da97d6-0a1c-4ec0-bafc-f7bc1fddafde
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796452941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.1796452941
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.3619161954
Short name T1036
Test name
Test status
Simulation time 125976494 ps
CPU time 2.83 seconds
Started Mar 19 02:48:02 PM PDT 24
Finished Mar 19 02:48:05 PM PDT 24
Peak memory 206140 kb
Host smart-a8822eff-664f-48f2-a840-61ca41534df5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619161954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.3619161954
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.2403551946
Short name T1024
Test name
Test status
Simulation time 277660115 ps
CPU time 4.5 seconds
Started Mar 19 02:47:57 PM PDT 24
Finished Mar 19 02:48:02 PM PDT 24
Peak memory 213800 kb
Host smart-693ef3ba-8c24-4db8-9f33-6f6844f15d5c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2403551946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.2403551946
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.2907105909
Short name T119
Test name
Test status
Simulation time 1556831323 ps
CPU time 7.28 seconds
Started Mar 19 02:47:57 PM PDT 24
Finished Mar 19 02:48:04 PM PDT 24
Peak memory 213908 kb
Host smart-66ad928d-1a1a-4044-867d-f9549f3132fd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2907105909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.2907105909
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.3973975696
Short name T1051
Test name
Test status
Simulation time 256003766 ps
CPU time 4.44 seconds
Started Mar 19 02:48:12 PM PDT 24
Finished Mar 19 02:48:17 PM PDT 24
Peak memory 216304 kb
Host smart-3a1ed750-7703-4aff-917d-f01cc8c2bd11
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3973975696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.3973975696
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.3583107584
Short name T1038
Test name
Test status
Simulation time 302892750 ps
CPU time 10.92 seconds
Started Mar 19 02:48:05 PM PDT 24
Finished Mar 19 02:48:17 PM PDT 24
Peak memory 209284 kb
Host smart-66b01c14-a2c6-445a-8836-8a10514b17ad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3583107584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er
r.3583107584
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.4188365545
Short name T916
Test name
Test status
Simulation time 20501355 ps
CPU time 1.41 seconds
Started Mar 19 02:48:09 PM PDT 24
Finished Mar 19 02:48:11 PM PDT 24
Peak memory 214192 kb
Host smart-96acb056-2f6d-479d-96d3-1ff1fcfa5750
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4188365545 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.4188365545
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.2773181121
Short name T1048
Test name
Test status
Simulation time 59555105 ps
CPU time 1.24 seconds
Started Mar 19 02:47:52 PM PDT 24
Finished Mar 19 02:47:54 PM PDT 24
Peak memory 205756 kb
Host smart-bec1d55b-367f-4738-af6f-8a1dfb37130a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2773181121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.2773181121
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.1795641731
Short name T932
Test name
Test status
Simulation time 11526715 ps
CPU time 0.83 seconds
Started Mar 19 02:47:52 PM PDT 24
Finished Mar 19 02:47:54 PM PDT 24
Peak memory 205524 kb
Host smart-3a8e83cd-0bf7-44f5-b73b-67571769290a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1795641731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.1795641731
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.318274518
Short name T1043
Test name
Test status
Simulation time 47140864 ps
CPU time 2.17 seconds
Started Mar 19 02:48:03 PM PDT 24
Finished Mar 19 02:48:05 PM PDT 24
Peak memory 206072 kb
Host smart-8d0da9b3-d6bd-45cc-84e2-e4d65a5c17c3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=318274518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_sa
me_csr_outstanding.318274518
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.1934780074
Short name T923
Test name
Test status
Simulation time 312810599 ps
CPU time 3.65 seconds
Started Mar 19 02:47:57 PM PDT 24
Finished Mar 19 02:48:01 PM PDT 24
Peak memory 214596 kb
Host smart-dea98f92-a04d-429f-acf6-6aba5b615fd1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934780074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.1934780074
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.1255699980
Short name T1067
Test name
Test status
Simulation time 267428887 ps
CPU time 3.63 seconds
Started Mar 19 02:48:07 PM PDT 24
Finished Mar 19 02:48:11 PM PDT 24
Peak memory 214520 kb
Host smart-c7a14f5b-d781-472a-a30e-dfdba3067c5b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255699980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.1255699980
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.266799340
Short name T1027
Test name
Test status
Simulation time 51222600 ps
CPU time 3.3 seconds
Started Mar 19 02:48:06 PM PDT 24
Finished Mar 19 02:48:10 PM PDT 24
Peak memory 214272 kb
Host smart-434b02fa-4f98-406d-8962-0dd61caacd41
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266799340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.266799340
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.2966870427
Short name T1071
Test name
Test status
Simulation time 583686947 ps
CPU time 4.88 seconds
Started Mar 19 02:48:09 PM PDT 24
Finished Mar 19 02:48:14 PM PDT 24
Peak memory 209544 kb
Host smart-32ed6b7e-5426-47b4-a1cf-1fd6884ed927
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2966870427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.2966870427
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.3828343038
Short name T938
Test name
Test status
Simulation time 75379176 ps
CPU time 1.43 seconds
Started Mar 19 02:48:01 PM PDT 24
Finished Mar 19 02:48:03 PM PDT 24
Peak memory 214332 kb
Host smart-ad45bcf5-0851-4ac5-89b6-4e08ee5e199b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3828343038 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.3828343038
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.2552062323
Short name T969
Test name
Test status
Simulation time 111473456 ps
CPU time 1.1 seconds
Started Mar 19 02:48:15 PM PDT 24
Finished Mar 19 02:48:16 PM PDT 24
Peak memory 206092 kb
Host smart-8f4fba27-4df9-4aa5-9252-f87a0414c4f2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2552062323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.2552062323
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.1041600709
Short name T1023
Test name
Test status
Simulation time 14670029 ps
CPU time 0.73 seconds
Started Mar 19 02:48:13 PM PDT 24
Finished Mar 19 02:48:14 PM PDT 24
Peak memory 205664 kb
Host smart-f10f59d0-5f2f-4195-820a-580f6424c729
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1041600709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.1041600709
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.2183163744
Short name T160
Test name
Test status
Simulation time 47724186 ps
CPU time 1.43 seconds
Started Mar 19 02:48:04 PM PDT 24
Finished Mar 19 02:48:05 PM PDT 24
Peak memory 206184 kb
Host smart-7eaa7ac6-db7a-41c5-b42e-6ea62759114e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2183163744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.2183163744
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.1606774068
Short name T129
Test name
Test status
Simulation time 445686826 ps
CPU time 8.15 seconds
Started Mar 19 02:48:04 PM PDT 24
Finished Mar 19 02:48:12 PM PDT 24
Peak memory 214596 kb
Host smart-de0c6008-0559-4fd3-8898-da083825539e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1606774068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.1606774068
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.3240138128
Short name T1069
Test name
Test status
Simulation time 609301115 ps
CPU time 4.97 seconds
Started Mar 19 02:48:18 PM PDT 24
Finished Mar 19 02:48:24 PM PDT 24
Peak memory 214532 kb
Host smart-7c66d666-f8f7-404e-9739-284d81630a95
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240138128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.3240138128
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.2994646249
Short name T975
Test name
Test status
Simulation time 222482099 ps
CPU time 2.89 seconds
Started Mar 19 02:48:03 PM PDT 24
Finished Mar 19 02:48:06 PM PDT 24
Peak memory 214300 kb
Host smart-3d0426ea-92d3-4525-acc2-56554f507def
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2994646249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.2994646249
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.2554662745
Short name T1062
Test name
Test status
Simulation time 106588635 ps
CPU time 1.77 seconds
Started Mar 19 02:48:12 PM PDT 24
Finished Mar 19 02:48:14 PM PDT 24
Peak memory 214236 kb
Host smart-246d479c-1275-4b7f-8ddc-de7a9ca52224
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2554662745 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.2554662745
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.1216618346
Short name T1004
Test name
Test status
Simulation time 20140965 ps
CPU time 0.92 seconds
Started Mar 19 02:48:12 PM PDT 24
Finished Mar 19 02:48:14 PM PDT 24
Peak memory 205736 kb
Host smart-04497148-fe91-4061-9f3f-1290de26f906
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216618346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.1216618346
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.2501325078
Short name T920
Test name
Test status
Simulation time 10097185 ps
CPU time 0.72 seconds
Started Mar 19 02:48:13 PM PDT 24
Finished Mar 19 02:48:14 PM PDT 24
Peak memory 205760 kb
Host smart-ba972fa3-cb19-4cdc-8f5c-3a1af058fb24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2501325078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.2501325078
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.1460035201
Short name T965
Test name
Test status
Simulation time 22722317 ps
CPU time 1.46 seconds
Started Mar 19 02:48:13 PM PDT 24
Finished Mar 19 02:48:15 PM PDT 24
Peak memory 205928 kb
Host smart-700284f3-9224-40df-809a-345cdf1c07c8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460035201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.1460035201
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.1625440788
Short name T1046
Test name
Test status
Simulation time 265267581 ps
CPU time 3.52 seconds
Started Mar 19 02:48:09 PM PDT 24
Finished Mar 19 02:48:14 PM PDT 24
Peak memory 214588 kb
Host smart-58577f23-3c16-46c2-b9e9-8f75d419dcf3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1625440788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.1625440788
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.2851676654
Short name T128
Test name
Test status
Simulation time 252304991 ps
CPU time 6.38 seconds
Started Mar 19 02:48:22 PM PDT 24
Finished Mar 19 02:48:29 PM PDT 24
Peak memory 214620 kb
Host smart-a5fd41c5-7cb9-4b90-a384-f9442744076e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2851676654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.2851676654
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.3205266980
Short name T985
Test name
Test status
Simulation time 184657716 ps
CPU time 3.67 seconds
Started Mar 19 02:48:05 PM PDT 24
Finished Mar 19 02:48:09 PM PDT 24
Peak memory 217460 kb
Host smart-b0b9c87c-f010-489a-9cda-f1408fa9fe36
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205266980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.3205266980
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.317950392
Short name T983
Test name
Test status
Simulation time 31605386 ps
CPU time 1.6 seconds
Started Mar 19 02:48:08 PM PDT 24
Finished Mar 19 02:48:11 PM PDT 24
Peak memory 214376 kb
Host smart-8fe51db8-0823-4f07-acb1-11cb2911bf37
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317950392 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.317950392
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.1497060820
Short name T1008
Test name
Test status
Simulation time 35314362 ps
CPU time 0.99 seconds
Started Mar 19 02:48:08 PM PDT 24
Finished Mar 19 02:48:10 PM PDT 24
Peak memory 205892 kb
Host smart-dabbe94d-6016-4619-8329-5e974109f48e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497060820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.1497060820
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.3931029557
Short name T963
Test name
Test status
Simulation time 38983169 ps
CPU time 0.7 seconds
Started Mar 19 02:48:13 PM PDT 24
Finished Mar 19 02:48:14 PM PDT 24
Peak memory 205700 kb
Host smart-1cbba596-4bdf-4e8b-af89-081f03b2298d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3931029557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.3931029557
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.777942381
Short name T1003
Test name
Test status
Simulation time 97598403 ps
CPU time 3 seconds
Started Mar 19 02:48:20 PM PDT 24
Finished Mar 19 02:48:23 PM PDT 24
Peak memory 206060 kb
Host smart-5c5043bb-2a76-4d34-8e35-27745e933fd2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=777942381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_sa
me_csr_outstanding.777942381
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.3536471094
Short name T925
Test name
Test status
Simulation time 197823141 ps
CPU time 2.28 seconds
Started Mar 19 02:48:02 PM PDT 24
Finished Mar 19 02:48:05 PM PDT 24
Peak memory 222800 kb
Host smart-da38184e-1c20-4252-b66c-a89fcc4dbea0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3536471094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.3536471094
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.941036608
Short name T118
Test name
Test status
Simulation time 479778807 ps
CPU time 5.18 seconds
Started Mar 19 02:48:04 PM PDT 24
Finished Mar 19 02:48:10 PM PDT 24
Peak memory 214664 kb
Host smart-fe086a58-3b93-4690-9bc7-ce2fea3c895b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=941036608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
keymgr_shadow_reg_errors_with_csr_rw.941036608
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.4117469428
Short name T1065
Test name
Test status
Simulation time 46612374 ps
CPU time 2.98 seconds
Started Mar 19 02:48:09 PM PDT 24
Finished Mar 19 02:48:13 PM PDT 24
Peak memory 216620 kb
Host smart-578d6cae-1e8c-4eca-9350-871c55f294a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4117469428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.4117469428
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.3217149799
Short name T937
Test name
Test status
Simulation time 62506832 ps
CPU time 1.76 seconds
Started Mar 19 02:48:14 PM PDT 24
Finished Mar 19 02:48:16 PM PDT 24
Peak memory 214248 kb
Host smart-6f4eb553-5c16-4b0a-8194-5c476c404bcd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217149799 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.3217149799
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.2037589248
Short name T1026
Test name
Test status
Simulation time 23103073 ps
CPU time 1.18 seconds
Started Mar 19 02:48:14 PM PDT 24
Finished Mar 19 02:48:16 PM PDT 24
Peak memory 206084 kb
Host smart-fff6ebff-4dc6-4fe1-aba5-48b8014568c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037589248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.2037589248
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.1815861484
Short name T957
Test name
Test status
Simulation time 9432797 ps
CPU time 0.77 seconds
Started Mar 19 02:48:08 PM PDT 24
Finished Mar 19 02:48:10 PM PDT 24
Peak memory 205768 kb
Host smart-105deed6-cff0-4b9f-8469-8d177fb471d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1815861484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.1815861484
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.1910344893
Short name T1075
Test name
Test status
Simulation time 176145372 ps
CPU time 2.34 seconds
Started Mar 19 02:48:14 PM PDT 24
Finished Mar 19 02:48:16 PM PDT 24
Peak memory 206016 kb
Host smart-c0b71879-2af1-4d93-99a2-55ce2ee76d1f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1910344893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.1910344893
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.1720933617
Short name T947
Test name
Test status
Simulation time 101139683 ps
CPU time 3.16 seconds
Started Mar 19 02:48:07 PM PDT 24
Finished Mar 19 02:48:11 PM PDT 24
Peak memory 214532 kb
Host smart-064b934d-d610-476b-b2c6-28a0de2a3e14
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1720933617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.1720933617
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.3756417084
Short name T976
Test name
Test status
Simulation time 296627801 ps
CPU time 6.84 seconds
Started Mar 19 02:48:15 PM PDT 24
Finished Mar 19 02:48:22 PM PDT 24
Peak memory 214588 kb
Host smart-061f4294-e845-465b-b47e-b1ad14d9e259
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3756417084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.3756417084
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.2500873040
Short name T942
Test name
Test status
Simulation time 158105581 ps
CPU time 2.13 seconds
Started Mar 19 02:48:05 PM PDT 24
Finished Mar 19 02:48:08 PM PDT 24
Peak memory 216420 kb
Host smart-da512b17-89e9-48e2-8141-34ae1ac9ceef
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2500873040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.2500873040
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.11148108
Short name T183
Test name
Test status
Simulation time 466295322 ps
CPU time 5.49 seconds
Started Mar 19 02:48:02 PM PDT 24
Finished Mar 19 02:48:08 PM PDT 24
Peak memory 209744 kb
Host smart-d6d6b307-fbcd-4ada-a8f8-c766f5f1414f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11148108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_err.11148108
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.1685787012
Short name T1015
Test name
Test status
Simulation time 39610676 ps
CPU time 1.6 seconds
Started Mar 19 02:48:26 PM PDT 24
Finished Mar 19 02:48:28 PM PDT 24
Peak memory 214224 kb
Host smart-903bacf6-029b-4a39-93e5-0daa0e01d8c3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1685787012 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.1685787012
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.4288646454
Short name T990
Test name
Test status
Simulation time 20943799 ps
CPU time 0.89 seconds
Started Mar 19 02:48:07 PM PDT 24
Finished Mar 19 02:48:09 PM PDT 24
Peak memory 205836 kb
Host smart-a9c1d143-6793-4249-99ed-d192cd024fb0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4288646454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.4288646454
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.2491916971
Short name T1053
Test name
Test status
Simulation time 18163943 ps
CPU time 0.83 seconds
Started Mar 19 02:48:12 PM PDT 24
Finished Mar 19 02:48:14 PM PDT 24
Peak memory 205788 kb
Host smart-b91c0219-5d5d-4310-94b6-bfc32324e7a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491916971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.2491916971
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.2208254981
Short name T1031
Test name
Test status
Simulation time 218031508 ps
CPU time 2.52 seconds
Started Mar 19 02:48:03 PM PDT 24
Finished Mar 19 02:48:06 PM PDT 24
Peak memory 206200 kb
Host smart-9184e729-0e08-4cda-b709-a9ec4510932c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2208254981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.2208254981
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.889890029
Short name T1045
Test name
Test status
Simulation time 49701424 ps
CPU time 1.94 seconds
Started Mar 19 02:48:25 PM PDT 24
Finished Mar 19 02:48:27 PM PDT 24
Peak memory 214580 kb
Host smart-387b8ae6-8376-4da1-88eb-c5bd502b3e70
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=889890029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shado
w_reg_errors.889890029
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.4273148367
Short name T958
Test name
Test status
Simulation time 424656965 ps
CPU time 8.93 seconds
Started Mar 19 02:48:12 PM PDT 24
Finished Mar 19 02:48:22 PM PDT 24
Peak memory 214616 kb
Host smart-641d4c32-9d6d-483f-a0c4-6cf6e245a575
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273148367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.4273148367
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.2550487254
Short name T934
Test name
Test status
Simulation time 109560405 ps
CPU time 2.03 seconds
Started Mar 19 02:48:03 PM PDT 24
Finished Mar 19 02:48:05 PM PDT 24
Peak memory 214240 kb
Host smart-dd17e599-cccd-4e6a-b524-58dcb9364f46
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2550487254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.2550487254
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.938267816
Short name T170
Test name
Test status
Simulation time 775822727 ps
CPU time 18.95 seconds
Started Mar 19 02:48:04 PM PDT 24
Finished Mar 19 02:48:23 PM PDT 24
Peak memory 209304 kb
Host smart-ff09a152-0f50-46f2-a068-491593f8bd17
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938267816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_err
.938267816
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.3925176538
Short name T953
Test name
Test status
Simulation time 1251779065 ps
CPU time 9.22 seconds
Started Mar 19 02:47:52 PM PDT 24
Finished Mar 19 02:48:02 PM PDT 24
Peak memory 205988 kb
Host smart-151b850d-b15c-4c72-ad1f-a370d398ad26
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3925176538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.3
925176538
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.2372644716
Short name T943
Test name
Test status
Simulation time 3994966059 ps
CPU time 18.71 seconds
Started Mar 19 02:47:50 PM PDT 24
Finished Mar 19 02:48:09 PM PDT 24
Peak memory 206136 kb
Host smart-f97c304b-ee3b-419b-b259-5a34d8493576
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2372644716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.2
372644716
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.3943658031
Short name T936
Test name
Test status
Simulation time 47152224 ps
CPU time 0.9 seconds
Started Mar 19 02:47:46 PM PDT 24
Finished Mar 19 02:47:47 PM PDT 24
Peak memory 205912 kb
Host smart-2cc06a0e-9e81-4fe1-a73a-d38e36b0dc84
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3943658031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.3
943658031
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.1724862790
Short name T1041
Test name
Test status
Simulation time 30717074 ps
CPU time 1.55 seconds
Started Mar 19 02:47:47 PM PDT 24
Finished Mar 19 02:47:48 PM PDT 24
Peak memory 206036 kb
Host smart-162f1db6-77f8-4de8-9c7f-91656dd400c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724862790 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.1724862790
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.2137192305
Short name T1025
Test name
Test status
Simulation time 18736726 ps
CPU time 0.97 seconds
Started Mar 19 02:47:48 PM PDT 24
Finished Mar 19 02:47:50 PM PDT 24
Peak memory 205844 kb
Host smart-6b92e828-ccd2-470c-906b-9f80e324e737
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137192305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.2137192305
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.66328831
Short name T1042
Test name
Test status
Simulation time 13997692 ps
CPU time 0.9 seconds
Started Mar 19 02:47:46 PM PDT 24
Finished Mar 19 02:47:47 PM PDT 24
Peak memory 205784 kb
Host smart-746c0a5f-66b3-4e21-99b5-561be5699021
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66328831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.66328831
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.2014732920
Short name T974
Test name
Test status
Simulation time 45460204 ps
CPU time 1.52 seconds
Started Mar 19 02:47:51 PM PDT 24
Finished Mar 19 02:47:53 PM PDT 24
Peak memory 206056 kb
Host smart-eede0733-46db-4993-b538-44dc7c7e07b7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014732920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.2014732920
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.1197286810
Short name T1073
Test name
Test status
Simulation time 201115864 ps
CPU time 2.21 seconds
Started Mar 19 02:47:46 PM PDT 24
Finished Mar 19 02:47:48 PM PDT 24
Peak memory 214648 kb
Host smart-6c9ed31b-c881-4745-9cf2-4161c1e0c6bd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1197286810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.1197286810
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.2769950181
Short name T945
Test name
Test status
Simulation time 534437183 ps
CPU time 4.35 seconds
Started Mar 19 02:47:46 PM PDT 24
Finished Mar 19 02:47:50 PM PDT 24
Peak memory 214588 kb
Host smart-90ae3aef-74e8-4616-b247-31d2e368e328
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769950181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.2769950181
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.139750776
Short name T909
Test name
Test status
Simulation time 49183736 ps
CPU time 2.88 seconds
Started Mar 19 02:47:46 PM PDT 24
Finished Mar 19 02:47:49 PM PDT 24
Peak memory 214256 kb
Host smart-270a90ac-670e-44ca-a19e-6214e9d9ebee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139750776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.139750776
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.3788796979
Short name T168
Test name
Test status
Simulation time 542499141 ps
CPU time 4.6 seconds
Started Mar 19 02:47:41 PM PDT 24
Finished Mar 19 02:47:45 PM PDT 24
Peak memory 209672 kb
Host smart-cd209429-1aa2-4cb5-a30e-a977106f5e9e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788796979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.3788796979
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.961950867
Short name T915
Test name
Test status
Simulation time 43841839 ps
CPU time 0.72 seconds
Started Mar 19 02:48:03 PM PDT 24
Finished Mar 19 02:48:04 PM PDT 24
Peak memory 205788 kb
Host smart-e9e7510f-7879-4218-8d66-d2bfd4a60fd7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961950867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.961950867
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.1807251102
Short name T948
Test name
Test status
Simulation time 37335364 ps
CPU time 0.75 seconds
Started Mar 19 02:48:11 PM PDT 24
Finished Mar 19 02:48:13 PM PDT 24
Peak memory 205768 kb
Host smart-8f30514e-930e-49cd-be05-863f933c69a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1807251102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.1807251102
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.3053696323
Short name T922
Test name
Test status
Simulation time 170538399 ps
CPU time 0.8 seconds
Started Mar 19 02:48:02 PM PDT 24
Finished Mar 19 02:48:03 PM PDT 24
Peak memory 205724 kb
Host smart-e4145cb1-69ff-4586-96ca-63eac3a65034
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3053696323 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.3053696323
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.2915032951
Short name T930
Test name
Test status
Simulation time 14815610 ps
CPU time 0.72 seconds
Started Mar 19 02:48:06 PM PDT 24
Finished Mar 19 02:48:07 PM PDT 24
Peak memory 205788 kb
Host smart-89ca8c2e-9e80-4719-bf3e-c0cb0105078d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915032951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.2915032951
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.2357188400
Short name T1039
Test name
Test status
Simulation time 43162018 ps
CPU time 0.91 seconds
Started Mar 19 02:48:02 PM PDT 24
Finished Mar 19 02:48:04 PM PDT 24
Peak memory 205772 kb
Host smart-a189f942-98f6-4d8c-bd60-a6509ced421d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2357188400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.2357188400
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.110754468
Short name T946
Test name
Test status
Simulation time 11312227 ps
CPU time 0.84 seconds
Started Mar 19 02:48:13 PM PDT 24
Finished Mar 19 02:48:14 PM PDT 24
Peak memory 205744 kb
Host smart-dda35ac6-e43c-4591-9350-cb99d8398323
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110754468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.110754468
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.2194723767
Short name T968
Test name
Test status
Simulation time 21318708 ps
CPU time 0.83 seconds
Started Mar 19 02:48:09 PM PDT 24
Finished Mar 19 02:48:11 PM PDT 24
Peak memory 205780 kb
Host smart-33a43d02-b2de-42e7-9f4c-7f384d494ee5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194723767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.2194723767
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.1551172562
Short name T1037
Test name
Test status
Simulation time 13762684 ps
CPU time 0.92 seconds
Started Mar 19 02:48:08 PM PDT 24
Finished Mar 19 02:48:10 PM PDT 24
Peak memory 205772 kb
Host smart-ac68c451-2f8f-44ab-9516-080fa7898948
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1551172562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.1551172562
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.1171842095
Short name T987
Test name
Test status
Simulation time 30102301 ps
CPU time 0.85 seconds
Started Mar 19 02:48:04 PM PDT 24
Finished Mar 19 02:48:05 PM PDT 24
Peak memory 205788 kb
Host smart-2d344ea4-fee1-4231-b464-a8d19be44df6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1171842095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.1171842095
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.2458898871
Short name T917
Test name
Test status
Simulation time 15180387 ps
CPU time 0.71 seconds
Started Mar 19 02:48:13 PM PDT 24
Finished Mar 19 02:48:14 PM PDT 24
Peak memory 205684 kb
Host smart-7d56d7df-b96a-4c33-95f3-ae43c6ad5ca0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458898871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.2458898871
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.2025966877
Short name T972
Test name
Test status
Simulation time 260197694 ps
CPU time 7.45 seconds
Started Mar 19 02:47:49 PM PDT 24
Finished Mar 19 02:47:56 PM PDT 24
Peak memory 206180 kb
Host smart-d7c4a0a0-c599-42e7-aab0-08c6bc0edb33
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025966877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.2
025966877
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.1532619528
Short name T926
Test name
Test status
Simulation time 694853549 ps
CPU time 10.83 seconds
Started Mar 19 02:47:47 PM PDT 24
Finished Mar 19 02:47:59 PM PDT 24
Peak memory 205992 kb
Host smart-70ffd10a-89a9-488a-9a88-32cd292db490
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1532619528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.1
532619528
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.1607756016
Short name T1000
Test name
Test status
Simulation time 35898593 ps
CPU time 0.98 seconds
Started Mar 19 02:47:51 PM PDT 24
Finished Mar 19 02:47:52 PM PDT 24
Peak memory 205864 kb
Host smart-9ab4b25d-4138-478c-8e57-21d85868b1d0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607756016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.1
607756016
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.2968772071
Short name T1072
Test name
Test status
Simulation time 58015927 ps
CPU time 2.25 seconds
Started Mar 19 02:47:50 PM PDT 24
Finished Mar 19 02:47:52 PM PDT 24
Peak memory 214316 kb
Host smart-67a13544-6136-4a6f-9a5a-b64252cc0162
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2968772071 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.2968772071
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.2321401401
Short name T155
Test name
Test status
Simulation time 24494613 ps
CPU time 1.21 seconds
Started Mar 19 02:47:49 PM PDT 24
Finished Mar 19 02:47:50 PM PDT 24
Peak memory 206044 kb
Host smart-486351f5-6452-462d-8a75-99ad607314ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321401401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.2321401401
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.3809265635
Short name T914
Test name
Test status
Simulation time 17769948 ps
CPU time 0.83 seconds
Started Mar 19 02:47:46 PM PDT 24
Finished Mar 19 02:47:47 PM PDT 24
Peak memory 205696 kb
Host smart-754372c8-e349-4235-81bb-c038334cd50d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3809265635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.3809265635
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.733230679
Short name T1018
Test name
Test status
Simulation time 455956050 ps
CPU time 2.97 seconds
Started Mar 19 02:47:51 PM PDT 24
Finished Mar 19 02:47:54 PM PDT 24
Peak memory 206104 kb
Host smart-aabe5dfb-d16e-4b60-a317-d9378960a7e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733230679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sam
e_csr_outstanding.733230679
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.4123701309
Short name T979
Test name
Test status
Simulation time 169575871 ps
CPU time 5.26 seconds
Started Mar 19 02:47:50 PM PDT 24
Finished Mar 19 02:47:55 PM PDT 24
Peak memory 222744 kb
Host smart-c31e2ada-9eee-42a5-a484-6f5d3b3c07a1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123701309 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.4123701309
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.2025203468
Short name T159
Test name
Test status
Simulation time 223422795 ps
CPU time 5.63 seconds
Started Mar 19 02:47:48 PM PDT 24
Finished Mar 19 02:47:54 PM PDT 24
Peak memory 214608 kb
Host smart-fe64e3ee-ea4f-403c-98a5-7e0e64fe693e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025203468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.2025203468
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.3751868987
Short name T999
Test name
Test status
Simulation time 55183197 ps
CPU time 2.47 seconds
Started Mar 19 02:47:48 PM PDT 24
Finished Mar 19 02:47:51 PM PDT 24
Peak memory 215920 kb
Host smart-faa11d12-4c55-44c2-a246-bc4e133adc30
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751868987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.3751868987
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.2000019063
Short name T173
Test name
Test status
Simulation time 193917129 ps
CPU time 5.51 seconds
Started Mar 19 02:47:48 PM PDT 24
Finished Mar 19 02:47:54 PM PDT 24
Peak memory 209844 kb
Host smart-523e255b-08e9-46ff-b52e-13306d3425cd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000019063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err
.2000019063
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.4235773120
Short name T1029
Test name
Test status
Simulation time 14620198 ps
CPU time 0.88 seconds
Started Mar 19 02:48:14 PM PDT 24
Finished Mar 19 02:48:16 PM PDT 24
Peak memory 205684 kb
Host smart-2e681eeb-1eed-4095-964f-ab40623a390e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235773120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.4235773120
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.1309524596
Short name T949
Test name
Test status
Simulation time 34293046 ps
CPU time 0.83 seconds
Started Mar 19 02:48:03 PM PDT 24
Finished Mar 19 02:48:04 PM PDT 24
Peak memory 205772 kb
Host smart-52d2305d-b274-47b9-9c9f-169b74f7796f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1309524596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.1309524596
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.3166278636
Short name T1013
Test name
Test status
Simulation time 35394644 ps
CPU time 0.84 seconds
Started Mar 19 02:48:03 PM PDT 24
Finished Mar 19 02:48:04 PM PDT 24
Peak memory 205800 kb
Host smart-379caa36-9676-4b73-970c-837ee411f8d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3166278636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.3166278636
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.3078121923
Short name T940
Test name
Test status
Simulation time 174921948 ps
CPU time 0.84 seconds
Started Mar 19 02:48:04 PM PDT 24
Finished Mar 19 02:48:05 PM PDT 24
Peak memory 205788 kb
Host smart-de8dd2f8-15be-4ffd-af55-c7b61f3ef02d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3078121923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.3078121923
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.1192373072
Short name T1034
Test name
Test status
Simulation time 35128396 ps
CPU time 0.85 seconds
Started Mar 19 02:48:10 PM PDT 24
Finished Mar 19 02:48:12 PM PDT 24
Peak memory 205752 kb
Host smart-87a90007-3e81-4c8e-96ad-570c46ccfa55
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1192373072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.1192373072
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.103866490
Short name T941
Test name
Test status
Simulation time 10176434 ps
CPU time 0.87 seconds
Started Mar 19 02:48:06 PM PDT 24
Finished Mar 19 02:48:07 PM PDT 24
Peak memory 205804 kb
Host smart-91502dea-ece5-4ead-b098-6067f68e7a5c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103866490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.103866490
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.649954398
Short name T913
Test name
Test status
Simulation time 18307439 ps
CPU time 0.76 seconds
Started Mar 19 02:48:03 PM PDT 24
Finished Mar 19 02:48:03 PM PDT 24
Peak memory 205772 kb
Host smart-3a609338-04f5-45da-a435-b7605d02fbc1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649954398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.649954398
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.30789482
Short name T955
Test name
Test status
Simulation time 30704101 ps
CPU time 0.83 seconds
Started Mar 19 02:48:11 PM PDT 24
Finished Mar 19 02:48:13 PM PDT 24
Peak memory 205768 kb
Host smart-44ef1e45-870d-4eef-942d-ebc3112cbcbf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30789482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.30789482
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.1085656283
Short name T1021
Test name
Test status
Simulation time 9396679 ps
CPU time 0.75 seconds
Started Mar 19 02:48:09 PM PDT 24
Finished Mar 19 02:48:11 PM PDT 24
Peak memory 205752 kb
Host smart-c4b81e5f-ab34-44e7-8e2c-7475b59342bb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1085656283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.1085656283
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.472862641
Short name T908
Test name
Test status
Simulation time 33917107 ps
CPU time 0.77 seconds
Started Mar 19 02:48:15 PM PDT 24
Finished Mar 19 02:48:16 PM PDT 24
Peak memory 205776 kb
Host smart-563fbceb-ce33-429b-8864-1eccd0458bfa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=472862641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.472862641
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.385498179
Short name T991
Test name
Test status
Simulation time 962013915 ps
CPU time 8.39 seconds
Started Mar 19 02:47:47 PM PDT 24
Finished Mar 19 02:47:56 PM PDT 24
Peak memory 206064 kb
Host smart-e7952181-2871-4017-8bc3-bbb080e01057
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=385498179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.385498179
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.1288750948
Short name T912
Test name
Test status
Simulation time 499341000 ps
CPU time 14.84 seconds
Started Mar 19 02:47:48 PM PDT 24
Finished Mar 19 02:48:03 PM PDT 24
Peak memory 206120 kb
Host smart-4cc0ce57-f196-42e1-936f-b9db44e103fb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288750948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.1
288750948
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.2691170454
Short name T1047
Test name
Test status
Simulation time 113276252 ps
CPU time 1.08 seconds
Started Mar 19 02:47:47 PM PDT 24
Finished Mar 19 02:47:49 PM PDT 24
Peak memory 206168 kb
Host smart-6270d53e-af46-48b6-bc28-5c9dbb1a2af3
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2691170454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.2
691170454
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.661689799
Short name T931
Test name
Test status
Simulation time 575680132 ps
CPU time 2.55 seconds
Started Mar 19 02:47:47 PM PDT 24
Finished Mar 19 02:47:50 PM PDT 24
Peak memory 214256 kb
Host smart-9913ac7b-80e7-4113-aff7-1fcbcb550777
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661689799 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.661689799
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.3570163803
Short name T966
Test name
Test status
Simulation time 32990342 ps
CPU time 1.12 seconds
Started Mar 19 02:47:50 PM PDT 24
Finished Mar 19 02:47:51 PM PDT 24
Peak memory 206044 kb
Host smart-27b9b75f-bc33-4022-abe7-39dde44f2ecd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570163803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.3570163803
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.1883668067
Short name T959
Test name
Test status
Simulation time 18794557 ps
CPU time 0.88 seconds
Started Mar 19 02:47:48 PM PDT 24
Finished Mar 19 02:47:49 PM PDT 24
Peak memory 205728 kb
Host smart-6864ece6-eb27-4a5a-92ad-c1a7f92b315e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883668067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.1883668067
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.890187639
Short name T1022
Test name
Test status
Simulation time 159237678 ps
CPU time 2.46 seconds
Started Mar 19 02:47:52 PM PDT 24
Finished Mar 19 02:47:58 PM PDT 24
Peak memory 206088 kb
Host smart-923c3ec7-e490-4888-acb6-e167ad1169d7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890187639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sam
e_csr_outstanding.890187639
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.2634881811
Short name T120
Test name
Test status
Simulation time 218543697 ps
CPU time 4.27 seconds
Started Mar 19 02:47:48 PM PDT 24
Finished Mar 19 02:47:53 PM PDT 24
Peak memory 219352 kb
Host smart-d946f16b-5da5-4955-ada8-79643c2884fc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634881811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.2634881811
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.2369237499
Short name T1005
Test name
Test status
Simulation time 1858189017 ps
CPU time 3.62 seconds
Started Mar 19 02:47:48 PM PDT 24
Finished Mar 19 02:47:52 PM PDT 24
Peak memory 214188 kb
Host smart-1f91d02b-c658-485c-849b-45e837066e49
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2369237499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.2369237499
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.3808249512
Short name T184
Test name
Test status
Simulation time 5136215639 ps
CPU time 29.4 seconds
Started Mar 19 02:47:52 PM PDT 24
Finished Mar 19 02:48:22 PM PDT 24
Peak memory 214396 kb
Host smart-5c8462f7-2721-48ce-b97d-537a20cec574
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3808249512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.3808249512
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.1091234376
Short name T924
Test name
Test status
Simulation time 25535638 ps
CPU time 0.71 seconds
Started Mar 19 02:48:26 PM PDT 24
Finished Mar 19 02:48:27 PM PDT 24
Peak memory 205692 kb
Host smart-084742ca-e97b-4c8a-aa43-d959e51584fe
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1091234376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.1091234376
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.681076641
Short name T1057
Test name
Test status
Simulation time 53162406 ps
CPU time 0.86 seconds
Started Mar 19 02:48:14 PM PDT 24
Finished Mar 19 02:48:15 PM PDT 24
Peak memory 205788 kb
Host smart-40e0bffd-d336-45fd-a06a-37b16f407b96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=681076641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.681076641
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.4016995778
Short name T918
Test name
Test status
Simulation time 10415423 ps
CPU time 0.74 seconds
Started Mar 19 02:48:16 PM PDT 24
Finished Mar 19 02:48:17 PM PDT 24
Peak memory 205776 kb
Host smart-6ab1de19-caeb-4b76-a155-c78d9a17c447
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016995778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.4016995778
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.1651310180
Short name T1061
Test name
Test status
Simulation time 10693772 ps
CPU time 0.83 seconds
Started Mar 19 02:48:24 PM PDT 24
Finished Mar 19 02:48:25 PM PDT 24
Peak memory 205776 kb
Host smart-65dd317f-4509-46f5-9063-7a321f9ee9f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651310180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.1651310180
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.2540340099
Short name T993
Test name
Test status
Simulation time 15199388 ps
CPU time 0.93 seconds
Started Mar 19 02:48:28 PM PDT 24
Finished Mar 19 02:48:30 PM PDT 24
Peak memory 205936 kb
Host smart-4a114b4d-91b0-425d-9355-bd9070913413
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2540340099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.2540340099
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.3087269629
Short name T970
Test name
Test status
Simulation time 46287100 ps
CPU time 0.81 seconds
Started Mar 19 02:48:24 PM PDT 24
Finished Mar 19 02:48:25 PM PDT 24
Peak memory 205664 kb
Host smart-4b47a2b2-05d1-488c-87c7-8c0c3eef719a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087269629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.3087269629
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.3151991936
Short name T973
Test name
Test status
Simulation time 12173948 ps
CPU time 0.91 seconds
Started Mar 19 02:48:23 PM PDT 24
Finished Mar 19 02:48:24 PM PDT 24
Peak memory 205792 kb
Host smart-b5e86ad5-83a5-4d8f-8ad2-ef24e64e619a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3151991936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.3151991936
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.4155879720
Short name T1010
Test name
Test status
Simulation time 33402728 ps
CPU time 0.71 seconds
Started Mar 19 02:48:15 PM PDT 24
Finished Mar 19 02:48:16 PM PDT 24
Peak memory 205772 kb
Host smart-6efa0d85-fe28-4e8d-ad76-9cb06c67a0ec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155879720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.4155879720
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.3382564414
Short name T971
Test name
Test status
Simulation time 10753352 ps
CPU time 0.74 seconds
Started Mar 19 02:48:27 PM PDT 24
Finished Mar 19 02:48:28 PM PDT 24
Peak memory 205760 kb
Host smart-421aad99-d31c-4e52-aaba-648e13c25fc0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3382564414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.3382564414
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.2629358654
Short name T997
Test name
Test status
Simulation time 17745443 ps
CPU time 0.88 seconds
Started Mar 19 02:48:27 PM PDT 24
Finished Mar 19 02:48:28 PM PDT 24
Peak memory 205696 kb
Host smart-a8073b23-6eb9-435d-ba7d-aa805c9746a0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629358654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.2629358654
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.3069295459
Short name T989
Test name
Test status
Simulation time 50143380 ps
CPU time 1.59 seconds
Started Mar 19 02:47:50 PM PDT 24
Finished Mar 19 02:47:51 PM PDT 24
Peak memory 214200 kb
Host smart-4aaf9489-27ca-4e85-b90d-187b95ef69c0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3069295459 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.3069295459
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.3512653077
Short name T954
Test name
Test status
Simulation time 83569224 ps
CPU time 1.4 seconds
Started Mar 19 02:47:47 PM PDT 24
Finished Mar 19 02:47:50 PM PDT 24
Peak memory 206012 kb
Host smart-d815868b-2f76-40cd-97c6-4deebbdeaadd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3512653077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.3512653077
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.624609075
Short name T910
Test name
Test status
Simulation time 9186504 ps
CPU time 0.73 seconds
Started Mar 19 02:47:50 PM PDT 24
Finished Mar 19 02:47:51 PM PDT 24
Peak memory 205768 kb
Host smart-3f941fa1-2e82-47d4-a1a0-ccee4a23f770
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=624609075 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.624609075
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.3518644232
Short name T1056
Test name
Test status
Simulation time 441142293 ps
CPU time 2.66 seconds
Started Mar 19 02:47:48 PM PDT 24
Finished Mar 19 02:47:51 PM PDT 24
Peak memory 206120 kb
Host smart-224bec7a-127b-4998-8a04-76b4248b913b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518644232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.3518644232
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.2455547902
Short name T961
Test name
Test status
Simulation time 71993649 ps
CPU time 2.53 seconds
Started Mar 19 02:47:48 PM PDT 24
Finished Mar 19 02:47:51 PM PDT 24
Peak memory 214592 kb
Host smart-78e52253-6f23-4800-8dc3-66e407b88e31
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455547902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.2455547902
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.3604102277
Short name T1054
Test name
Test status
Simulation time 1455867596 ps
CPU time 8 seconds
Started Mar 19 02:47:52 PM PDT 24
Finished Mar 19 02:48:00 PM PDT 24
Peak memory 214656 kb
Host smart-ed321556-635c-46ae-8082-90d3386e4a3d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604102277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
keymgr_shadow_reg_errors_with_csr_rw.3604102277
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.964251025
Short name T1068
Test name
Test status
Simulation time 750825456 ps
CPU time 4.46 seconds
Started Mar 19 02:47:48 PM PDT 24
Finished Mar 19 02:47:53 PM PDT 24
Peak memory 222436 kb
Host smart-ef19c8a5-4871-4954-8cb1-af1d7111d9f0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=964251025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.964251025
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.2379557216
Short name T187
Test name
Test status
Simulation time 436669098 ps
CPU time 5.19 seconds
Started Mar 19 02:47:50 PM PDT 24
Finished Mar 19 02:47:55 PM PDT 24
Peak memory 209488 kb
Host smart-c0c33cc3-7297-487d-9c4a-404f44b0120c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379557216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.2379557216
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.3890609973
Short name T1063
Test name
Test status
Simulation time 34660544 ps
CPU time 1.15 seconds
Started Mar 19 02:47:51 PM PDT 24
Finished Mar 19 02:47:53 PM PDT 24
Peak memory 214340 kb
Host smart-b2022b4e-d649-42be-be23-64802e5814b9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3890609973 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.3890609973
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.2464301381
Short name T952
Test name
Test status
Simulation time 50631187 ps
CPU time 1.44 seconds
Started Mar 19 02:47:47 PM PDT 24
Finished Mar 19 02:47:50 PM PDT 24
Peak memory 206084 kb
Host smart-ae174a51-175d-4bcc-ab06-898d2344db0a
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2464301381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.2464301381
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.1984561295
Short name T1066
Test name
Test status
Simulation time 9406822 ps
CPU time 0.88 seconds
Started Mar 19 02:47:51 PM PDT 24
Finished Mar 19 02:47:52 PM PDT 24
Peak memory 205696 kb
Host smart-03199479-46f4-4c4b-81fe-c3fbd9602b72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984561295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.1984561295
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.484891297
Short name T981
Test name
Test status
Simulation time 29351996 ps
CPU time 1.87 seconds
Started Mar 19 02:48:05 PM PDT 24
Finished Mar 19 02:48:07 PM PDT 24
Peak memory 206104 kb
Host smart-ed709251-f9b6-4589-8d48-5c7ff189bcc5
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=484891297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sam
e_csr_outstanding.484891297
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.3326537768
Short name T1058
Test name
Test status
Simulation time 300998768 ps
CPU time 6.08 seconds
Started Mar 19 02:47:48 PM PDT 24
Finished Mar 19 02:47:54 PM PDT 24
Peak memory 222728 kb
Host smart-63735203-06dc-44e4-b208-eb630e6890b1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326537768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.3326537768
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.2410688811
Short name T1055
Test name
Test status
Simulation time 306273357 ps
CPU time 8.74 seconds
Started Mar 19 02:47:49 PM PDT 24
Finished Mar 19 02:47:58 PM PDT 24
Peak memory 214596 kb
Host smart-9fb2f232-a47d-460f-afe0-38c8ac0dc2e4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2410688811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
keymgr_shadow_reg_errors_with_csr_rw.2410688811
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.1646156607
Short name T950
Test name
Test status
Simulation time 278466784 ps
CPU time 2.79 seconds
Started Mar 19 02:47:50 PM PDT 24
Finished Mar 19 02:47:53 PM PDT 24
Peak memory 214156 kb
Host smart-91dba0f2-6e84-432a-940c-cedee193934a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646156607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.1646156607
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.2033105052
Short name T919
Test name
Test status
Simulation time 47798332 ps
CPU time 2.02 seconds
Started Mar 19 02:47:50 PM PDT 24
Finished Mar 19 02:47:52 PM PDT 24
Peak memory 206104 kb
Host smart-807755d8-4ef8-42a2-b628-ae983f424250
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2033105052 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.2033105052
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.2317988481
Short name T956
Test name
Test status
Simulation time 23398769 ps
CPU time 0.99 seconds
Started Mar 19 02:47:48 PM PDT 24
Finished Mar 19 02:47:49 PM PDT 24
Peak memory 205908 kb
Host smart-d17642ca-8938-4776-8f58-d8cdd87a4043
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2317988481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.2317988481
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.242000730
Short name T1044
Test name
Test status
Simulation time 40012267 ps
CPU time 0.84 seconds
Started Mar 19 02:47:53 PM PDT 24
Finished Mar 19 02:47:54 PM PDT 24
Peak memory 205760 kb
Host smart-a22f424a-e26c-4a2c-9eaa-78f38f47407c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242000730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.242000730
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.3970819910
Short name T1012
Test name
Test status
Simulation time 109365385 ps
CPU time 2.76 seconds
Started Mar 19 02:47:48 PM PDT 24
Finished Mar 19 02:47:51 PM PDT 24
Peak memory 206124 kb
Host smart-5e864141-6e54-4921-abe9-e4bee818c0c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3970819910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.3970819910
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.768955285
Short name T960
Test name
Test status
Simulation time 323251713 ps
CPU time 5.11 seconds
Started Mar 19 02:47:47 PM PDT 24
Finished Mar 19 02:47:53 PM PDT 24
Peak memory 214624 kb
Host smart-df9809e9-d955-4045-937b-3ced4e1e15fe
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768955285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shadow
_reg_errors.768955285
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.4280201763
Short name T984
Test name
Test status
Simulation time 611490099 ps
CPU time 18.32 seconds
Started Mar 19 02:47:50 PM PDT 24
Finished Mar 19 02:48:08 PM PDT 24
Peak memory 214600 kb
Host smart-8068d325-de6d-4dcb-8e0d-db6fc7d40d05
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280201763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
keymgr_shadow_reg_errors_with_csr_rw.4280201763
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.3184223895
Short name T911
Test name
Test status
Simulation time 157394106 ps
CPU time 1.47 seconds
Started Mar 19 02:47:50 PM PDT 24
Finished Mar 19 02:47:52 PM PDT 24
Peak memory 214224 kb
Host smart-0b33d7f1-a05f-4bce-a561-de85067c3286
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3184223895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.3184223895
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.3975225513
Short name T982
Test name
Test status
Simulation time 48591439 ps
CPU time 1.18 seconds
Started Mar 19 02:47:51 PM PDT 24
Finished Mar 19 02:47:52 PM PDT 24
Peak memory 206040 kb
Host smart-e7a3cfe7-d428-4dfe-9269-bbdba45e64f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3975225513 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.3975225513
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.538142652
Short name T1001
Test name
Test status
Simulation time 14724347 ps
CPU time 1.09 seconds
Started Mar 19 02:47:51 PM PDT 24
Finished Mar 19 02:47:52 PM PDT 24
Peak memory 205908 kb
Host smart-e7224e9d-706f-447d-aa91-73952aab4f1c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538142652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.538142652
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.1926605996
Short name T939
Test name
Test status
Simulation time 8308076 ps
CPU time 0.73 seconds
Started Mar 19 02:47:51 PM PDT 24
Finished Mar 19 02:47:52 PM PDT 24
Peak memory 205768 kb
Host smart-32d58a9a-dcf8-463a-9394-59bba6f2e427
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1926605996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.1926605996
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.2498520998
Short name T1016
Test name
Test status
Simulation time 137901184 ps
CPU time 2.67 seconds
Started Mar 19 02:47:49 PM PDT 24
Finished Mar 19 02:47:51 PM PDT 24
Peak memory 206084 kb
Host smart-f6877044-c233-481d-bbb2-9e7fdcf91119
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2498520998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.2498520998
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.2148014267
Short name T1017
Test name
Test status
Simulation time 339622000 ps
CPU time 2.95 seconds
Started Mar 19 02:47:50 PM PDT 24
Finished Mar 19 02:47:53 PM PDT 24
Peak memory 214584 kb
Host smart-827ca0a7-7629-4da2-9767-4e95e94034b7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2148014267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.2148014267
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.2103538763
Short name T1014
Test name
Test status
Simulation time 88810510 ps
CPU time 3.96 seconds
Started Mar 19 02:47:49 PM PDT 24
Finished Mar 19 02:47:53 PM PDT 24
Peak memory 214704 kb
Host smart-3383b697-a2cd-414e-bf7a-1498ce2085c8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2103538763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
keymgr_shadow_reg_errors_with_csr_rw.2103538763
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.1090871574
Short name T994
Test name
Test status
Simulation time 155249307 ps
CPU time 2.99 seconds
Started Mar 19 02:47:49 PM PDT 24
Finished Mar 19 02:47:52 PM PDT 24
Peak memory 216536 kb
Host smart-d4262381-4b3b-4065-9145-557a8b2b3891
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1090871574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.1090871574
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.1080374071
Short name T162
Test name
Test status
Simulation time 123546246 ps
CPU time 5.42 seconds
Started Mar 19 02:47:47 PM PDT 24
Finished Mar 19 02:47:53 PM PDT 24
Peak memory 209512 kb
Host smart-3dbb1285-feea-4dc3-bc4d-d1a687690c8b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080374071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.1080374071
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.60407689
Short name T929
Test name
Test status
Simulation time 115690247 ps
CPU time 1.08 seconds
Started Mar 19 02:47:50 PM PDT 24
Finished Mar 19 02:47:57 PM PDT 24
Peak memory 205932 kb
Host smart-0aabe83c-0a97-4963-a101-e63f32069454
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=60407689 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.60407689
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.745785142
Short name T1002
Test name
Test status
Simulation time 30999787 ps
CPU time 1.7 seconds
Started Mar 19 02:47:57 PM PDT 24
Finished Mar 19 02:47:59 PM PDT 24
Peak memory 206100 kb
Host smart-f6b1d06c-1780-4f1d-a2b6-537e9060e20d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=745785142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.745785142
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.685111040
Short name T998
Test name
Test status
Simulation time 15533123 ps
CPU time 0.79 seconds
Started Mar 19 02:47:51 PM PDT 24
Finished Mar 19 02:47:52 PM PDT 24
Peak memory 205796 kb
Host smart-61e7a3a6-f915-4a15-8dad-546039275118
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685111040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.685111040
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.570816705
Short name T1035
Test name
Test status
Simulation time 29526700 ps
CPU time 1.33 seconds
Started Mar 19 02:47:51 PM PDT 24
Finished Mar 19 02:47:53 PM PDT 24
Peak memory 206016 kb
Host smart-33436787-5a4d-4cf0-800b-b1fd80607ac9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=570816705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sam
e_csr_outstanding.570816705
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.169244137
Short name T126
Test name
Test status
Simulation time 345518237 ps
CPU time 7.14 seconds
Started Mar 19 02:48:02 PM PDT 24
Finished Mar 19 02:48:09 PM PDT 24
Peak memory 214640 kb
Host smart-5de9753f-37b6-4a3c-8583-9454a8d58cc2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169244137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shadow
_reg_errors.169244137
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.2206753011
Short name T978
Test name
Test status
Simulation time 1080748881 ps
CPU time 6.92 seconds
Started Mar 19 02:48:00 PM PDT 24
Finished Mar 19 02:48:07 PM PDT 24
Peak memory 214652 kb
Host smart-68bd570e-cb6e-4979-811d-18eeee6cdfc4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2206753011 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.2206753011
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.3155235590
Short name T1032
Test name
Test status
Simulation time 34830301 ps
CPU time 2.34 seconds
Started Mar 19 02:47:51 PM PDT 24
Finished Mar 19 02:47:53 PM PDT 24
Peak memory 217392 kb
Host smart-064e9018-24d9-4d41-93d7-c513d1e38024
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155235590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.3155235590
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.479072578
Short name T878
Test name
Test status
Simulation time 30344803 ps
CPU time 0.75 seconds
Started Mar 19 03:21:13 PM PDT 24
Finished Mar 19 03:21:14 PM PDT 24
Peak memory 206444 kb
Host smart-e9fbc9d5-bc67-4ca8-b869-295d14838925
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479072578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.479072578
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.1524835243
Short name T405
Test name
Test status
Simulation time 42630534 ps
CPU time 1.78 seconds
Started Mar 19 03:21:12 PM PDT 24
Finished Mar 19 03:21:14 PM PDT 24
Peak memory 222988 kb
Host smart-5c0f18d2-7c50-43c1-a326-dd86ab7cadab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524835243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.1524835243
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.3149877485
Short name T97
Test name
Test status
Simulation time 363331658 ps
CPU time 3.97 seconds
Started Mar 19 03:21:13 PM PDT 24
Finished Mar 19 03:21:17 PM PDT 24
Peak memory 209184 kb
Host smart-ac8d3763-911e-479a-86a1-5f5fa5f8de63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149877485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.3149877485
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.2761909781
Short name T277
Test name
Test status
Simulation time 639725619 ps
CPU time 9.09 seconds
Started Mar 19 03:21:12 PM PDT 24
Finished Mar 19 03:21:21 PM PDT 24
Peak memory 214784 kb
Host smart-13b4e9d5-32cd-40e1-847e-9fb065594d01
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2761909781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.2761909781
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.1845032151
Short name T600
Test name
Test status
Simulation time 521320499 ps
CPU time 5.85 seconds
Started Mar 19 03:21:08 PM PDT 24
Finished Mar 19 03:21:14 PM PDT 24
Peak memory 222988 kb
Host smart-ac4a80f9-35db-45fb-b8b6-4826bc7ec203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845032151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.1845032151
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.2331243313
Short name T85
Test name
Test status
Simulation time 138112515 ps
CPU time 6.69 seconds
Started Mar 19 03:21:09 PM PDT 24
Finished Mar 19 03:21:16 PM PDT 24
Peak memory 218880 kb
Host smart-d7e71dd8-6ff4-4684-9f98-62137e4af812
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2331243313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.2331243313
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sideload.502367963
Short name T137
Test name
Test status
Simulation time 198096626 ps
CPU time 2.92 seconds
Started Mar 19 03:21:09 PM PDT 24
Finished Mar 19 03:21:12 PM PDT 24
Peak memory 207268 kb
Host smart-8d0be8bf-4cc2-47b4-8cb7-71a000169c30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502367963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.502367963
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.1676249957
Short name T841
Test name
Test status
Simulation time 207083193 ps
CPU time 2.53 seconds
Started Mar 19 03:21:09 PM PDT 24
Finished Mar 19 03:21:11 PM PDT 24
Peak memory 207212 kb
Host smart-67e12099-6e9a-44d0-bd12-10442b47f070
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676249957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.1676249957
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.1342861944
Short name T147
Test name
Test status
Simulation time 114151558 ps
CPU time 3.98 seconds
Started Mar 19 03:21:14 PM PDT 24
Finished Mar 19 03:21:18 PM PDT 24
Peak memory 209036 kb
Host smart-6ca26208-22e9-4d52-ae9c-ba1c4205c85a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342861944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.1342861944
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.3222478496
Short name T455
Test name
Test status
Simulation time 203614643 ps
CPU time 2.72 seconds
Started Mar 19 03:21:09 PM PDT 24
Finished Mar 19 03:21:12 PM PDT 24
Peak memory 207192 kb
Host smart-5980cb7e-9ecf-4cc1-9f52-3bb2812b715c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3222478496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.3222478496
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_smoke.4203257509
Short name T208
Test name
Test status
Simulation time 118350306 ps
CPU time 4.6 seconds
Started Mar 19 03:21:16 PM PDT 24
Finished Mar 19 03:21:21 PM PDT 24
Peak memory 207192 kb
Host smart-4b4a16e7-1511-47e3-8f65-749f181b0ec6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203257509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.4203257509
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all_with_rand_reset.2949867763
Short name T133
Test name
Test status
Simulation time 243021785 ps
CPU time 9.29 seconds
Started Mar 19 03:21:11 PM PDT 24
Finished Mar 19 03:21:21 PM PDT 24
Peak memory 223084 kb
Host smart-80abcb88-b826-4c70-bc99-7a93fc79c061
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949867763 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all_with_rand_reset.2949867763
Directory /workspace/0.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.2355465566
Short name T712
Test name
Test status
Simulation time 1192777644 ps
CPU time 38.98 seconds
Started Mar 19 03:21:11 PM PDT 24
Finished Mar 19 03:21:51 PM PDT 24
Peak memory 214792 kb
Host smart-918485f9-1d03-42d7-b785-db5116e33684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355465566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.2355465566
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.1515715322
Short name T178
Test name
Test status
Simulation time 84889118 ps
CPU time 3.06 seconds
Started Mar 19 03:21:12 PM PDT 24
Finished Mar 19 03:21:15 PM PDT 24
Peak memory 210212 kb
Host smart-936c48d3-9275-4a8c-8479-6bf4bb6533d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515715322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.1515715322
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.2890363262
Short name T552
Test name
Test status
Simulation time 15312759 ps
CPU time 0.78 seconds
Started Mar 19 03:21:11 PM PDT 24
Finished Mar 19 03:21:12 PM PDT 24
Peak memory 206348 kb
Host smart-f07b6f94-f668-44bd-9a3a-6d093b9343af
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2890363262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.2890363262
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.134826325
Short name T412
Test name
Test status
Simulation time 44439774 ps
CPU time 3.37 seconds
Started Mar 19 03:21:11 PM PDT 24
Finished Mar 19 03:21:15 PM PDT 24
Peak memory 216048 kb
Host smart-282a9145-bedb-4601-9467-0ca9c318c066
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=134826325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.134826325
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.400385336
Short name T63
Test name
Test status
Simulation time 288484937 ps
CPU time 3.68 seconds
Started Mar 19 03:21:16 PM PDT 24
Finished Mar 19 03:21:20 PM PDT 24
Peak memory 210960 kb
Host smart-ea2902ff-55a3-42a8-aebe-a84cce233048
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=400385336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.400385336
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.1387454056
Short name T825
Test name
Test status
Simulation time 884144417 ps
CPU time 10.82 seconds
Started Mar 19 03:21:14 PM PDT 24
Finished Mar 19 03:21:25 PM PDT 24
Peak memory 215720 kb
Host smart-9c24be97-88fa-4b6e-a0eb-5f3d79fba089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387454056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.1387454056
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.2269451725
Short name T837
Test name
Test status
Simulation time 3127978439 ps
CPU time 10.84 seconds
Started Mar 19 03:21:13 PM PDT 24
Finished Mar 19 03:21:25 PM PDT 24
Peak memory 211520 kb
Host smart-40153e81-75ee-4338-8676-163928b422c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269451725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.2269451725
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.1013743067
Short name T245
Test name
Test status
Simulation time 929233452 ps
CPU time 13.33 seconds
Started Mar 19 03:21:13 PM PDT 24
Finished Mar 19 03:21:27 PM PDT 24
Peak memory 214800 kb
Host smart-242c0608-a9be-482a-a01c-6f3271112690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1013743067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.1013743067
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.824510873
Short name T860
Test name
Test status
Simulation time 55998766 ps
CPU time 3.63 seconds
Started Mar 19 03:21:17 PM PDT 24
Finished Mar 19 03:21:21 PM PDT 24
Peak memory 209672 kb
Host smart-10815085-45a5-4863-804e-44b9c8697566
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=824510873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.824510873
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.268291540
Short name T104
Test name
Test status
Simulation time 1774658928 ps
CPU time 27.92 seconds
Started Mar 19 03:21:15 PM PDT 24
Finished Mar 19 03:21:43 PM PDT 24
Peak memory 236640 kb
Host smart-91e73c11-5d03-4a06-9bff-db82d944178b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268291540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.268291540
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload.3850864296
Short name T639
Test name
Test status
Simulation time 2365590884 ps
CPU time 48.14 seconds
Started Mar 19 03:21:13 PM PDT 24
Finished Mar 19 03:22:01 PM PDT 24
Peak memory 208348 kb
Host smart-4812daf6-c6b2-4d33-9864-57aaf746be63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3850864296 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.3850864296
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.1604896215
Short name T688
Test name
Test status
Simulation time 177031227 ps
CPU time 2.64 seconds
Started Mar 19 03:21:22 PM PDT 24
Finished Mar 19 03:21:25 PM PDT 24
Peak memory 209320 kb
Host smart-45f7f1e0-ad89-450d-b636-e2ef7ed9d5b5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1604896215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.1604896215
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.1995111317
Short name T573
Test name
Test status
Simulation time 48873372 ps
CPU time 2.7 seconds
Started Mar 19 03:21:13 PM PDT 24
Finished Mar 19 03:21:16 PM PDT 24
Peak memory 208824 kb
Host smart-7606f201-db76-4738-9975-17dd34d33c74
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1995111317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.1995111317
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.2676206202
Short name T490
Test name
Test status
Simulation time 245307587 ps
CPU time 3.22 seconds
Started Mar 19 03:21:15 PM PDT 24
Finished Mar 19 03:21:18 PM PDT 24
Peak memory 207300 kb
Host smart-2202c8cd-e97f-4dcb-be09-e57fdbedc96d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2676206202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.2676206202
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.2528128723
Short name T821
Test name
Test status
Simulation time 742493242 ps
CPU time 3.84 seconds
Started Mar 19 03:21:16 PM PDT 24
Finished Mar 19 03:21:19 PM PDT 24
Peak memory 218940 kb
Host smart-3965a0f2-8e54-4cbf-ba34-7040d4618d16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528128723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.2528128723
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.604431419
Short name T719
Test name
Test status
Simulation time 18340818512 ps
CPU time 61.34 seconds
Started Mar 19 03:21:09 PM PDT 24
Finished Mar 19 03:22:11 PM PDT 24
Peak memory 208724 kb
Host smart-e15fdcc2-b342-453b-804c-f5aa5ec7ec32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604431419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.604431419
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.1079116148
Short name T897
Test name
Test status
Simulation time 81451031 ps
CPU time 4.62 seconds
Started Mar 19 03:21:12 PM PDT 24
Finished Mar 19 03:21:17 PM PDT 24
Peak memory 207908 kb
Host smart-9c6bc163-7c19-49f8-b653-8013820cd856
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1079116148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.1079116148
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.1872408563
Short name T189
Test name
Test status
Simulation time 587520211 ps
CPU time 15.09 seconds
Started Mar 19 03:21:16 PM PDT 24
Finished Mar 19 03:21:31 PM PDT 24
Peak memory 211496 kb
Host smart-345418e0-1db7-4f82-9a71-0bb314743fa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1872408563 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.1872408563
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.302586870
Short name T569
Test name
Test status
Simulation time 9593405 ps
CPU time 0.82 seconds
Started Mar 19 03:21:40 PM PDT 24
Finished Mar 19 03:21:40 PM PDT 24
Peak memory 206424 kb
Host smart-e11ce012-5c86-4927-980f-da23ec202b23
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=302586870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.302586870
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.1006521042
Short name T669
Test name
Test status
Simulation time 115473804 ps
CPU time 2.77 seconds
Started Mar 19 03:21:34 PM PDT 24
Finished Mar 19 03:21:37 PM PDT 24
Peak memory 207708 kb
Host smart-b690def3-3787-4bbd-a723-7276e6353bba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006521042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.1006521042
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.3794019506
Short name T304
Test name
Test status
Simulation time 1063904397 ps
CPU time 5.19 seconds
Started Mar 19 03:21:34 PM PDT 24
Finished Mar 19 03:21:40 PM PDT 24
Peak memory 215392 kb
Host smart-b4058127-4642-4d82-8b3c-71db3f744690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794019506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.3794019506
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.3059644656
Short name T355
Test name
Test status
Simulation time 92617145 ps
CPU time 4 seconds
Started Mar 19 03:21:41 PM PDT 24
Finished Mar 19 03:21:45 PM PDT 24
Peak memory 211868 kb
Host smart-4cfa90a3-5c7e-434d-83cf-77a5239cb26c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059644656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.3059644656
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.176561307
Short name T236
Test name
Test status
Simulation time 117363239 ps
CPU time 3.4 seconds
Started Mar 19 03:21:33 PM PDT 24
Finished Mar 19 03:21:37 PM PDT 24
Peak memory 209728 kb
Host smart-0b06c0a7-ff7e-45a5-894d-6cffac9b22d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=176561307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.176561307
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.3600118176
Short name T502
Test name
Test status
Simulation time 1265886525 ps
CPU time 36.77 seconds
Started Mar 19 03:21:40 PM PDT 24
Finished Mar 19 03:22:18 PM PDT 24
Peak memory 208916 kb
Host smart-d301b1e7-984f-4335-a51a-2a8cafa3c45b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600118176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.3600118176
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.1569785069
Short name T699
Test name
Test status
Simulation time 2920477742 ps
CPU time 20 seconds
Started Mar 19 03:21:34 PM PDT 24
Finished Mar 19 03:21:54 PM PDT 24
Peak memory 208976 kb
Host smart-de5b9653-f3a7-4255-9c0e-ed5c5bc565d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569785069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.1569785069
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.782654163
Short name T518
Test name
Test status
Simulation time 247375572 ps
CPU time 5.91 seconds
Started Mar 19 03:21:41 PM PDT 24
Finished Mar 19 03:21:47 PM PDT 24
Peak memory 209144 kb
Host smart-88f07b4e-27dc-4809-a78a-8cd4a9d8e9ae
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782654163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.782654163
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.1011615016
Short name T503
Test name
Test status
Simulation time 1244396934 ps
CPU time 24.23 seconds
Started Mar 19 03:21:31 PM PDT 24
Finished Mar 19 03:21:56 PM PDT 24
Peak memory 208760 kb
Host smart-b0f77e35-4c1c-458d-aec2-e2724ec866ea
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1011615016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.1011615016
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.1775352204
Short name T491
Test name
Test status
Simulation time 1010633865 ps
CPU time 4.6 seconds
Started Mar 19 03:21:41 PM PDT 24
Finished Mar 19 03:21:45 PM PDT 24
Peak memory 208928 kb
Host smart-73b6ac0e-58a3-46b3-9696-b157e4e06ea8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1775352204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.1775352204
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.202252915
Short name T758
Test name
Test status
Simulation time 252739467 ps
CPU time 3.28 seconds
Started Mar 19 03:21:43 PM PDT 24
Finished Mar 19 03:21:46 PM PDT 24
Peak memory 209856 kb
Host smart-3855320c-3844-44cf-8511-21d76c6d8a65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202252915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.202252915
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.97022483
Short name T225
Test name
Test status
Simulation time 736289306 ps
CPU time 5.28 seconds
Started Mar 19 03:21:44 PM PDT 24
Finished Mar 19 03:21:50 PM PDT 24
Peak memory 208776 kb
Host smart-aaec335b-607e-4252-8cbb-a6a3da434172
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=97022483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.97022483
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.3041712658
Short name T437
Test name
Test status
Simulation time 299127578 ps
CPU time 10.8 seconds
Started Mar 19 03:21:41 PM PDT 24
Finished Mar 19 03:21:52 PM PDT 24
Peak memory 207316 kb
Host smart-7bc9c096-895c-49c7-bbfd-0e97a6706827
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041712658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.3041712658
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.467558506
Short name T114
Test name
Test status
Simulation time 451864451 ps
CPU time 2.82 seconds
Started Mar 19 03:21:33 PM PDT 24
Finished Mar 19 03:21:36 PM PDT 24
Peak memory 210724 kb
Host smart-1f711c82-4ac3-41ca-ac62-d2685d291303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467558506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.467558506
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.1796547927
Short name T480
Test name
Test status
Simulation time 38812040 ps
CPU time 0.82 seconds
Started Mar 19 03:21:56 PM PDT 24
Finished Mar 19 03:21:57 PM PDT 24
Peak memory 206432 kb
Host smart-9e2ef802-d7d0-445e-a124-b00849ad5329
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796547927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.1796547927
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.3672748758
Short name T246
Test name
Test status
Simulation time 37323054 ps
CPU time 2.76 seconds
Started Mar 19 03:21:47 PM PDT 24
Finished Mar 19 03:21:50 PM PDT 24
Peak memory 215800 kb
Host smart-98e45133-b4ee-4e6d-8515-12c38a2e05bf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3672748758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.3672748758
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.3858637023
Short name T29
Test name
Test status
Simulation time 73471196 ps
CPU time 2.12 seconds
Started Mar 19 03:21:42 PM PDT 24
Finished Mar 19 03:21:44 PM PDT 24
Peak memory 219816 kb
Host smart-713ff94c-6206-4353-9462-15420b159829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3858637023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.3858637023
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.2899475047
Short name T55
Test name
Test status
Simulation time 64805730 ps
CPU time 1.92 seconds
Started Mar 19 03:21:40 PM PDT 24
Finished Mar 19 03:21:42 PM PDT 24
Peak memory 208048 kb
Host smart-563223bd-80ea-4322-802d-bdcd7ce4d3e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2899475047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.2899475047
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.2115716752
Short name T607
Test name
Test status
Simulation time 4078926380 ps
CPU time 29.86 seconds
Started Mar 19 03:21:49 PM PDT 24
Finished Mar 19 03:22:19 PM PDT 24
Peak memory 221528 kb
Host smart-a01ef71e-6ce8-4532-bad1-60ea95d5f27e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2115716752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.2115716752
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.3352486934
Short name T680
Test name
Test status
Simulation time 536176995 ps
CPU time 4.67 seconds
Started Mar 19 03:21:47 PM PDT 24
Finished Mar 19 03:21:52 PM PDT 24
Peak memory 214836 kb
Host smart-e2a02146-ead1-4277-8cf0-19928e680a71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352486934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.3352486934
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.3120585742
Short name T496
Test name
Test status
Simulation time 48747822 ps
CPU time 3.4 seconds
Started Mar 19 03:21:41 PM PDT 24
Finished Mar 19 03:21:44 PM PDT 24
Peak memory 207864 kb
Host smart-3fa945ba-6eef-4d63-98b9-d60bcef2ea58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120585742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.3120585742
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.1910583282
Short name T761
Test name
Test status
Simulation time 1061166639 ps
CPU time 33.08 seconds
Started Mar 19 03:21:40 PM PDT 24
Finished Mar 19 03:22:14 PM PDT 24
Peak memory 208824 kb
Host smart-cf3a9966-58ab-45a4-a7a9-b617fa7e9d52
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1910583282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.1910583282
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.3899809306
Short name T364
Test name
Test status
Simulation time 3597877904 ps
CPU time 26.99 seconds
Started Mar 19 03:21:40 PM PDT 24
Finished Mar 19 03:22:08 PM PDT 24
Peak memory 208296 kb
Host smart-cd5abdd5-794d-49d8-ac35-f17aad578ee4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3899809306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.3899809306
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.185742627
Short name T598
Test name
Test status
Simulation time 71002411 ps
CPU time 2.56 seconds
Started Mar 19 03:21:43 PM PDT 24
Finished Mar 19 03:21:45 PM PDT 24
Peak memory 207248 kb
Host smart-0ad43878-bfb8-4ecc-a084-598770e2d570
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185742627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.185742627
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.3042308474
Short name T271
Test name
Test status
Simulation time 138160968 ps
CPU time 4.93 seconds
Started Mar 19 03:21:40 PM PDT 24
Finished Mar 19 03:21:46 PM PDT 24
Peak memory 209092 kb
Host smart-f961bac1-c4af-4965-99a7-adb6a8d6fe27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3042308474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.3042308474
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.1588190340
Short name T594
Test name
Test status
Simulation time 42449520 ps
CPU time 2.45 seconds
Started Mar 19 03:21:39 PM PDT 24
Finished Mar 19 03:21:42 PM PDT 24
Peak memory 207204 kb
Host smart-e0010454-70fd-4e88-ae0a-3c297816eaeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1588190340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.1588190340
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.4018260915
Short name T350
Test name
Test status
Simulation time 924118936 ps
CPU time 33.74 seconds
Started Mar 19 03:21:42 PM PDT 24
Finished Mar 19 03:22:16 PM PDT 24
Peak memory 215796 kb
Host smart-8dc66e50-63b4-460b-9ddb-b662d882ec2a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4018260915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.4018260915
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_stress_all_with_rand_reset.920491532
Short name T149
Test name
Test status
Simulation time 2329229349 ps
CPU time 17.2 seconds
Started Mar 19 03:21:40 PM PDT 24
Finished Mar 19 03:21:58 PM PDT 24
Peak memory 223236 kb
Host smart-fbacda96-8a74-42bd-afa5-1cfca92d5c91
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=920491532 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all_with_rand_reset.920491532
Directory /workspace/11.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.2246250827
Short name T700
Test name
Test status
Simulation time 6460195085 ps
CPU time 66.02 seconds
Started Mar 19 03:21:47 PM PDT 24
Finished Mar 19 03:22:53 PM PDT 24
Peak memory 210416 kb
Host smart-27456071-c5f0-48a8-b059-a4a6610765ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246250827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.2246250827
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.1590043637
Short name T36
Test name
Test status
Simulation time 62441717 ps
CPU time 2.09 seconds
Started Mar 19 03:21:41 PM PDT 24
Finished Mar 19 03:21:43 PM PDT 24
Peak memory 210224 kb
Host smart-7841f085-422f-4759-9c93-4dde463ac1a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1590043637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.1590043637
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.2634840898
Short name T533
Test name
Test status
Simulation time 11050838 ps
CPU time 0.84 seconds
Started Mar 19 03:21:45 PM PDT 24
Finished Mar 19 03:21:46 PM PDT 24
Peak memory 206456 kb
Host smart-5149b19c-a8f6-43eb-a32b-5a2dcd2c8a97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2634840898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.2634840898
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.2830214325
Short name T707
Test name
Test status
Simulation time 1078700148 ps
CPU time 20.89 seconds
Started Mar 19 03:21:48 PM PDT 24
Finished Mar 19 03:22:09 PM PDT 24
Peak memory 221284 kb
Host smart-efd05053-8709-4692-98b1-716f92681301
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2830214325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.2830214325
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.2873446568
Short name T577
Test name
Test status
Simulation time 7533380758 ps
CPU time 19.69 seconds
Started Mar 19 03:21:43 PM PDT 24
Finished Mar 19 03:22:03 PM PDT 24
Peak memory 209700 kb
Host smart-a3f60f43-5f79-439a-8f36-94f5b390bce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873446568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.2873446568
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.1912549375
Short name T348
Test name
Test status
Simulation time 232684809 ps
CPU time 4.33 seconds
Started Mar 19 03:21:52 PM PDT 24
Finished Mar 19 03:21:56 PM PDT 24
Peak memory 210180 kb
Host smart-82b52596-b9e1-48e4-a9c4-55b51294aa3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1912549375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.1912549375
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.439329895
Short name T82
Test name
Test status
Simulation time 279073858 ps
CPU time 2.36 seconds
Started Mar 19 03:21:50 PM PDT 24
Finished Mar 19 03:21:53 PM PDT 24
Peak memory 220300 kb
Host smart-cbf64d2f-dd2b-4c65-977b-6d4a10961757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439329895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.439329895
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.3697752229
Short name T812
Test name
Test status
Simulation time 817278030 ps
CPU time 4.77 seconds
Started Mar 19 03:22:03 PM PDT 24
Finished Mar 19 03:22:08 PM PDT 24
Peak memory 209192 kb
Host smart-66932bb3-92d2-47b9-9e0e-df81c8614ee8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3697752229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.3697752229
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.570560126
Short name T614
Test name
Test status
Simulation time 132249958 ps
CPU time 2.67 seconds
Started Mar 19 03:21:49 PM PDT 24
Finished Mar 19 03:21:52 PM PDT 24
Peak memory 209104 kb
Host smart-48b5b9dc-45a7-41cc-a615-eed89e9ef68d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=570560126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.570560126
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.1277626721
Short name T445
Test name
Test status
Simulation time 73498590 ps
CPU time 3.36 seconds
Started Mar 19 03:21:47 PM PDT 24
Finished Mar 19 03:21:50 PM PDT 24
Peak memory 208308 kb
Host smart-ea805a84-e06c-4fe5-b5b3-b16c40e5d5a0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277626721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.1277626721
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.1181433749
Short name T727
Test name
Test status
Simulation time 141557029 ps
CPU time 4.24 seconds
Started Mar 19 03:21:52 PM PDT 24
Finished Mar 19 03:21:57 PM PDT 24
Peak memory 208436 kb
Host smart-6f121794-79bd-49f5-9c4c-dfa43edd700d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1181433749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.1181433749
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.1229308051
Short name T606
Test name
Test status
Simulation time 533875870 ps
CPU time 2.2 seconds
Started Mar 19 03:21:47 PM PDT 24
Finished Mar 19 03:21:50 PM PDT 24
Peak memory 208052 kb
Host smart-a0def0ab-e033-4b1c-947b-82b1e43378c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1229308051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.1229308051
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.341884929
Short name T611
Test name
Test status
Simulation time 120200547 ps
CPU time 2.42 seconds
Started Mar 19 03:21:43 PM PDT 24
Finished Mar 19 03:21:45 PM PDT 24
Peak memory 207488 kb
Host smart-1381c037-ea88-4e6b-9704-fec9e976e6e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=341884929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.341884929
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.3001202663
Short name T337
Test name
Test status
Simulation time 15378014643 ps
CPU time 130.89 seconds
Started Mar 19 03:21:49 PM PDT 24
Finished Mar 19 03:24:00 PM PDT 24
Peak memory 223076 kb
Host smart-ad4e47e2-dd0f-4b27-b3e2-f667b4e3fc45
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001202663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.3001202663
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_stress_all_with_rand_reset.346256246
Short name T683
Test name
Test status
Simulation time 175675410 ps
CPU time 12.17 seconds
Started Mar 19 03:21:48 PM PDT 24
Finished Mar 19 03:22:00 PM PDT 24
Peak memory 223088 kb
Host smart-07aa08ad-bd03-4136-9f1f-2412cbe16e1f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=346256246 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all_with_rand_reset.346256246
Directory /workspace/12.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.975989674
Short name T373
Test name
Test status
Simulation time 213470387 ps
CPU time 5.49 seconds
Started Mar 19 03:21:41 PM PDT 24
Finished Mar 19 03:21:47 PM PDT 24
Peak memory 208568 kb
Host smart-94e9cf7a-ce6f-43eb-a599-efd94623c46f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975989674 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.975989674
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.3969162073
Short name T115
Test name
Test status
Simulation time 306998365 ps
CPU time 2.54 seconds
Started Mar 19 03:21:43 PM PDT 24
Finished Mar 19 03:21:46 PM PDT 24
Peak memory 210812 kb
Host smart-c569a382-d59e-4b38-981c-0292fed3f09a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3969162073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.3969162073
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.2161058808
Short name T756
Test name
Test status
Simulation time 15501396 ps
CPU time 0.76 seconds
Started Mar 19 03:21:49 PM PDT 24
Finished Mar 19 03:21:50 PM PDT 24
Peak memory 206448 kb
Host smart-0b6cae91-89aa-48a3-86b2-f13b5a241390
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2161058808 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.2161058808
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.1064682716
Short name T422
Test name
Test status
Simulation time 99616095 ps
CPU time 3.54 seconds
Started Mar 19 03:21:56 PM PDT 24
Finished Mar 19 03:21:59 PM PDT 24
Peak memory 215696 kb
Host smart-53533550-ebb8-4e5c-842e-28b13fc41d2c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1064682716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.1064682716
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.3640725864
Short name T40
Test name
Test status
Simulation time 53716101 ps
CPU time 1.76 seconds
Started Mar 19 03:21:48 PM PDT 24
Finished Mar 19 03:21:49 PM PDT 24
Peak memory 220720 kb
Host smart-91fa4e8d-8fcc-45f6-996f-ba6713ac01bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3640725864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.3640725864
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.1432571171
Short name T559
Test name
Test status
Simulation time 128860938 ps
CPU time 3.29 seconds
Started Mar 19 03:21:51 PM PDT 24
Finished Mar 19 03:21:55 PM PDT 24
Peak memory 209108 kb
Host smart-d637cc87-df2e-428c-86f9-0aa2c7239ddc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1432571171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.1432571171
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.3940528576
Short name T341
Test name
Test status
Simulation time 1251842911 ps
CPU time 7.62 seconds
Started Mar 19 03:21:42 PM PDT 24
Finished Mar 19 03:21:50 PM PDT 24
Peak memory 222844 kb
Host smart-fd507b60-c970-4ca0-bc84-4cac0706ab40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3940528576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.3940528576
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.3144425909
Short name T816
Test name
Test status
Simulation time 587637805 ps
CPU time 2.26 seconds
Started Mar 19 03:22:01 PM PDT 24
Finished Mar 19 03:22:04 PM PDT 24
Peak memory 206636 kb
Host smart-7cd41c52-5f62-44ed-98d8-aa9da4fe506a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3144425909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.3144425909
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.1323268497
Short name T854
Test name
Test status
Simulation time 1689468998 ps
CPU time 12.22 seconds
Started Mar 19 03:21:53 PM PDT 24
Finished Mar 19 03:22:06 PM PDT 24
Peak memory 207912 kb
Host smart-1eb21c35-dbeb-42e2-8151-fac7bed049eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323268497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.1323268497
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.3185219341
Short name T508
Test name
Test status
Simulation time 63244945 ps
CPU time 2.43 seconds
Started Mar 19 03:21:48 PM PDT 24
Finished Mar 19 03:21:51 PM PDT 24
Peak memory 207180 kb
Host smart-a086b234-1c27-4672-8406-8784a598620a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185219341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.3185219341
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.152385711
Short name T385
Test name
Test status
Simulation time 43798118 ps
CPU time 2.48 seconds
Started Mar 19 03:21:51 PM PDT 24
Finished Mar 19 03:21:54 PM PDT 24
Peak memory 207136 kb
Host smart-2001c123-dbc5-433d-9050-5fb470e959f2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=152385711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.152385711
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.2195442956
Short name T721
Test name
Test status
Simulation time 854831430 ps
CPU time 7.38 seconds
Started Mar 19 03:21:54 PM PDT 24
Finished Mar 19 03:22:01 PM PDT 24
Peak memory 208472 kb
Host smart-e671bdef-3854-498e-86be-d1d4ae319516
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195442956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.2195442956
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.2400593384
Short name T880
Test name
Test status
Simulation time 1652166254 ps
CPU time 4.29 seconds
Started Mar 19 03:21:45 PM PDT 24
Finished Mar 19 03:21:50 PM PDT 24
Peak memory 209216 kb
Host smart-82e29271-879a-430a-ba9a-683d21813442
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400593384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.2400593384
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.3321546997
Short name T675
Test name
Test status
Simulation time 642735616 ps
CPU time 8.29 seconds
Started Mar 19 03:21:52 PM PDT 24
Finished Mar 19 03:22:01 PM PDT 24
Peak memory 209220 kb
Host smart-c6426552-9344-401f-9180-e4669840c431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321546997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.3321546997
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.687665583
Short name T596
Test name
Test status
Simulation time 203314199 ps
CPU time 2.57 seconds
Started Mar 19 03:22:04 PM PDT 24
Finished Mar 19 03:22:07 PM PDT 24
Peak memory 208768 kb
Host smart-a7994169-a5c4-4971-b149-44b910088974
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687665583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.687665583
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all_with_rand_reset.481280410
Short name T111
Test name
Test status
Simulation time 392623804 ps
CPU time 13.45 seconds
Started Mar 19 03:21:59 PM PDT 24
Finished Mar 19 03:22:13 PM PDT 24
Peak memory 223468 kb
Host smart-3594323a-92b5-4e72-a765-94d53a12abaa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=481280410 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all_with_rand_reset.481280410
Directory /workspace/13.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.2487060728
Short name T397
Test name
Test status
Simulation time 140565011 ps
CPU time 2.23 seconds
Started Mar 19 03:21:50 PM PDT 24
Finished Mar 19 03:21:52 PM PDT 24
Peak memory 210416 kb
Host smart-de1202be-3cc7-46ca-8e15-2d39a096871a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2487060728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.2487060728
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.1121147381
Short name T399
Test name
Test status
Simulation time 59382806 ps
CPU time 4.27 seconds
Started Mar 19 03:21:49 PM PDT 24
Finished Mar 19 03:21:53 PM PDT 24
Peak memory 214748 kb
Host smart-b1416a64-1b1c-4bc8-951d-0d62c5bd5439
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1121147381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.1121147381
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.1604671542
Short name T653
Test name
Test status
Simulation time 72428525 ps
CPU time 3.37 seconds
Started Mar 19 03:22:07 PM PDT 24
Finished Mar 19 03:22:10 PM PDT 24
Peak memory 209212 kb
Host smart-aef4438f-3294-40f2-ad9a-b87dc2cf301d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1604671542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.1604671542
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.963305820
Short name T720
Test name
Test status
Simulation time 1510258959 ps
CPU time 9.86 seconds
Started Mar 19 03:21:52 PM PDT 24
Finished Mar 19 03:22:02 PM PDT 24
Peak memory 208788 kb
Host smart-8a9634ee-86af-45e4-bb01-291ffc5e65a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963305820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.963305820
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.3507741404
Short name T279
Test name
Test status
Simulation time 31454402 ps
CPU time 2.32 seconds
Started Mar 19 03:22:07 PM PDT 24
Finished Mar 19 03:22:09 PM PDT 24
Peak memory 209820 kb
Host smart-3a01a598-8581-4175-b689-5f94d5c84aee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3507741404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.3507741404
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.1803381809
Short name T537
Test name
Test status
Simulation time 175105974 ps
CPU time 3.28 seconds
Started Mar 19 03:21:52 PM PDT 24
Finished Mar 19 03:21:55 PM PDT 24
Peak memory 214804 kb
Host smart-37fd994a-6fe5-47e3-94f7-0dc3d57eee60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803381809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.1803381809
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.2126344600
Short name T658
Test name
Test status
Simulation time 93346597 ps
CPU time 4.53 seconds
Started Mar 19 03:21:56 PM PDT 24
Finished Mar 19 03:22:01 PM PDT 24
Peak memory 209720 kb
Host smart-2d195005-9df2-4aaa-9a07-8f02170e1483
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126344600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.2126344600
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.2769765168
Short name T844
Test name
Test status
Simulation time 43558148 ps
CPU time 2.43 seconds
Started Mar 19 03:21:50 PM PDT 24
Finished Mar 19 03:21:52 PM PDT 24
Peak memory 207452 kb
Host smart-1ba041aa-1b44-4bf9-9104-b25bab34b8fa
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769765168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.2769765168
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.315995319
Short name T530
Test name
Test status
Simulation time 125755470 ps
CPU time 2.56 seconds
Started Mar 19 03:21:45 PM PDT 24
Finished Mar 19 03:21:48 PM PDT 24
Peak memory 207256 kb
Host smart-64889e18-f197-4165-a3f9-f972d1c6e8fa
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=315995319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.315995319
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.2531653356
Short name T435
Test name
Test status
Simulation time 183824902 ps
CPU time 5.8 seconds
Started Mar 19 03:22:02 PM PDT 24
Finished Mar 19 03:22:08 PM PDT 24
Peak memory 207144 kb
Host smart-f93f7b3c-e3ad-4c3b-808a-597d764e4bb4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531653356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.2531653356
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.1602703344
Short name T143
Test name
Test status
Simulation time 870861185 ps
CPU time 22.21 seconds
Started Mar 19 03:22:04 PM PDT 24
Finished Mar 19 03:22:27 PM PDT 24
Peak memory 210236 kb
Host smart-20021fc0-d6f0-4444-8960-aa86d854905a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1602703344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.1602703344
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.2656150114
Short name T210
Test name
Test status
Simulation time 387186844 ps
CPU time 3.14 seconds
Started Mar 19 03:22:04 PM PDT 24
Finished Mar 19 03:22:07 PM PDT 24
Peak memory 206964 kb
Host smart-825fc483-d25f-4749-9a52-e573da8aeff5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2656150114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.2656150114
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.2844946631
Short name T851
Test name
Test status
Simulation time 15477684 ps
CPU time 0.76 seconds
Started Mar 19 03:22:04 PM PDT 24
Finished Mar 19 03:22:05 PM PDT 24
Peak memory 206356 kb
Host smart-ae2158cb-fb0e-4d14-a504-a368b0f6ae85
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2844946631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.2844946631
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_stress_all_with_rand_reset.2254252735
Short name T113
Test name
Test status
Simulation time 854044480 ps
CPU time 11.08 seconds
Started Mar 19 03:21:51 PM PDT 24
Finished Mar 19 03:22:02 PM PDT 24
Peak memory 222396 kb
Host smart-7ec57c76-fbc8-4351-a5dc-0b483b79d34e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254252735 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all_with_rand_reset.2254252735
Directory /workspace/14.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.2773353661
Short name T474
Test name
Test status
Simulation time 78473861 ps
CPU time 4 seconds
Started Mar 19 03:21:48 PM PDT 24
Finished Mar 19 03:21:52 PM PDT 24
Peak memory 214796 kb
Host smart-c5dea9a4-31c5-4caa-a5c4-8c5730d2f29d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773353661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.2773353661
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.1911120349
Short name T188
Test name
Test status
Simulation time 167791450 ps
CPU time 2.63 seconds
Started Mar 19 03:21:56 PM PDT 24
Finished Mar 19 03:21:59 PM PDT 24
Peak memory 210676 kb
Host smart-6959d699-eb00-4096-b120-19f7a4b700ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911120349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.1911120349
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.94285036
Short name T457
Test name
Test status
Simulation time 35830386 ps
CPU time 0.87 seconds
Started Mar 19 03:21:57 PM PDT 24
Finished Mar 19 03:21:58 PM PDT 24
Peak memory 206460 kb
Host smart-4e0297eb-74d2-4e03-92c1-8b1ca0cf92da
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94285036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.94285036
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.1522302802
Short name T697
Test name
Test status
Simulation time 24919484 ps
CPU time 1.92 seconds
Started Mar 19 03:21:57 PM PDT 24
Finished Mar 19 03:21:59 PM PDT 24
Peak memory 214816 kb
Host smart-ca137c0b-7e56-4535-92e1-aeb9d7845736
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1522302802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.1522302802
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.1362477394
Short name T378
Test name
Test status
Simulation time 135350727 ps
CPU time 3 seconds
Started Mar 19 03:22:01 PM PDT 24
Finished Mar 19 03:22:04 PM PDT 24
Peak memory 209496 kb
Host smart-ea153c3b-cf04-45de-a20d-622ebfa53a3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362477394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.1362477394
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.1360051012
Short name T278
Test name
Test status
Simulation time 263219383 ps
CPU time 10.43 seconds
Started Mar 19 03:21:54 PM PDT 24
Finished Mar 19 03:22:04 PM PDT 24
Peak memory 214768 kb
Host smart-cb8ee528-18e9-4577-87c7-a21f690858b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1360051012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.1360051012
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.2893246503
Short name T826
Test name
Test status
Simulation time 1018786782 ps
CPU time 7.96 seconds
Started Mar 19 03:22:02 PM PDT 24
Finished Mar 19 03:22:11 PM PDT 24
Peak memory 222948 kb
Host smart-7e44cdc9-db76-4756-a37d-094992710f60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893246503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.2893246503
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.664617738
Short name T764
Test name
Test status
Simulation time 115356934 ps
CPU time 4.54 seconds
Started Mar 19 03:21:58 PM PDT 24
Finished Mar 19 03:22:03 PM PDT 24
Peak memory 209752 kb
Host smart-03dda650-8b68-43cb-b0ef-ece32f0ca4c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=664617738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.664617738
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.851077432
Short name T605
Test name
Test status
Simulation time 66105487 ps
CPU time 2.41 seconds
Started Mar 19 03:21:51 PM PDT 24
Finished Mar 19 03:21:53 PM PDT 24
Peak memory 207088 kb
Host smart-0697add9-05b7-41f7-a8ca-9a0ccf628509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851077432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.851077432
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.454510959
Short name T634
Test name
Test status
Simulation time 15229084056 ps
CPU time 30.01 seconds
Started Mar 19 03:21:50 PM PDT 24
Finished Mar 19 03:22:20 PM PDT 24
Peak memory 209508 kb
Host smart-472e48d5-3059-4515-aae8-b4ccfe8aa1ef
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454510959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.454510959
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.54528212
Short name T744
Test name
Test status
Simulation time 32494324 ps
CPU time 2.44 seconds
Started Mar 19 03:21:58 PM PDT 24
Finished Mar 19 03:22:00 PM PDT 24
Peak memory 208064 kb
Host smart-34f070a6-a29e-4fd8-8ad9-7218af972fb1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54528212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.54528212
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.3750987663
Short name T871
Test name
Test status
Simulation time 394345242 ps
CPU time 4.94 seconds
Started Mar 19 03:21:55 PM PDT 24
Finished Mar 19 03:22:00 PM PDT 24
Peak memory 209232 kb
Host smart-449b8f40-905e-4518-ae0b-3664732aba1f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3750987663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.3750987663
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.3570837722
Short name T590
Test name
Test status
Simulation time 1377845932 ps
CPU time 2.75 seconds
Started Mar 19 03:21:57 PM PDT 24
Finished Mar 19 03:22:00 PM PDT 24
Peak memory 214832 kb
Host smart-52294a34-5a25-4669-a2a8-26efdfd3891b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3570837722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.3570837722
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.2564928071
Short name T782
Test name
Test status
Simulation time 2497458822 ps
CPU time 6 seconds
Started Mar 19 03:21:55 PM PDT 24
Finished Mar 19 03:22:01 PM PDT 24
Peak memory 208988 kb
Host smart-09145ca7-99f3-413b-85ee-14305314f864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564928071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.2564928071
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.4090315505
Short name T328
Test name
Test status
Simulation time 870841503 ps
CPU time 22.82 seconds
Started Mar 19 03:21:58 PM PDT 24
Finished Mar 19 03:22:21 PM PDT 24
Peak memory 217260 kb
Host smart-87ef9671-a721-4828-aef5-2934ed703893
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4090315505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.4090315505
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.2476220906
Short name T69
Test name
Test status
Simulation time 258989144 ps
CPU time 8.41 seconds
Started Mar 19 03:21:50 PM PDT 24
Finished Mar 19 03:21:59 PM PDT 24
Peak memory 220376 kb
Host smart-6ae38d30-a92a-4bce-b648-bb822b469ead
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2476220906 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.2476220906
Directory /workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.2893911313
Short name T221
Test name
Test status
Simulation time 198809252 ps
CPU time 7.59 seconds
Started Mar 19 03:21:49 PM PDT 24
Finished Mar 19 03:21:56 PM PDT 24
Peak memory 214712 kb
Host smart-d502b1ce-0976-4671-95da-417f3fc8bc38
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893911313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.2893911313
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.295232625
Short name T899
Test name
Test status
Simulation time 27646070 ps
CPU time 1.98 seconds
Started Mar 19 03:22:01 PM PDT 24
Finished Mar 19 03:22:03 PM PDT 24
Peak memory 210272 kb
Host smart-a810bd1d-2e82-4493-bcba-8ce57fbce117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295232625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.295232625
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.2223320208
Short name T431
Test name
Test status
Simulation time 53569014 ps
CPU time 0.81 seconds
Started Mar 19 03:21:58 PM PDT 24
Finished Mar 19 03:21:59 PM PDT 24
Peak memory 206416 kb
Host smart-7d8883d8-dbec-4d43-99d1-b98c077fde13
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2223320208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.2223320208
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.2317096142
Short name T546
Test name
Test status
Simulation time 91884672 ps
CPU time 1.87 seconds
Started Mar 19 03:22:00 PM PDT 24
Finished Mar 19 03:22:02 PM PDT 24
Peak memory 208228 kb
Host smart-3297bf3a-f352-4fbb-8c33-a6717f879142
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2317096142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.2317096142
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.3953338008
Short name T335
Test name
Test status
Simulation time 429886895 ps
CPU time 7.14 seconds
Started Mar 19 03:21:51 PM PDT 24
Finished Mar 19 03:21:58 PM PDT 24
Peak memory 210800 kb
Host smart-9058db1f-23fd-4a91-b111-8345bf356286
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3953338008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.3953338008
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.3476994423
Short name T568
Test name
Test status
Simulation time 117992844 ps
CPU time 4 seconds
Started Mar 19 03:21:55 PM PDT 24
Finished Mar 19 03:21:59 PM PDT 24
Peak memory 220972 kb
Host smart-46af3e23-2459-4b11-843c-3206f114f233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476994423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.3476994423
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.1237964514
Short name T822
Test name
Test status
Simulation time 532661128 ps
CPU time 7.79 seconds
Started Mar 19 03:21:58 PM PDT 24
Finished Mar 19 03:22:06 PM PDT 24
Peak memory 208748 kb
Host smart-0ddeb6b4-17d3-4547-ad15-168ef6537a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237964514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.1237964514
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.3069580285
Short name T340
Test name
Test status
Simulation time 1249793259 ps
CPU time 5.41 seconds
Started Mar 19 03:21:55 PM PDT 24
Finished Mar 19 03:22:01 PM PDT 24
Peak memory 208840 kb
Host smart-95e1fe64-6f24-440d-838a-39f077013a97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3069580285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.3069580285
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.3008619001
Short name T779
Test name
Test status
Simulation time 117121810 ps
CPU time 2.52 seconds
Started Mar 19 03:22:04 PM PDT 24
Finished Mar 19 03:22:07 PM PDT 24
Peak memory 207304 kb
Host smart-046dd444-1021-4c61-8012-e1d7e47c688c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3008619001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.3008619001
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.2560873052
Short name T211
Test name
Test status
Simulation time 263848426 ps
CPU time 4.7 seconds
Started Mar 19 03:22:01 PM PDT 24
Finished Mar 19 03:22:05 PM PDT 24
Peak memory 207348 kb
Host smart-ced4d53d-7497-42f5-805a-0d62dd786c25
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560873052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.2560873052
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.1115877511
Short name T231
Test name
Test status
Simulation time 1935378054 ps
CPU time 6.68 seconds
Started Mar 19 03:21:59 PM PDT 24
Finished Mar 19 03:22:06 PM PDT 24
Peak memory 208308 kb
Host smart-275c4dd9-5e72-4a62-9fe7-39cc5356ad0e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115877511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.1115877511
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.4265589928
Short name T326
Test name
Test status
Simulation time 947466919 ps
CPU time 17.16 seconds
Started Mar 19 03:21:49 PM PDT 24
Finished Mar 19 03:22:06 PM PDT 24
Peak memory 218664 kb
Host smart-7235df19-1e6b-4262-b942-a0e6f279e75c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265589928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.4265589928
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.439770300
Short name T632
Test name
Test status
Simulation time 176638766 ps
CPU time 4.3 seconds
Started Mar 19 03:21:57 PM PDT 24
Finished Mar 19 03:22:01 PM PDT 24
Peak memory 209004 kb
Host smart-22e8c7a9-3537-499b-ab0c-bc4633435e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439770300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.439770300
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.2902261072
Short name T48
Test name
Test status
Simulation time 2879288905 ps
CPU time 57.6 seconds
Started Mar 19 03:21:59 PM PDT 24
Finished Mar 19 03:22:57 PM PDT 24
Peak memory 217468 kb
Host smart-ab6051f8-4bf6-429d-9754-b33f73eab90c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2902261072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.2902261072
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_stress_all_with_rand_reset.3011673749
Short name T199
Test name
Test status
Simulation time 632876435 ps
CPU time 15.41 seconds
Started Mar 19 03:21:59 PM PDT 24
Finished Mar 19 03:22:19 PM PDT 24
Peak memory 223132 kb
Host smart-ecc17084-12b5-4312-81f8-001752d7c2f8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3011673749 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all_with_rand_reset.3011673749
Directory /workspace/16.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.564951043
Short name T708
Test name
Test status
Simulation time 3647065416 ps
CPU time 22.29 seconds
Started Mar 19 03:21:55 PM PDT 24
Finished Mar 19 03:22:17 PM PDT 24
Peak memory 208940 kb
Host smart-4d7a03d0-d9df-4fa5-8fae-346ec5bb3133
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=564951043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.564951043
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.2169362712
Short name T174
Test name
Test status
Simulation time 379097287 ps
CPU time 2.44 seconds
Started Mar 19 03:21:54 PM PDT 24
Finished Mar 19 03:21:56 PM PDT 24
Peak memory 210192 kb
Host smart-f42334a0-e069-489f-8d7a-ca3a5b50be9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169362712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.2169362712
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.3742507765
Short name T507
Test name
Test status
Simulation time 38067841 ps
CPU time 0.85 seconds
Started Mar 19 03:22:06 PM PDT 24
Finished Mar 19 03:22:07 PM PDT 24
Peak memory 206472 kb
Host smart-27f21bd3-3427-46c8-b5c1-b647156a3c03
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742507765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.3742507765
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.2508128153
Short name T630
Test name
Test status
Simulation time 187274238 ps
CPU time 2.36 seconds
Started Mar 19 03:21:57 PM PDT 24
Finished Mar 19 03:21:59 PM PDT 24
Peak memory 208496 kb
Host smart-1df167a4-ea38-43f5-9987-14b2e42cf1c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2508128153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.2508128153
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.1524455670
Short name T591
Test name
Test status
Simulation time 437001904 ps
CPU time 4.62 seconds
Started Mar 19 03:21:53 PM PDT 24
Finished Mar 19 03:21:57 PM PDT 24
Peak memory 209116 kb
Host smart-e211b5a8-1489-46a9-8f07-546cccabde3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1524455670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.1524455670
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.2665772217
Short name T468
Test name
Test status
Simulation time 1047576393 ps
CPU time 4.5 seconds
Started Mar 19 03:21:52 PM PDT 24
Finished Mar 19 03:21:57 PM PDT 24
Peak memory 209112 kb
Host smart-3b1bdc33-9476-4763-8a80-44f0b73eb2f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665772217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.2665772217
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.269020115
Short name T257
Test name
Test status
Simulation time 908734976 ps
CPU time 16.71 seconds
Started Mar 19 03:22:06 PM PDT 24
Finished Mar 19 03:22:23 PM PDT 24
Peak memory 214704 kb
Host smart-9cbdf569-7ba8-4501-95c4-ec742c2aa023
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=269020115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.269020115
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_random.2205227679
Short name T444
Test name
Test status
Simulation time 1418578236 ps
CPU time 43.27 seconds
Started Mar 19 03:21:57 PM PDT 24
Finished Mar 19 03:22:40 PM PDT 24
Peak memory 209956 kb
Host smart-36366921-35cf-4f74-812e-88fe07df2fef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205227679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.2205227679
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.2126914228
Short name T726
Test name
Test status
Simulation time 31624214 ps
CPU time 2.19 seconds
Started Mar 19 03:21:59 PM PDT 24
Finished Mar 19 03:22:02 PM PDT 24
Peak memory 209088 kb
Host smart-01e6a530-2279-40d7-9adc-a74438798b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126914228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.2126914228
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.1721198820
Short name T723
Test name
Test status
Simulation time 510560912 ps
CPU time 6.52 seconds
Started Mar 19 03:21:50 PM PDT 24
Finished Mar 19 03:21:57 PM PDT 24
Peak memory 207204 kb
Host smart-9a61a82a-0e42-4e69-a842-3cce43517d15
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721198820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.1721198820
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.2037163393
Short name T443
Test name
Test status
Simulation time 112754555 ps
CPU time 2.08 seconds
Started Mar 19 03:21:51 PM PDT 24
Finished Mar 19 03:21:53 PM PDT 24
Peak memory 207972 kb
Host smart-05e4e7b0-b733-4772-acf3-e4ed75fec2c0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037163393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.2037163393
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.556615028
Short name T838
Test name
Test status
Simulation time 182920285 ps
CPU time 2.8 seconds
Started Mar 19 03:21:50 PM PDT 24
Finished Mar 19 03:21:53 PM PDT 24
Peak memory 209128 kb
Host smart-36a42b84-a142-45d2-9830-50e57d6b5050
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556615028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.556615028
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.3771626606
Short name T754
Test name
Test status
Simulation time 2992291316 ps
CPU time 27.72 seconds
Started Mar 19 03:21:53 PM PDT 24
Finished Mar 19 03:22:21 PM PDT 24
Peak memory 209380 kb
Host smart-6fd0d233-eaee-44d2-a9cf-355abc7954eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3771626606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.3771626606
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.141562436
Short name T433
Test name
Test status
Simulation time 620067844 ps
CPU time 5.92 seconds
Started Mar 19 03:21:59 PM PDT 24
Finished Mar 19 03:22:05 PM PDT 24
Peak memory 208940 kb
Host smart-c8b3a511-e211-4135-bf68-b4e6c95cc186
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141562436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.141562436
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.3868430788
Short name T817
Test name
Test status
Simulation time 470182848 ps
CPU time 4 seconds
Started Mar 19 03:21:57 PM PDT 24
Finished Mar 19 03:22:01 PM PDT 24
Peak memory 209644 kb
Host smart-745a4b89-07c8-4e92-9a08-197fd0786533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3868430788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.3868430788
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.138985901
Short name T562
Test name
Test status
Simulation time 477442805 ps
CPU time 2.62 seconds
Started Mar 19 03:21:57 PM PDT 24
Finished Mar 19 03:22:00 PM PDT 24
Peak memory 210140 kb
Host smart-5746caee-c540-4d4d-9eab-8f18efa31298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=138985901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.138985901
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.3800286707
Short name T438
Test name
Test status
Simulation time 13457924 ps
CPU time 0.84 seconds
Started Mar 19 03:22:03 PM PDT 24
Finished Mar 19 03:22:04 PM PDT 24
Peak memory 206356 kb
Host smart-1c1042fb-6d7b-4103-a792-0cbe76ea65d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800286707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.3800286707
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.395718051
Short name T287
Test name
Test status
Simulation time 134748535 ps
CPU time 2.88 seconds
Started Mar 19 03:22:00 PM PDT 24
Finished Mar 19 03:22:03 PM PDT 24
Peak memory 214824 kb
Host smart-ab882ccd-0937-4069-bdcb-f9ac1fe030a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=395718051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.395718051
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.334854139
Short name T740
Test name
Test status
Simulation time 40434997 ps
CPU time 2.96 seconds
Started Mar 19 03:22:01 PM PDT 24
Finished Mar 19 03:22:04 PM PDT 24
Peak memory 210124 kb
Host smart-18ee1d5c-1882-4183-ae96-5a8c0a65390c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334854139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.334854139
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.409168061
Short name T360
Test name
Test status
Simulation time 448019130 ps
CPU time 5.82 seconds
Started Mar 19 03:22:02 PM PDT 24
Finished Mar 19 03:22:08 PM PDT 24
Peak memory 209560 kb
Host smart-dd49a050-2bdb-426c-922d-786ddd6f59be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409168061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.409168061
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.1237958007
Short name T296
Test name
Test status
Simulation time 203305278 ps
CPU time 6.31 seconds
Started Mar 19 03:22:04 PM PDT 24
Finished Mar 19 03:22:10 PM PDT 24
Peak memory 211024 kb
Host smart-ee829a56-a60c-4214-aad6-9abcf4d96b7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1237958007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.1237958007
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.3241583779
Short name T487
Test name
Test status
Simulation time 195106397 ps
CPU time 1.95 seconds
Started Mar 19 03:21:55 PM PDT 24
Finished Mar 19 03:21:57 PM PDT 24
Peak memory 207168 kb
Host smart-0411f322-8215-43b1-b0f8-30fbc6cb2fea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3241583779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.3241583779
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_sideload.3872130237
Short name T689
Test name
Test status
Simulation time 99998637 ps
CPU time 4 seconds
Started Mar 19 03:22:06 PM PDT 24
Finished Mar 19 03:22:10 PM PDT 24
Peak memory 208584 kb
Host smart-f3b008a1-2917-402c-b26e-97e4f81ffabf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3872130237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.3872130237
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.1901673565
Short name T570
Test name
Test status
Simulation time 531814784 ps
CPU time 8.03 seconds
Started Mar 19 03:21:52 PM PDT 24
Finished Mar 19 03:22:00 PM PDT 24
Peak memory 208908 kb
Host smart-6268a794-ada2-4db9-aa3e-7452f60027aa
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1901673565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.1901673565
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.864858804
Short name T561
Test name
Test status
Simulation time 124242231 ps
CPU time 3.32 seconds
Started Mar 19 03:21:52 PM PDT 24
Finished Mar 19 03:21:55 PM PDT 24
Peak memory 209036 kb
Host smart-a00713fc-b30a-4f28-9150-f6339109d25d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864858804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.864858804
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.1869442198
Short name T253
Test name
Test status
Simulation time 117254088 ps
CPU time 3.29 seconds
Started Mar 19 03:21:53 PM PDT 24
Finished Mar 19 03:21:56 PM PDT 24
Peak memory 209496 kb
Host smart-16c3d2c8-90f8-4dc2-846d-b5f2aeb245ff
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869442198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.1869442198
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.1045002272
Short name T901
Test name
Test status
Simulation time 184250624 ps
CPU time 2.69 seconds
Started Mar 19 03:22:05 PM PDT 24
Finished Mar 19 03:22:08 PM PDT 24
Peak memory 208628 kb
Host smart-6f38a494-a5cc-4581-916b-4fe340b6d7be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045002272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.1045002272
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.1569230460
Short name T873
Test name
Test status
Simulation time 45713475 ps
CPU time 2.62 seconds
Started Mar 19 03:21:54 PM PDT 24
Finished Mar 19 03:21:56 PM PDT 24
Peak memory 209076 kb
Host smart-3c059641-0e7f-4b19-b186-e3595afd0309
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569230460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.1569230460
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.2882182613
Short name T274
Test name
Test status
Simulation time 3054121968 ps
CPU time 59.09 seconds
Started Mar 19 03:21:59 PM PDT 24
Finished Mar 19 03:22:58 PM PDT 24
Peak memory 217392 kb
Host smart-0da7c141-fb1d-4d59-bb05-056cb263b6dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2882182613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.2882182613
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_stress_all_with_rand_reset.3515124663
Short name T763
Test name
Test status
Simulation time 1509174274 ps
CPU time 18.03 seconds
Started Mar 19 03:22:02 PM PDT 24
Finished Mar 19 03:22:20 PM PDT 24
Peak memory 223128 kb
Host smart-0b5d9aca-12f1-4a7b-b861-bdc37d0f7f3b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3515124663 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all_with_rand_reset.3515124663
Directory /workspace/18.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.1655884977
Short name T386
Test name
Test status
Simulation time 80731847 ps
CPU time 2.81 seconds
Started Mar 19 03:21:56 PM PDT 24
Finished Mar 19 03:21:59 PM PDT 24
Peak memory 208000 kb
Host smart-55bfe13f-e7c4-4f12-b5e6-0f1106512a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1655884977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.1655884977
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.2736398415
Short name T768
Test name
Test status
Simulation time 469736867 ps
CPU time 3.3 seconds
Started Mar 19 03:22:04 PM PDT 24
Finished Mar 19 03:22:07 PM PDT 24
Peak memory 211476 kb
Host smart-187e0f73-1df0-4d94-82b0-95a69f089c34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2736398415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.2736398415
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.2560088853
Short name T583
Test name
Test status
Simulation time 28869120 ps
CPU time 0.83 seconds
Started Mar 19 03:21:59 PM PDT 24
Finished Mar 19 03:22:00 PM PDT 24
Peak memory 206376 kb
Host smart-a3cde901-186e-4412-9a2c-d03883f743c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560088853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.2560088853
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.1080673488
Short name T417
Test name
Test status
Simulation time 1021208206 ps
CPU time 9.87 seconds
Started Mar 19 03:22:03 PM PDT 24
Finished Mar 19 03:22:13 PM PDT 24
Peak memory 215872 kb
Host smart-d7df4cd2-e532-45a5-b145-d754e2709d34
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1080673488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.1080673488
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.576156663
Short name T7
Test name
Test status
Simulation time 434777885 ps
CPU time 5.46 seconds
Started Mar 19 03:22:03 PM PDT 24
Finished Mar 19 03:22:08 PM PDT 24
Peak memory 218940 kb
Host smart-a6d8d7d4-c42c-45b4-bc4d-9427ae6b484a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=576156663 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.576156663
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.2002050227
Short name T786
Test name
Test status
Simulation time 189661063 ps
CPU time 4.86 seconds
Started Mar 19 03:22:04 PM PDT 24
Finished Mar 19 03:22:09 PM PDT 24
Peak memory 210724 kb
Host smart-ba3d669b-0c76-49c6-a2eb-29d0fd90fc3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002050227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.2002050227
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.851811980
Short name T760
Test name
Test status
Simulation time 173289660 ps
CPU time 4.47 seconds
Started Mar 19 03:22:01 PM PDT 24
Finished Mar 19 03:22:06 PM PDT 24
Peak memory 214708 kb
Host smart-c51ddd1c-121c-4ef3-897c-e0a257def998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=851811980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.851811980
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.1506032654
Short name T2
Test name
Test status
Simulation time 100595542 ps
CPU time 3.64 seconds
Started Mar 19 03:22:03 PM PDT 24
Finished Mar 19 03:22:06 PM PDT 24
Peak memory 220844 kb
Host smart-2bd9c2ba-a1a6-4341-9260-ae467768f304
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506032654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.1506032654
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.978833065
Short name T207
Test name
Test status
Simulation time 758698628 ps
CPU time 5.67 seconds
Started Mar 19 03:22:02 PM PDT 24
Finished Mar 19 03:22:08 PM PDT 24
Peak memory 209404 kb
Host smart-958388a5-2da8-4afb-82f0-e3ca63688615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=978833065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.978833065
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.4160180864
Short name T289
Test name
Test status
Simulation time 36676166 ps
CPU time 2.68 seconds
Started Mar 19 03:22:04 PM PDT 24
Finished Mar 19 03:22:06 PM PDT 24
Peak memory 207640 kb
Host smart-e3870b58-5304-459a-8ba6-a2c84913f0f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160180864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.4160180864
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.1651989449
Short name T804
Test name
Test status
Simulation time 1322331090 ps
CPU time 41.39 seconds
Started Mar 19 03:21:59 PM PDT 24
Finished Mar 19 03:22:40 PM PDT 24
Peak memory 208644 kb
Host smart-36a07286-ffc4-43a9-883a-ddaeedc39404
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1651989449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.1651989449
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.3086555543
Short name T454
Test name
Test status
Simulation time 147414590 ps
CPU time 3.14 seconds
Started Mar 19 03:22:14 PM PDT 24
Finished Mar 19 03:22:18 PM PDT 24
Peak memory 209192 kb
Host smart-1c8c4bcd-066f-4ebd-80d0-f00a9903e218
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3086555543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.3086555543
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.4232131206
Short name T563
Test name
Test status
Simulation time 223139789 ps
CPU time 5.12 seconds
Started Mar 19 03:22:00 PM PDT 24
Finished Mar 19 03:22:06 PM PDT 24
Peak memory 208996 kb
Host smart-b913b608-813c-45bf-840f-9bac5ec8a9ab
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232131206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.4232131206
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.2208057707
Short name T905
Test name
Test status
Simulation time 407246303 ps
CPU time 9.8 seconds
Started Mar 19 03:22:00 PM PDT 24
Finished Mar 19 03:22:10 PM PDT 24
Peak memory 218976 kb
Host smart-36ce9511-9aa2-4df9-9d0d-33557657c0fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2208057707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.2208057707
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.3538103168
Short name T442
Test name
Test status
Simulation time 69312515 ps
CPU time 2.86 seconds
Started Mar 19 03:22:03 PM PDT 24
Finished Mar 19 03:22:06 PM PDT 24
Peak memory 207480 kb
Host smart-364c659d-a904-4ad1-9ad7-0f57c6ed4c46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3538103168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.3538103168
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.1514787306
Short name T446
Test name
Test status
Simulation time 3261649169 ps
CPU time 14.83 seconds
Started Mar 19 03:22:04 PM PDT 24
Finished Mar 19 03:22:19 PM PDT 24
Peak memory 209040 kb
Host smart-086885cf-71b1-46b7-897f-c8b5152c8737
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1514787306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.1514787306
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.173858887
Short name T185
Test name
Test status
Simulation time 44341534 ps
CPU time 2.39 seconds
Started Mar 19 03:22:11 PM PDT 24
Finished Mar 19 03:22:14 PM PDT 24
Peak memory 210432 kb
Host smart-588ca71a-1662-467c-80eb-50fce85a622b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173858887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.173858887
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.3921384783
Short name T565
Test name
Test status
Simulation time 9471929 ps
CPU time 0.7 seconds
Started Mar 19 03:21:23 PM PDT 24
Finished Mar 19 03:21:24 PM PDT 24
Peak memory 206424 kb
Host smart-f6a49dc6-f41a-4869-beca-675ef49cf285
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3921384783 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.3921384783
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.1577020647
Short name T67
Test name
Test status
Simulation time 274105179 ps
CPU time 3.57 seconds
Started Mar 19 03:21:10 PM PDT 24
Finished Mar 19 03:21:13 PM PDT 24
Peak memory 207684 kb
Host smart-42d463ac-a1b7-477a-a841-7de5f19109bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577020647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.1577020647
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.3625811100
Short name T374
Test name
Test status
Simulation time 95672961 ps
CPU time 3.59 seconds
Started Mar 19 03:21:10 PM PDT 24
Finished Mar 19 03:21:14 PM PDT 24
Peak memory 223004 kb
Host smart-3fec5e62-d3ea-44e2-8adc-8090f8003f90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625811100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.3625811100
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.26051469
Short name T401
Test name
Test status
Simulation time 94397262 ps
CPU time 4.13 seconds
Started Mar 19 03:21:13 PM PDT 24
Finished Mar 19 03:21:18 PM PDT 24
Peak memory 214756 kb
Host smart-27dcfeca-9574-47cc-b784-180e1fd6c558
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26051469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.26051469
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.2247577398
Short name T696
Test name
Test status
Simulation time 344401281 ps
CPU time 8.62 seconds
Started Mar 19 03:21:09 PM PDT 24
Finished Mar 19 03:21:18 PM PDT 24
Peak memory 218840 kb
Host smart-8932a2f1-5f71-4183-a173-e76d0273f5b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2247577398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.2247577398
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.1735724602
Short name T11
Test name
Test status
Simulation time 1689287761 ps
CPU time 10.44 seconds
Started Mar 19 03:21:11 PM PDT 24
Finished Mar 19 03:21:22 PM PDT 24
Peak memory 238108 kb
Host smart-34da8a27-f88e-4580-9e17-0618973d42d7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1735724602 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.1735724602
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.2551725167
Short name T371
Test name
Test status
Simulation time 740518091 ps
CPU time 5.68 seconds
Started Mar 19 03:21:11 PM PDT 24
Finished Mar 19 03:21:17 PM PDT 24
Peak memory 209024 kb
Host smart-763b9f7e-84aa-4274-b62a-b1df5366982c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551725167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.2551725167
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.2325394478
Short name T517
Test name
Test status
Simulation time 61674126 ps
CPU time 2.34 seconds
Started Mar 19 03:21:10 PM PDT 24
Finished Mar 19 03:21:12 PM PDT 24
Peak memory 207264 kb
Host smart-7daeece3-9127-413f-823b-d86d4332b5b6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325394478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.2325394478
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.4013894818
Short name T656
Test name
Test status
Simulation time 196132730 ps
CPU time 3.49 seconds
Started Mar 19 03:21:08 PM PDT 24
Finished Mar 19 03:21:12 PM PDT 24
Peak memory 207276 kb
Host smart-3d91ba94-7091-4663-9a68-4f36101bb3eb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4013894818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.4013894818
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.1160142035
Short name T81
Test name
Test status
Simulation time 120192761 ps
CPU time 2.41 seconds
Started Mar 19 03:21:10 PM PDT 24
Finished Mar 19 03:21:12 PM PDT 24
Peak memory 209140 kb
Host smart-5c0fd3e1-452b-4455-b467-bd056274e875
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160142035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.1160142035
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.245770595
Short name T228
Test name
Test status
Simulation time 53502502 ps
CPU time 3.02 seconds
Started Mar 19 03:21:23 PM PDT 24
Finished Mar 19 03:21:27 PM PDT 24
Peak memory 218936 kb
Host smart-8fcb2c24-bb1b-4654-9030-97c624650ddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=245770595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.245770595
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.1698403023
Short name T566
Test name
Test status
Simulation time 60558626 ps
CPU time 2.21 seconds
Started Mar 19 03:21:16 PM PDT 24
Finished Mar 19 03:21:18 PM PDT 24
Peak memory 207164 kb
Host smart-479f91c4-94b6-435e-ae78-f3be444fdfc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698403023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.1698403023
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.1462132795
Short name T377
Test name
Test status
Simulation time 1478236224 ps
CPU time 17.64 seconds
Started Mar 19 03:21:12 PM PDT 24
Finished Mar 19 03:21:30 PM PDT 24
Peak memory 216160 kb
Host smart-b4ba54df-5533-4e77-b61f-65da8286a5c4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462132795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.1462132795
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.3237168433
Short name T269
Test name
Test status
Simulation time 54438860 ps
CPU time 3.44 seconds
Started Mar 19 03:21:15 PM PDT 24
Finished Mar 19 03:21:19 PM PDT 24
Peak memory 209856 kb
Host smart-5c48b397-97ba-4867-98e0-0bbba9999a3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237168433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.3237168433
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.2509601838
Short name T824
Test name
Test status
Simulation time 82714699 ps
CPU time 3.11 seconds
Started Mar 19 03:21:07 PM PDT 24
Finished Mar 19 03:21:11 PM PDT 24
Peak memory 210536 kb
Host smart-42b04946-614b-41b0-909b-67b56b895ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2509601838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.2509601838
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.413370891
Short name T892
Test name
Test status
Simulation time 11399387 ps
CPU time 0.83 seconds
Started Mar 19 03:22:04 PM PDT 24
Finished Mar 19 03:22:05 PM PDT 24
Peak memory 206416 kb
Host smart-78320330-4d95-4cff-9c24-3c51f7477023
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=413370891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.413370891
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.4254568639
Short name T418
Test name
Test status
Simulation time 46410577 ps
CPU time 3.3 seconds
Started Mar 19 03:22:02 PM PDT 24
Finished Mar 19 03:22:05 PM PDT 24
Peak memory 215896 kb
Host smart-0ef2050b-8662-4a08-aeb6-6dc680aaca44
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4254568639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.4254568639
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.3753088343
Short name T793
Test name
Test status
Simulation time 786597329 ps
CPU time 5.45 seconds
Started Mar 19 03:22:04 PM PDT 24
Finished Mar 19 03:22:10 PM PDT 24
Peak memory 209024 kb
Host smart-2e3a9f36-70ce-4456-b49f-24a31484f682
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753088343 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.3753088343
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.3847255877
Short name T572
Test name
Test status
Simulation time 405957843 ps
CPU time 10.52 seconds
Started Mar 19 03:22:12 PM PDT 24
Finished Mar 19 03:22:23 PM PDT 24
Peak memory 223000 kb
Host smart-2ad943d8-81cc-4bae-b087-f6020681372c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847255877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.3847255877
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.2169222383
Short name T84
Test name
Test status
Simulation time 427598120 ps
CPU time 2.97 seconds
Started Mar 19 03:22:09 PM PDT 24
Finished Mar 19 03:22:12 PM PDT 24
Peak memory 208752 kb
Host smart-b4635942-a0fc-480a-bccb-ae4b61e5b5eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169222383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.2169222383
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.1687225341
Short name T500
Test name
Test status
Simulation time 173691870 ps
CPU time 2.91 seconds
Started Mar 19 03:22:06 PM PDT 24
Finished Mar 19 03:22:10 PM PDT 24
Peak memory 210144 kb
Host smart-ac557089-a377-493e-a301-b1227b04daf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687225341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.1687225341
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.894197715
Short name T799
Test name
Test status
Simulation time 142702636 ps
CPU time 5.79 seconds
Started Mar 19 03:22:01 PM PDT 24
Finished Mar 19 03:22:07 PM PDT 24
Peak memory 209084 kb
Host smart-243b841c-348e-40bc-988e-bc4e3ddd8904
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894197715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.894197715
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.3470599
Short name T78
Test name
Test status
Simulation time 3997041017 ps
CPU time 39.86 seconds
Started Mar 19 03:22:04 PM PDT 24
Finished Mar 19 03:22:44 PM PDT 24
Peak memory 209180 kb
Host smart-541d573c-6e1b-48c9-9c8b-d34757bf0bd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.3470599
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.3283192090
Short name T319
Test name
Test status
Simulation time 230377519 ps
CPU time 3.17 seconds
Started Mar 19 03:22:02 PM PDT 24
Finished Mar 19 03:22:05 PM PDT 24
Peak memory 209092 kb
Host smart-7d95893e-de95-4b02-a4f3-8857180870c3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3283192090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.3283192090
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.1021869197
Short name T138
Test name
Test status
Simulation time 2107136016 ps
CPU time 53.91 seconds
Started Mar 19 03:22:03 PM PDT 24
Finished Mar 19 03:22:57 PM PDT 24
Peak memory 208644 kb
Host smart-28f187f0-097f-4150-a99d-0b97180a5fe6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021869197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.1021869197
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.418617871
Short name T803
Test name
Test status
Simulation time 76612291 ps
CPU time 3.8 seconds
Started Mar 19 03:22:03 PM PDT 24
Finished Mar 19 03:22:07 PM PDT 24
Peak memory 209280 kb
Host smart-7a65e037-6949-4eab-9c36-df45338b7200
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=418617871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.418617871
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.3481573153
Short name T885
Test name
Test status
Simulation time 31157637 ps
CPU time 2.31 seconds
Started Mar 19 03:22:03 PM PDT 24
Finished Mar 19 03:22:05 PM PDT 24
Peak memory 214788 kb
Host smart-0e514f1a-6ffe-42df-8fda-aec5552b3b7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481573153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.3481573153
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.2859685599
Short name T459
Test name
Test status
Simulation time 382169001 ps
CPU time 3.07 seconds
Started Mar 19 03:21:59 PM PDT 24
Finished Mar 19 03:22:02 PM PDT 24
Peak memory 207612 kb
Host smart-1e792bd4-c0bf-43de-b12d-02b0c42c8d9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2859685599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.2859685599
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.3020943566
Short name T329
Test name
Test status
Simulation time 2674525572 ps
CPU time 64.98 seconds
Started Mar 19 03:22:03 PM PDT 24
Finished Mar 19 03:23:08 PM PDT 24
Peak memory 217204 kb
Host smart-1308799d-7c37-42a6-aeb4-851ed2629a9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3020943566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.3020943566
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.4002005046
Short name T268
Test name
Test status
Simulation time 4092380158 ps
CPU time 55.01 seconds
Started Mar 19 03:22:06 PM PDT 24
Finished Mar 19 03:23:01 PM PDT 24
Peak memory 209792 kb
Host smart-172ed417-52b3-49f7-a82b-52d0cbe0c294
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4002005046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.4002005046
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.2190411004
Short name T101
Test name
Test status
Simulation time 130406202 ps
CPU time 2.08 seconds
Started Mar 19 03:22:04 PM PDT 24
Finished Mar 19 03:22:06 PM PDT 24
Peak memory 210572 kb
Host smart-afe04add-b022-4f59-8770-e2734e5d1c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190411004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.2190411004
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.3346341084
Short name T428
Test name
Test status
Simulation time 14750327 ps
CPU time 0.74 seconds
Started Mar 19 03:22:15 PM PDT 24
Finished Mar 19 03:22:16 PM PDT 24
Peak memory 206472 kb
Host smart-1d37417b-bfd3-460e-a0b4-73eced72db93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3346341084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.3346341084
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.2562492869
Short name T398
Test name
Test status
Simulation time 179718094 ps
CPU time 3.76 seconds
Started Mar 19 03:22:04 PM PDT 24
Finished Mar 19 03:22:08 PM PDT 24
Peak memory 215816 kb
Host smart-6af60a93-93da-4b56-add0-89064c010597
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2562492869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.2562492869
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.2906180698
Short name T893
Test name
Test status
Simulation time 213764735 ps
CPU time 2.07 seconds
Started Mar 19 03:22:01 PM PDT 24
Finished Mar 19 03:22:03 PM PDT 24
Peak memory 214856 kb
Host smart-2040b5ed-9edc-4a98-8c8a-06df2c767f1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2906180698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.2906180698
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.2340514809
Short name T800
Test name
Test status
Simulation time 97974742 ps
CPU time 4.67 seconds
Started Mar 19 03:22:03 PM PDT 24
Finished Mar 19 03:22:08 PM PDT 24
Peak memory 209116 kb
Host smart-dc4d5e9f-5108-404a-a2df-e93a405637df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2340514809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.2340514809
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.2772508141
Short name T90
Test name
Test status
Simulation time 504249422 ps
CPU time 6.56 seconds
Started Mar 19 03:22:09 PM PDT 24
Finished Mar 19 03:22:16 PM PDT 24
Peak memory 214808 kb
Host smart-cea932be-e3ce-4dab-b199-2ec0fc3f5f8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2772508141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.2772508141
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.2988896061
Short name T657
Test name
Test status
Simulation time 82998547 ps
CPU time 4.49 seconds
Started Mar 19 03:22:06 PM PDT 24
Finished Mar 19 03:22:11 PM PDT 24
Peak memory 222920 kb
Host smart-1c2ec92f-c371-4087-9935-b0830f2fc487
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2988896061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.2988896061
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.644922181
Short name T792
Test name
Test status
Simulation time 202995219 ps
CPU time 5.32 seconds
Started Mar 19 03:22:00 PM PDT 24
Finished Mar 19 03:22:05 PM PDT 24
Peak memory 220420 kb
Host smart-74029c9f-b2e0-43f1-8ce2-2390818c4746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644922181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.644922181
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.2089462640
Short name T381
Test name
Test status
Simulation time 120266846 ps
CPU time 3.35 seconds
Started Mar 19 03:22:06 PM PDT 24
Finished Mar 19 03:22:09 PM PDT 24
Peak memory 208636 kb
Host smart-6252810e-1694-4f1e-b6b5-8d0b0156d2d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089462640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.2089462640
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.3355412151
Short name T693
Test name
Test status
Simulation time 36839471 ps
CPU time 2.1 seconds
Started Mar 19 03:22:04 PM PDT 24
Finished Mar 19 03:22:06 PM PDT 24
Peak memory 208984 kb
Host smart-cedc8f1c-7950-42f9-9de5-04ccfbf4061c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3355412151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.3355412151
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.1131004818
Short name T735
Test name
Test status
Simulation time 36668094 ps
CPU time 2.44 seconds
Started Mar 19 03:22:04 PM PDT 24
Finished Mar 19 03:22:07 PM PDT 24
Peak memory 209060 kb
Host smart-4c71eb83-b51e-46ea-9508-cbc7dae3f13c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1131004818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.1131004818
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.3256265905
Short name T539
Test name
Test status
Simulation time 2252843059 ps
CPU time 7.79 seconds
Started Mar 19 03:22:10 PM PDT 24
Finished Mar 19 03:22:18 PM PDT 24
Peak memory 207420 kb
Host smart-6cee7a7b-9159-4322-9db8-d22a8bead76e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3256265905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.3256265905
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.2733992279
Short name T83
Test name
Test status
Simulation time 207835693 ps
CPU time 5.64 seconds
Started Mar 19 03:22:04 PM PDT 24
Finished Mar 19 03:22:10 PM PDT 24
Peak memory 209512 kb
Host smart-76ee6b20-0422-4e12-870c-d08935347268
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2733992279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.2733992279
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.2105346124
Short name T330
Test name
Test status
Simulation time 521730166 ps
CPU time 4.71 seconds
Started Mar 19 03:22:05 PM PDT 24
Finished Mar 19 03:22:10 PM PDT 24
Peak memory 210372 kb
Host smart-ba160abc-b158-4a3a-976b-67006af3ced6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105346124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.2105346124
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.1531040431
Short name T716
Test name
Test status
Simulation time 38280905 ps
CPU time 2.41 seconds
Started Mar 19 03:22:09 PM PDT 24
Finished Mar 19 03:22:12 PM PDT 24
Peak memory 208776 kb
Host smart-150fbc69-7d25-4fea-ba78-3eadaa6f4d94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1531040431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.1531040431
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.3531140832
Short name T312
Test name
Test status
Simulation time 696832992 ps
CPU time 10.38 seconds
Started Mar 19 03:22:18 PM PDT 24
Finished Mar 19 03:22:28 PM PDT 24
Peak memory 219044 kb
Host smart-dcc2311e-a095-4dc0-93f8-d92fb28db967
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3531140832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.3531140832
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.833135523
Short name T463
Test name
Test status
Simulation time 3194029257 ps
CPU time 7.75 seconds
Started Mar 19 03:22:04 PM PDT 24
Finished Mar 19 03:22:12 PM PDT 24
Peak memory 214864 kb
Host smart-e9d547a5-5bf8-46d4-b119-1d24657a1445
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=833135523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.833135523
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.2702067100
Short name T214
Test name
Test status
Simulation time 304188928 ps
CPU time 3.31 seconds
Started Mar 19 03:22:11 PM PDT 24
Finished Mar 19 03:22:15 PM PDT 24
Peak memory 210424 kb
Host smart-538eefc8-b765-422c-90c0-33c7f9b9c4be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2702067100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.2702067100
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.17621790
Short name T608
Test name
Test status
Simulation time 30199540 ps
CPU time 0.79 seconds
Started Mar 19 03:22:17 PM PDT 24
Finished Mar 19 03:22:18 PM PDT 24
Peak memory 206420 kb
Host smart-a5730edc-6999-4378-83b1-55e759462e51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17621790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.17621790
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.267587320
Short name T310
Test name
Test status
Simulation time 548701496 ps
CPU time 9.03 seconds
Started Mar 19 03:22:20 PM PDT 24
Finished Mar 19 03:22:29 PM PDT 24
Peak memory 215420 kb
Host smart-a0527b07-c3b1-4384-bc41-30616434c456
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=267587320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.267587320
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.3849893313
Short name T865
Test name
Test status
Simulation time 894346015 ps
CPU time 3.72 seconds
Started Mar 19 03:22:13 PM PDT 24
Finished Mar 19 03:22:17 PM PDT 24
Peak memory 214748 kb
Host smart-f0e037d3-f38a-40c1-a5a8-7878e4ef64a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3849893313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.3849893313
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.1001667558
Short name T339
Test name
Test status
Simulation time 124901785 ps
CPU time 4.55 seconds
Started Mar 19 03:22:14 PM PDT 24
Finished Mar 19 03:22:19 PM PDT 24
Peak memory 220884 kb
Host smart-f5b7d75f-f62e-4ee8-a597-7c2334f724a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1001667558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.1001667558
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.110400894
Short name T846
Test name
Test status
Simulation time 2223875701 ps
CPU time 9.53 seconds
Started Mar 19 03:22:29 PM PDT 24
Finished Mar 19 03:22:39 PM PDT 24
Peak memory 215148 kb
Host smart-d777dd4a-fa92-4afb-9a43-10a654e7759a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110400894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.110400894
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.2786491906
Short name T610
Test name
Test status
Simulation time 406498498 ps
CPU time 5.51 seconds
Started Mar 19 03:22:21 PM PDT 24
Finished Mar 19 03:22:26 PM PDT 24
Peak memory 215920 kb
Host smart-38a6bc5d-51ce-4c7f-8e79-e971967555bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786491906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.2786491906
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.1966000665
Short name T891
Test name
Test status
Simulation time 145471170 ps
CPU time 6.37 seconds
Started Mar 19 03:22:17 PM PDT 24
Finished Mar 19 03:22:24 PM PDT 24
Peak memory 218764 kb
Host smart-6237babf-6055-4c7a-85d0-0eb5bd25ed74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966000665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.1966000665
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.1240026361
Short name T281
Test name
Test status
Simulation time 179599334 ps
CPU time 2.6 seconds
Started Mar 19 03:22:22 PM PDT 24
Finished Mar 19 03:22:25 PM PDT 24
Peak memory 209020 kb
Host smart-60d28601-d96e-470c-b14f-5dbc1bab7fa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240026361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.1240026361
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.807684696
Short name T887
Test name
Test status
Simulation time 425371200 ps
CPU time 6.47 seconds
Started Mar 19 03:22:31 PM PDT 24
Finished Mar 19 03:22:37 PM PDT 24
Peak memory 208464 kb
Host smart-0fb2dc54-cf37-4b69-a779-4b5c6662143f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807684696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.807684696
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.2964447224
Short name T575
Test name
Test status
Simulation time 95740769 ps
CPU time 4.15 seconds
Started Mar 19 03:22:15 PM PDT 24
Finished Mar 19 03:22:20 PM PDT 24
Peak memory 208964 kb
Host smart-3ae350dc-17ab-443a-9fd8-a432c7913827
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964447224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.2964447224
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.3374936508
Short name T864
Test name
Test status
Simulation time 555740901 ps
CPU time 5.87 seconds
Started Mar 19 03:22:20 PM PDT 24
Finished Mar 19 03:22:26 PM PDT 24
Peak memory 208760 kb
Host smart-3c68bf89-e2d1-4a92-a6cf-37b31f50b1bc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3374936508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.3374936508
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.2814466545
Short name T567
Test name
Test status
Simulation time 2786856994 ps
CPU time 29.24 seconds
Started Mar 19 03:22:15 PM PDT 24
Finished Mar 19 03:22:45 PM PDT 24
Peak memory 218784 kb
Host smart-9f1316ab-1af1-426b-b00d-3d558ec35374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2814466545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.2814466545
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.2653845926
Short name T12
Test name
Test status
Simulation time 718912831 ps
CPU time 8.02 seconds
Started Mar 19 03:22:20 PM PDT 24
Finished Mar 19 03:22:28 PM PDT 24
Peak memory 209104 kb
Host smart-208f4541-4071-40fa-837e-02435ba41df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2653845926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.2653845926
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.2398166618
Short name T238
Test name
Test status
Simulation time 38215879488 ps
CPU time 573.91 seconds
Started Mar 19 03:22:16 PM PDT 24
Finished Mar 19 03:31:50 PM PDT 24
Peak memory 223080 kb
Host smart-ef8b6067-652b-4931-9e92-7103ba8e128c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2398166618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.2398166618
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.1935753545
Short name T384
Test name
Test status
Simulation time 461288923 ps
CPU time 5.97 seconds
Started Mar 19 03:22:19 PM PDT 24
Finished Mar 19 03:22:25 PM PDT 24
Peak memory 207896 kb
Host smart-1fa86077-41c1-4c20-b319-b15c3bb4f6a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935753545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.1935753545
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.3165188496
Short name T863
Test name
Test status
Simulation time 66811769 ps
CPU time 2.26 seconds
Started Mar 19 03:22:21 PM PDT 24
Finished Mar 19 03:22:24 PM PDT 24
Peak memory 210472 kb
Host smart-7e0fb9fd-ef62-4ec1-930c-b228831a9fec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3165188496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.3165188496
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.343112019
Short name T709
Test name
Test status
Simulation time 51950897 ps
CPU time 0.93 seconds
Started Mar 19 03:22:22 PM PDT 24
Finished Mar 19 03:22:23 PM PDT 24
Peak memory 206564 kb
Host smart-185e35a8-cc27-4a97-af1c-541b4bb1c2aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343112019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.343112019
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.1762085503
Short name T666
Test name
Test status
Simulation time 9453163829 ps
CPU time 46.2 seconds
Started Mar 19 03:22:20 PM PDT 24
Finished Mar 19 03:23:07 PM PDT 24
Peak memory 223016 kb
Host smart-6a928437-1139-4884-93dc-a82284958e3e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1762085503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.1762085503
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.4153651450
Short name T617
Test name
Test status
Simulation time 50020935 ps
CPU time 1.93 seconds
Started Mar 19 03:22:28 PM PDT 24
Finished Mar 19 03:22:30 PM PDT 24
Peak memory 208332 kb
Host smart-2b37b733-2ec3-453d-b9ff-9df89829cb8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4153651450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.4153651450
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.2181983963
Short name T788
Test name
Test status
Simulation time 509584363 ps
CPU time 6 seconds
Started Mar 19 03:22:15 PM PDT 24
Finished Mar 19 03:22:22 PM PDT 24
Peak memory 219832 kb
Host smart-c5dca1fd-6eda-4c96-a803-80befe0760d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2181983963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.2181983963
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.3025373186
Short name T796
Test name
Test status
Simulation time 177592403 ps
CPU time 2.94 seconds
Started Mar 19 03:22:19 PM PDT 24
Finished Mar 19 03:22:22 PM PDT 24
Peak memory 209540 kb
Host smart-4d8f0ad3-3301-4266-8bb3-d562e32cdcf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025373186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.3025373186
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_sideload.454977409
Short name T327
Test name
Test status
Simulation time 797804504 ps
CPU time 6.16 seconds
Started Mar 19 03:22:17 PM PDT 24
Finished Mar 19 03:22:23 PM PDT 24
Peak memory 208872 kb
Host smart-d3dea9a9-64aa-4a58-bec5-4ccdb120c56d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=454977409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.454977409
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.1817394501
Short name T365
Test name
Test status
Simulation time 577697668 ps
CPU time 20.12 seconds
Started Mar 19 03:22:14 PM PDT 24
Finished Mar 19 03:22:35 PM PDT 24
Peak memory 207396 kb
Host smart-830cb62c-14d9-49bc-bd2b-ed86b9d4296d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817394501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.1817394501
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.3269778712
Short name T110
Test name
Test status
Simulation time 33940475 ps
CPU time 2.38 seconds
Started Mar 19 03:22:17 PM PDT 24
Finished Mar 19 03:22:19 PM PDT 24
Peak memory 207324 kb
Host smart-488bc725-ed76-47e1-93aa-15f0775b8143
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3269778712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.3269778712
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.3563763730
Short name T732
Test name
Test status
Simulation time 156240500 ps
CPU time 4.56 seconds
Started Mar 19 03:22:16 PM PDT 24
Finished Mar 19 03:22:21 PM PDT 24
Peak memory 208268 kb
Host smart-66957e88-a0f5-4c2b-a7e6-9ea7957b9862
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563763730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.3563763730
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.409377840
Short name T655
Test name
Test status
Simulation time 2315259938 ps
CPU time 16.12 seconds
Started Mar 19 03:22:15 PM PDT 24
Finished Mar 19 03:22:32 PM PDT 24
Peak memory 214840 kb
Host smart-a5465276-0821-46cd-ac0d-be8eef3ddb11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=409377840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.409377840
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.934230469
Short name T640
Test name
Test status
Simulation time 47205418 ps
CPU time 2.42 seconds
Started Mar 19 03:22:30 PM PDT 24
Finished Mar 19 03:22:32 PM PDT 24
Peak memory 208684 kb
Host smart-12cf75c8-7017-4633-930c-8aceef6b2425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934230469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.934230469
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.51835795
Short name T280
Test name
Test status
Simulation time 1337757076 ps
CPU time 34.9 seconds
Started Mar 19 03:22:43 PM PDT 24
Finished Mar 19 03:23:18 PM PDT 24
Peak memory 223040 kb
Host smart-084a6cbe-ce77-4c92-bdeb-84ffd2aed95a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51835795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.51835795
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_stress_all_with_rand_reset.331826681
Short name T884
Test name
Test status
Simulation time 2447128746 ps
CPU time 29.59 seconds
Started Mar 19 03:22:11 PM PDT 24
Finished Mar 19 03:22:41 PM PDT 24
Peak memory 223596 kb
Host smart-d19a7587-e75a-4654-993b-9f1f4c200743
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=331826681 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all_with_rand_reset.331826681
Directory /workspace/23.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.4292330721
Short name T602
Test name
Test status
Simulation time 130236949 ps
CPU time 3.94 seconds
Started Mar 19 03:22:13 PM PDT 24
Finished Mar 19 03:22:17 PM PDT 24
Peak memory 208628 kb
Host smart-7fac177b-10a8-4586-ba6e-c8b09ce4d6d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292330721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.4292330721
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.985013231
Short name T823
Test name
Test status
Simulation time 75271983 ps
CPU time 1.58 seconds
Started Mar 19 03:22:19 PM PDT 24
Finished Mar 19 03:22:21 PM PDT 24
Peak memory 210332 kb
Host smart-410a9100-c871-4b05-969c-55fb70b5786d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=985013231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.985013231
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.135416777
Short name T456
Test name
Test status
Simulation time 10392814 ps
CPU time 0.73 seconds
Started Mar 19 03:22:19 PM PDT 24
Finished Mar 19 03:22:20 PM PDT 24
Peak memory 206456 kb
Host smart-e384e481-7cec-402f-81fc-95e4923f555f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=135416777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.135416777
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.1793838023
Short name T423
Test name
Test status
Simulation time 115623930 ps
CPU time 4.26 seconds
Started Mar 19 03:22:16 PM PDT 24
Finished Mar 19 03:22:21 PM PDT 24
Peak memory 214876 kb
Host smart-89f5cb1e-d72c-4a3a-935a-03ddaf314180
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1793838023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.1793838023
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.1959721231
Short name T31
Test name
Test status
Simulation time 190517986 ps
CPU time 2.63 seconds
Started Mar 19 03:22:19 PM PDT 24
Finished Mar 19 03:22:22 PM PDT 24
Peak memory 208564 kb
Host smart-1408126a-bbb5-4f71-8300-e2d2bc503e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1959721231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.1959721231
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.3403883466
Short name T830
Test name
Test status
Simulation time 44292831 ps
CPU time 1.65 seconds
Started Mar 19 03:22:21 PM PDT 24
Finished Mar 19 03:22:23 PM PDT 24
Peak memory 208412 kb
Host smart-f6a09ce0-f91d-40d9-9dec-ec44e9c7d43b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403883466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.3403883466
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.2840722561
Short name T94
Test name
Test status
Simulation time 142202084 ps
CPU time 3.68 seconds
Started Mar 19 03:22:26 PM PDT 24
Finished Mar 19 03:22:30 PM PDT 24
Peak memory 214812 kb
Host smart-34710423-b97b-40a2-aa5a-9e566dc807f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2840722561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.2840722561
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.2553988533
Short name T316
Test name
Test status
Simulation time 1342147697 ps
CPU time 11.21 seconds
Started Mar 19 03:22:21 PM PDT 24
Finished Mar 19 03:22:32 PM PDT 24
Peak memory 211068 kb
Host smart-c4b53a76-e124-47e4-a8cf-0d8735b4c05f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553988533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.2553988533
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.3634099562
Short name T801
Test name
Test status
Simulation time 165801539 ps
CPU time 4.54 seconds
Started Mar 19 03:22:16 PM PDT 24
Finished Mar 19 03:22:20 PM PDT 24
Peak memory 210060 kb
Host smart-7ae4db8b-eee5-4a9e-aa01-e866e71fd64c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3634099562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.3634099562
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.805913095
Short name T497
Test name
Test status
Simulation time 2242442603 ps
CPU time 74.75 seconds
Started Mar 19 03:22:13 PM PDT 24
Finished Mar 19 03:23:33 PM PDT 24
Peak memory 209576 kb
Host smart-5982e35f-d738-4779-93bf-dba2ceaaafea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805913095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.805913095
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.2725675993
Short name T789
Test name
Test status
Simulation time 576203915 ps
CPU time 3.46 seconds
Started Mar 19 03:22:15 PM PDT 24
Finished Mar 19 03:22:19 PM PDT 24
Peak memory 208712 kb
Host smart-9f423583-e95d-41b9-a747-bef33a86d17c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725675993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.2725675993
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.754471671
Short name T484
Test name
Test status
Simulation time 3391656532 ps
CPU time 7.85 seconds
Started Mar 19 03:22:16 PM PDT 24
Finished Mar 19 03:22:24 PM PDT 24
Peak memory 207568 kb
Host smart-8d87e9cf-d7d2-413d-b11f-be69659e5434
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=754471671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.754471671
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.3811982499
Short name T624
Test name
Test status
Simulation time 1063125789 ps
CPU time 11.32 seconds
Started Mar 19 03:22:18 PM PDT 24
Finished Mar 19 03:22:29 PM PDT 24
Peak memory 208444 kb
Host smart-8a2f8895-8fd8-423d-814a-aca1ea3560a6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3811982499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.3811982499
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.3723642297
Short name T87
Test name
Test status
Simulation time 344460882 ps
CPU time 3.11 seconds
Started Mar 19 03:22:17 PM PDT 24
Finished Mar 19 03:22:20 PM PDT 24
Peak memory 207156 kb
Host smart-75ae7411-d873-48d6-9c2e-86e50a9d5709
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3723642297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.3723642297
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.3049345276
Short name T881
Test name
Test status
Simulation time 261749546 ps
CPU time 4.06 seconds
Started Mar 19 03:22:22 PM PDT 24
Finished Mar 19 03:22:27 PM PDT 24
Peak memory 209696 kb
Host smart-8ca510df-82bd-4aa7-87ad-f0229b2c4080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3049345276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.3049345276
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.3364038513
Short name T440
Test name
Test status
Simulation time 193204387 ps
CPU time 5.06 seconds
Started Mar 19 03:22:17 PM PDT 24
Finished Mar 19 03:22:22 PM PDT 24
Peak memory 207020 kb
Host smart-9aa3a5e5-e2c6-447e-8671-53824a7b65d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364038513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.3364038513
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.3985903810
Short name T284
Test name
Test status
Simulation time 1329942192 ps
CPU time 8.58 seconds
Started Mar 19 03:22:15 PM PDT 24
Finished Mar 19 03:22:24 PM PDT 24
Peak memory 210316 kb
Host smart-d2c2b40d-7618-4084-87fe-74178d9887e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3985903810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.3985903810
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.24105469
Short name T116
Test name
Test status
Simulation time 130799831 ps
CPU time 1.88 seconds
Started Mar 19 03:22:26 PM PDT 24
Finished Mar 19 03:22:28 PM PDT 24
Peak memory 210140 kb
Host smart-7cde47e4-85c5-42d1-9aba-e5afccad7124
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24105469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.24105469
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.3087308610
Short name T145
Test name
Test status
Simulation time 22467902 ps
CPU time 0.88 seconds
Started Mar 19 03:22:35 PM PDT 24
Finished Mar 19 03:22:36 PM PDT 24
Peak memory 206356 kb
Host smart-c844947f-3dd6-4e26-bc26-58f8507fb0e2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087308610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.3087308610
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.259528312
Short name T424
Test name
Test status
Simulation time 94181082 ps
CPU time 3.75 seconds
Started Mar 19 03:22:27 PM PDT 24
Finished Mar 19 03:22:31 PM PDT 24
Peak memory 214740 kb
Host smart-7be3527f-cdad-408c-8e59-db7b0d13886d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=259528312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.259528312
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.4148884671
Short name T35
Test name
Test status
Simulation time 48707847 ps
CPU time 3.14 seconds
Started Mar 19 03:22:18 PM PDT 24
Finished Mar 19 03:22:22 PM PDT 24
Peak memory 221948 kb
Host smart-b0425f70-580a-49c2-a116-7cc516e4b95a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148884671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.4148884671
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.2036784053
Short name T886
Test name
Test status
Simulation time 45901222 ps
CPU time 1.98 seconds
Started Mar 19 03:22:20 PM PDT 24
Finished Mar 19 03:22:22 PM PDT 24
Peak memory 208680 kb
Host smart-95536a82-f7e4-47db-87f9-d89454fb0d09
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2036784053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.2036784053
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.2885625600
Short name T703
Test name
Test status
Simulation time 493466207 ps
CPU time 7.18 seconds
Started Mar 19 03:22:28 PM PDT 24
Finished Mar 19 03:22:35 PM PDT 24
Peak memory 219692 kb
Host smart-56d7bf2a-e8f7-4217-9bc1-5a9330df67dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2885625600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.2885625600
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.1273157664
Short name T771
Test name
Test status
Simulation time 46738643 ps
CPU time 2.46 seconds
Started Mar 19 03:22:18 PM PDT 24
Finished Mar 19 03:22:21 PM PDT 24
Peak memory 216136 kb
Host smart-96c75890-bedf-46f2-afab-db8f3009a31b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273157664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.1273157664
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.3339908002
Short name T755
Test name
Test status
Simulation time 416527264 ps
CPU time 4.76 seconds
Started Mar 19 03:22:15 PM PDT 24
Finished Mar 19 03:22:20 PM PDT 24
Peak memory 214824 kb
Host smart-2807e578-7a16-4da2-a5c9-0c005db474c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339908002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.3339908002
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.2778878677
Short name T460
Test name
Test status
Simulation time 124737603 ps
CPU time 4.76 seconds
Started Mar 19 03:22:20 PM PDT 24
Finished Mar 19 03:22:25 PM PDT 24
Peak memory 207096 kb
Host smart-cf9024c8-4adf-4827-a2e8-bb1796c81249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778878677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.2778878677
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.951471201
Short name T902
Test name
Test status
Simulation time 88910660 ps
CPU time 2.03 seconds
Started Mar 19 03:22:22 PM PDT 24
Finished Mar 19 03:22:24 PM PDT 24
Peak memory 209432 kb
Host smart-1b873f17-708d-4f15-a62c-d0781e12353d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=951471201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.951471201
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.2575282504
Short name T346
Test name
Test status
Simulation time 174839978 ps
CPU time 4.93 seconds
Started Mar 19 03:22:23 PM PDT 24
Finished Mar 19 03:22:28 PM PDT 24
Peak memory 209540 kb
Host smart-cad60a7e-a1df-4e61-b7ff-ff593c4624eb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2575282504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.2575282504
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.2308907736
Short name T842
Test name
Test status
Simulation time 449215121 ps
CPU time 3.79 seconds
Started Mar 19 03:22:17 PM PDT 24
Finished Mar 19 03:22:21 PM PDT 24
Peak memory 209212 kb
Host smart-66e4a98c-40a4-47d2-8bbf-8e9d899766eb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2308907736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.2308907736
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.448740836
Short name T636
Test name
Test status
Simulation time 91603513 ps
CPU time 4 seconds
Started Mar 19 03:22:38 PM PDT 24
Finished Mar 19 03:22:42 PM PDT 24
Peak memory 210120 kb
Host smart-b1110491-c455-4269-94a1-e1bd21a685e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448740836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.448740836
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.4210853256
Short name T430
Test name
Test status
Simulation time 615910501 ps
CPU time 2.48 seconds
Started Mar 19 03:22:22 PM PDT 24
Finished Mar 19 03:22:25 PM PDT 24
Peak memory 207156 kb
Host smart-343534ad-5f2e-4c9c-a6c7-38ef2920e470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210853256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.4210853256
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.1231870659
Short name T262
Test name
Test status
Simulation time 4361744825 ps
CPU time 25.25 seconds
Started Mar 19 03:22:31 PM PDT 24
Finished Mar 19 03:22:56 PM PDT 24
Peak memory 216936 kb
Host smart-d15d9bc8-b694-455c-8bf8-1e2099d691bd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1231870659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.1231870659
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.1598768492
Short name T856
Test name
Test status
Simulation time 119903821 ps
CPU time 5.22 seconds
Started Mar 19 03:22:19 PM PDT 24
Finished Mar 19 03:22:24 PM PDT 24
Peak memory 210828 kb
Host smart-c4bee1f6-9370-45c9-b30d-dd433a1895e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598768492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.1598768492
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.2642218646
Short name T588
Test name
Test status
Simulation time 153515143 ps
CPU time 2.31 seconds
Started Mar 19 03:22:27 PM PDT 24
Finished Mar 19 03:22:29 PM PDT 24
Peak memory 210784 kb
Host smart-b1a13783-0631-48ff-a99f-f3480b48864f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642218646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.2642218646
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.794414207
Short name T674
Test name
Test status
Simulation time 62837305 ps
CPU time 0.77 seconds
Started Mar 19 03:22:43 PM PDT 24
Finished Mar 19 03:22:44 PM PDT 24
Peak memory 206424 kb
Host smart-624c3bef-b72d-40f7-b12d-278e11b8a816
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=794414207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.794414207
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.320259066
Short name T407
Test name
Test status
Simulation time 210763342 ps
CPU time 4.28 seconds
Started Mar 19 03:22:44 PM PDT 24
Finished Mar 19 03:22:48 PM PDT 24
Peak memory 214824 kb
Host smart-3781a643-9992-4773-ac96-568cb43cc2fc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=320259066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.320259066
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.1482478583
Short name T813
Test name
Test status
Simulation time 17459657 ps
CPU time 1.56 seconds
Started Mar 19 03:22:42 PM PDT 24
Finished Mar 19 03:22:44 PM PDT 24
Peak memory 210488 kb
Host smart-7c618d81-fcf2-4582-ac07-ee5151c1418f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1482478583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.1482478583
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.3237849931
Short name T900
Test name
Test status
Simulation time 89785001 ps
CPU time 3.53 seconds
Started Mar 19 03:22:39 PM PDT 24
Finished Mar 19 03:22:43 PM PDT 24
Peak memory 220840 kb
Host smart-8a832f4b-f05c-46f1-9236-09166c92c189
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237849931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.3237849931
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.111146246
Short name T255
Test name
Test status
Simulation time 95091296 ps
CPU time 3.77 seconds
Started Mar 19 03:22:29 PM PDT 24
Finished Mar 19 03:22:39 PM PDT 24
Peak memory 214644 kb
Host smart-53c7d699-5c85-4d1a-b4df-25116d5d52e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=111146246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.111146246
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.2305984206
Short name T44
Test name
Test status
Simulation time 784488097 ps
CPU time 2.99 seconds
Started Mar 19 03:22:25 PM PDT 24
Finished Mar 19 03:22:29 PM PDT 24
Peak memory 220720 kb
Host smart-29b10dfd-0fa0-43c5-b5d4-141e66195a2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2305984206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.2305984206
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.4072880123
Short name T794
Test name
Test status
Simulation time 34671996 ps
CPU time 2.43 seconds
Started Mar 19 03:22:34 PM PDT 24
Finished Mar 19 03:22:36 PM PDT 24
Peak memory 208304 kb
Host smart-1dcc4f54-4f2d-4979-b76a-648aa71e037a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4072880123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.4072880123
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.1463654709
Short name T626
Test name
Test status
Simulation time 400745713 ps
CPU time 1.97 seconds
Started Mar 19 03:22:27 PM PDT 24
Finished Mar 19 03:22:29 PM PDT 24
Peak memory 207588 kb
Host smart-55a9bd0f-d89b-45ff-9d89-6d8d6bd9e030
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463654709 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.1463654709
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.428005809
Short name T106
Test name
Test status
Simulation time 204625128 ps
CPU time 3.18 seconds
Started Mar 19 03:22:46 PM PDT 24
Finished Mar 19 03:22:50 PM PDT 24
Peak memory 207220 kb
Host smart-c1878bbb-501b-4ef6-80c3-36b53891328f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=428005809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.428005809
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.3623400881
Short name T642
Test name
Test status
Simulation time 304885305 ps
CPU time 3.4 seconds
Started Mar 19 03:22:26 PM PDT 24
Finished Mar 19 03:22:30 PM PDT 24
Peak memory 209000 kb
Host smart-629483b0-08ec-47d5-adec-797877248026
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3623400881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.3623400881
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.3818169744
Short name T766
Test name
Test status
Simulation time 41841915 ps
CPU time 1.76 seconds
Started Mar 19 03:22:44 PM PDT 24
Finished Mar 19 03:22:46 PM PDT 24
Peak memory 207312 kb
Host smart-ff830b4c-7537-4912-8481-9f95113ca00a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3818169744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.3818169744
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.3522848101
Short name T325
Test name
Test status
Simulation time 779376670 ps
CPU time 23.64 seconds
Started Mar 19 03:22:26 PM PDT 24
Finished Mar 19 03:22:49 PM PDT 24
Peak memory 214804 kb
Host smart-83e15937-1656-4171-94f1-aaa02a3910d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3522848101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.3522848101
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.2488011552
Short name T403
Test name
Test status
Simulation time 103997481 ps
CPU time 2.8 seconds
Started Mar 19 03:22:29 PM PDT 24
Finished Mar 19 03:22:32 PM PDT 24
Peak memory 207164 kb
Host smart-0ff0c2b8-1a27-4cd3-a759-b5dc39fbbc6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2488011552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.2488011552
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all_with_rand_reset.3644144362
Short name T733
Test name
Test status
Simulation time 133589071 ps
CPU time 9.23 seconds
Started Mar 19 03:22:28 PM PDT 24
Finished Mar 19 03:22:43 PM PDT 24
Peak memory 223068 kb
Host smart-d70c7bc1-6dfc-463f-9c81-586ef5db78d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3644144362 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all_with_rand_reset.3644144362
Directory /workspace/26.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.1660757697
Short name T216
Test name
Test status
Simulation time 201123854 ps
CPU time 6.69 seconds
Started Mar 19 03:22:22 PM PDT 24
Finished Mar 19 03:22:29 PM PDT 24
Peak memory 209092 kb
Host smart-d99a3897-127f-4f01-bd6c-ea8aa06745ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660757697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.1660757697
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.3371366682
Short name T166
Test name
Test status
Simulation time 410320109 ps
CPU time 2.23 seconds
Started Mar 19 03:22:30 PM PDT 24
Finished Mar 19 03:22:33 PM PDT 24
Peak memory 210576 kb
Host smart-82a22567-6eaf-4a31-bfa4-a6c18aa72f91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3371366682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.3371366682
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.3841352048
Short name T98
Test name
Test status
Simulation time 9699882 ps
CPU time 0.82 seconds
Started Mar 19 03:22:28 PM PDT 24
Finished Mar 19 03:22:29 PM PDT 24
Peak memory 206464 kb
Host smart-1ff2c2b4-50f5-4b33-8806-ad34278831e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3841352048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.3841352048
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.174871984
Short name T241
Test name
Test status
Simulation time 120773291 ps
CPU time 4.32 seconds
Started Mar 19 03:22:35 PM PDT 24
Finished Mar 19 03:22:40 PM PDT 24
Peak memory 210380 kb
Host smart-98313e3c-161e-4d54-9949-f8febc372eee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=174871984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.174871984
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.2764975576
Short name T76
Test name
Test status
Simulation time 83990389 ps
CPU time 2.66 seconds
Started Mar 19 03:22:33 PM PDT 24
Finished Mar 19 03:22:36 PM PDT 24
Peak memory 209776 kb
Host smart-97f3ca33-8d1f-45c6-b702-bc97dc36f98a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764975576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.2764975576
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.4188666111
Short name T358
Test name
Test status
Simulation time 63981596 ps
CPU time 3.9 seconds
Started Mar 19 03:22:37 PM PDT 24
Finished Mar 19 03:22:42 PM PDT 24
Peak memory 222916 kb
Host smart-f15e1e94-90bc-4369-86af-a8bd4ddf06e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188666111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.4188666111
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.3642938055
Short name T299
Test name
Test status
Simulation time 2623135305 ps
CPU time 70.2 seconds
Started Mar 19 03:22:24 PM PDT 24
Finished Mar 19 03:23:34 PM PDT 24
Peak memory 227472 kb
Host smart-146c17f1-080c-449b-88a0-d82d5680cfa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642938055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.3642938055
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.1876999827
Short name T62
Test name
Test status
Simulation time 80725415 ps
CPU time 3.66 seconds
Started Mar 19 03:22:31 PM PDT 24
Finished Mar 19 03:22:35 PM PDT 24
Peak memory 209516 kb
Host smart-2e37f30d-8a31-4891-a62a-99256052d0da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1876999827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.1876999827
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.2421330628
Short name T904
Test name
Test status
Simulation time 239341609 ps
CPU time 6.18 seconds
Started Mar 19 03:22:33 PM PDT 24
Finished Mar 19 03:22:40 PM PDT 24
Peak memory 210116 kb
Host smart-66a6451f-7ceb-419f-82bf-5fb3efb4d378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421330628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.2421330628
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.1954184363
Short name T301
Test name
Test status
Simulation time 385300870 ps
CPU time 8.42 seconds
Started Mar 19 03:22:24 PM PDT 24
Finished Mar 19 03:22:33 PM PDT 24
Peak memory 209304 kb
Host smart-105ab0f1-0868-4043-b67b-c9bf2e0cb11b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954184363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.1954184363
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.1734862402
Short name T877
Test name
Test status
Simulation time 350413014 ps
CPU time 9.01 seconds
Started Mar 19 03:22:34 PM PDT 24
Finished Mar 19 03:22:44 PM PDT 24
Peak memory 208408 kb
Host smart-c92019c8-0e7f-47aa-b5cf-1a378c218ba6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1734862402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.1734862402
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.4292835485
Short name T342
Test name
Test status
Simulation time 64868297 ps
CPU time 3.2 seconds
Started Mar 19 03:22:28 PM PDT 24
Finished Mar 19 03:22:32 PM PDT 24
Peak memory 207868 kb
Host smart-0e589e78-01c5-4c1f-bc3e-4e3333ffb928
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4292835485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.4292835485
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.2106029114
Short name T504
Test name
Test status
Simulation time 48405533 ps
CPU time 2.9 seconds
Started Mar 19 03:22:39 PM PDT 24
Finished Mar 19 03:22:42 PM PDT 24
Peak memory 207324 kb
Host smart-db6f6f34-e2b6-45ad-98c4-7a0ac22ee52c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2106029114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.2106029114
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.231618457
Short name T547
Test name
Test status
Simulation time 149616626 ps
CPU time 2.6 seconds
Started Mar 19 03:22:25 PM PDT 24
Finished Mar 19 03:22:27 PM PDT 24
Peak memory 210012 kb
Host smart-d5444a6f-9748-4ede-8d44-256579b7322c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231618457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.231618457
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.2394546884
Short name T671
Test name
Test status
Simulation time 210847568 ps
CPU time 6.75 seconds
Started Mar 19 03:22:25 PM PDT 24
Finished Mar 19 03:22:32 PM PDT 24
Peak memory 208936 kb
Host smart-ced8ecc3-fd91-4a01-a771-db22f1d40f4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2394546884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.2394546884
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.2432155231
Short name T359
Test name
Test status
Simulation time 2283407872 ps
CPU time 24.02 seconds
Started Mar 19 03:22:33 PM PDT 24
Finished Mar 19 03:22:57 PM PDT 24
Peak memory 215992 kb
Host smart-6f50ec2b-55f5-48f9-98c6-3227e84aceeb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432155231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.2432155231
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.2495785098
Short name T529
Test name
Test status
Simulation time 781535544 ps
CPU time 8.56 seconds
Started Mar 19 03:22:28 PM PDT 24
Finished Mar 19 03:22:37 PM PDT 24
Peak memory 218844 kb
Host smart-1a3f9527-12e2-422e-b220-0e053e06456f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2495785098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.2495785098
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.1745024764
Short name T215
Test name
Test status
Simulation time 105171903 ps
CPU time 1.6 seconds
Started Mar 19 03:22:34 PM PDT 24
Finished Mar 19 03:22:37 PM PDT 24
Peak memory 210540 kb
Host smart-41c19142-7e18-4c62-bfe2-e024b796ee74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745024764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.1745024764
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.1442445886
Short name T668
Test name
Test status
Simulation time 96688088 ps
CPU time 0.76 seconds
Started Mar 19 03:22:33 PM PDT 24
Finished Mar 19 03:22:33 PM PDT 24
Peak memory 206424 kb
Host smart-69037fc2-1496-419e-ade5-01a71e313565
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1442445886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.1442445886
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.2722415858
Short name T140
Test name
Test status
Simulation time 28993078 ps
CPU time 2.51 seconds
Started Mar 19 03:22:25 PM PDT 24
Finished Mar 19 03:22:28 PM PDT 24
Peak memory 214792 kb
Host smart-0104f155-df05-49d2-9443-bfca7bacae23
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2722415858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.2722415858
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.713449993
Short name T618
Test name
Test status
Simulation time 129772114 ps
CPU time 2.57 seconds
Started Mar 19 03:22:25 PM PDT 24
Finished Mar 19 03:22:27 PM PDT 24
Peak memory 218184 kb
Host smart-15e38f73-6be7-4b6c-92c1-710eab93261d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=713449993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.713449993
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.2507016785
Short name T72
Test name
Test status
Simulation time 163616957 ps
CPU time 2.83 seconds
Started Mar 19 03:22:28 PM PDT 24
Finished Mar 19 03:22:31 PM PDT 24
Peak memory 207448 kb
Host smart-a4666738-ff25-40af-b436-146ef5ad8205
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2507016785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.2507016785
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.2620933128
Short name T777
Test name
Test status
Simulation time 241607215 ps
CPU time 4.77 seconds
Started Mar 19 03:22:24 PM PDT 24
Finished Mar 19 03:22:29 PM PDT 24
Peak memory 210744 kb
Host smart-7da639f9-ba1c-4e6a-bd3f-a352443688de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2620933128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.2620933128
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.1511894470
Short name T554
Test name
Test status
Simulation time 58989356 ps
CPU time 3.14 seconds
Started Mar 19 03:22:25 PM PDT 24
Finished Mar 19 03:22:28 PM PDT 24
Peak memory 209788 kb
Host smart-6ee6163d-8a79-4ec4-9888-fd70adc3d386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511894470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.1511894470
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.4022256491
Short name T252
Test name
Test status
Simulation time 374624343 ps
CPU time 4.45 seconds
Started Mar 19 03:22:28 PM PDT 24
Finished Mar 19 03:22:33 PM PDT 24
Peak memory 210348 kb
Host smart-716736bf-3bea-4eed-a94f-c18c49908c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4022256491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.4022256491
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.3090237620
Short name T876
Test name
Test status
Simulation time 76407086 ps
CPU time 3.19 seconds
Started Mar 19 03:22:33 PM PDT 24
Finished Mar 19 03:22:37 PM PDT 24
Peak memory 208940 kb
Host smart-33ceaece-04ff-4f3f-8f6a-13bb020feef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090237620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.3090237620
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.3945923509
Short name T691
Test name
Test status
Simulation time 3479939281 ps
CPU time 23.41 seconds
Started Mar 19 03:22:26 PM PDT 24
Finished Mar 19 03:22:49 PM PDT 24
Peak memory 209572 kb
Host smart-4938b705-ff08-41e8-b000-bb4e609636ee
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3945923509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.3945923509
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.3692108152
Short name T870
Test name
Test status
Simulation time 240225219 ps
CPU time 8.85 seconds
Started Mar 19 03:22:22 PM PDT 24
Finished Mar 19 03:22:31 PM PDT 24
Peak memory 209124 kb
Host smart-1fe271dc-1b05-45d4-a9d9-1ac54f82a7ee
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3692108152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.3692108152
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.3358328857
Short name T501
Test name
Test status
Simulation time 122298756 ps
CPU time 3.92 seconds
Started Mar 19 03:22:30 PM PDT 24
Finished Mar 19 03:22:34 PM PDT 24
Peak memory 209108 kb
Host smart-39125e29-c698-4a2b-8fa5-6f340118740f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358328857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.3358328857
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.1115218628
Short name T222
Test name
Test status
Simulation time 310672659 ps
CPU time 3.25 seconds
Started Mar 19 03:22:30 PM PDT 24
Finished Mar 19 03:22:33 PM PDT 24
Peak memory 209464 kb
Host smart-faff4ad4-61d0-4c78-b797-fc32154b34e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115218628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.1115218628
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.1692643380
Short name T536
Test name
Test status
Simulation time 324962376 ps
CPU time 3.82 seconds
Started Mar 19 03:22:46 PM PDT 24
Finished Mar 19 03:22:50 PM PDT 24
Peak memory 209112 kb
Host smart-cd5495a5-16de-4f7a-921a-9368b22338f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692643380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.1692643380
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.2334161906
Short name T595
Test name
Test status
Simulation time 1201120021 ps
CPU time 12.73 seconds
Started Mar 19 03:22:25 PM PDT 24
Finished Mar 19 03:22:37 PM PDT 24
Peak memory 215212 kb
Host smart-254c76b6-164f-4555-bfb1-b89716b80eaa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334161906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.2334161906
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.1241409125
Short name T472
Test name
Test status
Simulation time 283649082 ps
CPU time 8.22 seconds
Started Mar 19 03:22:37 PM PDT 24
Finished Mar 19 03:22:46 PM PDT 24
Peak memory 209992 kb
Host smart-d5f2fb5f-4841-401d-b427-83c6e55f89fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241409125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.1241409125
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.639237315
Short name T57
Test name
Test status
Simulation time 148408572 ps
CPU time 4.67 seconds
Started Mar 19 03:22:25 PM PDT 24
Finished Mar 19 03:22:29 PM PDT 24
Peak memory 210936 kb
Host smart-0580f773-b74e-4b3a-bcbe-743813265253
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=639237315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.639237315
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.2190999083
Short name T637
Test name
Test status
Simulation time 29093151 ps
CPU time 0.7 seconds
Started Mar 19 03:22:34 PM PDT 24
Finished Mar 19 03:22:36 PM PDT 24
Peak memory 206480 kb
Host smart-0f8d2c9b-c918-4f36-8f28-2eafb68313ba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2190999083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.2190999083
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.2416950948
Short name T413
Test name
Test status
Simulation time 564029682 ps
CPU time 7.16 seconds
Started Mar 19 03:22:34 PM PDT 24
Finished Mar 19 03:22:41 PM PDT 24
Peak memory 214756 kb
Host smart-7cb2d25c-bd4e-4287-a6e2-89599889d526
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2416950948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.2416950948
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.1627012302
Short name T643
Test name
Test status
Simulation time 126991795 ps
CPU time 5.4 seconds
Started Mar 19 03:22:34 PM PDT 24
Finished Mar 19 03:22:39 PM PDT 24
Peak memory 220452 kb
Host smart-54817c31-6877-4557-ad92-6721380d1185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627012302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.1627012302
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.1966192366
Short name T526
Test name
Test status
Simulation time 209227182 ps
CPU time 2.74 seconds
Started Mar 19 03:22:29 PM PDT 24
Finished Mar 19 03:22:33 PM PDT 24
Peak memory 214800 kb
Host smart-2816cd93-d189-4023-8cfe-6fd6beb5d410
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966192366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.1966192366
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.468524508
Short name T89
Test name
Test status
Simulation time 3641813443 ps
CPU time 43.78 seconds
Started Mar 19 03:22:29 PM PDT 24
Finished Mar 19 03:23:13 PM PDT 24
Peak memory 223080 kb
Host smart-58e8f917-38d3-48c3-a6e3-4bb2816cbb58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=468524508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.468524508
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.2169769994
Short name T400
Test name
Test status
Simulation time 3678472126 ps
CPU time 25.77 seconds
Started Mar 19 03:22:50 PM PDT 24
Finished Mar 19 03:23:16 PM PDT 24
Peak memory 214884 kb
Host smart-62fc34b6-1aa3-4482-ae5f-9f25a6fadd4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2169769994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.2169769994
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.1159126971
Short name T635
Test name
Test status
Simulation time 143539997 ps
CPU time 3.9 seconds
Started Mar 19 03:22:43 PM PDT 24
Finished Mar 19 03:22:47 PM PDT 24
Peak memory 214760 kb
Host smart-f9d0fcd1-cfa7-418a-a24c-97ac7a86463f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1159126971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.1159126971
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.3107633824
Short name T475
Test name
Test status
Simulation time 177133757 ps
CPU time 7.23 seconds
Started Mar 19 03:22:33 PM PDT 24
Finished Mar 19 03:22:41 PM PDT 24
Peak memory 218768 kb
Host smart-e40e3c2c-2d1e-45b9-a5e6-7c057199f991
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3107633824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.3107633824
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.34856188
Short name T499
Test name
Test status
Simulation time 72141435 ps
CPU time 3.46 seconds
Started Mar 19 03:22:26 PM PDT 24
Finished Mar 19 03:22:30 PM PDT 24
Peak memory 209064 kb
Host smart-aa95beda-4c7e-4914-90e8-cecddf8a662a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34856188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.34856188
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.3067205764
Short name T615
Test name
Test status
Simulation time 87606992 ps
CPU time 3.01 seconds
Started Mar 19 03:22:28 PM PDT 24
Finished Mar 19 03:22:32 PM PDT 24
Peak memory 207348 kb
Host smart-cc5d75be-363f-42d4-991b-6b15ea163655
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067205764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.3067205764
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.3169180958
Short name T227
Test name
Test status
Simulation time 58282153 ps
CPU time 3.1 seconds
Started Mar 19 03:22:28 PM PDT 24
Finished Mar 19 03:22:32 PM PDT 24
Peak memory 208984 kb
Host smart-6b53a6e6-2a38-4b60-a1b5-10defada1aac
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3169180958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.3169180958
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.1023272452
Short name T447
Test name
Test status
Simulation time 290818353 ps
CPU time 4.97 seconds
Started Mar 19 03:22:28 PM PDT 24
Finished Mar 19 03:22:34 PM PDT 24
Peak memory 209220 kb
Host smart-dc405618-3a27-46f6-a122-66a8ab61719a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023272452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.1023272452
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.2897057441
Short name T578
Test name
Test status
Simulation time 407726546 ps
CPU time 3.65 seconds
Started Mar 19 03:22:46 PM PDT 24
Finished Mar 19 03:22:51 PM PDT 24
Peak memory 214784 kb
Host smart-bfba4a62-f2cf-429e-841f-7063cd14b8e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897057441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.2897057441
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.1995224307
Short name T776
Test name
Test status
Simulation time 988215876 ps
CPU time 5.06 seconds
Started Mar 19 03:22:35 PM PDT 24
Finished Mar 19 03:22:41 PM PDT 24
Peak memory 208932 kb
Host smart-3aba7a8e-e3d2-4e1c-9218-0891a8a451f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995224307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.1995224307
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.2391412776
Short name T286
Test name
Test status
Simulation time 3471042536 ps
CPU time 75.05 seconds
Started Mar 19 03:22:34 PM PDT 24
Finished Mar 19 03:23:50 PM PDT 24
Peak memory 217236 kb
Host smart-fbb713bc-3ac7-4155-b9fc-b6381ba8229a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2391412776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.2391412776
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.859498728
Short name T148
Test name
Test status
Simulation time 730495052 ps
CPU time 6.08 seconds
Started Mar 19 03:22:44 PM PDT 24
Finished Mar 19 03:22:50 PM PDT 24
Peak memory 209016 kb
Host smart-7cf8f43e-6a85-4565-a884-8aad167ca599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=859498728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.859498728
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.2776505881
Short name T775
Test name
Test status
Simulation time 79201394 ps
CPU time 3.38 seconds
Started Mar 19 03:22:47 PM PDT 24
Finished Mar 19 03:22:51 PM PDT 24
Peak memory 210588 kb
Host smart-d0267495-11b2-48a3-994d-ffcb42bcba0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776505881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.2776505881
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.1528261540
Short name T862
Test name
Test status
Simulation time 27140372 ps
CPU time 0.81 seconds
Started Mar 19 03:21:23 PM PDT 24
Finished Mar 19 03:21:23 PM PDT 24
Peak memory 206384 kb
Host smart-3d2a6ba8-db8a-4d6a-94a9-88d5e66773f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528261540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.1528261540
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.3871460010
Short name T853
Test name
Test status
Simulation time 140050698 ps
CPU time 6.26 seconds
Started Mar 19 03:21:18 PM PDT 24
Finished Mar 19 03:21:24 PM PDT 24
Peak memory 221212 kb
Host smart-60868532-4579-431c-aeb5-45e06925c916
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3871460010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.3871460010
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.2428793843
Short name T520
Test name
Test status
Simulation time 39333110 ps
CPU time 1.83 seconds
Started Mar 19 03:21:21 PM PDT 24
Finished Mar 19 03:21:23 PM PDT 24
Peak memory 208644 kb
Host smart-d7b74190-0fc3-427f-8348-9b386fb084d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2428793843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.2428793843
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.3261717054
Short name T652
Test name
Test status
Simulation time 52093237 ps
CPU time 3.65 seconds
Started Mar 19 03:21:19 PM PDT 24
Finished Mar 19 03:21:23 PM PDT 24
Peak memory 214816 kb
Host smart-ebaa3056-e39b-412b-a11b-0ea3990dae2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261717054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.3261717054
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.927741139
Short name T672
Test name
Test status
Simulation time 163358360 ps
CPU time 4.58 seconds
Started Mar 19 03:21:20 PM PDT 24
Finished Mar 19 03:21:25 PM PDT 24
Peak memory 214736 kb
Host smart-8fa82ebc-a989-493e-b0e3-345104a7da5b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927741139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.927741139
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.958890345
Short name T564
Test name
Test status
Simulation time 179706959 ps
CPU time 2.28 seconds
Started Mar 19 03:21:21 PM PDT 24
Finished Mar 19 03:21:24 PM PDT 24
Peak memory 208052 kb
Host smart-97371e36-e59a-49f4-a081-03835134bb2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958890345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.958890345
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.2608250608
Short name T264
Test name
Test status
Simulation time 519164896 ps
CPU time 4.64 seconds
Started Mar 19 03:21:22 PM PDT 24
Finished Mar 19 03:21:27 PM PDT 24
Peak memory 210836 kb
Host smart-46fc71ea-98f5-4f81-ad42-1ee67cddfee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608250608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.2608250608
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.81832946
Short name T5
Test name
Test status
Simulation time 18251102079 ps
CPU time 21.89 seconds
Started Mar 19 03:21:21 PM PDT 24
Finished Mar 19 03:21:43 PM PDT 24
Peak memory 242952 kb
Host smart-f07535a6-1639-4a52-b079-d6b07dd72b99
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81832946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.81832946
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sideload.4148869177
Short name T808
Test name
Test status
Simulation time 148204177 ps
CPU time 4.26 seconds
Started Mar 19 03:21:22 PM PDT 24
Finished Mar 19 03:21:26 PM PDT 24
Peak memory 208592 kb
Host smart-23e93f99-9d6c-4856-9a61-5b13a7011563
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148869177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.4148869177
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.1772210237
Short name T432
Test name
Test status
Simulation time 25290307 ps
CPU time 1.93 seconds
Started Mar 19 03:21:20 PM PDT 24
Finished Mar 19 03:21:22 PM PDT 24
Peak memory 207272 kb
Host smart-c7cf25ea-110a-4c12-839e-9acba171f57c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1772210237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.1772210237
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.2847921332
Short name T574
Test name
Test status
Simulation time 2500948934 ps
CPU time 26.33 seconds
Started Mar 19 03:21:29 PM PDT 24
Finished Mar 19 03:21:56 PM PDT 24
Peak memory 209648 kb
Host smart-1d357c4c-a89a-45ae-8c10-bfb50219e497
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2847921332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.2847921332
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.2091397283
Short name T521
Test name
Test status
Simulation time 416348407 ps
CPU time 6.91 seconds
Started Mar 19 03:21:24 PM PDT 24
Finished Mar 19 03:21:31 PM PDT 24
Peak memory 208308 kb
Host smart-c0b28e8b-f152-4af4-a990-8f56c706bcea
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2091397283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.2091397283
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.3601194612
Short name T488
Test name
Test status
Simulation time 136398875 ps
CPU time 1.65 seconds
Started Mar 19 03:21:17 PM PDT 24
Finished Mar 19 03:21:19 PM PDT 24
Peak memory 208588 kb
Host smart-2a4ee0af-ca83-49cd-94cb-63f81acb9749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3601194612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.3601194612
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.878684358
Short name T834
Test name
Test status
Simulation time 850810561 ps
CPU time 6.32 seconds
Started Mar 19 03:21:21 PM PDT 24
Finished Mar 19 03:21:27 PM PDT 24
Peak memory 208972 kb
Host smart-58c80c2c-2994-4449-9772-32dae94cf615
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878684358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.878684358
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all_with_rand_reset.5988433
Short name T131
Test name
Test status
Simulation time 248774858 ps
CPU time 15.1 seconds
Started Mar 19 03:21:23 PM PDT 24
Finished Mar 19 03:21:39 PM PDT 24
Peak memory 223132 kb
Host smart-fb5f5024-0977-4837-a6bb-d6290a0bdc56
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=5988433 -assert nopostpr
oc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defau
lt.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all_with_rand_reset.5988433
Directory /workspace/3.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.2476157988
Short name T717
Test name
Test status
Simulation time 253337749 ps
CPU time 3.14 seconds
Started Mar 19 03:21:24 PM PDT 24
Finished Mar 19 03:21:28 PM PDT 24
Peak memory 208916 kb
Host smart-b1a5b1cc-0228-48aa-8139-b9763741f989
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476157988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.2476157988
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.3483209708
Short name T469
Test name
Test status
Simulation time 33325092 ps
CPU time 0.82 seconds
Started Mar 19 03:22:45 PM PDT 24
Finished Mar 19 03:22:46 PM PDT 24
Peak memory 206452 kb
Host smart-864eb373-c6b9-4ec0-a6df-9e3dec361f2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3483209708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.3483209708
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.1137650415
Short name T426
Test name
Test status
Simulation time 137285881 ps
CPU time 2.39 seconds
Started Mar 19 03:22:41 PM PDT 24
Finished Mar 19 03:22:44 PM PDT 24
Peak memory 214836 kb
Host smart-aeba015b-e516-4f04-823a-efb9a6556c66
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1137650415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.1137650415
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.2725529295
Short name T820
Test name
Test status
Simulation time 398052796 ps
CPU time 13.98 seconds
Started Mar 19 03:22:43 PM PDT 24
Finished Mar 19 03:22:57 PM PDT 24
Peak memory 210748 kb
Host smart-5abb20c0-ac60-4368-8205-a223d78c529a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725529295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.2725529295
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.3234537791
Short name T589
Test name
Test status
Simulation time 335519981 ps
CPU time 5.94 seconds
Started Mar 19 03:22:53 PM PDT 24
Finished Mar 19 03:22:59 PM PDT 24
Peak memory 210256 kb
Host smart-ab90d43c-d9e3-4686-8ee9-cb9483012c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3234537791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.3234537791
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.2976223829
Short name T828
Test name
Test status
Simulation time 855292626 ps
CPU time 9.86 seconds
Started Mar 19 03:22:47 PM PDT 24
Finished Mar 19 03:22:58 PM PDT 24
Peak memory 218864 kb
Host smart-6d771eb7-4d94-45ea-a7bd-3f288395280d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976223829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.2976223829
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.3263471079
Short name T621
Test name
Test status
Simulation time 358317562 ps
CPU time 3.72 seconds
Started Mar 19 03:22:45 PM PDT 24
Finished Mar 19 03:22:49 PM PDT 24
Peak memory 208760 kb
Host smart-115099b3-434f-4058-967e-b11a3fe09970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263471079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.3263471079
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.3214143913
Short name T524
Test name
Test status
Simulation time 507658095 ps
CPU time 5.31 seconds
Started Mar 19 03:22:29 PM PDT 24
Finished Mar 19 03:22:34 PM PDT 24
Peak memory 207248 kb
Host smart-1c7c7c0b-b078-4668-9ce5-cb6e154d3dc7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3214143913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.3214143913
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.2598533639
Short name T436
Test name
Test status
Simulation time 2021740274 ps
CPU time 37.08 seconds
Started Mar 19 03:22:29 PM PDT 24
Finished Mar 19 03:23:07 PM PDT 24
Peak memory 208372 kb
Host smart-21269a01-4a2e-4e2c-bb67-7b3fa9572dcc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2598533639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.2598533639
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.1092282698
Short name T251
Test name
Test status
Simulation time 1349177781 ps
CPU time 8.53 seconds
Started Mar 19 03:22:46 PM PDT 24
Finished Mar 19 03:22:56 PM PDT 24
Peak memory 208192 kb
Host smart-71267235-26d4-4a6a-8a1f-043a337e9421
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092282698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.1092282698
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.1652138607
Short name T331
Test name
Test status
Simulation time 609261536 ps
CPU time 4.02 seconds
Started Mar 19 03:22:40 PM PDT 24
Finished Mar 19 03:22:45 PM PDT 24
Peak memory 208556 kb
Host smart-e7c64cb2-6c5e-47f9-b959-75da233e8eba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652138607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.1652138607
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.556663056
Short name T219
Test name
Test status
Simulation time 127636326 ps
CPU time 2.43 seconds
Started Mar 19 03:22:46 PM PDT 24
Finished Mar 19 03:22:50 PM PDT 24
Peak memory 206656 kb
Host smart-ddc0592b-d723-4fe4-8da5-7e83037982d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556663056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.556663056
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.451869804
Short name T372
Test name
Test status
Simulation time 1290368453 ps
CPU time 31.85 seconds
Started Mar 19 03:22:27 PM PDT 24
Finished Mar 19 03:22:59 PM PDT 24
Peak memory 223008 kb
Host smart-756844a1-232f-49e8-b54a-5a156ccf2b6a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=451869804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.451869804
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.2601951892
Short name T450
Test name
Test status
Simulation time 666612624 ps
CPU time 6.14 seconds
Started Mar 19 03:22:44 PM PDT 24
Finished Mar 19 03:22:50 PM PDT 24
Peak memory 210648 kb
Host smart-ab86a968-f186-4a75-9721-5ff5dddd8749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601951892 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.2601951892
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.4079544637
Short name T906
Test name
Test status
Simulation time 265080548 ps
CPU time 7.04 seconds
Started Mar 19 03:22:40 PM PDT 24
Finished Mar 19 03:22:47 PM PDT 24
Peak memory 210992 kb
Host smart-1f88fb5a-59f9-4142-bf9c-8c4d8160b0ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4079544637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.4079544637
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.3481164435
Short name T142
Test name
Test status
Simulation time 13805987 ps
CPU time 0.8 seconds
Started Mar 19 03:22:30 PM PDT 24
Finished Mar 19 03:22:31 PM PDT 24
Peak memory 206444 kb
Host smart-ca61280e-d789-4ae1-aad0-9a314fcb68e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481164435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.3481164435
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.2150124495
Short name T248
Test name
Test status
Simulation time 287968151 ps
CPU time 15.81 seconds
Started Mar 19 03:22:36 PM PDT 24
Finished Mar 19 03:22:53 PM PDT 24
Peak memory 215384 kb
Host smart-516cfbc0-2662-4aa3-8292-cced21df6a57
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2150124495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.2150124495
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.2153769628
Short name T33
Test name
Test status
Simulation time 108344122 ps
CPU time 4.44 seconds
Started Mar 19 03:22:35 PM PDT 24
Finished Mar 19 03:22:40 PM PDT 24
Peak memory 223344 kb
Host smart-e035e14e-0360-4340-b7ad-46f829cbe80b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2153769628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.2153769628
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.4128031673
Short name T619
Test name
Test status
Simulation time 261117450 ps
CPU time 2.52 seconds
Started Mar 19 03:22:30 PM PDT 24
Finished Mar 19 03:22:32 PM PDT 24
Peak memory 208352 kb
Host smart-4fdbdcd8-d392-42ee-8996-04babce5e706
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128031673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.4128031673
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.3257872303
Short name T356
Test name
Test status
Simulation time 116631867 ps
CPU time 4.84 seconds
Started Mar 19 03:22:38 PM PDT 24
Finished Mar 19 03:22:44 PM PDT 24
Peak memory 220560 kb
Host smart-d7a886ae-2911-4fbd-9898-33dcd9fa8059
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3257872303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.3257872303
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.106500708
Short name T580
Test name
Test status
Simulation time 3345838042 ps
CPU time 31.08 seconds
Started Mar 19 03:22:33 PM PDT 24
Finished Mar 19 03:23:05 PM PDT 24
Peak memory 214852 kb
Host smart-d7360bc5-3ffd-4c74-9b97-991e6e87f02a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106500708 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.106500708
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.813130883
Short name T664
Test name
Test status
Simulation time 25271551 ps
CPU time 2.16 seconds
Started Mar 19 03:22:47 PM PDT 24
Finished Mar 19 03:22:50 PM PDT 24
Peak memory 214816 kb
Host smart-6dcbfdd1-513b-4646-93e2-49c66f79b52a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813130883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.813130883
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.3713489858
Short name T291
Test name
Test status
Simulation time 713645300 ps
CPU time 3.44 seconds
Started Mar 19 03:22:34 PM PDT 24
Finished Mar 19 03:22:37 PM PDT 24
Peak memory 208576 kb
Host smart-c22e4b3c-79ab-4ecc-8425-587992dc7720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3713489858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.3713489858
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.4172028768
Short name T220
Test name
Test status
Simulation time 253424036 ps
CPU time 3.21 seconds
Started Mar 19 03:22:43 PM PDT 24
Finished Mar 19 03:22:47 PM PDT 24
Peak memory 208992 kb
Host smart-9d879e72-7e4f-4ca4-a0b7-1f120ab3bf40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172028768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.4172028768
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.2586353367
Short name T749
Test name
Test status
Simulation time 525982583 ps
CPU time 14.95 seconds
Started Mar 19 03:22:42 PM PDT 24
Finished Mar 19 03:22:58 PM PDT 24
Peak memory 209628 kb
Host smart-0505db7b-3b73-4cf9-a1c4-930b06b47867
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2586353367 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.2586353367
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.3159993486
Short name T701
Test name
Test status
Simulation time 79860443 ps
CPU time 3.01 seconds
Started Mar 19 03:22:47 PM PDT 24
Finished Mar 19 03:22:51 PM PDT 24
Peak memory 207196 kb
Host smart-c4c15762-15c2-45bf-8121-a8a6996cb45e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3159993486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.3159993486
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.4149208218
Short name T739
Test name
Test status
Simulation time 402389974 ps
CPU time 3.61 seconds
Started Mar 19 03:22:34 PM PDT 24
Finished Mar 19 03:22:39 PM PDT 24
Peak memory 207308 kb
Host smart-8341e923-f519-4349-b639-70c63bbc2b42
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149208218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.4149208218
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.1525107312
Short name T267
Test name
Test status
Simulation time 526274559 ps
CPU time 2.81 seconds
Started Mar 19 03:22:47 PM PDT 24
Finished Mar 19 03:22:51 PM PDT 24
Peak memory 218620 kb
Host smart-50168508-456b-45da-bb10-673362d54705
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1525107312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.1525107312
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.2086835059
Short name T807
Test name
Test status
Simulation time 500749365 ps
CPU time 6.06 seconds
Started Mar 19 03:22:44 PM PDT 24
Finished Mar 19 03:22:51 PM PDT 24
Peak memory 207024 kb
Host smart-e4362484-3796-4292-8e9f-b938ec10bb11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2086835059 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.2086835059
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.571742037
Short name T513
Test name
Test status
Simulation time 591656495 ps
CPU time 6.4 seconds
Started Mar 19 03:22:53 PM PDT 24
Finished Mar 19 03:23:00 PM PDT 24
Peak memory 210320 kb
Host smart-b084c050-2a1f-4618-8207-dfabcbf8c08e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=571742037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.571742037
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.486763173
Short name T486
Test name
Test status
Simulation time 29120948 ps
CPU time 1.79 seconds
Started Mar 19 03:22:50 PM PDT 24
Finished Mar 19 03:22:52 PM PDT 24
Peak memory 210172 kb
Host smart-363f77c1-3b69-450c-b88f-3c352a4fc269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486763173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.486763173
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.3464104144
Short name T874
Test name
Test status
Simulation time 11999908 ps
CPU time 0.87 seconds
Started Mar 19 03:22:38 PM PDT 24
Finished Mar 19 03:22:39 PM PDT 24
Peak memory 206384 kb
Host smart-faec3e0b-d9cd-463a-83b5-66cf7ff9982a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464104144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.3464104144
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.1455201104
Short name T122
Test name
Test status
Simulation time 81577652 ps
CPU time 3.11 seconds
Started Mar 19 03:22:35 PM PDT 24
Finished Mar 19 03:22:39 PM PDT 24
Peak memory 216232 kb
Host smart-3fe98864-d84f-4724-ac62-8b80f8fea705
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1455201104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.1455201104
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.2463862155
Short name T586
Test name
Test status
Simulation time 127010633 ps
CPU time 3.18 seconds
Started Mar 19 03:22:45 PM PDT 24
Finished Mar 19 03:22:49 PM PDT 24
Peak memory 209712 kb
Host smart-c14c70dc-2dcf-407d-8e1e-cc566313e1f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2463862155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.2463862155
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.2499210064
Short name T295
Test name
Test status
Simulation time 1746866831 ps
CPU time 18.5 seconds
Started Mar 19 03:22:46 PM PDT 24
Finished Mar 19 03:23:06 PM PDT 24
Peak memory 209648 kb
Host smart-efd47aa9-9cb1-4eba-8b77-9d1b1e508aab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499210064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.2499210064
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.3318402399
Short name T336
Test name
Test status
Simulation time 227279020 ps
CPU time 6.03 seconds
Started Mar 19 03:22:37 PM PDT 24
Finished Mar 19 03:22:43 PM PDT 24
Peak memory 210668 kb
Host smart-856c06df-3943-49c3-8675-b5543a4d2aa8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3318402399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.3318402399
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.1403438087
Short name T604
Test name
Test status
Simulation time 166423166 ps
CPU time 3.28 seconds
Started Mar 19 03:22:34 PM PDT 24
Finished Mar 19 03:22:37 PM PDT 24
Peak memory 208744 kb
Host smart-fdb35958-1e0d-461a-916d-4f3c4b37f6e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1403438087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.1403438087
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.2680306539
Short name T366
Test name
Test status
Simulation time 405789984 ps
CPU time 3.51 seconds
Started Mar 19 03:22:40 PM PDT 24
Finished Mar 19 03:22:44 PM PDT 24
Peak memory 218676 kb
Host smart-d61abc43-b8ea-4aad-b3e4-c7d2856deac7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680306539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.2680306539
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.1406146695
Short name T809
Test name
Test status
Simulation time 237925657 ps
CPU time 5.17 seconds
Started Mar 19 03:22:46 PM PDT 24
Finished Mar 19 03:22:52 PM PDT 24
Peak memory 206776 kb
Host smart-70c3c524-24ce-4c2c-a59e-ea3a134dd7a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1406146695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.1406146695
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.2503125299
Short name T212
Test name
Test status
Simulation time 158770806 ps
CPU time 4.93 seconds
Started Mar 19 03:22:49 PM PDT 24
Finished Mar 19 03:22:54 PM PDT 24
Peak memory 208880 kb
Host smart-1c1f3f31-060d-4eeb-8b86-3098641b502b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2503125299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.2503125299
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.1096270582
Short name T685
Test name
Test status
Simulation time 5463524761 ps
CPU time 48.17 seconds
Started Mar 19 03:22:37 PM PDT 24
Finished Mar 19 03:23:26 PM PDT 24
Peak memory 208784 kb
Host smart-613c38c6-19a3-473a-aa6d-4addfea6c9f1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1096270582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.1096270582
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.2455012909
Short name T448
Test name
Test status
Simulation time 235601366 ps
CPU time 5.65 seconds
Started Mar 19 03:22:47 PM PDT 24
Finished Mar 19 03:22:53 PM PDT 24
Peak memory 208876 kb
Host smart-f4acb308-1cc3-4a0f-9f75-40e97ff5cde1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455012909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.2455012909
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.1616928717
Short name T601
Test name
Test status
Simulation time 63955844 ps
CPU time 2.47 seconds
Started Mar 19 03:22:46 PM PDT 24
Finished Mar 19 03:22:50 PM PDT 24
Peak memory 214400 kb
Host smart-b46f58bc-54d6-4ae9-919f-63f2b496d720
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616928717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.1616928717
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.1771678288
Short name T473
Test name
Test status
Simulation time 800084015 ps
CPU time 6.4 seconds
Started Mar 19 03:22:47 PM PDT 24
Finished Mar 19 03:22:54 PM PDT 24
Peak memory 207244 kb
Host smart-dfd09d38-6430-4083-aee4-05eb5b9002d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771678288 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.1771678288
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.324127886
Short name T363
Test name
Test status
Simulation time 255430419 ps
CPU time 5.03 seconds
Started Mar 19 03:22:30 PM PDT 24
Finished Mar 19 03:22:35 PM PDT 24
Peak memory 209076 kb
Host smart-a1b84bd2-3c6e-4b7b-9d88-3724c62e2bd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=324127886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.324127886
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.387352472
Short name T555
Test name
Test status
Simulation time 14285035 ps
CPU time 0.75 seconds
Started Mar 19 03:22:45 PM PDT 24
Finished Mar 19 03:22:47 PM PDT 24
Peak memory 206424 kb
Host smart-4b3f3431-5289-47ce-9d74-ee5b96a47e64
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=387352472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.387352472
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.2559421975
Short name T419
Test name
Test status
Simulation time 38789535 ps
CPU time 3.01 seconds
Started Mar 19 03:22:57 PM PDT 24
Finished Mar 19 03:23:00 PM PDT 24
Peak memory 215036 kb
Host smart-ce835d63-6bef-4d46-b39d-023828c46125
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2559421975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.2559421975
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.402975948
Short name T64
Test name
Test status
Simulation time 168738799 ps
CPU time 1.96 seconds
Started Mar 19 03:22:49 PM PDT 24
Finished Mar 19 03:22:51 PM PDT 24
Peak memory 208380 kb
Host smart-3a3ba21e-cceb-44ad-9c1d-aee042db3771
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402975948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.402975948
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.928178790
Short name T357
Test name
Test status
Simulation time 49011359 ps
CPU time 3.07 seconds
Started Mar 19 03:22:51 PM PDT 24
Finished Mar 19 03:22:54 PM PDT 24
Peak memory 209892 kb
Host smart-d90ba7d8-b601-48d8-992c-b00740901a26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928178790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.928178790
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.2442605587
Short name T43
Test name
Test status
Simulation time 87822467 ps
CPU time 2.93 seconds
Started Mar 19 03:22:49 PM PDT 24
Finished Mar 19 03:22:52 PM PDT 24
Peak memory 210068 kb
Host smart-c22e6cc6-58e4-46d8-87b1-88b76432ec73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2442605587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.2442605587
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.244491819
Short name T848
Test name
Test status
Simulation time 215335910 ps
CPU time 4.07 seconds
Started Mar 19 03:22:59 PM PDT 24
Finished Mar 19 03:23:03 PM PDT 24
Peak memory 214788 kb
Host smart-26ea1a86-adbe-4842-a1ec-302a5b3f415d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=244491819 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.244491819
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.1606413166
Short name T673
Test name
Test status
Simulation time 38741098 ps
CPU time 2.8 seconds
Started Mar 19 03:22:46 PM PDT 24
Finished Mar 19 03:22:50 PM PDT 24
Peak memory 209052 kb
Host smart-5a92161c-8dca-4c80-aa89-14707df96830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1606413166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.1606413166
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.3727955691
Short name T230
Test name
Test status
Simulation time 30561745 ps
CPU time 1.86 seconds
Started Mar 19 03:22:40 PM PDT 24
Finished Mar 19 03:22:42 PM PDT 24
Peak memory 207416 kb
Host smart-b9204bb8-d354-470a-ab88-9b1de9300798
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3727955691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.3727955691
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.3664466960
Short name T382
Test name
Test status
Simulation time 831512843 ps
CPU time 9.97 seconds
Started Mar 19 03:22:51 PM PDT 24
Finished Mar 19 03:23:01 PM PDT 24
Peak memory 208640 kb
Host smart-cc394f14-39ff-466b-af51-eec064876362
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3664466960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.3664466960
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.1867441948
Short name T762
Test name
Test status
Simulation time 107541611 ps
CPU time 3.17 seconds
Started Mar 19 03:22:45 PM PDT 24
Finished Mar 19 03:22:48 PM PDT 24
Peak memory 207276 kb
Host smart-ee24e5b2-7655-425e-a84a-dd8dc6b8e825
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867441948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.1867441948
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.1793690835
Short name T783
Test name
Test status
Simulation time 100894805 ps
CPU time 4.16 seconds
Started Mar 19 03:22:49 PM PDT 24
Finished Mar 19 03:22:54 PM PDT 24
Peak memory 214840 kb
Host smart-a0694bfc-95ea-4dc8-a34c-877f975fa546
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1793690835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.1793690835
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.809296093
Short name T787
Test name
Test status
Simulation time 427006042 ps
CPU time 5.5 seconds
Started Mar 19 03:22:47 PM PDT 24
Finished Mar 19 03:22:53 PM PDT 24
Peak memory 207096 kb
Host smart-5cbca4c5-92e0-4767-a2ee-54e4ac048ede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=809296093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.809296093
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.3246351325
Short name T449
Test name
Test status
Simulation time 73512738 ps
CPU time 2.29 seconds
Started Mar 19 03:22:55 PM PDT 24
Finished Mar 19 03:22:57 PM PDT 24
Peak memory 208892 kb
Host smart-52067404-8025-48f2-808b-72efc8a2eacf
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3246351325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.3246351325
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.602366390
Short name T861
Test name
Test status
Simulation time 296595756 ps
CPU time 6.98 seconds
Started Mar 19 03:22:48 PM PDT 24
Finished Mar 19 03:22:55 PM PDT 24
Peak memory 219000 kb
Host smart-b48f8da6-d423-45d4-8ec4-575fb00ce7f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602366390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.602366390
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.2399132788
Short name T879
Test name
Test status
Simulation time 115572446 ps
CPU time 2.5 seconds
Started Mar 19 03:22:50 PM PDT 24
Finished Mar 19 03:22:53 PM PDT 24
Peak memory 210688 kb
Host smart-c65d8679-9a8f-4c31-8e8d-02845834ea95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2399132788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.2399132788
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.893904358
Short name T802
Test name
Test status
Simulation time 17855137 ps
CPU time 0.8 seconds
Started Mar 19 03:22:43 PM PDT 24
Finished Mar 19 03:22:45 PM PDT 24
Peak memory 206460 kb
Host smart-4c72e788-76f5-4135-a7dd-30986eca7d07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893904358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.893904358
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.2829182379
Short name T22
Test name
Test status
Simulation time 79411178 ps
CPU time 3 seconds
Started Mar 19 03:22:48 PM PDT 24
Finished Mar 19 03:22:52 PM PDT 24
Peak memory 209932 kb
Host smart-a7427b5d-23ae-4398-bdaa-1db1d943871f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2829182379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.2829182379
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.1331358284
Short name T795
Test name
Test status
Simulation time 101870453 ps
CPU time 3.17 seconds
Started Mar 19 03:22:49 PM PDT 24
Finished Mar 19 03:22:52 PM PDT 24
Peak memory 209672 kb
Host smart-a6fef7c2-0832-4a5d-9751-b0bbe5551ec9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331358284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.1331358284
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.2163060041
Short name T88
Test name
Test status
Simulation time 10499654965 ps
CPU time 36.34 seconds
Started Mar 19 03:22:53 PM PDT 24
Finished Mar 19 03:23:29 PM PDT 24
Peak memory 214844 kb
Host smart-755b8f73-a828-4180-b4c9-fb2cc0652b60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2163060041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.2163060041
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.3243802595
Short name T622
Test name
Test status
Simulation time 480417330 ps
CPU time 4.4 seconds
Started Mar 19 03:22:46 PM PDT 24
Finished Mar 19 03:22:51 PM PDT 24
Peak memory 215648 kb
Host smart-1438587f-0aa1-44db-88df-d375cfabfb02
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243802595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.3243802595
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.2623844942
Short name T144
Test name
Test status
Simulation time 149185873 ps
CPU time 4.74 seconds
Started Mar 19 03:22:46 PM PDT 24
Finished Mar 19 03:22:51 PM PDT 24
Peak memory 208380 kb
Host smart-ff14a17c-41ec-42f3-9a40-4a754c338d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2623844942 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.2623844942
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.2887191609
Short name T725
Test name
Test status
Simulation time 5451964684 ps
CPU time 38.62 seconds
Started Mar 19 03:22:48 PM PDT 24
Finished Mar 19 03:23:32 PM PDT 24
Peak memory 208460 kb
Host smart-174523d5-a967-4a95-abb6-e6e52b4d0df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2887191609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.2887191609
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.1819207473
Short name T453
Test name
Test status
Simulation time 207906290 ps
CPU time 1.85 seconds
Started Mar 19 03:22:51 PM PDT 24
Finished Mar 19 03:22:53 PM PDT 24
Peak memory 207292 kb
Host smart-957a27b0-041b-45cd-9afe-a0b17b783741
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819207473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.1819207473
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.1276285357
Short name T582
Test name
Test status
Simulation time 501599761 ps
CPU time 13.33 seconds
Started Mar 19 03:22:51 PM PDT 24
Finished Mar 19 03:23:05 PM PDT 24
Peak memory 208284 kb
Host smart-618612a5-c246-47a0-804a-a87c979d15c5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276285357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.1276285357
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.3666017246
Short name T647
Test name
Test status
Simulation time 2521558788 ps
CPU time 10.69 seconds
Started Mar 19 03:22:50 PM PDT 24
Finished Mar 19 03:23:01 PM PDT 24
Peak memory 208564 kb
Host smart-ca446101-0c1d-4fd1-9134-6d797dc5aa2e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3666017246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.3666017246
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.3966594722
Short name T629
Test name
Test status
Simulation time 27668610 ps
CPU time 2.02 seconds
Started Mar 19 03:22:45 PM PDT 24
Finished Mar 19 03:22:48 PM PDT 24
Peak memory 210212 kb
Host smart-e2fd6cab-086a-40fb-b9bf-75a74edea743
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3966594722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.3966594722
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.4246771066
Short name T785
Test name
Test status
Simulation time 859927854 ps
CPU time 6.11 seconds
Started Mar 19 03:22:51 PM PDT 24
Finished Mar 19 03:22:58 PM PDT 24
Peak memory 208988 kb
Host smart-b29fb575-b27d-4676-a0a4-90cc61c7c022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246771066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.4246771066
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.3067155837
Short name T773
Test name
Test status
Simulation time 39261933 ps
CPU time 1.85 seconds
Started Mar 19 03:22:52 PM PDT 24
Finished Mar 19 03:22:54 PM PDT 24
Peak memory 208644 kb
Host smart-ebcd3028-76d0-4f06-8da9-5332d41d143a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3067155837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.3067155837
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.3456150333
Short name T746
Test name
Test status
Simulation time 133665130 ps
CPU time 2.96 seconds
Started Mar 19 03:22:50 PM PDT 24
Finished Mar 19 03:22:54 PM PDT 24
Peak memory 208196 kb
Host smart-be80f4fa-03ed-4809-b6ce-36d6b93bc77b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456150333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.3456150333
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.532894987
Short name T516
Test name
Test status
Simulation time 78235686 ps
CPU time 3.04 seconds
Started Mar 19 03:22:52 PM PDT 24
Finished Mar 19 03:22:56 PM PDT 24
Peak memory 210372 kb
Host smart-d7a98e7a-0315-4349-9903-5b3c183f5f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532894987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.532894987
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.698182544
Short name T99
Test name
Test status
Simulation time 17350320 ps
CPU time 0.86 seconds
Started Mar 19 03:22:49 PM PDT 24
Finished Mar 19 03:22:50 PM PDT 24
Peak memory 206456 kb
Host smart-5eb34ee1-1270-4605-8696-e0450c0e5e04
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698182544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.698182544
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.4130869593
Short name T151
Test name
Test status
Simulation time 33460631 ps
CPU time 2.87 seconds
Started Mar 19 03:22:48 PM PDT 24
Finished Mar 19 03:22:51 PM PDT 24
Peak memory 214716 kb
Host smart-7f6a3cd0-09c3-4421-abd3-99d20ddb6f94
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4130869593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.4130869593
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.1226060108
Short name T13
Test name
Test status
Simulation time 507410894 ps
CPU time 4.29 seconds
Started Mar 19 03:22:45 PM PDT 24
Finished Mar 19 03:22:51 PM PDT 24
Peak memory 209716 kb
Host smart-dd395b6d-f2e9-40fb-a00f-3b052daf4c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226060108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.1226060108
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.4104656594
Short name T757
Test name
Test status
Simulation time 32781328 ps
CPU time 1.88 seconds
Started Mar 19 03:22:53 PM PDT 24
Finished Mar 19 03:22:55 PM PDT 24
Peak memory 209712 kb
Host smart-830fc573-bd30-4817-b120-8d76502ee83c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4104656594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.4104656594
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.4023185239
Short name T91
Test name
Test status
Simulation time 995293403 ps
CPU time 5.76 seconds
Started Mar 19 03:22:55 PM PDT 24
Finished Mar 19 03:23:01 PM PDT 24
Peak memory 209924 kb
Host smart-6df7942e-2a98-4ef7-9553-4253b20adcbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4023185239 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.4023185239
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.4280524532
Short name T581
Test name
Test status
Simulation time 89776787 ps
CPU time 3.84 seconds
Started Mar 19 03:22:45 PM PDT 24
Finished Mar 19 03:22:50 PM PDT 24
Peak memory 220456 kb
Host smart-0520e25c-7437-4930-9c32-3a7182e65853
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280524532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.4280524532
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.1008380795
Short name T839
Test name
Test status
Simulation time 122599904 ps
CPU time 4.1 seconds
Started Mar 19 03:22:55 PM PDT 24
Finished Mar 19 03:22:59 PM PDT 24
Peak memory 214824 kb
Host smart-eccc1a4b-ae8b-4955-abff-c5f5d4e5e357
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008380795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.1008380795
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.1632423990
Short name T311
Test name
Test status
Simulation time 395267562 ps
CPU time 3.41 seconds
Started Mar 19 03:22:52 PM PDT 24
Finished Mar 19 03:22:56 PM PDT 24
Peak memory 207068 kb
Host smart-a1261eba-4308-4c15-b6ab-30be7fb38347
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1632423990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.1632423990
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.2326230537
Short name T836
Test name
Test status
Simulation time 449771932 ps
CPU time 5.38 seconds
Started Mar 19 03:22:52 PM PDT 24
Finished Mar 19 03:22:57 PM PDT 24
Peak memory 207224 kb
Host smart-4e7cbe6b-bebe-4efb-b38f-8dee2bbc491d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2326230537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.2326230537
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.350896240
Short name T644
Test name
Test status
Simulation time 896419670 ps
CPU time 6.37 seconds
Started Mar 19 03:22:58 PM PDT 24
Finished Mar 19 03:23:05 PM PDT 24
Peak memory 209056 kb
Host smart-d24f4713-9755-4be3-a0b0-4e5b5a57fcec
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=350896240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.350896240
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.4250979595
Short name T556
Test name
Test status
Simulation time 1863052766 ps
CPU time 24.23 seconds
Started Mar 19 03:22:51 PM PDT 24
Finished Mar 19 03:23:15 PM PDT 24
Peak memory 208436 kb
Host smart-b79cb54c-a367-4047-b19d-43045b0c5a5b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250979595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.4250979595
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.740436207
Short name T485
Test name
Test status
Simulation time 41465971 ps
CPU time 1.99 seconds
Started Mar 19 03:22:55 PM PDT 24
Finished Mar 19 03:22:57 PM PDT 24
Peak memory 209668 kb
Host smart-92807469-4151-4611-8d07-32479ebd4269
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=740436207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.740436207
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.2225951361
Short name T662
Test name
Test status
Simulation time 60573144 ps
CPU time 2.36 seconds
Started Mar 19 03:23:03 PM PDT 24
Finished Mar 19 03:23:05 PM PDT 24
Peak memory 209272 kb
Host smart-ff3fd2a6-6a90-471f-bdc2-9967f812d4f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2225951361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.2225951361
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.3838314593
Short name T369
Test name
Test status
Simulation time 290661800 ps
CPU time 5.05 seconds
Started Mar 19 03:22:47 PM PDT 24
Finished Mar 19 03:22:53 PM PDT 24
Peak memory 207992 kb
Host smart-cde31c17-695b-46f2-a16f-f8981cc80241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3838314593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.3838314593
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.1548845596
Short name T481
Test name
Test status
Simulation time 335406280 ps
CPU time 3.39 seconds
Started Mar 19 03:22:56 PM PDT 24
Finished Mar 19 03:22:59 PM PDT 24
Peak memory 210464 kb
Host smart-acbe2237-81a1-4f1f-ae06-08565916073e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548845596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.1548845596
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.2175481801
Short name T464
Test name
Test status
Simulation time 11680059 ps
CPU time 0.72 seconds
Started Mar 19 03:22:54 PM PDT 24
Finished Mar 19 03:22:55 PM PDT 24
Peak memory 206356 kb
Host smart-f60d20de-a1a7-4c89-b39d-a6d05207f65c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2175481801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.2175481801
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.459908902
Short name T73
Test name
Test status
Simulation time 341091071 ps
CPU time 4.65 seconds
Started Mar 19 03:22:54 PM PDT 24
Finished Mar 19 03:22:59 PM PDT 24
Peak memory 208536 kb
Host smart-99c15963-0cf1-4f04-81a0-f12b652415ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459908902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.459908902
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.2418272844
Short name T677
Test name
Test status
Simulation time 955100575 ps
CPU time 11.44 seconds
Started Mar 19 03:22:52 PM PDT 24
Finished Mar 19 03:23:03 PM PDT 24
Peak memory 214884 kb
Host smart-df972338-1130-407e-8df1-e49f936c8eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2418272844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.2418272844
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.2092402294
Short name T806
Test name
Test status
Simulation time 316800354 ps
CPU time 3.19 seconds
Started Mar 19 03:23:01 PM PDT 24
Finished Mar 19 03:23:05 PM PDT 24
Peak memory 211856 kb
Host smart-daf7b153-bfe2-4bba-a1b0-10276864d9e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2092402294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.2092402294
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.3226843698
Short name T774
Test name
Test status
Simulation time 906986389 ps
CPU time 3.5 seconds
Started Mar 19 03:23:08 PM PDT 24
Finished Mar 19 03:23:11 PM PDT 24
Peak memory 214796 kb
Host smart-eac5d2ef-41ba-4274-a4cb-8af18a8e77f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3226843698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.3226843698
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.977140558
Short name T599
Test name
Test status
Simulation time 774827132 ps
CPU time 5.51 seconds
Started Mar 19 03:22:47 PM PDT 24
Finished Mar 19 03:22:53 PM PDT 24
Peak memory 210144 kb
Host smart-46a5328d-7cd0-468d-80ec-b34fbc22bb51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=977140558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.977140558
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.390032065
Short name T349
Test name
Test status
Simulation time 644721755 ps
CPU time 6.98 seconds
Started Mar 19 03:22:53 PM PDT 24
Finished Mar 19 03:23:00 PM PDT 24
Peak memory 208856 kb
Host smart-799a1a44-1780-4e15-9c17-04dc111bff59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390032065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.390032065
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.939959629
Short name T890
Test name
Test status
Simulation time 54614198 ps
CPU time 2.85 seconds
Started Mar 19 03:22:48 PM PDT 24
Finished Mar 19 03:22:51 PM PDT 24
Peak memory 207328 kb
Host smart-043e3706-5da7-4e67-9e28-03187fe7e431
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939959629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.939959629
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.2736736810
Short name T205
Test name
Test status
Simulation time 115337454 ps
CPU time 3.24 seconds
Started Mar 19 03:22:51 PM PDT 24
Finished Mar 19 03:22:55 PM PDT 24
Peak memory 209328 kb
Host smart-3bf5685b-1feb-4556-8e61-ccf789b52e88
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2736736810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.2736736810
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.1178438799
Short name T135
Test name
Test status
Simulation time 65834580 ps
CPU time 3.17 seconds
Started Mar 19 03:22:50 PM PDT 24
Finished Mar 19 03:22:53 PM PDT 24
Peak memory 207124 kb
Host smart-38d855e7-72b6-4920-84bb-816a65be7e77
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1178438799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.1178438799
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.55078515
Short name T380
Test name
Test status
Simulation time 76181407 ps
CPU time 2.81 seconds
Started Mar 19 03:22:57 PM PDT 24
Finished Mar 19 03:23:00 PM PDT 24
Peak memory 218964 kb
Host smart-559303b1-ad28-4e60-a7f2-7a09c7f0a28d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55078515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.55078515
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.162262636
Short name T579
Test name
Test status
Simulation time 1255198691 ps
CPU time 6.67 seconds
Started Mar 19 03:22:56 PM PDT 24
Finished Mar 19 03:23:03 PM PDT 24
Peak memory 208780 kb
Host smart-3f3975d2-1583-4ce4-8b49-5098fc80c52b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162262636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.162262636
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.4250044954
Short name T71
Test name
Test status
Simulation time 4633801319 ps
CPU time 57.88 seconds
Started Mar 19 03:22:54 PM PDT 24
Finished Mar 19 03:23:52 PM PDT 24
Peak memory 222768 kb
Host smart-c338df63-b458-4935-905e-cd71e793bcf4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4250044954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.4250044954
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.2758327044
Short name T718
Test name
Test status
Simulation time 727265465 ps
CPU time 19.04 seconds
Started Mar 19 03:23:00 PM PDT 24
Finished Mar 19 03:23:19 PM PDT 24
Peak memory 214772 kb
Host smart-8a2b10ab-a5a3-4e38-96d0-d16bfecc4005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2758327044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.2758327044
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.2922753882
Short name T798
Test name
Test status
Simulation time 13121758 ps
CPU time 0.88 seconds
Started Mar 19 03:22:50 PM PDT 24
Finished Mar 19 03:22:51 PM PDT 24
Peak memory 206448 kb
Host smart-4db56446-63a5-47f4-ba7f-0162002d64fb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2922753882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.2922753882
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.1899481227
Short name T152
Test name
Test status
Simulation time 108789076 ps
CPU time 2.66 seconds
Started Mar 19 03:22:57 PM PDT 24
Finished Mar 19 03:23:00 PM PDT 24
Peak memory 215660 kb
Host smart-c477469a-372d-40f1-853c-7f533e145c59
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1899481227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.1899481227
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.4199653592
Short name T731
Test name
Test status
Simulation time 171754148 ps
CPU time 1.25 seconds
Started Mar 19 03:22:57 PM PDT 24
Finished Mar 19 03:22:59 PM PDT 24
Peak memory 207492 kb
Host smart-5203a44c-8231-4718-aeae-4335dd5098cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199653592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.4199653592
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.1496042814
Short name T323
Test name
Test status
Simulation time 145565361 ps
CPU time 4.8 seconds
Started Mar 19 03:23:03 PM PDT 24
Finished Mar 19 03:23:08 PM PDT 24
Peak memory 219648 kb
Host smart-75261385-a0e5-4cd8-bfab-e2c948255f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1496042814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.1496042814
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.2304382919
Short name T686
Test name
Test status
Simulation time 113305347 ps
CPU time 6.39 seconds
Started Mar 19 03:22:58 PM PDT 24
Finished Mar 19 03:23:05 PM PDT 24
Peak memory 214884 kb
Host smart-4f2f9f95-e560-4002-8d58-4f4aa3486c3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2304382919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.2304382919
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.2871739338
Short name T309
Test name
Test status
Simulation time 106383017 ps
CPU time 3.01 seconds
Started Mar 19 03:22:58 PM PDT 24
Finished Mar 19 03:23:02 PM PDT 24
Peak memory 207920 kb
Host smart-51fc5639-e530-4c1f-bc55-c6972253f411
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871739338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.2871739338
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.520647233
Short name T829
Test name
Test status
Simulation time 73183911 ps
CPU time 3.45 seconds
Started Mar 19 03:22:58 PM PDT 24
Finished Mar 19 03:23:02 PM PDT 24
Peak memory 208388 kb
Host smart-acce3e99-145f-4771-9b8d-c5538a6c84ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520647233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.520647233
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.2032472939
Short name T549
Test name
Test status
Simulation time 2609461900 ps
CPU time 18.69 seconds
Started Mar 19 03:22:57 PM PDT 24
Finished Mar 19 03:23:17 PM PDT 24
Peak memory 209260 kb
Host smart-8a863276-e551-4136-9164-59e3e2f2f6a3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2032472939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.2032472939
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.3180242171
Short name T654
Test name
Test status
Simulation time 476475907 ps
CPU time 6.22 seconds
Started Mar 19 03:22:53 PM PDT 24
Finished Mar 19 03:23:00 PM PDT 24
Peak memory 209092 kb
Host smart-f28a4414-755c-44ad-81fa-ab59302e09a8
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3180242171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.3180242171
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.3199004543
Short name T684
Test name
Test status
Simulation time 43565895 ps
CPU time 2.64 seconds
Started Mar 19 03:23:04 PM PDT 24
Finished Mar 19 03:23:07 PM PDT 24
Peak memory 207184 kb
Host smart-cd686eb8-5d80-4947-b1c7-b11eb79ea8c6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199004543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.3199004543
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.4196178626
Short name T282
Test name
Test status
Simulation time 84798264 ps
CPU time 2.34 seconds
Started Mar 19 03:22:54 PM PDT 24
Finished Mar 19 03:22:57 PM PDT 24
Peak memory 209748 kb
Host smart-21c9c0f3-354f-4267-afff-043a30735ee5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4196178626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.4196178626
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.2277783316
Short name T203
Test name
Test status
Simulation time 3443661329 ps
CPU time 5.41 seconds
Started Mar 19 03:22:55 PM PDT 24
Finished Mar 19 03:23:01 PM PDT 24
Peak memory 207268 kb
Host smart-b987c91a-f16f-4eda-af10-da18af842398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277783316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.2277783316
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all_with_rand_reset.3731099020
Short name T333
Test name
Test status
Simulation time 1161558809 ps
CPU time 13.55 seconds
Started Mar 19 03:22:57 PM PDT 24
Finished Mar 19 03:23:11 PM PDT 24
Peak memory 221260 kb
Host smart-184f0d19-fc8f-45e1-887b-d22bc2ba1004
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3731099020 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all_with_rand_reset.3731099020
Directory /workspace/37.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.1177752280
Short name T293
Test name
Test status
Simulation time 83127375 ps
CPU time 4.12 seconds
Started Mar 19 03:22:59 PM PDT 24
Finished Mar 19 03:23:03 PM PDT 24
Peak memory 209720 kb
Host smart-83d9a4f2-b318-4860-837a-5d0c397a784b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177752280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.1177752280
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.1855230187
Short name T394
Test name
Test status
Simulation time 236935822 ps
CPU time 2.88 seconds
Started Mar 19 03:22:54 PM PDT 24
Finished Mar 19 03:22:57 PM PDT 24
Peak memory 210488 kb
Host smart-98bd98f8-47ef-48bb-98f1-5ec96e406007
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855230187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.1855230187
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.3765901809
Short name T827
Test name
Test status
Simulation time 20003379 ps
CPU time 0.93 seconds
Started Mar 19 03:22:57 PM PDT 24
Finished Mar 19 03:22:59 PM PDT 24
Peak memory 206512 kb
Host smart-4b762a68-a3a9-4df4-b5f5-336e4b340d0f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3765901809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.3765901809
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.4001531739
Short name T411
Test name
Test status
Simulation time 313280808 ps
CPU time 4.97 seconds
Started Mar 19 03:22:55 PM PDT 24
Finished Mar 19 03:23:00 PM PDT 24
Peak memory 222980 kb
Host smart-def3094c-58f2-4467-971e-93b73cb9c6ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4001531739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.4001531739
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.2002848240
Short name T545
Test name
Test status
Simulation time 866774901 ps
CPU time 32.47 seconds
Started Mar 19 03:23:01 PM PDT 24
Finished Mar 19 03:23:34 PM PDT 24
Peak memory 222016 kb
Host smart-2726e934-bef5-4a04-b08d-4827b27a73bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002848240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.2002848240
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.530581300
Short name T738
Test name
Test status
Simulation time 1205953022 ps
CPU time 24.71 seconds
Started Mar 19 03:22:52 PM PDT 24
Finished Mar 19 03:23:17 PM PDT 24
Peak memory 219504 kb
Host smart-f1122254-9c8e-4386-99f7-de37370b3aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=530581300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.530581300
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.3189479341
Short name T736
Test name
Test status
Simulation time 149412756 ps
CPU time 2.98 seconds
Started Mar 19 03:23:07 PM PDT 24
Finished Mar 19 03:23:10 PM PDT 24
Peak memory 209884 kb
Host smart-25fd2350-9037-4e9f-a9e3-847390a7d35c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189479341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.3189479341
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.2819615056
Short name T37
Test name
Test status
Simulation time 103537666 ps
CPU time 3.28 seconds
Started Mar 19 03:23:00 PM PDT 24
Finished Mar 19 03:23:04 PM PDT 24
Peak memory 212088 kb
Host smart-95cf34d7-a30d-48c5-b442-ee07dcb31ce4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819615056 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.2819615056
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.2793060312
Short name T42
Test name
Test status
Simulation time 117401236 ps
CPU time 2.44 seconds
Started Mar 19 03:22:56 PM PDT 24
Finished Mar 19 03:22:58 PM PDT 24
Peak memory 208772 kb
Host smart-e59ecffe-bd72-49b7-b7b9-5e2a597def6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2793060312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.2793060312
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.3508617661
Short name T728
Test name
Test status
Simulation time 1341548852 ps
CPU time 17.73 seconds
Started Mar 19 03:22:59 PM PDT 24
Finished Mar 19 03:23:17 PM PDT 24
Peak memory 209600 kb
Host smart-0a2f7282-cb7d-48fb-b196-d857029b9e28
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3508617661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.3508617661
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.336771123
Short name T478
Test name
Test status
Simulation time 248476676 ps
CPU time 7.41 seconds
Started Mar 19 03:22:53 PM PDT 24
Finished Mar 19 03:23:00 PM PDT 24
Peak memory 208308 kb
Host smart-175c0112-696a-4a6d-9d3a-7ca2fa583693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=336771123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.336771123
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.2162719238
Short name T867
Test name
Test status
Simulation time 1207794532 ps
CPU time 27.76 seconds
Started Mar 19 03:23:09 PM PDT 24
Finished Mar 19 03:23:37 PM PDT 24
Peak memory 208880 kb
Host smart-2b5b91aa-8ff1-4b52-b125-30be9fb6b127
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2162719238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.2162719238
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.2618747321
Short name T894
Test name
Test status
Simulation time 409182418 ps
CPU time 4.95 seconds
Started Mar 19 03:23:08 PM PDT 24
Finished Mar 19 03:23:13 PM PDT 24
Peak memory 207280 kb
Host smart-1462b085-0b8c-4210-afe4-962c50c2e098
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2618747321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.2618747321
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.2474911769
Short name T313
Test name
Test status
Simulation time 196508258 ps
CPU time 7.29 seconds
Started Mar 19 03:22:54 PM PDT 24
Finished Mar 19 03:23:01 PM PDT 24
Peak memory 208600 kb
Host smart-71640fff-abe2-499b-b612-3422533613bb
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474911769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.2474911769
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.3642160526
Short name T772
Test name
Test status
Simulation time 157478022 ps
CPU time 3.95 seconds
Started Mar 19 03:22:51 PM PDT 24
Finished Mar 19 03:22:55 PM PDT 24
Peak memory 208888 kb
Host smart-c75bc338-37af-437b-8203-8d85cbb8e52b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3642160526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.3642160526
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.915966281
Short name T849
Test name
Test status
Simulation time 91939910 ps
CPU time 1.94 seconds
Started Mar 19 03:23:00 PM PDT 24
Finished Mar 19 03:23:02 PM PDT 24
Peak memory 208880 kb
Host smart-60fb4d33-99a5-4269-9b5d-c6c54b8bbc53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915966281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.915966281
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.320441251
Short name T242
Test name
Test status
Simulation time 25168410241 ps
CPU time 257.74 seconds
Started Mar 19 03:22:55 PM PDT 24
Finished Mar 19 03:27:13 PM PDT 24
Peak memory 219360 kb
Host smart-2ba48613-3f1a-4702-89a3-644b9269a694
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=320441251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.320441251
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.1050383108
Short name T344
Test name
Test status
Simulation time 184682174 ps
CPU time 3.11 seconds
Started Mar 19 03:22:54 PM PDT 24
Finished Mar 19 03:22:57 PM PDT 24
Peak memory 215596 kb
Host smart-a7e43e02-8c02-4f8b-8a97-bd671accee2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1050383108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.1050383108
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.3493542666
Short name T560
Test name
Test status
Simulation time 1851915891 ps
CPU time 4.96 seconds
Started Mar 19 03:23:01 PM PDT 24
Finished Mar 19 03:23:06 PM PDT 24
Peak memory 211464 kb
Host smart-e4694abb-8ec6-47b3-be83-44052f6c5221
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493542666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.3493542666
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.2867762325
Short name T855
Test name
Test status
Simulation time 12085574 ps
CPU time 0.88 seconds
Started Mar 19 03:22:55 PM PDT 24
Finished Mar 19 03:22:56 PM PDT 24
Peak memory 206424 kb
Host smart-15f1af6f-7e8b-41b5-9573-76fdb343641e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2867762325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.2867762325
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.3463541827
Short name T414
Test name
Test status
Simulation time 230910086 ps
CPU time 4.48 seconds
Started Mar 19 03:22:57 PM PDT 24
Finished Mar 19 03:23:02 PM PDT 24
Peak memory 214792 kb
Host smart-60c6ef1a-7eed-402d-945f-81afea90248c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3463541827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.3463541827
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.2020321518
Short name T818
Test name
Test status
Simulation time 26587307 ps
CPU time 1.6 seconds
Started Mar 19 03:23:01 PM PDT 24
Finished Mar 19 03:23:02 PM PDT 24
Peak memory 208240 kb
Host smart-9ec41733-3f90-4520-b13e-29e9837d9b85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020321518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.2020321518
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.3478506851
Short name T467
Test name
Test status
Simulation time 297428467 ps
CPU time 7.59 seconds
Started Mar 19 03:22:53 PM PDT 24
Finished Mar 19 03:23:01 PM PDT 24
Peak memory 214696 kb
Host smart-089cba1e-7727-454e-ad13-b7e5212f6404
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478506851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.3478506851
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.2353383992
Short name T297
Test name
Test status
Simulation time 540597390 ps
CPU time 7.12 seconds
Started Mar 19 03:22:58 PM PDT 24
Finished Mar 19 03:23:06 PM PDT 24
Peak memory 210424 kb
Host smart-09e1f557-e405-4378-81bf-441a048fe8d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353383992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.2353383992
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.4010336900
Short name T584
Test name
Test status
Simulation time 1326628364 ps
CPU time 3.92 seconds
Started Mar 19 03:23:01 PM PDT 24
Finished Mar 19 03:23:05 PM PDT 24
Peak memory 219416 kb
Host smart-627b439f-b826-4d14-8ebd-09ac3c2c5dd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010336900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.4010336900
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.1008499190
Short name T218
Test name
Test status
Simulation time 2758989987 ps
CPU time 7.02 seconds
Started Mar 19 03:23:00 PM PDT 24
Finished Mar 19 03:23:07 PM PDT 24
Peak memory 209508 kb
Host smart-3d31cb7e-8966-4104-af3c-d39fda0f7102
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1008499190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.1008499190
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.4039802676
Short name T482
Test name
Test status
Simulation time 359405921 ps
CPU time 5.41 seconds
Started Mar 19 03:22:58 PM PDT 24
Finished Mar 19 03:23:04 PM PDT 24
Peak memory 208348 kb
Host smart-defbaa7d-72ab-45af-9931-67636f3ea5fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039802676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.4039802676
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.3123907413
Short name T840
Test name
Test status
Simulation time 255413328 ps
CPU time 3.36 seconds
Started Mar 19 03:22:48 PM PDT 24
Finished Mar 19 03:22:51 PM PDT 24
Peak memory 208624 kb
Host smart-25910028-5ff2-4d2c-9e8d-4aae730150df
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3123907413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.3123907413
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.3859814014
Short name T633
Test name
Test status
Simulation time 1100736548 ps
CPU time 4.31 seconds
Started Mar 19 03:23:00 PM PDT 24
Finished Mar 19 03:23:04 PM PDT 24
Peak memory 209200 kb
Host smart-1867181a-0a86-4767-b429-c79190483dfb
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3859814014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.3859814014
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.379985735
Short name T553
Test name
Test status
Simulation time 153825819 ps
CPU time 4.81 seconds
Started Mar 19 03:23:09 PM PDT 24
Finished Mar 19 03:23:14 PM PDT 24
Peak memory 208992 kb
Host smart-3c5a84b3-1946-46d6-958c-0a30d3d71f41
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379985735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.379985735
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.958461255
Short name T261
Test name
Test status
Simulation time 150665740 ps
CPU time 2.42 seconds
Started Mar 19 03:23:03 PM PDT 24
Finished Mar 19 03:23:06 PM PDT 24
Peak memory 209984 kb
Host smart-02c21460-2444-4002-98bf-9f274e2bbbab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=958461255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.958461255
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.3893945785
Short name T659
Test name
Test status
Simulation time 142383250 ps
CPU time 3.74 seconds
Started Mar 19 03:22:57 PM PDT 24
Finished Mar 19 03:23:02 PM PDT 24
Peak memory 208660 kb
Host smart-45fa900a-5e94-4e98-ae39-62bce3f91dce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893945785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.3893945785
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.2046160971
Short name T833
Test name
Test status
Simulation time 3125970525 ps
CPU time 30.48 seconds
Started Mar 19 03:22:56 PM PDT 24
Finished Mar 19 03:23:26 PM PDT 24
Peak memory 216260 kb
Host smart-d0eb1c5a-c0d4-4d69-8b56-4d63b843f73c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2046160971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.2046160971
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.1515664847
Short name T361
Test name
Test status
Simulation time 159284959 ps
CPU time 4.21 seconds
Started Mar 19 03:22:56 PM PDT 24
Finished Mar 19 03:23:00 PM PDT 24
Peak memory 209728 kb
Host smart-e8eb434e-23a0-483e-8282-37432180ce70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515664847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.1515664847
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.3043953524
Short name T868
Test name
Test status
Simulation time 1271018836 ps
CPU time 11.9 seconds
Started Mar 19 03:22:58 PM PDT 24
Finished Mar 19 03:23:11 PM PDT 24
Peak memory 211408 kb
Host smart-e8716757-5bcd-469f-8b35-d85e78286be6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043953524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.3043953524
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.2478419286
Short name T747
Test name
Test status
Simulation time 75661034 ps
CPU time 1 seconds
Started Mar 19 03:21:25 PM PDT 24
Finished Mar 19 03:21:26 PM PDT 24
Peak memory 206668 kb
Host smart-405b875a-48d4-4551-8deb-a0013d231b1e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478419286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.2478419286
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.328109209
Short name T415
Test name
Test status
Simulation time 311959649 ps
CPU time 17.69 seconds
Started Mar 19 03:21:21 PM PDT 24
Finished Mar 19 03:21:39 PM PDT 24
Peak memory 214872 kb
Host smart-0e5f21dd-c7ea-4a94-b043-83586851d0bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=328109209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.328109209
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.3099815154
Short name T32
Test name
Test status
Simulation time 581189398 ps
CPU time 3.2 seconds
Started Mar 19 03:21:20 PM PDT 24
Finished Mar 19 03:21:23 PM PDT 24
Peak memory 219556 kb
Host smart-73850ba7-b6b7-42bd-9463-805ed76a69eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099815154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.3099815154
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.1550159090
Short name T476
Test name
Test status
Simulation time 320314320 ps
CPU time 1.98 seconds
Started Mar 19 03:21:22 PM PDT 24
Finished Mar 19 03:21:24 PM PDT 24
Peak memory 222940 kb
Host smart-868af1ba-e2a1-4792-89c3-d841c75f9b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1550159090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.1550159090
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.1775116151
Short name T715
Test name
Test status
Simulation time 786084687 ps
CPU time 6.41 seconds
Started Mar 19 03:21:24 PM PDT 24
Finished Mar 19 03:21:31 PM PDT 24
Peak memory 214704 kb
Host smart-12cf0cdb-a23e-4957-9c2e-bb0ff07f19e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775116151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.1775116151
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.281533254
Short name T25
Test name
Test status
Simulation time 587416986 ps
CPU time 6.91 seconds
Started Mar 19 03:21:26 PM PDT 24
Finished Mar 19 03:21:33 PM PDT 24
Peak memory 214756 kb
Host smart-05299834-9993-4993-b367-233aba28bc35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=281533254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.281533254
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_random.3631265286
Short name T743
Test name
Test status
Simulation time 3256967033 ps
CPU time 73.57 seconds
Started Mar 19 03:21:20 PM PDT 24
Finished Mar 19 03:22:33 PM PDT 24
Peak memory 223112 kb
Host smart-c895cbd4-7936-43ad-8e95-f8b4b56c9ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631265286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.3631265286
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.3406919700
Short name T105
Test name
Test status
Simulation time 6856313476 ps
CPU time 44 seconds
Started Mar 19 03:21:29 PM PDT 24
Finished Mar 19 03:22:13 PM PDT 24
Peak memory 237280 kb
Host smart-ff1132ba-ca95-4e50-8b04-abc836118753
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406919700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.3406919700
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.4280973787
Short name T593
Test name
Test status
Simulation time 63507811 ps
CPU time 3.31 seconds
Started Mar 19 03:21:18 PM PDT 24
Finished Mar 19 03:21:21 PM PDT 24
Peak memory 207960 kb
Host smart-c2119edd-73bb-4827-9a91-cf6e56a34bc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280973787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.4280973787
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.869166189
Short name T465
Test name
Test status
Simulation time 287889310 ps
CPU time 3.05 seconds
Started Mar 19 03:21:23 PM PDT 24
Finished Mar 19 03:21:26 PM PDT 24
Peak memory 207300 kb
Host smart-fdcddf96-bb65-4d8e-ae62-720b18b7b1fe
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=869166189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.869166189
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.3093757223
Short name T136
Test name
Test status
Simulation time 116452506 ps
CPU time 4.3 seconds
Started Mar 19 03:21:18 PM PDT 24
Finished Mar 19 03:21:22 PM PDT 24
Peak memory 208988 kb
Host smart-09bbba37-f8ef-475c-9581-b28aba18b3ed
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3093757223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.3093757223
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.1610521132
Short name T292
Test name
Test status
Simulation time 126327838 ps
CPU time 4.69 seconds
Started Mar 19 03:21:21 PM PDT 24
Finished Mar 19 03:21:26 PM PDT 24
Peak memory 208792 kb
Host smart-be232c59-0244-4eda-8276-64d3b065d988
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610521132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.1610521132
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_smoke.3000426700
Short name T663
Test name
Test status
Simulation time 25799174 ps
CPU time 1.95 seconds
Started Mar 19 03:21:19 PM PDT 24
Finished Mar 19 03:21:21 PM PDT 24
Peak memory 208812 kb
Host smart-c009faeb-9593-47e2-9eac-cb48011042b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000426700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.3000426700
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.3771829419
Short name T722
Test name
Test status
Simulation time 1173121202 ps
CPU time 12.86 seconds
Started Mar 19 03:21:21 PM PDT 24
Finished Mar 19 03:21:34 PM PDT 24
Peak memory 221644 kb
Host smart-469d5afc-95d5-4859-aff4-5aa80c79771c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3771829419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.3771829419
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_stress_all_with_rand_reset.2542482059
Short name T200
Test name
Test status
Simulation time 457397373 ps
CPU time 16.32 seconds
Started Mar 19 03:21:25 PM PDT 24
Finished Mar 19 03:21:41 PM PDT 24
Peak memory 223008 kb
Host smart-dfaf99c9-d91f-4447-8583-ba9c6f216369
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2542482059 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all_with_rand_reset.2542482059
Directory /workspace/4.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.2976477165
Short name T895
Test name
Test status
Simulation time 608334395 ps
CPU time 9.08 seconds
Started Mar 19 03:21:24 PM PDT 24
Finished Mar 19 03:21:33 PM PDT 24
Peak memory 209788 kb
Host smart-839d8a57-ae56-47f6-8b37-bd677fced506
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976477165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.2976477165
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.3794870077
Short name T661
Test name
Test status
Simulation time 30893391 ps
CPU time 2.03 seconds
Started Mar 19 03:21:25 PM PDT 24
Finished Mar 19 03:21:27 PM PDT 24
Peak memory 210528 kb
Host smart-6561c9a3-d5aa-448b-b365-ddd8c20801a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3794870077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.3794870077
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.576602357
Short name T612
Test name
Test status
Simulation time 60488651 ps
CPU time 0.82 seconds
Started Mar 19 03:22:56 PM PDT 24
Finished Mar 19 03:22:56 PM PDT 24
Peak memory 206364 kb
Host smart-3070b7c9-651b-40c2-9e19-9d07a8d317e6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576602357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.576602357
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.1643321321
Short name T146
Test name
Test status
Simulation time 31568292 ps
CPU time 2.23 seconds
Started Mar 19 03:22:57 PM PDT 24
Finished Mar 19 03:22:59 PM PDT 24
Peak memory 208816 kb
Host smart-271ab3d9-f652-420d-8c03-fbe54a30086e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1643321321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.1643321321
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.1580980863
Short name T495
Test name
Test status
Simulation time 987699296 ps
CPU time 29.59 seconds
Started Mar 19 03:23:00 PM PDT 24
Finished Mar 19 03:23:30 PM PDT 24
Peak memory 214776 kb
Host smart-80a4b866-68ad-4813-8212-c1a020073bed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580980863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.1580980863
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.3618965907
Short name T259
Test name
Test status
Simulation time 414171539 ps
CPU time 12.37 seconds
Started Mar 19 03:23:03 PM PDT 24
Finished Mar 19 03:23:16 PM PDT 24
Peak memory 222344 kb
Host smart-2f1a49a7-10d2-4d46-a8bc-ed7386cf7890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3618965907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.3618965907
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.2483823208
Short name T153
Test name
Test status
Simulation time 851363282 ps
CPU time 11.34 seconds
Started Mar 19 03:23:04 PM PDT 24
Finished Mar 19 03:23:16 PM PDT 24
Peak memory 214836 kb
Host smart-93cf80b7-67d9-4ec9-811b-7b65d5a05c9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2483823208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.2483823208
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.3934785634
Short name T308
Test name
Test status
Simulation time 634975021 ps
CPU time 6.03 seconds
Started Mar 19 03:22:57 PM PDT 24
Finished Mar 19 03:23:03 PM PDT 24
Peak memory 214832 kb
Host smart-ca0f1a2d-9a50-44af-bcbb-b1c26ee999ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3934785634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.3934785634
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.2216496817
Short name T541
Test name
Test status
Simulation time 516611660 ps
CPU time 6.04 seconds
Started Mar 19 03:22:56 PM PDT 24
Finished Mar 19 03:23:02 PM PDT 24
Peak memory 208472 kb
Host smart-af8e20cd-19f1-4c07-b246-a7987681e08a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216496817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.2216496817
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.390468816
Short name T660
Test name
Test status
Simulation time 62834034 ps
CPU time 3.48 seconds
Started Mar 19 03:23:04 PM PDT 24
Finished Mar 19 03:23:07 PM PDT 24
Peak memory 207324 kb
Host smart-74132cd4-74fe-42ce-b18b-6a175d348654
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390468816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.390468816
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.1796873647
Short name T682
Test name
Test status
Simulation time 343820847 ps
CPU time 4.96 seconds
Started Mar 19 03:23:05 PM PDT 24
Finished Mar 19 03:23:10 PM PDT 24
Peak memory 209268 kb
Host smart-9e0ba13a-5913-41c8-b583-092f091e2256
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796873647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.1796873647
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.479044273
Short name T702
Test name
Test status
Simulation time 73931834 ps
CPU time 1.75 seconds
Started Mar 19 03:23:04 PM PDT 24
Finished Mar 19 03:23:06 PM PDT 24
Peak memory 207268 kb
Host smart-2785eede-a2f5-478b-a583-4e51bdf0916e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=479044273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.479044273
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.971124946
Short name T542
Test name
Test status
Simulation time 86026596 ps
CPU time 3.9 seconds
Started Mar 19 03:22:58 PM PDT 24
Finished Mar 19 03:23:03 PM PDT 24
Peak memory 210796 kb
Host smart-06a8f26a-1418-4e44-afe6-53d275a94b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=971124946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.971124946
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.1944101339
Short name T402
Test name
Test status
Simulation time 77445129 ps
CPU time 2.3 seconds
Started Mar 19 03:22:52 PM PDT 24
Finished Mar 19 03:22:55 PM PDT 24
Peak memory 207184 kb
Host smart-e4cb17b6-0b74-461a-a7fc-3f1f9b7b848e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1944101339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.1944101339
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.619732705
Short name T753
Test name
Test status
Simulation time 269577746 ps
CPU time 8.33 seconds
Started Mar 19 03:23:17 PM PDT 24
Finished Mar 19 03:23:26 PM PDT 24
Peak memory 207280 kb
Host smart-308096e1-dc61-4a34-a586-cfb6a70aee39
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619732705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.619732705
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.3004711831
Short name T649
Test name
Test status
Simulation time 641139907 ps
CPU time 3.8 seconds
Started Mar 19 03:23:02 PM PDT 24
Finished Mar 19 03:23:06 PM PDT 24
Peak memory 207736 kb
Host smart-b96a891a-c38a-4e32-8e16-0e04c4120a33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004711831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.3004711831
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.82749603
Short name T18
Test name
Test status
Simulation time 275491664 ps
CPU time 2.05 seconds
Started Mar 19 03:22:52 PM PDT 24
Finished Mar 19 03:22:54 PM PDT 24
Peak memory 210240 kb
Host smart-3fb365cc-ec09-4c02-b5fc-2d42012e878c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82749603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.82749603
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.3462282793
Short name T645
Test name
Test status
Simulation time 124271078 ps
CPU time 0.89 seconds
Started Mar 19 03:22:57 PM PDT 24
Finished Mar 19 03:22:58 PM PDT 24
Peak memory 206424 kb
Host smart-86abdbae-d6fb-4ae3-b166-68bab1c90b75
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3462282793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.3462282793
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.2026283168
Short name T283
Test name
Test status
Simulation time 250484779 ps
CPU time 3.32 seconds
Started Mar 19 03:22:59 PM PDT 24
Finished Mar 19 03:23:03 PM PDT 24
Peak memory 223076 kb
Host smart-88a3d127-7422-4173-815b-308d612e5408
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2026283168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.2026283168
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.498792488
Short name T641
Test name
Test status
Simulation time 7140803800 ps
CPU time 54.77 seconds
Started Mar 19 03:23:00 PM PDT 24
Finished Mar 19 03:23:56 PM PDT 24
Peak memory 223484 kb
Host smart-e54584d1-d8b1-4cc9-891e-93d9c10da1a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498792488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.498792488
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.2324648004
Short name T679
Test name
Test status
Simulation time 204551812 ps
CPU time 2.55 seconds
Started Mar 19 03:23:09 PM PDT 24
Finished Mar 19 03:23:12 PM PDT 24
Peak memory 214776 kb
Host smart-5c15361d-8441-4388-a193-50f029106d73
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2324648004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.2324648004
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.1240753577
Short name T548
Test name
Test status
Simulation time 236427991 ps
CPU time 7.84 seconds
Started Mar 19 03:23:03 PM PDT 24
Finished Mar 19 03:23:12 PM PDT 24
Peak memory 214864 kb
Host smart-2ba0d2c4-06ae-4b89-a553-29ce15cb83a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1240753577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.1240753577
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.1110966964
Short name T1
Test name
Test status
Simulation time 116384233 ps
CPU time 2.64 seconds
Started Mar 19 03:22:55 PM PDT 24
Finished Mar 19 03:22:57 PM PDT 24
Peak memory 211632 kb
Host smart-4ec072bb-0625-44f2-bb33-012addae40b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110966964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.1110966964
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.3140985952
Short name T510
Test name
Test status
Simulation time 42216835 ps
CPU time 2.52 seconds
Started Mar 19 03:23:16 PM PDT 24
Finished Mar 19 03:23:18 PM PDT 24
Peak memory 220776 kb
Host smart-7d099331-89c3-43b3-a97e-52f15333be39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140985952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.3140985952
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.3708908580
Short name T332
Test name
Test status
Simulation time 541101910 ps
CPU time 3.66 seconds
Started Mar 19 03:23:10 PM PDT 24
Finished Mar 19 03:23:14 PM PDT 24
Peak memory 214788 kb
Host smart-305b94d7-b836-4aa0-9097-4499edad971e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708908580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.3708908580
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.2089605817
Short name T811
Test name
Test status
Simulation time 1519299048 ps
CPU time 4.76 seconds
Started Mar 19 03:23:01 PM PDT 24
Finished Mar 19 03:23:05 PM PDT 24
Peak memory 207240 kb
Host smart-94a9ecbc-0533-4fb1-9f6a-b8f9cf5a2d46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2089605817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.2089605817
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.3567290336
Short name T544
Test name
Test status
Simulation time 98692810 ps
CPU time 4.36 seconds
Started Mar 19 03:23:02 PM PDT 24
Finished Mar 19 03:23:06 PM PDT 24
Peak memory 209072 kb
Host smart-108f51bf-ccb1-4fb9-a4f1-41af641725ea
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3567290336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.3567290336
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.2670519772
Short name T80
Test name
Test status
Simulation time 98623087 ps
CPU time 2.35 seconds
Started Mar 19 03:23:10 PM PDT 24
Finished Mar 19 03:23:12 PM PDT 24
Peak memory 207308 kb
Host smart-72c0d0e9-820c-463d-a928-ebd7d8ab93fd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2670519772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.2670519772
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.154049793
Short name T706
Test name
Test status
Simulation time 297694179 ps
CPU time 9.68 seconds
Started Mar 19 03:23:08 PM PDT 24
Finished Mar 19 03:23:18 PM PDT 24
Peak memory 208932 kb
Host smart-b6a130c0-b52f-4eec-90fe-6d20870bceca
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154049793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.154049793
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.600980141
Short name T531
Test name
Test status
Simulation time 23230987 ps
CPU time 1.85 seconds
Started Mar 19 03:23:01 PM PDT 24
Finished Mar 19 03:23:03 PM PDT 24
Peak memory 210612 kb
Host smart-87157900-87ca-43c8-a410-8bc244846732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=600980141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.600980141
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.2090706515
Short name T650
Test name
Test status
Simulation time 275375295 ps
CPU time 3.36 seconds
Started Mar 19 03:22:58 PM PDT 24
Finished Mar 19 03:23:02 PM PDT 24
Peak memory 209092 kb
Host smart-1e05b73a-3d0a-4ee8-83e2-41092c4c8829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2090706515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.2090706515
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.236529851
Short name T239
Test name
Test status
Simulation time 976301457 ps
CPU time 25.44 seconds
Started Mar 19 03:22:58 PM PDT 24
Finished Mar 19 03:23:25 PM PDT 24
Peak memory 216228 kb
Host smart-99520834-19d2-488b-a080-b8536f76080b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=236529851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.236529851
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.3579219421
Short name T648
Test name
Test status
Simulation time 931654869 ps
CPU time 10 seconds
Started Mar 19 03:23:04 PM PDT 24
Finished Mar 19 03:23:14 PM PDT 24
Peak memory 220048 kb
Host smart-d632f931-1af9-4f7f-93a7-d3f07ba1bb82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3579219421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.3579219421
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.1086460222
Short name T831
Test name
Test status
Simulation time 114088608 ps
CPU time 1.67 seconds
Started Mar 19 03:23:04 PM PDT 24
Finished Mar 19 03:23:06 PM PDT 24
Peak memory 210396 kb
Host smart-3fe4ebd8-a93e-49dc-badb-5a7613360fde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1086460222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.1086460222
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.1728968070
Short name T631
Test name
Test status
Simulation time 35185093 ps
CPU time 0.96 seconds
Started Mar 19 03:23:10 PM PDT 24
Finished Mar 19 03:23:12 PM PDT 24
Peak memory 206596 kb
Host smart-8856f9c3-8aa5-4273-9d6f-dca209bc71dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728968070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.1728968070
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.3562148154
Short name T38
Test name
Test status
Simulation time 354809704 ps
CPU time 4.49 seconds
Started Mar 19 03:23:10 PM PDT 24
Finished Mar 19 03:23:14 PM PDT 24
Peak memory 209428 kb
Host smart-887b3a04-5a2c-4aae-ae27-3a7eb1b7f070
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3562148154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.3562148154
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.879286051
Short name T75
Test name
Test status
Simulation time 1444335569 ps
CPU time 16.84 seconds
Started Mar 19 03:23:06 PM PDT 24
Finished Mar 19 03:23:23 PM PDT 24
Peak memory 209484 kb
Host smart-db9de6d7-dcc0-42cb-8657-3cb35fe85b7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=879286051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.879286051
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.2287673840
Short name T302
Test name
Test status
Simulation time 188128575 ps
CPU time 4.89 seconds
Started Mar 19 03:22:59 PM PDT 24
Finished Mar 19 03:23:04 PM PDT 24
Peak memory 209268 kb
Host smart-92f99e66-1f9f-45a5-a590-5235ee2df7d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287673840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.2287673840
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.223418025
Short name T882
Test name
Test status
Simulation time 1288476038 ps
CPU time 11.64 seconds
Started Mar 19 03:23:04 PM PDT 24
Finished Mar 19 03:23:16 PM PDT 24
Peak memory 222860 kb
Host smart-f59c6326-97e5-4b43-b99e-3e82e096738a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223418025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.223418025
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.4203223839
Short name T266
Test name
Test status
Simulation time 62764142 ps
CPU time 3.53 seconds
Started Mar 19 03:22:59 PM PDT 24
Finished Mar 19 03:23:03 PM PDT 24
Peak memory 214840 kb
Host smart-29226890-eb6e-4e58-b755-f01cd89e072a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4203223839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.4203223839
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.2255019860
Short name T532
Test name
Test status
Simulation time 470963746 ps
CPU time 4.29 seconds
Started Mar 19 03:22:57 PM PDT 24
Finished Mar 19 03:23:02 PM PDT 24
Peak memory 208292 kb
Host smart-cc6a71fd-ca5b-49e7-9057-77908edd3c03
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2255019860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.2255019860
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.2079643143
Short name T620
Test name
Test status
Simulation time 116420729 ps
CPU time 2.76 seconds
Started Mar 19 03:23:08 PM PDT 24
Finished Mar 19 03:23:11 PM PDT 24
Peak memory 208860 kb
Host smart-f4d40265-bdb9-4a09-b878-662cc83fba3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2079643143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.2079643143
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.3579898998
Short name T742
Test name
Test status
Simulation time 217799856 ps
CPU time 6.89 seconds
Started Mar 19 03:23:10 PM PDT 24
Finished Mar 19 03:23:17 PM PDT 24
Peak memory 209124 kb
Host smart-bec895e1-6576-4ada-84eb-ad48055de7da
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3579898998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.3579898998
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.2184591422
Short name T77
Test name
Test status
Simulation time 140495854 ps
CPU time 2.41 seconds
Started Mar 19 03:22:58 PM PDT 24
Finished Mar 19 03:23:01 PM PDT 24
Peak memory 209072 kb
Host smart-58dd7c1c-c847-4a6f-b862-ad5dea18ebca
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2184591422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.2184591422
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.896653230
Short name T439
Test name
Test status
Simulation time 134195108 ps
CPU time 4.81 seconds
Started Mar 19 03:23:10 PM PDT 24
Finished Mar 19 03:23:16 PM PDT 24
Peak memory 208764 kb
Host smart-e83c1a87-e76b-4e41-955a-0900bf56a930
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896653230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.896653230
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.2085642941
Short name T505
Test name
Test status
Simulation time 292664701 ps
CPU time 3.54 seconds
Started Mar 19 03:23:11 PM PDT 24
Finished Mar 19 03:23:15 PM PDT 24
Peak memory 208576 kb
Host smart-29981910-c430-4696-8146-fc17fcc458f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085642941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.2085642941
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.2383694315
Short name T204
Test name
Test status
Simulation time 90176323 ps
CPU time 3.66 seconds
Started Mar 19 03:22:59 PM PDT 24
Finished Mar 19 03:23:03 PM PDT 24
Peak memory 208724 kb
Host smart-78499b4e-7d72-43d0-a39b-226911e8ded3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383694315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.2383694315
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.3333558071
Short name T483
Test name
Test status
Simulation time 233597446 ps
CPU time 5.16 seconds
Started Mar 19 03:23:02 PM PDT 24
Finished Mar 19 03:23:08 PM PDT 24
Peak memory 214796 kb
Host smart-f1d1e956-1f74-46d1-999c-58bba13c59a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3333558071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.3333558071
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.839217847
Short name T603
Test name
Test status
Simulation time 336161376 ps
CPU time 3.55 seconds
Started Mar 19 03:23:08 PM PDT 24
Finished Mar 19 03:23:11 PM PDT 24
Peak memory 211328 kb
Host smart-a5981103-be65-4432-8f1e-e165049ec130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=839217847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.839217847
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.980790656
Short name T872
Test name
Test status
Simulation time 10725660 ps
CPU time 0.72 seconds
Started Mar 19 03:23:04 PM PDT 24
Finished Mar 19 03:23:05 PM PDT 24
Peak memory 206452 kb
Host smart-996633b2-79f9-458d-bd8d-caf2bf3098db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=980790656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.980790656
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.23828401
Short name T154
Test name
Test status
Simulation time 37902124 ps
CPU time 3.12 seconds
Started Mar 19 03:23:12 PM PDT 24
Finished Mar 19 03:23:16 PM PDT 24
Peak memory 216120 kb
Host smart-0d3a0439-bff5-4057-9f2a-3c2e690bb5e8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=23828401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.23828401
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.1209461741
Short name T751
Test name
Test status
Simulation time 64634119 ps
CPU time 1.91 seconds
Started Mar 19 03:23:10 PM PDT 24
Finished Mar 19 03:23:13 PM PDT 24
Peak memory 214892 kb
Host smart-cd6cc725-03d9-447a-b393-8a2aea8dc4bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209461741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.1209461741
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.1331711025
Short name T711
Test name
Test status
Simulation time 523388270 ps
CPU time 3.71 seconds
Started Mar 19 03:23:10 PM PDT 24
Finished Mar 19 03:23:14 PM PDT 24
Peak memory 209792 kb
Host smart-dbd230a0-48a5-4990-8e52-aa17a353b9ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331711025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.1331711025
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.3615742807
Short name T260
Test name
Test status
Simulation time 854542080 ps
CPU time 7.79 seconds
Started Mar 19 03:23:10 PM PDT 24
Finished Mar 19 03:23:17 PM PDT 24
Peak memory 210604 kb
Host smart-bacb1b92-e408-499b-b8a0-649ae271f6f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3615742807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.3615742807
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.2585429642
Short name T16
Test name
Test status
Simulation time 27827304 ps
CPU time 2.14 seconds
Started Mar 19 03:23:12 PM PDT 24
Finished Mar 19 03:23:14 PM PDT 24
Peak memory 208764 kb
Host smart-34288828-b3ba-431f-a2b8-280faaf5b346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585429642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.2585429642
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.2030930543
Short name T543
Test name
Test status
Simulation time 80625077 ps
CPU time 4.3 seconds
Started Mar 19 03:23:11 PM PDT 24
Finished Mar 19 03:23:15 PM PDT 24
Peak memory 214704 kb
Host smart-9ae40ba8-a7d5-4f40-a2ab-1a6351b0ff71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2030930543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.2030930543
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.730078402
Short name T843
Test name
Test status
Simulation time 352967400 ps
CPU time 3.09 seconds
Started Mar 19 03:23:17 PM PDT 24
Finished Mar 19 03:23:20 PM PDT 24
Peak memory 207304 kb
Host smart-7ef0b930-8798-4184-a32f-25f0e632cfcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=730078402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.730078402
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.31645777
Short name T451
Test name
Test status
Simulation time 246276395 ps
CPU time 3.31 seconds
Started Mar 19 03:23:10 PM PDT 24
Finished Mar 19 03:23:13 PM PDT 24
Peak memory 207252 kb
Host smart-ee57f808-0e12-462d-bc18-ce9b6c0fc2c5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31645777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.31645777
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.1645704724
Short name T506
Test name
Test status
Simulation time 93397557 ps
CPU time 4.07 seconds
Started Mar 19 03:23:08 PM PDT 24
Finished Mar 19 03:23:13 PM PDT 24
Peak memory 207960 kb
Host smart-47e526fc-d4de-4b9a-9972-f8ae45f6ea27
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645704724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.1645704724
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.1907969162
Short name T263
Test name
Test status
Simulation time 2290091338 ps
CPU time 19.28 seconds
Started Mar 19 03:23:13 PM PDT 24
Finished Mar 19 03:23:33 PM PDT 24
Peak memory 209356 kb
Host smart-a793b732-e402-4161-9f61-338de98a54f5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1907969162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.1907969162
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.1672211085
Short name T509
Test name
Test status
Simulation time 83028690 ps
CPU time 2.32 seconds
Started Mar 19 03:23:10 PM PDT 24
Finished Mar 19 03:23:12 PM PDT 24
Peak memory 208444 kb
Host smart-539a06d1-a634-4a48-bade-b07d5dbe6a75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1672211085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.1672211085
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.1784331028
Short name T790
Test name
Test status
Simulation time 717342654 ps
CPU time 5.4 seconds
Started Mar 19 03:23:03 PM PDT 24
Finished Mar 19 03:23:08 PM PDT 24
Peak memory 207160 kb
Host smart-5028ab65-8ce6-42bb-97e8-2d03b0246069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784331028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.1784331028
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.4273824127
Short name T235
Test name
Test status
Simulation time 1000020307 ps
CPU time 21.31 seconds
Started Mar 19 03:23:09 PM PDT 24
Finished Mar 19 03:23:31 PM PDT 24
Peak memory 217708 kb
Host smart-33e014eb-6d9d-4720-9e2d-666d6073101b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273824127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.4273824127
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.3368028999
Short name T678
Test name
Test status
Simulation time 168333110 ps
CPU time 2.84 seconds
Started Mar 19 03:23:12 PM PDT 24
Finished Mar 19 03:23:15 PM PDT 24
Peak memory 208768 kb
Host smart-1fb5c2ee-da17-4be3-b7d7-c3a89baace55
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3368028999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.3368028999
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.1616120229
Short name T479
Test name
Test status
Simulation time 578496636 ps
CPU time 3.74 seconds
Started Mar 19 03:23:10 PM PDT 24
Finished Mar 19 03:23:14 PM PDT 24
Peak memory 210560 kb
Host smart-b093423f-3890-4e31-8179-362dd8d783c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1616120229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.1616120229
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.242563528
Short name T681
Test name
Test status
Simulation time 37418307 ps
CPU time 0.81 seconds
Started Mar 19 03:23:08 PM PDT 24
Finished Mar 19 03:23:09 PM PDT 24
Peak memory 206344 kb
Host smart-516b9850-6abc-4f54-8aa5-667fe8c443aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=242563528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.242563528
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.2354628174
Short name T420
Test name
Test status
Simulation time 55235848 ps
CPU time 2.59 seconds
Started Mar 19 03:23:17 PM PDT 24
Finished Mar 19 03:23:20 PM PDT 24
Peak memory 214788 kb
Host smart-010ec58b-8503-44b9-aaf8-47bdcbddc0ad
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2354628174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.2354628174
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.46634830
Short name T45
Test name
Test status
Simulation time 242178002 ps
CPU time 3.19 seconds
Started Mar 19 03:23:08 PM PDT 24
Finished Mar 19 03:23:11 PM PDT 24
Peak memory 218912 kb
Host smart-8959fb02-522a-4c91-ac9e-df16659f1662
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=46634830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.46634830
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.359341422
Short name T710
Test name
Test status
Simulation time 215050359 ps
CPU time 8.15 seconds
Started Mar 19 03:23:18 PM PDT 24
Finished Mar 19 03:23:27 PM PDT 24
Peak memory 214796 kb
Host smart-6feae474-db7c-4974-aa62-5284c1e5f97f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359341422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.359341422
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.1486252750
Short name T698
Test name
Test status
Simulation time 152736388 ps
CPU time 2.87 seconds
Started Mar 19 03:23:12 PM PDT 24
Finished Mar 19 03:23:16 PM PDT 24
Peak memory 206632 kb
Host smart-308921bc-dddc-42c0-b6f0-30332b063305
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486252750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.1486252750
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.2897844013
Short name T729
Test name
Test status
Simulation time 130042076 ps
CPU time 2.68 seconds
Started Mar 19 03:23:18 PM PDT 24
Finished Mar 19 03:23:21 PM PDT 24
Peak memory 208608 kb
Host smart-17bd5210-6713-42c7-b41d-6f1598b7031b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2897844013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.2897844013
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.3442378628
Short name T616
Test name
Test status
Simulation time 131875885 ps
CPU time 4.83 seconds
Started Mar 19 03:23:09 PM PDT 24
Finished Mar 19 03:23:14 PM PDT 24
Peak memory 209016 kb
Host smart-0eba3b4d-d01d-416b-a4e9-632b89c6e0c7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442378628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.3442378628
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.3942828278
Short name T462
Test name
Test status
Simulation time 3035706867 ps
CPU time 56.55 seconds
Started Mar 19 03:23:09 PM PDT 24
Finished Mar 19 03:24:06 PM PDT 24
Peak memory 208656 kb
Host smart-166b9ed5-9e65-4359-a39a-6d689addd3a9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942828278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.3942828278
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.1827773787
Short name T107
Test name
Test status
Simulation time 676196940 ps
CPU time 4.49 seconds
Started Mar 19 03:23:09 PM PDT 24
Finished Mar 19 03:23:14 PM PDT 24
Peak memory 208684 kb
Host smart-ff439c74-b40a-410a-a585-f1e93a516e5a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1827773787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.1827773787
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.746912364
Short name T217
Test name
Test status
Simulation time 259885526 ps
CPU time 4.06 seconds
Started Mar 19 03:23:09 PM PDT 24
Finished Mar 19 03:23:13 PM PDT 24
Peak memory 210420 kb
Host smart-26dcc6cb-997f-4afe-9f3c-2639ef02411b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746912364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.746912364
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.3676437290
Short name T540
Test name
Test status
Simulation time 47317927 ps
CPU time 2.37 seconds
Started Mar 19 03:23:09 PM PDT 24
Finished Mar 19 03:23:11 PM PDT 24
Peak memory 206652 kb
Host smart-6f1bf3a3-c130-4207-aa28-7c3c6de46390
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3676437290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.3676437290
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.515271272
Short name T70
Test name
Test status
Simulation time 1195298851 ps
CPU time 16.61 seconds
Started Mar 19 03:23:14 PM PDT 24
Finished Mar 19 03:23:31 PM PDT 24
Peak memory 222964 kb
Host smart-64559e20-2737-46c1-aa8a-cf1fc3da5717
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515271272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.515271272
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.41780759
Short name T889
Test name
Test status
Simulation time 323239409 ps
CPU time 8.77 seconds
Started Mar 19 03:23:11 PM PDT 24
Finished Mar 19 03:23:20 PM PDT 24
Peak memory 209632 kb
Host smart-f27af6d5-5dbb-4ddc-818b-a041c0b726bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=41780759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.41780759
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.4278505984
Short name T180
Test name
Test status
Simulation time 136759268 ps
CPU time 2.48 seconds
Started Mar 19 03:23:10 PM PDT 24
Finished Mar 19 03:23:12 PM PDT 24
Peak memory 210896 kb
Host smart-003342d7-b6db-43a5-b316-bfcaf673f7ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4278505984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.4278505984
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.2400963277
Short name T778
Test name
Test status
Simulation time 13282236 ps
CPU time 0.77 seconds
Started Mar 19 03:23:39 PM PDT 24
Finished Mar 19 03:23:40 PM PDT 24
Peak memory 206360 kb
Host smart-16ebbb0a-4ebb-40b0-b565-2366ee3219cb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400963277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.2400963277
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.2672069387
Short name T410
Test name
Test status
Simulation time 172910568 ps
CPU time 9.72 seconds
Started Mar 19 03:23:18 PM PDT 24
Finished Mar 19 03:23:28 PM PDT 24
Peak memory 215152 kb
Host smart-c371fd4d-8040-49bb-90b9-976497022034
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2672069387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.2672069387
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.3316912987
Short name T814
Test name
Test status
Simulation time 103156027 ps
CPU time 4.63 seconds
Started Mar 19 03:23:14 PM PDT 24
Finished Mar 19 03:23:19 PM PDT 24
Peak memory 210348 kb
Host smart-bb721113-50f8-4812-a20b-5c046d95462f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3316912987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.3316912987
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.1921083589
Short name T466
Test name
Test status
Simulation time 616338799 ps
CPU time 8.64 seconds
Started Mar 19 03:23:15 PM PDT 24
Finished Mar 19 03:23:24 PM PDT 24
Peak memory 214776 kb
Host smart-0b73a7bb-7abd-4975-9558-df8a7ab05fa7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921083589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.1921083589
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.2559208214
Short name T387
Test name
Test status
Simulation time 155261791 ps
CPU time 3.54 seconds
Started Mar 19 03:23:19 PM PDT 24
Finished Mar 19 03:23:22 PM PDT 24
Peak memory 210468 kb
Host smart-b3301f72-469a-4624-b7d3-8704bdb202cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2559208214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.2559208214
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.3765894531
Short name T352
Test name
Test status
Simulation time 563313382 ps
CPU time 8.29 seconds
Started Mar 19 03:23:29 PM PDT 24
Finished Mar 19 03:23:37 PM PDT 24
Peak memory 214748 kb
Host smart-8a506525-f132-41c9-8904-f18637a60b57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3765894531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.3765894531
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.1508500443
Short name T694
Test name
Test status
Simulation time 326808234 ps
CPU time 4.64 seconds
Started Mar 19 03:23:09 PM PDT 24
Finished Mar 19 03:23:14 PM PDT 24
Peak memory 208668 kb
Host smart-8026f212-d944-496a-8661-1a4dc0187ecb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1508500443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.1508500443
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.629754045
Short name T625
Test name
Test status
Simulation time 82879580 ps
CPU time 3.74 seconds
Started Mar 19 03:23:18 PM PDT 24
Finished Mar 19 03:23:22 PM PDT 24
Peak memory 209344 kb
Host smart-3ec37bad-5d36-4012-be0d-b3d0f292481e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629754045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.629754045
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.991081031
Short name T627
Test name
Test status
Simulation time 198948722 ps
CPU time 2.89 seconds
Started Mar 19 03:23:12 PM PDT 24
Finished Mar 19 03:23:15 PM PDT 24
Peak memory 207264 kb
Host smart-da195fbd-fe05-4ce2-9f25-a3f9d56ef6bc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=991081031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.991081031
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.3697283294
Short name T250
Test name
Test status
Simulation time 927344452 ps
CPU time 29.84 seconds
Started Mar 19 03:23:19 PM PDT 24
Finished Mar 19 03:23:49 PM PDT 24
Peak memory 208868 kb
Host smart-d2cd3c86-c9d2-4ca8-b2c5-e480e6a413dd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697283294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.3697283294
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.2286070286
Short name T750
Test name
Test status
Simulation time 87520359 ps
CPU time 3.54 seconds
Started Mar 19 03:23:19 PM PDT 24
Finished Mar 19 03:23:22 PM PDT 24
Peak memory 218888 kb
Host smart-eb1af3b4-2c06-4b93-8f90-8db3f7b3ac11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286070286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.2286070286
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.1579250350
Short name T224
Test name
Test status
Simulation time 213315590 ps
CPU time 6.64 seconds
Started Mar 19 03:23:04 PM PDT 24
Finished Mar 19 03:23:11 PM PDT 24
Peak memory 208936 kb
Host smart-cf59106c-2e2a-466d-bb35-df410858d2ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579250350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.1579250350
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.3144574729
Short name T243
Test name
Test status
Simulation time 1661035158 ps
CPU time 12.92 seconds
Started Mar 19 03:23:17 PM PDT 24
Finished Mar 19 03:23:31 PM PDT 24
Peak memory 216184 kb
Host smart-d0fb9195-2caf-443e-91ad-1bd8ccb5499c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144574729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.3144574729
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.48029718
Short name T406
Test name
Test status
Simulation time 569451028 ps
CPU time 10.88 seconds
Started Mar 19 03:23:17 PM PDT 24
Finished Mar 19 03:23:28 PM PDT 24
Peak memory 210176 kb
Host smart-67235220-d8e3-4d75-8af2-98762f6f69ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48029718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.48029718
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.2400259524
Short name T163
Test name
Test status
Simulation time 48377022 ps
CPU time 2.2 seconds
Started Mar 19 03:23:17 PM PDT 24
Finished Mar 19 03:23:19 PM PDT 24
Peak memory 209992 kb
Host smart-c4948836-4d60-4044-acab-1a8117401abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400259524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.2400259524
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.2229825399
Short name T907
Test name
Test status
Simulation time 19927554 ps
CPU time 0.75 seconds
Started Mar 19 03:23:24 PM PDT 24
Finished Mar 19 03:23:25 PM PDT 24
Peak memory 206456 kb
Host smart-e9163588-8e38-4bef-94c8-ed1119244244
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229825399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.2229825399
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.86057975
Short name T390
Test name
Test status
Simulation time 103289683 ps
CPU time 3.74 seconds
Started Mar 19 03:23:18 PM PDT 24
Finished Mar 19 03:23:22 PM PDT 24
Peak memory 215916 kb
Host smart-f5c82a02-6ac2-4f11-b40a-1dda7ef24927
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=86057975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.86057975
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.2400536432
Short name T21
Test name
Test status
Simulation time 168995984 ps
CPU time 5.44 seconds
Started Mar 19 03:23:16 PM PDT 24
Finished Mar 19 03:23:22 PM PDT 24
Peak memory 222300 kb
Host smart-16ccd50f-1438-4fd9-b2a0-d1b419cbcf67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2400536432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.2400536432
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.940913136
Short name T315
Test name
Test status
Simulation time 69874057 ps
CPU time 1.65 seconds
Started Mar 19 03:23:23 PM PDT 24
Finished Mar 19 03:23:25 PM PDT 24
Peak memory 207816 kb
Host smart-f1c0b01a-4f55-45c1-9d0e-f92550a6be5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=940913136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.940913136
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.1248120644
Short name T256
Test name
Test status
Simulation time 322712404 ps
CPU time 2.86 seconds
Started Mar 19 03:23:23 PM PDT 24
Finished Mar 19 03:23:26 PM PDT 24
Peak memory 222884 kb
Host smart-d591cc82-4f9a-4caa-892a-bca5d1a54ad9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1248120644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.1248120644
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.276536400
Short name T515
Test name
Test status
Simulation time 36798920 ps
CPU time 2.23 seconds
Started Mar 19 03:23:17 PM PDT 24
Finished Mar 19 03:23:20 PM PDT 24
Peak memory 215024 kb
Host smart-6ada4f9b-ce3b-41b3-b570-01b5dcc23147
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276536400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.276536400
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.3661118492
Short name T705
Test name
Test status
Simulation time 141250180 ps
CPU time 4.47 seconds
Started Mar 19 03:23:14 PM PDT 24
Finished Mar 19 03:23:19 PM PDT 24
Peak memory 214688 kb
Host smart-b5742019-6688-4df2-878d-f2229017f01c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661118492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.3661118492
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.2567869139
Short name T730
Test name
Test status
Simulation time 56165813 ps
CPU time 2.2 seconds
Started Mar 19 03:23:18 PM PDT 24
Finished Mar 19 03:23:21 PM PDT 24
Peak memory 207240 kb
Host smart-db5b69cd-8e60-4889-ad53-e320265ad9da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2567869139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.2567869139
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.1106889524
Short name T351
Test name
Test status
Simulation time 1417859596 ps
CPU time 19.95 seconds
Started Mar 19 03:23:29 PM PDT 24
Finished Mar 19 03:23:49 PM PDT 24
Peak memory 208128 kb
Host smart-913761ff-9576-4920-a50a-6568f5453cd0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1106889524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.1106889524
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.2980151744
Short name T866
Test name
Test status
Simulation time 63106051 ps
CPU time 2.16 seconds
Started Mar 19 03:23:15 PM PDT 24
Finished Mar 19 03:23:18 PM PDT 24
Peak memory 209084 kb
Host smart-549fbae2-c434-490c-bb9a-524d61b96150
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2980151744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.2980151744
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.4028441403
Short name T461
Test name
Test status
Simulation time 96423761 ps
CPU time 3.48 seconds
Started Mar 19 03:23:18 PM PDT 24
Finished Mar 19 03:23:22 PM PDT 24
Peak memory 207320 kb
Host smart-6122bd89-0eec-4f77-8b7c-a4a1885a278a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4028441403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.4028441403
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.3108126015
Short name T213
Test name
Test status
Simulation time 59620692 ps
CPU time 1.57 seconds
Started Mar 19 03:23:19 PM PDT 24
Finished Mar 19 03:23:21 PM PDT 24
Peak memory 207908 kb
Host smart-137f29b6-c498-4b96-ad67-b70b8c5a7c95
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108126015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.3108126015
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.1629672063
Short name T667
Test name
Test status
Simulation time 54899694 ps
CPU time 2.73 seconds
Started Mar 19 03:23:17 PM PDT 24
Finished Mar 19 03:23:20 PM PDT 24
Peak memory 209084 kb
Host smart-91101009-23c7-407f-9f3a-1c13456356b6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629672063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.1629672063
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all_with_rand_reset.405793375
Short name T198
Test name
Test status
Simulation time 309370402 ps
CPU time 6.43 seconds
Started Mar 19 03:23:17 PM PDT 24
Finished Mar 19 03:23:24 PM PDT 24
Peak memory 222236 kb
Host smart-29e0f89b-276c-413a-925e-5f57c96f3824
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=405793375 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all_with_rand_reset.405793375
Directory /workspace/46.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.775452884
Short name T477
Test name
Test status
Simulation time 447273695 ps
CPU time 5.23 seconds
Started Mar 19 03:23:33 PM PDT 24
Finished Mar 19 03:23:38 PM PDT 24
Peak memory 210504 kb
Host smart-3aa867d4-80dc-4617-be86-ebbd1d0215c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=775452884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.775452884
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.1007101282
Short name T132
Test name
Test status
Simulation time 333628181 ps
CPU time 2.54 seconds
Started Mar 19 03:23:12 PM PDT 24
Finished Mar 19 03:23:15 PM PDT 24
Peak memory 210416 kb
Host smart-56e77ed5-48f1-4d88-9657-a1f8f6821eed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007101282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.1007101282
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.1607881381
Short name T665
Test name
Test status
Simulation time 11022449 ps
CPU time 0.71 seconds
Started Mar 19 03:23:18 PM PDT 24
Finished Mar 19 03:23:19 PM PDT 24
Peak memory 206436 kb
Host smart-0a25bd42-1192-4c47-99cc-9dffad53632d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607881381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.1607881381
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.2189046002
Short name T651
Test name
Test status
Simulation time 1039473341 ps
CPU time 15.04 seconds
Started Mar 19 03:23:19 PM PDT 24
Finished Mar 19 03:23:34 PM PDT 24
Peak memory 223364 kb
Host smart-fa8cd9df-0a1c-4670-887d-3e074c36312f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189046002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.2189046002
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.164834816
Short name T550
Test name
Test status
Simulation time 62714668 ps
CPU time 2.53 seconds
Started Mar 19 03:23:18 PM PDT 24
Finished Mar 19 03:23:21 PM PDT 24
Peak memory 214780 kb
Host smart-eb1e8a47-15ae-4811-95e1-b327e0d1cc5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=164834816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.164834816
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.1041924903
Short name T95
Test name
Test status
Simulation time 1612696686 ps
CPU time 42.67 seconds
Started Mar 19 03:23:13 PM PDT 24
Finished Mar 19 03:23:56 PM PDT 24
Peak memory 209532 kb
Host smart-f7149ff3-76a2-462b-a139-006a048c4c5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041924903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.1041924903
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.10093493
Short name T781
Test name
Test status
Simulation time 111883349 ps
CPU time 5.58 seconds
Started Mar 19 03:23:19 PM PDT 24
Finished Mar 19 03:23:24 PM PDT 24
Peak memory 222264 kb
Host smart-54ac433b-f680-4189-a186-59bcb2b6f227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10093493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.10093493
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.1858326407
Short name T6
Test name
Test status
Simulation time 126732140 ps
CPU time 4.12 seconds
Started Mar 19 03:23:19 PM PDT 24
Finished Mar 19 03:23:23 PM PDT 24
Peak memory 220124 kb
Host smart-f77555f8-9c90-4133-9bd9-4e85f93b461a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858326407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.1858326407
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.1165733155
Short name T226
Test name
Test status
Simulation time 1142467129 ps
CPU time 16.76 seconds
Started Mar 19 03:23:18 PM PDT 24
Finished Mar 19 03:23:35 PM PDT 24
Peak memory 208452 kb
Host smart-57627fc5-0d0b-4890-ae5f-e82b0f781cc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1165733155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.1165733155
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.748080584
Short name T404
Test name
Test status
Simulation time 123420925 ps
CPU time 2.52 seconds
Started Mar 19 03:23:25 PM PDT 24
Finished Mar 19 03:23:28 PM PDT 24
Peak memory 207148 kb
Host smart-1f6f2d8c-14a0-4c02-bdff-d9fb2733f2c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=748080584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.748080584
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.2863038635
Short name T759
Test name
Test status
Simulation time 121106831 ps
CPU time 4.34 seconds
Started Mar 19 03:23:18 PM PDT 24
Finished Mar 19 03:23:22 PM PDT 24
Peak memory 207300 kb
Host smart-953d6952-b411-40f3-8baf-f371c6f6c5b7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2863038635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.2863038635
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.4043051103
Short name T670
Test name
Test status
Simulation time 72039296 ps
CPU time 2.54 seconds
Started Mar 19 03:23:42 PM PDT 24
Finished Mar 19 03:23:45 PM PDT 24
Peak memory 208860 kb
Host smart-1b22d8a5-b4e3-4385-931c-60f81f25564a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4043051103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.4043051103
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.1764766548
Short name T14
Test name
Test status
Simulation time 967392562 ps
CPU time 31.85 seconds
Started Mar 19 03:23:17 PM PDT 24
Finished Mar 19 03:23:50 PM PDT 24
Peak memory 209416 kb
Host smart-ecc817b9-071a-45ca-b9d4-e54be5cde267
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764766548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.1764766548
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.2319112667
Short name T692
Test name
Test status
Simulation time 245439831 ps
CPU time 5.17 seconds
Started Mar 19 03:23:16 PM PDT 24
Finished Mar 19 03:23:22 PM PDT 24
Peak memory 210208 kb
Host smart-e65cd78f-ed50-484b-86fc-03a2a8adc1f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2319112667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.2319112667
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.193464017
Short name T609
Test name
Test status
Simulation time 2187273615 ps
CPU time 12.34 seconds
Started Mar 19 03:23:11 PM PDT 24
Finished Mar 19 03:23:24 PM PDT 24
Peak memory 208528 kb
Host smart-3c2533b8-11c5-4bdd-a862-0f160b1e0a20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=193464017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.193464017
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.4224662557
Short name T597
Test name
Test status
Simulation time 1920543169 ps
CPU time 16.48 seconds
Started Mar 19 03:23:15 PM PDT 24
Finished Mar 19 03:23:31 PM PDT 24
Peak memory 217368 kb
Host smart-ed147871-77d6-4d19-8e06-8856120758b1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4224662557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.4224662557
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.2071108203
Short name T676
Test name
Test status
Simulation time 131140761 ps
CPU time 6.37 seconds
Started Mar 19 03:23:18 PM PDT 24
Finished Mar 19 03:23:24 PM PDT 24
Peak memory 210996 kb
Host smart-3815acf6-6708-4c97-8551-99a245fc738d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2071108203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.2071108203
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.847171095
Short name T896
Test name
Test status
Simulation time 201285251 ps
CPU time 2.61 seconds
Started Mar 19 03:23:29 PM PDT 24
Finished Mar 19 03:23:31 PM PDT 24
Peak memory 210632 kb
Host smart-d64e5704-6074-4de1-a568-eed3a7554a12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847171095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.847171095
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.4128134999
Short name T79
Test name
Test status
Simulation time 17691646 ps
CPU time 0.79 seconds
Started Mar 19 03:23:40 PM PDT 24
Finished Mar 19 03:23:41 PM PDT 24
Peak memory 206460 kb
Host smart-90ec7f57-9f90-4aac-a930-1bd5fdc7da5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128134999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.4128134999
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.1573869891
Short name T514
Test name
Test status
Simulation time 1735848971 ps
CPU time 13.87 seconds
Started Mar 19 03:23:19 PM PDT 24
Finished Mar 19 03:23:33 PM PDT 24
Peak memory 222612 kb
Host smart-36bb23bb-1d96-40e1-b9c9-71f5262995da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1573869891 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.1573869891
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.1466822831
Short name T50
Test name
Test status
Simulation time 179183406 ps
CPU time 2.33 seconds
Started Mar 19 03:23:18 PM PDT 24
Finished Mar 19 03:23:20 PM PDT 24
Peak memory 208548 kb
Host smart-8a2c260a-8803-4d2c-8edc-3d27eda0b554
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1466822831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.1466822831
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.3857111790
Short name T93
Test name
Test status
Simulation time 83779105 ps
CPU time 4.49 seconds
Started Mar 19 03:23:18 PM PDT 24
Finished Mar 19 03:23:23 PM PDT 24
Peak memory 219056 kb
Host smart-9898d6c7-223b-44c0-a254-2e32af2a0509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3857111790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.3857111790
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.781824104
Short name T353
Test name
Test status
Simulation time 670458604 ps
CPU time 4.72 seconds
Started Mar 19 03:23:21 PM PDT 24
Finished Mar 19 03:23:26 PM PDT 24
Peak memory 222916 kb
Host smart-b8ebd751-1459-41cc-8692-ac488b92d0b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=781824104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.781824104
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_random.257795856
Short name T367
Test name
Test status
Simulation time 1869091088 ps
CPU time 20.76 seconds
Started Mar 19 03:23:15 PM PDT 24
Finished Mar 19 03:23:36 PM PDT 24
Peak memory 209936 kb
Host smart-68b6f905-acb3-4f32-aa84-fe5949445bf6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257795856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.257795856
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.1852259374
Short name T832
Test name
Test status
Simulation time 34169509 ps
CPU time 2.39 seconds
Started Mar 19 03:23:28 PM PDT 24
Finished Mar 19 03:23:30 PM PDT 24
Peak memory 209056 kb
Host smart-dc2d0c0e-4ed4-46e4-a1ed-af20521b2cfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1852259374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.1852259374
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.3539512595
Short name T229
Test name
Test status
Simulation time 1876552561 ps
CPU time 35.86 seconds
Started Mar 19 03:23:23 PM PDT 24
Finished Mar 19 03:23:59 PM PDT 24
Peak memory 208364 kb
Host smart-215af3ff-2605-435f-bdb8-e7da8a8e5149
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539512595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.3539512595
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.977906982
Short name T638
Test name
Test status
Simulation time 84088601 ps
CPU time 1.94 seconds
Started Mar 19 03:23:22 PM PDT 24
Finished Mar 19 03:23:24 PM PDT 24
Peak memory 207824 kb
Host smart-a073f9ce-51e3-4537-ae5b-d1417d090c70
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977906982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.977906982
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.3102881463
Short name T734
Test name
Test status
Simulation time 26927808 ps
CPU time 2.2 seconds
Started Mar 19 03:23:16 PM PDT 24
Finished Mar 19 03:23:18 PM PDT 24
Peak memory 209060 kb
Host smart-58dc5db5-fc1e-4396-be3f-f52aacfd9232
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102881463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.3102881463
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.1509268498
Short name T810
Test name
Test status
Simulation time 79064147 ps
CPU time 3.81 seconds
Started Mar 19 03:23:15 PM PDT 24
Finished Mar 19 03:23:19 PM PDT 24
Peak memory 209204 kb
Host smart-b3ba2209-88c3-41bc-aafb-346247d9d4de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1509268498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.1509268498
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.2946685077
Short name T628
Test name
Test status
Simulation time 109321608 ps
CPU time 3.16 seconds
Started Mar 19 03:23:28 PM PDT 24
Finished Mar 19 03:23:31 PM PDT 24
Peak memory 208728 kb
Host smart-6fbd8154-8602-44d6-ab93-c852b2c5ec10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946685077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.2946685077
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.8671953
Short name T54
Test name
Test status
Simulation time 296730506 ps
CPU time 14.32 seconds
Started Mar 19 03:23:54 PM PDT 24
Finished Mar 19 03:24:09 PM PDT 24
Peak memory 215580 kb
Host smart-648ebf5a-6ed8-4f9f-9cbd-ffa438cd7e3e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8671953 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.8671953
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.1930799844
Short name T571
Test name
Test status
Simulation time 3024858752 ps
CPU time 17.12 seconds
Started Mar 19 03:23:31 PM PDT 24
Finished Mar 19 03:23:49 PM PDT 24
Peak memory 218564 kb
Host smart-d1e38bd5-3491-466e-b265-49f9e9204bc0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930799844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.1930799844
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.786993517
Short name T393
Test name
Test status
Simulation time 468234439 ps
CPU time 6.85 seconds
Started Mar 19 03:23:30 PM PDT 24
Finished Mar 19 03:23:37 PM PDT 24
Peak memory 211400 kb
Host smart-45dfc398-72ea-4f18-aa45-b8bc7de7f2b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=786993517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.786993517
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.1550196690
Short name T100
Test name
Test status
Simulation time 82669882 ps
CPU time 1.07 seconds
Started Mar 19 03:23:26 PM PDT 24
Finished Mar 19 03:23:27 PM PDT 24
Peak memory 206584 kb
Host smart-60c5d1d5-f63b-4dc2-bca7-23e4f720e121
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550196690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.1550196690
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.2296447852
Short name T249
Test name
Test status
Simulation time 254247737 ps
CPU time 2.73 seconds
Started Mar 19 03:23:26 PM PDT 24
Finished Mar 19 03:23:29 PM PDT 24
Peak memory 214812 kb
Host smart-7c337179-f298-4c07-a7a5-3ea01abf00ea
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2296447852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.2296447852
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.965928713
Short name T9
Test name
Test status
Simulation time 1992568002 ps
CPU time 49.88 seconds
Started Mar 19 03:23:32 PM PDT 24
Finished Mar 19 03:24:22 PM PDT 24
Peak memory 223348 kb
Host smart-f6e71cf5-5414-4591-a020-49760d5320c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965928713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.965928713
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.1156160212
Short name T551
Test name
Test status
Simulation time 147724294 ps
CPU time 2.2 seconds
Started Mar 19 03:23:38 PM PDT 24
Finished Mar 19 03:23:40 PM PDT 24
Peak memory 209100 kb
Host smart-d480c8c1-0877-401d-8fad-29be1a1fc830
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1156160212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.1156160212
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.1411864498
Short name T769
Test name
Test status
Simulation time 209744832 ps
CPU time 3.98 seconds
Started Mar 19 03:23:35 PM PDT 24
Finished Mar 19 03:23:40 PM PDT 24
Peak memory 214804 kb
Host smart-4adbbc26-be93-4e8e-8597-bb704a251bc7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1411864498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.1411864498
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.28592373
Short name T254
Test name
Test status
Simulation time 508885263 ps
CPU time 7.31 seconds
Started Mar 19 03:23:37 PM PDT 24
Finished Mar 19 03:23:44 PM PDT 24
Peak memory 222920 kb
Host smart-a59b517f-4037-480b-ae46-662780e910bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=28592373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.28592373
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.3655560044
Short name T875
Test name
Test status
Simulation time 90999397 ps
CPU time 2.08 seconds
Started Mar 19 03:23:31 PM PDT 24
Finished Mar 19 03:23:33 PM PDT 24
Peak memory 206652 kb
Host smart-22ced132-d57f-4587-9202-ada1305f741b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655560044 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.3655560044
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.695977300
Short name T857
Test name
Test status
Simulation time 181001780 ps
CPU time 2.89 seconds
Started Mar 19 03:23:20 PM PDT 24
Finished Mar 19 03:23:23 PM PDT 24
Peak memory 208440 kb
Host smart-a3f4df49-e0ee-4265-8e02-8406b41eeda1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=695977300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.695977300
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.4016528904
Short name T784
Test name
Test status
Simulation time 114394855 ps
CPU time 4.25 seconds
Started Mar 19 03:23:38 PM PDT 24
Finished Mar 19 03:23:43 PM PDT 24
Peak memory 207040 kb
Host smart-dd78f724-cd9f-4939-a729-c681d3c9b409
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4016528904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.4016528904
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.3481159487
Short name T613
Test name
Test status
Simulation time 139719550 ps
CPU time 2.72 seconds
Started Mar 19 03:23:24 PM PDT 24
Finished Mar 19 03:23:27 PM PDT 24
Peak memory 209264 kb
Host smart-9819b3c5-1b3e-4e03-bb7c-4edd9bc3006d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3481159487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.3481159487
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.2885914813
Short name T765
Test name
Test status
Simulation time 724147018 ps
CPU time 5.51 seconds
Started Mar 19 03:23:40 PM PDT 24
Finished Mar 19 03:23:46 PM PDT 24
Peak memory 208368 kb
Host smart-9dc73800-98ba-4839-9983-4d9cd1f06d43
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885914813 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.2885914813
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.1241736653
Short name T493
Test name
Test status
Simulation time 155344639 ps
CPU time 3.1 seconds
Started Mar 19 03:23:46 PM PDT 24
Finished Mar 19 03:23:49 PM PDT 24
Peak memory 209524 kb
Host smart-04d5fdba-d2c6-4d1c-ad51-2be6023afc60
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1241736653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.1241736653
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.1651219385
Short name T752
Test name
Test status
Simulation time 74043529 ps
CPU time 1.77 seconds
Started Mar 19 03:23:33 PM PDT 24
Finished Mar 19 03:23:34 PM PDT 24
Peak memory 207192 kb
Host smart-38ebf299-67ea-4ba4-bb71-3f18e0c226ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651219385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.1651219385
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.3961077629
Short name T714
Test name
Test status
Simulation time 187001691 ps
CPU time 4.45 seconds
Started Mar 19 03:23:42 PM PDT 24
Finished Mar 19 03:23:46 PM PDT 24
Peak memory 208036 kb
Host smart-3de941da-4481-445e-89f3-5dd952b5dc76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961077629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.3961077629
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.1945324278
Short name T858
Test name
Test status
Simulation time 59646714 ps
CPU time 2.2 seconds
Started Mar 19 03:23:31 PM PDT 24
Finished Mar 19 03:23:34 PM PDT 24
Peak memory 210260 kb
Host smart-c9c25996-cb99-4b75-b476-470b5c3c0923
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1945324278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.1945324278
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.2216405421
Short name T492
Test name
Test status
Simulation time 15647499 ps
CPU time 0.72 seconds
Started Mar 19 03:21:24 PM PDT 24
Finished Mar 19 03:21:25 PM PDT 24
Peak memory 206384 kb
Host smart-6e095581-a5ac-4024-adae-0d81b36a13a5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216405421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.2216405421
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.2497499908
Short name T869
Test name
Test status
Simulation time 135618948 ps
CPU time 2.42 seconds
Started Mar 19 03:21:24 PM PDT 24
Finished Mar 19 03:21:26 PM PDT 24
Peak memory 214740 kb
Host smart-6f631584-ca4b-4b52-abaf-e320211dc52a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2497499908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.2497499908
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.3453383890
Short name T713
Test name
Test status
Simulation time 594965888 ps
CPU time 5.36 seconds
Started Mar 19 03:21:24 PM PDT 24
Finished Mar 19 03:21:30 PM PDT 24
Peak memory 219640 kb
Host smart-36c5f8c2-4a5a-4be7-a67a-c3bbd3c9a62a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3453383890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.3453383890
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.603385617
Short name T850
Test name
Test status
Simulation time 46175024 ps
CPU time 2.35 seconds
Started Mar 19 03:21:24 PM PDT 24
Finished Mar 19 03:21:27 PM PDT 24
Peak memory 209012 kb
Host smart-3c7aebbf-0c56-4643-b278-5420d48a939c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=603385617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.603385617
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.2392282752
Short name T322
Test name
Test status
Simulation time 1124788595 ps
CPU time 7.67 seconds
Started Mar 19 03:21:24 PM PDT 24
Finished Mar 19 03:21:32 PM PDT 24
Peak memory 222560 kb
Host smart-5a92b961-508b-4a3e-9a3d-aef964323ab6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2392282752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.2392282752
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.222037259
Short name T797
Test name
Test status
Simulation time 113866286 ps
CPU time 3.66 seconds
Started Mar 19 03:21:23 PM PDT 24
Finished Mar 19 03:21:27 PM PDT 24
Peak memory 210688 kb
Host smart-74d60562-0331-4228-8820-e8cf8e6bc86f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=222037259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.222037259
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.1329722657
Short name T587
Test name
Test status
Simulation time 120014740 ps
CPU time 2.49 seconds
Started Mar 19 03:21:24 PM PDT 24
Finished Mar 19 03:21:26 PM PDT 24
Peak memory 214908 kb
Host smart-a1eaa324-6903-4a91-a201-62670055cabc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1329722657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.1329722657
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.208668021
Short name T585
Test name
Test status
Simulation time 364121982 ps
CPU time 6.38 seconds
Started Mar 19 03:21:23 PM PDT 24
Finished Mar 19 03:21:30 PM PDT 24
Peak memory 207984 kb
Host smart-0ec8a990-afbe-457a-9edf-8f6aa667e53d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208668021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.208668021
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.752915040
Short name T223
Test name
Test status
Simulation time 1175197304 ps
CPU time 6.53 seconds
Started Mar 19 03:21:24 PM PDT 24
Finished Mar 19 03:21:31 PM PDT 24
Peak memory 209328 kb
Host smart-697dcf73-c647-43cb-9939-89c40f67e04e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752915040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.752915040
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.1351789285
Short name T847
Test name
Test status
Simulation time 822404560 ps
CPU time 5.09 seconds
Started Mar 19 03:21:21 PM PDT 24
Finished Mar 19 03:21:27 PM PDT 24
Peak memory 209432 kb
Host smart-63790496-6f75-4713-b41d-b303d648ccf2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1351789285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.1351789285
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.3639163867
Short name T576
Test name
Test status
Simulation time 110423988 ps
CPU time 3.82 seconds
Started Mar 19 03:21:25 PM PDT 24
Finished Mar 19 03:21:29 PM PDT 24
Peak memory 207356 kb
Host smart-17713324-6cb4-430b-a629-67fb4137bc9d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3639163867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.3639163867
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.3128202787
Short name T17
Test name
Test status
Simulation time 336516865 ps
CPU time 4.68 seconds
Started Mar 19 03:21:23 PM PDT 24
Finished Mar 19 03:21:28 PM PDT 24
Peak memory 208996 kb
Host smart-dfb5749d-24e1-47a2-ab65-7286ac4d8046
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3128202787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.3128202787
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.3977923868
Short name T557
Test name
Test status
Simulation time 235636074 ps
CPU time 3.23 seconds
Started Mar 19 03:21:23 PM PDT 24
Finished Mar 19 03:21:27 PM PDT 24
Peak memory 209788 kb
Host smart-4f2565eb-48ee-4262-afe5-70549538aace
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3977923868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.3977923868
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.3493046065
Short name T845
Test name
Test status
Simulation time 4487213318 ps
CPU time 10.95 seconds
Started Mar 19 03:21:22 PM PDT 24
Finished Mar 19 03:21:34 PM PDT 24
Peak memory 208380 kb
Host smart-5c72f279-eb7e-44f1-a1fb-605457b64de9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493046065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.3493046065
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.3568049810
Short name T687
Test name
Test status
Simulation time 765366907 ps
CPU time 20.75 seconds
Started Mar 19 03:21:24 PM PDT 24
Finished Mar 19 03:21:45 PM PDT 24
Peak memory 216948 kb
Host smart-13dbc6d5-225e-40a2-8baa-bc5784dfdd83
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568049810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.3568049810
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.1901272814
Short name T898
Test name
Test status
Simulation time 630060137 ps
CPU time 9.21 seconds
Started Mar 19 03:21:23 PM PDT 24
Finished Mar 19 03:21:33 PM PDT 24
Peak memory 208668 kb
Host smart-1d5db4b1-4d12-4f85-8981-2db0a5f86425
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1901272814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.1901272814
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.34532628
Short name T434
Test name
Test status
Simulation time 258607618 ps
CPU time 5.77 seconds
Started Mar 19 03:21:20 PM PDT 24
Finished Mar 19 03:21:26 PM PDT 24
Peak memory 210644 kb
Host smart-4f66d256-4d0e-40bb-9e00-5bd4da620acd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=34532628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.34532628
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.134912174
Short name T452
Test name
Test status
Simulation time 26362027 ps
CPU time 1.02 seconds
Started Mar 19 03:21:35 PM PDT 24
Finished Mar 19 03:21:36 PM PDT 24
Peak memory 206616 kb
Host smart-e4adb8b3-10fe-4677-a979-b728fa189e93
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=134912174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.134912174
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.1374747366
Short name T391
Test name
Test status
Simulation time 1004571230 ps
CPU time 11.91 seconds
Started Mar 19 03:21:21 PM PDT 24
Finished Mar 19 03:21:33 PM PDT 24
Peak memory 214832 kb
Host smart-fb8a2995-739c-42bf-89b6-0acc1e35abbc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1374747366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.1374747366
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.2551553867
Short name T528
Test name
Test status
Simulation time 700918258 ps
CPU time 13.6 seconds
Started Mar 19 03:21:25 PM PDT 24
Finished Mar 19 03:21:38 PM PDT 24
Peak memory 209644 kb
Host smart-0a516e0b-1f93-43e2-bf4b-5cfd3d356bf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2551553867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.2551553867
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.843465364
Short name T623
Test name
Test status
Simulation time 147273319 ps
CPU time 5.73 seconds
Started Mar 19 03:21:24 PM PDT 24
Finished Mar 19 03:21:30 PM PDT 24
Peak memory 220664 kb
Host smart-21d1187f-7f50-42e1-8e03-cb9334feb3a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843465364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.843465364
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_random.1619491626
Short name T347
Test name
Test status
Simulation time 521853778 ps
CPU time 10.77 seconds
Started Mar 19 03:21:28 PM PDT 24
Finished Mar 19 03:21:39 PM PDT 24
Peak memory 209604 kb
Host smart-07a340b6-b081-4d00-889f-5407f8d30394
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619491626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.1619491626
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.20852914
Short name T523
Test name
Test status
Simulation time 417224093 ps
CPU time 5.89 seconds
Started Mar 19 03:21:22 PM PDT 24
Finished Mar 19 03:21:28 PM PDT 24
Peak memory 207348 kb
Host smart-9ec3400e-3727-43c7-bc5b-6d8ced412eb5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=20852914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.20852914
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.475311670
Short name T748
Test name
Test status
Simulation time 591368402 ps
CPU time 3.47 seconds
Started Mar 19 03:21:27 PM PDT 24
Finished Mar 19 03:21:31 PM PDT 24
Peak memory 208920 kb
Host smart-7b68cf41-747c-4aea-9249-055b6ba5ca57
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=475311670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.475311670
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.1627568642
Short name T527
Test name
Test status
Simulation time 250408053 ps
CPU time 3.01 seconds
Started Mar 19 03:21:26 PM PDT 24
Finished Mar 19 03:21:29 PM PDT 24
Peak memory 208872 kb
Host smart-5deeae53-9f34-42e6-9176-7f65d5cd5fa7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627568642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.1627568642
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.1215521630
Short name T525
Test name
Test status
Simulation time 90920717 ps
CPU time 1.75 seconds
Started Mar 19 03:21:27 PM PDT 24
Finished Mar 19 03:21:29 PM PDT 24
Peak memory 207328 kb
Host smart-f32e5e72-2cd3-42cf-bb25-bf995e274bab
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1215521630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.1215521630
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.1051034814
Short name T321
Test name
Test status
Simulation time 530033473 ps
CPU time 3.42 seconds
Started Mar 19 03:21:23 PM PDT 24
Finished Mar 19 03:21:26 PM PDT 24
Peak memory 214732 kb
Host smart-81485cbf-ee4a-4601-bccd-a910e63a7c80
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051034814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.1051034814
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.2839038994
Short name T471
Test name
Test status
Simulation time 61742645 ps
CPU time 2.26 seconds
Started Mar 19 03:21:22 PM PDT 24
Finished Mar 19 03:21:25 PM PDT 24
Peak memory 207024 kb
Host smart-3b6f4eae-aa94-4009-8b51-bfffb0e676dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839038994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.2839038994
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.290360559
Short name T303
Test name
Test status
Simulation time 1809521219 ps
CPU time 8.98 seconds
Started Mar 19 03:21:25 PM PDT 24
Finished Mar 19 03:21:34 PM PDT 24
Peak memory 215424 kb
Host smart-48a858d6-17a5-4cc4-9877-5e48a2697ea9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=290360559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.290360559
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_stress_all_with_rand_reset.942842888
Short name T498
Test name
Test status
Simulation time 118642649 ps
CPU time 7.84 seconds
Started Mar 19 03:21:38 PM PDT 24
Finished Mar 19 03:21:46 PM PDT 24
Peak memory 220152 kb
Host smart-4a31565e-332d-4d01-8446-479c35a98a08
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=942842888 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all_with_rand_reset.942842888
Directory /workspace/6.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.3531472160
Short name T86
Test name
Test status
Simulation time 64445981 ps
CPU time 3.11 seconds
Started Mar 19 03:21:24 PM PDT 24
Finished Mar 19 03:21:28 PM PDT 24
Peak memory 210448 kb
Host smart-0c3a50a1-288f-4529-a483-956e123375ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531472160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.3531472160
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.310673230
Short name T396
Test name
Test status
Simulation time 249731928 ps
CPU time 2.11 seconds
Started Mar 19 03:21:23 PM PDT 24
Finished Mar 19 03:21:26 PM PDT 24
Peak memory 210816 kb
Host smart-8ed523fe-d4f2-467b-9c66-a10fadd915d8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=310673230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.310673230
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.939016187
Short name T429
Test name
Test status
Simulation time 37123247 ps
CPU time 0.72 seconds
Started Mar 19 03:21:44 PM PDT 24
Finished Mar 19 03:21:45 PM PDT 24
Peak memory 206376 kb
Host smart-63b9d9d4-1266-484b-bbfd-da6c4aebfc2a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939016187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.939016187
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.271974162
Short name T109
Test name
Test status
Simulation time 306480471 ps
CPU time 5.54 seconds
Started Mar 19 03:21:40 PM PDT 24
Finished Mar 19 03:21:46 PM PDT 24
Peak memory 214704 kb
Host smart-d2a48613-0319-47fd-bcf5-91ef6e5d645d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=271974162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.271974162
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.980905811
Short name T704
Test name
Test status
Simulation time 86202676 ps
CPU time 2.92 seconds
Started Mar 19 03:21:31 PM PDT 24
Finished Mar 19 03:21:34 PM PDT 24
Peak memory 210304 kb
Host smart-31ab9c1a-dbdd-45be-9bfe-1077b1c1f739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=980905811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.980905811
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.2287324646
Short name T305
Test name
Test status
Simulation time 2654611203 ps
CPU time 57.27 seconds
Started Mar 19 03:21:40 PM PDT 24
Finished Mar 19 03:22:38 PM PDT 24
Peak memory 214900 kb
Host smart-41820cf9-31ca-49ce-9733-e0b03638004f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2287324646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.2287324646
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.162986562
Short name T375
Test name
Test status
Simulation time 168210630 ps
CPU time 6.84 seconds
Started Mar 19 03:21:38 PM PDT 24
Finished Mar 19 03:21:45 PM PDT 24
Peak memory 222204 kb
Host smart-3686a5ed-de96-46a1-9043-e7ce5d8306de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162986562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.162986562
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.2211462793
Short name T737
Test name
Test status
Simulation time 152668331 ps
CPU time 4.2 seconds
Started Mar 19 03:21:38 PM PDT 24
Finished Mar 19 03:21:42 PM PDT 24
Peak memory 220380 kb
Host smart-928669e8-8ff6-4179-98e8-102c6625792b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211462793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.2211462793
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.3446875263
Short name T819
Test name
Test status
Simulation time 551871036 ps
CPU time 18.37 seconds
Started Mar 19 03:21:34 PM PDT 24
Finished Mar 19 03:21:53 PM PDT 24
Peak memory 209676 kb
Host smart-b06f67a9-9260-416b-9339-ea5ba4e270bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3446875263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.3446875263
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.3645718496
Short name T534
Test name
Test status
Simulation time 174517555 ps
CPU time 3.05 seconds
Started Mar 19 03:21:36 PM PDT 24
Finished Mar 19 03:21:39 PM PDT 24
Peak memory 207240 kb
Host smart-130aa808-20e4-41b3-9062-b3696f937a13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645718496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.3645718496
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.3035314986
Short name T859
Test name
Test status
Simulation time 243046745 ps
CPU time 6.24 seconds
Started Mar 19 03:21:39 PM PDT 24
Finished Mar 19 03:21:46 PM PDT 24
Peak memory 208980 kb
Host smart-39ce8308-fac5-4fbb-8002-27f2bb879c73
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3035314986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.3035314986
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.3433598201
Short name T522
Test name
Test status
Simulation time 1734888538 ps
CPU time 4.63 seconds
Started Mar 19 03:21:36 PM PDT 24
Finished Mar 19 03:21:41 PM PDT 24
Peak memory 209452 kb
Host smart-87272ddc-04dc-4cbb-8d6b-08d3ca00e5de
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3433598201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.3433598201
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.4246288728
Short name T815
Test name
Test status
Simulation time 63994062 ps
CPU time 3.13 seconds
Started Mar 19 03:21:37 PM PDT 24
Finished Mar 19 03:21:40 PM PDT 24
Peak memory 208444 kb
Host smart-2ede3fcb-41c7-4bef-9d1c-b2f9a44dd619
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246288728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.4246288728
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.3182206981
Short name T770
Test name
Test status
Simulation time 113109824 ps
CPU time 2.81 seconds
Started Mar 19 03:21:33 PM PDT 24
Finished Mar 19 03:21:36 PM PDT 24
Peak memory 209780 kb
Host smart-832bb39d-40a2-4eb8-9c8c-21d04cb00c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182206981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.3182206981
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.3335709800
Short name T883
Test name
Test status
Simulation time 216657804 ps
CPU time 3.93 seconds
Started Mar 19 03:21:33 PM PDT 24
Finished Mar 19 03:21:38 PM PDT 24
Peak memory 209020 kb
Host smart-08513cc7-b1e9-4d30-984b-89a7fce67d64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335709800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.3335709800
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all_with_rand_reset.3265920553
Short name T134
Test name
Test status
Simulation time 1008373626 ps
CPU time 16.92 seconds
Started Mar 19 03:21:40 PM PDT 24
Finished Mar 19 03:21:57 PM PDT 24
Peak memory 223144 kb
Host smart-5e117e35-dee6-4d20-8bfc-3001c258f35b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3265920553 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all_with_rand_reset.3265920553
Directory /workspace/7.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.606269179
Short name T368
Test name
Test status
Simulation time 5201847511 ps
CPU time 25.65 seconds
Started Mar 19 03:21:31 PM PDT 24
Finished Mar 19 03:21:57 PM PDT 24
Peak memory 208936 kb
Host smart-64459bea-a0b5-4d9a-8f6b-4b022e18411c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606269179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.606269179
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.970928519
Short name T395
Test name
Test status
Simulation time 332091714 ps
CPU time 7.14 seconds
Started Mar 19 03:21:39 PM PDT 24
Finished Mar 19 03:21:46 PM PDT 24
Peak memory 210840 kb
Host smart-f48f11a4-c623-40f9-ab28-f64cb2389abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=970928519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.970928519
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.2962876284
Short name T558
Test name
Test status
Simulation time 140223700 ps
CPU time 0.88 seconds
Started Mar 19 03:21:39 PM PDT 24
Finished Mar 19 03:21:40 PM PDT 24
Peak memory 206428 kb
Host smart-83dce409-e2a3-4b9a-9a25-40fc609f99f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2962876284 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.2962876284
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.2545965006
Short name T835
Test name
Test status
Simulation time 252968991 ps
CPU time 3.15 seconds
Started Mar 19 03:21:38 PM PDT 24
Finished Mar 19 03:21:41 PM PDT 24
Peak memory 215096 kb
Host smart-96818b88-43f9-428b-ac0d-bb1eec45fcee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2545965006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.2545965006
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.502544460
Short name T888
Test name
Test status
Simulation time 2214052971 ps
CPU time 19.43 seconds
Started Mar 19 03:21:36 PM PDT 24
Finished Mar 19 03:21:55 PM PDT 24
Peak memory 210076 kb
Host smart-48847bc4-de2f-4dd7-80a6-51eba8fad6a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502544460 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.502544460
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.3890475589
Short name T300
Test name
Test status
Simulation time 760876486 ps
CPU time 5.93 seconds
Started Mar 19 03:21:33 PM PDT 24
Finished Mar 19 03:21:40 PM PDT 24
Peak memory 222908 kb
Host smart-fe34c3fb-1d00-4632-a2df-1f86fced8ba2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3890475589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.3890475589
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.3823000445
Short name T805
Test name
Test status
Simulation time 902982324 ps
CPU time 2.57 seconds
Started Mar 19 03:21:36 PM PDT 24
Finished Mar 19 03:21:38 PM PDT 24
Peak memory 214796 kb
Host smart-40b1cb62-3c97-4aca-9eec-fcd7506f584b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3823000445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.3823000445
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.202381859
Short name T519
Test name
Test status
Simulation time 245491718 ps
CPU time 5.44 seconds
Started Mar 19 03:21:32 PM PDT 24
Finished Mar 19 03:21:38 PM PDT 24
Peak memory 209780 kb
Host smart-7903105f-3988-457d-8178-eb8eff864cb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=202381859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.202381859
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.3999456876
Short name T745
Test name
Test status
Simulation time 591473810 ps
CPU time 12.54 seconds
Started Mar 19 03:21:32 PM PDT 24
Finished Mar 19 03:21:45 PM PDT 24
Peak memory 209052 kb
Host smart-4bd6fbca-44e4-44bf-8638-5beb8c2ec4c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999456876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.3999456876
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.4235444374
Short name T130
Test name
Test status
Simulation time 1461774548 ps
CPU time 7.89 seconds
Started Mar 19 03:21:34 PM PDT 24
Finished Mar 19 03:21:42 PM PDT 24
Peak memory 208372 kb
Host smart-3c5743ac-2efd-4c42-b116-9d2b4213ce2d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235444374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.4235444374
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.245352256
Short name T535
Test name
Test status
Simulation time 171812225 ps
CPU time 3.98 seconds
Started Mar 19 03:21:40 PM PDT 24
Finished Mar 19 03:21:44 PM PDT 24
Peak memory 209104 kb
Host smart-025ab44c-6f09-45ed-9416-2892d4c1b6c1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=245352256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.245352256
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.3873499492
Short name T592
Test name
Test status
Simulation time 491590083 ps
CPU time 7.21 seconds
Started Mar 19 03:21:36 PM PDT 24
Finished Mar 19 03:21:44 PM PDT 24
Peak memory 208340 kb
Host smart-31831c07-d8f0-4113-ad10-8ad286381697
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873499492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.3873499492
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.1345101100
Short name T791
Test name
Test status
Simulation time 73863599 ps
CPU time 2.3 seconds
Started Mar 19 03:21:34 PM PDT 24
Finished Mar 19 03:21:37 PM PDT 24
Peak memory 208256 kb
Host smart-73416841-20bc-48dd-8d54-dde7fbc17cf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345101100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.1345101100
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.2959372066
Short name T511
Test name
Test status
Simulation time 329953649 ps
CPU time 10.13 seconds
Started Mar 19 03:21:31 PM PDT 24
Finished Mar 19 03:21:42 PM PDT 24
Peak memory 207240 kb
Host smart-cd9b63ac-8b4c-4fdc-b127-8c82cc5250ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2959372066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.2959372066
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.3974462406
Short name T512
Test name
Test status
Simulation time 147403686 ps
CPU time 7.43 seconds
Started Mar 19 03:21:35 PM PDT 24
Finished Mar 19 03:21:43 PM PDT 24
Peak memory 216096 kb
Host smart-514df9ba-f185-48a4-b418-38de42581c16
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3974462406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.3974462406
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_stress_all_with_rand_reset.2915135453
Short name T646
Test name
Test status
Simulation time 2719961109 ps
CPU time 9.05 seconds
Started Mar 19 03:21:29 PM PDT 24
Finished Mar 19 03:21:43 PM PDT 24
Peak memory 222540 kb
Host smart-02ac9f42-72bc-4669-b89b-7b8c518941d3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2915135453 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all_with_rand_reset.2915135453
Directory /workspace/8.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.3216771591
Short name T494
Test name
Test status
Simulation time 144392090 ps
CPU time 5.06 seconds
Started Mar 19 03:21:38 PM PDT 24
Finished Mar 19 03:21:43 PM PDT 24
Peak memory 208116 kb
Host smart-35ff2a4c-e9bf-44b5-8865-42d49917fd7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3216771591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.3216771591
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.2843242457
Short name T206
Test name
Test status
Simulation time 322706569 ps
CPU time 2.41 seconds
Started Mar 19 03:21:37 PM PDT 24
Finished Mar 19 03:21:40 PM PDT 24
Peak memory 210860 kb
Host smart-016d3867-56da-46f3-b90f-9e93c27f06f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843242457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.2843242457
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.2034547366
Short name T741
Test name
Test status
Simulation time 13459653 ps
CPU time 0.75 seconds
Started Mar 19 03:21:30 PM PDT 24
Finished Mar 19 03:21:31 PM PDT 24
Peak memory 206384 kb
Host smart-f6a4150f-4f0b-42bc-a42b-e6c5bdfb0ba8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2034547366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.2034547366
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.302170408
Short name T425
Test name
Test status
Simulation time 183533391 ps
CPU time 5.75 seconds
Started Mar 19 03:21:33 PM PDT 24
Finished Mar 19 03:21:39 PM PDT 24
Peak memory 215392 kb
Host smart-aae13199-464a-47c0-ab9a-6fb8de62d027
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=302170408 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.302170408
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.2815748038
Short name T30
Test name
Test status
Simulation time 122445271 ps
CPU time 1.92 seconds
Started Mar 19 03:21:38 PM PDT 24
Finished Mar 19 03:21:40 PM PDT 24
Peak memory 221420 kb
Host smart-ad917a0b-51bc-4d23-aabf-890253d41be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2815748038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.2815748038
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.1619470038
Short name T66
Test name
Test status
Simulation time 2502384479 ps
CPU time 6.95 seconds
Started Mar 19 03:21:38 PM PDT 24
Finished Mar 19 03:21:45 PM PDT 24
Peak memory 209016 kb
Host smart-422ff805-f140-44d3-b8d3-e790af00bb9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619470038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.1619470038
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.1681000111
Short name T695
Test name
Test status
Simulation time 40363883 ps
CPU time 2.62 seconds
Started Mar 19 03:21:39 PM PDT 24
Finished Mar 19 03:21:42 PM PDT 24
Peak memory 209400 kb
Host smart-b1248f94-962d-404c-a3f3-cefb8b093207
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1681000111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.1681000111
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.669381910
Short name T767
Test name
Test status
Simulation time 1281589956 ps
CPU time 10.72 seconds
Started Mar 19 03:21:32 PM PDT 24
Finished Mar 19 03:21:43 PM PDT 24
Peak memory 211024 kb
Host smart-cdfc97fe-8308-4067-9d13-e0ff10726907
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=669381910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.669381910
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.1045204831
Short name T538
Test name
Test status
Simulation time 104857857 ps
CPU time 4.96 seconds
Started Mar 19 03:21:43 PM PDT 24
Finished Mar 19 03:21:48 PM PDT 24
Peak memory 220704 kb
Host smart-6ce0305c-1fce-4db7-9a20-b052bfe7a2f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1045204831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.1045204831
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.847215169
Short name T690
Test name
Test status
Simulation time 557948161 ps
CPU time 4.89 seconds
Started Mar 19 03:21:38 PM PDT 24
Finished Mar 19 03:21:43 PM PDT 24
Peak memory 210508 kb
Host smart-db99d44a-ee82-4998-8690-f32f091a4227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847215169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.847215169
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.3341598571
Short name T903
Test name
Test status
Simulation time 2071835203 ps
CPU time 46.97 seconds
Started Mar 19 03:21:42 PM PDT 24
Finished Mar 19 03:22:29 PM PDT 24
Peak memory 209320 kb
Host smart-50191b17-f050-4c33-be40-3967e68d7f89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3341598571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.3341598571
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.1655456026
Short name T852
Test name
Test status
Simulation time 113833522 ps
CPU time 4.24 seconds
Started Mar 19 03:21:36 PM PDT 24
Finished Mar 19 03:21:40 PM PDT 24
Peak memory 208428 kb
Host smart-7b115b91-00b8-4feb-93e6-80af7e51527e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1655456026 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.1655456026
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.4149711630
Short name T489
Test name
Test status
Simulation time 43842821 ps
CPU time 2.73 seconds
Started Mar 19 03:21:32 PM PDT 24
Finished Mar 19 03:21:35 PM PDT 24
Peak memory 209040 kb
Host smart-bd2cfd38-9765-4702-80e5-6f63816de4d9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149711630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.4149711630
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.3331385308
Short name T470
Test name
Test status
Simulation time 1058097418 ps
CPU time 22.69 seconds
Started Mar 19 03:21:44 PM PDT 24
Finished Mar 19 03:22:06 PM PDT 24
Peak memory 208416 kb
Host smart-d616a109-3d73-413d-8445-64fad6de6e63
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3331385308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.3331385308
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.673298385
Short name T441
Test name
Test status
Simulation time 306608889 ps
CPU time 8.12 seconds
Started Mar 19 03:21:34 PM PDT 24
Finished Mar 19 03:21:42 PM PDT 24
Peak memory 214800 kb
Host smart-6d42f68c-051f-4d25-ab9e-743ed2dbe756
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=673298385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.673298385
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.2817963799
Short name T458
Test name
Test status
Simulation time 3518225466 ps
CPU time 31.63 seconds
Started Mar 19 03:21:30 PM PDT 24
Finished Mar 19 03:22:02 PM PDT 24
Peak memory 208992 kb
Host smart-6b779ad7-7511-470d-9dd4-137fa52e667c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2817963799 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.2817963799
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.556763610
Short name T294
Test name
Test status
Simulation time 176184808 ps
CPU time 4.31 seconds
Started Mar 19 03:21:37 PM PDT 24
Finished Mar 19 03:21:42 PM PDT 24
Peak memory 208760 kb
Host smart-3f918611-85e8-43c5-91c3-1fcd2975c11b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=556763610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.556763610
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.3376846533
Short name T388
Test name
Test status
Simulation time 1114475278 ps
CPU time 8.69 seconds
Started Mar 19 03:21:32 PM PDT 24
Finished Mar 19 03:21:41 PM PDT 24
Peak memory 214804 kb
Host smart-42b849e5-83f0-4d7c-97cb-14822ee9ea89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376846533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.3376846533
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.1162451975
Short name T780
Test name
Test status
Simulation time 135887124 ps
CPU time 3.25 seconds
Started Mar 19 03:21:40 PM PDT 24
Finished Mar 19 03:21:43 PM PDT 24
Peak memory 210656 kb
Host smart-28cd4a5b-841e-4bd4-8ecd-d4c338642c19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162451975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.1162451975
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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