Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
43.16	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	360	216	144	40.00

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	168	112	40.00	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11555

1

T1

23

T2

126

T3

2

auto[Attestation]

8104

1

T1

10

T2

93

T3

6

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2838	1			T1	5		T2	34		T3	2
auto[Aes]	3467	1			T1	6		T2	38		T3	1
auto[Kmac]	3731	1			T1	4		T2	35		T3	1
auto[Otbn]	3533	1			T1	4		T2	41		T3	2

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7956	1			T1	13		T2	100		T3	8
auto[OpGenId]	6090	1			T1	14		T2	71		T3	2
auto[OpGenSwOut]	6244	1			T1	10		T2	72		T3	3
auto[OpGenHwOut]	7325	1			T1	9		T2	76		T3	3
auto[OpDisable]	130	1			T1	1		T2	2		T4	3

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10315

1

T1

18

T2

145

T3

8

auto[OpDoneFail]

17430

1

T1

29

T2

176

T3

8

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6292	1			T1	17		T2	40		T3	1
auto[StInit]	4371	1			T1	12		T2	56		T3	2
auto[StCreatorRootKey]	3096	1			T1	7		T2	46		T3	2
auto[StOwnerIntKey]	2672	1			T1	2		T2	36		T3	2
auto[StOwnerKey]	2387	1			T1	2		T2	35		T3	2
auto[StDisabled]	7847	1			T1	7		T2	108		T3	7
auto[StInvalid]	1080	1			T28	20		T39	19		T25	19

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	168	112	40.00	168

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	330	1			T2	2		T15	3		T19	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	120	1			T2	1		T28	1		T4	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	81	1			T2	4		T4	1		T98	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	80	1			T2	1		T4	2		T38	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	63	1			T2	1		T52	1		T61	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	208	1			T2	3		T4	1		T52	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	32	1			T28	2		T180	1		T181	3
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	318	1			T1	2		T2	2		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	132	1			T2	2		T82	1		T28	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	66	1			T2	1		T4	1		T114	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	75	1			T2	1		T4	1		T38	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	80	1			T2	2		T4	1		T98	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	195	1			T2	2		T17	1		T18	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	23	1			T28	1		T39	1		T80	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	360	1			T2	2		T19	1		T82	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	127	1			T1	1		T2	1		T15	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	76	1			T2	2		T82	1		T4	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	83	1			T4	3		T24	1		T182	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	47	1			T24	1		T79	1		T61	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	232	1			T1	1		T2	2		T17	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	35	1			T28	1		T39	2		T25	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	324	1			T2	3		T15	3		T19	4
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	137	1			T1	1		T18	2		T114	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	74	1			T1	1		T2	2		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	67	1			T2	1		T4	4		T61	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	68	1			T17	1		T4	1		T183	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	204	1			T1	1		T2	3		T114	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	35	1			T39	1		T26	2		T60	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	59	1			T4	1		T50	1		T123	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	106	1			T1	1		T2	2		T98	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	88	1			T1	1		T2	2		T3	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	69	1			T1	1		T17	1		T4	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	62	1			T4	1		T98	1		T56	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	186	1			T4	2		T114	1		T50	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	40	1			T26	1		T184	3		T80	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	63	1			T4	3		T122	2		T185	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	122	1			T2	3		T4	1		T24	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	91	1			T4	1		T98	1		T127	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	83	1			T2	2		T3	1		T17	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	52	1			T2	1		T127	1		T50	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	205	1			T2	4		T4	1		T114	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	37	1			T26	1		T184	1		T80	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	82	1			T4	3		T50	1		T80	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	107	1			T2	3		T38	1		T126	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	101	1			T2	1		T17	1		T4	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	51	1			T4	1		T50	1		T52	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	56	1			T2	1		T61	1		T185	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	224	1			T2	4		T18	1		T4	3
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	42	1			T39	1		T26	1		T184	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	59	1			T4	1		T55	1		T186	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	133	1			T2	2		T4	2		T29	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	86	1			T2	1		T4	1		T98	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	72	1			T2	4		T38	1		T52	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	52	1			T2	1		T17	1		T52	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	216	1			T2	3		T3	1		T4	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	28	1			T28	1		T26	3		T60	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	271	1			T1	1		T2	2		T15	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	96	1			T2	3		T4	1		T25	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	54	1			T2	1		T4	1		T127	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	52	1			T2	1		T50	1		T187	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	56	1			T2	1		T24	1		T61	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	165	1			T2	4		T17	1		T4	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	38	1			T28	1		T25	2		T80	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	448	1			T1	2		T2	1		T15	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	134	1			T13	1		T4	1		T24	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	99	1			T1	1		T2	2		T4	3
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	86	1			T2	1		T13	1		T14	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	85	1			T16	1		T52	1		T79	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	268	1			T2	4		T13	1		T14	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	39	1			T26	1		T80	1		T180	3
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	510	1			T2	2		T16	2		T4	3
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	140	1			T2	2		T4	3		T83	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	112	1			T188	1		T189	1		T190	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	79	1			T18	1		T114	1		T191	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	100	1			T1	1		T4	1		T188	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	287	1			T1	1		T2	6		T4	3
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	33	1			T28	1		T184	2		T186	3
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	421	1			T1	1		T2	1		T15	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	129	1			T2	2		T15	1		T82	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	107	1			T2	2		T38	1		T127	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	107	1			T2	1		T192	1		T50	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	82	1			T2	2		T18	1		T24	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	275	1			T2	5		T17	1		T18	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	35	1			T39	3		T25	1		T26	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	58	1			T193	1		T194	1		T186	3
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	115	1			T1	1		T2	1		T28	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	77	1			T4	2		T98	2		T61	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	55	1			T2	1		T4	2		T52	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	46	1			T2	1		T195	1		T196	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	209	1			T2	3		T3	1		T17	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	22	1			T28	1		T25	1		T180	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	45	1			T4	1		T61	1		T55	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	127	1			T1	1		T2	3		T14	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	111	1			T2	2		T13	1		T14	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	78	1			T24	1		T124	1		T125	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	81	1			T2	2		T13	1		T14	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	284	1			T2	3		T13	3		T14	3
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	40	1			T184	1		T181	1		T193	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	54	1			T4	2		T50	1		T122	3
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	166	1			T2	3		T82	1		T4	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	112	1			T2	1		T17	1		T82	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	91	1			T2	1		T4	1		T126	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	83	1			T2	2		T4	1		T127	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	306	1			T2	2		T3	1		T4	3
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	35	1			T28	1		T25	1		T80	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	53	1			T4	2		T50	1		T80	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	148	1			T2	1		T24	1		T39	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	108	1			T2	1		T7	1		T114	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	96	1			T2	2		T4	1		T113	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	93	1			T2	1		T3	1		T4	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	288	1			T2	3		T17	1		T4	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	36	1			T28	1		T39	1		T25	3

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	205	1			T2	5		T4	3		T38	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	709	1			T2	7		T15	3		T19	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	210	1			T2	4		T4	3		T38	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	679	1			T1	2		T2	6		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	194	1			T2	2		T82	1		T4	3
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	766	1			T1	2		T2	5		T15	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	191	1			T1	1		T2	3		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	718	1			T1	2		T2	6		T15	3
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	208	1			T1	2		T2	2		T3	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	402	1			T1	1		T2	2		T4	3
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	212	1			T2	3		T3	1		T18	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	441	1			T2	7		T17	1		T4	5
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	190	1			T2	1		T4	2		T114	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	473	1			T2	8		T17	1		T18	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	196	1			T2	5		T17	1		T4	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	450	1			T2	6		T3	1		T28	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	141	1			T2	2		T24	1		T127	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	591	1			T1	1		T2	10		T15	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	249	1			T1	1		T2	3		T13	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	910	1			T1	2		T2	5		T13	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	277	1			T1	1		T18	1		T4	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	984	1			T1	1		T2	10		T16	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	277	1			T2	5		T18	1		T24	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	879	1			T1	1		T2	8		T15	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	159	1			T2	2		T4	4		T52	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	423	1			T1	1		T2	4		T3	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	252	1			T2	4		T13	2		T14	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	514	1			T1	1		T2	6		T13	3
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	273	1			T2	4		T17	1		T82	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	574	1			T2	5		T3	1		T82	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	286	1			T2	4		T3	1		T7	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	536	1			T2	4		T17	1		T28	1