Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31827

1

T1

50

T2

371

T3

22

auto[1]

290

1

T83

2

T114

5

T127

8

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	31838	1			T1	50		T2	371		T3	22
auto[134217728:268435455]	14	1			T114	1		T195	1		T337	2
auto[268435456:402653183]	9	1			T255	1		T223	1		T104	1
auto[402653184:536870911]	10	1			T140	1		T130	1		T337	1
auto[536870912:671088639]	5	1			T255	1		T297	1		T233	1
auto[671088640:805306367]	9	1			T114	1		T127	1		T297	1
auto[805306368:939524095]	14	1			T127	1		T128	1		T129	1
auto[939524096:1073741823]	14	1			T195	1		T128	1		T129	3
auto[1073741824:1207959551]	10	1			T127	1		T223	1		T337	2
auto[1207959552:1342177279]	9	1			T83	1		T128	1		T130	1
auto[1342177280:1476395007]	8	1			T255	1		T381	1		T223	1
auto[1476395008:1610612735]	7	1			T127	1		T140	1		T219	1
auto[1610612736:1744830463]	5	1			T140	1		T219	1		T233	1
auto[1744830464:1879048191]	7	1			T140	1		T195	1		T219	1
auto[1879048192:2013265919]	7	1			T127	1		T130	1		T131	2
auto[2013265920:2147483647]	13	1			T127	1		T81	1		T195	2
auto[2147483648:2281701375]	6	1			T195	1		T129	1		T361	1
auto[2281701376:2415919103]	7	1			T255	1		T337	1		T297	1
auto[2415919104:2550136831]	8	1			T81	1		T140	2		T129	1
auto[2550136832:2684354559]	6	1			T236	1		T104	1		T291	2
auto[2684354560:2818572287]	12	1			T127	1		T129	1		T130	2
auto[2818572288:2952790015]	7	1			T219	1		T255	1		T130	1
auto[2952790016:3087007743]	9	1			T195	2		T263	1		T291	1
auto[3087007744:3221225471]	8	1			T291	3		T391	1		T392	1
auto[3221225472:3355443199]	8	1			T114	1		T140	1		T195	1
auto[3355443200:3489660927]	8	1			T129	2		T219	1		T337	1
auto[3489660928:3623878655]	13	1			T128	1		T129	1		T219	2
auto[3623878656:3758096383]	10	1			T129	1		T219	1		T297	1
auto[3758096384:3892314111]	8	1			T83	1		T219	1		T291	1
auto[3892314112:4026531839]	12	1			T114	1		T127	1		T140	1
auto[4026531840:4160749567]	8	1			T114	1		T104	1		T231	1
auto[4160749568:4294967295]	8	1			T195	1		T219	1		T295	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	31827	1			T1	50		T2	371		T3	22
auto[0:134217727]	auto[1]	11	1			T195	1		T337	1		T297	2
auto[134217728:268435455]	auto[1]	14	1			T114	1		T195	1		T337	2
auto[268435456:402653183]	auto[1]	9	1			T255	1		T223	1		T104	1
auto[402653184:536870911]	auto[1]	10	1			T140	1		T130	1		T337	1
auto[536870912:671088639]	auto[1]	5	1			T255	1		T297	1		T233	1
auto[671088640:805306367]	auto[1]	9	1			T114	1		T127	1		T297	1
auto[805306368:939524095]	auto[1]	14	1			T127	1		T128	1		T129	1
auto[939524096:1073741823]	auto[1]	14	1			T195	1		T128	1		T129	3
auto[1073741824:1207959551]	auto[1]	10	1			T127	1		T223	1		T337	2
auto[1207959552:1342177279]	auto[1]	9	1			T83	1		T128	1		T130	1
auto[1342177280:1476395007]	auto[1]	8	1			T255	1		T381	1		T223	1
auto[1476395008:1610612735]	auto[1]	7	1			T127	1		T140	1		T219	1
auto[1610612736:1744830463]	auto[1]	5	1			T140	1		T219	1		T233	1
auto[1744830464:1879048191]	auto[1]	7	1			T140	1		T195	1		T219	1
auto[1879048192:2013265919]	auto[1]	7	1			T127	1		T130	1		T131	2
auto[2013265920:2147483647]	auto[1]	13	1			T127	1		T81	1		T195	2
auto[2147483648:2281701375]	auto[1]	6	1			T195	1		T129	1		T361	1
auto[2281701376:2415919103]	auto[1]	7	1			T255	1		T337	1		T297	1
auto[2415919104:2550136831]	auto[1]	8	1			T81	1		T140	2		T129	1
auto[2550136832:2684354559]	auto[1]	6	1			T236	1		T104	1		T291	2
auto[2684354560:2818572287]	auto[1]	12	1			T127	1		T129	1		T130	2
auto[2818572288:2952790015]	auto[1]	7	1			T219	1		T255	1		T130	1
auto[2952790016:3087007743]	auto[1]	9	1			T195	2		T263	1		T291	1
auto[3087007744:3221225471]	auto[1]	8	1			T291	3		T391	1		T392	1
auto[3221225472:3355443199]	auto[1]	8	1			T114	1		T140	1		T195	1
auto[3355443200:3489660927]	auto[1]	8	1			T129	2		T219	1		T337	1
auto[3489660928:3623878655]	auto[1]	13	1			T128	1		T129	1		T219	2
auto[3623878656:3758096383]	auto[1]	10	1			T129	1		T219	1		T297	1
auto[3758096384:3892314111]	auto[1]	8	1			T83	1		T219	1		T291	1
auto[3892314112:4026531839]	auto[1]	12	1			T114	1		T127	1		T140	1
auto[4026531840:4160749567]	auto[1]	8	1			T114	1		T104	1		T231	1
auto[4160749568:4294967295]	auto[1]	8	1			T195	1		T219	1		T295	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1559

1

T2

21

T15

8

T16

1

auto[1]

1788

1

T1

5

T2

28

T16

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	95	1			T2	1		T15	1		T7	1
auto[134217728:268435455]	109	1			T1	1		T2	4		T4	1
auto[268435456:402653183]	87	1			T15	1		T16	1		T82	1
auto[402653184:536870911]	103	1			T2	3		T126	1		T127	1
auto[536870912:671088639]	121	1			T2	3		T4	3		T126	1
auto[671088640:805306367]	90	1			T2	2		T4	2		T25	1
auto[805306368:939524095]	111	1			T2	4		T126	1		T50	1
auto[939524096:1073741823]	94	1			T1	1		T2	2		T4	1
auto[1073741824:1207959551]	122	1			T2	1		T28	1		T4	1
auto[1207959552:1342177279]	114	1			T2	3		T16	1		T17	1
auto[1342177280:1476395007]	103	1			T15	1		T82	1		T126	2
auto[1476395008:1610612735]	103	1			T2	3		T17	1		T39	2
auto[1610612736:1744830463]	100	1			T2	2		T17	1		T39	1
auto[1744830464:1879048191]	118	1			T2	1		T4	2		T98	1
auto[1879048192:2013265919]	103	1			T2	2		T16	1		T28	1
auto[2013265920:2147483647]	91	1			T15	1		T17	1		T4	1
auto[2147483648:2281701375]	91	1			T83	1		T39	1		T98	1
auto[2281701376:2415919103]	116	1			T2	3		T17	1		T24	1
auto[2415919104:2550136831]	106	1			T15	1		T83	1		T127	1
auto[2550136832:2684354559]	108	1			T1	1		T2	2		T4	1
auto[2684354560:2818572287]	98	1			T2	1		T4	1		T29	1
auto[2818572288:2952790015]	113	1			T1	1		T2	2		T18	1
auto[2952790016:3087007743]	110	1			T2	1		T16	1		T18	1
auto[3087007744:3221225471]	86	1			T2	1		T82	1		T28	1
auto[3221225472:3355443199]	108	1			T7	1		T4	3		T126	1
auto[3355443200:3489660927]	112	1			T2	2		T25	1		T40	1
auto[3489660928:3623878655]	106	1			T1	1		T2	2		T7	1
auto[3623878656:3758096383]	103	1			T17	1		T28	1		T4	3
auto[3758096384:3892314111]	128	1			T2	1		T15	2		T18	1
auto[3892314112:4026531839]	98	1			T4	3		T81	2		T61	1
auto[4026531840:4160749567]	104	1			T2	2		T15	1		T18	1
auto[4160749568:4294967295]	96	1			T2	1		T4	1		T8	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	45	1			T15	1		T7	1		T28	1
auto[0:134217727]	auto[1]	50	1			T2	1		T187	1		T185	1
auto[134217728:268435455]	auto[0]	50	1			T2	2		T122	1		T113	1
auto[134217728:268435455]	auto[1]	59	1			T1	1		T2	2		T4	1
auto[268435456:402653183]	auto[0]	38	1			T15	1		T82	1		T4	1
auto[268435456:402653183]	auto[1]	49	1			T16	1		T25	1		T126	1
auto[402653184:536870911]	auto[0]	48	1			T126	1		T122	1		T44	1
auto[402653184:536870911]	auto[1]	55	1			T2	3		T127	1		T50	1
auto[536870912:671088639]	auto[0]	56	1			T2	2		T4	2		T98	1
auto[536870912:671088639]	auto[1]	65	1			T2	1		T4	1		T126	1
auto[671088640:805306367]	auto[0]	45	1			T25	1		T98	1		T40	1
auto[671088640:805306367]	auto[1]	45	1			T2	2		T4	2		T184	2
auto[805306368:939524095]	auto[0]	56	1			T2	1		T126	1		T50	1
auto[805306368:939524095]	auto[1]	55	1			T2	3		T76	1		T189	1
auto[939524096:1073741823]	auto[0]	40	1			T2	1		T27	1		T61	1
auto[939524096:1073741823]	auto[1]	54	1			T1	1		T2	1		T4	1
auto[1073741824:1207959551]	auto[0]	54	1			T2	1		T28	1		T39	1
auto[1073741824:1207959551]	auto[1]	68	1			T4	1		T83	1		T50	1
auto[1207959552:1342177279]	auto[0]	46	1			T2	1		T17	1		T4	2
auto[1207959552:1342177279]	auto[1]	68	1			T2	2		T16	1		T4	1
auto[1342177280:1476395007]	auto[0]	44	1			T15	1		T82	1		T40	1
auto[1342177280:1476395007]	auto[1]	59	1			T126	2		T76	1		T53	2
auto[1476395008:1610612735]	auto[0]	40	1			T2	1		T17	1		T50	1
auto[1476395008:1610612735]	auto[1]	63	1			T2	2		T39	2		T98	2
auto[1610612736:1744830463]	auto[0]	58	1			T2	2		T17	1		T126	1
auto[1610612736:1744830463]	auto[1]	42	1			T39	1		T9	1		T381	1
auto[1744830464:1879048191]	auto[0]	51	1			T98	1		T127	1		T50	1
auto[1744830464:1879048191]	auto[1]	67	1			T2	1		T4	2		T122	1
auto[1879048192:2013265919]	auto[0]	43	1			T2	1		T24	1		T98	1
auto[1879048192:2013265919]	auto[1]	60	1			T2	1		T16	1		T28	1
auto[2013265920:2147483647]	auto[0]	35	1			T15	1		T17	1		T114	1
auto[2013265920:2147483647]	auto[1]	56	1			T4	1		T61	1		T227	1
auto[2147483648:2281701375]	auto[0]	38	1			T39	1		T122	1		T53	1
auto[2147483648:2281701375]	auto[1]	53	1			T83	1		T98	1		T187	1
auto[2281701376:2415919103]	auto[0]	53	1			T2	1		T24	1		T98	1
auto[2281701376:2415919103]	auto[1]	63	1			T2	2		T17	1		T83	1
auto[2415919104:2550136831]	auto[0]	43	1			T15	1		T81	1		T61	1
auto[2415919104:2550136831]	auto[1]	63	1			T83	1		T127	1		T185	3
auto[2550136832:2684354559]	auto[0]	58	1			T2	2		T24	1		T79	1
auto[2550136832:2684354559]	auto[1]	50	1			T1	1		T4	1		T184	1
auto[2684354560:2818572287]	auto[0]	57	1			T2	1		T4	1		T29	1
auto[2684354560:2818572287]	auto[1]	41	1			T114	1		T50	1		T52	1
auto[2818572288:2952790015]	auto[0]	51	1			T2	2		T80	1		T140	1
auto[2818572288:2952790015]	auto[1]	62	1			T1	1		T18	1		T83	1
auto[2952790016:3087007743]	auto[0]	59	1			T16	1		T4	1		T98	1
auto[2952790016:3087007743]	auto[1]	51	1			T2	1		T18	1		T4	1
auto[3087007744:3221225471]	auto[0]	34	1			T82	1		T28	1		T98	1
auto[3087007744:3221225471]	auto[1]	52	1			T2	1		T4	1		T184	1
auto[3221225472:3355443199]	auto[0]	54	1			T7	1		T4	1		T114	1
auto[3221225472:3355443199]	auto[1]	54	1			T4	2		T126	1		T127	1
auto[3355443200:3489660927]	auto[0]	54	1			T2	1		T25	1		T80	1
auto[3355443200:3489660927]	auto[1]	58	1			T2	1		T40	1		T185	1
auto[3489660928:3623878655]	auto[0]	49	1			T2	1		T7	1		T25	1
auto[3489660928:3623878655]	auto[1]	57	1			T1	1		T2	1		T52	1
auto[3623878656:3758096383]	auto[0]	54	1			T28	1		T4	2		T39	2
auto[3623878656:3758096383]	auto[1]	49	1			T17	1		T4	1		T127	1
auto[3758096384:3892314111]	auto[0]	69	1			T15	2		T24	1		T25	1
auto[3758096384:3892314111]	auto[1]	59	1			T2	1		T18	1		T98	1
auto[3892314112:4026531839]	auto[0]	42	1			T4	1		T81	1		T87	1
auto[3892314112:4026531839]	auto[1]	56	1			T4	2		T81	1		T61	1
auto[4026531840:4160749567]	auto[0]	47	1			T2	1		T15	1		T25	1
auto[4026531840:4160749567]	auto[1]	57	1			T2	1		T18	1		T4	1
auto[4160749568:4294967295]	auto[0]	48	1			T4	1		T8	1		T25	1
auto[4160749568:4294967295]	auto[1]	48	1			T2	1		T126	1		T52	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1568

1

T2

18

T15

7

T16

2

auto[1]

1780

1

T1

5

T2

31

T15

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	93	1			T2	1		T16	1		T4	1
auto[134217728:268435455]	92	1			T4	1		T98	1		T52	2
auto[268435456:402653183]	92	1			T2	1		T28	2		T83	1
auto[402653184:536870911]	104	1			T2	1		T83	1		T29	1
auto[536870912:671088639]	97	1			T2	2		T83	1		T114	1
auto[671088640:805306367]	122	1			T2	1		T4	1		T114	1
auto[805306368:939524095]	109	1			T2	2		T82	1		T4	1
auto[939524096:1073741823]	103	1			T2	2		T15	1		T4	1
auto[1073741824:1207959551]	106	1			T2	1		T17	1		T4	1
auto[1207959552:1342177279]	113	1			T1	1		T2	2		T15	3
auto[1342177280:1476395007]	105	1			T2	1		T4	1		T39	1
auto[1476395008:1610612735]	106	1			T1	1		T18	1		T4	3
auto[1610612736:1744830463]	108	1			T2	3		T82	1		T25	1
auto[1744830464:1879048191]	101	1			T2	1		T28	1		T4	3
auto[1879048192:2013265919]	92	1			T2	2		T4	1		T126	1
auto[2013265920:2147483647]	107	1			T1	1		T2	1		T4	1
auto[2147483648:2281701375]	105	1			T2	3		T15	1		T7	2
auto[2281701376:2415919103]	117	1			T2	5		T16	1		T18	1
auto[2415919104:2550136831]	104	1			T2	2		T4	1		T98	1
auto[2550136832:2684354559]	93	1			T2	2		T4	1		T126	1
auto[2684354560:2818572287]	111	1			T2	1		T25	1		T98	1
auto[2818572288:2952790015]	101	1			T2	1		T18	1		T7	1
auto[2952790016:3087007743]	130	1			T2	2		T17	1		T4	3
auto[3087007744:3221225471]	110	1			T15	2		T16	1		T17	1
auto[3221225472:3355443199]	108	1			T1	1		T2	2		T4	1
auto[3355443200:3489660927]	95	1			T2	1		T16	1		T4	1
auto[3489660928:3623878655]	112	1			T2	3		T8	1		T98	1
auto[3623878656:3758096383]	108	1			T2	1		T17	1		T29	1
auto[3758096384:3892314111]	109	1			T2	1		T15	1		T17	1
auto[3892314112:4026531839]	87	1			T4	2		T114	1		T127	1
auto[4026531840:4160749567]	117	1			T1	1		T2	2		T17	1
auto[4160749568:4294967295]	91	1			T2	2		T4	1		T25	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	41	1			T2	1		T122	1		T27	1
auto[0:134217727]	auto[1]	52	1			T16	1		T4	1		T81	1
auto[134217728:268435455]	auto[0]	48	1			T98	1		T122	2		T27	1
auto[134217728:268435455]	auto[1]	44	1			T4	1		T52	2		T185	1
auto[268435456:402653183]	auto[0]	43	1			T28	2		T76	1		T80	1
auto[268435456:402653183]	auto[1]	49	1			T2	1		T83	1		T114	1
auto[402653184:536870911]	auto[0]	50	1			T2	1		T127	1		T50	1
auto[402653184:536870911]	auto[1]	54	1			T83	1		T29	1		T98	1
auto[536870912:671088639]	auto[0]	48	1			T2	1		T52	1		T27	1
auto[536870912:671088639]	auto[1]	49	1			T2	1		T83	1		T114	1
auto[671088640:805306367]	auto[0]	48	1			T114	1		T61	2		T30	1
auto[671088640:805306367]	auto[1]	74	1			T2	1		T4	1		T113	1
auto[805306368:939524095]	auto[0]	51	1			T2	2		T82	1		T4	1
auto[805306368:939524095]	auto[1]	58	1			T126	1		T98	1		T122	1
auto[939524096:1073741823]	auto[0]	56	1			T15	1		T25	1		T52	1
auto[939524096:1073741823]	auto[1]	47	1			T2	2		T4	1		T50	1
auto[1073741824:1207959551]	auto[0]	45	1			T17	1		T24	1		T98	1
auto[1073741824:1207959551]	auto[1]	61	1			T2	1		T4	1		T83	1
auto[1207959552:1342177279]	auto[0]	51	1			T2	2		T15	2		T61	1
auto[1207959552:1342177279]	auto[1]	62	1			T1	1		T15	1		T4	1
auto[1342177280:1476395007]	auto[0]	52	1			T2	1		T39	1		T126	1
auto[1342177280:1476395007]	auto[1]	53	1			T4	1		T126	1		T114	1
auto[1476395008:1610612735]	auto[0]	49	1			T98	1		T79	1		T226	1
auto[1476395008:1610612735]	auto[1]	57	1			T1	1		T18	1		T4	3
auto[1610612736:1744830463]	auto[0]	51	1			T25	1		T126	1		T55	1
auto[1610612736:1744830463]	auto[1]	57	1			T2	3		T82	1		T81	1
auto[1744830464:1879048191]	auto[0]	46	1			T28	1		T4	2		T39	1
auto[1744830464:1879048191]	auto[1]	55	1			T2	1		T4	1		T127	1
auto[1879048192:2013265919]	auto[0]	42	1			T4	1		T5	1		T129	1
auto[1879048192:2013265919]	auto[1]	50	1			T2	2		T126	1		T52	1
auto[2013265920:2147483647]	auto[0]	60	1			T2	1		T4	1		T25	1
auto[2013265920:2147483647]	auto[1]	47	1			T1	1		T40	1		T76	1
auto[2147483648:2281701375]	auto[0]	49	1			T2	2		T15	1		T7	2
auto[2147483648:2281701375]	auto[1]	56	1			T2	1		T39	1		T127	1
auto[2281701376:2415919103]	auto[0]	50	1			T2	2		T16	1		T4	1
auto[2281701376:2415919103]	auto[1]	67	1			T2	3		T18	1		T39	1
auto[2415919104:2550136831]	auto[0]	53	1			T2	1		T4	1		T81	1
auto[2415919104:2550136831]	auto[1]	51	1			T2	1		T98	1		T61	1
auto[2550136832:2684354559]	auto[0]	39	1			T2	1		T4	1		T61	1
auto[2550136832:2684354559]	auto[1]	54	1			T2	1		T126	1		T127	1
auto[2684354560:2818572287]	auto[0]	48	1			T2	1		T25	1		T122	1
auto[2684354560:2818572287]	auto[1]	63	1			T98	1		T61	2		T189	1
auto[2818572288:2952790015]	auto[0]	52	1			T2	1		T7	1		T187	3
auto[2818572288:2952790015]	auto[1]	49	1			T18	1		T28	1		T50	1
auto[2952790016:3087007743]	auto[0]	61	1			T17	1		T4	1		T25	1
auto[2952790016:3087007743]	auto[1]	69	1			T2	2		T4	2		T39	1
auto[3087007744:3221225471]	auto[0]	54	1			T15	2		T4	1		T24	1
auto[3087007744:3221225471]	auto[1]	56	1			T16	1		T17	1		T18	1
auto[3221225472:3355443199]	auto[0]	53	1			T98	1		T80	1		T113	1
auto[3221225472:3355443199]	auto[1]	55	1			T1	1		T2	2		T4	1
auto[3355443200:3489660927]	auto[0]	42	1			T2	1		T16	1		T122	1
auto[3355443200:3489660927]	auto[1]	53	1			T4	1		T127	1		T50	2
auto[3489660928:3623878655]	auto[0]	52	1			T98	1		T122	1		T80	1
auto[3489660928:3623878655]	auto[1]	60	1			T2	3		T8	1		T122	1
auto[3623878656:3758096383]	auto[0]	46	1			T29	1		T50	1		T42	1
auto[3623878656:3758096383]	auto[1]	62	1			T2	1		T17	1		T126	1
auto[3758096384:3892314111]	auto[0]	50	1			T15	1		T98	2		T50	1
auto[3758096384:3892314111]	auto[1]	59	1			T2	1		T17	1		T39	1
auto[3892314112:4026531839]	auto[0]	38	1			T4	1		T114	1		T127	1
auto[3892314112:4026531839]	auto[1]	49	1			T4	1		T52	1		T122	2
auto[4026531840:4160749567]	auto[0]	54	1			T17	1		T82	1		T28	1
auto[4026531840:4160749567]	auto[1]	63	1			T1	1		T2	2		T4	1
auto[4160749568:4294967295]	auto[0]	46	1			T25	1		T127	1		T189	1
auto[4160749568:4294967295]	auto[1]	45	1			T2	2		T4	1		T64	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1514

1

T2

21

T15

8

T16

1

auto[1]

1832

1

T1

5

T2

28

T16

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	109	1			T2	3		T15	1		T18	1
auto[134217728:268435455]	103	1			T2	2		T15	1		T28	1
auto[268435456:402653183]	95	1			T4	1		T29	1		T98	1
auto[402653184:536870911]	97	1			T2	2		T17	1		T39	1
auto[536870912:671088639]	122	1			T2	4		T15	1		T82	1
auto[671088640:805306367]	102	1			T2	1		T16	1		T4	1
auto[805306368:939524095]	121	1			T1	1		T2	1		T17	2
auto[939524096:1073741823]	86	1			T2	1		T4	1		T39	1
auto[1073741824:1207959551]	96	1			T2	4		T4	2		T52	1
auto[1207959552:1342177279]	103	1			T2	1		T17	1		T28	1
auto[1342177280:1476395007]	108	1			T15	1		T16	1		T82	1
auto[1476395008:1610612735]	110	1			T1	1		T2	1		T24	1
auto[1610612736:1744830463]	103	1			T1	1		T2	1		T16	1
auto[1744830464:1879048191]	109	1			T1	1		T2	2		T83	1
auto[1879048192:2013265919]	98	1			T2	1		T17	1		T4	1
auto[2013265920:2147483647]	102	1			T2	2		T15	1		T4	2
auto[2147483648:2281701375]	129	1			T1	1		T2	2		T15	1
auto[2281701376:2415919103]	95	1			T2	2		T25	1		T52	1
auto[2415919104:2550136831]	101	1			T2	1		T24	1		T127	1
auto[2550136832:2684354559]	103	1			T2	2		T4	1		T126	1
auto[2684354560:2818572287]	108	1			T2	1		T4	2		T25	1
auto[2818572288:2952790015]	100	1			T2	1		T16	1		T4	1
auto[2952790016:3087007743]	91	1			T4	2		T98	1		T127	1
auto[3087007744:3221225471]	107	1			T2	1		T15	1		T18	1
auto[3221225472:3355443199]	112	1			T2	1		T18	1		T82	1
auto[3355443200:3489660927]	114	1			T2	4		T4	2		T83	1
auto[3489660928:3623878655]	97	1			T2	3		T4	2		T39	1
auto[3623878656:3758096383]	89	1			T2	1		T28	1		T4	1
auto[3758096384:3892314111]	111	1			T2	2		T4	4		T25	1
auto[3892314112:4026531839]	105	1			T15	1		T7	1		T4	2
auto[4026531840:4160749567]	90	1			T2	2		T4	1		T24	1
auto[4160749568:4294967295]	130	1			T18	1		T4	1		T114	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	41	1			T2	1		T15	1		T4	2
auto[0:134217727]	auto[1]	68	1			T2	2		T18	1		T187	1
auto[134217728:268435455]	auto[0]	45	1			T2	1		T15	1		T28	1
auto[134217728:268435455]	auto[1]	58	1			T2	1		T4	1		T127	1
auto[268435456:402653183]	auto[0]	43	1			T29	1		T98	1		T5	1
auto[268435456:402653183]	auto[1]	52	1			T4	1		T127	1		T113	1
auto[402653184:536870911]	auto[0]	53	1			T185	1		T42	1		T123	1
auto[402653184:536870911]	auto[1]	44	1			T2	2		T17	1		T39	1
auto[536870912:671088639]	auto[0]	53	1			T2	2		T15	1		T82	1
auto[536870912:671088639]	auto[1]	69	1			T2	2		T52	1		T81	1
auto[671088640:805306367]	auto[0]	48	1			T140	1		T245	2		T44	1
auto[671088640:805306367]	auto[1]	54	1			T2	1		T16	1		T4	1
auto[805306368:939524095]	auto[0]	48	1			T2	1		T122	1		T76	1
auto[805306368:939524095]	auto[1]	73	1			T1	1		T17	2		T39	1
auto[939524096:1073741823]	auto[0]	38	1			T98	1		T140	1		T181	1
auto[939524096:1073741823]	auto[1]	48	1			T2	1		T4	1		T39	1
auto[1073741824:1207959551]	auto[0]	55	1			T2	4		T4	1		T40	1
auto[1073741824:1207959551]	auto[1]	41	1			T4	1		T52	1		T255	1
auto[1207959552:1342177279]	auto[0]	56	1			T17	1		T28	1		T24	1
auto[1207959552:1342177279]	auto[1]	47	1			T2	1		T114	2		T50	1
auto[1342177280:1476395007]	auto[0]	42	1			T15	1		T82	1		T80	1
auto[1342177280:1476395007]	auto[1]	66	1			T16	1		T4	1		T25	1
auto[1476395008:1610612735]	auto[0]	55	1			T24	1		T98	1		T80	1
auto[1476395008:1610612735]	auto[1]	55	1			T1	1		T2	1		T126	2
auto[1610612736:1744830463]	auto[0]	51	1			T7	1		T126	1		T98	1
auto[1610612736:1744830463]	auto[1]	52	1			T1	1		T2	1		T16	1
auto[1744830464:1879048191]	auto[0]	43	1			T25	1		T185	1		T266	1
auto[1744830464:1879048191]	auto[1]	66	1			T1	1		T2	2		T83	1
auto[1879048192:2013265919]	auto[0]	37	1			T17	1		T61	1		T381	1
auto[1879048192:2013265919]	auto[1]	61	1			T2	1		T4	1		T65	1
auto[2013265920:2147483647]	auto[0]	47	1			T2	1		T15	1		T4	2
auto[2013265920:2147483647]	auto[1]	55	1			T2	1		T25	1		T184	1
auto[2147483648:2281701375]	auto[0]	59	1			T15	1		T7	1		T39	1
auto[2147483648:2281701375]	auto[1]	70	1			T1	1		T2	2		T17	1
auto[2281701376:2415919103]	auto[0]	48	1			T25	1		T52	1		T113	1
auto[2281701376:2415919103]	auto[1]	47	1			T2	2		T140	1		T185	1
auto[2415919104:2550136831]	auto[0]	44	1			T24	1		T127	1		T187	1
auto[2415919104:2550136831]	auto[1]	57	1			T2	1		T52	1		T185	1
auto[2550136832:2684354559]	auto[0]	46	1			T2	1		T126	1		T98	1
auto[2550136832:2684354559]	auto[1]	57	1			T2	1		T4	1		T98	1
auto[2684354560:2818572287]	auto[0]	45	1			T4	1		T25	1		T98	1
auto[2684354560:2818572287]	auto[1]	63	1			T2	1		T4	1		T50	1
auto[2818572288:2952790015]	auto[0]	42	1			T16	1		T126	1		T27	1
auto[2818572288:2952790015]	auto[1]	58	1			T2	1		T4	1		T50	1
auto[2952790016:3087007743]	auto[0]	41	1			T98	1		T52	2		T27	1
auto[2952790016:3087007743]	auto[1]	50	1			T4	2		T127	1		T184	2
auto[3087007744:3221225471]	auto[0]	50	1			T15	1		T122	1		T80	2
auto[3087007744:3221225471]	auto[1]	57	1			T2	1		T18	1		T126	1
auto[3221225472:3355443199]	auto[0]	51	1			T2	1		T18	1		T82	1
auto[3221225472:3355443199]	auto[1]	61	1			T4	1		T29	1		T61	1
auto[3355443200:3489660927]	auto[0]	50	1			T2	2		T4	1		T39	1
auto[3355443200:3489660927]	auto[1]	64	1			T2	2		T4	1		T83	1
auto[3489660928:3623878655]	auto[0]	45	1			T2	2		T79	1		T61	2
auto[3489660928:3623878655]	auto[1]	52	1			T2	1		T4	2		T39	1
auto[3623878656:3758096383]	auto[0]	35	1			T2	1		T52	1		T81	1
auto[3623878656:3758096383]	auto[1]	54	1			T28	1		T4	1		T235	1
auto[3758096384:3892314111]	auto[0]	55	1			T2	2		T4	3		T25	1
auto[3758096384:3892314111]	auto[1]	56	1			T4	1		T50	1		T40	1
auto[3892314112:4026531839]	auto[0]	49	1			T15	1		T7	1		T4	1
auto[3892314112:4026531839]	auto[1]	56	1			T4	1		T76	1		T113	1
auto[4026531840:4160749567]	auto[0]	40	1			T2	2		T24	1		T80	1
auto[4026531840:4160749567]	auto[1]	50	1			T4	1		T8	1		T122	1
auto[4160749568:4294967295]	auto[0]	59	1			T18	1		T122	1		T5	1
auto[4160749568:4294967295]	auto[1]	71	1			T4	1		T114	1		T98	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1577

1

T2

21

T15

8

T16

1

auto[1]

1770

1

T1

5

T2

28

T16

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	108	1			T2	1		T15	2		T16	1
auto[134217728:268435455]	106	1			T2	2		T98	1		T52	1
auto[268435456:402653183]	98	1			T2	3		T15	1		T4	1
auto[402653184:536870911]	106	1			T2	3		T4	4		T8	1
auto[536870912:671088639]	115	1			T2	3		T39	1		T127	2
auto[671088640:805306367]	100	1			T2	1		T4	2		T24	1
auto[805306368:939524095]	135	1			T2	1		T4	2		T126	1
auto[939524096:1073741823]	117	1			T2	2		T4	1		T126	1
auto[1073741824:1207959551]	114	1			T1	1		T2	1		T28	1
auto[1207959552:1342177279]	99	1			T1	1		T2	2		T15	1
auto[1342177280:1476395007]	101	1			T2	1		T4	1		T24	1
auto[1476395008:1610612735]	97	1			T2	1		T7	1		T25	1
auto[1610612736:1744830463]	99	1			T2	2		T18	1		T28	1
auto[1744830464:1879048191]	135	1			T2	1		T16	1		T4	3
auto[1879048192:2013265919]	119	1			T2	1		T7	1		T4	1
auto[2013265920:2147483647]	105	1			T2	1		T4	2		T39	1
auto[2147483648:2281701375]	125	1			T2	3		T16	1		T17	1
auto[2281701376:2415919103]	91	1			T18	1		T4	3		T50	1
auto[2415919104:2550136831]	93	1			T2	4		T15	2		T39	1
auto[2550136832:2684354559]	91	1			T17	1		T82	1		T4	1
auto[2684354560:2818572287]	95	1			T2	2		T17	1		T4	3
auto[2818572288:2952790015]	100	1			T28	1		T24	1		T184	1
auto[2952790016:3087007743]	114	1			T2	1		T15	1		T28	1
auto[3087007744:3221225471]	109	1			T4	1		T98	2		T50	1
auto[3221225472:3355443199]	93	1			T1	1		T2	1		T98	1
auto[3355443200:3489660927]	110	1			T2	2		T4	1		T83	1
auto[3489660928:3623878655]	99	1			T1	1		T2	3		T25	1
auto[3623878656:3758096383]	87	1			T2	3		T16	1		T18	1
auto[3758096384:3892314111]	85	1			T17	1		T18	1		T4	1
auto[3892314112:4026531839]	95	1			T2	3		T15	1		T17	1
auto[4026531840:4160749567]	100	1			T1	1		T17	1		T7	1
auto[4160749568:4294967295]	106	1			T2	1		T50	1		T187	1