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Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 2935 1 T1 4 T2 40 T15 4
auto[1] 279 1 T83 1 T114 3 T127 6


Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] 86 1 T15 1 T17 1 T28 1
auto[134217728:268435455] 88 1 T2 1 T18 1 T28 1
auto[268435456:402653183] 107 1 T4 1 T24 1 T126 1
auto[402653184:536870911] 111 1 T2 1 T4 1 T39 3
auto[536870912:671088639] 110 1 T2 1 T15 1 T114 1
auto[671088640:805306367] 88 1 T2 2 T17 1 T28 1
auto[805306368:939524095] 102 1 T2 1 T16 1 T17 1
auto[939524096:1073741823] 106 1 T2 2 T24 1 T83 1
auto[1073741824:1207959551] 106 1 T1 1 T2 1 T4 1
auto[1207959552:1342177279] 93 1 T2 1 T114 1 T127 1
auto[1342177280:1476395007] 105 1 T2 1 T4 2 T52 1
auto[1476395008:1610612735] 84 1 T2 5 T7 2 T98 1
auto[1610612736:1744830463] 97 1 T2 1 T4 1 T83 1
auto[1744830464:1879048191] 87 1 T2 1 T4 2 T189 1
auto[1879048192:2013265919] 97 1 T15 1 T16 1 T4 1
auto[2013265920:2147483647] 121 1 T1 1 T24 1 T25 2
auto[2147483648:2281701375] 104 1 T2 2 T17 1 T29 1
auto[2281701376:2415919103] 94 1 T2 1 T126 1 T127 3
auto[2415919104:2550136831] 91 1 T2 1 T18 1 T82 1
auto[2550136832:2684354559] 93 1 T2 2 T4 3 T126 1
auto[2684354560:2818572287] 115 1 T2 2 T4 3 T114 1
auto[2818572288:2952790015] 91 1 T2 2 T17 1 T82 1
auto[2952790016:3087007743] 98 1 T2 1 T4 1 T39 1
auto[3087007744:3221225471] 116 1 T2 1 T16 1 T17 1
auto[3221225472:3355443199] 94 1 T2 1 T4 1 T83 1
auto[3355443200:3489660927] 96 1 T2 1 T18 1 T4 1
auto[3489660928:3623878655] 103 1 T2 3 T16 1 T28 1
auto[3623878656:3758096383] 110 1 T1 1 T2 1 T15 1
auto[3758096384:3892314111] 100 1 T2 1 T4 2 T25 1
auto[3892314112:4026531839] 106 1 T114 1 T52 1 T122 1
auto[4026531840:4160749567] 105 1 T1 1 T2 2 T50 1
auto[4160749568:4294967295] 110 1 T2 1 T82 1 T4 2


Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cpregwen_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] auto[0] 84 1 T15 1 T17 1 T28 1
auto[0:134217727] auto[1] 2 1 T255 1 T394 1 - -
auto[134217728:268435455] auto[0] 79 1 T2 1 T18 1 T28 1
auto[134217728:268435455] auto[1] 9 1 T127 1 T195 1 T255 1
auto[268435456:402653183] auto[0] 98 1 T4 1 T24 1 T126 1
auto[268435456:402653183] auto[1] 9 1 T128 1 T255 1 T337 1
auto[402653184:536870911] auto[0] 99 1 T2 1 T4 1 T39 3
auto[402653184:536870911] auto[1] 12 1 T327 1 T104 1 T297 1
auto[536870912:671088639] auto[0] 104 1 T2 1 T15 1 T114 1
auto[536870912:671088639] auto[1] 6 1 T128 2 T219 1 T297 1
auto[671088640:805306367] auto[0] 82 1 T2 2 T17 1 T28 1
auto[671088640:805306367] auto[1] 6 1 T195 1 T219 1 T104 1
auto[805306368:939524095] auto[0] 92 1 T2 1 T16 1 T17 1
auto[805306368:939524095] auto[1] 10 1 T140 1 T129 1 T223 1
auto[939524096:1073741823] auto[0] 97 1 T2 2 T24 1 T127 1
auto[939524096:1073741823] auto[1] 9 1 T83 1 T195 1 T219 1
auto[1073741824:1207959551] auto[0] 96 1 T1 1 T2 1 T4 1
auto[1073741824:1207959551] auto[1] 10 1 T195 1 T219 1 T130 1
auto[1207959552:1342177279] auto[0] 84 1 T2 1 T127 1 T80 1
auto[1207959552:1342177279] auto[1] 9 1 T114 1 T104 1 T233 1
auto[1342177280:1476395007] auto[0] 92 1 T2 1 T4 2 T52 1
auto[1342177280:1476395007] auto[1] 13 1 T81 1 T195 2 T233 3
auto[1476395008:1610612735] auto[0] 73 1 T2 5 T7 2 T98 1
auto[1476395008:1610612735] auto[1] 11 1 T128 1 T129 1 T381 1
auto[1610612736:1744830463] auto[0] 89 1 T2 1 T4 1 T83 1
auto[1610612736:1744830463] auto[1] 8 1 T114 1 T219 1 T337 1
auto[1744830464:1879048191] auto[0] 79 1 T2 1 T4 2 T189 1
auto[1744830464:1879048191] auto[1] 8 1 T129 1 T263 1 T393 1
auto[1879048192:2013265919] auto[0] 94 1 T15 1 T16 1 T4 1
auto[1879048192:2013265919] auto[1] 3 1 T128 1 T129 1 T404 1
auto[2013265920:2147483647] auto[0] 113 1 T1 1 T24 1 T25 2
auto[2013265920:2147483647] auto[1] 8 1 T327 1 T337 1 T297 1
auto[2147483648:2281701375] auto[0] 96 1 T2 2 T17 1 T29 1
auto[2147483648:2281701375] auto[1] 8 1 T130 1 T361 1 T291 2
auto[2281701376:2415919103] auto[0] 80 1 T2 1 T126 1 T127 1
auto[2281701376:2415919103] auto[1] 14 1 T127 2 T128 1 T129 1
auto[2415919104:2550136831] auto[0] 84 1 T2 1 T18 1 T82 1
auto[2415919104:2550136831] auto[1] 7 1 T337 1 T233 1 T291 2
auto[2550136832:2684354559] auto[0] 85 1 T2 2 T4 3 T126 1
auto[2550136832:2684354559] auto[1] 8 1 T81 1 T219 1 T104 2
auto[2684354560:2818572287] auto[0] 108 1 T2 2 T4 3 T187 1
auto[2684354560:2818572287] auto[1] 7 1 T114 1 T127 1 T327 1
auto[2818572288:2952790015] auto[0] 86 1 T2 2 T17 1 T82 1
auto[2818572288:2952790015] auto[1] 5 1 T129 1 T219 1 T291 1
auto[2952790016:3087007743] auto[0] 88 1 T2 1 T4 1 T39 1
auto[2952790016:3087007743] auto[1] 10 1 T127 1 T140 1 T130 1
auto[3087007744:3221225471] auto[0] 105 1 T2 1 T16 1 T17 1
auto[3087007744:3221225471] auto[1] 11 1 T81 1 T129 1 T295 1
auto[3221225472:3355443199] auto[0] 83 1 T2 1 T4 1 T83 1
auto[3221225472:3355443199] auto[1] 11 1 T255 1 T131 1 T337 1
auto[3355443200:3489660927] auto[0] 85 1 T2 1 T18 1 T4 1
auto[3355443200:3489660927] auto[1] 11 1 T128 1 T129 2 T263 1
auto[3489660928:3623878655] auto[0] 95 1 T2 3 T16 1 T28 1
auto[3489660928:3623878655] auto[1] 8 1 T127 1 T128 1 T223 1
auto[3623878656:3758096383] auto[0] 99 1 T1 1 T2 1 T15 1
auto[3623878656:3758096383] auto[1] 11 1 T195 2 T128 1 T131 1
auto[3758096384:3892314111] auto[0] 90 1 T2 1 T4 2 T25 1
auto[3758096384:3892314111] auto[1] 10 1 T81 1 T195 1 T263 1
auto[3892314112:4026531839] auto[0] 99 1 T114 1 T52 1 T122 1
auto[3892314112:4026531839] auto[1] 7 1 T195 1 T129 1 T130 1
auto[4026531840:4160749567] auto[0] 93 1 T1 1 T2 2 T50 1
auto[4026531840:4160749567] auto[1] 12 1 T81 1 T195 1 T219 1
auto[4160749568:4294967295] auto[0] 104 1 T2 1 T82 1 T4 2
auto[4160749568:4294967295] auto[1] 6 1 T337 1 T263 1 T291 1

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