Unified Coverage Report :: Group Instance : salt_5

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2938

1

T1

4

T2

40

T15

4

auto[1]

282

1

T83

3

T114

5

T127

7

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	89	1			T28	1		T98	1		T127	2
auto[134217728:268435455]	119	1			T2	2		T16	1		T82	1
auto[268435456:402653183]	88	1			T39	1		T114	2		T98	1
auto[402653184:536870911]	82	1			T82	1		T4	1		T184	1
auto[536870912:671088639]	115	1			T2	1		T17	2		T4	1
auto[671088640:805306367]	103	1			T2	3		T16	1		T4	1
auto[805306368:939524095]	94	1			T2	1		T4	1		T39	1
auto[939524096:1073741823]	86	1			T4	1		T126	2		T76	1
auto[1073741824:1207959551]	95	1			T4	3		T39	1		T114	1
auto[1207959552:1342177279]	117	1			T2	2		T39	1		T98	1
auto[1342177280:1476395007]	96	1			T2	2		T18	1		T25	1
auto[1476395008:1610612735]	100	1			T2	1		T82	1		T83	1
auto[1610612736:1744830463]	105	1			T2	1		T7	1		T4	2
auto[1744830464:1879048191]	104	1			T1	1		T2	2		T4	1
auto[1879048192:2013265919]	106	1			T2	2		T4	1		T98	1
auto[2013265920:2147483647]	89	1			T2	5		T15	1		T4	2
auto[2147483648:2281701375]	99	1			T2	1		T4	3		T25	1
auto[2281701376:2415919103]	117	1			T2	1		T4	2		T81	1
auto[2415919104:2550136831]	93	1			T4	1		T126	1		T114	1
auto[2550136832:2684354559]	114	1			T2	2		T17	1		T28	1
auto[2684354560:2818572287]	102	1			T1	1		T2	2		T15	1
auto[2818572288:2952790015]	105	1			T1	1		T2	1		T16	1
auto[2952790016:3087007743]	95	1			T4	1		T8	1		T126	1
auto[3087007744:3221225471]	92	1			T4	2		T39	2		T187	1
auto[3221225472:3355443199]	104	1			T2	3		T17	1		T4	1
auto[3355443200:3489660927]	86	1			T2	2		T15	1		T7	1
auto[3489660928:3623878655]	114	1			T1	1		T2	1		T25	1
auto[3623878656:3758096383]	104	1			T2	1		T4	1		T24	1
auto[3758096384:3892314111]	86	1			T2	2		T4	1		T98	1
auto[3892314112:4026531839]	109	1			T18	2		T24	1		T27	1
auto[4026531840:4160749567]	85	1			T2	1		T15	1		T17	1
auto[4160749568:4294967295]	127	1			T2	1		T83	1		T127	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	79	1			T28	1		T98	1		T127	2
auto[0:134217727]	auto[1]	10	1			T81	1		T140	1		T129	1
auto[134217728:268435455]	auto[0]	113	1			T2	2		T16	1		T82	1
auto[134217728:268435455]	auto[1]	6	1			T114	1		T223	1		T297	1
auto[268435456:402653183]	auto[0]	77	1			T39	1		T98	1		T122	2
auto[268435456:402653183]	auto[1]	11	1			T114	2		T255	1		T297	1
auto[402653184:536870911]	auto[0]	72	1			T82	1		T4	1		T184	1
auto[402653184:536870911]	auto[1]	10	1			T219	2		T381	1		T130	1
auto[536870912:671088639]	auto[0]	102	1			T2	1		T17	2		T4	1
auto[536870912:671088639]	auto[1]	13	1			T130	1		T297	2		T233	1
auto[671088640:805306367]	auto[0]	96	1			T2	3		T16	1		T4	1
auto[671088640:805306367]	auto[1]	7	1			T223	1		T327	2		T403	1
auto[805306368:939524095]	auto[0]	83	1			T2	1		T4	1		T39	1
auto[805306368:939524095]	auto[1]	11	1			T128	1		T131	2		T263	1
auto[939524096:1073741823]	auto[0]	82	1			T4	1		T126	2		T76	1
auto[939524096:1073741823]	auto[1]	4	1			T337	1		T231	1		T404	1
auto[1073741824:1207959551]	auto[0]	88	1			T4	3		T39	1		T114	1
auto[1073741824:1207959551]	auto[1]	7	1			T195	1		T219	1		T223	1
auto[1207959552:1342177279]	auto[0]	107	1			T2	2		T39	1		T98	1
auto[1207959552:1342177279]	auto[1]	10	1			T127	1		T337	2		T233	1
auto[1342177280:1476395007]	auto[0]	82	1			T2	2		T18	1		T25	1
auto[1342177280:1476395007]	auto[1]	14	1			T127	1		T195	2		T297	1
auto[1476395008:1610612735]	auto[0]	90	1			T2	1		T82	1		T83	1
auto[1476395008:1610612735]	auto[1]	10	1			T195	1		T219	1		T327	1
auto[1610612736:1744830463]	auto[0]	98	1			T2	1		T7	1		T4	2
auto[1610612736:1744830463]	auto[1]	7	1			T219	1		T130	1		T297	1
auto[1744830464:1879048191]	auto[0]	96	1			T1	1		T2	2		T4	1
auto[1744830464:1879048191]	auto[1]	8	1			T129	1		T217	1		T297	1
auto[1879048192:2013265919]	auto[0]	94	1			T2	2		T4	1		T98	1
auto[1879048192:2013265919]	auto[1]	12	1			T140	1		T236	1		T395	1
auto[2013265920:2147483647]	auto[0]	83	1			T2	5		T15	1		T4	2
auto[2013265920:2147483647]	auto[1]	6	1			T127	1		T219	1		T291	1
auto[2147483648:2281701375]	auto[0]	93	1			T2	1		T4	3		T25	1
auto[2147483648:2281701375]	auto[1]	6	1			T127	1		T297	1		T263	1
auto[2281701376:2415919103]	auto[0]	104	1			T2	1		T4	2		T81	1
auto[2281701376:2415919103]	auto[1]	13	1			T128	1		T129	2		T219	1
auto[2415919104:2550136831]	auto[0]	82	1			T4	1		T126	1		T114	1
auto[2415919104:2550136831]	auto[1]	11	1			T195	1		T255	1		T223	1
auto[2550136832:2684354559]	auto[0]	104	1			T2	2		T17	1		T28	1
auto[2550136832:2684354559]	auto[1]	10	1			T83	1		T195	2		T255	1
auto[2684354560:2818572287]	auto[0]	98	1			T1	1		T2	2		T15	1
auto[2684354560:2818572287]	auto[1]	4	1			T83	1		T195	1		T406	1
auto[2818572288:2952790015]	auto[0]	96	1			T1	1		T2	1		T16	1
auto[2818572288:2952790015]	auto[1]	9	1			T130	1		T263	1		T233	1
auto[2952790016:3087007743]	auto[0]	83	1			T4	1		T8	1		T126	1
auto[2952790016:3087007743]	auto[1]	12	1			T127	1		T128	1		T223	1
auto[3087007744:3221225471]	auto[0]	86	1			T4	2		T39	2		T187	1
auto[3087007744:3221225471]	auto[1]	6	1			T140	1		T130	1		T223	1
auto[3221225472:3355443199]	auto[0]	98	1			T2	3		T17	1		T4	1
auto[3221225472:3355443199]	auto[1]	6	1			T83	1		T127	1		T263	1
auto[3355443200:3489660927]	auto[0]	79	1			T2	2		T15	1		T7	1
auto[3355443200:3489660927]	auto[1]	7	1			T223	1		T399	1		T352	2
auto[3489660928:3623878655]	auto[0]	104	1			T1	1		T2	1		T25	1
auto[3489660928:3623878655]	auto[1]	10	1			T114	1		T128	1		T219	1
auto[3623878656:3758096383]	auto[0]	98	1			T2	1		T4	1		T24	1
auto[3623878656:3758096383]	auto[1]	6	1			T114	1		T129	1		T255	1
auto[3758096384:3892314111]	auto[0]	74	1			T2	2		T4	1		T98	1
auto[3758096384:3892314111]	auto[1]	12	1			T81	1		T219	1		T255	1
auto[3892314112:4026531839]	auto[0]	98	1			T18	2		T24	1		T27	1
auto[3892314112:4026531839]	auto[1]	11	1			T129	1		T297	1		T263	1
auto[4026531840:4160749567]	auto[0]	80	1			T2	1		T15	1		T17	1
auto[4026531840:4160749567]	auto[1]	5	1			T140	1		T352	1		T218	1
auto[4160749568:4294967295]	auto[0]	119	1			T2	1		T83	1		T184	1
auto[4160749568:4294967295]	auto[1]	8	1			T127	1		T128	1		T263	1