Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.79 99.07 98.06 98.43 100.00 99.11 98.41 91.49


Total test records in report: 1075
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T1004 /workspace/coverage/cover_reg_top/43.keymgr_intr_test.4020318595 Mar 21 01:22:45 PM PDT 24 Mar 21 01:22:46 PM PDT 24 28601901 ps
T1005 /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.3168651538 Mar 21 01:22:17 PM PDT 24 Mar 21 01:22:19 PM PDT 24 54138897 ps
T1006 /workspace/coverage/cover_reg_top/19.keymgr_intr_test.3889571223 Mar 21 01:22:24 PM PDT 24 Mar 21 01:22:25 PM PDT 24 44660460 ps
T1007 /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.3785808138 Mar 21 01:22:12 PM PDT 24 Mar 21 01:22:13 PM PDT 24 20578482 ps
T1008 /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.1149682509 Mar 21 01:22:11 PM PDT 24 Mar 21 01:22:13 PM PDT 24 67979785 ps
T1009 /workspace/coverage/cover_reg_top/47.keymgr_intr_test.2100327858 Mar 21 01:22:42 PM PDT 24 Mar 21 01:22:43 PM PDT 24 56058997 ps
T1010 /workspace/coverage/cover_reg_top/41.keymgr_intr_test.2128715639 Mar 21 01:22:39 PM PDT 24 Mar 21 01:22:40 PM PDT 24 11241110 ps
T1011 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.1949317895 Mar 21 01:22:24 PM PDT 24 Mar 21 01:22:30 PM PDT 24 1558425792 ps
T1012 /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.1340376687 Mar 21 01:22:25 PM PDT 24 Mar 21 01:22:32 PM PDT 24 780226795 ps
T1013 /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.2488408687 Mar 21 01:22:14 PM PDT 24 Mar 21 01:22:16 PM PDT 24 49793888 ps
T1014 /workspace/coverage/cover_reg_top/4.keymgr_intr_test.4177684437 Mar 21 01:22:09 PM PDT 24 Mar 21 01:22:10 PM PDT 24 12211213 ps
T1015 /workspace/coverage/cover_reg_top/45.keymgr_intr_test.3934825290 Mar 21 01:22:31 PM PDT 24 Mar 21 01:22:32 PM PDT 24 19329201 ps
T1016 /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.3361755180 Mar 21 01:22:10 PM PDT 24 Mar 21 01:22:12 PM PDT 24 70037320 ps
T1017 /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.390953171 Mar 21 01:22:18 PM PDT 24 Mar 21 01:22:20 PM PDT 24 36382322 ps
T1018 /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.1560930203 Mar 21 01:22:20 PM PDT 24 Mar 21 01:22:24 PM PDT 24 264866538 ps
T1019 /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.1983240951 Mar 21 01:22:10 PM PDT 24 Mar 21 01:22:11 PM PDT 24 38256894 ps
T1020 /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.3242999200 Mar 21 01:22:25 PM PDT 24 Mar 21 01:22:29 PM PDT 24 2827684538 ps
T1021 /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.3516713472 Mar 21 01:22:10 PM PDT 24 Mar 21 01:22:11 PM PDT 24 11862927 ps
T156 /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.1115282338 Mar 21 01:22:18 PM PDT 24 Mar 21 01:22:22 PM PDT 24 88682669 ps
T1022 /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.354701613 Mar 21 01:22:21 PM PDT 24 Mar 21 01:22:22 PM PDT 24 38843710 ps
T1023 /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.2509025205 Mar 21 01:22:27 PM PDT 24 Mar 21 01:22:33 PM PDT 24 140840044 ps
T1024 /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.3873099014 Mar 21 01:22:20 PM PDT 24 Mar 21 01:22:21 PM PDT 24 65799415 ps
T1025 /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.2604295610 Mar 21 01:22:12 PM PDT 24 Mar 21 01:22:13 PM PDT 24 71160955 ps
T1026 /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.128784453 Mar 21 01:22:12 PM PDT 24 Mar 21 01:22:16 PM PDT 24 46094643 ps
T1027 /workspace/coverage/cover_reg_top/37.keymgr_intr_test.666104883 Mar 21 01:22:38 PM PDT 24 Mar 21 01:22:39 PM PDT 24 49703891 ps
T1028 /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.1069134238 Mar 21 01:22:13 PM PDT 24 Mar 21 01:22:20 PM PDT 24 158190306 ps
T1029 /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.3356785924 Mar 21 01:22:09 PM PDT 24 Mar 21 01:22:11 PM PDT 24 211725361 ps
T1030 /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.3794203371 Mar 21 01:22:09 PM PDT 24 Mar 21 01:22:15 PM PDT 24 828158363 ps
T1031 /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.2707865595 Mar 21 01:22:25 PM PDT 24 Mar 21 01:22:26 PM PDT 24 38321489 ps
T1032 /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.2132290706 Mar 21 01:22:27 PM PDT 24 Mar 21 01:22:29 PM PDT 24 22331130 ps
T1033 /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.2153009721 Mar 21 01:22:26 PM PDT 24 Mar 21 01:22:32 PM PDT 24 182725941 ps
T166 /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.2497746693 Mar 21 01:22:25 PM PDT 24 Mar 21 01:22:34 PM PDT 24 398937170 ps
T1034 /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.3125775038 Mar 21 01:22:19 PM PDT 24 Mar 21 01:22:28 PM PDT 24 667177425 ps
T1035 /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.1713154061 Mar 21 01:22:14 PM PDT 24 Mar 21 01:22:16 PM PDT 24 778858455 ps
T1036 /workspace/coverage/cover_reg_top/11.keymgr_intr_test.3891949584 Mar 21 01:22:22 PM PDT 24 Mar 21 01:22:22 PM PDT 24 41394903 ps
T1037 /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.2417206395 Mar 21 01:22:16 PM PDT 24 Mar 21 01:22:16 PM PDT 24 34921000 ps
T1038 /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.1333732851 Mar 21 01:22:27 PM PDT 24 Mar 21 01:22:39 PM PDT 24 529019922 ps
T1039 /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.3096756541 Mar 21 01:22:25 PM PDT 24 Mar 21 01:22:26 PM PDT 24 21615765 ps
T1040 /workspace/coverage/cover_reg_top/16.keymgr_intr_test.4111084446 Mar 21 01:22:27 PM PDT 24 Mar 21 01:22:28 PM PDT 24 17539320 ps
T1041 /workspace/coverage/cover_reg_top/33.keymgr_intr_test.1262370017 Mar 21 01:22:54 PM PDT 24 Mar 21 01:22:55 PM PDT 24 40565559 ps
T1042 /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.2835067763 Mar 21 01:22:24 PM PDT 24 Mar 21 01:22:26 PM PDT 24 23834537 ps
T1043 /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.1559563238 Mar 21 01:22:24 PM PDT 24 Mar 21 01:22:25 PM PDT 24 16674013 ps
T1044 /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.4275111732 Mar 21 01:22:21 PM PDT 24 Mar 21 01:22:23 PM PDT 24 32545827 ps
T1045 /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.3995863222 Mar 21 01:22:20 PM PDT 24 Mar 21 01:22:33 PM PDT 24 862413410 ps
T1046 /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.514398970 Mar 21 01:22:15 PM PDT 24 Mar 21 01:22:16 PM PDT 24 36355181 ps
T1047 /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.580498320 Mar 21 01:22:25 PM PDT 24 Mar 21 01:22:26 PM PDT 24 24342851 ps
T1048 /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.3310991926 Mar 21 01:22:17 PM PDT 24 Mar 21 01:22:18 PM PDT 24 43703566 ps
T1049 /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.3279224373 Mar 21 01:22:16 PM PDT 24 Mar 21 01:22:19 PM PDT 24 36235538 ps
T1050 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.3790227331 Mar 21 01:22:24 PM PDT 24 Mar 21 01:22:27 PM PDT 24 338805599 ps
T1051 /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.470453775 Mar 21 01:22:11 PM PDT 24 Mar 21 01:22:15 PM PDT 24 720019364 ps
T1052 /workspace/coverage/cover_reg_top/24.keymgr_intr_test.1574825952 Mar 21 01:22:43 PM PDT 24 Mar 21 01:22:44 PM PDT 24 28222303 ps
T1053 /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.977946492 Mar 21 01:22:11 PM PDT 24 Mar 21 01:22:15 PM PDT 24 230237212 ps
T1054 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.3705130633 Mar 21 01:22:17 PM PDT 24 Mar 21 01:22:31 PM PDT 24 799934613 ps
T1055 /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.2826336958 Mar 21 01:22:17 PM PDT 24 Mar 21 01:22:19 PM PDT 24 30771170 ps
T1056 /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.1587844580 Mar 21 01:22:20 PM PDT 24 Mar 21 01:22:22 PM PDT 24 138523184 ps
T1057 /workspace/coverage/cover_reg_top/30.keymgr_intr_test.3751771268 Mar 21 01:22:40 PM PDT 24 Mar 21 01:22:42 PM PDT 24 35010125 ps
T1058 /workspace/coverage/cover_reg_top/38.keymgr_intr_test.619306921 Mar 21 01:22:51 PM PDT 24 Mar 21 01:22:52 PM PDT 24 11611578 ps
T1059 /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.502733508 Mar 21 01:22:09 PM PDT 24 Mar 21 01:22:13 PM PDT 24 605947972 ps
T1060 /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.857196681 Mar 21 01:22:24 PM PDT 24 Mar 21 01:22:26 PM PDT 24 120851067 ps
T1061 /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.1094331960 Mar 21 01:22:18 PM PDT 24 Mar 21 01:22:21 PM PDT 24 59832151 ps
T1062 /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.2415172941 Mar 21 01:22:27 PM PDT 24 Mar 21 01:22:29 PM PDT 24 190486529 ps
T1063 /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.673646552 Mar 21 01:22:15 PM PDT 24 Mar 21 01:22:17 PM PDT 24 23537277 ps
T1064 /workspace/coverage/cover_reg_top/13.keymgr_intr_test.4121770550 Mar 21 01:22:23 PM PDT 24 Mar 21 01:22:24 PM PDT 24 17186265 ps
T1065 /workspace/coverage/cover_reg_top/29.keymgr_intr_test.1212193028 Mar 21 01:22:37 PM PDT 24 Mar 21 01:22:38 PM PDT 24 33100507 ps
T1066 /workspace/coverage/cover_reg_top/10.keymgr_intr_test.2581975357 Mar 21 01:22:19 PM PDT 24 Mar 21 01:22:20 PM PDT 24 20679516 ps
T1067 /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.1484813266 Mar 21 01:22:27 PM PDT 24 Mar 21 01:22:30 PM PDT 24 59655713 ps
T1068 /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.1310484673 Mar 21 01:22:16 PM PDT 24 Mar 21 01:22:33 PM PDT 24 2162913440 ps
T1069 /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.985603650 Mar 21 01:22:13 PM PDT 24 Mar 21 01:22:14 PM PDT 24 84700283 ps
T150 /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.2570064633 Mar 21 01:22:21 PM PDT 24 Mar 21 01:22:32 PM PDT 24 360854947 ps
T1070 /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.3916506855 Mar 21 01:22:21 PM PDT 24 Mar 21 01:22:22 PM PDT 24 167126679 ps
T1071 /workspace/coverage/cover_reg_top/21.keymgr_intr_test.2798399185 Mar 21 01:22:23 PM PDT 24 Mar 21 01:22:24 PM PDT 24 10227902 ps
T1072 /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.3942245929 Mar 21 01:22:10 PM PDT 24 Mar 21 01:22:12 PM PDT 24 201250753 ps
T1073 /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.1077532249 Mar 21 01:22:16 PM PDT 24 Mar 21 01:22:18 PM PDT 24 77400100 ps
T1074 /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.3985438185 Mar 21 01:22:14 PM PDT 24 Mar 21 01:22:16 PM PDT 24 38016217 ps
T1075 /workspace/coverage/cover_reg_top/5.keymgr_intr_test.367869945 Mar 21 01:22:12 PM PDT 24 Mar 21 01:22:13 PM PDT 24 14905186 ps

Test location /workspace/coverage/default/43.keymgr_stress_all.3835275703
Short name T2
Test name
Test status
Simulation time 1180011105 ps
CPU time 44.76 seconds
Started Mar 21 03:26:30 PM PDT 24
Finished Mar 21 03:27:15 PM PDT 24
Peak memory 222920 kb
Host smart-b3152234-d4aa-4e97-aa27-79ba96f06595
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3835275703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.3835275703
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_stress_all_with_rand_reset.3106605199
Short name T122
Test name
Test status
Simulation time 1197009569 ps
CPU time 7.17 seconds
Started Mar 21 03:26:55 PM PDT 24
Finished Mar 21 03:27:03 PM PDT 24
Peak memory 222920 kb
Host smart-ad2a2929-9915-4afd-bb84-7d9b20e4147a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106605199 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all_with_rand_reset.3106605199
Directory /workspace/44.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.1006353704
Short name T10
Test name
Test status
Simulation time 1211691518 ps
CPU time 27.83 seconds
Started Mar 21 03:23:46 PM PDT 24
Finished Mar 21 03:24:15 PM PDT 24
Peak memory 235884 kb
Host smart-0df17273-d5f9-472b-87a4-a132f3e17ace
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1006353704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.1006353704
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/42.keymgr_stress_all_with_rand_reset.3463250077
Short name T61
Test name
Test status
Simulation time 555715208 ps
CPU time 24.18 seconds
Started Mar 21 03:26:30 PM PDT 24
Finished Mar 21 03:26:54 PM PDT 24
Peak memory 221008 kb
Host smart-3377a581-0e8c-4c95-9987-0e28450836d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3463250077 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all_with_rand_reset.3463250077
Directory /workspace/42.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.3244045992
Short name T4
Test name
Test status
Simulation time 275393484040 ps
CPU time 446.03 seconds
Started Mar 21 03:25:02 PM PDT 24
Finished Mar 21 03:32:28 PM PDT 24
Peak memory 221060 kb
Host smart-c93988ff-4097-447d-ac74-eb8e721419d2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244045992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.3244045992
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.349071873
Short name T9
Test name
Test status
Simulation time 54858809 ps
CPU time 3.26 seconds
Started Mar 21 03:23:48 PM PDT 24
Finished Mar 21 03:23:52 PM PDT 24
Peak memory 215140 kb
Host smart-d75f668a-4a5a-4f60-91e3-c92ea53fe033
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=349071873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.349071873
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.3781140375
Short name T46
Test name
Test status
Simulation time 3867091132 ps
CPU time 38.41 seconds
Started Mar 21 03:24:29 PM PDT 24
Finished Mar 21 03:25:08 PM PDT 24
Peak memory 216692 kb
Host smart-9c9f11d1-77d6-4e6d-875a-14457d4417dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781140375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.3781140375
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.2805657319
Short name T129
Test name
Test status
Simulation time 231497586 ps
CPU time 13.03 seconds
Started Mar 21 03:23:58 PM PDT 24
Finished Mar 21 03:24:11 PM PDT 24
Peak memory 215372 kb
Host smart-cd6bee46-313f-49e0-b2ad-1b5ccdba860a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2805657319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.2805657319
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.830372183
Short name T112
Test name
Test status
Simulation time 1631415492 ps
CPU time 9.39 seconds
Started Mar 21 01:22:23 PM PDT 24
Finished Mar 21 01:22:32 PM PDT 24
Peak memory 220488 kb
Host smart-6f6a0f0c-fdc3-40c1-9170-693e70c6f6c9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=830372183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.
keymgr_shadow_reg_errors_with_csr_rw.830372183
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.1871662880
Short name T25
Test name
Test status
Simulation time 60618921 ps
CPU time 3.99 seconds
Started Mar 21 03:24:47 PM PDT 24
Finished Mar 21 03:24:51 PM PDT 24
Peak memory 214772 kb
Host smart-e7c4ca63-dd92-4a73-894d-a306c9eff3c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1871662880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.1871662880
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.275385859
Short name T352
Test name
Test status
Simulation time 215270939 ps
CPU time 11.82 seconds
Started Mar 21 03:26:14 PM PDT 24
Finished Mar 21 03:26:26 PM PDT 24
Peak memory 216200 kb
Host smart-5555a9b5-9d30-4fbd-ad51-15a4335a5eb1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=275385859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.275385859
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.231349767
Short name T337
Test name
Test status
Simulation time 5684854337 ps
CPU time 135.33 seconds
Started Mar 21 03:24:25 PM PDT 24
Finished Mar 21 03:26:40 PM PDT 24
Peak memory 215204 kb
Host smart-730fc797-5264-4ea3-8ab1-60811fdca507
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=231349767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.231349767
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_stress_all_with_rand_reset.2521566851
Short name T98
Test name
Test status
Simulation time 1461655808 ps
CPU time 12.33 seconds
Started Mar 21 03:24:30 PM PDT 24
Finished Mar 21 03:24:42 PM PDT 24
Peak memory 223116 kb
Host smart-aa47b97e-200f-4f9c-afb1-396edcdd6233
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521566851 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all_with_rand_reset.2521566851
Directory /workspace/12.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.1455603252
Short name T27
Test name
Test status
Simulation time 108070312 ps
CPU time 4.99 seconds
Started Mar 21 03:26:44 PM PDT 24
Finished Mar 21 03:26:49 PM PDT 24
Peak memory 214808 kb
Host smart-a1b4dae8-c5fe-447f-82ab-b48eb8b2944f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455603252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.1455603252
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.351707747
Short name T255
Test name
Test status
Simulation time 372713330 ps
CPU time 7.19 seconds
Started Mar 21 03:25:49 PM PDT 24
Finished Mar 21 03:25:57 PM PDT 24
Peak memory 215596 kb
Host smart-6f69dbc5-340e-4f85-9ba0-fcd7fdbf71e5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=351707747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.351707747
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.3384148835
Short name T38
Test name
Test status
Simulation time 141620160 ps
CPU time 3.71 seconds
Started Mar 21 03:26:58 PM PDT 24
Finished Mar 21 03:27:02 PM PDT 24
Peak memory 210968 kb
Host smart-e897b433-5f9a-492d-8999-26f616e2e1cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384148835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.3384148835
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.1448638519
Short name T233
Test name
Test status
Simulation time 933304050 ps
CPU time 13.28 seconds
Started Mar 21 03:23:44 PM PDT 24
Finished Mar 21 03:23:59 PM PDT 24
Peak memory 214892 kb
Host smart-041089c8-dec5-4bdf-81e1-4e7e266427c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1448638519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.1448638519
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.3136406401
Short name T40
Test name
Test status
Simulation time 3032046479 ps
CPU time 5.88 seconds
Started Mar 21 03:24:49 PM PDT 24
Finished Mar 21 03:24:55 PM PDT 24
Peak memory 219088 kb
Host smart-2d8b522d-9414-45eb-ba61-f2055b6aaeb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136406401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.3136406401
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.2649232274
Short name T185
Test name
Test status
Simulation time 1397813196 ps
CPU time 15.05 seconds
Started Mar 21 03:24:10 PM PDT 24
Finished Mar 21 03:24:25 PM PDT 24
Peak memory 216392 kb
Host smart-c0d5e470-04db-42c9-923e-abbc043d075f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2649232274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.2649232274
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.529051993
Short name T110
Test name
Test status
Simulation time 160692733 ps
CPU time 4.13 seconds
Started Mar 21 01:22:25 PM PDT 24
Finished Mar 21 01:22:29 PM PDT 24
Peak memory 214564 kb
Host smart-b65f2a20-c42c-4337-bc3c-795092315414
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529051993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.
keymgr_shadow_reg_errors_with_csr_rw.529051993
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.4122330299
Short name T127
Test name
Test status
Simulation time 1375630966 ps
CPU time 9.72 seconds
Started Mar 21 03:25:48 PM PDT 24
Finished Mar 21 03:25:59 PM PDT 24
Peak memory 216336 kb
Host smart-798b3562-81d4-448a-ac75-07cb3f166b45
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4122330299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.4122330299
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_stress_all_with_rand_reset.555093833
Short name T59
Test name
Test status
Simulation time 1922401747 ps
CPU time 20.69 seconds
Started Mar 21 03:23:54 PM PDT 24
Finished Mar 21 03:24:15 PM PDT 24
Peak memory 223152 kb
Host smart-49081de3-a1f1-4d63-b3a2-1b0856725b42
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555093833 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all_with_rand_reset.555093833
Directory /workspace/6.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.688056043
Short name T114
Test name
Test status
Simulation time 56129766 ps
CPU time 3.96 seconds
Started Mar 21 03:25:50 PM PDT 24
Finished Mar 21 03:25:54 PM PDT 24
Peak memory 214824 kb
Host smart-d3ad772e-1760-42c9-9db9-068942891c10
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=688056043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.688056043
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.2358174512
Short name T30
Test name
Test status
Simulation time 1071024689 ps
CPU time 8.58 seconds
Started Mar 21 03:26:46 PM PDT 24
Finished Mar 21 03:26:55 PM PDT 24
Peak memory 221608 kb
Host smart-8e7bd355-be4e-400f-80cd-59d16197ea6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2358174512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.2358174512
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.80775745
Short name T70
Test name
Test status
Simulation time 1085548270 ps
CPU time 46.21 seconds
Started Mar 21 03:23:43 PM PDT 24
Finished Mar 21 03:24:30 PM PDT 24
Peak memory 215496 kb
Host smart-96f5f97b-5ed4-4ab6-8865-39b5c52dcbed
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80775745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.80775745
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.3626548345
Short name T116
Test name
Test status
Simulation time 149850238 ps
CPU time 4.67 seconds
Started Mar 21 01:22:21 PM PDT 24
Finished Mar 21 01:22:26 PM PDT 24
Peak memory 214576 kb
Host smart-44726c54-a1c0-4cc9-9e47-dd894c817737
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626548345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.3626548345
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.117486317
Short name T23
Test name
Test status
Simulation time 377337980 ps
CPU time 5.67 seconds
Started Mar 21 03:24:46 PM PDT 24
Finished Mar 21 03:24:52 PM PDT 24
Peak memory 221024 kb
Host smart-6a8b38c7-afad-4ecc-98b4-7f7bb60e71e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117486317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.117486317
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.3162412377
Short name T402
Test name
Test status
Simulation time 671260677 ps
CPU time 13.31 seconds
Started Mar 21 03:23:43 PM PDT 24
Finished Mar 21 03:23:57 PM PDT 24
Peak memory 214864 kb
Host smart-c50cce3a-c112-4d4e-80d2-20dad43425b5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3162412377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.3162412377
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.3997387164
Short name T260
Test name
Test status
Simulation time 4490480217 ps
CPU time 46.18 seconds
Started Mar 21 03:25:10 PM PDT 24
Finished Mar 21 03:25:57 PM PDT 24
Peak memory 216776 kb
Host smart-e8c8d55b-a469-4a4f-a6d2-3e0d5aea366c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997387164 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.3997387164
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.3208306240
Short name T184
Test name
Test status
Simulation time 96329840 ps
CPU time 4.58 seconds
Started Mar 21 03:25:03 PM PDT 24
Finished Mar 21 03:25:07 PM PDT 24
Peak memory 214592 kb
Host smart-27d31de5-2bcc-48f5-9798-8f6465df09a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208306240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.3208306240
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.2778283242
Short name T147
Test name
Test status
Simulation time 52113791 ps
CPU time 3.75 seconds
Started Mar 21 03:24:46 PM PDT 24
Finished Mar 21 03:24:49 PM PDT 24
Peak memory 219024 kb
Host smart-0370f2bc-e5a6-4bf8-a34f-f9ee9261df27
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778283242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.2778283242
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.391112915
Short name T475
Test name
Test status
Simulation time 460125412 ps
CPU time 11.43 seconds
Started Mar 21 03:23:42 PM PDT 24
Finished Mar 21 03:23:54 PM PDT 24
Peak memory 218324 kb
Host smart-9d855252-499f-4eb6-b76f-67ebfc3de8eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391112915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.391112915
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.2092723238
Short name T223
Test name
Test status
Simulation time 109481630 ps
CPU time 6.44 seconds
Started Mar 21 03:23:44 PM PDT 24
Finished Mar 21 03:23:52 PM PDT 24
Peak memory 215052 kb
Host smart-e0b36187-05eb-4e3f-a38b-5a9ea96252a7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2092723238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.2092723238
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.2985963586
Short name T195
Test name
Test status
Simulation time 2740036289 ps
CPU time 42.11 seconds
Started Mar 21 03:25:01 PM PDT 24
Finished Mar 21 03:25:43 PM PDT 24
Peak memory 214896 kb
Host smart-3ea1c3e5-c10c-4df8-88e1-61e77f0db6c3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2985963586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.2985963586
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.2124364999
Short name T415
Test name
Test status
Simulation time 34845533 ps
CPU time 0.71 seconds
Started Mar 21 03:23:43 PM PDT 24
Finished Mar 21 03:23:45 PM PDT 24
Peak memory 206388 kb
Host smart-5964401a-bdc6-4f31-bae1-ada9f78187cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2124364999 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.2124364999
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.3891762893
Short name T230
Test name
Test status
Simulation time 77397795 ps
CPU time 2.74 seconds
Started Mar 21 03:23:46 PM PDT 24
Finished Mar 21 03:23:50 PM PDT 24
Peak memory 222820 kb
Host smart-41e740b3-f5f0-4b75-a204-62c275fe6112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891762893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.3891762893
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.2520989254
Short name T318
Test name
Test status
Simulation time 4420597964 ps
CPU time 42.87 seconds
Started Mar 21 03:25:46 PM PDT 24
Finished Mar 21 03:26:30 PM PDT 24
Peak memory 217088 kb
Host smart-02d29d91-9033-41a1-9dda-086179ddbc9b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520989254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.2520989254
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.2570064633
Short name T150
Test name
Test status
Simulation time 360854947 ps
CPU time 10.16 seconds
Started Mar 21 01:22:21 PM PDT 24
Finished Mar 21 01:22:32 PM PDT 24
Peak memory 214188 kb
Host smart-1277d44d-19e0-4dfa-8228-39c39d1145d9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2570064633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.2570064633
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.3597927776
Short name T159
Test name
Test status
Simulation time 7409346359 ps
CPU time 42.17 seconds
Started Mar 21 01:22:33 PM PDT 24
Finished Mar 21 01:23:16 PM PDT 24
Peak memory 214220 kb
Host smart-2d69c627-dba1-4695-b69a-15a7b6b23741
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597927776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.3597927776
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.3386387568
Short name T186
Test name
Test status
Simulation time 3347200446 ps
CPU time 41.15 seconds
Started Mar 21 03:24:46 PM PDT 24
Finished Mar 21 03:25:28 PM PDT 24
Peak memory 231160 kb
Host smart-685c10b9-f7dc-4cdd-9b59-8254b56e8fc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386387568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.3386387568
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.1965357014
Short name T280
Test name
Test status
Simulation time 2451324583 ps
CPU time 28.11 seconds
Started Mar 21 03:25:06 PM PDT 24
Finished Mar 21 03:25:34 PM PDT 24
Peak memory 221492 kb
Host smart-e26e5565-bda0-4330-9d46-af9d273c2eb2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1965357014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.1965357014
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.870098578
Short name T202
Test name
Test status
Simulation time 2029609563 ps
CPU time 69.56 seconds
Started Mar 21 03:25:19 PM PDT 24
Finished Mar 21 03:26:28 PM PDT 24
Peak memory 217920 kb
Host smart-521fe1a1-4134-4c6a-b62b-f8573b5943e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=870098578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.870098578
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.3011744878
Short name T399
Test name
Test status
Simulation time 7441097548 ps
CPU time 103.44 seconds
Started Mar 21 03:25:35 PM PDT 24
Finished Mar 21 03:27:19 PM PDT 24
Peak memory 219040 kb
Host smart-6a7f044b-7542-49cc-babd-14a20c777fca
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3011744878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.3011744878
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.2574311683
Short name T213
Test name
Test status
Simulation time 3618968429 ps
CPU time 34.07 seconds
Started Mar 21 03:27:01 PM PDT 24
Finished Mar 21 03:27:36 PM PDT 24
Peak memory 216312 kb
Host smart-89d702c5-4eab-4c07-9cb4-35df3c570989
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2574311683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.2574311683
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.3461527102
Short name T128
Test name
Test status
Simulation time 100740644 ps
CPU time 3.84 seconds
Started Mar 21 03:23:52 PM PDT 24
Finished Mar 21 03:23:56 PM PDT 24
Peak memory 214812 kb
Host smart-9f6ffb28-a6f7-42cb-a3ae-fe3650599054
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3461527102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.3461527102
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_stress_all_with_rand_reset.912390947
Short name T6
Test name
Test status
Simulation time 702040340 ps
CPU time 11.23 seconds
Started Mar 21 03:26:14 PM PDT 24
Finished Mar 21 03:26:25 PM PDT 24
Peak memory 223080 kb
Host smart-0a0c128d-ed94-4bb9-96f0-054db85bfba8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=912390947 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all_with_rand_reset.912390947
Directory /workspace/38.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.2934993623
Short name T163
Test name
Test status
Simulation time 639559889 ps
CPU time 8.69 seconds
Started Mar 21 01:22:22 PM PDT 24
Finished Mar 21 01:22:31 PM PDT 24
Peak memory 214172 kb
Host smart-7d145266-62e7-4f8f-9ed9-5e0fa4e3b359
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934993623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_er
r.2934993623
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.2365688699
Short name T333
Test name
Test status
Simulation time 183431828 ps
CPU time 7.72 seconds
Started Mar 21 03:24:26 PM PDT 24
Finished Mar 21 03:24:34 PM PDT 24
Peak memory 214876 kb
Host smart-4c87920d-69a7-453a-b89c-1025bd815180
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2365688699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.2365688699
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.3392790698
Short name T142
Test name
Test status
Simulation time 178880060 ps
CPU time 2.53 seconds
Started Mar 21 03:25:37 PM PDT 24
Finished Mar 21 03:25:40 PM PDT 24
Peak memory 223160 kb
Host smart-5510c68d-66a7-430c-8fc8-aa62f589eea1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3392790698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.3392790698
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.3948343286
Short name T296
Test name
Test status
Simulation time 67435362 ps
CPU time 2.58 seconds
Started Mar 21 03:24:30 PM PDT 24
Finished Mar 21 03:24:32 PM PDT 24
Peak memory 207360 kb
Host smart-60876e91-11c8-4da2-b7d5-d07df5742c33
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3948343286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.3948343286
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.3899228231
Short name T28
Test name
Test status
Simulation time 177447763 ps
CPU time 4.66 seconds
Started Mar 21 03:24:44 PM PDT 24
Finished Mar 21 03:24:49 PM PDT 24
Peak memory 222820 kb
Host smart-c557c628-ea94-4b43-9729-76bf0e1f96eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899228231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.3899228231
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.1566614552
Short name T360
Test name
Test status
Simulation time 6254938009 ps
CPU time 27.31 seconds
Started Mar 21 03:24:59 PM PDT 24
Finished Mar 21 03:25:26 PM PDT 24
Peak memory 216308 kb
Host smart-5b2c51ef-38e6-4936-a848-a4a6f6f47a7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1566614552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.1566614552
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.1251488222
Short name T51
Test name
Test status
Simulation time 316335880 ps
CPU time 2.61 seconds
Started Mar 21 03:25:00 PM PDT 24
Finished Mar 21 03:25:03 PM PDT 24
Peak memory 210680 kb
Host smart-617ad2a9-41c2-4853-998a-4fdb8e437509
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251488222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.1251488222
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.2245806393
Short name T218
Test name
Test status
Simulation time 138089973 ps
CPU time 7.68 seconds
Started Mar 21 03:26:45 PM PDT 24
Finished Mar 21 03:26:53 PM PDT 24
Peak memory 216268 kb
Host smart-c4ff7f16-18eb-4e36-ac43-f5711a8d383b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2245806393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.2245806393
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.28452541
Short name T158
Test name
Test status
Simulation time 364296418 ps
CPU time 5.56 seconds
Started Mar 21 01:22:24 PM PDT 24
Finished Mar 21 01:22:29 PM PDT 24
Peak memory 209600 kb
Host smart-4cc85481-4ff1-4030-832c-793131ea6ceb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28452541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_err.28452541
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.3536449134
Short name T141
Test name
Test status
Simulation time 3095128643 ps
CPU time 37.78 seconds
Started Mar 21 03:26:14 PM PDT 24
Finished Mar 21 03:26:52 PM PDT 24
Peak memory 218608 kb
Host smart-3abcce14-4568-4da5-9b33-051f3d8e9df9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536449134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.3536449134
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.1486947332
Short name T438
Test name
Test status
Simulation time 215210205 ps
CPU time 2.65 seconds
Started Mar 21 03:25:36 PM PDT 24
Finished Mar 21 03:25:39 PM PDT 24
Peak memory 208912 kb
Host smart-0edc7fdd-3bc3-4513-a469-a6d2ab390f69
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1486947332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.1486947332
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.3161848792
Short name T342
Test name
Test status
Simulation time 4858309092 ps
CPU time 48.72 seconds
Started Mar 21 03:26:18 PM PDT 24
Finished Mar 21 03:27:07 PM PDT 24
Peak memory 216332 kb
Host smart-c63bee51-b9af-4c0c-8a96-b077b5f81651
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161848792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.3161848792
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.2352699955
Short name T193
Test name
Test status
Simulation time 42109643 ps
CPU time 3.03 seconds
Started Mar 21 03:26:43 PM PDT 24
Finished Mar 21 03:26:46 PM PDT 24
Peak memory 214664 kb
Host smart-4ab7aa81-63d4-4e4b-a04d-5cfdd0d000c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2352699955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.2352699955
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.1920891449
Short name T302
Test name
Test status
Simulation time 470467068 ps
CPU time 5.8 seconds
Started Mar 21 03:23:55 PM PDT 24
Finished Mar 21 03:24:01 PM PDT 24
Peak memory 211396 kb
Host smart-7a80772c-95ef-417c-b0ce-11ae9cdd8ee1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1920891449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.1920891449
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.2045974810
Short name T143
Test name
Test status
Simulation time 268841135 ps
CPU time 7.53 seconds
Started Mar 21 03:24:44 PM PDT 24
Finished Mar 21 03:24:52 PM PDT 24
Peak memory 223204 kb
Host smart-b546dd99-5b6e-4563-98ed-302491181db2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2045974810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.2045974810
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.3545584114
Short name T145
Test name
Test status
Simulation time 420356285 ps
CPU time 9.94 seconds
Started Mar 21 03:25:35 PM PDT 24
Finished Mar 21 03:25:46 PM PDT 24
Peak memory 217212 kb
Host smart-648e456a-4f63-437e-9006-ba06f3b30c0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3545584114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.3545584114
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.3986538476
Short name T146
Test name
Test status
Simulation time 158221201 ps
CPU time 1.96 seconds
Started Mar 21 03:25:56 PM PDT 24
Finished Mar 21 03:25:58 PM PDT 24
Peak memory 218312 kb
Host smart-89ce6f94-a020-48c1-b564-e25a2652c553
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986538476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.3986538476
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.2246208289
Short name T54
Test name
Test status
Simulation time 124412418 ps
CPU time 5.04 seconds
Started Mar 21 03:23:41 PM PDT 24
Finished Mar 21 03:23:47 PM PDT 24
Peak memory 210016 kb
Host smart-208f350d-0665-43e8-9cee-b1c62609737a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246208289 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.2246208289
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.1973404067
Short name T232
Test name
Test status
Simulation time 232668643 ps
CPU time 3.15 seconds
Started Mar 21 03:23:41 PM PDT 24
Finished Mar 21 03:23:45 PM PDT 24
Peak memory 208008 kb
Host smart-db0e8d5a-de41-4540-b362-f91da0281adc
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1973404067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.1973404067
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.3897777918
Short name T262
Test name
Test status
Simulation time 3978277322 ps
CPU time 15.73 seconds
Started Mar 21 03:24:27 PM PDT 24
Finished Mar 21 03:24:43 PM PDT 24
Peak memory 209204 kb
Host smart-1a42697b-6393-432f-9e27-7faadc68691c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897777918 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.3897777918
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.1834194771
Short name T372
Test name
Test status
Simulation time 58181128 ps
CPU time 3.11 seconds
Started Mar 21 03:24:57 PM PDT 24
Finished Mar 21 03:25:01 PM PDT 24
Peak memory 214792 kb
Host smart-25c475d2-6d3b-4dad-8fa1-5e6cb1af5136
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1834194771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.1834194771
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.2407544559
Short name T24
Test name
Test status
Simulation time 111019247 ps
CPU time 4.26 seconds
Started Mar 21 03:25:10 PM PDT 24
Finished Mar 21 03:25:15 PM PDT 24
Peak memory 222776 kb
Host smart-ac702dad-9f13-4b03-b0d8-3060fd1c3a5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2407544559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.2407544559
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.4246618417
Short name T303
Test name
Test status
Simulation time 609177914 ps
CPU time 6.9 seconds
Started Mar 21 03:25:22 PM PDT 24
Finished Mar 21 03:25:29 PM PDT 24
Peak memory 222892 kb
Host smart-575dc318-2e68-4973-a2ea-1a112583a284
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4246618417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.4246618417
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_stress_all_with_rand_reset.2671775999
Short name T212
Test name
Test status
Simulation time 1151472227 ps
CPU time 26.9 seconds
Started Mar 21 03:25:20 PM PDT 24
Finished Mar 21 03:25:47 PM PDT 24
Peak memory 223128 kb
Host smart-afa403c5-6144-4838-9c63-cb7068b0aace
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2671775999 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all_with_rand_reset.2671775999
Directory /workspace/23.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.196698369
Short name T86
Test name
Test status
Simulation time 59796547 ps
CPU time 2.69 seconds
Started Mar 21 03:25:49 PM PDT 24
Finished Mar 21 03:25:52 PM PDT 24
Peak memory 209820 kb
Host smart-9221cb1a-0f13-48c6-a41f-4084e7cf68ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=196698369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.196698369
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.3950637553
Short name T229
Test name
Test status
Simulation time 53055311 ps
CPU time 3.14 seconds
Started Mar 21 03:25:49 PM PDT 24
Finished Mar 21 03:25:53 PM PDT 24
Peak memory 211088 kb
Host smart-cc4beeda-972d-40a8-aaa3-2d9413cc91ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950637553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.3950637553
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.3979019229
Short name T256
Test name
Test status
Simulation time 1332714534 ps
CPU time 29.89 seconds
Started Mar 21 03:26:01 PM PDT 24
Finished Mar 21 03:26:31 PM PDT 24
Peak memory 216484 kb
Host smart-b6af7293-b88f-4907-ae6d-bfd440fa1240
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979019229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.3979019229
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.3485907191
Short name T306
Test name
Test status
Simulation time 217925202 ps
CPU time 7 seconds
Started Mar 21 03:26:24 PM PDT 24
Finished Mar 21 03:26:31 PM PDT 24
Peak memory 210240 kb
Host smart-fc1f62e5-3dec-4fca-be58-7f9f42ec6a9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3485907191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.3485907191
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.1115282338
Short name T156
Test name
Test status
Simulation time 88682669 ps
CPU time 4.18 seconds
Started Mar 21 01:22:18 PM PDT 24
Finished Mar 21 01:22:22 PM PDT 24
Peak memory 209460 kb
Host smart-390ab5de-91ac-41e0-816a-54ac70ea973f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1115282338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err
.1115282338
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.1161893580
Short name T167
Test name
Test status
Simulation time 477082443 ps
CPU time 8.11 seconds
Started Mar 21 01:22:21 PM PDT 24
Finished Mar 21 01:22:29 PM PDT 24
Peak memory 209288 kb
Host smart-57178041-2bfa-4248-a8c6-b4722cf029ac
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161893580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_er
r.1161893580
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.1152769438
Short name T160
Test name
Test status
Simulation time 112183675 ps
CPU time 3.4 seconds
Started Mar 21 01:22:16 PM PDT 24
Finished Mar 21 01:22:20 PM PDT 24
Peak memory 214228 kb
Host smart-4f26eed4-ec05-43ff-b905-3952da972d48
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152769438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.1152769438
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.2996648797
Short name T164
Test name
Test status
Simulation time 294985199 ps
CPU time 8.6 seconds
Started Mar 21 01:22:15 PM PDT 24
Finished Mar 21 01:22:24 PM PDT 24
Peak memory 209740 kb
Host smart-dcd4c40b-b179-4b68-a351-db473dfa60c2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2996648797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err
.2996648797
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.3965386469
Short name T35
Test name
Test status
Simulation time 252696933 ps
CPU time 2.69 seconds
Started Mar 21 03:24:43 PM PDT 24
Finished Mar 21 03:24:46 PM PDT 24
Peak memory 210232 kb
Host smart-6992d13c-07e7-41b7-a5dc-e044c599bef2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3965386469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.3965386469
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.1838513884
Short name T170
Test name
Test status
Simulation time 94940226 ps
CPU time 1.9 seconds
Started Mar 21 03:23:44 PM PDT 24
Finished Mar 21 03:23:47 PM PDT 24
Peak memory 210772 kb
Host smart-cfe45990-7d3d-415e-a637-bc8ef41d4d7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838513884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.1838513884
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.5950810
Short name T154
Test name
Test status
Simulation time 120544352 ps
CPU time 2.27 seconds
Started Mar 21 03:26:46 PM PDT 24
Finished Mar 21 03:26:48 PM PDT 24
Peak memory 210380 kb
Host smart-ed0a3e23-209c-4921-9537-019e3910a9fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5950810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.5950810
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.3924810867
Short name T144
Test name
Test status
Simulation time 65664092 ps
CPU time 3.2 seconds
Started Mar 21 03:26:13 PM PDT 24
Finished Mar 21 03:26:17 PM PDT 24
Peak memory 218436 kb
Host smart-53d038ae-5c23-401e-b275-b940caa0dd54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3924810867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.3924810867
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.2871666909
Short name T287
Test name
Test status
Simulation time 372961776 ps
CPU time 4.44 seconds
Started Mar 21 03:26:42 PM PDT 24
Finished Mar 21 03:26:47 PM PDT 24
Peak memory 220852 kb
Host smart-5bbfd3c9-c525-4593-bcc4-555d7caea0a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871666909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.2871666909
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.2353377915
Short name T148
Test name
Test status
Simulation time 389316955 ps
CPU time 11.9 seconds
Started Mar 21 03:26:46 PM PDT 24
Finished Mar 21 03:26:59 PM PDT 24
Peak memory 223212 kb
Host smart-19ea7d08-892a-425b-af20-dfb83d0b1718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353377915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.2353377915
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.1245354723
Short name T738
Test name
Test status
Simulation time 204466566 ps
CPU time 3 seconds
Started Mar 21 03:23:28 PM PDT 24
Finished Mar 21 03:23:31 PM PDT 24
Peak memory 209108 kb
Host smart-ae998fe3-c5a0-4653-bd15-16d79c01128f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1245354723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.1245354723
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.2028380410
Short name T354
Test name
Test status
Simulation time 6854291850 ps
CPU time 29.6 seconds
Started Mar 21 03:23:43 PM PDT 24
Finished Mar 21 03:24:13 PM PDT 24
Peak memory 221232 kb
Host smart-7fe9bbd1-5b79-47e1-90b9-c82345fdb618
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028380410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.2028380410
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.3912634173
Short name T729
Test name
Test status
Simulation time 392641030 ps
CPU time 7.86 seconds
Started Mar 21 03:24:05 PM PDT 24
Finished Mar 21 03:24:14 PM PDT 24
Peak memory 208956 kb
Host smart-0677e40e-28b3-4690-8beb-9cd0b567a178
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3912634173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.3912634173
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.2744896828
Short name T62
Test name
Test status
Simulation time 124162916 ps
CPU time 5.57 seconds
Started Mar 21 03:24:27 PM PDT 24
Finished Mar 21 03:24:32 PM PDT 24
Peak memory 220524 kb
Host smart-820f5dd0-7bfa-4559-ba1b-84f79e9850ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2744896828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.2744896828
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.3694849672
Short name T551
Test name
Test status
Simulation time 177126337 ps
CPU time 5.37 seconds
Started Mar 21 03:24:28 PM PDT 24
Finished Mar 21 03:24:34 PM PDT 24
Peak memory 208444 kb
Host smart-43e5e9b2-346f-4e79-bf7c-8c05f6aed3f2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3694849672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.3694849672
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.3795514025
Short name T271
Test name
Test status
Simulation time 558678098 ps
CPU time 3.26 seconds
Started Mar 21 03:24:43 PM PDT 24
Finished Mar 21 03:24:46 PM PDT 24
Peak memory 218812 kb
Host smart-d866d43b-e7b6-4748-bc1a-f1ef974793f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795514025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.3795514025
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.1608228392
Short name T359
Test name
Test status
Simulation time 17717745346 ps
CPU time 77.93 seconds
Started Mar 21 03:24:45 PM PDT 24
Finished Mar 21 03:26:03 PM PDT 24
Peak memory 217316 kb
Host smart-4e20d4a6-8e96-402a-a887-7dfdfb689b61
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1608228392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.1608228392
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.2086330020
Short name T298
Test name
Test status
Simulation time 1234865524 ps
CPU time 45.61 seconds
Started Mar 21 03:24:47 PM PDT 24
Finished Mar 21 03:25:33 PM PDT 24
Peak memory 217072 kb
Host smart-79a6c6c1-2e89-4f22-9979-8420e8d613af
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086330020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.2086330020
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_stress_all_with_rand_reset.3981957215
Short name T52
Test name
Test status
Simulation time 506713053 ps
CPU time 20.58 seconds
Started Mar 21 03:24:57 PM PDT 24
Finished Mar 21 03:25:18 PM PDT 24
Peak memory 223108 kb
Host smart-5580eed1-1f15-4a5b-98d8-a4b6b4759414
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3981957215 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all_with_rand_reset.3981957215
Directory /workspace/17.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.2067252295
Short name T81
Test name
Test status
Simulation time 64055496 ps
CPU time 4.32 seconds
Started Mar 21 03:24:58 PM PDT 24
Finished Mar 21 03:25:02 PM PDT 24
Peak memory 215612 kb
Host smart-8efd54e5-73b9-480d-9168-9b549b209ce3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2067252295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.2067252295
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.3999019409
Short name T197
Test name
Test status
Simulation time 739851931 ps
CPU time 5.88 seconds
Started Mar 21 03:25:02 PM PDT 24
Finished Mar 21 03:25:08 PM PDT 24
Peak memory 211092 kb
Host smart-a6ab5567-6338-4487-b33a-d2b425a45c94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999019409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.3999019409
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.873566922
Short name T379
Test name
Test status
Simulation time 329569890 ps
CPU time 1.85 seconds
Started Mar 21 03:25:02 PM PDT 24
Finished Mar 21 03:25:04 PM PDT 24
Peak memory 210660 kb
Host smart-25e8ef95-884f-4620-a385-bb17f2816c59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=873566922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.873566922
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.2711200562
Short name T274
Test name
Test status
Simulation time 58322197 ps
CPU time 3.45 seconds
Started Mar 21 03:24:59 PM PDT 24
Finished Mar 21 03:25:02 PM PDT 24
Peak memory 222964 kb
Host smart-04ba0dba-3852-444d-81a1-e7a9cd4b50c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711200562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.2711200562
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.2910419509
Short name T316
Test name
Test status
Simulation time 2484982989 ps
CPU time 27.4 seconds
Started Mar 21 03:23:43 PM PDT 24
Finished Mar 21 03:24:12 PM PDT 24
Peak memory 223144 kb
Host smart-88296ccf-4f0f-499b-966b-5e5db8d4f917
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2910419509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.2910419509
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.4257663415
Short name T293
Test name
Test status
Simulation time 208921675 ps
CPU time 3.15 seconds
Started Mar 21 03:25:06 PM PDT 24
Finished Mar 21 03:25:09 PM PDT 24
Peak memory 210040 kb
Host smart-a3108707-1b3e-4730-b4a3-7d81157d18b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257663415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.4257663415
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.3279447470
Short name T314
Test name
Test status
Simulation time 209860562 ps
CPU time 3.5 seconds
Started Mar 21 03:25:19 PM PDT 24
Finished Mar 21 03:25:23 PM PDT 24
Peak memory 210664 kb
Host smart-846a0c8b-817a-4073-a4f2-ecdbfdcba7f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279447470 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.3279447470
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.166372895
Short name T60
Test name
Test status
Simulation time 488734299 ps
CPU time 3.82 seconds
Started Mar 21 03:25:21 PM PDT 24
Finished Mar 21 03:25:25 PM PDT 24
Peak memory 212316 kb
Host smart-be650c57-410b-4287-824b-670cb6750097
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=166372895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.166372895
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_stress_all_with_rand_reset.2838185358
Short name T215
Test name
Test status
Simulation time 2308650216 ps
CPU time 21.05 seconds
Started Mar 21 03:25:36 PM PDT 24
Finished Mar 21 03:25:57 PM PDT 24
Peak memory 223172 kb
Host smart-33653d34-8a9c-4638-9ee0-810009323113
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838185358 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all_with_rand_reset.2838185358
Directory /workspace/25.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.22126949
Short name T210
Test name
Test status
Simulation time 8849404463 ps
CPU time 61.16 seconds
Started Mar 21 03:25:33 PM PDT 24
Finished Mar 21 03:26:34 PM PDT 24
Peak memory 215540 kb
Host smart-fc12b1c7-d72a-4b7a-9b0c-7049842aae96
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22126949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.22126949
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.2823346628
Short name T214
Test name
Test status
Simulation time 110487409 ps
CPU time 5.21 seconds
Started Mar 21 03:25:50 PM PDT 24
Finished Mar 21 03:25:56 PM PDT 24
Peak memory 210728 kb
Host smart-5c9a1d12-c0db-417e-90ab-3411e5aa0af2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823346628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.2823346628
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.878638863
Short name T284
Test name
Test status
Simulation time 1059340809 ps
CPU time 8.87 seconds
Started Mar 21 03:25:55 PM PDT 24
Finished Mar 21 03:26:05 PM PDT 24
Peak memory 222908 kb
Host smart-a369f4b6-f1c0-44ff-9443-926835706cd6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=878638863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.878638863
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.1982754601
Short name T328
Test name
Test status
Simulation time 178390596 ps
CPU time 2.61 seconds
Started Mar 21 03:26:18 PM PDT 24
Finished Mar 21 03:26:21 PM PDT 24
Peak memory 209440 kb
Host smart-7b5be628-13cc-4b73-8f66-6d0ad4dd0ab0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1982754601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.1982754601
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.3165277300
Short name T231
Test name
Test status
Simulation time 291302434 ps
CPU time 4.8 seconds
Started Mar 21 03:26:16 PM PDT 24
Finished Mar 21 03:26:21 PM PDT 24
Peak memory 215860 kb
Host smart-3376efa3-0a2f-4308-b316-cb6c3205cbec
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3165277300 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.3165277300
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.1687641811
Short name T216
Test name
Test status
Simulation time 318368621 ps
CPU time 6.57 seconds
Started Mar 21 03:23:58 PM PDT 24
Finished Mar 21 03:24:05 PM PDT 24
Peak memory 208320 kb
Host smart-433a6b9a-f182-4ba6-a3f3-9992284583fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1687641811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.1687641811
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.2037201597
Short name T949
Test name
Test status
Simulation time 362229689 ps
CPU time 10.47 seconds
Started Mar 21 01:22:18 PM PDT 24
Finished Mar 21 01:22:28 PM PDT 24
Peak memory 205904 kb
Host smart-608385c0-67d1-4ad5-8160-2e6fbe9c8f37
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037201597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.2
037201597
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.2633009453
Short name T915
Test name
Test status
Simulation time 2413904042 ps
CPU time 14.52 seconds
Started Mar 21 01:22:12 PM PDT 24
Finished Mar 21 01:22:26 PM PDT 24
Peak memory 206076 kb
Host smart-fe5d8a5e-ef15-4661-bf0c-78f1860ad601
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633009453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.2
633009453
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.2604295610
Short name T1025
Test name
Test status
Simulation time 71160955 ps
CPU time 1.16 seconds
Started Mar 21 01:22:12 PM PDT 24
Finished Mar 21 01:22:13 PM PDT 24
Peak memory 206060 kb
Host smart-07aeaf40-d0a2-4bd0-95f3-6eb5963da6db
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604295610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.2
604295610
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.390953171
Short name T1017
Test name
Test status
Simulation time 36382322 ps
CPU time 1.82 seconds
Started Mar 21 01:22:18 PM PDT 24
Finished Mar 21 01:22:20 PM PDT 24
Peak memory 205824 kb
Host smart-7b9fd76a-52b0-4483-b0e4-97bef8570150
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=390953171 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.390953171
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.3785808138
Short name T1007
Test name
Test status
Simulation time 20578482 ps
CPU time 0.91 seconds
Started Mar 21 01:22:12 PM PDT 24
Finished Mar 21 01:22:13 PM PDT 24
Peak memory 205856 kb
Host smart-b21954e8-1cc7-46cd-98b3-c1335be82a91
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785808138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.3785808138
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.1343009191
Short name T910
Test name
Test status
Simulation time 13917133 ps
CPU time 0.74 seconds
Started Mar 21 01:22:12 PM PDT 24
Finished Mar 21 01:22:13 PM PDT 24
Peak memory 205596 kb
Host smart-cfe90fa0-a5b2-4503-998d-6fa6f6decdc2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1343009191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.1343009191
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.3361755180
Short name T1016
Test name
Test status
Simulation time 70037320 ps
CPU time 2.42 seconds
Started Mar 21 01:22:10 PM PDT 24
Finished Mar 21 01:22:12 PM PDT 24
Peak memory 206076 kb
Host smart-5a13386d-8e0d-450a-9f6b-ef0f4bd4a140
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3361755180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.3361755180
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.470453775
Short name T1051
Test name
Test status
Simulation time 720019364 ps
CPU time 4.15 seconds
Started Mar 21 01:22:11 PM PDT 24
Finished Mar 21 01:22:15 PM PDT 24
Peak memory 214444 kb
Host smart-7bdee391-82fd-4429-8969-4e6afce32f49
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=470453775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shadow
_reg_errors.470453775
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.63396280
Short name T936
Test name
Test status
Simulation time 87091594 ps
CPU time 4.74 seconds
Started Mar 21 01:22:10 PM PDT 24
Finished Mar 21 01:22:15 PM PDT 24
Peak memory 214380 kb
Host smart-4c9ea0a4-2ecd-41c0-8741-8943c9cbf59b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63396280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_
SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.ke
ymgr_shadow_reg_errors_with_csr_rw.63396280
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.2328531633
Short name T177
Test name
Test status
Simulation time 327257660 ps
CPU time 1.72 seconds
Started Mar 21 01:22:14 PM PDT 24
Finished Mar 21 01:22:16 PM PDT 24
Peak memory 214172 kb
Host smart-ed0bd32e-b5e2-443b-9b0b-740d6089a295
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2328531633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.2328531633
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.4259916639
Short name T157
Test name
Test status
Simulation time 369818822 ps
CPU time 9.31 seconds
Started Mar 21 01:22:08 PM PDT 24
Finished Mar 21 01:22:17 PM PDT 24
Peak memory 209264 kb
Host smart-16227989-4932-4ca6-af51-3fce96bcc1cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4259916639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err
.4259916639
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.649433872
Short name T924
Test name
Test status
Simulation time 278126454 ps
CPU time 4.63 seconds
Started Mar 21 01:22:16 PM PDT 24
Finished Mar 21 01:22:21 PM PDT 24
Peak memory 205988 kb
Host smart-2a939306-8f69-425b-b692-ae4f72956cd0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=649433872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.649433872
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.2546292112
Short name T997
Test name
Test status
Simulation time 545467067 ps
CPU time 6.95 seconds
Started Mar 21 01:22:14 PM PDT 24
Finished Mar 21 01:22:21 PM PDT 24
Peak memory 206032 kb
Host smart-e427ca0d-465d-40ee-abc0-8bbbcb9e3a0c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2546292112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.2
546292112
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.1310213627
Short name T925
Test name
Test status
Simulation time 16911666 ps
CPU time 1.08 seconds
Started Mar 21 01:22:09 PM PDT 24
Finished Mar 21 01:22:11 PM PDT 24
Peak memory 205920 kb
Host smart-b6539907-92b5-43b5-94bd-ebee01245fad
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310213627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.1
310213627
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.42188421
Short name T986
Test name
Test status
Simulation time 25140721 ps
CPU time 1.32 seconds
Started Mar 21 01:22:09 PM PDT 24
Finished Mar 21 01:22:10 PM PDT 24
Peak memory 205972 kb
Host smart-c8275c1e-eebe-493c-b01f-5e38e628fe24
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42188421 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.42188421
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.3516713472
Short name T1021
Test name
Test status
Simulation time 11862927 ps
CPU time 0.94 seconds
Started Mar 21 01:22:10 PM PDT 24
Finished Mar 21 01:22:11 PM PDT 24
Peak memory 205800 kb
Host smart-c653e09f-6279-4c09-998f-b889a4e9fe60
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3516713472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.3516713472
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.961013267
Short name T982
Test name
Test status
Simulation time 31596386 ps
CPU time 0.86 seconds
Started Mar 21 01:22:14 PM PDT 24
Finished Mar 21 01:22:14 PM PDT 24
Peak memory 205624 kb
Host smart-7ff56009-a87e-4fb2-830d-981aaf22766e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961013267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.961013267
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.977946492
Short name T1053
Test name
Test status
Simulation time 230237212 ps
CPU time 3.63 seconds
Started Mar 21 01:22:11 PM PDT 24
Finished Mar 21 01:22:15 PM PDT 24
Peak memory 206048 kb
Host smart-94193a5b-b0a9-45d1-90e1-e5e427e95758
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977946492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sam
e_csr_outstanding.977946492
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.3846545473
Short name T115
Test name
Test status
Simulation time 494032652 ps
CPU time 10.74 seconds
Started Mar 21 01:22:11 PM PDT 24
Finished Mar 21 01:22:22 PM PDT 24
Peak memory 214444 kb
Host smart-ce32eb20-d120-4a66-bdb6-0e939e956c22
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3846545473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.3846545473
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.100236465
Short name T111
Test name
Test status
Simulation time 227506173 ps
CPU time 5.34 seconds
Started Mar 21 01:22:11 PM PDT 24
Finished Mar 21 01:22:17 PM PDT 24
Peak memory 214396 kb
Host smart-1e61eec5-bbe4-4e3f-b327-e510bd9277ff
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=100236465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.k
eymgr_shadow_reg_errors_with_csr_rw.100236465
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.2388104194
Short name T943
Test name
Test status
Simulation time 168872691 ps
CPU time 3.21 seconds
Started Mar 21 01:22:15 PM PDT 24
Finished Mar 21 01:22:18 PM PDT 24
Peak memory 214092 kb
Host smart-8fabf7f7-0361-4350-8341-87a0e20d8b80
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2388104194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.2388104194
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.3916506855
Short name T1070
Test name
Test status
Simulation time 167126679 ps
CPU time 1.54 seconds
Started Mar 21 01:22:21 PM PDT 24
Finished Mar 21 01:22:22 PM PDT 24
Peak memory 214128 kb
Host smart-01bc28b0-5c1a-4bda-9f35-fe42c1145be2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3916506855 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.3916506855
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.2060392045
Short name T138
Test name
Test status
Simulation time 47796928 ps
CPU time 1.11 seconds
Started Mar 21 01:22:22 PM PDT 24
Finished Mar 21 01:22:23 PM PDT 24
Peak memory 205952 kb
Host smart-a672545d-c08b-4a21-afc7-f0f6431d343e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060392045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.2060392045
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.2581975357
Short name T1066
Test name
Test status
Simulation time 20679516 ps
CPU time 0.83 seconds
Started Mar 21 01:22:19 PM PDT 24
Finished Mar 21 01:22:20 PM PDT 24
Peak memory 205668 kb
Host smart-4cc89380-1e16-493e-aad6-ee26a45cf2b8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2581975357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.2581975357
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.1094331960
Short name T1061
Test name
Test status
Simulation time 59832151 ps
CPU time 2.21 seconds
Started Mar 21 01:22:18 PM PDT 24
Finished Mar 21 01:22:21 PM PDT 24
Peak memory 205976 kb
Host smart-f3fbd6a6-f9d2-4e7c-9d85-352308a8ec92
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094331960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.1094331960
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.811134624
Short name T117
Test name
Test status
Simulation time 95495860 ps
CPU time 2.73 seconds
Started Mar 21 01:22:23 PM PDT 24
Finished Mar 21 01:22:26 PM PDT 24
Peak memory 214596 kb
Host smart-e6a7c39c-d733-4308-8fb8-d184af5cf2f1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=811134624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shado
w_reg_errors.811134624
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.3627511786
Short name T934
Test name
Test status
Simulation time 207685234 ps
CPU time 7.73 seconds
Started Mar 21 01:22:23 PM PDT 24
Finished Mar 21 01:22:30 PM PDT 24
Peak memory 214508 kb
Host smart-82c73396-9f3a-46e1-b6d4-a3d24b6a5ac8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3627511786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.keymgr_shadow_reg_errors_with_csr_rw.3627511786
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.2132290706
Short name T1032
Test name
Test status
Simulation time 22331130 ps
CPU time 1.94 seconds
Started Mar 21 01:22:27 PM PDT 24
Finished Mar 21 01:22:29 PM PDT 24
Peak memory 214192 kb
Host smart-35924eec-3b4c-40d4-842d-38e9436a2260
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2132290706 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.2132290706
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.1389184285
Short name T960
Test name
Test status
Simulation time 24131087 ps
CPU time 1.16 seconds
Started Mar 21 01:22:21 PM PDT 24
Finished Mar 21 01:22:22 PM PDT 24
Peak memory 206064 kb
Host smart-90a28dd8-c43c-4ba8-bb9e-c422fd0f30b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1389184285 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.1389184285
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.2697478140
Short name T137
Test name
Test status
Simulation time 13941711 ps
CPU time 1.21 seconds
Started Mar 21 01:22:21 PM PDT 24
Finished Mar 21 01:22:22 PM PDT 24
Peak memory 205980 kb
Host smart-a653cfdc-213e-4f35-ab41-5cb0448c3a54
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2697478140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.2697478140
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.3891949584
Short name T1036
Test name
Test status
Simulation time 41394903 ps
CPU time 0.67 seconds
Started Mar 21 01:22:22 PM PDT 24
Finished Mar 21 01:22:22 PM PDT 24
Peak memory 205572 kb
Host smart-d3d94160-ce84-4c50-a74b-b28f2f39719d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891949584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.3891949584
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.2936994822
Short name T136
Test name
Test status
Simulation time 343365918 ps
CPU time 2.67 seconds
Started Mar 21 01:22:21 PM PDT 24
Finished Mar 21 01:22:23 PM PDT 24
Peak memory 205968 kb
Host smart-ef39be0e-3ea6-4fde-b07c-5f9321cb43a0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2936994822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s
ame_csr_outstanding.2936994822
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.1722517348
Short name T973
Test name
Test status
Simulation time 251946408 ps
CPU time 6.43 seconds
Started Mar 21 01:22:17 PM PDT 24
Finished Mar 21 01:22:24 PM PDT 24
Peak memory 222716 kb
Host smart-858209c7-710d-430e-abfa-e1e8fc258601
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722517348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.1722517348
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.1340376687
Short name T1012
Test name
Test status
Simulation time 780226795 ps
CPU time 6.8 seconds
Started Mar 21 01:22:25 PM PDT 24
Finished Mar 21 01:22:32 PM PDT 24
Peak memory 214644 kb
Host smart-eb1636a3-c6db-4550-ae64-dabc7399c2a4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1340376687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.1340376687
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.2835067763
Short name T1042
Test name
Test status
Simulation time 23834537 ps
CPU time 2.04 seconds
Started Mar 21 01:22:24 PM PDT 24
Finished Mar 21 01:22:26 PM PDT 24
Peak memory 214196 kb
Host smart-a7e5eef5-9c5b-430f-a811-16e0c95d189a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2835067763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.2835067763
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.1333732851
Short name T1038
Test name
Test status
Simulation time 529019922 ps
CPU time 11.51 seconds
Started Mar 21 01:22:27 PM PDT 24
Finished Mar 21 01:22:39 PM PDT 24
Peak memory 209716 kb
Host smart-2d1cdf3a-4d4a-4859-a44c-34921aed6fde
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1333732851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.1333732851
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.26292600
Short name T976
Test name
Test status
Simulation time 106265310 ps
CPU time 1.23 seconds
Started Mar 21 01:22:23 PM PDT 24
Finished Mar 21 01:22:24 PM PDT 24
Peak memory 205960 kb
Host smart-f0ef192b-d853-4d19-bb88-c218dd616ef8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26292600 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.26292600
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.2182947100
Short name T132
Test name
Test status
Simulation time 105236205 ps
CPU time 1.23 seconds
Started Mar 21 01:22:24 PM PDT 24
Finished Mar 21 01:22:26 PM PDT 24
Peak memory 206060 kb
Host smart-6c3b120a-f511-4687-b155-8f9a45261bdf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2182947100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.2182947100
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.720417637
Short name T913
Test name
Test status
Simulation time 13243811 ps
CPU time 0.91 seconds
Started Mar 21 01:22:27 PM PDT 24
Finished Mar 21 01:22:28 PM PDT 24
Peak memory 205680 kb
Host smart-b1529ab0-9e44-497f-9b31-c791bc477b7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=720417637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.720417637
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.1426513927
Short name T139
Test name
Test status
Simulation time 451209004 ps
CPU time 2.9 seconds
Started Mar 21 01:22:22 PM PDT 24
Finished Mar 21 01:22:25 PM PDT 24
Peak memory 214232 kb
Host smart-c09daad9-8ef8-473d-97d7-7c413d01da6f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1426513927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.1426513927
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.2153009721
Short name T1033
Test name
Test status
Simulation time 182725941 ps
CPU time 5.57 seconds
Started Mar 21 01:22:26 PM PDT 24
Finished Mar 21 01:22:32 PM PDT 24
Peak memory 214572 kb
Host smart-7cfebd99-2e00-41c6-8df5-92bb4979ee00
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2153009721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shad
ow_reg_errors.2153009721
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.2509025205
Short name T1023
Test name
Test status
Simulation time 140840044 ps
CPU time 5.48 seconds
Started Mar 21 01:22:27 PM PDT 24
Finished Mar 21 01:22:33 PM PDT 24
Peak memory 216548 kb
Host smart-61075cc7-4d2e-4d28-825d-af0028d23315
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509025205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.2509025205
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.3631007339
Short name T918
Test name
Test status
Simulation time 51005611 ps
CPU time 1.38 seconds
Started Mar 21 01:22:26 PM PDT 24
Finished Mar 21 01:22:28 PM PDT 24
Peak memory 205884 kb
Host smart-c5bb5871-2486-4223-919b-2678fba1a6d7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3631007339 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.3631007339
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.3096756541
Short name T1039
Test name
Test status
Simulation time 21615765 ps
CPU time 1.21 seconds
Started Mar 21 01:22:25 PM PDT 24
Finished Mar 21 01:22:26 PM PDT 24
Peak memory 206048 kb
Host smart-a91b815c-bb07-4511-b2f4-79d4f318b869
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3096756541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.3096756541
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.4121770550
Short name T1064
Test name
Test status
Simulation time 17186265 ps
CPU time 0.86 seconds
Started Mar 21 01:22:23 PM PDT 24
Finished Mar 21 01:22:24 PM PDT 24
Peak memory 205616 kb
Host smart-76e38609-9e49-401f-9817-530aa4109edb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4121770550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.4121770550
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.1484813266
Short name T1067
Test name
Test status
Simulation time 59655713 ps
CPU time 2.29 seconds
Started Mar 21 01:22:27 PM PDT 24
Finished Mar 21 01:22:30 PM PDT 24
Peak memory 205964 kb
Host smart-ce8739df-ce24-4055-b9b2-a6e90dd749f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1484813266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_s
ame_csr_outstanding.1484813266
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.3510460005
Short name T121
Test name
Test status
Simulation time 4582089431 ps
CPU time 25.6 seconds
Started Mar 21 01:22:22 PM PDT 24
Finished Mar 21 01:22:48 PM PDT 24
Peak memory 220672 kb
Host smart-44ebd328-8337-4d71-995f-a05b7114ce81
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3510460005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.3510460005
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.3125775038
Short name T1034
Test name
Test status
Simulation time 667177425 ps
CPU time 8.9 seconds
Started Mar 21 01:22:19 PM PDT 24
Finished Mar 21 01:22:28 PM PDT 24
Peak memory 214452 kb
Host smart-94bd311e-9918-485c-90fe-a10c6ff98123
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125775038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.3125775038
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.3440127490
Short name T926
Test name
Test status
Simulation time 124225790 ps
CPU time 2.96 seconds
Started Mar 21 01:22:23 PM PDT 24
Finished Mar 21 01:22:26 PM PDT 24
Peak memory 214232 kb
Host smart-1a5e8fc0-f91d-4eef-b957-f23cf92e875a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3440127490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.3440127490
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.153992086
Short name T149
Test name
Test status
Simulation time 456630293 ps
CPU time 5.59 seconds
Started Mar 21 01:22:27 PM PDT 24
Finished Mar 21 01:22:33 PM PDT 24
Peak memory 209300 kb
Host smart-8b5fbfa1-e56d-46f2-b0b9-6c639fa8bcda
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=153992086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_err
.153992086
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.3785208975
Short name T928
Test name
Test status
Simulation time 60286977 ps
CPU time 1.44 seconds
Started Mar 21 01:22:24 PM PDT 24
Finished Mar 21 01:22:25 PM PDT 24
Peak memory 214252 kb
Host smart-6a527b15-208b-450f-b187-a2e6910d6726
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3785208975 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.3785208975
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.4194507805
Short name T952
Test name
Test status
Simulation time 99011406 ps
CPU time 1.07 seconds
Started Mar 21 01:22:23 PM PDT 24
Finished Mar 21 01:22:24 PM PDT 24
Peak memory 206056 kb
Host smart-839a79f8-a6a0-4cd3-804b-0a9e1934b864
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194507805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.4194507805
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.4123845791
Short name T946
Test name
Test status
Simulation time 34403952 ps
CPU time 0.85 seconds
Started Mar 21 01:22:25 PM PDT 24
Finished Mar 21 01:22:26 PM PDT 24
Peak memory 205652 kb
Host smart-94ea43c3-f906-43d4-a7aa-2c53ef8ec2e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123845791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.4123845791
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.354851683
Short name T978
Test name
Test status
Simulation time 240582254 ps
CPU time 2.05 seconds
Started Mar 21 01:22:19 PM PDT 24
Finished Mar 21 01:22:21 PM PDT 24
Peak memory 205984 kb
Host smart-f1f5694e-9a0a-4fdf-af97-8ebe0c9fca0d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354851683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_sa
me_csr_outstanding.354851683
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.529069904
Short name T119
Test name
Test status
Simulation time 118531699 ps
CPU time 2.19 seconds
Started Mar 21 01:22:23 PM PDT 24
Finished Mar 21 01:22:26 PM PDT 24
Peak memory 214588 kb
Host smart-91ebdf4f-e434-433c-8e8d-d8a8d0217321
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=529069904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shado
w_reg_errors.529069904
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.1949317895
Short name T1011
Test name
Test status
Simulation time 1558425792 ps
CPU time 5.33 seconds
Started Mar 21 01:22:24 PM PDT 24
Finished Mar 21 01:22:30 PM PDT 24
Peak memory 220632 kb
Host smart-a969bb38-71b6-4492-aa79-4d1e8d0901bb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1949317895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.1949317895
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.826775680
Short name T999
Test name
Test status
Simulation time 73996971 ps
CPU time 2.89 seconds
Started Mar 21 01:22:26 PM PDT 24
Finished Mar 21 01:22:29 PM PDT 24
Peak memory 214088 kb
Host smart-d964c0ab-1cab-4716-bc1a-f6cf27c69006
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826775680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.826775680
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.3825835705
Short name T151
Test name
Test status
Simulation time 430778516 ps
CPU time 5.1 seconds
Started Mar 21 01:22:23 PM PDT 24
Finished Mar 21 01:22:28 PM PDT 24
Peak memory 214100 kb
Host smart-3fb8adbc-6b23-4b46-a7db-9e41673f0013
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3825835705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.3825835705
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.1938656209
Short name T921
Test name
Test status
Simulation time 34998717 ps
CPU time 2.32 seconds
Started Mar 21 01:22:26 PM PDT 24
Finished Mar 21 01:22:29 PM PDT 24
Peak memory 214180 kb
Host smart-d205bb44-557d-43bd-8c24-eec83b3ef396
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1938656209 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.1938656209
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.62647285
Short name T929
Test name
Test status
Simulation time 119610571 ps
CPU time 1.15 seconds
Started Mar 21 01:22:24 PM PDT 24
Finished Mar 21 01:22:25 PM PDT 24
Peak memory 206020 kb
Host smart-709c853a-5053-4eb2-856a-c0a3f50526c2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62647285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.62647285
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.664209715
Short name T953
Test name
Test status
Simulation time 43335388 ps
CPU time 0.72 seconds
Started Mar 21 01:22:18 PM PDT 24
Finished Mar 21 01:22:19 PM PDT 24
Peak memory 205748 kb
Host smart-bc39898d-bb58-483e-8704-74869ecbd313
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=664209715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.664209715
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.354701613
Short name T1022
Test name
Test status
Simulation time 38843710 ps
CPU time 1.38 seconds
Started Mar 21 01:22:21 PM PDT 24
Finished Mar 21 01:22:22 PM PDT 24
Peak memory 205984 kb
Host smart-cee04c26-34da-4120-9070-931b93ac08c0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=354701613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_sa
me_csr_outstanding.354701613
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.1745557870
Short name T974
Test name
Test status
Simulation time 1649027625 ps
CPU time 10.69 seconds
Started Mar 21 01:22:18 PM PDT 24
Finished Mar 21 01:22:29 PM PDT 24
Peak memory 214576 kb
Host smart-e9befb93-77a6-4238-83a7-bfcad24a4da5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1745557870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.1745557870
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.159147415
Short name T998
Test name
Test status
Simulation time 348650518 ps
CPU time 2.66 seconds
Started Mar 21 01:22:25 PM PDT 24
Finished Mar 21 01:22:28 PM PDT 24
Peak memory 214096 kb
Host smart-151799de-1fa0-46a7-b80b-89bdaba1c0e6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=159147415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.159147415
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.795934229
Short name T176
Test name
Test status
Simulation time 355520683 ps
CPU time 2.47 seconds
Started Mar 21 01:22:25 PM PDT 24
Finished Mar 21 01:22:27 PM PDT 24
Peak memory 214244 kb
Host smart-59423cd9-dbb9-4c8b-83f2-806b9d941f20
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795934229 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.795934229
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.1559563238
Short name T1043
Test name
Test status
Simulation time 16674013 ps
CPU time 1.04 seconds
Started Mar 21 01:22:24 PM PDT 24
Finished Mar 21 01:22:25 PM PDT 24
Peak memory 205964 kb
Host smart-c4d8ec7f-b10b-4ef7-943f-c75d008e880b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1559563238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.1559563238
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.4111084446
Short name T1040
Test name
Test status
Simulation time 17539320 ps
CPU time 0.72 seconds
Started Mar 21 01:22:27 PM PDT 24
Finished Mar 21 01:22:28 PM PDT 24
Peak memory 205756 kb
Host smart-f8c932a9-5638-4305-a4ad-9f19fa34db6c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4111084446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.4111084446
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.2086706013
Short name T992
Test name
Test status
Simulation time 442860913 ps
CPU time 4.35 seconds
Started Mar 21 01:22:24 PM PDT 24
Finished Mar 21 01:22:28 PM PDT 24
Peak memory 206016 kb
Host smart-03788ef9-ed75-4369-aef6-9fc2ce8b6052
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2086706013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.2086706013
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.1311535771
Short name T996
Test name
Test status
Simulation time 401731582 ps
CPU time 2.69 seconds
Started Mar 21 01:22:27 PM PDT 24
Finished Mar 21 01:22:30 PM PDT 24
Peak memory 214620 kb
Host smart-61d6f084-1652-44e8-ac99-8cd94c567c99
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311535771 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.1311535771
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.3242999200
Short name T1020
Test name
Test status
Simulation time 2827684538 ps
CPU time 4.17 seconds
Started Mar 21 01:22:25 PM PDT 24
Finished Mar 21 01:22:29 PM PDT 24
Peak memory 214340 kb
Host smart-3fc1cc82-a0f3-4e3d-99f7-c9b6768027fe
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3242999200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.3242999200
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.2497746693
Short name T166
Test name
Test status
Simulation time 398937170 ps
CPU time 8.71 seconds
Started Mar 21 01:22:25 PM PDT 24
Finished Mar 21 01:22:34 PM PDT 24
Peak memory 209576 kb
Host smart-d0080fd2-2a8c-4e7b-8131-ad2eb47bcb9e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2497746693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.2497746693
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.4275111732
Short name T1044
Test name
Test status
Simulation time 32545827 ps
CPU time 2.26 seconds
Started Mar 21 01:22:21 PM PDT 24
Finished Mar 21 01:22:23 PM PDT 24
Peak memory 214056 kb
Host smart-c22d2410-e7e4-4a5d-9f44-7d457dd8d1e7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4275111732 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.4275111732
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.580498320
Short name T1047
Test name
Test status
Simulation time 24342851 ps
CPU time 1.47 seconds
Started Mar 21 01:22:25 PM PDT 24
Finished Mar 21 01:22:26 PM PDT 24
Peak memory 205980 kb
Host smart-b3a74c2e-9d1b-41e2-afc9-d79a7dc3480e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580498320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.580498320
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.1285015853
Short name T1002
Test name
Test status
Simulation time 55356357 ps
CPU time 0.73 seconds
Started Mar 21 01:22:27 PM PDT 24
Finished Mar 21 01:22:28 PM PDT 24
Peak memory 205756 kb
Host smart-a6595d76-2a88-4d6b-90fa-64a607a8ee76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285015853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.1285015853
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.2415172941
Short name T1062
Test name
Test status
Simulation time 190486529 ps
CPU time 2.49 seconds
Started Mar 21 01:22:27 PM PDT 24
Finished Mar 21 01:22:29 PM PDT 24
Peak memory 206136 kb
Host smart-aa291c72-429a-47f4-8377-3abd8e570220
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2415172941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.2415172941
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.3649892755
Short name T932
Test name
Test status
Simulation time 390968034 ps
CPU time 2.66 seconds
Started Mar 21 01:22:24 PM PDT 24
Finished Mar 21 01:22:27 PM PDT 24
Peak memory 214380 kb
Host smart-de5dc236-a673-443a-92cc-c80c6c183e05
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649892755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shad
ow_reg_errors.3649892755
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.2167385635
Short name T954
Test name
Test status
Simulation time 206689124 ps
CPU time 7.94 seconds
Started Mar 21 01:22:27 PM PDT 24
Finished Mar 21 01:22:35 PM PDT 24
Peak memory 214680 kb
Host smart-bd19f4b3-6e15-4df6-a033-1d64b8ed741c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2167385635 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.keymgr_shadow_reg_errors_with_csr_rw.2167385635
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.1005482346
Short name T957
Test name
Test status
Simulation time 114056731 ps
CPU time 1.86 seconds
Started Mar 21 01:22:23 PM PDT 24
Finished Mar 21 01:22:25 PM PDT 24
Peak memory 214152 kb
Host smart-1d1f3ea1-2fd4-4154-abbb-8a2633a693b8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005482346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.1005482346
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.2857068950
Short name T989
Test name
Test status
Simulation time 162388730 ps
CPU time 2.05 seconds
Started Mar 21 01:22:25 PM PDT 24
Finished Mar 21 01:22:27 PM PDT 24
Peak memory 214152 kb
Host smart-f205298f-166f-4c0b-9afb-c8dd6c1d00b7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2857068950 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.2857068950
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.857196681
Short name T1060
Test name
Test status
Simulation time 120851067 ps
CPU time 1.66 seconds
Started Mar 21 01:22:24 PM PDT 24
Finished Mar 21 01:22:26 PM PDT 24
Peak memory 206056 kb
Host smart-7c661d79-f232-475b-b0b5-6b6a397efe90
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857196681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.857196681
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.2411951856
Short name T919
Test name
Test status
Simulation time 15659795 ps
CPU time 0.72 seconds
Started Mar 21 01:22:25 PM PDT 24
Finished Mar 21 01:22:25 PM PDT 24
Peak memory 205680 kb
Host smart-aba6e3c6-2d48-4a50-bdc4-ab1acc370eb7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2411951856 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.2411951856
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.2707865595
Short name T1031
Test name
Test status
Simulation time 38321489 ps
CPU time 1.35 seconds
Started Mar 21 01:22:25 PM PDT 24
Finished Mar 21 01:22:26 PM PDT 24
Peak memory 206032 kb
Host smart-4cd46291-2edb-4696-a91e-22144ffc652b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707865595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.2707865595
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.2878267980
Short name T963
Test name
Test status
Simulation time 194162084 ps
CPU time 3.53 seconds
Started Mar 21 01:22:23 PM PDT 24
Finished Mar 21 01:22:27 PM PDT 24
Peak memory 222612 kb
Host smart-0e61d2f7-ceaa-447a-ba4b-7e254b4631fe
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878267980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.2878267980
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.706201972
Short name T118
Test name
Test status
Simulation time 286903035 ps
CPU time 8.69 seconds
Started Mar 21 01:22:25 PM PDT 24
Finished Mar 21 01:22:33 PM PDT 24
Peak memory 214536 kb
Host smart-98e5db5a-d646-499a-ab33-f3bcfd3d73f9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=706201972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.
keymgr_shadow_reg_errors_with_csr_rw.706201972
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.2944977389
Short name T988
Test name
Test status
Simulation time 243834521 ps
CPU time 2.76 seconds
Started Mar 21 01:22:24 PM PDT 24
Finished Mar 21 01:22:27 PM PDT 24
Peak memory 217320 kb
Host smart-a954fa7f-f7d6-400b-98be-690129432a7f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2944977389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.2944977389
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.3226521570
Short name T938
Test name
Test status
Simulation time 118648055 ps
CPU time 1.89 seconds
Started Mar 21 01:22:22 PM PDT 24
Finished Mar 21 01:22:24 PM PDT 24
Peak memory 214060 kb
Host smart-f6b1bdd4-c818-4c4f-8a42-93ba76c7ef80
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3226521570 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.3226521570
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.4198871865
Short name T133
Test name
Test status
Simulation time 26453519 ps
CPU time 0.98 seconds
Started Mar 21 01:22:23 PM PDT 24
Finished Mar 21 01:22:29 PM PDT 24
Peak memory 205720 kb
Host smart-f79d3862-678a-4046-9ac1-517944836e8e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198871865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.4198871865
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.3889571223
Short name T1006
Test name
Test status
Simulation time 44660460 ps
CPU time 0.74 seconds
Started Mar 21 01:22:24 PM PDT 24
Finished Mar 21 01:22:25 PM PDT 24
Peak memory 205660 kb
Host smart-46337077-1c85-40bc-806f-b4bcf25cf9d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889571223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.3889571223
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.2839358902
Short name T965
Test name
Test status
Simulation time 166280494 ps
CPU time 1.88 seconds
Started Mar 21 01:22:24 PM PDT 24
Finished Mar 21 01:22:26 PM PDT 24
Peak memory 205976 kb
Host smart-dff51d01-eb98-441e-9ef5-c2f263f3abcd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2839358902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.2839358902
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.3790227331
Short name T1050
Test name
Test status
Simulation time 338805599 ps
CPU time 2.9 seconds
Started Mar 21 01:22:24 PM PDT 24
Finished Mar 21 01:22:27 PM PDT 24
Peak memory 214592 kb
Host smart-dd79796d-934e-4ba3-ae4b-93a0d9f6cdb8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3790227331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.3790227331
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.3609761108
Short name T958
Test name
Test status
Simulation time 3883991729 ps
CPU time 7.55 seconds
Started Mar 21 01:22:24 PM PDT 24
Finished Mar 21 01:22:31 PM PDT 24
Peak memory 214512 kb
Host smart-d007cfda-33b3-4138-afba-1ba44e4532f5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3609761108 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.3609761108
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.1692753569
Short name T912
Test name
Test status
Simulation time 96216540 ps
CPU time 2.17 seconds
Started Mar 21 01:22:24 PM PDT 24
Finished Mar 21 01:22:26 PM PDT 24
Peak memory 214132 kb
Host smart-1ef919f7-3116-48f7-8640-00b711f8787a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692753569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.1692753569
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.3564267103
Short name T922
Test name
Test status
Simulation time 498696413 ps
CPU time 9.86 seconds
Started Mar 21 01:22:23 PM PDT 24
Finished Mar 21 01:22:33 PM PDT 24
Peak memory 208116 kb
Host smart-f6555741-2c99-4c24-ae40-568a5889b697
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3564267103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.3564267103
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.3255308341
Short name T966
Test name
Test status
Simulation time 191637235 ps
CPU time 7.24 seconds
Started Mar 21 01:22:12 PM PDT 24
Finished Mar 21 01:22:19 PM PDT 24
Peak memory 206096 kb
Host smart-493b914e-a746-4cab-ae02-df3b2c47e790
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255308341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.3
255308341
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.1310484673
Short name T1068
Test name
Test status
Simulation time 2162913440 ps
CPU time 16.52 seconds
Started Mar 21 01:22:16 PM PDT 24
Finished Mar 21 01:22:33 PM PDT 24
Peak memory 206032 kb
Host smart-4b8bed3d-8143-44ce-a47a-1fa22fbfbdc8
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310484673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.1
310484673
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.1313952363
Short name T991
Test name
Test status
Simulation time 45364273 ps
CPU time 0.87 seconds
Started Mar 21 01:22:14 PM PDT 24
Finished Mar 21 01:22:15 PM PDT 24
Peak memory 205736 kb
Host smart-57b9d148-2d00-4e47-a9f7-1f2ca0382d6f
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1313952363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.1
313952363
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.1138897793
Short name T985
Test name
Test status
Simulation time 48824973 ps
CPU time 1.78 seconds
Started Mar 21 01:22:15 PM PDT 24
Finished Mar 21 01:22:17 PM PDT 24
Peak memory 214152 kb
Host smart-a9f96f4a-6b84-41e4-8113-dc09bcef58d6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1138897793 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.1138897793
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.3310991926
Short name T1048
Test name
Test status
Simulation time 43703566 ps
CPU time 0.93 seconds
Started Mar 21 01:22:17 PM PDT 24
Finished Mar 21 01:22:18 PM PDT 24
Peak memory 205780 kb
Host smart-62b65cd9-4ad6-4a42-b1bc-e6f6716384e7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3310991926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.3310991926
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.4015372625
Short name T968
Test name
Test status
Simulation time 38706827 ps
CPU time 0.74 seconds
Started Mar 21 01:22:16 PM PDT 24
Finished Mar 21 01:22:17 PM PDT 24
Peak memory 205796 kb
Host smart-06715fc5-ee19-4bc7-b85b-6a4397690daf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4015372625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.4015372625
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.673646552
Short name T1063
Test name
Test status
Simulation time 23537277 ps
CPU time 1.41 seconds
Started Mar 21 01:22:15 PM PDT 24
Finished Mar 21 01:22:17 PM PDT 24
Peak memory 205992 kb
Host smart-c841edc9-49e9-4e71-9791-59f9f467c888
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673646552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sam
e_csr_outstanding.673646552
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.3202046948
Short name T947
Test name
Test status
Simulation time 86265000 ps
CPU time 2.08 seconds
Started Mar 21 01:22:13 PM PDT 24
Finished Mar 21 01:22:15 PM PDT 24
Peak memory 219068 kb
Host smart-220f372b-eded-462c-b3f4-4fa3bffb8a4e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3202046948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.3202046948
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.3006345115
Short name T942
Test name
Test status
Simulation time 559988620 ps
CPU time 6.69 seconds
Started Mar 21 01:22:13 PM PDT 24
Finished Mar 21 01:22:20 PM PDT 24
Peak memory 214492 kb
Host smart-a5cd6d45-b730-433d-8428-b6621b2b8e2b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006345115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.3006345115
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.3168651538
Short name T1005
Test name
Test status
Simulation time 54138897 ps
CPU time 1.77 seconds
Started Mar 21 01:22:17 PM PDT 24
Finished Mar 21 01:22:19 PM PDT 24
Peak memory 205976 kb
Host smart-575f7327-e030-4399-ba29-5429c0ab30c5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168651538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.3168651538
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.2282709908
Short name T911
Test name
Test status
Simulation time 28198691 ps
CPU time 0.71 seconds
Started Mar 21 01:22:23 PM PDT 24
Finished Mar 21 01:22:24 PM PDT 24
Peak memory 205712 kb
Host smart-b66c61ed-fc7b-4125-9896-341b10f41d6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2282709908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.2282709908
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.2798399185
Short name T1071
Test name
Test status
Simulation time 10227902 ps
CPU time 0.82 seconds
Started Mar 21 01:22:23 PM PDT 24
Finished Mar 21 01:22:24 PM PDT 24
Peak memory 205568 kb
Host smart-6ab78958-600d-4cf2-9065-5d36adf183aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798399185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.2798399185
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.1963465025
Short name T971
Test name
Test status
Simulation time 32949463 ps
CPU time 0.81 seconds
Started Mar 21 01:22:37 PM PDT 24
Finished Mar 21 01:22:38 PM PDT 24
Peak memory 205560 kb
Host smart-ffe1c14d-6aab-4af8-b292-8abb5e617900
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963465025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.1963465025
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.2407756948
Short name T933
Test name
Test status
Simulation time 160264442 ps
CPU time 0.71 seconds
Started Mar 21 01:22:37 PM PDT 24
Finished Mar 21 01:22:38 PM PDT 24
Peak memory 205796 kb
Host smart-fd8158c3-2d15-4899-a74c-b3cddea639f4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407756948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.2407756948
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.1574825952
Short name T1052
Test name
Test status
Simulation time 28222303 ps
CPU time 0.68 seconds
Started Mar 21 01:22:43 PM PDT 24
Finished Mar 21 01:22:44 PM PDT 24
Peak memory 205652 kb
Host smart-3cfc2be8-0938-4151-a6d6-23a2fce630f7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1574825952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.1574825952
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.3446164015
Short name T931
Test name
Test status
Simulation time 34353947 ps
CPU time 0.74 seconds
Started Mar 21 01:22:42 PM PDT 24
Finished Mar 21 01:22:44 PM PDT 24
Peak memory 205740 kb
Host smart-19ca5b36-d24b-4b3b-999f-16f176b7e386
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3446164015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.3446164015
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.3724378135
Short name T917
Test name
Test status
Simulation time 20534370 ps
CPU time 0.7 seconds
Started Mar 21 01:22:48 PM PDT 24
Finished Mar 21 01:22:48 PM PDT 24
Peak memory 205664 kb
Host smart-f7b7e94c-fdd2-4a03-b105-05cadcbeb63e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3724378135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.3724378135
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.3111762417
Short name T927
Test name
Test status
Simulation time 14047626 ps
CPU time 0.92 seconds
Started Mar 21 01:22:43 PM PDT 24
Finished Mar 21 01:22:44 PM PDT 24
Peak memory 205812 kb
Host smart-aff75fa2-88fa-43f3-bfd3-36063dcfa88e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3111762417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.3111762417
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.800785507
Short name T981
Test name
Test status
Simulation time 30811158 ps
CPU time 0.84 seconds
Started Mar 21 01:22:32 PM PDT 24
Finished Mar 21 01:22:33 PM PDT 24
Peak memory 205592 kb
Host smart-ae16e470-2494-4289-955a-eb4675567059
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=800785507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.800785507
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.1212193028
Short name T1065
Test name
Test status
Simulation time 33100507 ps
CPU time 0.85 seconds
Started Mar 21 01:22:37 PM PDT 24
Finished Mar 21 01:22:38 PM PDT 24
Peak memory 205564 kb
Host smart-963aa14e-8b60-496a-b026-da0dd40fd017
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1212193028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.1212193028
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.1560930203
Short name T1018
Test name
Test status
Simulation time 264866538 ps
CPU time 3.76 seconds
Started Mar 21 01:22:20 PM PDT 24
Finished Mar 21 01:22:24 PM PDT 24
Peak memory 206084 kb
Host smart-d913a033-5fba-41db-920f-6a8133c493f2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1560930203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.1
560930203
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.3995863222
Short name T1045
Test name
Test status
Simulation time 862413410 ps
CPU time 13.18 seconds
Started Mar 21 01:22:20 PM PDT 24
Finished Mar 21 01:22:33 PM PDT 24
Peak memory 206028 kb
Host smart-e5d5049a-dc06-4a33-b4d2-5e7e0b0ec595
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3995863222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.3
995863222
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.306868410
Short name T940
Test name
Test status
Simulation time 31038418 ps
CPU time 1.06 seconds
Started Mar 21 01:22:19 PM PDT 24
Finished Mar 21 01:22:20 PM PDT 24
Peak memory 206072 kb
Host smart-bf684859-7bbb-4759-be6c-286a61f3eec2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=306868410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.306868410
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.2488408687
Short name T1013
Test name
Test status
Simulation time 49793888 ps
CPU time 2.02 seconds
Started Mar 21 01:22:14 PM PDT 24
Finished Mar 21 01:22:16 PM PDT 24
Peak memory 214336 kb
Host smart-af8fcd9f-09d0-42cb-aed0-68b554f17478
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2488408687 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.2488408687
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.3873099014
Short name T1024
Test name
Test status
Simulation time 65799415 ps
CPU time 1.21 seconds
Started Mar 21 01:22:20 PM PDT 24
Finished Mar 21 01:22:21 PM PDT 24
Peak memory 206084 kb
Host smart-94e37248-1a94-4613-8925-5760305b3683
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3873099014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.3873099014
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.3022631770
Short name T955
Test name
Test status
Simulation time 17426406 ps
CPU time 0.78 seconds
Started Mar 21 01:22:12 PM PDT 24
Finished Mar 21 01:22:13 PM PDT 24
Peak memory 205620 kb
Host smart-5f471cd0-793a-475d-a1b4-3eb37099ab15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3022631770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.3022631770
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.1587844580
Short name T1056
Test name
Test status
Simulation time 138523184 ps
CPU time 2.18 seconds
Started Mar 21 01:22:20 PM PDT 24
Finished Mar 21 01:22:22 PM PDT 24
Peak memory 206096 kb
Host smart-93330a37-ca14-4cbf-93bb-6424f30aa020
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1587844580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.1587844580
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.2508345375
Short name T995
Test name
Test status
Simulation time 173010146 ps
CPU time 5.52 seconds
Started Mar 21 01:22:17 PM PDT 24
Finished Mar 21 01:22:23 PM PDT 24
Peak memory 222676 kb
Host smart-2adc35e9-32c9-4eae-8c2e-ba9346ccba0b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2508345375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.2508345375
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.4069430728
Short name T970
Test name
Test status
Simulation time 211244533 ps
CPU time 4.86 seconds
Started Mar 21 01:22:17 PM PDT 24
Finished Mar 21 01:22:22 PM PDT 24
Peak memory 214612 kb
Host smart-444e6e35-536d-4639-83f8-9f22c22d1b5e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4069430728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.4069430728
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.1077532249
Short name T1073
Test name
Test status
Simulation time 77400100 ps
CPU time 2.77 seconds
Started Mar 21 01:22:16 PM PDT 24
Finished Mar 21 01:22:18 PM PDT 24
Peak memory 215304 kb
Host smart-7e7a67dc-9e58-4289-978b-2bc63b98dd05
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1077532249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.1077532249
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.3751771268
Short name T1057
Test name
Test status
Simulation time 35010125 ps
CPU time 0.87 seconds
Started Mar 21 01:22:40 PM PDT 24
Finished Mar 21 01:22:42 PM PDT 24
Peak memory 205592 kb
Host smart-b72f65cf-e79d-4617-bf57-2536d9442fa2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3751771268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.3751771268
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.3619489744
Short name T1000
Test name
Test status
Simulation time 50992380 ps
CPU time 0.75 seconds
Started Mar 21 01:22:37 PM PDT 24
Finished Mar 21 01:22:38 PM PDT 24
Peak memory 205588 kb
Host smart-be4e6fc5-b5d2-4104-a976-1ba7252f43e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3619489744 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.3619489744
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.1980178876
Short name T909
Test name
Test status
Simulation time 51983525 ps
CPU time 0.82 seconds
Started Mar 21 01:22:41 PM PDT 24
Finished Mar 21 01:22:42 PM PDT 24
Peak memory 205588 kb
Host smart-668da68c-09c1-4b82-8271-cacd438a6800
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980178876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.1980178876
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.1262370017
Short name T1041
Test name
Test status
Simulation time 40565559 ps
CPU time 0.83 seconds
Started Mar 21 01:22:54 PM PDT 24
Finished Mar 21 01:22:55 PM PDT 24
Peak memory 205648 kb
Host smart-d01f2de2-e4c9-4514-a9e2-a4be0e306ab7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1262370017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.1262370017
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.3860256134
Short name T959
Test name
Test status
Simulation time 19918011 ps
CPU time 0.74 seconds
Started Mar 21 01:22:32 PM PDT 24
Finished Mar 21 01:22:32 PM PDT 24
Peak memory 205652 kb
Host smart-17c019be-5d26-415c-8c39-b4759025d128
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3860256134 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.3860256134
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.4153821183
Short name T961
Test name
Test status
Simulation time 99991119 ps
CPU time 0.79 seconds
Started Mar 21 01:22:44 PM PDT 24
Finished Mar 21 01:22:46 PM PDT 24
Peak memory 205572 kb
Host smart-434a8f5d-37c8-42c4-8b3e-747d0f438887
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153821183 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.4153821183
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.3207598322
Short name T994
Test name
Test status
Simulation time 32336396 ps
CPU time 0.71 seconds
Started Mar 21 01:22:47 PM PDT 24
Finished Mar 21 01:22:48 PM PDT 24
Peak memory 205572 kb
Host smart-fa4d48dc-1926-4c10-809c-fc1115ca6a7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207598322 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.3207598322
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.666104883
Short name T1027
Test name
Test status
Simulation time 49703891 ps
CPU time 0.76 seconds
Started Mar 21 01:22:38 PM PDT 24
Finished Mar 21 01:22:39 PM PDT 24
Peak memory 205672 kb
Host smart-3ba76ab1-056c-4738-8687-7b190ee3b71c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=666104883 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.666104883
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.619306921
Short name T1058
Test name
Test status
Simulation time 11611578 ps
CPU time 0.87 seconds
Started Mar 21 01:22:51 PM PDT 24
Finished Mar 21 01:22:52 PM PDT 24
Peak memory 205632 kb
Host smart-b3f48502-e66a-4f69-8ab1-26994f31a91d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=619306921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.619306921
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.3866812189
Short name T990
Test name
Test status
Simulation time 64924648 ps
CPU time 0.82 seconds
Started Mar 21 01:22:43 PM PDT 24
Finished Mar 21 01:22:44 PM PDT 24
Peak memory 205588 kb
Host smart-bb4e21fa-38ab-454e-9315-a06b990307c2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3866812189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.3866812189
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.2194786531
Short name T175
Test name
Test status
Simulation time 216819278 ps
CPU time 5.21 seconds
Started Mar 21 01:22:08 PM PDT 24
Finished Mar 21 01:22:14 PM PDT 24
Peak memory 206072 kb
Host smart-8b55205f-59bc-4f22-8a30-a516682ff693
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194786531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.2
194786531
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.3033901698
Short name T980
Test name
Test status
Simulation time 262935814 ps
CPU time 6.59 seconds
Started Mar 21 01:22:09 PM PDT 24
Finished Mar 21 01:22:16 PM PDT 24
Peak memory 205972 kb
Host smart-73f52a5b-c652-4412-94ee-55632fb717ea
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033901698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.3
033901698
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.1983240951
Short name T1019
Test name
Test status
Simulation time 38256894 ps
CPU time 0.97 seconds
Started Mar 21 01:22:10 PM PDT 24
Finished Mar 21 01:22:11 PM PDT 24
Peak memory 205712 kb
Host smart-8707997c-24a7-413d-88ea-f21bad3a88f6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983240951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.1
983240951
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.3942245929
Short name T1072
Test name
Test status
Simulation time 201250753 ps
CPU time 2.03 seconds
Started Mar 21 01:22:10 PM PDT 24
Finished Mar 21 01:22:12 PM PDT 24
Peak memory 219008 kb
Host smart-2149e99b-1396-4311-ac8b-443d107f0f44
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3942245929 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.3942245929
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.650361598
Short name T948
Test name
Test status
Simulation time 32261673 ps
CPU time 1.17 seconds
Started Mar 21 01:22:13 PM PDT 24
Finished Mar 21 01:22:14 PM PDT 24
Peak memory 205960 kb
Host smart-8bb1cec5-c001-4559-95aa-52c4df43ef5f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=650361598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.650361598
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.4177684437
Short name T1014
Test name
Test status
Simulation time 12211213 ps
CPU time 0.9 seconds
Started Mar 21 01:22:09 PM PDT 24
Finished Mar 21 01:22:10 PM PDT 24
Peak memory 205636 kb
Host smart-fa5f6eef-e26a-46a6-8ae5-ddbf71157d15
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177684437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.4177684437
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.1149682509
Short name T1008
Test name
Test status
Simulation time 67979785 ps
CPU time 1.87 seconds
Started Mar 21 01:22:11 PM PDT 24
Finished Mar 21 01:22:13 PM PDT 24
Peak memory 206092 kb
Host smart-b8d57475-8437-490c-bad1-fa6dc8cc0d95
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1149682509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.1149682509
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.4149624008
Short name T120
Test name
Test status
Simulation time 308288086 ps
CPU time 2.93 seconds
Started Mar 21 01:22:11 PM PDT 24
Finished Mar 21 01:22:14 PM PDT 24
Peak memory 222744 kb
Host smart-beca7e42-c73b-4d11-9a87-9a162ab9863f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4149624008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.4149624008
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.502733508
Short name T1059
Test name
Test status
Simulation time 605947972 ps
CPU time 4.03 seconds
Started Mar 21 01:22:09 PM PDT 24
Finished Mar 21 01:22:13 PM PDT 24
Peak memory 214424 kb
Host smart-97694ca3-af83-4dd6-a3f3-f72eebe75238
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=502733508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.k
eymgr_shadow_reg_errors_with_csr_rw.502733508
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.2180872161
Short name T914
Test name
Test status
Simulation time 57112518 ps
CPU time 1.82 seconds
Started Mar 21 01:22:10 PM PDT 24
Finished Mar 21 01:22:12 PM PDT 24
Peak memory 214312 kb
Host smart-f3d9f316-dd4e-4872-b83f-b67043ff5a7f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2180872161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.2180872161
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.1669555869
Short name T376
Test name
Test status
Simulation time 413520614 ps
CPU time 5.52 seconds
Started Mar 21 01:22:10 PM PDT 24
Finished Mar 21 01:22:16 PM PDT 24
Peak memory 214164 kb
Host smart-48b797eb-632b-4118-ace4-f131f6100937
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669555869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.1669555869
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.617315489
Short name T979
Test name
Test status
Simulation time 11154935 ps
CPU time 0.79 seconds
Started Mar 21 01:22:40 PM PDT 24
Finished Mar 21 01:22:40 PM PDT 24
Peak memory 205612 kb
Host smart-db2fded7-428c-4e80-9823-e174e79ac969
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617315489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.617315489
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.2128715639
Short name T1010
Test name
Test status
Simulation time 11241110 ps
CPU time 0.77 seconds
Started Mar 21 01:22:39 PM PDT 24
Finished Mar 21 01:22:40 PM PDT 24
Peak memory 205668 kb
Host smart-f73edefb-7bf1-472d-be47-2a51de0c5c3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2128715639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.2128715639
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.2760318346
Short name T939
Test name
Test status
Simulation time 12802111 ps
CPU time 0.74 seconds
Started Mar 21 01:22:53 PM PDT 24
Finished Mar 21 01:22:54 PM PDT 24
Peak memory 205708 kb
Host smart-65288cd2-b3dd-41ee-9214-0cca47514894
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760318346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.2760318346
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.4020318595
Short name T1004
Test name
Test status
Simulation time 28601901 ps
CPU time 0.83 seconds
Started Mar 21 01:22:45 PM PDT 24
Finished Mar 21 01:22:46 PM PDT 24
Peak memory 205652 kb
Host smart-85c465a0-d203-4dc8-861c-1cea566008da
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4020318595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.4020318595
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.1679898998
Short name T935
Test name
Test status
Simulation time 11263015 ps
CPU time 0.79 seconds
Started Mar 21 01:22:41 PM PDT 24
Finished Mar 21 01:22:42 PM PDT 24
Peak memory 205692 kb
Host smart-790511d0-b9c4-4af5-b843-b496eda15eb1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679898998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.1679898998
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.3934825290
Short name T1015
Test name
Test status
Simulation time 19329201 ps
CPU time 0.83 seconds
Started Mar 21 01:22:31 PM PDT 24
Finished Mar 21 01:22:32 PM PDT 24
Peak memory 205668 kb
Host smart-6e2807aa-98e2-4589-a8cc-4b96442710a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3934825290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.3934825290
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.2722171144
Short name T937
Test name
Test status
Simulation time 50296180 ps
CPU time 0.8 seconds
Started Mar 21 01:22:49 PM PDT 24
Finished Mar 21 01:22:50 PM PDT 24
Peak memory 205672 kb
Host smart-791cb6e0-db27-4047-b452-4ea59a77d9ae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2722171144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.2722171144
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.2100327858
Short name T1009
Test name
Test status
Simulation time 56058997 ps
CPU time 0.73 seconds
Started Mar 21 01:22:42 PM PDT 24
Finished Mar 21 01:22:43 PM PDT 24
Peak memory 205704 kb
Host smart-60ac35c7-94ce-42ba-ace3-6ca1ad998a4d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100327858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.2100327858
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.4161780922
Short name T944
Test name
Test status
Simulation time 11452728 ps
CPU time 0.74 seconds
Started Mar 21 01:22:54 PM PDT 24
Finished Mar 21 01:22:55 PM PDT 24
Peak memory 205796 kb
Host smart-e0459461-796a-42a1-ab14-8c9fb7552dec
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161780922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.4161780922
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.1897628899
Short name T923
Test name
Test status
Simulation time 10848481 ps
CPU time 0.7 seconds
Started Mar 21 01:22:32 PM PDT 24
Finished Mar 21 01:22:33 PM PDT 24
Peak memory 205660 kb
Host smart-eca2afc8-d215-4f5e-be32-79fb610f31d2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1897628899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.1897628899
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.3356785924
Short name T1029
Test name
Test status
Simulation time 211725361 ps
CPU time 2.24 seconds
Started Mar 21 01:22:09 PM PDT 24
Finished Mar 21 01:22:11 PM PDT 24
Peak memory 218248 kb
Host smart-82e54f3a-8b09-40e9-b4b3-d8215c10bb55
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3356785924 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.3356785924
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.3518177328
Short name T945
Test name
Test status
Simulation time 34283205 ps
CPU time 0.88 seconds
Started Mar 21 01:22:18 PM PDT 24
Finished Mar 21 01:22:19 PM PDT 24
Peak memory 205708 kb
Host smart-70cadaa2-7d31-4ccd-8372-6107dc8efd21
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3518177328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.3518177328
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.367869945
Short name T1075
Test name
Test status
Simulation time 14905186 ps
CPU time 0.77 seconds
Started Mar 21 01:22:12 PM PDT 24
Finished Mar 21 01:22:13 PM PDT 24
Peak memory 205672 kb
Host smart-82180749-eb47-4d20-b742-e32b4ed56bb4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=367869945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.367869945
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.2036225516
Short name T135
Test name
Test status
Simulation time 1237960258 ps
CPU time 2.7 seconds
Started Mar 21 01:22:12 PM PDT 24
Finished Mar 21 01:22:15 PM PDT 24
Peak memory 206088 kb
Host smart-819fbf75-8e39-41a5-9cc5-03cb24d66ac3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2036225516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.2036225516
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.4184276313
Short name T972
Test name
Test status
Simulation time 181981429 ps
CPU time 1.97 seconds
Started Mar 21 01:22:08 PM PDT 24
Finished Mar 21 01:22:10 PM PDT 24
Peak memory 222720 kb
Host smart-e17ea97c-4452-4e71-b919-e387113a9118
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4184276313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.4184276313
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.2434693222
Short name T993
Test name
Test status
Simulation time 278931558 ps
CPU time 6.35 seconds
Started Mar 21 01:22:14 PM PDT 24
Finished Mar 21 01:22:20 PM PDT 24
Peak memory 214548 kb
Host smart-3676ab85-3066-463e-9d6d-1a24c93d3c6e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2434693222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
keymgr_shadow_reg_errors_with_csr_rw.2434693222
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.3675888660
Short name T977
Test name
Test status
Simulation time 207305241 ps
CPU time 1.76 seconds
Started Mar 21 01:22:08 PM PDT 24
Finished Mar 21 01:22:10 PM PDT 24
Peak memory 214188 kb
Host smart-89403c23-0035-4326-8847-057510f2c736
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675888660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.3675888660
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.2949500149
Short name T152
Test name
Test status
Simulation time 678323346 ps
CPU time 3.56 seconds
Started Mar 21 01:22:10 PM PDT 24
Finished Mar 21 01:22:14 PM PDT 24
Peak memory 209632 kb
Host smart-bc6b853d-a7c9-4442-ae27-505c8d5292d4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2949500149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err
.2949500149
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.4263923515
Short name T969
Test name
Test status
Simulation time 396359462 ps
CPU time 1.85 seconds
Started Mar 21 01:22:10 PM PDT 24
Finished Mar 21 01:22:12 PM PDT 24
Peak memory 214240 kb
Host smart-cbc403e3-ab9b-4250-966d-371081b6f93b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4263923515 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.4263923515
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.4223936857
Short name T975
Test name
Test status
Simulation time 146878374 ps
CPU time 1.54 seconds
Started Mar 21 01:22:15 PM PDT 24
Finished Mar 21 01:22:16 PM PDT 24
Peak memory 205920 kb
Host smart-d4c8237f-2000-4591-82ba-4d377afa85e6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223936857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.4223936857
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.2257122132
Short name T920
Test name
Test status
Simulation time 11076089 ps
CPU time 0.8 seconds
Started Mar 21 01:22:15 PM PDT 24
Finished Mar 21 01:22:16 PM PDT 24
Peak memory 205620 kb
Host smart-5c52809c-7147-4155-9771-2c9ac888b319
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257122132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.2257122132
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.2178851818
Short name T962
Test name
Test status
Simulation time 177893007 ps
CPU time 2.1 seconds
Started Mar 21 01:22:12 PM PDT 24
Finished Mar 21 01:22:14 PM PDT 24
Peak memory 206004 kb
Host smart-52316c57-7077-49f2-826c-be567ba0c7e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178851818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.2178851818
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.3687771860
Short name T983
Test name
Test status
Simulation time 83001653 ps
CPU time 2.14 seconds
Started Mar 21 01:22:14 PM PDT 24
Finished Mar 21 01:22:16 PM PDT 24
Peak memory 214596 kb
Host smart-3cd79db7-6314-4e6b-8641-5159a75b1556
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3687771860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.3687771860
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.3358902339
Short name T941
Test name
Test status
Simulation time 306527678 ps
CPU time 8.84 seconds
Started Mar 21 01:22:13 PM PDT 24
Finished Mar 21 01:22:22 PM PDT 24
Peak memory 214512 kb
Host smart-0c1a252c-5ce6-4ad7-bf61-dc1365532f7a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358902339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
keymgr_shadow_reg_errors_with_csr_rw.3358902339
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.128784453
Short name T1026
Test name
Test status
Simulation time 46094643 ps
CPU time 3.34 seconds
Started Mar 21 01:22:12 PM PDT 24
Finished Mar 21 01:22:16 PM PDT 24
Peak memory 214044 kb
Host smart-32908390-a969-4497-8c4e-980c13489d0e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128784453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.128784453
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.2376799370
Short name T161
Test name
Test status
Simulation time 1436531472 ps
CPU time 10.68 seconds
Started Mar 21 01:22:09 PM PDT 24
Finished Mar 21 01:22:20 PM PDT 24
Peak memory 214096 kb
Host smart-ab88536e-53a4-431e-81ca-d991afafec1e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376799370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.2376799370
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.3985438185
Short name T1074
Test name
Test status
Simulation time 38016217 ps
CPU time 1.44 seconds
Started Mar 21 01:22:14 PM PDT 24
Finished Mar 21 01:22:16 PM PDT 24
Peak memory 214236 kb
Host smart-02f659c4-c42c-40ae-b919-53ec359fac20
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3985438185 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.3985438185
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.514398970
Short name T1046
Test name
Test status
Simulation time 36355181 ps
CPU time 0.97 seconds
Started Mar 21 01:22:15 PM PDT 24
Finished Mar 21 01:22:16 PM PDT 24
Peak memory 206112 kb
Host smart-59273baa-7b1c-47c3-acb6-648adc13c783
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=514398970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.514398970
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.34535093
Short name T984
Test name
Test status
Simulation time 20672682 ps
CPU time 0.79 seconds
Started Mar 21 01:22:14 PM PDT 24
Finished Mar 21 01:22:15 PM PDT 24
Peak memory 205736 kb
Host smart-2837bd91-52f7-4169-9fb9-5ac4804ea562
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34535093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.34535093
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.597331093
Short name T951
Test name
Test status
Simulation time 55952320 ps
CPU time 2.35 seconds
Started Mar 21 01:22:16 PM PDT 24
Finished Mar 21 01:22:19 PM PDT 24
Peak memory 205968 kb
Host smart-9a1cfce1-9186-4104-a75f-9de3dd6265f7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=597331093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sam
e_csr_outstanding.597331093
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.3794203371
Short name T1030
Test name
Test status
Simulation time 828158363 ps
CPU time 5.54 seconds
Started Mar 21 01:22:09 PM PDT 24
Finished Mar 21 01:22:15 PM PDT 24
Peak memory 214576 kb
Host smart-649fc773-efc4-41cf-9060-636051d9eb43
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3794203371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.3794203371
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.1069134238
Short name T1028
Test name
Test status
Simulation time 158190306 ps
CPU time 6.45 seconds
Started Mar 21 01:22:13 PM PDT 24
Finished Mar 21 01:22:20 PM PDT 24
Peak memory 220496 kb
Host smart-b97119c3-e226-49c6-8593-268dd987d059
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1069134238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
keymgr_shadow_reg_errors_with_csr_rw.1069134238
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.3568789781
Short name T1003
Test name
Test status
Simulation time 47508288 ps
CPU time 2.21 seconds
Started Mar 21 01:22:13 PM PDT 24
Finished Mar 21 01:22:15 PM PDT 24
Peak memory 214012 kb
Host smart-e7b0976b-2477-435e-a6fb-e7cc6718dcb8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3568789781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.3568789781
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.2216475090
Short name T375
Test name
Test status
Simulation time 1509112208 ps
CPU time 39.93 seconds
Started Mar 21 01:22:16 PM PDT 24
Finished Mar 21 01:22:56 PM PDT 24
Peak memory 214304 kb
Host smart-a3cf0085-3d0b-494d-9582-25f1cf4ee7a1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2216475090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.2216475090
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.985603650
Short name T1069
Test name
Test status
Simulation time 84700283 ps
CPU time 1.58 seconds
Started Mar 21 01:22:13 PM PDT 24
Finished Mar 21 01:22:14 PM PDT 24
Peak memory 214188 kb
Host smart-68b1de33-d7db-4a6d-a616-19f7ed643941
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=985603650 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.985603650
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.2417206395
Short name T1037
Test name
Test status
Simulation time 34921000 ps
CPU time 0.9 seconds
Started Mar 21 01:22:16 PM PDT 24
Finished Mar 21 01:22:16 PM PDT 24
Peak memory 205808 kb
Host smart-ec33f389-3194-4b7b-a0db-e857c8382d1c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2417206395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.2417206395
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.2272432145
Short name T916
Test name
Test status
Simulation time 25860336 ps
CPU time 0.86 seconds
Started Mar 21 01:22:08 PM PDT 24
Finished Mar 21 01:22:09 PM PDT 24
Peak memory 205664 kb
Host smart-a1c723f7-1472-4998-8261-5647590aa13e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2272432145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.2272432145
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.1713154061
Short name T1035
Test name
Test status
Simulation time 778858455 ps
CPU time 1.93 seconds
Started Mar 21 01:22:14 PM PDT 24
Finished Mar 21 01:22:16 PM PDT 24
Peak memory 206032 kb
Host smart-33a7ac4e-cee7-4e24-ad7b-edc2b4b38550
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1713154061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.1713154061
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.1269117259
Short name T950
Test name
Test status
Simulation time 1020230403 ps
CPU time 5.25 seconds
Started Mar 21 01:22:15 PM PDT 24
Finished Mar 21 01:22:21 PM PDT 24
Peak memory 219180 kb
Host smart-156d2f26-2fc5-4d04-82c3-7b0aaa29c06c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1269117259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.1269117259
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.1593255172
Short name T1001
Test name
Test status
Simulation time 1374511246 ps
CPU time 5.05 seconds
Started Mar 21 01:22:16 PM PDT 24
Finished Mar 21 01:22:21 PM PDT 24
Peak memory 214496 kb
Host smart-524117a8-3cdf-4e8d-9739-c6c2c086847c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593255172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
keymgr_shadow_reg_errors_with_csr_rw.1593255172
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.2572458197
Short name T956
Test name
Test status
Simulation time 128588929 ps
CPU time 4.89 seconds
Started Mar 21 01:22:21 PM PDT 24
Finished Mar 21 01:22:26 PM PDT 24
Peak memory 214216 kb
Host smart-f08d152b-4c27-43dc-b59b-2cb2ac09feac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2572458197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.2572458197
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.1154436868
Short name T964
Test name
Test status
Simulation time 1064324683 ps
CPU time 14.6 seconds
Started Mar 21 01:22:17 PM PDT 24
Finished Mar 21 01:22:31 PM PDT 24
Peak memory 214176 kb
Host smart-e4bd4775-5641-4744-a7e3-edcf176803a7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1154436868 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.1154436868
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.2826336958
Short name T1055
Test name
Test status
Simulation time 30771170 ps
CPU time 2.37 seconds
Started Mar 21 01:22:17 PM PDT 24
Finished Mar 21 01:22:19 PM PDT 24
Peak memory 214160 kb
Host smart-42519ba2-6b81-44c4-a8cb-fcfe59a0be74
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2826336958 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.2826336958
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.2379218571
Short name T134
Test name
Test status
Simulation time 12738007 ps
CPU time 0.97 seconds
Started Mar 21 01:22:11 PM PDT 24
Finished Mar 21 01:22:12 PM PDT 24
Peak memory 205972 kb
Host smart-f75d2cc7-1b29-4490-9ee9-4ab01eeb0995
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2379218571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.2379218571
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.3936922776
Short name T987
Test name
Test status
Simulation time 13364354 ps
CPU time 0.84 seconds
Started Mar 21 01:22:19 PM PDT 24
Finished Mar 21 01:22:20 PM PDT 24
Peak memory 205688 kb
Host smart-8f5c33f2-abd9-48ef-9573-d8442faa2974
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3936922776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.3936922776
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.4198062845
Short name T930
Test name
Test status
Simulation time 48547258 ps
CPU time 2.03 seconds
Started Mar 21 01:22:20 PM PDT 24
Finished Mar 21 01:22:22 PM PDT 24
Peak memory 206004 kb
Host smart-f48df838-9ae0-4051-9e14-05d081fb4810
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198062845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.4198062845
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.3776274453
Short name T967
Test name
Test status
Simulation time 195277436 ps
CPU time 4.48 seconds
Started Mar 21 01:22:19 PM PDT 24
Finished Mar 21 01:22:24 PM PDT 24
Peak memory 222748 kb
Host smart-57f612e6-f171-4373-a0ee-df781f411e9f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3776274453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.3776274453
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.3705130633
Short name T1054
Test name
Test status
Simulation time 799934613 ps
CPU time 13.89 seconds
Started Mar 21 01:22:17 PM PDT 24
Finished Mar 21 01:22:31 PM PDT 24
Peak memory 214480 kb
Host smart-bc830791-f35a-4637-911d-58fb68cc728a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3705130633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.3705130633
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.3279224373
Short name T1049
Test name
Test status
Simulation time 36235538 ps
CPU time 2.48 seconds
Started Mar 21 01:22:16 PM PDT 24
Finished Mar 21 01:22:19 PM PDT 24
Peak memory 214260 kb
Host smart-dfa69f99-b48a-4c46-b67a-1f68d4b56079
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279224373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.3279224373
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.1948354969
Short name T168
Test name
Test status
Simulation time 2756897674 ps
CPU time 6.7 seconds
Started Mar 21 01:22:19 PM PDT 24
Finished Mar 21 01:22:26 PM PDT 24
Peak memory 209744 kb
Host smart-47e2f303-8594-4bf0-9252-91fca0b2c0a4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948354969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err
.1948354969
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.3060538153
Short name T593
Test name
Test status
Simulation time 63067298 ps
CPU time 2.74 seconds
Started Mar 21 03:23:41 PM PDT 24
Finished Mar 21 03:23:44 PM PDT 24
Peak memory 208684 kb
Host smart-57d9d1fc-55ea-4830-9b8f-00abc5ef643b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3060538153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.3060538153
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.2602067787
Short name T228
Test name
Test status
Simulation time 2574702899 ps
CPU time 29.04 seconds
Started Mar 21 03:23:44 PM PDT 24
Finished Mar 21 03:24:14 PM PDT 24
Peak memory 218920 kb
Host smart-288443a6-bb00-4bf0-a074-df72030aab63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2602067787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.2602067787
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.232281386
Short name T873
Test name
Test status
Simulation time 252441236 ps
CPU time 6.47 seconds
Started Mar 21 03:23:42 PM PDT 24
Finished Mar 21 03:23:48 PM PDT 24
Peak memory 210344 kb
Host smart-c5e0b595-71b0-4695-95c9-afadf66d7998
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=232281386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.232281386
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.2634636133
Short name T5
Test name
Test status
Simulation time 338026521 ps
CPU time 3.22 seconds
Started Mar 21 03:23:41 PM PDT 24
Finished Mar 21 03:23:45 PM PDT 24
Peak memory 223040 kb
Host smart-3be86c6f-2da8-4628-88b3-f2f813aa6b54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2634636133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.2634636133
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.445114642
Short name T339
Test name
Test status
Simulation time 194214091 ps
CPU time 8.31 seconds
Started Mar 21 03:23:30 PM PDT 24
Finished Mar 21 03:23:40 PM PDT 24
Peak memory 214916 kb
Host smart-6c333c7a-18ce-488d-aa69-9d1008f339cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=445114642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.445114642
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.477452541
Short name T99
Test name
Test status
Simulation time 956929401 ps
CPU time 9.76 seconds
Started Mar 21 03:23:42 PM PDT 24
Finished Mar 21 03:23:52 PM PDT 24
Peak memory 231720 kb
Host smart-30cafe43-cfa1-457f-9b11-63336d4b2dc7
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=477452541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.477452541
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload.89966626
Short name T690
Test name
Test status
Simulation time 204770815 ps
CPU time 7.41 seconds
Started Mar 21 03:23:29 PM PDT 24
Finished Mar 21 03:23:37 PM PDT 24
Peak memory 208904 kb
Host smart-a4df822b-c997-41f0-97f7-11be83f7d735
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89966626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.89966626
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.4168625392
Short name T694
Test name
Test status
Simulation time 29586858 ps
CPU time 1.97 seconds
Started Mar 21 03:23:29 PM PDT 24
Finished Mar 21 03:23:32 PM PDT 24
Peak memory 208516 kb
Host smart-c8959ef6-6650-45b3-bacf-640702f4a4be
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4168625392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.4168625392
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.2772844915
Short name T311
Test name
Test status
Simulation time 205355482 ps
CPU time 2.73 seconds
Started Mar 21 03:23:30 PM PDT 24
Finished Mar 21 03:23:33 PM PDT 24
Peak memory 209064 kb
Host smart-8e514a72-8ecc-4579-91a3-04b69b294e50
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2772844915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.2772844915
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.2258669417
Short name T862
Test name
Test status
Simulation time 147137791 ps
CPU time 3.49 seconds
Started Mar 21 03:23:42 PM PDT 24
Finished Mar 21 03:23:46 PM PDT 24
Peak memory 210056 kb
Host smart-2fa52110-8d52-469a-9820-205f58b63f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258669417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.2258669417
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.2039621641
Short name T830
Test name
Test status
Simulation time 90501926 ps
CPU time 2.45 seconds
Started Mar 21 03:23:30 PM PDT 24
Finished Mar 21 03:23:34 PM PDT 24
Peak memory 208756 kb
Host smart-aa3007d6-af37-4cc9-93e1-7b4bea18f194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039621641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.2039621641
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all_with_rand_reset.2262235126
Short name T173
Test name
Test status
Simulation time 1168875991 ps
CPU time 11.79 seconds
Started Mar 21 03:23:42 PM PDT 24
Finished Mar 21 03:23:54 PM PDT 24
Peak memory 221404 kb
Host smart-d4f81b44-f61d-4f8e-9396-9038e5e96b4d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2262235126 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all_with_rand_reset.2262235126
Directory /workspace/0.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.2586687304
Short name T890
Test name
Test status
Simulation time 358183444 ps
CPU time 6.82 seconds
Started Mar 21 03:23:42 PM PDT 24
Finished Mar 21 03:23:49 PM PDT 24
Peak memory 209972 kb
Host smart-62912cf3-f18f-44e7-a29a-b5a2dd89da71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2586687304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.2586687304
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.2664742632
Short name T378
Test name
Test status
Simulation time 164656734 ps
CPU time 1.71 seconds
Started Mar 21 03:23:41 PM PDT 24
Finished Mar 21 03:23:43 PM PDT 24
Peak memory 210560 kb
Host smart-503c4a50-fd56-458a-a63f-5bc165c5855c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664742632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.2664742632
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.3375463766
Short name T545
Test name
Test status
Simulation time 20769217 ps
CPU time 0.72 seconds
Started Mar 21 03:23:42 PM PDT 24
Finished Mar 21 03:23:43 PM PDT 24
Peak memory 206448 kb
Host smart-dc9e3f24-3631-4019-9cfb-526415e1a063
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3375463766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.3375463766
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.4148197903
Short name T865
Test name
Test status
Simulation time 526587153 ps
CPU time 10.1 seconds
Started Mar 21 03:23:43 PM PDT 24
Finished Mar 21 03:23:54 PM PDT 24
Peak memory 214712 kb
Host smart-e5ea0ca7-6b7c-4e07-9919-7d06b484fff1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4148197903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.4148197903
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.4039120207
Short name T253
Test name
Test status
Simulation time 191928586 ps
CPU time 6.29 seconds
Started Mar 21 03:23:46 PM PDT 24
Finished Mar 21 03:23:53 PM PDT 24
Peak memory 210156 kb
Host smart-7f2c9db2-25b9-448b-9f4c-fc21cb6a68cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4039120207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.4039120207
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.296894786
Short name T331
Test name
Test status
Simulation time 104831543 ps
CPU time 2.87 seconds
Started Mar 21 03:23:45 PM PDT 24
Finished Mar 21 03:23:48 PM PDT 24
Peak memory 220340 kb
Host smart-fe81b1a8-3543-47e0-9f49-b9ebc06a5a9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=296894786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.296894786
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.3921591178
Short name T267
Test name
Test status
Simulation time 218065701 ps
CPU time 6.79 seconds
Started Mar 21 03:23:44 PM PDT 24
Finished Mar 21 03:23:52 PM PDT 24
Peak memory 210260 kb
Host smart-99eeea08-54b7-458e-b271-836ba80fbd12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921591178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.3921591178
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sideload.1269491232
Short name T508
Test name
Test status
Simulation time 645637727 ps
CPU time 3.4 seconds
Started Mar 21 03:23:43 PM PDT 24
Finished Mar 21 03:23:47 PM PDT 24
Peak memory 208824 kb
Host smart-bff0d431-d6af-445f-a787-eae2b9d5add6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1269491232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.1269491232
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.3092917834
Short name T265
Test name
Test status
Simulation time 78336323 ps
CPU time 3.37 seconds
Started Mar 21 03:23:44 PM PDT 24
Finished Mar 21 03:23:48 PM PDT 24
Peak memory 208936 kb
Host smart-4c1f9bcc-18a7-4998-b155-e947762671bc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092917834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.3092917834
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.1896496726
Short name T706
Test name
Test status
Simulation time 45791412 ps
CPU time 2.01 seconds
Started Mar 21 03:23:42 PM PDT 24
Finished Mar 21 03:23:44 PM PDT 24
Peak memory 207644 kb
Host smart-7bb48faf-3603-4ab4-88f9-c5478a9bc2a4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1896496726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.1896496726
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.2778247554
Short name T730
Test name
Test status
Simulation time 168400080 ps
CPU time 3.89 seconds
Started Mar 21 03:23:44 PM PDT 24
Finished Mar 21 03:23:49 PM PDT 24
Peak memory 214840 kb
Host smart-201eeb65-4ede-4c60-a424-69611279694d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778247554 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.2778247554
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.4105184553
Short name T520
Test name
Test status
Simulation time 90065051 ps
CPU time 2.46 seconds
Started Mar 21 03:23:43 PM PDT 24
Finished Mar 21 03:23:47 PM PDT 24
Peak memory 207240 kb
Host smart-00e31266-1b0e-430b-90b7-fc1c4428320c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4105184553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.4105184553
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.1385093550
Short name T247
Test name
Test status
Simulation time 242036673 ps
CPU time 6.99 seconds
Started Mar 21 03:23:43 PM PDT 24
Finished Mar 21 03:23:51 PM PDT 24
Peak memory 207520 kb
Host smart-21a4963a-8a5f-45e4-ac96-cb4a9b6fad66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1385093550 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.1385093550
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.2822395725
Short name T845
Test name
Test status
Simulation time 282018873 ps
CPU time 3.43 seconds
Started Mar 21 03:23:45 PM PDT 24
Finished Mar 21 03:23:49 PM PDT 24
Peak memory 210500 kb
Host smart-1da765e4-3ef2-4934-b960-29d153943380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2822395725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.2822395725
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.4222027035
Short name T712
Test name
Test status
Simulation time 11627599 ps
CPU time 0.92 seconds
Started Mar 21 03:24:29 PM PDT 24
Finished Mar 21 03:24:30 PM PDT 24
Peak memory 206440 kb
Host smart-ffb7a413-0799-4a90-be1a-7a1f6ceb3235
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222027035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.4222027035
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.3237103731
Short name T350
Test name
Test status
Simulation time 85180507 ps
CPU time 3.58 seconds
Started Mar 21 03:24:05 PM PDT 24
Finished Mar 21 03:24:09 PM PDT 24
Peak memory 216060 kb
Host smart-38ed633f-59af-4e98-8a20-758b27d00611
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3237103731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.3237103731
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.495662527
Short name T547
Test name
Test status
Simulation time 176007655 ps
CPU time 4.55 seconds
Started Mar 21 03:24:26 PM PDT 24
Finished Mar 21 03:24:30 PM PDT 24
Peak memory 209928 kb
Host smart-836c6fec-75c1-44d9-a007-ac04af64bb2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=495662527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.495662527
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.113359042
Short name T704
Test name
Test status
Simulation time 185976198 ps
CPU time 5.49 seconds
Started Mar 21 03:24:06 PM PDT 24
Finished Mar 21 03:24:11 PM PDT 24
Peak memory 209660 kb
Host smart-44030aee-0d56-466c-8502-05512d805a76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=113359042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.113359042
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.101933403
Short name T334
Test name
Test status
Simulation time 139806812 ps
CPU time 3.8 seconds
Started Mar 21 03:24:26 PM PDT 24
Finished Mar 21 03:24:30 PM PDT 24
Peak memory 209524 kb
Host smart-7b5ac714-cc85-477a-9761-3cade2cbd43d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101933403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.101933403
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.224761159
Short name T721
Test name
Test status
Simulation time 213418388 ps
CPU time 6.33 seconds
Started Mar 21 03:24:30 PM PDT 24
Finished Mar 21 03:24:37 PM PDT 24
Peak memory 211232 kb
Host smart-6fd4fd31-f545-48ae-ae44-bc83208433e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=224761159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.224761159
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.1956080317
Short name T208
Test name
Test status
Simulation time 92650610 ps
CPU time 4.02 seconds
Started Mar 21 03:24:09 PM PDT 24
Finished Mar 21 03:24:13 PM PDT 24
Peak memory 210484 kb
Host smart-1c7c0f5d-d876-47b9-9337-2f8ac9eba25c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956080317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.1956080317
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.963224585
Short name T422
Test name
Test status
Simulation time 107181774 ps
CPU time 4.83 seconds
Started Mar 21 03:24:09 PM PDT 24
Finished Mar 21 03:24:14 PM PDT 24
Peak memory 209728 kb
Host smart-d90025b7-0dc5-4130-907c-4e8950baafaf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963224585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.963224585
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.2625030596
Short name T824
Test name
Test status
Simulation time 31310918 ps
CPU time 2.38 seconds
Started Mar 21 03:24:10 PM PDT 24
Finished Mar 21 03:24:12 PM PDT 24
Peak memory 207200 kb
Host smart-f308c8dd-e506-4c9b-a551-409b387f18a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2625030596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.2625030596
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.775031378
Short name T793
Test name
Test status
Simulation time 135688662 ps
CPU time 3.46 seconds
Started Mar 21 03:24:07 PM PDT 24
Finished Mar 21 03:24:12 PM PDT 24
Peak memory 207404 kb
Host smart-c8f6106f-7840-4155-ade3-b094cecef096
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775031378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.775031378
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.3844104265
Short name T503
Test name
Test status
Simulation time 231977325 ps
CPU time 2.37 seconds
Started Mar 21 03:24:05 PM PDT 24
Finished Mar 21 03:24:08 PM PDT 24
Peak memory 207296 kb
Host smart-1351efc3-70e1-4d6a-85ee-ebbfe0b4c236
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3844104265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.3844104265
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.24161728
Short name T470
Test name
Test status
Simulation time 110685722 ps
CPU time 2.69 seconds
Started Mar 21 03:24:24 PM PDT 24
Finished Mar 21 03:24:27 PM PDT 24
Peak memory 210876 kb
Host smart-0a101ce7-ca65-4996-a589-ae57bf925089
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24161728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.24161728
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.1612826986
Short name T571
Test name
Test status
Simulation time 450113547 ps
CPU time 4.28 seconds
Started Mar 21 03:24:07 PM PDT 24
Finished Mar 21 03:24:12 PM PDT 24
Peak memory 207156 kb
Host smart-cc83c068-3a76-40b2-865b-d9b39546cf54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612826986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.1612826986
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all_with_rand_reset.2219133012
Short name T616
Test name
Test status
Simulation time 500574545 ps
CPU time 14.65 seconds
Started Mar 21 03:24:27 PM PDT 24
Finished Mar 21 03:24:42 PM PDT 24
Peak memory 223036 kb
Host smart-7045774f-dddd-48b1-ba69-53282486c2dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219133012 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all_with_rand_reset.2219133012
Directory /workspace/10.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.3583136167
Short name T743
Test name
Test status
Simulation time 803150060 ps
CPU time 6 seconds
Started Mar 21 03:24:18 PM PDT 24
Finished Mar 21 03:24:24 PM PDT 24
Peak memory 219012 kb
Host smart-3549d692-c236-4db0-bc2c-7bd76f8aa6ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3583136167 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.3583136167
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.4211014985
Short name T572
Test name
Test status
Simulation time 178016935 ps
CPU time 2.98 seconds
Started Mar 21 03:24:28 PM PDT 24
Finished Mar 21 03:24:31 PM PDT 24
Peak memory 210960 kb
Host smart-be198445-ca9a-4779-bf63-90e5d32c2328
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4211014985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.4211014985
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.1722823837
Short name T413
Test name
Test status
Simulation time 25328674 ps
CPU time 0.74 seconds
Started Mar 21 03:24:28 PM PDT 24
Finished Mar 21 03:24:29 PM PDT 24
Peak memory 206420 kb
Host smart-83c083ab-4474-445f-928e-f62d4aa8ae69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1722823837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.1722823837
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.1708174967
Short name T398
Test name
Test status
Simulation time 500200820 ps
CPU time 4.96 seconds
Started Mar 21 03:24:35 PM PDT 24
Finished Mar 21 03:24:40 PM PDT 24
Peak memory 214788 kb
Host smart-86dca1d4-abe1-40f0-a561-6d9393d74e2a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1708174967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.1708174967
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.2233976779
Short name T523
Test name
Test status
Simulation time 80136198 ps
CPU time 3.56 seconds
Started Mar 21 03:24:30 PM PDT 24
Finished Mar 21 03:24:34 PM PDT 24
Peak memory 210040 kb
Host smart-3b34fefc-5b04-4eca-af49-ce6c6add7653
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233976779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.2233976779
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.1369821393
Short name T579
Test name
Test status
Simulation time 164060054 ps
CPU time 2.5 seconds
Started Mar 21 03:24:27 PM PDT 24
Finished Mar 21 03:24:29 PM PDT 24
Peak memory 207544 kb
Host smart-16bfeb8c-7153-467d-8db0-53b942588c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1369821393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.1369821393
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.687319380
Short name T84
Test name
Test status
Simulation time 578350718 ps
CPU time 7.45 seconds
Started Mar 21 03:24:28 PM PDT 24
Finished Mar 21 03:24:35 PM PDT 24
Peak memory 214720 kb
Host smart-c0e07bff-2ba7-4ac1-aec3-953ec0ac72d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687319380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.687319380
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.3357069104
Short name T26
Test name
Test status
Simulation time 895893397 ps
CPU time 9.48 seconds
Started Mar 21 03:24:28 PM PDT 24
Finished Mar 21 03:24:37 PM PDT 24
Peak memory 211180 kb
Host smart-d02e5e45-d87b-41f3-9ed4-6ca92ee6c8ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3357069104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.3357069104
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_random.2633131769
Short name T882
Test name
Test status
Simulation time 128921172 ps
CPU time 2.5 seconds
Started Mar 21 03:24:28 PM PDT 24
Finished Mar 21 03:24:31 PM PDT 24
Peak memory 207928 kb
Host smart-2fd28f34-8018-4750-b49c-13dae2a9f4e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2633131769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.2633131769
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.313041473
Short name T701
Test name
Test status
Simulation time 368097593 ps
CPU time 6.95 seconds
Started Mar 21 03:24:28 PM PDT 24
Finished Mar 21 03:24:35 PM PDT 24
Peak memory 208376 kb
Host smart-a269ddc7-8a08-44c9-8486-e1115eb1b0ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313041473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.313041473
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.3309093141
Short name T355
Test name
Test status
Simulation time 250295770 ps
CPU time 6.15 seconds
Started Mar 21 03:24:25 PM PDT 24
Finished Mar 21 03:24:32 PM PDT 24
Peak memory 208992 kb
Host smart-8b303a50-07de-46d0-a290-7bca60b136ee
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3309093141 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.3309093141
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.3946801162
Short name T705
Test name
Test status
Simulation time 761716881 ps
CPU time 9.32 seconds
Started Mar 21 03:24:31 PM PDT 24
Finished Mar 21 03:24:40 PM PDT 24
Peak memory 208492 kb
Host smart-e6abef60-f17a-4da4-b06d-1d60aa256818
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3946801162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.3946801162
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.1094186687
Short name T778
Test name
Test status
Simulation time 82833582 ps
CPU time 3.47 seconds
Started Mar 21 03:24:28 PM PDT 24
Finished Mar 21 03:24:32 PM PDT 24
Peak memory 208508 kb
Host smart-08b448a1-7828-4f49-b0ef-0f7b16d399a4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1094186687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.1094186687
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.512324038
Short name T459
Test name
Test status
Simulation time 41834705 ps
CPU time 2.1 seconds
Started Mar 21 03:24:28 PM PDT 24
Finished Mar 21 03:24:30 PM PDT 24
Peak memory 215616 kb
Host smart-c15e171e-0751-447f-839c-d6222f3794cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512324038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.512324038
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.891493492
Short name T870
Test name
Test status
Simulation time 246338909 ps
CPU time 3.08 seconds
Started Mar 21 03:24:27 PM PDT 24
Finished Mar 21 03:24:30 PM PDT 24
Peak memory 207176 kb
Host smart-0908d37c-3a75-4d68-bd00-8ca63b461f08
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891493492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.891493492
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.1463699609
Short name T340
Test name
Test status
Simulation time 278696561 ps
CPU time 4.24 seconds
Started Mar 21 03:24:23 PM PDT 24
Finished Mar 21 03:24:28 PM PDT 24
Peak memory 207972 kb
Host smart-a36ffc91-da9c-4185-89c6-1cdf08bf1ef6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463699609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.1463699609
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.3002994748
Short name T635
Test name
Test status
Simulation time 139702230 ps
CPU time 2.42 seconds
Started Mar 21 03:24:30 PM PDT 24
Finished Mar 21 03:24:32 PM PDT 24
Peak memory 210344 kb
Host smart-f3481690-1ecf-4d0c-be99-8a9313b5e870
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3002994748 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.3002994748
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.3230644207
Short name T518
Test name
Test status
Simulation time 15303292 ps
CPU time 0.81 seconds
Started Mar 21 03:24:25 PM PDT 24
Finished Mar 21 03:24:26 PM PDT 24
Peak memory 206380 kb
Host smart-870e573b-ad1c-41f8-addc-daf7fa2abebf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230644207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.3230644207
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.2709210386
Short name T677
Test name
Test status
Simulation time 251334016 ps
CPU time 6.86 seconds
Started Mar 21 03:24:31 PM PDT 24
Finished Mar 21 03:24:38 PM PDT 24
Peak memory 215176 kb
Host smart-cb0b73d4-3c3f-4a95-82b1-6ac0799bc6ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2709210386 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.2709210386
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.1921282293
Short name T878
Test name
Test status
Simulation time 151159570 ps
CPU time 4.68 seconds
Started Mar 21 03:24:31 PM PDT 24
Finished Mar 21 03:24:36 PM PDT 24
Peak memory 210444 kb
Host smart-8d8dbab9-30e7-46ce-bc74-d9a0c352a92b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921282293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.1921282293
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.1985097255
Short name T94
Test name
Test status
Simulation time 3996093955 ps
CPU time 18.05 seconds
Started Mar 21 03:24:27 PM PDT 24
Finished Mar 21 03:24:45 PM PDT 24
Peak memory 223020 kb
Host smart-83bce42d-b751-46e2-9ca5-be6d7303c84e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1985097255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.1985097255
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.846797393
Short name T57
Test name
Test status
Simulation time 39954657 ps
CPU time 2.9 seconds
Started Mar 21 03:24:29 PM PDT 24
Finished Mar 21 03:24:32 PM PDT 24
Peak memory 216372 kb
Host smart-41e43607-cc9e-4a3b-b381-148a30c38274
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846797393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.846797393
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.1476911149
Short name T777
Test name
Test status
Simulation time 679636230 ps
CPU time 10.74 seconds
Started Mar 21 03:24:26 PM PDT 24
Finished Mar 21 03:24:37 PM PDT 24
Peak memory 218704 kb
Host smart-f1b8908c-7006-40fb-be35-24e20f985e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476911149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.1476911149
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.2128025021
Short name T618
Test name
Test status
Simulation time 240770247 ps
CPU time 3.11 seconds
Started Mar 21 03:24:28 PM PDT 24
Finished Mar 21 03:24:31 PM PDT 24
Peak memory 209000 kb
Host smart-357115d7-4126-4e44-b583-900edb2a5d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2128025021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.2128025021
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.2045241228
Short name T627
Test name
Test status
Simulation time 121117402 ps
CPU time 2.98 seconds
Started Mar 21 03:24:26 PM PDT 24
Finished Mar 21 03:24:30 PM PDT 24
Peak memory 209176 kb
Host smart-b32f6e77-035b-4ff2-9087-09c3f1108bae
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045241228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.2045241228
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.3677376598
Short name T539
Test name
Test status
Simulation time 6125073851 ps
CPU time 35.97 seconds
Started Mar 21 03:24:24 PM PDT 24
Finished Mar 21 03:25:00 PM PDT 24
Peak memory 208808 kb
Host smart-bca11189-ad25-461d-b60c-062bf669bf7d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3677376598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.3677376598
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_smoke.1181121633
Short name T474
Test name
Test status
Simulation time 262363654 ps
CPU time 4.96 seconds
Started Mar 21 03:24:25 PM PDT 24
Finished Mar 21 03:24:30 PM PDT 24
Peak memory 207552 kb
Host smart-82070189-cee7-4dc0-becb-d1cddc1a0ddf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1181121633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.1181121633
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.853124488
Short name T696
Test name
Test status
Simulation time 2290908857 ps
CPU time 45.33 seconds
Started Mar 21 03:24:31 PM PDT 24
Finished Mar 21 03:25:17 PM PDT 24
Peak memory 221532 kb
Host smart-c8495823-631b-40f1-8411-b1b6c19e076f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=853124488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.853124488
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.3683269556
Short name T881
Test name
Test status
Simulation time 1113066980 ps
CPU time 6.82 seconds
Started Mar 21 03:24:26 PM PDT 24
Finished Mar 21 03:24:33 PM PDT 24
Peak memory 214792 kb
Host smart-8ebcd7ff-63a6-4761-9263-a33dee941c82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3683269556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.3683269556
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.2694223807
Short name T609
Test name
Test status
Simulation time 161045841 ps
CPU time 3.36 seconds
Started Mar 21 03:24:25 PM PDT 24
Finished Mar 21 03:24:28 PM PDT 24
Peak memory 210380 kb
Host smart-df48723e-22f1-4089-adef-833bc4b526df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2694223807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.2694223807
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.1605587600
Short name T414
Test name
Test status
Simulation time 17961932 ps
CPU time 0.81 seconds
Started Mar 21 03:24:47 PM PDT 24
Finished Mar 21 03:24:48 PM PDT 24
Peak memory 206444 kb
Host smart-022d291c-1614-4ff6-bf24-86c61a9da439
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605587600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.1605587600
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.3691232264
Short name T879
Test name
Test status
Simulation time 527527563 ps
CPU time 26.6 seconds
Started Mar 21 03:24:28 PM PDT 24
Finished Mar 21 03:24:55 PM PDT 24
Peak memory 215408 kb
Host smart-841c5a0c-1c65-4ab5-8796-b6df8e87d747
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3691232264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.3691232264
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.602639173
Short name T64
Test name
Test status
Simulation time 62031609 ps
CPU time 1.84 seconds
Started Mar 21 03:24:28 PM PDT 24
Finished Mar 21 03:24:30 PM PDT 24
Peak memory 207992 kb
Host smart-145ac34e-7b3a-47b4-bce2-d201bec64f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602639173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.602639173
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.3891898890
Short name T289
Test name
Test status
Simulation time 1323635892 ps
CPU time 6.68 seconds
Started Mar 21 03:24:24 PM PDT 24
Finished Mar 21 03:24:31 PM PDT 24
Peak memory 220432 kb
Host smart-5ee57866-d886-4fd0-b357-1d3c637d162f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891898890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.3891898890
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.683292394
Short name T180
Test name
Test status
Simulation time 1214412964 ps
CPU time 7.86 seconds
Started Mar 21 03:24:45 PM PDT 24
Finished Mar 21 03:24:53 PM PDT 24
Peak memory 214780 kb
Host smart-504de9a0-b98b-4f65-b029-610155f32380
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683292394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.683292394
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.2039487809
Short name T624
Test name
Test status
Simulation time 146449949 ps
CPU time 4.15 seconds
Started Mar 21 03:24:25 PM PDT 24
Finished Mar 21 03:24:30 PM PDT 24
Peak memory 215932 kb
Host smart-aab1f140-8e0b-45cc-adcc-271d161e076f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2039487809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.2039487809
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.2258751516
Short name T245
Test name
Test status
Simulation time 234312552 ps
CPU time 4.41 seconds
Started Mar 21 03:24:27 PM PDT 24
Finished Mar 21 03:24:32 PM PDT 24
Peak memory 214820 kb
Host smart-96d7ae9a-f4fa-4724-980e-0d2124380060
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2258751516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.2258751516
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.3600526280
Short name T388
Test name
Test status
Simulation time 2857789287 ps
CPU time 28.51 seconds
Started Mar 21 03:24:28 PM PDT 24
Finished Mar 21 03:24:56 PM PDT 24
Peak memory 208384 kb
Host smart-65366eca-057e-48d1-bec4-354fa7f74397
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600526280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.3600526280
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.305223656
Short name T188
Test name
Test status
Simulation time 33101998 ps
CPU time 1.85 seconds
Started Mar 21 03:24:29 PM PDT 24
Finished Mar 21 03:24:30 PM PDT 24
Peak memory 207148 kb
Host smart-b4359035-bc61-4b77-9c0f-d43c0bd5b07c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=305223656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.305223656
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.1401696630
Short name T482
Test name
Test status
Simulation time 50551033 ps
CPU time 2.76 seconds
Started Mar 21 03:24:26 PM PDT 24
Finished Mar 21 03:24:29 PM PDT 24
Peak memory 207232 kb
Host smart-3eece30b-269f-46e2-b783-fe55a997b778
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1401696630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.1401696630
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.4224833609
Short name T702
Test name
Test status
Simulation time 43359198 ps
CPU time 2.19 seconds
Started Mar 21 03:24:45 PM PDT 24
Finished Mar 21 03:24:47 PM PDT 24
Peak memory 215540 kb
Host smart-a80a4549-b50a-4f9c-b5cb-75fb3e10e261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4224833609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.4224833609
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.1735854128
Short name T646
Test name
Test status
Simulation time 10307032052 ps
CPU time 43.24 seconds
Started Mar 21 03:24:25 PM PDT 24
Finished Mar 21 03:25:08 PM PDT 24
Peak memory 208944 kb
Host smart-c66a8284-b4a8-4a9f-bcff-162317e01df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735854128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.1735854128
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.3610084500
Short name T699
Test name
Test status
Simulation time 1354023285 ps
CPU time 43.99 seconds
Started Mar 21 03:24:47 PM PDT 24
Finished Mar 21 03:25:31 PM PDT 24
Peak memory 209308 kb
Host smart-bc4c42af-0fd6-4a47-8d0f-23a2312b265b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610084500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.3610084500
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.2277625923
Short name T79
Test name
Test status
Simulation time 290244320 ps
CPU time 4.24 seconds
Started Mar 21 03:24:30 PM PDT 24
Finished Mar 21 03:24:35 PM PDT 24
Peak memory 207988 kb
Host smart-08068b81-758d-4119-acd8-1832adc16abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2277625923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.2277625923
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.906466236
Short name T724
Test name
Test status
Simulation time 67891799 ps
CPU time 3.12 seconds
Started Mar 21 03:24:45 PM PDT 24
Finished Mar 21 03:24:48 PM PDT 24
Peak memory 210908 kb
Host smart-6b8dfa8f-5926-43c8-809b-fc15f305f690
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=906466236 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.906466236
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.3628681231
Short name T476
Test name
Test status
Simulation time 50690857 ps
CPU time 0.89 seconds
Started Mar 21 03:24:46 PM PDT 24
Finished Mar 21 03:24:48 PM PDT 24
Peak memory 206308 kb
Host smart-32f9b58c-52c0-4843-afd8-b8c232626468
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3628681231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.3628681231
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.445243492
Short name T400
Test name
Test status
Simulation time 75868867 ps
CPU time 4.07 seconds
Started Mar 21 03:24:42 PM PDT 24
Finished Mar 21 03:24:47 PM PDT 24
Peak memory 215012 kb
Host smart-aaad8d49-5a9d-4c89-9bd7-0e4eb7400fb8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=445243492 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.445243492
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.1172860590
Short name T640
Test name
Test status
Simulation time 2921611380 ps
CPU time 15.7 seconds
Started Mar 21 03:24:45 PM PDT 24
Finished Mar 21 03:25:01 PM PDT 24
Peak memory 210044 kb
Host smart-9573a896-5842-4c19-b3e6-35673bd1bc3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172860590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.1172860590
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.2528208615
Short name T812
Test name
Test status
Simulation time 143203674 ps
CPU time 3.7 seconds
Started Mar 21 03:24:45 PM PDT 24
Finished Mar 21 03:24:49 PM PDT 24
Peak memory 209832 kb
Host smart-5ba584e4-59c6-494b-857f-0a6966ec87c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2528208615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.2528208615
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.2405050852
Short name T458
Test name
Test status
Simulation time 1799120983 ps
CPU time 4.58 seconds
Started Mar 21 03:24:45 PM PDT 24
Finished Mar 21 03:24:50 PM PDT 24
Peak memory 214812 kb
Host smart-e2b36f45-5a4b-40a9-9157-6e3bde7b0e34
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2405050852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.2405050852
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.4070493947
Short name T324
Test name
Test status
Simulation time 53443237 ps
CPU time 2.8 seconds
Started Mar 21 03:24:45 PM PDT 24
Finished Mar 21 03:24:48 PM PDT 24
Peak memory 207092 kb
Host smart-6cdf827f-6ff4-4329-8cbb-b37df8a9780b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4070493947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.4070493947
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.3293340507
Short name T891
Test name
Test status
Simulation time 105555067 ps
CPU time 2.84 seconds
Started Mar 21 03:24:44 PM PDT 24
Finished Mar 21 03:24:47 PM PDT 24
Peak memory 207240 kb
Host smart-c93359ea-082a-4707-a60f-3fedf8a15ee5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3293340507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.3293340507
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.4072286354
Short name T488
Test name
Test status
Simulation time 617919118 ps
CPU time 4.46 seconds
Started Mar 21 03:24:43 PM PDT 24
Finished Mar 21 03:24:48 PM PDT 24
Peak memory 207272 kb
Host smart-1ad19847-001d-40d4-815f-db20d28cbeac
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072286354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.4072286354
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.1010355855
Short name T344
Test name
Test status
Simulation time 32834930 ps
CPU time 2.5 seconds
Started Mar 21 03:24:44 PM PDT 24
Finished Mar 21 03:24:47 PM PDT 24
Peak memory 207136 kb
Host smart-dc8324d3-9a72-4333-8e7f-27a8934e9412
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010355855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.1010355855
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.462356569
Short name T693
Test name
Test status
Simulation time 963244696 ps
CPU time 4.26 seconds
Started Mar 21 03:24:45 PM PDT 24
Finished Mar 21 03:24:49 PM PDT 24
Peak memory 210372 kb
Host smart-ef1ed14e-8e16-4aa5-9a33-b82d9edad15d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462356569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.462356569
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.1682279369
Short name T449
Test name
Test status
Simulation time 115457651 ps
CPU time 3.25 seconds
Started Mar 21 03:24:44 PM PDT 24
Finished Mar 21 03:24:47 PM PDT 24
Peak memory 209116 kb
Host smart-ad53f00b-f950-45c6-a26e-36d8f883a66e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1682279369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.1682279369
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all_with_rand_reset.3001813964
Short name T155
Test name
Test status
Simulation time 726708724 ps
CPU time 30.24 seconds
Started Mar 21 03:24:44 PM PDT 24
Finished Mar 21 03:25:15 PM PDT 24
Peak memory 223188 kb
Host smart-f2df69ef-8aba-4e44-915c-22c82fbbfe0d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001813964 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all_with_rand_reset.3001813964
Directory /workspace/14.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.3553028755
Short name T358
Test name
Test status
Simulation time 106519893 ps
CPU time 5.01 seconds
Started Mar 21 03:24:45 PM PDT 24
Finished Mar 21 03:24:50 PM PDT 24
Peak memory 214820 kb
Host smart-3f239c0e-fac6-4593-9d64-a5041c4f610f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3553028755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.3553028755
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.1767363280
Short name T675
Test name
Test status
Simulation time 19928104 ps
CPU time 0.86 seconds
Started Mar 21 03:24:47 PM PDT 24
Finished Mar 21 03:24:48 PM PDT 24
Peak memory 206460 kb
Host smart-28c4a291-d1d0-4ed9-90c4-782e84cc6298
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1767363280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.1767363280
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.1572290274
Short name T393
Test name
Test status
Simulation time 200586269 ps
CPU time 2.49 seconds
Started Mar 21 03:24:44 PM PDT 24
Finished Mar 21 03:24:47 PM PDT 24
Peak memory 214824 kb
Host smart-0c3d4e04-3189-452b-89ae-64f6444e96e4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1572290274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.1572290274
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.3999197560
Short name T31
Test name
Test status
Simulation time 1785371532 ps
CPU time 36.02 seconds
Started Mar 21 03:24:45 PM PDT 24
Finished Mar 21 03:25:21 PM PDT 24
Peak memory 222888 kb
Host smart-0e5b9f1e-f338-4c73-9298-9498ff9a815b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999197560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.3999197560
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.803343994
Short name T662
Test name
Test status
Simulation time 578142372 ps
CPU time 10.13 seconds
Started Mar 21 03:24:44 PM PDT 24
Finished Mar 21 03:24:55 PM PDT 24
Peak memory 218612 kb
Host smart-f0abb32f-9eb8-471f-a926-95e7068c95de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803343994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.803343994
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.1412771449
Short name T840
Test name
Test status
Simulation time 586683230 ps
CPU time 5.18 seconds
Started Mar 21 03:24:43 PM PDT 24
Finished Mar 21 03:24:49 PM PDT 24
Peak memory 209284 kb
Host smart-31cc0789-2f78-494e-870f-78656aa70d96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412771449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.1412771449
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.4273091782
Short name T258
Test name
Test status
Simulation time 210191462 ps
CPU time 4.22 seconds
Started Mar 21 03:24:45 PM PDT 24
Finished Mar 21 03:24:49 PM PDT 24
Peak memory 221348 kb
Host smart-dd9fb0f7-1918-4989-bf72-7e8a0ed63a78
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4273091782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.4273091782
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.2300355496
Short name T204
Test name
Test status
Simulation time 75138813 ps
CPU time 2.92 seconds
Started Mar 21 03:24:46 PM PDT 24
Finished Mar 21 03:24:49 PM PDT 24
Peak memory 209040 kb
Host smart-90ceabf3-22fb-4704-a411-d7fcc6c0583a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2300355496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.2300355496
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.394583616
Short name T790
Test name
Test status
Simulation time 571731139 ps
CPU time 6 seconds
Started Mar 21 03:24:46 PM PDT 24
Finished Mar 21 03:24:52 PM PDT 24
Peak memory 218852 kb
Host smart-6a2ca8f6-1591-45bb-9f18-aed3e3101f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394583616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.394583616
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.1189534885
Short name T485
Test name
Test status
Simulation time 3483032855 ps
CPU time 22.38 seconds
Started Mar 21 03:24:45 PM PDT 24
Finished Mar 21 03:25:07 PM PDT 24
Peak memory 208520 kb
Host smart-5a6e0242-bcfb-4ca1-ada7-f10327c3f2a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1189534885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.1189534885
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.1537578981
Short name T468
Test name
Test status
Simulation time 72745212 ps
CPU time 1.79 seconds
Started Mar 21 03:24:44 PM PDT 24
Finished Mar 21 03:24:46 PM PDT 24
Peak memory 207352 kb
Host smart-5d40932a-04aa-4c83-9022-6fcc75e63530
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537578981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.1537578981
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.4002364580
Short name T483
Test name
Test status
Simulation time 188569700 ps
CPU time 2.78 seconds
Started Mar 21 03:24:45 PM PDT 24
Finished Mar 21 03:24:48 PM PDT 24
Peak memory 209032 kb
Host smart-960b33a2-7632-4a47-b23b-e49076b2fd58
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4002364580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.4002364580
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.3319478956
Short name T758
Test name
Test status
Simulation time 194605648 ps
CPU time 1.87 seconds
Started Mar 21 03:24:45 PM PDT 24
Finished Mar 21 03:24:47 PM PDT 24
Peak memory 207444 kb
Host smart-c90bceae-11e9-4fb4-af6b-15e26633b0a2
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3319478956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.3319478956
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.1511999669
Short name T448
Test name
Test status
Simulation time 413935778 ps
CPU time 3.81 seconds
Started Mar 21 03:24:47 PM PDT 24
Finished Mar 21 03:24:51 PM PDT 24
Peak memory 216404 kb
Host smart-e47c367b-6190-4e7b-84bf-3b5f152eed67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511999669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.1511999669
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.2870779724
Short name T761
Test name
Test status
Simulation time 53550074 ps
CPU time 2.6 seconds
Started Mar 21 03:24:43 PM PDT 24
Finished Mar 21 03:24:46 PM PDT 24
Peak memory 207092 kb
Host smart-97a07071-103c-4ab6-90a5-ed61175e6f9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870779724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.2870779724
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.1305772206
Short name T55
Test name
Test status
Simulation time 238244268 ps
CPU time 9.17 seconds
Started Mar 21 03:24:46 PM PDT 24
Finished Mar 21 03:24:55 PM PDT 24
Peak memory 217076 kb
Host smart-885642e6-910c-4aea-af0c-52bc93c62a5d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1305772206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.1305772206
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_stress_all_with_rand_reset.392566300
Short name T73
Test name
Test status
Simulation time 130503869 ps
CPU time 8.22 seconds
Started Mar 21 03:24:47 PM PDT 24
Finished Mar 21 03:24:55 PM PDT 24
Peak memory 220848 kb
Host smart-2023e7dc-1f89-4426-ae44-fbd304c2bc23
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=392566300 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all_with_rand_reset.392566300
Directory /workspace/15.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.3612126784
Short name T17
Test name
Test status
Simulation time 86315490 ps
CPU time 4.25 seconds
Started Mar 21 03:24:46 PM PDT 24
Finished Mar 21 03:24:50 PM PDT 24
Peak memory 209572 kb
Host smart-d475c4ef-7535-4b29-8c64-943a84e15c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3612126784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.3612126784
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.2168368130
Short name T540
Test name
Test status
Simulation time 178102036 ps
CPU time 2.35 seconds
Started Mar 21 03:24:45 PM PDT 24
Finished Mar 21 03:24:47 PM PDT 24
Peak memory 210568 kb
Host smart-403c7397-46c8-430f-b165-b961c48f47a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168368130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.2168368130
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.3691381582
Short name T655
Test name
Test status
Simulation time 31160347 ps
CPU time 0.77 seconds
Started Mar 21 03:24:47 PM PDT 24
Finished Mar 21 03:24:48 PM PDT 24
Peak memory 206468 kb
Host smart-9d43acce-c481-4fc3-a62a-b7713f9a5d02
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691381582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.3691381582
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.1659945747
Short name T392
Test name
Test status
Simulation time 407291291 ps
CPU time 10.92 seconds
Started Mar 21 03:24:46 PM PDT 24
Finished Mar 21 03:24:57 PM PDT 24
Peak memory 215084 kb
Host smart-5730c5c9-1fd0-4c2c-91f4-e77101ffed76
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1659945747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.1659945747
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.3290341359
Short name T770
Test name
Test status
Simulation time 139848292 ps
CPU time 3.7 seconds
Started Mar 21 03:24:47 PM PDT 24
Finished Mar 21 03:24:51 PM PDT 24
Peak memory 214828 kb
Host smart-72048046-4df7-46d8-a510-e00c315ab6f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290341359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.3290341359
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.1537304668
Short name T874
Test name
Test status
Simulation time 356990101 ps
CPU time 4.69 seconds
Started Mar 21 03:24:46 PM PDT 24
Finished Mar 21 03:24:52 PM PDT 24
Peak memory 214708 kb
Host smart-5f2a6044-92e5-430f-a4bd-a8e0867e1ac5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537304668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.1537304668
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.1640921844
Short name T611
Test name
Test status
Simulation time 269686118 ps
CPU time 2.69 seconds
Started Mar 21 03:24:44 PM PDT 24
Finished Mar 21 03:24:47 PM PDT 24
Peak memory 214800 kb
Host smart-e382b782-2252-4184-a821-5df30b96d0f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640921844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.1640921844
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.1767658770
Short name T322
Test name
Test status
Simulation time 177392469 ps
CPU time 2.45 seconds
Started Mar 21 03:24:49 PM PDT 24
Finished Mar 21 03:24:51 PM PDT 24
Peak memory 208548 kb
Host smart-700af3cb-5324-448f-a4a3-a9af780213db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767658770 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.1767658770
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.3689824699
Short name T478
Test name
Test status
Simulation time 120973318 ps
CPU time 3.12 seconds
Started Mar 21 03:24:47 PM PDT 24
Finished Mar 21 03:24:50 PM PDT 24
Peak memory 207220 kb
Host smart-220f6658-6a09-47ba-9c84-a3a5e1c4d863
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689824699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.3689824699
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.3279301621
Short name T249
Test name
Test status
Simulation time 73367762 ps
CPU time 2.99 seconds
Started Mar 21 03:24:45 PM PDT 24
Finished Mar 21 03:24:48 PM PDT 24
Peak memory 207248 kb
Host smart-1d0fa6b1-a521-4ee1-bcb9-5c7c06e9a88e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3279301621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.3279301621
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.1914474252
Short name T725
Test name
Test status
Simulation time 81269553 ps
CPU time 3.77 seconds
Started Mar 21 03:24:47 PM PDT 24
Finished Mar 21 03:24:51 PM PDT 24
Peak memory 208792 kb
Host smart-f021229e-d66f-4ee0-a21d-03844f92eaac
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1914474252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.1914474252
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.2426528344
Short name T431
Test name
Test status
Simulation time 345788571 ps
CPU time 4.26 seconds
Started Mar 21 03:24:45 PM PDT 24
Finished Mar 21 03:24:50 PM PDT 24
Peak memory 207436 kb
Host smart-5283ebcf-81a9-4087-80b3-ed72dfaa69c0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2426528344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.2426528344
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.1472246507
Short name T660
Test name
Test status
Simulation time 1870250163 ps
CPU time 23.64 seconds
Started Mar 21 03:24:47 PM PDT 24
Finished Mar 21 03:25:11 PM PDT 24
Peak memory 209292 kb
Host smart-077cf53d-0e10-4c5b-a19b-eca4aafa4266
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1472246507 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.1472246507
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.1018377286
Short name T440
Test name
Test status
Simulation time 78731360 ps
CPU time 3.45 seconds
Started Mar 21 03:24:45 PM PDT 24
Finished Mar 21 03:24:49 PM PDT 24
Peak memory 207188 kb
Host smart-4c79f299-57be-4c2e-a6ac-ecc166e96b9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1018377286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.1018377286
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.2658268116
Short name T307
Test name
Test status
Simulation time 179596889 ps
CPU time 4.13 seconds
Started Mar 21 03:24:48 PM PDT 24
Finished Mar 21 03:24:52 PM PDT 24
Peak memory 218660 kb
Host smart-aefcd638-6ff1-44a2-8a0a-09489d9865bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2658268116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.2658268116
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.456896800
Short name T703
Test name
Test status
Simulation time 381440440 ps
CPU time 2.66 seconds
Started Mar 21 03:24:46 PM PDT 24
Finished Mar 21 03:24:49 PM PDT 24
Peak memory 210076 kb
Host smart-1c9afd28-3ed0-49a8-9988-792da78ea1e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=456896800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.456896800
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.2610181074
Short name T667
Test name
Test status
Simulation time 85616748 ps
CPU time 0.77 seconds
Started Mar 21 03:25:00 PM PDT 24
Finished Mar 21 03:25:01 PM PDT 24
Peak memory 206468 kb
Host smart-c07bb124-9d3f-4bb5-9218-fbb3517d7081
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610181074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.2610181074
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.3459063929
Short name T405
Test name
Test status
Simulation time 939110390 ps
CPU time 47.41 seconds
Started Mar 21 03:24:47 PM PDT 24
Finished Mar 21 03:25:34 PM PDT 24
Peak memory 214836 kb
Host smart-ae0cfab9-c5c5-4367-b7f1-9d7ca70cffa7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3459063929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.3459063929
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.3620097065
Short name T893
Test name
Test status
Simulation time 155302264 ps
CPU time 1.98 seconds
Started Mar 21 03:24:47 PM PDT 24
Finished Mar 21 03:24:49 PM PDT 24
Peak memory 208532 kb
Host smart-cfbf51be-9c0e-4831-99b4-1ac6a080546e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3620097065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.3620097065
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.1081787510
Short name T519
Test name
Test status
Simulation time 60330708 ps
CPU time 1.91 seconds
Started Mar 21 03:24:46 PM PDT 24
Finished Mar 21 03:24:48 PM PDT 24
Peak memory 214892 kb
Host smart-5553ae2e-5930-4550-afab-c4ae3da14d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081787510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.1081787510
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.1884357357
Short name T792
Test name
Test status
Simulation time 4306934731 ps
CPU time 26.53 seconds
Started Mar 21 03:24:48 PM PDT 24
Finished Mar 21 03:25:14 PM PDT 24
Peak memory 210476 kb
Host smart-5333b220-f9d0-4bf1-9878-2a8ddb93f455
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884357357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.1884357357
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.152577366
Short name T629
Test name
Test status
Simulation time 124298139 ps
CPU time 2.28 seconds
Started Mar 21 03:24:47 PM PDT 24
Finished Mar 21 03:24:50 PM PDT 24
Peak memory 207716 kb
Host smart-28878ff3-c849-42dc-966b-4188122b5c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=152577366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.152577366
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.365670625
Short name T565
Test name
Test status
Simulation time 34681825 ps
CPU time 2.27 seconds
Started Mar 21 03:24:47 PM PDT 24
Finished Mar 21 03:24:50 PM PDT 24
Peak memory 207320 kb
Host smart-9e1a7faa-b625-4231-a181-9b9175b2cd81
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=365670625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.365670625
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.3703824693
Short name T659
Test name
Test status
Simulation time 161910046 ps
CPU time 2.56 seconds
Started Mar 21 03:24:49 PM PDT 24
Finished Mar 21 03:24:51 PM PDT 24
Peak memory 207332 kb
Host smart-54dfbd3e-5818-4651-8fbd-4641b96cd379
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703824693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.3703824693
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.3667267975
Short name T876
Test name
Test status
Simulation time 52117286 ps
CPU time 2.85 seconds
Started Mar 21 03:24:47 PM PDT 24
Finished Mar 21 03:24:50 PM PDT 24
Peak memory 207404 kb
Host smart-2c6bf8d9-18c5-49f2-9467-c2ccc1c13913
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3667267975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.3667267975
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.1904553393
Short name T615
Test name
Test status
Simulation time 361397073 ps
CPU time 2.01 seconds
Started Mar 21 03:24:47 PM PDT 24
Finished Mar 21 03:24:49 PM PDT 24
Peak memory 214748 kb
Host smart-235a88aa-0041-44e8-babe-62b07be4200a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904553393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.1904553393
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.141169767
Short name T903
Test name
Test status
Simulation time 968710916 ps
CPU time 3.18 seconds
Started Mar 21 03:24:47 PM PDT 24
Finished Mar 21 03:24:50 PM PDT 24
Peak memory 208820 kb
Host smart-30cf8b13-e789-4f70-97c7-b391acf41a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141169767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.141169767
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.3939495525
Short name T907
Test name
Test status
Simulation time 3741038317 ps
CPU time 43.04 seconds
Started Mar 21 03:24:58 PM PDT 24
Finished Mar 21 03:25:41 PM PDT 24
Peak memory 217544 kb
Host smart-da3ef398-1ca5-4f21-a964-eeb099694872
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939495525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.3939495525
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.3201958653
Short name T332
Test name
Test status
Simulation time 401163847 ps
CPU time 6.56 seconds
Started Mar 21 03:24:47 PM PDT 24
Finished Mar 21 03:24:53 PM PDT 24
Peak memory 218664 kb
Host smart-8f404809-507a-48c4-820f-955fafe3da6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3201958653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.3201958653
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.2655106040
Short name T169
Test name
Test status
Simulation time 76642592 ps
CPU time 2.51 seconds
Started Mar 21 03:24:56 PM PDT 24
Finished Mar 21 03:24:59 PM PDT 24
Peak memory 210268 kb
Host smart-7e4d6107-be9c-42e3-87e6-46e65e0d18f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2655106040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.2655106040
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.20440264
Short name T860
Test name
Test status
Simulation time 14545253 ps
CPU time 0.77 seconds
Started Mar 21 03:25:00 PM PDT 24
Finished Mar 21 03:25:01 PM PDT 24
Peak memory 206452 kb
Host smart-dbd2ae8f-7585-4747-9b4c-905711fe7eb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20440264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.20440264
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.2184940878
Short name T544
Test name
Test status
Simulation time 50305470 ps
CPU time 2.08 seconds
Started Mar 21 03:24:59 PM PDT 24
Finished Mar 21 03:25:01 PM PDT 24
Peak memory 210492 kb
Host smart-17b9665d-d100-4a3d-9273-469f69c974e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184940878 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.2184940878
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.3847891687
Short name T784
Test name
Test status
Simulation time 746815366 ps
CPU time 18.06 seconds
Started Mar 21 03:25:00 PM PDT 24
Finished Mar 21 03:25:18 PM PDT 24
Peak memory 208236 kb
Host smart-52eded43-5fe1-4799-a369-84891d20bc5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847891687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.3847891687
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.2235688625
Short name T801
Test name
Test status
Simulation time 118343082 ps
CPU time 5.32 seconds
Started Mar 21 03:25:00 PM PDT 24
Finished Mar 21 03:25:05 PM PDT 24
Peak memory 214780 kb
Host smart-2e841b93-86d0-4028-8135-9343a8aec96f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235688625 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.2235688625
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.337539077
Short name T684
Test name
Test status
Simulation time 42215565 ps
CPU time 2.76 seconds
Started Mar 21 03:24:56 PM PDT 24
Finished Mar 21 03:24:59 PM PDT 24
Peak memory 212096 kb
Host smart-20ab34fa-8627-44de-bf1c-d7b0c849c101
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337539077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.337539077
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_random.1998593760
Short name T443
Test name
Test status
Simulation time 1099676150 ps
CPU time 7.98 seconds
Started Mar 21 03:24:56 PM PDT 24
Finished Mar 21 03:25:04 PM PDT 24
Peak memory 209352 kb
Host smart-aa0b89d2-4c5c-4051-af9b-6a9eb2c462c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998593760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.1998593760
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.784822504
Short name T183
Test name
Test status
Simulation time 24265701 ps
CPU time 2 seconds
Started Mar 21 03:24:58 PM PDT 24
Finished Mar 21 03:25:00 PM PDT 24
Peak memory 207680 kb
Host smart-fe8228ff-dd43-4f88-b527-a342945bb643
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=784822504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.784822504
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.3168283685
Short name T585
Test name
Test status
Simulation time 173863293 ps
CPU time 2.64 seconds
Started Mar 21 03:24:55 PM PDT 24
Finished Mar 21 03:24:58 PM PDT 24
Peak memory 207180 kb
Host smart-0de25fcb-b145-4ac2-9f68-60ea78fdaf8e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3168283685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.3168283685
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.2848436871
Short name T731
Test name
Test status
Simulation time 41744543 ps
CPU time 2.81 seconds
Started Mar 21 03:24:57 PM PDT 24
Finished Mar 21 03:25:00 PM PDT 24
Peak memory 209256 kb
Host smart-c2866c3a-ada3-42e9-977a-8616eaaa0c4b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848436871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.2848436871
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.2256788106
Short name T751
Test name
Test status
Simulation time 2272637561 ps
CPU time 24.82 seconds
Started Mar 21 03:24:56 PM PDT 24
Finished Mar 21 03:25:21 PM PDT 24
Peak memory 209072 kb
Host smart-e7720aaa-ef5f-4818-a605-0b5a6339f06d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256788106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.2256788106
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.3909304111
Short name T607
Test name
Test status
Simulation time 129861170 ps
CPU time 2.52 seconds
Started Mar 21 03:24:58 PM PDT 24
Finished Mar 21 03:25:01 PM PDT 24
Peak memory 210300 kb
Host smart-0c02f18b-b992-47cb-97bc-0c69e575d602
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909304111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.3909304111
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.1783397671
Short name T586
Test name
Test status
Simulation time 116103095 ps
CPU time 2.76 seconds
Started Mar 21 03:25:00 PM PDT 24
Finished Mar 21 03:25:03 PM PDT 24
Peak memory 208712 kb
Host smart-5a032350-bb70-4b3a-84fc-e4557a8c7c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783397671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.1783397671
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.1688362348
Short name T63
Test name
Test status
Simulation time 268953397 ps
CPU time 12.25 seconds
Started Mar 21 03:24:57 PM PDT 24
Finished Mar 21 03:25:09 PM PDT 24
Peak memory 220480 kb
Host smart-4dcbcb02-907f-4f28-b32a-31c183ffb0c9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1688362348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.1688362348
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_stress_all_with_rand_reset.550574234
Short name T813
Test name
Test status
Simulation time 1450116554 ps
CPU time 13.63 seconds
Started Mar 21 03:25:03 PM PDT 24
Finished Mar 21 03:25:16 PM PDT 24
Peak memory 223096 kb
Host smart-ec265833-244e-4699-a35e-3624e324960b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=550574234 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all_with_rand_reset.550574234
Directory /workspace/18.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.1538585928
Short name T825
Test name
Test status
Simulation time 73545945 ps
CPU time 3.76 seconds
Started Mar 21 03:24:58 PM PDT 24
Finished Mar 21 03:25:02 PM PDT 24
Peak memory 214812 kb
Host smart-2d948990-b836-447c-a64f-b4fc4446a317
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1538585928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.1538585928
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.1881115726
Short name T78
Test name
Test status
Simulation time 40329881 ps
CPU time 0.83 seconds
Started Mar 21 03:25:00 PM PDT 24
Finished Mar 21 03:25:01 PM PDT 24
Peak memory 206440 kb
Host smart-19f7519f-6eef-4db5-976e-4c7865b98fb3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1881115726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.1881115726
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.1567250378
Short name T395
Test name
Test status
Simulation time 132160441 ps
CPU time 2.98 seconds
Started Mar 21 03:24:55 PM PDT 24
Finished Mar 21 03:24:59 PM PDT 24
Peak memory 214784 kb
Host smart-99e71941-094a-42cc-a986-cdbcbf98d58e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1567250378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.1567250378
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.3699174050
Short name T781
Test name
Test status
Simulation time 147097867 ps
CPU time 2.73 seconds
Started Mar 21 03:24:58 PM PDT 24
Finished Mar 21 03:25:00 PM PDT 24
Peak memory 215184 kb
Host smart-c9076e70-9492-46cc-8eba-b180490a85b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3699174050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.3699174050
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.3483852178
Short name T241
Test name
Test status
Simulation time 4871599531 ps
CPU time 32.86 seconds
Started Mar 21 03:24:58 PM PDT 24
Finished Mar 21 03:25:31 PM PDT 24
Peak memory 218836 kb
Host smart-e84b04d4-f99e-49f2-8388-20f031e29786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483852178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.3483852178
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.2203097636
Short name T409
Test name
Test status
Simulation time 73122714 ps
CPU time 3.68 seconds
Started Mar 21 03:25:00 PM PDT 24
Finished Mar 21 03:25:04 PM PDT 24
Peak memory 209616 kb
Host smart-9be05524-3588-47da-84b0-f66c4ba8d11f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2203097636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.2203097636
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.4139468753
Short name T601
Test name
Test status
Simulation time 1705234385 ps
CPU time 11.06 seconds
Started Mar 21 03:25:03 PM PDT 24
Finished Mar 21 03:25:14 PM PDT 24
Peak memory 209912 kb
Host smart-735f04ba-0608-4aac-bca1-81a9344d6080
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139468753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.4139468753
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.3607802106
Short name T330
Test name
Test status
Simulation time 878775648 ps
CPU time 21.66 seconds
Started Mar 21 03:24:56 PM PDT 24
Finished Mar 21 03:25:18 PM PDT 24
Peak memory 209296 kb
Host smart-0c95ae98-db45-4945-873a-5eb6c50ed5c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3607802106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.3607802106
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.1169801263
Short name T349
Test name
Test status
Simulation time 3043123082 ps
CPU time 20.81 seconds
Started Mar 21 03:25:02 PM PDT 24
Finished Mar 21 03:25:23 PM PDT 24
Peak memory 209052 kb
Host smart-56a2aa54-fb5d-44fe-b670-e55833c51b3e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1169801263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.1169801263
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.126581223
Short name T451
Test name
Test status
Simulation time 2602892371 ps
CPU time 20.49 seconds
Started Mar 21 03:25:00 PM PDT 24
Finished Mar 21 03:25:20 PM PDT 24
Peak memory 208444 kb
Host smart-4db73dae-a6a2-4fa7-9bc0-ee74816d0817
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=126581223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.126581223
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.4052623529
Short name T663
Test name
Test status
Simulation time 48957705 ps
CPU time 2.55 seconds
Started Mar 21 03:24:56 PM PDT 24
Finished Mar 21 03:24:59 PM PDT 24
Peak memory 207148 kb
Host smart-7e4140af-f5ca-46f5-8d70-1058f46486dd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4052623529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.4052623529
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.2316861646
Short name T799
Test name
Test status
Simulation time 108302818 ps
CPU time 4.13 seconds
Started Mar 21 03:25:00 PM PDT 24
Finished Mar 21 03:25:04 PM PDT 24
Peak memory 210640 kb
Host smart-62717378-636d-45bc-8362-113571842254
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2316861646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.2316861646
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.127490568
Short name T857
Test name
Test status
Simulation time 395754679 ps
CPU time 5.76 seconds
Started Mar 21 03:25:01 PM PDT 24
Finished Mar 21 03:25:08 PM PDT 24
Peak memory 208396 kb
Host smart-e07e0c29-6012-4270-acbd-b621463de6b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127490568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.127490568
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.2803014858
Short name T326
Test name
Test status
Simulation time 375352278 ps
CPU time 4.63 seconds
Started Mar 21 03:25:01 PM PDT 24
Finished Mar 21 03:25:05 PM PDT 24
Peak memory 218772 kb
Host smart-a910a84e-6f1d-4ed0-9cfb-f244a2532ed7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803014858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.2803014858
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.3863416972
Short name T101
Test name
Test status
Simulation time 318463554 ps
CPU time 2.39 seconds
Started Mar 21 03:24:58 PM PDT 24
Finished Mar 21 03:25:01 PM PDT 24
Peak memory 211068 kb
Host smart-9b952825-b99d-49fa-8bc7-cbe406dbe76a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3863416972 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.3863416972
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.1025907510
Short name T410
Test name
Test status
Simulation time 50955920 ps
CPU time 0.82 seconds
Started Mar 21 03:23:42 PM PDT 24
Finished Mar 21 03:23:43 PM PDT 24
Peak memory 206428 kb
Host smart-7ac4cff5-025b-486e-aef8-cc92b6ed7e96
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025907510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.1025907510
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.284806890
Short name T513
Test name
Test status
Simulation time 1163381418 ps
CPU time 17.75 seconds
Started Mar 21 03:23:44 PM PDT 24
Finished Mar 21 03:24:03 PM PDT 24
Peak memory 209620 kb
Host smart-d0ea79ab-994b-412c-9510-5864fce6f564
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=284806890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.284806890
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.3447830844
Short name T76
Test name
Test status
Simulation time 770890027 ps
CPU time 20.19 seconds
Started Mar 21 03:23:44 PM PDT 24
Finished Mar 21 03:24:05 PM PDT 24
Peak memory 220704 kb
Host smart-39878a10-e384-4df2-9ac7-6ef1f73f80fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447830844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.3447830844
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.1851569446
Short name T194
Test name
Test status
Simulation time 484373757 ps
CPU time 5.53 seconds
Started Mar 21 03:23:42 PM PDT 24
Finished Mar 21 03:23:48 PM PDT 24
Peak memory 222944 kb
Host smart-04b0fc5c-9449-4cbc-97c3-43fd08d2be22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1851569446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.1851569446
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.3022245489
Short name T237
Test name
Test status
Simulation time 55728386 ps
CPU time 3.41 seconds
Started Mar 21 03:23:44 PM PDT 24
Finished Mar 21 03:23:49 PM PDT 24
Peak memory 210624 kb
Host smart-9290db43-48e5-4f7d-9006-c127403402ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3022245489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.3022245489
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.1318274777
Short name T528
Test name
Test status
Simulation time 472043284 ps
CPU time 4.72 seconds
Started Mar 21 03:23:40 PM PDT 24
Finished Mar 21 03:23:45 PM PDT 24
Peak memory 210740 kb
Host smart-11e6f9f7-2856-43d0-97b5-01e43e83b850
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318274777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.1318274777
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.2400790121
Short name T100
Test name
Test status
Simulation time 1236563688 ps
CPU time 28.69 seconds
Started Mar 21 03:23:44 PM PDT 24
Finished Mar 21 03:24:14 PM PDT 24
Peak memory 238964 kb
Host smart-62a00a2a-dbd2-45a3-b56d-81e7b181480d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400790121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.2400790121
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.167983135
Short name T500
Test name
Test status
Simulation time 34472903 ps
CPU time 2.54 seconds
Started Mar 21 03:23:43 PM PDT 24
Finished Mar 21 03:23:46 PM PDT 24
Peak memory 207824 kb
Host smart-ec8b244b-6575-4c8b-a26a-38cc2a6ca9c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167983135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.167983135
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.4042596992
Short name T700
Test name
Test status
Simulation time 20678223 ps
CPU time 1.83 seconds
Started Mar 21 03:23:49 PM PDT 24
Finished Mar 21 03:23:51 PM PDT 24
Peak memory 207236 kb
Host smart-c12c59ca-de04-40d4-82de-4dc2b0bb657d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042596992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.4042596992
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.2541759804
Short name T190
Test name
Test status
Simulation time 37917889 ps
CPU time 2.43 seconds
Started Mar 21 03:23:45 PM PDT 24
Finished Mar 21 03:23:48 PM PDT 24
Peak memory 207244 kb
Host smart-131f3f51-5a32-4d7a-a7b7-b20b091ad557
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541759804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.2541759804
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.1010709727
Short name T619
Test name
Test status
Simulation time 120567130 ps
CPU time 4.76 seconds
Started Mar 21 03:23:43 PM PDT 24
Finished Mar 21 03:23:48 PM PDT 24
Peak memory 208704 kb
Host smart-4df16dab-0f3c-4cd4-8bef-09412b41136a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1010709727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.1010709727
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.1645067928
Short name T362
Test name
Test status
Simulation time 529173519 ps
CPU time 17.34 seconds
Started Mar 21 03:23:42 PM PDT 24
Finished Mar 21 03:23:59 PM PDT 24
Peak memory 209064 kb
Host smart-88f779d1-f6da-463a-b13b-d0e352d9a261
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1645067928 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.1645067928
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.1963629502
Short name T679
Test name
Test status
Simulation time 248586994 ps
CPU time 6.17 seconds
Started Mar 21 03:23:48 PM PDT 24
Finished Mar 21 03:23:54 PM PDT 24
Peak memory 208688 kb
Host smart-b5040570-a052-4cac-a6fb-97fda4117857
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963629502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.1963629502
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_stress_all_with_rand_reset.1400657277
Short name T757
Test name
Test status
Simulation time 486072526 ps
CPU time 15.92 seconds
Started Mar 21 03:23:44 PM PDT 24
Finished Mar 21 03:24:01 PM PDT 24
Peak memory 223120 kb
Host smart-87c878ee-db80-4ee0-9a9b-57207fb47b87
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1400657277 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all_with_rand_reset.1400657277
Directory /workspace/2.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.1151308081
Short name T800
Test name
Test status
Simulation time 40141314 ps
CPU time 2.96 seconds
Started Mar 21 03:23:41 PM PDT 24
Finished Mar 21 03:23:44 PM PDT 24
Peak memory 207744 kb
Host smart-0b080d15-68fa-4117-8a70-6c5d6916c7fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151308081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.1151308081
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.3291868398
Short name T569
Test name
Test status
Simulation time 10151355 ps
CPU time 0.86 seconds
Started Mar 21 03:25:02 PM PDT 24
Finished Mar 21 03:25:03 PM PDT 24
Peak memory 206368 kb
Host smart-14cac6d3-cb0d-4a62-b5be-3298c93cf51c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291868398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.3291868398
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.93936160
Short name T217
Test name
Test status
Simulation time 313768590 ps
CPU time 4.96 seconds
Started Mar 21 03:25:01 PM PDT 24
Finished Mar 21 03:25:06 PM PDT 24
Peak memory 214800 kb
Host smart-ce07bb0d-17c3-497d-b320-0aeb40e3d53f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=93936160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.93936160
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.3183081914
Short name T36
Test name
Test status
Simulation time 147235963 ps
CPU time 2.45 seconds
Started Mar 21 03:25:06 PM PDT 24
Finished Mar 21 03:25:09 PM PDT 24
Peak memory 210464 kb
Host smart-1a5dd6ba-f09d-4c3a-a7c3-192fa7eb5913
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3183081914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.3183081914
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.3438152246
Short name T53
Test name
Test status
Simulation time 137317553 ps
CPU time 4.44 seconds
Started Mar 21 03:25:17 PM PDT 24
Finished Mar 21 03:25:22 PM PDT 24
Peak memory 208712 kb
Host smart-c89a9ab4-67a5-47de-b0c1-67aba5f6169b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3438152246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.3438152246
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.432848693
Short name T278
Test name
Test status
Simulation time 332417218 ps
CPU time 3.89 seconds
Started Mar 21 03:25:04 PM PDT 24
Finished Mar 21 03:25:08 PM PDT 24
Peak memory 208840 kb
Host smart-ba784bfc-2591-4415-9e0f-0791999301e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432848693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.432848693
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.2177747315
Short name T823
Test name
Test status
Simulation time 74712195 ps
CPU time 2.53 seconds
Started Mar 21 03:25:00 PM PDT 24
Finished Mar 21 03:25:03 PM PDT 24
Peak memory 221084 kb
Host smart-151d2edf-32f6-4726-bdac-16340f4d2749
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2177747315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.2177747315
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.2470711681
Short name T888
Test name
Test status
Simulation time 56899184 ps
CPU time 3.66 seconds
Started Mar 21 03:25:04 PM PDT 24
Finished Mar 21 03:25:08 PM PDT 24
Peak memory 210608 kb
Host smart-acdda40e-ef32-4c57-a881-19a360c6d2bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2470711681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.2470711681
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.4251042450
Short name T554
Test name
Test status
Simulation time 48418383 ps
CPU time 2.56 seconds
Started Mar 21 03:25:00 PM PDT 24
Finished Mar 21 03:25:02 PM PDT 24
Peak memory 207336 kb
Host smart-33b810b7-a81a-47d9-9761-98ab6a4a93bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4251042450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.4251042450
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.4219068285
Short name T286
Test name
Test status
Simulation time 41019041 ps
CPU time 2.79 seconds
Started Mar 21 03:25:01 PM PDT 24
Finished Mar 21 03:25:04 PM PDT 24
Peak memory 209136 kb
Host smart-9f6efdd5-7411-46bd-bf80-82aa3e72e5ef
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219068285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.4219068285
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.3211378579
Short name T773
Test name
Test status
Simulation time 44357947 ps
CPU time 1.93 seconds
Started Mar 21 03:24:58 PM PDT 24
Finished Mar 21 03:25:00 PM PDT 24
Peak memory 207396 kb
Host smart-28ec0f57-2fcc-40e6-9060-f921f86894cf
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211378579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.3211378579
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.4134282785
Short name T564
Test name
Test status
Simulation time 63844105 ps
CPU time 3.11 seconds
Started Mar 21 03:25:04 PM PDT 24
Finished Mar 21 03:25:07 PM PDT 24
Peak memory 207212 kb
Host smart-1af640d6-26ef-4674-b053-2062266a2303
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4134282785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.4134282785
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_smoke.4009988690
Short name T435
Test name
Test status
Simulation time 299932057 ps
CPU time 4.66 seconds
Started Mar 21 03:24:59 PM PDT 24
Finished Mar 21 03:25:04 PM PDT 24
Peak memory 209044 kb
Host smart-0f2afa07-9784-4d7f-8351-0b3b6923c18f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4009988690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.4009988690
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.637505341
Short name T380
Test name
Test status
Simulation time 153809928 ps
CPU time 6.26 seconds
Started Mar 21 03:25:06 PM PDT 24
Finished Mar 21 03:25:13 PM PDT 24
Peak memory 207284 kb
Host smart-8194602c-db50-4231-adbf-3291be4516a8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=637505341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.637505341
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.2804262670
Short name T649
Test name
Test status
Simulation time 129570310 ps
CPU time 5.84 seconds
Started Mar 21 03:25:04 PM PDT 24
Finished Mar 21 03:25:10 PM PDT 24
Peak memory 218720 kb
Host smart-766184ee-2904-4586-b716-eb72b01e7461
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804262670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.2804262670
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.3773234870
Short name T426
Test name
Test status
Simulation time 145088066 ps
CPU time 1.88 seconds
Started Mar 21 03:25:06 PM PDT 24
Finished Mar 21 03:25:08 PM PDT 24
Peak memory 210660 kb
Host smart-26b50345-d0f0-44c3-a0f5-448a3aa4e954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3773234870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.3773234870
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.4173112559
Short name T815
Test name
Test status
Simulation time 42558802 ps
CPU time 0.76 seconds
Started Mar 21 03:25:10 PM PDT 24
Finished Mar 21 03:25:12 PM PDT 24
Peak memory 206388 kb
Host smart-de5ed4c5-4849-456b-af97-9bf94ee640de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173112559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.4173112559
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.223890807
Short name T576
Test name
Test status
Simulation time 57519918 ps
CPU time 2.41 seconds
Started Mar 21 03:25:05 PM PDT 24
Finished Mar 21 03:25:07 PM PDT 24
Peak memory 214800 kb
Host smart-ba57d18f-73ee-49c3-95ac-29d155e4435c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=223890807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.223890807
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.1558265749
Short name T647
Test name
Test status
Simulation time 236257243 ps
CPU time 3.51 seconds
Started Mar 21 03:25:06 PM PDT 24
Finished Mar 21 03:25:10 PM PDT 24
Peak memory 214600 kb
Host smart-bd5a04b2-edca-4909-a248-0d933f6322cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1558265749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.1558265749
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.2081688290
Short name T829
Test name
Test status
Simulation time 112578830 ps
CPU time 3.74 seconds
Started Mar 21 03:25:04 PM PDT 24
Finished Mar 21 03:25:08 PM PDT 24
Peak memory 210144 kb
Host smart-3bd8fc23-c182-47bb-8472-d5e6f5bd0017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2081688290 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.2081688290
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.3178297684
Short name T18
Test name
Test status
Simulation time 191956360 ps
CPU time 5.5 seconds
Started Mar 21 03:25:06 PM PDT 24
Finished Mar 21 03:25:12 PM PDT 24
Peak memory 207616 kb
Host smart-a4359038-173d-4b99-8152-a7c30d6d706d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3178297684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.3178297684
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.467407609
Short name T685
Test name
Test status
Simulation time 196371044 ps
CPU time 4.58 seconds
Started Mar 21 03:25:06 PM PDT 24
Finished Mar 21 03:25:10 PM PDT 24
Peak memory 208888 kb
Host smart-2c726a65-3fbb-405d-820c-be64e39a187a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=467407609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.467407609
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.3635854807
Short name T125
Test name
Test status
Simulation time 110580582 ps
CPU time 3.8 seconds
Started Mar 21 03:25:05 PM PDT 24
Finished Mar 21 03:25:09 PM PDT 24
Peak memory 209028 kb
Host smart-64028053-6e53-48dd-9a50-6f0165608fcf
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3635854807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.3635854807
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.2911945124
Short name T499
Test name
Test status
Simulation time 145714120 ps
CPU time 3.47 seconds
Started Mar 21 03:25:05 PM PDT 24
Finished Mar 21 03:25:09 PM PDT 24
Peak memory 207296 kb
Host smart-231d2ce6-a74d-4517-a6f1-1db8a6536307
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911945124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.2911945124
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.4034979327
Short name T637
Test name
Test status
Simulation time 662146386 ps
CPU time 5.51 seconds
Started Mar 21 03:25:05 PM PDT 24
Finished Mar 21 03:25:11 PM PDT 24
Peak memory 209256 kb
Host smart-8cc68a04-62ce-47e2-b5a4-c7de71f714a6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4034979327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.4034979327
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.2427397508
Short name T708
Test name
Test status
Simulation time 20483731 ps
CPU time 1.62 seconds
Started Mar 21 03:25:10 PM PDT 24
Finished Mar 21 03:25:12 PM PDT 24
Peak memory 210100 kb
Host smart-724955ad-6d6f-4487-bda3-448453ae6e35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2427397508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.2427397508
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.1642355515
Short name T887
Test name
Test status
Simulation time 45532256 ps
CPU time 2.43 seconds
Started Mar 21 03:25:05 PM PDT 24
Finished Mar 21 03:25:07 PM PDT 24
Peak memory 208744 kb
Host smart-636a1eba-8eae-4620-bbd4-da05353b61fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642355515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.1642355515
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.1244626362
Short name T290
Test name
Test status
Simulation time 430636434 ps
CPU time 6.97 seconds
Started Mar 21 03:25:06 PM PDT 24
Finished Mar 21 03:25:13 PM PDT 24
Peak memory 210112 kb
Host smart-15c67aa4-93d5-41c3-9df2-8087f9943b68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1244626362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.1244626362
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.801002662
Short name T650
Test name
Test status
Simulation time 173205036 ps
CPU time 2.46 seconds
Started Mar 21 03:25:05 PM PDT 24
Finished Mar 21 03:25:08 PM PDT 24
Peak memory 210236 kb
Host smart-fb494352-d505-4cf2-a8bd-f9bf62322eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=801002662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.801002662
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.4198292817
Short name T766
Test name
Test status
Simulation time 10602295 ps
CPU time 0.73 seconds
Started Mar 21 03:24:58 PM PDT 24
Finished Mar 21 03:24:59 PM PDT 24
Peak memory 206436 kb
Host smart-1747addb-8d7e-494d-ac2d-a791c9a5281e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198292817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.4198292817
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.382134224
Short name T295
Test name
Test status
Simulation time 66631111 ps
CPU time 3.23 seconds
Started Mar 21 03:25:09 PM PDT 24
Finished Mar 21 03:25:12 PM PDT 24
Peak memory 215976 kb
Host smart-951da7a0-f6b6-468d-b2e1-12c472bc4dbf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=382134224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.382134224
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.2201145416
Short name T683
Test name
Test status
Simulation time 737428988 ps
CPU time 4.7 seconds
Started Mar 21 03:24:59 PM PDT 24
Finished Mar 21 03:25:04 PM PDT 24
Peak memory 219008 kb
Host smart-fe855e6b-aa42-43df-9e57-76c8ade59519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2201145416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.2201145416
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.834428330
Short name T570
Test name
Test status
Simulation time 636037945 ps
CPU time 12.87 seconds
Started Mar 21 03:24:59 PM PDT 24
Finished Mar 21 03:25:12 PM PDT 24
Peak memory 209316 kb
Host smart-9b6f876f-625f-4c60-969e-edc6b6f7cf6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834428330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.834428330
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.13024523
Short name T281
Test name
Test status
Simulation time 785554957 ps
CPU time 6.34 seconds
Started Mar 21 03:24:56 PM PDT 24
Finished Mar 21 03:25:02 PM PDT 24
Peak memory 223012 kb
Host smart-f923c8dd-b9ae-4ad3-a55c-290e23a1f7ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13024523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.13024523
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.3582220061
Short name T209
Test name
Test status
Simulation time 136711087 ps
CPU time 3.39 seconds
Started Mar 21 03:24:57 PM PDT 24
Finished Mar 21 03:25:01 PM PDT 24
Peak memory 209456 kb
Host smart-89fc4dd2-8cca-4f73-8add-06b63aeca97c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582220061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.3582220061
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.2985024922
Short name T567
Test name
Test status
Simulation time 121108888 ps
CPU time 3.01 seconds
Started Mar 21 03:25:09 PM PDT 24
Finished Mar 21 03:25:12 PM PDT 24
Peak memory 209272 kb
Host smart-5547f96d-ea1a-42ef-aefa-2f8c2f8265cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2985024922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.2985024922
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.1729685561
Short name T3
Test name
Test status
Simulation time 382003569 ps
CPU time 2.86 seconds
Started Mar 21 03:25:08 PM PDT 24
Finished Mar 21 03:25:12 PM PDT 24
Peak memory 207020 kb
Host smart-b52641a7-cd4e-4610-a22f-55ccaaed9b8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729685561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.1729685561
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.623143680
Short name T559
Test name
Test status
Simulation time 169717228 ps
CPU time 3.59 seconds
Started Mar 21 03:25:00 PM PDT 24
Finished Mar 21 03:25:04 PM PDT 24
Peak memory 209396 kb
Host smart-e25af591-0a49-49a9-9fdf-c3887297296e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=623143680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.623143680
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.2864111581
Short name T491
Test name
Test status
Simulation time 113037913 ps
CPU time 2.46 seconds
Started Mar 21 03:25:08 PM PDT 24
Finished Mar 21 03:25:11 PM PDT 24
Peak memory 207264 kb
Host smart-10bc9c76-f0f6-4deb-ae26-766d14234429
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864111581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.2864111581
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.559866612
Short name T831
Test name
Test status
Simulation time 195896698 ps
CPU time 2.98 seconds
Started Mar 21 03:25:10 PM PDT 24
Finished Mar 21 03:25:14 PM PDT 24
Peak memory 207304 kb
Host smart-693149d5-1a42-4d20-b956-c3e1af2d3080
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=559866612 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.559866612
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.4158869427
Short name T894
Test name
Test status
Simulation time 57077332 ps
CPU time 2.75 seconds
Started Mar 21 03:24:56 PM PDT 24
Finished Mar 21 03:24:59 PM PDT 24
Peak memory 208932 kb
Host smart-8dfaafbd-c941-4f7a-b01c-0c5d9cb2401a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158869427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.4158869427
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.4050543149
Short name T546
Test name
Test status
Simulation time 179629756 ps
CPU time 4.36 seconds
Started Mar 21 03:25:09 PM PDT 24
Finished Mar 21 03:25:13 PM PDT 24
Peak memory 207640 kb
Host smart-9db6b004-cb50-4f32-9a43-4ee897f3c52b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4050543149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.4050543149
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.1787499593
Short name T810
Test name
Test status
Simulation time 115506666 ps
CPU time 5.28 seconds
Started Mar 21 03:24:59 PM PDT 24
Finished Mar 21 03:25:04 PM PDT 24
Peak memory 214860 kb
Host smart-35d143d7-092c-4937-b4ab-fa5085361d5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787499593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.1787499593
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.4258336444
Short name T844
Test name
Test status
Simulation time 61547345 ps
CPU time 0.84 seconds
Started Mar 21 03:25:28 PM PDT 24
Finished Mar 21 03:25:29 PM PDT 24
Peak memory 206456 kb
Host smart-5e070a3f-7378-47fa-952a-756023769286
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258336444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.4258336444
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.315053273
Short name T406
Test name
Test status
Simulation time 28557224 ps
CPU time 2.38 seconds
Started Mar 21 03:25:02 PM PDT 24
Finished Mar 21 03:25:05 PM PDT 24
Peak memory 214848 kb
Host smart-32ab3891-bdfe-48a8-9b3b-57abd08261ff
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=315053273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.315053273
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.864833232
Short name T42
Test name
Test status
Simulation time 139680773 ps
CPU time 5.18 seconds
Started Mar 21 03:25:28 PM PDT 24
Finished Mar 21 03:25:34 PM PDT 24
Peak memory 218884 kb
Host smart-5f9abea3-51a6-4c54-a63c-dbebc0a42fd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=864833232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.864833232
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.907794898
Short name T625
Test name
Test status
Simulation time 1162817941 ps
CPU time 11.71 seconds
Started Mar 21 03:25:29 PM PDT 24
Finished Mar 21 03:25:41 PM PDT 24
Peak memory 209132 kb
Host smart-09ad3dac-e6f5-42e7-bbb0-7e786d404958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907794898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.907794898
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.4075644297
Short name T575
Test name
Test status
Simulation time 1026911501 ps
CPU time 30.36 seconds
Started Mar 21 03:25:20 PM PDT 24
Finished Mar 21 03:25:50 PM PDT 24
Peak memory 209692 kb
Host smart-2a15cbed-a981-4341-a3ea-d8fb83cd75cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4075644297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.4075644297
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.3123435963
Short name T47
Test name
Test status
Simulation time 115785277 ps
CPU time 3.72 seconds
Started Mar 21 03:25:18 PM PDT 24
Finished Mar 21 03:25:22 PM PDT 24
Peak memory 214740 kb
Host smart-e1c50e78-85ad-4658-bd27-c51e6d8d2084
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3123435963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.3123435963
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.1688391074
Short name T227
Test name
Test status
Simulation time 314873314 ps
CPU time 4.83 seconds
Started Mar 21 03:24:58 PM PDT 24
Finished Mar 21 03:25:03 PM PDT 24
Peak memory 209872 kb
Host smart-51ad1b5d-ea61-43a2-8ae6-1054ea85e16d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688391074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.1688391074
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.4094342536
Short name T242
Test name
Test status
Simulation time 367344894 ps
CPU time 9.58 seconds
Started Mar 21 03:25:02 PM PDT 24
Finished Mar 21 03:25:12 PM PDT 24
Peak memory 208340 kb
Host smart-c592ea66-f16f-4001-9a4e-59bbbc335a74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094342536 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.4094342536
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.3037474723
Short name T653
Test name
Test status
Simulation time 44976995 ps
CPU time 2.6 seconds
Started Mar 21 03:25:06 PM PDT 24
Finished Mar 21 03:25:08 PM PDT 24
Peak memory 209140 kb
Host smart-a2c3df25-6cce-47af-91f1-4595ce263db0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3037474723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.3037474723
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.1146024410
Short name T687
Test name
Test status
Simulation time 61474988 ps
CPU time 3.04 seconds
Started Mar 21 03:25:01 PM PDT 24
Finished Mar 21 03:25:04 PM PDT 24
Peak memory 208912 kb
Host smart-de450ae0-b2da-4dab-b89f-fe4f6e838f3a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1146024410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.1146024410
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.1983154582
Short name T497
Test name
Test status
Simulation time 3136465286 ps
CPU time 29.73 seconds
Started Mar 21 03:25:03 PM PDT 24
Finished Mar 21 03:25:33 PM PDT 24
Peak memory 208864 kb
Host smart-48d6ed30-583e-4200-b2d1-55b7087017ca
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1983154582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.1983154582
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.1904360177
Short name T769
Test name
Test status
Simulation time 105887344 ps
CPU time 3.48 seconds
Started Mar 21 03:25:29 PM PDT 24
Finished Mar 21 03:25:33 PM PDT 24
Peak memory 214776 kb
Host smart-c538fce5-1a09-4685-b676-bbc37c0c88e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904360177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.1904360177
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.3856529223
Short name T584
Test name
Test status
Simulation time 385785488 ps
CPU time 4.71 seconds
Started Mar 21 03:24:58 PM PDT 24
Finished Mar 21 03:25:03 PM PDT 24
Peak memory 207132 kb
Host smart-7fa00a96-ef95-4d45-8d0b-3edb02bec245
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856529223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.3856529223
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.268817889
Short name T317
Test name
Test status
Simulation time 2188792395 ps
CPU time 56.69 seconds
Started Mar 21 03:25:21 PM PDT 24
Finished Mar 21 03:26:18 PM PDT 24
Peak memory 216448 kb
Host smart-a8ab4ab7-4779-49fb-84f0-da482302a323
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=268817889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.268817889
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.2668490052
Short name T747
Test name
Test status
Simulation time 215443453 ps
CPU time 3.2 seconds
Started Mar 21 03:25:19 PM PDT 24
Finished Mar 21 03:25:22 PM PDT 24
Peak memory 210888 kb
Host smart-e8736e9a-c18d-49e7-b86a-614236bc2be5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668490052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.2668490052
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.1321618611
Short name T97
Test name
Test status
Simulation time 40152989 ps
CPU time 0.74 seconds
Started Mar 21 03:25:19 PM PDT 24
Finished Mar 21 03:25:20 PM PDT 24
Peak memory 206448 kb
Host smart-7a704b8f-0442-4b69-bba4-ac51f2332c77
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321618611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.1321618611
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.3822039807
Short name T381
Test name
Test status
Simulation time 110313423 ps
CPU time 2.58 seconds
Started Mar 21 03:25:20 PM PDT 24
Finished Mar 21 03:25:22 PM PDT 24
Peak memory 214820 kb
Host smart-149c3261-b423-4afc-b38f-91650d9e8d62
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3822039807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.3822039807
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.919560234
Short name T552
Test name
Test status
Simulation time 4439817444 ps
CPU time 31.08 seconds
Started Mar 21 03:25:30 PM PDT 24
Finished Mar 21 03:26:01 PM PDT 24
Peak memory 209068 kb
Host smart-77a7076a-3637-4f3c-8e5d-2bb6ab5dbc8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=919560234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.919560234
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.2673611600
Short name T373
Test name
Test status
Simulation time 6450467893 ps
CPU time 41.34 seconds
Started Mar 21 03:25:18 PM PDT 24
Finished Mar 21 03:26:00 PM PDT 24
Peak memory 214832 kb
Host smart-5efe9b2f-737b-404c-b853-e03f747582d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2673611600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.2673611600
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.1281384951
Short name T203
Test name
Test status
Simulation time 1786082368 ps
CPU time 3.58 seconds
Started Mar 21 03:25:20 PM PDT 24
Finished Mar 21 03:25:24 PM PDT 24
Peak memory 209356 kb
Host smart-e56b42b5-15ad-4041-8c99-aa3edbc95e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1281384951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.1281384951
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.1886836930
Short name T525
Test name
Test status
Simulation time 5743276309 ps
CPU time 23.48 seconds
Started Mar 21 03:25:19 PM PDT 24
Finished Mar 21 03:25:43 PM PDT 24
Peak memory 208604 kb
Host smart-82de3913-27e7-4edc-92f0-ed0affe316b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1886836930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.1886836930
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.1233202642
Short name T261
Test name
Test status
Simulation time 276391116 ps
CPU time 3.9 seconds
Started Mar 21 03:25:23 PM PDT 24
Finished Mar 21 03:25:27 PM PDT 24
Peak memory 208708 kb
Host smart-d52e671e-08ed-4bb2-85c2-c7673da52c2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233202642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.1233202642
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.4118208610
Short name T425
Test name
Test status
Simulation time 26986426 ps
CPU time 2.31 seconds
Started Mar 21 03:25:18 PM PDT 24
Finished Mar 21 03:25:20 PM PDT 24
Peak memory 209212 kb
Host smart-1e2b5d18-ff06-4088-9680-8cb01a340045
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4118208610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.4118208610
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.1161677510
Short name T578
Test name
Test status
Simulation time 288489454 ps
CPU time 4.64 seconds
Started Mar 21 03:25:21 PM PDT 24
Finished Mar 21 03:25:26 PM PDT 24
Peak memory 208780 kb
Host smart-488ad20e-f4cb-4a9f-8175-b91936000c0d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161677510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.1161677510
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.410331873
Short name T356
Test name
Test status
Simulation time 81200094 ps
CPU time 3.53 seconds
Started Mar 21 03:25:18 PM PDT 24
Finished Mar 21 03:25:22 PM PDT 24
Peak memory 208944 kb
Host smart-fb88a016-9e91-424d-928d-bcaa62983b67
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=410331873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.410331873
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.1235800907
Short name T182
Test name
Test status
Simulation time 94599960 ps
CPU time 1.95 seconds
Started Mar 21 03:25:27 PM PDT 24
Finished Mar 21 03:25:29 PM PDT 24
Peak memory 208332 kb
Host smart-c7a74378-51f1-45e0-8188-bb4ff93a1f35
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235800907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.1235800907
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.119016155
Short name T716
Test name
Test status
Simulation time 268501518 ps
CPU time 5.14 seconds
Started Mar 21 03:25:21 PM PDT 24
Finished Mar 21 03:25:27 PM PDT 24
Peak memory 207204 kb
Host smart-fda2ed1a-64c3-4a29-8572-0ac3cd256689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=119016155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.119016155
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.2120829330
Short name T446
Test name
Test status
Simulation time 3554366521 ps
CPU time 31.18 seconds
Started Mar 21 03:25:20 PM PDT 24
Finished Mar 21 03:25:51 PM PDT 24
Peak memory 209020 kb
Host smart-b9f8fffa-4269-4efc-a5d8-d75e1b5d8ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120829330 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.2120829330
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.690176760
Short name T871
Test name
Test status
Simulation time 58647478 ps
CPU time 2.06 seconds
Started Mar 21 03:25:22 PM PDT 24
Finished Mar 21 03:25:25 PM PDT 24
Peak memory 210716 kb
Host smart-595d6a6c-71ee-4c7e-8933-6dafe6caea3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690176760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.690176760
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.795585987
Short name T418
Test name
Test status
Simulation time 140466463 ps
CPU time 0.91 seconds
Started Mar 21 03:25:36 PM PDT 24
Finished Mar 21 03:25:37 PM PDT 24
Peak memory 206384 kb
Host smart-6fece8a9-d942-4959-bf7e-c79ca5a403de
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=795585987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.795585987
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.4228097844
Short name T291
Test name
Test status
Simulation time 119154042 ps
CPU time 6.54 seconds
Started Mar 21 03:25:37 PM PDT 24
Finished Mar 21 03:25:44 PM PDT 24
Peak memory 214800 kb
Host smart-5b42ac2a-8550-4ec8-bc77-337ed39432f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4228097844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.4228097844
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.4051759213
Short name T631
Test name
Test status
Simulation time 245997289 ps
CPU time 2.61 seconds
Started Mar 21 03:25:35 PM PDT 24
Finished Mar 21 03:25:39 PM PDT 24
Peak memory 207936 kb
Host smart-ed546b30-1cff-43a8-af12-c5e887bff448
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4051759213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.4051759213
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.2907122654
Short name T867
Test name
Test status
Simulation time 1453051141 ps
CPU time 19.98 seconds
Started Mar 21 03:25:36 PM PDT 24
Finished Mar 21 03:25:57 PM PDT 24
Peak memory 209488 kb
Host smart-027e39b9-930f-4286-ac01-58da76d599b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907122654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.2907122654
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.1792555047
Short name T836
Test name
Test status
Simulation time 695826378 ps
CPU time 11.78 seconds
Started Mar 21 03:25:37 PM PDT 24
Finished Mar 21 03:25:49 PM PDT 24
Peak memory 214692 kb
Host smart-03b8ede2-05c7-40ca-87d1-71bfd6c7e363
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1792555047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.1792555047
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.167120551
Short name T44
Test name
Test status
Simulation time 207613707 ps
CPU time 4.03 seconds
Started Mar 21 03:25:35 PM PDT 24
Finished Mar 21 03:25:39 PM PDT 24
Peak memory 220256 kb
Host smart-27eadc3a-1d45-4489-9862-1502216029c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167120551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.167120551
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.1858475463
Short name T368
Test name
Test status
Simulation time 1204092162 ps
CPU time 22.4 seconds
Started Mar 21 03:25:35 PM PDT 24
Finished Mar 21 03:25:58 PM PDT 24
Peak memory 208908 kb
Host smart-d24e6243-2fb8-4c48-bc81-7b544ddeb470
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858475463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.1858475463
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.604519861
Short name T501
Test name
Test status
Simulation time 50282941 ps
CPU time 2.9 seconds
Started Mar 21 03:25:30 PM PDT 24
Finished Mar 21 03:25:33 PM PDT 24
Peak memory 207224 kb
Host smart-e1ffce8e-01c2-4f0f-abed-c10efbcd7df2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=604519861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.604519861
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.785239626
Short name T108
Test name
Test status
Simulation time 65144216 ps
CPU time 3.36 seconds
Started Mar 21 03:25:29 PM PDT 24
Finished Mar 21 03:25:33 PM PDT 24
Peak memory 209284 kb
Host smart-4182aac6-a6bc-4256-9d2b-795f453cbfcf
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=785239626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.785239626
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.1324364303
Short name T477
Test name
Test status
Simulation time 59120882 ps
CPU time 3.36 seconds
Started Mar 21 03:25:19 PM PDT 24
Finished Mar 21 03:25:23 PM PDT 24
Peak memory 207344 kb
Host smart-2d1c9115-bceb-467b-9d1c-106bf947f3e0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1324364303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.1324364303
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.527948505
Short name T487
Test name
Test status
Simulation time 266511934 ps
CPU time 7.95 seconds
Started Mar 21 03:25:34 PM PDT 24
Finished Mar 21 03:25:42 PM PDT 24
Peak memory 209136 kb
Host smart-3d7ceb61-9f26-43c4-9473-36cff35ea76c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=527948505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.527948505
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.2028172329
Short name T82
Test name
Test status
Simulation time 139302547 ps
CPU time 2.85 seconds
Started Mar 21 03:25:36 PM PDT 24
Finished Mar 21 03:25:39 PM PDT 24
Peak memory 209388 kb
Host smart-61d15dcf-e8ad-45f7-ae7e-f9fd274a9215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2028172329 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.2028172329
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.112425036
Short name T634
Test name
Test status
Simulation time 33791751 ps
CPU time 2.43 seconds
Started Mar 21 03:25:19 PM PDT 24
Finished Mar 21 03:25:22 PM PDT 24
Peak memory 207248 kb
Host smart-d4ac0459-199a-48c8-9d3c-e3c1f2a91879
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=112425036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.112425036
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.72728742
Short name T898
Test name
Test status
Simulation time 5842601160 ps
CPU time 60.82 seconds
Started Mar 21 03:25:32 PM PDT 24
Finished Mar 21 03:26:33 PM PDT 24
Peak memory 215640 kb
Host smart-1e46101e-5415-4e36-8663-380535061567
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72728742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.72728742
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.3842852979
Short name T732
Test name
Test status
Simulation time 284093097 ps
CPU time 7.79 seconds
Started Mar 21 03:25:33 PM PDT 24
Finished Mar 21 03:25:41 PM PDT 24
Peak memory 209632 kb
Host smart-c33c1483-f71e-4f9f-ac55-46dba3d4dc57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3842852979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.3842852979
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.3464704184
Short name T56
Test name
Test status
Simulation time 1716606967 ps
CPU time 9.81 seconds
Started Mar 21 03:25:36 PM PDT 24
Finished Mar 21 03:25:46 PM PDT 24
Peak memory 211168 kb
Host smart-07d661e6-b1c7-47e3-ba5f-5a3495baeda4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3464704184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.3464704184
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.448682888
Short name T834
Test name
Test status
Simulation time 48177024 ps
CPU time 0.76 seconds
Started Mar 21 03:25:34 PM PDT 24
Finished Mar 21 03:25:35 PM PDT 24
Peak memory 206404 kb
Host smart-22e2a0e9-8091-47d5-9e89-98da15f53e14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448682888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.448682888
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.2595914245
Short name T66
Test name
Test status
Simulation time 76078683 ps
CPU time 2.69 seconds
Started Mar 21 03:25:35 PM PDT 24
Finished Mar 21 03:25:38 PM PDT 24
Peak memory 214812 kb
Host smart-37ba39bb-905e-4b77-ad40-91b9d4a5bb48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2595914245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.2595914245
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.1176291990
Short name T598
Test name
Test status
Simulation time 280301655 ps
CPU time 7.47 seconds
Started Mar 21 03:25:37 PM PDT 24
Finished Mar 21 03:25:45 PM PDT 24
Peak memory 209184 kb
Host smart-26d99b8e-c124-4c44-826c-4336e725ee96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176291990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.1176291990
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.547090620
Short name T636
Test name
Test status
Simulation time 47031321 ps
CPU time 2.51 seconds
Started Mar 21 03:25:34 PM PDT 24
Finished Mar 21 03:25:36 PM PDT 24
Peak memory 220496 kb
Host smart-a992144c-5fc7-4dcd-b7be-fe090a4d05e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=547090620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.547090620
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.1903648726
Short name T383
Test name
Test status
Simulation time 866161201 ps
CPU time 21.84 seconds
Started Mar 21 03:25:35 PM PDT 24
Finished Mar 21 03:25:58 PM PDT 24
Peak memory 210292 kb
Host smart-7ece7f0a-b7fb-467f-bef4-534193b95a9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903648726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.1903648726
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.91512545
Short name T277
Test name
Test status
Simulation time 651400687 ps
CPU time 22.41 seconds
Started Mar 21 03:25:33 PM PDT 24
Finished Mar 21 03:25:55 PM PDT 24
Peak memory 208448 kb
Host smart-0ee5debb-7756-4d1c-b33f-4f62d393571e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91512545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.91512545
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.3495029852
Short name T612
Test name
Test status
Simulation time 218682802 ps
CPU time 3.52 seconds
Started Mar 21 03:25:35 PM PDT 24
Finished Mar 21 03:25:39 PM PDT 24
Peak memory 208052 kb
Host smart-9f5ef03a-4df9-42ef-b014-2d2f8101c86c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495029852 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.3495029852
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.3697797273
Short name T628
Test name
Test status
Simulation time 1359448126 ps
CPU time 10.55 seconds
Started Mar 21 03:25:35 PM PDT 24
Finished Mar 21 03:25:46 PM PDT 24
Peak memory 209172 kb
Host smart-86e8017c-ec70-424c-aa66-8ba066620d95
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3697797273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.3697797273
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.1549033335
Short name T639
Test name
Test status
Simulation time 310178590 ps
CPU time 7.87 seconds
Started Mar 21 03:25:35 PM PDT 24
Finished Mar 21 03:25:43 PM PDT 24
Peak memory 208284 kb
Host smart-4c908b6a-8075-432f-b93a-868bbebd6089
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1549033335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.1549033335
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.1812921681
Short name T715
Test name
Test status
Simulation time 310955691 ps
CPU time 5.03 seconds
Started Mar 21 03:25:37 PM PDT 24
Finished Mar 21 03:25:43 PM PDT 24
Peak memory 208808 kb
Host smart-379dfe59-461f-41c8-831f-b1c721941502
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812921681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.1812921681
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.2886170102
Short name T538
Test name
Test status
Simulation time 719799985 ps
CPU time 22.32 seconds
Started Mar 21 03:25:35 PM PDT 24
Finished Mar 21 03:25:59 PM PDT 24
Peak memory 208868 kb
Host smart-883b439e-a05e-424b-a3cd-9825deea07ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886170102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.2886170102
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all_with_rand_reset.3529143430
Short name T746
Test name
Test status
Simulation time 328789442 ps
CPU time 21.08 seconds
Started Mar 21 03:25:37 PM PDT 24
Finished Mar 21 03:25:58 PM PDT 24
Peak memory 223064 kb
Host smart-7408f68e-87be-4acb-a3f3-aafdab985017
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529143430 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all_with_rand_reset.3529143430
Directory /workspace/26.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.2532307685
Short name T814
Test name
Test status
Simulation time 7128077298 ps
CPU time 12.67 seconds
Started Mar 21 03:25:35 PM PDT 24
Finished Mar 21 03:25:48 PM PDT 24
Peak memory 209360 kb
Host smart-e15f17fa-61da-43ff-bcab-64786574a53c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532307685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.2532307685
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.587140542
Short name T806
Test name
Test status
Simulation time 31741205 ps
CPU time 1.91 seconds
Started Mar 21 03:25:32 PM PDT 24
Finished Mar 21 03:25:34 PM PDT 24
Peak memory 210484 kb
Host smart-34e2e686-0867-412c-a999-39d7c8159e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=587140542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.587140542
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.1562209185
Short name T473
Test name
Test status
Simulation time 37330428 ps
CPU time 0.75 seconds
Started Mar 21 03:25:35 PM PDT 24
Finished Mar 21 03:25:36 PM PDT 24
Peak memory 206456 kb
Host smart-092a4173-4b23-43df-9c4f-41fe69ff6efb
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1562209185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.1562209185
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.195881582
Short name T782
Test name
Test status
Simulation time 122868880 ps
CPU time 4.72 seconds
Started Mar 21 03:25:37 PM PDT 24
Finished Mar 21 03:25:42 PM PDT 24
Peak memory 210348 kb
Host smart-26606f9b-3e84-4e74-b1dd-8ff5a6c0fa51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195881582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.195881582
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.3790102616
Short name T791
Test name
Test status
Simulation time 88505765 ps
CPU time 1.95 seconds
Started Mar 21 03:25:36 PM PDT 24
Finished Mar 21 03:25:38 PM PDT 24
Peak memory 218680 kb
Host smart-c918c1a4-f028-4332-9953-93a64b3a956c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3790102616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.3790102616
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.197187718
Short name T737
Test name
Test status
Simulation time 250783098 ps
CPU time 3.67 seconds
Started Mar 21 03:25:37 PM PDT 24
Finished Mar 21 03:25:41 PM PDT 24
Peak memory 217976 kb
Host smart-b3b45bfa-403d-4d49-bd73-c13f35d79c44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=197187718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.197187718
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.939864039
Short name T351
Test name
Test status
Simulation time 201759943 ps
CPU time 5.09 seconds
Started Mar 21 03:25:35 PM PDT 24
Finished Mar 21 03:25:41 PM PDT 24
Peak memory 214756 kb
Host smart-37cafbe2-f61c-4093-a2a6-127530a2289c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939864039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.939864039
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.2299759789
Short name T456
Test name
Test status
Simulation time 131517017 ps
CPU time 3.91 seconds
Started Mar 21 03:25:35 PM PDT 24
Finished Mar 21 03:25:39 PM PDT 24
Peak memory 218904 kb
Host smart-367767c8-4443-479d-a01b-c29233de1af9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2299759789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.2299759789
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.2420541824
Short name T221
Test name
Test status
Simulation time 215145124 ps
CPU time 3.81 seconds
Started Mar 21 03:25:37 PM PDT 24
Finished Mar 21 03:25:41 PM PDT 24
Peak memory 219012 kb
Host smart-5facde68-2725-4649-b95f-93d3981e83a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2420541824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.2420541824
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.101927636
Short name T522
Test name
Test status
Simulation time 303310664 ps
CPU time 8.03 seconds
Started Mar 21 03:25:31 PM PDT 24
Finished Mar 21 03:25:40 PM PDT 24
Peak memory 208572 kb
Host smart-a667e9fd-73cd-41fb-b307-6ccb72a051eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=101927636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.101927636
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.2118447370
Short name T357
Test name
Test status
Simulation time 111007238 ps
CPU time 2.66 seconds
Started Mar 21 03:25:37 PM PDT 24
Finished Mar 21 03:25:40 PM PDT 24
Peak memory 208880 kb
Host smart-525622da-98b1-4876-a5af-69f08f2015c9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2118447370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.2118447370
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.1977784381
Short name T666
Test name
Test status
Simulation time 69372970 ps
CPU time 2.55 seconds
Started Mar 21 03:25:41 PM PDT 24
Finished Mar 21 03:25:44 PM PDT 24
Peak memory 207868 kb
Host smart-4ed06097-1e78-48c1-8a17-bf26cc8e2060
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1977784381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.1977784381
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.1821922683
Short name T680
Test name
Test status
Simulation time 21288178 ps
CPU time 1.83 seconds
Started Mar 21 03:25:35 PM PDT 24
Finished Mar 21 03:25:37 PM PDT 24
Peak memory 207184 kb
Host smart-d0be694d-97bb-4e6f-a07a-a7d98b9e8471
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1821922683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.1821922683
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.1277933024
Short name T561
Test name
Test status
Simulation time 1376271999 ps
CPU time 6.9 seconds
Started Mar 21 03:25:34 PM PDT 24
Finished Mar 21 03:25:41 PM PDT 24
Peak memory 218976 kb
Host smart-86d6d422-37fd-4405-8868-6fab8dd5a278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277933024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.1277933024
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.1327308124
Short name T610
Test name
Test status
Simulation time 326866315 ps
CPU time 3.23 seconds
Started Mar 21 03:25:36 PM PDT 24
Finished Mar 21 03:25:40 PM PDT 24
Peak memory 207304 kb
Host smart-8b6442bd-b85c-4d74-b659-ebd23fe1e386
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1327308124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.1327308124
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.55394472
Short name T257
Test name
Test status
Simulation time 303464114 ps
CPU time 7.87 seconds
Started Mar 21 03:25:35 PM PDT 24
Finished Mar 21 03:25:44 PM PDT 24
Peak memory 214780 kb
Host smart-30a3c825-3901-4ba1-945f-253c3e2447e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55394472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.55394472
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.617529140
Short name T189
Test name
Test status
Simulation time 153980384 ps
CPU time 5.66 seconds
Started Mar 21 03:25:34 PM PDT 24
Finished Mar 21 03:25:40 PM PDT 24
Peak memory 210336 kb
Host smart-e7d89dd3-92cf-448a-b5e3-85849cf92ae0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=617529140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.617529140
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.1387712476
Short name T630
Test name
Test status
Simulation time 45847541 ps
CPU time 2.29 seconds
Started Mar 21 03:25:37 PM PDT 24
Finished Mar 21 03:25:40 PM PDT 24
Peak memory 210612 kb
Host smart-1d6c291f-5bd9-4c2d-8714-b3872d1af291
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387712476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.1387712476
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.473862509
Short name T568
Test name
Test status
Simulation time 30338547 ps
CPU time 0.81 seconds
Started Mar 21 03:25:53 PM PDT 24
Finished Mar 21 03:25:54 PM PDT 24
Peak memory 206440 kb
Host smart-0356278d-7b63-41bd-968e-8cefed8fd912
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=473862509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.473862509
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.769145317
Short name T361
Test name
Test status
Simulation time 35326783 ps
CPU time 2.76 seconds
Started Mar 21 03:25:33 PM PDT 24
Finished Mar 21 03:25:36 PM PDT 24
Peak memory 214752 kb
Host smart-3fe7ff2c-1a98-4715-80f8-56be7919118b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=769145317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.769145317
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.3957175658
Short name T33
Test name
Test status
Simulation time 44687359 ps
CPU time 2.33 seconds
Started Mar 21 03:25:49 PM PDT 24
Finished Mar 21 03:25:52 PM PDT 24
Peak memory 209048 kb
Host smart-f66e03be-1bda-4b56-a9e4-95ef5c846c4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3957175658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.3957175658
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.3786369373
Short name T652
Test name
Test status
Simulation time 126092211 ps
CPU time 2.51 seconds
Started Mar 21 03:25:48 PM PDT 24
Finished Mar 21 03:25:52 PM PDT 24
Peak memory 207744 kb
Host smart-74d0f2b4-97d0-4869-8bdf-3cf28984a52e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3786369373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.3786369373
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.3263208282
Short name T744
Test name
Test status
Simulation time 105150122 ps
CPU time 5.07 seconds
Started Mar 21 03:25:48 PM PDT 24
Finished Mar 21 03:25:54 PM PDT 24
Peak memory 214804 kb
Host smart-a24ca635-42c5-49a2-bd1e-4dc30a7be2dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3263208282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.3263208282
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.2389154270
Short name T719
Test name
Test status
Simulation time 1317259806 ps
CPU time 40.92 seconds
Started Mar 21 03:25:51 PM PDT 24
Finished Mar 21 03:26:32 PM PDT 24
Peak memory 222596 kb
Host smart-9bf09df6-ff70-49c1-84be-5c65b00a7859
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389154270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.2389154270
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_random.1199292573
Short name T580
Test name
Test status
Simulation time 99476752 ps
CPU time 3.41 seconds
Started Mar 21 03:25:36 PM PDT 24
Finished Mar 21 03:25:40 PM PDT 24
Peak memory 209864 kb
Host smart-d5bad02b-5b13-4f94-8c65-bb1375b2036c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199292573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.1199292573
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.2874790919
Short name T698
Test name
Test status
Simulation time 85894950 ps
CPU time 3.85 seconds
Started Mar 21 03:25:36 PM PDT 24
Finished Mar 21 03:25:40 PM PDT 24
Peak memory 208984 kb
Host smart-c01424a9-4787-4017-bc06-999e4af32b32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2874790919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.2874790919
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.424512614
Short name T536
Test name
Test status
Simulation time 1022772924 ps
CPU time 13.02 seconds
Started Mar 21 03:25:34 PM PDT 24
Finished Mar 21 03:25:48 PM PDT 24
Peak memory 208764 kb
Host smart-e71c5f1c-e047-4bac-9f36-7655187677ff
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424512614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.424512614
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.277373192
Short name T495
Test name
Test status
Simulation time 213688236 ps
CPU time 2.96 seconds
Started Mar 21 03:25:35 PM PDT 24
Finished Mar 21 03:25:38 PM PDT 24
Peak memory 207368 kb
Host smart-c4e8daec-2a72-43fc-8c03-e486b87ce19f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=277373192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.277373192
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.3218344307
Short name T389
Test name
Test status
Simulation time 180128095 ps
CPU time 2.69 seconds
Started Mar 21 03:25:47 PM PDT 24
Finished Mar 21 03:25:50 PM PDT 24
Peak memory 210068 kb
Host smart-c596fc74-00ca-47e2-a58d-be0d2881971c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3218344307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.3218344307
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.3348660798
Short name T648
Test name
Test status
Simulation time 232687027 ps
CPU time 5.5 seconds
Started Mar 21 03:25:35 PM PDT 24
Finished Mar 21 03:25:41 PM PDT 24
Peak memory 207240 kb
Host smart-3172a2a7-a17c-4efe-af23-ce4a3e35d8c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348660798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.3348660798
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.2864491790
Short name T858
Test name
Test status
Simulation time 9053340655 ps
CPU time 190.11 seconds
Started Mar 21 03:25:51 PM PDT 24
Finished Mar 21 03:29:01 PM PDT 24
Peak memory 217108 kb
Host smart-6b8a966b-2baa-490a-b3c8-5d86d8639197
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2864491790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.2864491790
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.3223346220
Short name T187
Test name
Test status
Simulation time 596578400 ps
CPU time 19.6 seconds
Started Mar 21 03:25:49 PM PDT 24
Finished Mar 21 03:26:09 PM PDT 24
Peak memory 214840 kb
Host smart-d9f141fb-6393-4ee4-93e6-a11dac679478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3223346220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.3223346220
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.2497748925
Short name T479
Test name
Test status
Simulation time 44952256 ps
CPU time 1.77 seconds
Started Mar 21 03:25:48 PM PDT 24
Finished Mar 21 03:25:50 PM PDT 24
Peak memory 210492 kb
Host smart-a4cd4946-e8a5-4c5b-84e6-ca1807b23860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2497748925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.2497748925
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.1049547701
Short name T622
Test name
Test status
Simulation time 48103672 ps
CPU time 0.89 seconds
Started Mar 21 03:25:50 PM PDT 24
Finished Mar 21 03:25:51 PM PDT 24
Peak memory 206496 kb
Host smart-0f494f9c-3da9-4f07-b7ca-ae0d8f6b56b4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049547701 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.1049547701
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.3869068975
Short name T21
Test name
Test status
Simulation time 49196889 ps
CPU time 1.84 seconds
Started Mar 21 03:25:46 PM PDT 24
Finished Mar 21 03:25:49 PM PDT 24
Peak memory 223384 kb
Host smart-b4633313-8258-4fbe-9cc4-4c35295f8391
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869068975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.3869068975
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.1115550869
Short name T543
Test name
Test status
Simulation time 148538217 ps
CPU time 2.4 seconds
Started Mar 21 03:25:51 PM PDT 24
Finished Mar 21 03:25:54 PM PDT 24
Peak memory 209044 kb
Host smart-0d1ab1e3-aece-4259-9c5b-2d848f5ddb6b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115550869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.1115550869
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.1860043504
Short name T521
Test name
Test status
Simulation time 82111743 ps
CPU time 2.48 seconds
Started Mar 21 03:25:48 PM PDT 24
Finished Mar 21 03:25:51 PM PDT 24
Peak memory 220184 kb
Host smart-92018bec-c6c8-49af-a31f-4ca1768119bd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860043504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.1860043504
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.550319469
Short name T608
Test name
Test status
Simulation time 1544864805 ps
CPU time 6.28 seconds
Started Mar 21 03:25:47 PM PDT 24
Finished Mar 21 03:25:54 PM PDT 24
Peak memory 214848 kb
Host smart-f2f99f28-4310-43fd-a686-ecf7fb7cf444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550319469 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.550319469
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.1210892773
Short name T589
Test name
Test status
Simulation time 1132492476 ps
CPU time 7.97 seconds
Started Mar 21 03:25:47 PM PDT 24
Finished Mar 21 03:25:55 PM PDT 24
Peak memory 209168 kb
Host smart-4d78604e-bf98-44ad-8c53-1e6c988640f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1210892773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.1210892773
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.2137904913
Short name T430
Test name
Test status
Simulation time 1617830102 ps
CPU time 37.4 seconds
Started Mar 21 03:25:48 PM PDT 24
Finished Mar 21 03:26:26 PM PDT 24
Peak memory 208380 kb
Host smart-123506a5-0842-448a-9151-2d56047a207d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2137904913 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.2137904913
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.576573734
Short name T191
Test name
Test status
Simulation time 539927604 ps
CPU time 4.52 seconds
Started Mar 21 03:25:51 PM PDT 24
Finished Mar 21 03:25:56 PM PDT 24
Peak memory 207972 kb
Host smart-72c9cffc-ff8c-4909-8587-1f99e4269952
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=576573734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.576573734
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.612535262
Short name T452
Test name
Test status
Simulation time 213540745 ps
CPU time 2.55 seconds
Started Mar 21 03:25:48 PM PDT 24
Finished Mar 21 03:25:52 PM PDT 24
Peak memory 207356 kb
Host smart-fed73920-9fe5-49b8-bbe0-b5ce86fe9904
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612535262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.612535262
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.3459804338
Short name T718
Test name
Test status
Simulation time 190442342 ps
CPU time 3.47 seconds
Started Mar 21 03:25:48 PM PDT 24
Finished Mar 21 03:25:52 PM PDT 24
Peak memory 214848 kb
Host smart-e1f72c8d-4e14-4203-90d1-5047380b54cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459804338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.3459804338
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.2525729717
Short name T762
Test name
Test status
Simulation time 132513626 ps
CPU time 2.75 seconds
Started Mar 21 03:25:46 PM PDT 24
Finished Mar 21 03:25:50 PM PDT 24
Peak memory 207220 kb
Host smart-777eb018-798d-4ae3-858b-83c0c9075444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525729717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.2525729717
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.4155098610
Short name T502
Test name
Test status
Simulation time 159078936 ps
CPU time 8.39 seconds
Started Mar 21 03:25:50 PM PDT 24
Finished Mar 21 03:25:59 PM PDT 24
Peak memory 216100 kb
Host smart-0871d05a-b460-4a8f-a73d-990c447a43aa
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155098610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.4155098610
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.2671258267
Short name T226
Test name
Test status
Simulation time 2782369529 ps
CPU time 8.28 seconds
Started Mar 21 03:25:49 PM PDT 24
Finished Mar 21 03:25:58 PM PDT 24
Peak memory 209096 kb
Host smart-be83f3b7-34b8-4019-baaf-bb3579ddf09a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671258267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.2671258267
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.960302366
Short name T658
Test name
Test status
Simulation time 102319692 ps
CPU time 2.03 seconds
Started Mar 21 03:25:49 PM PDT 24
Finished Mar 21 03:25:52 PM PDT 24
Peak memory 210864 kb
Host smart-debaded0-04c2-4c3a-b60a-5623e743fa51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960302366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.960302366
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.1569553703
Short name T852
Test name
Test status
Simulation time 11296067 ps
CPU time 0.88 seconds
Started Mar 21 03:23:52 PM PDT 24
Finished Mar 21 03:23:53 PM PDT 24
Peak memory 206384 kb
Host smart-4d79b641-b670-4003-894e-25d65c8adf97
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1569553703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.1569553703
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.3085142689
Short name T236
Test name
Test status
Simulation time 32895102 ps
CPU time 2.69 seconds
Started Mar 21 03:23:46 PM PDT 24
Finished Mar 21 03:23:50 PM PDT 24
Peak memory 215236 kb
Host smart-907297b0-952a-4317-b490-5134c6850fae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3085142689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.3085142689
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.4069331615
Short name T548
Test name
Test status
Simulation time 219058305 ps
CPU time 3.48 seconds
Started Mar 21 03:23:44 PM PDT 24
Finished Mar 21 03:23:48 PM PDT 24
Peak memory 222256 kb
Host smart-fc713351-b110-4f75-ab6f-26504c640977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069331615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.4069331615
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.1115989061
Short name T669
Test name
Test status
Simulation time 450469848 ps
CPU time 2.22 seconds
Started Mar 21 03:23:44 PM PDT 24
Finished Mar 21 03:23:48 PM PDT 24
Peak memory 218796 kb
Host smart-fa4325e9-035f-4772-ad14-9b0822676f1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115989061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.1115989061
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.1534387415
Short name T510
Test name
Test status
Simulation time 330918010 ps
CPU time 8.89 seconds
Started Mar 21 03:23:44 PM PDT 24
Finished Mar 21 03:23:54 PM PDT 24
Peak memory 210068 kb
Host smart-bcc54460-01b4-4fa4-a3d0-024bc422e1d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534387415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.1534387415
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.945272761
Short name T582
Test name
Test status
Simulation time 315791498 ps
CPU time 5.08 seconds
Started Mar 21 03:23:44 PM PDT 24
Finished Mar 21 03:23:50 PM PDT 24
Peak memory 222916 kb
Host smart-bfeb9d92-f126-48a1-a38e-727af4bd4e31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945272761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.945272761
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.2926645396
Short name T49
Test name
Test status
Simulation time 96521530 ps
CPU time 3.29 seconds
Started Mar 21 03:23:42 PM PDT 24
Finished Mar 21 03:23:46 PM PDT 24
Peak memory 222992 kb
Host smart-1fb116f3-6690-4deb-8d0d-76a965799440
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926645396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.2926645396
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.3862166723
Short name T851
Test name
Test status
Simulation time 817546769 ps
CPU time 8.18 seconds
Started Mar 21 03:23:44 PM PDT 24
Finished Mar 21 03:23:53 PM PDT 24
Peak memory 208560 kb
Host smart-88b81f75-078b-40dd-9144-cf0d176e0746
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3862166723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.3862166723
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.3783833497
Short name T12
Test name
Test status
Simulation time 1652074268 ps
CPU time 32.43 seconds
Started Mar 21 03:23:53 PM PDT 24
Finished Mar 21 03:24:26 PM PDT 24
Peak memory 237628 kb
Host smart-cec64c0b-8a4d-4bde-8e40-cba4ebfecf52
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3783833497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.3783833497
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sideload.2739154990
Short name T798
Test name
Test status
Simulation time 79760303 ps
CPU time 3.32 seconds
Started Mar 21 03:23:44 PM PDT 24
Finished Mar 21 03:23:49 PM PDT 24
Peak memory 209060 kb
Host smart-a3551067-328f-4782-a737-9902f16b1420
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2739154990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.2739154990
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.1692232893
Short name T13
Test name
Test status
Simulation time 4062962213 ps
CPU time 24.51 seconds
Started Mar 21 03:23:44 PM PDT 24
Finished Mar 21 03:24:09 PM PDT 24
Peak memory 208464 kb
Host smart-16442423-25e5-43b1-ac9c-85d3eb6f11d6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1692232893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.1692232893
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.1899398641
Short name T321
Test name
Test status
Simulation time 115086689 ps
CPU time 2.85 seconds
Started Mar 21 03:23:42 PM PDT 24
Finished Mar 21 03:23:46 PM PDT 24
Peak memory 208656 kb
Host smart-5988b0f3-1856-48bb-8977-00ba05f78e72
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1899398641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.1899398641
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.2265061099
Short name T505
Test name
Test status
Simulation time 73524973 ps
CPU time 3.35 seconds
Started Mar 21 03:23:44 PM PDT 24
Finished Mar 21 03:23:49 PM PDT 24
Peak memory 208892 kb
Host smart-33faa56b-25c3-4084-92ba-788a3aface55
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2265061099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.2265061099
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.1420988733
Short name T464
Test name
Test status
Simulation time 605861028 ps
CPU time 17.5 seconds
Started Mar 21 03:23:46 PM PDT 24
Finished Mar 21 03:24:04 PM PDT 24
Peak memory 217276 kb
Host smart-ce97d134-3938-40a6-99d4-63069f17967c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1420988733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.1420988733
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.3709557136
Short name T817
Test name
Test status
Simulation time 237480364 ps
CPU time 3.1 seconds
Started Mar 21 03:23:44 PM PDT 24
Finished Mar 21 03:23:48 PM PDT 24
Peak memory 208640 kb
Host smart-9ac8bd92-50b0-4935-9e0d-ff4de4d27aff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3709557136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.3709557136
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.3263535202
Short name T74
Test name
Test status
Simulation time 13462658308 ps
CPU time 82.12 seconds
Started Mar 21 03:23:41 PM PDT 24
Finished Mar 21 03:25:03 PM PDT 24
Peak memory 223128 kb
Host smart-3729cced-35af-4b9d-9bd6-d4d4ff0a2e08
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3263535202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.3263535202
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.2539013681
Short name T566
Test name
Test status
Simulation time 1459826243 ps
CPU time 10 seconds
Started Mar 21 03:23:48 PM PDT 24
Finished Mar 21 03:23:58 PM PDT 24
Peak memory 210724 kb
Host smart-c1c5b4dc-8ee6-47cb-a6e5-c1f2e0eab99a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539013681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.2539013681
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.4066131544
Short name T775
Test name
Test status
Simulation time 230186304 ps
CPU time 2.14 seconds
Started Mar 21 03:23:42 PM PDT 24
Finished Mar 21 03:23:45 PM PDT 24
Peak memory 210208 kb
Host smart-57a93db3-4690-4cef-9a83-a65188013f9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066131544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.4066131544
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.2655064110
Short name T850
Test name
Test status
Simulation time 41891185 ps
CPU time 1 seconds
Started Mar 21 03:25:52 PM PDT 24
Finished Mar 21 03:25:53 PM PDT 24
Peak memory 206640 kb
Host smart-5c0e1c73-73f4-4f4c-9920-a7f35dd49bba
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2655064110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.2655064110
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.1166184065
Short name T558
Test name
Test status
Simulation time 73970511 ps
CPU time 2.95 seconds
Started Mar 21 03:25:48 PM PDT 24
Finished Mar 21 03:25:52 PM PDT 24
Peak memory 220168 kb
Host smart-0a23c8f0-e108-41ce-9992-31e783a8d022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166184065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.1166184065
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.489977258
Short name T72
Test name
Test status
Simulation time 195241800 ps
CPU time 2.6 seconds
Started Mar 21 03:25:47 PM PDT 24
Finished Mar 21 03:25:50 PM PDT 24
Peak memory 208032 kb
Host smart-5f39ac27-81ed-4622-94b3-92246cb9b2b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=489977258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.489977258
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.1641382757
Short name T93
Test name
Test status
Simulation time 111768787 ps
CPU time 3.09 seconds
Started Mar 21 03:25:51 PM PDT 24
Finished Mar 21 03:25:55 PM PDT 24
Peak memory 209388 kb
Host smart-51cc1d08-b154-46b7-a72e-e04cb8da6327
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1641382757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.1641382757
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.4252602478
Short name T596
Test name
Test status
Simulation time 259084906 ps
CPU time 3.17 seconds
Started Mar 21 03:25:52 PM PDT 24
Finished Mar 21 03:25:55 PM PDT 24
Peak memory 222892 kb
Host smart-4c2d559a-a93f-4c6c-aa88-15e79044ab7f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4252602478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.4252602478
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.10328964
Short name T276
Test name
Test status
Simulation time 35223226 ps
CPU time 2.54 seconds
Started Mar 21 03:25:51 PM PDT 24
Finished Mar 21 03:25:54 PM PDT 24
Peak memory 208384 kb
Host smart-cdfb226a-2861-4b24-83d8-6887a73c8b9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10328964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.10328964
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.3821305155
Short name T805
Test name
Test status
Simulation time 38476311 ps
CPU time 2.78 seconds
Started Mar 21 03:25:53 PM PDT 24
Finished Mar 21 03:25:55 PM PDT 24
Peak memory 209016 kb
Host smart-943e68ca-d4a2-42f0-be87-a8c3ac3f62e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821305155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.3821305155
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.648596728
Short name T432
Test name
Test status
Simulation time 7939388062 ps
CPU time 84.21 seconds
Started Mar 21 03:25:49 PM PDT 24
Finished Mar 21 03:27:14 PM PDT 24
Peak memory 209284 kb
Host smart-0a8bd348-1f64-4233-9ae4-08633831dfb6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648596728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.648596728
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.328883354
Short name T259
Test name
Test status
Simulation time 225447510 ps
CPU time 3.92 seconds
Started Mar 21 03:25:46 PM PDT 24
Finished Mar 21 03:25:50 PM PDT 24
Peak memory 208872 kb
Host smart-2df5a2ef-325a-481b-ac11-7953b2cf1630
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=328883354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.328883354
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.588720150
Short name T489
Test name
Test status
Simulation time 1033147179 ps
CPU time 19.62 seconds
Started Mar 21 03:25:48 PM PDT 24
Finished Mar 21 03:26:08 PM PDT 24
Peak memory 209300 kb
Host smart-384dafd6-4bd7-42e9-b91b-d227098a71b8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588720150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.588720150
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.3559466224
Short name T594
Test name
Test status
Simulation time 73743169 ps
CPU time 3.23 seconds
Started Mar 21 03:25:52 PM PDT 24
Finished Mar 21 03:25:55 PM PDT 24
Peak memory 210740 kb
Host smart-ff368986-c42a-43f1-9edc-8106f53eb064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559466224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.3559466224
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.1757148233
Short name T753
Test name
Test status
Simulation time 915704745 ps
CPU time 6.11 seconds
Started Mar 21 03:25:47 PM PDT 24
Finished Mar 21 03:25:53 PM PDT 24
Peak memory 207044 kb
Host smart-8aeb95cc-eca5-49bd-a916-fb759b1fad2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1757148233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.1757148233
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.3892201061
Short name T272
Test name
Test status
Simulation time 968989960 ps
CPU time 33.51 seconds
Started Mar 21 03:25:51 PM PDT 24
Finished Mar 21 03:26:25 PM PDT 24
Peak memory 216524 kb
Host smart-93cea8a6-02de-4088-98a8-13dc6afe8e00
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3892201061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.3892201061
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_stress_all_with_rand_reset.4161877456
Short name T172
Test name
Test status
Simulation time 970778856 ps
CPU time 9.53 seconds
Started Mar 21 03:25:50 PM PDT 24
Finished Mar 21 03:26:00 PM PDT 24
Peak memory 220268 kb
Host smart-6bb5d19a-7bc8-43f1-89a5-4e58aa87b670
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4161877456 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all_with_rand_reset.4161877456
Directory /workspace/30.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.3536166684
Short name T789
Test name
Test status
Simulation time 97230556 ps
CPU time 3.22 seconds
Started Mar 21 03:25:52 PM PDT 24
Finished Mar 21 03:25:56 PM PDT 24
Peak memory 207708 kb
Host smart-1ac99ebb-b984-45b0-a417-62610d6e65aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3536166684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.3536166684
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.2017315090
Short name T560
Test name
Test status
Simulation time 83441047 ps
CPU time 3.05 seconds
Started Mar 21 03:25:49 PM PDT 24
Finished Mar 21 03:25:53 PM PDT 24
Peak memory 210332 kb
Host smart-36bf1065-c69f-4f34-a9be-a511b8b7a40a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2017315090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.2017315090
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.1312105079
Short name T494
Test name
Test status
Simulation time 21556636 ps
CPU time 0.75 seconds
Started Mar 21 03:25:52 PM PDT 24
Finished Mar 21 03:25:53 PM PDT 24
Peak memory 206388 kb
Host smart-7d7da49a-8bc7-4ed9-acd5-2f3da6936f52
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1312105079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.1312105079
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.3426460156
Short name T130
Test name
Test status
Simulation time 94047464 ps
CPU time 5.48 seconds
Started Mar 21 03:25:53 PM PDT 24
Finished Mar 21 03:25:58 PM PDT 24
Peak memory 215112 kb
Host smart-73b04fef-bb93-4431-8f44-d4502aad4b6c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3426460156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.3426460156
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.268012496
Short name T32
Test name
Test status
Simulation time 599723325 ps
CPU time 4.55 seconds
Started Mar 21 03:25:52 PM PDT 24
Finished Mar 21 03:25:57 PM PDT 24
Peak memory 219728 kb
Host smart-aed6086d-d1cb-4ce7-929f-8243681ea6ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268012496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.268012496
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.2461816608
Short name T251
Test name
Test status
Simulation time 77402235 ps
CPU time 3.87 seconds
Started Mar 21 03:25:47 PM PDT 24
Finished Mar 21 03:25:51 PM PDT 24
Peak memory 210284 kb
Host smart-2a8ed10e-e8ee-4479-96eb-a1eaa97fe9e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2461816608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.2461816608
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.3493921558
Short name T288
Test name
Test status
Simulation time 467350432 ps
CPU time 4.66 seconds
Started Mar 21 03:25:53 PM PDT 24
Finished Mar 21 03:25:57 PM PDT 24
Peak memory 214820 kb
Host smart-c519a1e9-f230-40d6-8eff-ad7ab85ef8d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493921558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.3493921558
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.1719819849
Short name T366
Test name
Test status
Simulation time 101584852 ps
CPU time 5.02 seconds
Started Mar 21 03:25:54 PM PDT 24
Finished Mar 21 03:26:00 PM PDT 24
Peak memory 214692 kb
Host smart-c0922af0-cafa-44ef-a18c-43828757b090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1719819849 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.1719819849
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.134113245
Short name T767
Test name
Test status
Simulation time 1152372466 ps
CPU time 9.24 seconds
Started Mar 21 03:25:54 PM PDT 24
Finished Mar 21 03:26:04 PM PDT 24
Peak memory 214812 kb
Host smart-dc35266b-e4e0-4b3f-a14b-7bed273ce861
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134113245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.134113245
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.439913234
Short name T691
Test name
Test status
Simulation time 1365789856 ps
CPU time 34.39 seconds
Started Mar 21 03:25:53 PM PDT 24
Finished Mar 21 03:26:28 PM PDT 24
Peak memory 209076 kb
Host smart-5f25bb95-88c6-4bf5-b98a-0e3078addca2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439913234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.439913234
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.1899896403
Short name T305
Test name
Test status
Simulation time 233576516 ps
CPU time 3.42 seconds
Started Mar 21 03:25:55 PM PDT 24
Finished Mar 21 03:25:59 PM PDT 24
Peak memory 208784 kb
Host smart-639e6341-ba24-418a-9de2-3d3289a55517
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1899896403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.1899896403
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.1520790749
Short name T457
Test name
Test status
Simulation time 663869413 ps
CPU time 6.53 seconds
Started Mar 21 03:25:53 PM PDT 24
Finished Mar 21 03:26:00 PM PDT 24
Peak memory 209000 kb
Host smart-7c5c865c-b68b-4964-ae24-70f60616d1d5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520790749 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.1520790749
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.1811226104
Short name T811
Test name
Test status
Simulation time 86759277 ps
CPU time 3.82 seconds
Started Mar 21 03:25:54 PM PDT 24
Finished Mar 21 03:25:58 PM PDT 24
Peak memory 209212 kb
Host smart-b52ff9ae-7d70-4ef0-b1c1-b28a5d890fa4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1811226104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.1811226104
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.2341621292
Short name T498
Test name
Test status
Simulation time 78446270 ps
CPU time 2.27 seconds
Started Mar 21 03:25:53 PM PDT 24
Finished Mar 21 03:25:55 PM PDT 24
Peak memory 207280 kb
Host smart-168bca52-b7c3-45a8-81d1-0a574d850045
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341621292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.2341621292
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.3222616607
Short name T421
Test name
Test status
Simulation time 45226885 ps
CPU time 2.43 seconds
Started Mar 21 03:25:53 PM PDT 24
Finished Mar 21 03:25:55 PM PDT 24
Peak memory 210120 kb
Host smart-bc4a2817-91bf-49fb-9456-e5d224f51c1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222616607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.3222616607
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.1866168250
Short name T728
Test name
Test status
Simulation time 197095121 ps
CPU time 3.98 seconds
Started Mar 21 03:25:52 PM PDT 24
Finished Mar 21 03:25:56 PM PDT 24
Peak memory 207280 kb
Host smart-2f80c347-9c71-4775-9cca-99cfc08423cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1866168250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.1866168250
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.2382135511
Short name T206
Test name
Test status
Simulation time 3332974701 ps
CPU time 26.95 seconds
Started Mar 21 03:25:58 PM PDT 24
Finished Mar 21 03:26:25 PM PDT 24
Peak memory 216896 kb
Host smart-5325496b-bd00-4923-a344-88fe848798ce
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2382135511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.2382135511
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.2218981404
Short name T626
Test name
Test status
Simulation time 167563678 ps
CPU time 5.95 seconds
Started Mar 21 03:25:53 PM PDT 24
Finished Mar 21 03:25:59 PM PDT 24
Peak memory 208324 kb
Host smart-b42c3ad4-cef3-422a-ac21-14db8b42caca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218981404 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.2218981404
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.1644279578
Short name T445
Test name
Test status
Simulation time 102678388 ps
CPU time 1.71 seconds
Started Mar 21 03:25:52 PM PDT 24
Finished Mar 21 03:25:54 PM PDT 24
Peak memory 210200 kb
Host smart-b71d1981-c023-4720-87fe-ac30da7a0064
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644279578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.1644279578
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.3126037571
Short name T95
Test name
Test status
Simulation time 12639854 ps
CPU time 0.83 seconds
Started Mar 21 03:25:52 PM PDT 24
Finished Mar 21 03:25:53 PM PDT 24
Peak memory 206388 kb
Host smart-41338f03-7d19-4fcf-ab66-268204386988
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3126037571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.3126037571
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.3767097503
Short name T263
Test name
Test status
Simulation time 1316407184 ps
CPU time 11.45 seconds
Started Mar 21 03:25:54 PM PDT 24
Finished Mar 21 03:26:07 PM PDT 24
Peak memory 214816 kb
Host smart-309b0af9-4dd7-42b2-8d34-41daa6960c23
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3767097503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.3767097503
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.2895991277
Short name T885
Test name
Test status
Simulation time 55298944 ps
CPU time 2.45 seconds
Started Mar 21 03:25:55 PM PDT 24
Finished Mar 21 03:25:58 PM PDT 24
Peak memory 207744 kb
Host smart-199961a8-b231-4068-b1ca-43fa77fd0f07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2895991277 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.2895991277
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.1721113541
Short name T803
Test name
Test status
Simulation time 131246097 ps
CPU time 5.69 seconds
Started Mar 21 03:25:50 PM PDT 24
Finished Mar 21 03:25:56 PM PDT 24
Peak memory 220420 kb
Host smart-0752bc71-a6e5-4f8f-817b-8f3c559f43a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1721113541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.1721113541
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.1844611432
Short name T43
Test name
Test status
Simulation time 244007106 ps
CPU time 3.93 seconds
Started Mar 21 03:25:53 PM PDT 24
Finished Mar 21 03:25:57 PM PDT 24
Peak memory 220004 kb
Host smart-c0bf94cb-07fb-4d14-ac4c-f05cbc31a7e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1844611432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.1844611432
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.1729806639
Short name T346
Test name
Test status
Simulation time 60613809 ps
CPU time 3.16 seconds
Started Mar 21 03:25:58 PM PDT 24
Finished Mar 21 03:26:02 PM PDT 24
Peak memory 207560 kb
Host smart-ddccd1fc-59f5-4ad8-b40a-7d224db3140b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1729806639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.1729806639
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.3101721914
Short name T248
Test name
Test status
Simulation time 817161284 ps
CPU time 4.79 seconds
Started Mar 21 03:25:56 PM PDT 24
Finished Mar 21 03:26:01 PM PDT 24
Peak memory 209240 kb
Host smart-bc6ff34f-9758-4349-9c9f-4f02f05302b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3101721914 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.3101721914
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.4100003888
Short name T651
Test name
Test status
Simulation time 531884745 ps
CPU time 6.48 seconds
Started Mar 21 03:25:52 PM PDT 24
Finished Mar 21 03:25:59 PM PDT 24
Peak memory 207384 kb
Host smart-8d0e2cbd-2baf-4cfa-b7a1-49dcaad08ff7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4100003888 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.4100003888
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.1355634863
Short name T786
Test name
Test status
Simulation time 902454880 ps
CPU time 4.85 seconds
Started Mar 21 03:25:54 PM PDT 24
Finished Mar 21 03:26:00 PM PDT 24
Peak memory 207356 kb
Host smart-0455455a-addb-4b53-add6-04db7046dbb2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1355634863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.1355634863
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.1394862009
Short name T192
Test name
Test status
Simulation time 55301738 ps
CPU time 2.98 seconds
Started Mar 21 03:25:54 PM PDT 24
Finished Mar 21 03:25:58 PM PDT 24
Peak memory 209224 kb
Host smart-797be347-4cf1-45ea-9a69-54f18581afac
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394862009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.1394862009
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.3153080198
Short name T526
Test name
Test status
Simulation time 121196170 ps
CPU time 2.8 seconds
Started Mar 21 03:25:56 PM PDT 24
Finished Mar 21 03:26:00 PM PDT 24
Peak memory 214792 kb
Host smart-dc86689e-7a43-4a7c-9e48-3afb54284115
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3153080198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.3153080198
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.983216369
Short name T515
Test name
Test status
Simulation time 847187698 ps
CPU time 5.41 seconds
Started Mar 21 03:25:48 PM PDT 24
Finished Mar 21 03:25:54 PM PDT 24
Peak memory 208788 kb
Host smart-93301136-13b6-4608-b726-af2b50689ad8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983216369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.983216369
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.87803266
Short name T58
Test name
Test status
Simulation time 679664948 ps
CPU time 23.89 seconds
Started Mar 21 03:25:54 PM PDT 24
Finished Mar 21 03:26:19 PM PDT 24
Peak memory 222848 kb
Host smart-fb57f5b1-0b54-460a-9085-390079c110e4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87803266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.87803266
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.359453998
Short name T264
Test name
Test status
Simulation time 671186283 ps
CPU time 17.24 seconds
Started Mar 21 03:25:54 PM PDT 24
Finished Mar 21 03:26:12 PM PDT 24
Peak memory 208896 kb
Host smart-158d1d74-0ccd-4d73-ab5d-76e6f928f25d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359453998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.359453998
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.1105577540
Short name T374
Test name
Test status
Simulation time 98999908 ps
CPU time 1.7 seconds
Started Mar 21 03:25:55 PM PDT 24
Finished Mar 21 03:25:58 PM PDT 24
Peak memory 210308 kb
Host smart-a636831a-7b3e-49a4-a4af-7b65c58e3f77
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1105577540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.1105577540
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.2875163065
Short name T434
Test name
Test status
Simulation time 49581407 ps
CPU time 0.88 seconds
Started Mar 21 03:25:48 PM PDT 24
Finished Mar 21 03:25:49 PM PDT 24
Peak memory 206464 kb
Host smart-97ef52c8-5ccc-4dca-9ac1-15715eacae1b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2875163065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.2875163065
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.1010214988
Short name T407
Test name
Test status
Simulation time 575474826 ps
CPU time 30 seconds
Started Mar 21 03:25:52 PM PDT 24
Finished Mar 21 03:26:22 PM PDT 24
Peak memory 222908 kb
Host smart-1b757c11-54f2-464d-b295-caaf60d91938
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1010214988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.1010214988
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.2322585794
Short name T29
Test name
Test status
Simulation time 107017213 ps
CPU time 3.84 seconds
Started Mar 21 03:25:52 PM PDT 24
Finished Mar 21 03:25:56 PM PDT 24
Peak memory 215204 kb
Host smart-e2b6a8e9-7236-42d6-bb79-5b791a9ca090
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322585794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.2322585794
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.942926711
Short name T692
Test name
Test status
Simulation time 60518652 ps
CPU time 2.64 seconds
Started Mar 21 03:25:53 PM PDT 24
Finished Mar 21 03:25:55 PM PDT 24
Peak memory 208848 kb
Host smart-2c4562d8-8cb4-45fa-aea7-ac1a3882ebc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=942926711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.942926711
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.2056017930
Short name T308
Test name
Test status
Simulation time 142888084 ps
CPU time 3.69 seconds
Started Mar 21 03:25:53 PM PDT 24
Finished Mar 21 03:25:56 PM PDT 24
Peak memory 214736 kb
Host smart-5e7dbc71-a3f2-4521-b409-d8e151bb63ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056017930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.2056017930
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.2644124766
Short name T85
Test name
Test status
Simulation time 330532767 ps
CPU time 7.46 seconds
Started Mar 21 03:25:53 PM PDT 24
Finished Mar 21 03:26:00 PM PDT 24
Peak memory 214704 kb
Host smart-982c8e31-7051-4ea1-832f-18bb5bc2d2ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2644124766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.2644124766
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.307551915
Short name T207
Test name
Test status
Simulation time 290987436 ps
CPU time 4.1 seconds
Started Mar 21 03:25:53 PM PDT 24
Finished Mar 21 03:25:58 PM PDT 24
Peak memory 209688 kb
Host smart-a5fed341-bac5-488d-a224-d781713ea993
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307551915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.307551915
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.754328803
Short name T897
Test name
Test status
Simulation time 441179445 ps
CPU time 5.08 seconds
Started Mar 21 03:25:52 PM PDT 24
Finished Mar 21 03:25:57 PM PDT 24
Peak memory 214772 kb
Host smart-30412b3f-dcbd-41e9-9dfc-6e7fb9c371e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=754328803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.754328803
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.4257054039
Short name T600
Test name
Test status
Simulation time 1330368632 ps
CPU time 4.51 seconds
Started Mar 21 03:25:51 PM PDT 24
Finished Mar 21 03:25:56 PM PDT 24
Peak memory 208892 kb
Host smart-76ff2b1d-eb33-466a-bc6d-ef658e80abc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4257054039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.4257054039
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.1454822986
Short name T645
Test name
Test status
Simulation time 25445433 ps
CPU time 2.11 seconds
Started Mar 21 03:25:51 PM PDT 24
Finished Mar 21 03:25:53 PM PDT 24
Peak memory 208996 kb
Host smart-da771f43-d5f3-4ce8-ac9c-ed64bbac467f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1454822986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.1454822986
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.736061409
Short name T819
Test name
Test status
Simulation time 226330979 ps
CPU time 7.04 seconds
Started Mar 21 03:25:54 PM PDT 24
Finished Mar 21 03:26:02 PM PDT 24
Peak memory 209040 kb
Host smart-e24c64dc-a6ae-4066-8ff1-df6d5db64049
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=736061409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.736061409
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.172516534
Short name T901
Test name
Test status
Simulation time 2268293124 ps
CPU time 11.7 seconds
Started Mar 21 03:25:52 PM PDT 24
Finished Mar 21 03:26:03 PM PDT 24
Peak memory 207584 kb
Host smart-4b8fcd11-2630-408b-9202-1b3caa6bf26f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172516534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.172516534
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.2347365415
Short name T467
Test name
Test status
Simulation time 65621900 ps
CPU time 1.65 seconds
Started Mar 21 03:25:53 PM PDT 24
Finished Mar 21 03:25:55 PM PDT 24
Peak memory 207352 kb
Host smart-3791ab01-6572-4e7c-8cfb-d3e3f74aa62b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2347365415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.2347365415
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.2575720415
Short name T889
Test name
Test status
Simulation time 126758422 ps
CPU time 2.28 seconds
Started Mar 21 03:25:52 PM PDT 24
Finished Mar 21 03:25:54 PM PDT 24
Peak memory 207180 kb
Host smart-a4295e0b-4ce9-471a-82c5-bc081574d3c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2575720415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.2575720415
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all_with_rand_reset.555054920
Short name T642
Test name
Test status
Simulation time 1089452569 ps
CPU time 14.02 seconds
Started Mar 21 03:25:52 PM PDT 24
Finished Mar 21 03:26:06 PM PDT 24
Peak memory 223148 kb
Host smart-54ccac80-c101-4f19-b181-5d78acb0c4c6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=555054920 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all_with_rand_reset.555054920
Directory /workspace/33.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.439186145
Short name T884
Test name
Test status
Simulation time 221569814 ps
CPU time 5.61 seconds
Started Mar 21 03:25:51 PM PDT 24
Finished Mar 21 03:25:57 PM PDT 24
Peak memory 208528 kb
Host smart-bfe9acec-59d3-415e-a466-b98a115ffde1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=439186145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.439186145
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.53237006
Short name T847
Test name
Test status
Simulation time 37344267 ps
CPU time 1.99 seconds
Started Mar 21 03:25:53 PM PDT 24
Finished Mar 21 03:25:55 PM PDT 24
Peak memory 210936 kb
Host smart-2c8f0c6f-6b30-4709-baea-1e64b930fdd5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53237006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.53237006
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.4042514235
Short name T562
Test name
Test status
Simulation time 21355254 ps
CPU time 1.02 seconds
Started Mar 21 03:25:51 PM PDT 24
Finished Mar 21 03:25:52 PM PDT 24
Peak memory 206600 kb
Host smart-d4123408-0315-4cb6-9c32-78adf8b441dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4042514235 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.4042514235
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.3585737004
Short name T471
Test name
Test status
Simulation time 344159538 ps
CPU time 10.32 seconds
Started Mar 21 03:25:49 PM PDT 24
Finished Mar 21 03:26:00 PM PDT 24
Peak memory 221748 kb
Host smart-fdc498c3-0abc-401c-95ee-719784c57236
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585737004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.3585737004
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.651984802
Short name T481
Test name
Test status
Simulation time 104305058 ps
CPU time 2.96 seconds
Started Mar 21 03:25:46 PM PDT 24
Finished Mar 21 03:25:49 PM PDT 24
Peak memory 208852 kb
Host smart-3a96b84e-94c0-4b95-89af-f2cc0863a8b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651984802 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.651984802
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.1325976733
Short name T88
Test name
Test status
Simulation time 71945943 ps
CPU time 4.16 seconds
Started Mar 21 03:25:54 PM PDT 24
Finished Mar 21 03:25:58 PM PDT 24
Peak memory 209944 kb
Host smart-f7b4fc26-6c66-435c-bd5f-78604f3fff17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325976733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.1325976733
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.1830312171
Short name T365
Test name
Test status
Simulation time 184686252 ps
CPU time 6.71 seconds
Started Mar 21 03:25:50 PM PDT 24
Finished Mar 21 03:25:57 PM PDT 24
Peak memory 214804 kb
Host smart-ff2bd663-f39d-4cd2-91e6-87198e987889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1830312171 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.1830312171
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.2162156355
Short name T205
Test name
Test status
Simulation time 42127083 ps
CPU time 2.87 seconds
Started Mar 21 03:25:49 PM PDT 24
Finished Mar 21 03:25:52 PM PDT 24
Peak memory 214872 kb
Host smart-308b4cb8-1fe4-4237-a72d-012dc010e5a4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162156355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.2162156355
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.1828155566
Short name T268
Test name
Test status
Simulation time 217714310 ps
CPU time 3.06 seconds
Started Mar 21 03:25:50 PM PDT 24
Finished Mar 21 03:25:53 PM PDT 24
Peak memory 207496 kb
Host smart-d897521e-92cb-40dc-ba47-70e4ab151cb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828155566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.1828155566
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.3689154759
Short name T419
Test name
Test status
Simulation time 305272096 ps
CPU time 3.11 seconds
Started Mar 21 03:25:49 PM PDT 24
Finished Mar 21 03:25:53 PM PDT 24
Peak memory 207072 kb
Host smart-83b60258-b435-419e-a2e8-49bb00a5ac90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3689154759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.3689154759
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.1391115123
Short name T14
Test name
Test status
Simulation time 309580953 ps
CPU time 5.06 seconds
Started Mar 21 03:25:50 PM PDT 24
Finished Mar 21 03:25:55 PM PDT 24
Peak memory 208148 kb
Host smart-317e9b22-a6f8-4f46-9da5-985734532686
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391115123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.1391115123
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.3869823609
Short name T294
Test name
Test status
Simulation time 204788517 ps
CPU time 3.45 seconds
Started Mar 21 03:25:51 PM PDT 24
Finished Mar 21 03:25:55 PM PDT 24
Peak memory 207660 kb
Host smart-566d9513-2eb7-499d-824d-7423194861cf
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869823609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.3869823609
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.1461927855
Short name T335
Test name
Test status
Simulation time 112568645 ps
CPU time 4.47 seconds
Started Mar 21 03:25:46 PM PDT 24
Finished Mar 21 03:25:51 PM PDT 24
Peak memory 209140 kb
Host smart-1bc07302-7cfa-44dd-9235-7724ce15741d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1461927855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.1461927855
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.1424018039
Short name T807
Test name
Test status
Simulation time 2800073956 ps
CPU time 19.72 seconds
Started Mar 21 03:25:49 PM PDT 24
Finished Mar 21 03:26:09 PM PDT 24
Peak memory 208844 kb
Host smart-558f3648-b336-4897-be71-36b92f201feb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1424018039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.1424018039
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.195914919
Short name T674
Test name
Test status
Simulation time 660779791 ps
CPU time 6.32 seconds
Started Mar 21 03:25:53 PM PDT 24
Finished Mar 21 03:25:59 PM PDT 24
Peak memory 208360 kb
Host smart-0d3ab083-76a3-494f-b5fb-84c15f1056e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=195914919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.195914919
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.4040640435
Short name T68
Test name
Test status
Simulation time 9096199177 ps
CPU time 57.95 seconds
Started Mar 21 03:25:49 PM PDT 24
Finished Mar 21 03:26:48 PM PDT 24
Peak memory 222880 kb
Host smart-e7eab919-60cf-4fad-a6e3-d004fbca5a42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4040640435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.4040640435
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_stress_all_with_rand_reset.755278634
Short name T174
Test name
Test status
Simulation time 205367954 ps
CPU time 7.29 seconds
Started Mar 21 03:25:46 PM PDT 24
Finished Mar 21 03:25:54 PM PDT 24
Peak memory 223096 kb
Host smart-d00fd37a-8025-4069-8a39-4bdea1b01114
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=755278634 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all_with_rand_reset.755278634
Directory /workspace/34.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.3616290500
Short name T752
Test name
Test status
Simulation time 123804341 ps
CPU time 4.4 seconds
Started Mar 21 03:25:59 PM PDT 24
Finished Mar 21 03:26:04 PM PDT 24
Peak memory 210172 kb
Host smart-92a5715b-8ed3-413c-8e0c-0725057ccad4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616290500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.3616290500
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.3846831058
Short name T749
Test name
Test status
Simulation time 45035778 ps
CPU time 2.41 seconds
Started Mar 21 03:25:52 PM PDT 24
Finished Mar 21 03:25:55 PM PDT 24
Peak memory 210448 kb
Host smart-3ef38a19-5ea5-4c02-a8c1-ce4cce478c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846831058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.3846831058
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.2579552213
Short name T710
Test name
Test status
Simulation time 34314076 ps
CPU time 0.75 seconds
Started Mar 21 03:26:07 PM PDT 24
Finished Mar 21 03:26:08 PM PDT 24
Peak memory 206440 kb
Host smart-2bd6b108-6258-4e1c-99f7-d017d0e1cc1f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2579552213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.2579552213
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.2089358818
Short name T219
Test name
Test status
Simulation time 6028539797 ps
CPU time 70.17 seconds
Started Mar 21 03:26:06 PM PDT 24
Finished Mar 21 03:27:16 PM PDT 24
Peak memory 215840 kb
Host smart-1094190b-48cc-428b-bb82-ff3cb50276c8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2089358818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.2089358818
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.106541980
Short name T41
Test name
Test status
Simulation time 91568124 ps
CPU time 3.99 seconds
Started Mar 21 03:26:06 PM PDT 24
Finished Mar 21 03:26:10 PM PDT 24
Peak memory 218892 kb
Host smart-b3a6c6c4-e149-4da3-997e-9e41dc942910
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=106541980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.106541980
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.2812688035
Short name T591
Test name
Test status
Simulation time 100402195 ps
CPU time 2.58 seconds
Started Mar 21 03:26:01 PM PDT 24
Finished Mar 21 03:26:04 PM PDT 24
Peak memory 207548 kb
Host smart-a88e7714-21d6-40bc-a463-368ed2fd12e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2812688035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.2812688035
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.794132360
Short name T711
Test name
Test status
Simulation time 1487578629 ps
CPU time 24.83 seconds
Started Mar 21 03:26:01 PM PDT 24
Finished Mar 21 03:26:26 PM PDT 24
Peak memory 214756 kb
Host smart-c317825e-7f5a-4895-92f6-80a940503a10
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=794132360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.794132360
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.872604778
Short name T367
Test name
Test status
Simulation time 311246231 ps
CPU time 8.1 seconds
Started Mar 21 03:26:05 PM PDT 24
Finished Mar 21 03:26:13 PM PDT 24
Peak memory 214796 kb
Host smart-a94bebfc-3142-48ac-8d86-c9cebffa2abb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872604778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.872604778
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.2614151760
Short name T15
Test name
Test status
Simulation time 72851548 ps
CPU time 2.9 seconds
Started Mar 21 03:26:05 PM PDT 24
Finished Mar 21 03:26:08 PM PDT 24
Peak memory 223088 kb
Host smart-b70cf54a-e1ee-4e3f-abe5-755e8d9f5786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2614151760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.2614151760
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.1943413303
Short name T794
Test name
Test status
Simulation time 425673384 ps
CPU time 9.74 seconds
Started Mar 21 03:26:00 PM PDT 24
Finished Mar 21 03:26:10 PM PDT 24
Peak memory 208388 kb
Host smart-cf0c3716-c167-4eb5-9f28-20d7fb4a33c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943413303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.1943413303
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.885398636
Short name T742
Test name
Test status
Simulation time 4095013583 ps
CPU time 7.14 seconds
Started Mar 21 03:25:49 PM PDT 24
Finished Mar 21 03:25:57 PM PDT 24
Peak memory 207200 kb
Host smart-b8043503-7af9-4cd5-a402-3d74ba73d202
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885398636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.885398636
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.453380286
Short name T643
Test name
Test status
Simulation time 213991030 ps
CPU time 4.07 seconds
Started Mar 21 03:25:48 PM PDT 24
Finished Mar 21 03:25:52 PM PDT 24
Peak memory 207264 kb
Host smart-635e105b-9643-4102-a7f4-259398a0be92
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=453380286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.453380286
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.1413239975
Short name T861
Test name
Test status
Simulation time 34771366 ps
CPU time 2.47 seconds
Started Mar 21 03:25:50 PM PDT 24
Finished Mar 21 03:25:53 PM PDT 24
Peak memory 207372 kb
Host smart-2df0d156-9b40-4fe7-8d0e-fdb041ef8256
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1413239975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.1413239975
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.227904651
Short name T310
Test name
Test status
Simulation time 148584830 ps
CPU time 4.68 seconds
Started Mar 21 03:25:48 PM PDT 24
Finished Mar 21 03:25:53 PM PDT 24
Peak memory 207704 kb
Host smart-cc35149d-9de2-43df-9d82-c75f846fd7b4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=227904651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.227904651
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.3752669262
Short name T661
Test name
Test status
Simulation time 146488472 ps
CPU time 3.28 seconds
Started Mar 21 03:26:06 PM PDT 24
Finished Mar 21 03:26:09 PM PDT 24
Peak memory 210144 kb
Host smart-55b190f7-70eb-4cfa-8db3-91128056bed1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752669262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.3752669262
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.1208368907
Short name T832
Test name
Test status
Simulation time 59335021 ps
CPU time 2.29 seconds
Started Mar 21 03:25:48 PM PDT 24
Finished Mar 21 03:25:51 PM PDT 24
Peak memory 207260 kb
Host smart-cac96fe5-5157-4e79-8908-2a962574b12d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1208368907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.1208368907
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.606939634
Short name T727
Test name
Test status
Simulation time 65987303 ps
CPU time 4.7 seconds
Started Mar 21 03:26:09 PM PDT 24
Finished Mar 21 03:26:14 PM PDT 24
Peak memory 208704 kb
Host smart-2e7b33e4-9c2e-4c80-9889-5d00b640fdca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606939634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.606939634
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.3635171457
Short name T444
Test name
Test status
Simulation time 95419194 ps
CPU time 3.26 seconds
Started Mar 21 03:26:05 PM PDT 24
Finished Mar 21 03:26:08 PM PDT 24
Peak memory 210484 kb
Host smart-470c7053-9ac1-4ec9-a85c-3b1ad1ab4d2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635171457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.3635171457
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.1712468801
Short name T754
Test name
Test status
Simulation time 24407865 ps
CPU time 0.75 seconds
Started Mar 21 03:26:14 PM PDT 24
Finished Mar 21 03:26:14 PM PDT 24
Peak memory 206304 kb
Host smart-8f6bc98e-5a4f-4827-81b6-d60ce3a2aba1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1712468801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.1712468801
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.3808178397
Short name T408
Test name
Test status
Simulation time 268609383 ps
CPU time 4.25 seconds
Started Mar 21 03:26:05 PM PDT 24
Finished Mar 21 03:26:09 PM PDT 24
Peak memory 214712 kb
Host smart-cab2d2df-da81-4100-958c-5f402cccecc9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3808178397 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.3808178397
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.3905907272
Short name T22
Test name
Test status
Simulation time 118257627 ps
CPU time 2.26 seconds
Started Mar 21 03:25:59 PM PDT 24
Finished Mar 21 03:26:02 PM PDT 24
Peak memory 222020 kb
Host smart-7d8258a1-e20b-4609-86da-f4d2870fb3ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905907272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.3905907272
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.2920890862
Short name T529
Test name
Test status
Simulation time 913793832 ps
CPU time 2.86 seconds
Started Mar 21 03:25:59 PM PDT 24
Finished Mar 21 03:26:03 PM PDT 24
Peak memory 218612 kb
Host smart-a77b0d41-82ad-4c96-a2af-6be6c226a381
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2920890862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.2920890862
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.621073544
Short name T574
Test name
Test status
Simulation time 466699098 ps
CPU time 4.97 seconds
Started Mar 21 03:26:03 PM PDT 24
Finished Mar 21 03:26:08 PM PDT 24
Peak memory 209556 kb
Host smart-f79f5e85-4dd5-4b9f-9e7f-bb89f02c3545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=621073544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.621073544
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.357534697
Short name T304
Test name
Test status
Simulation time 781312117 ps
CPU time 6.16 seconds
Started Mar 21 03:26:08 PM PDT 24
Finished Mar 21 03:26:14 PM PDT 24
Peak memory 214752 kb
Host smart-953ab0fa-fb29-41cd-9fea-5d209f7fc7c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357534697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.357534697
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.722914018
Short name T843
Test name
Test status
Simulation time 1190615458 ps
CPU time 3.36 seconds
Started Mar 21 03:26:13 PM PDT 24
Finished Mar 21 03:26:17 PM PDT 24
Peak memory 220716 kb
Host smart-ad5d4123-fbfa-45fd-a024-fc5e682cccad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722914018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.722914018
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.415503686
Short name T325
Test name
Test status
Simulation time 99051863 ps
CPU time 5.31 seconds
Started Mar 21 03:26:01 PM PDT 24
Finished Mar 21 03:26:07 PM PDT 24
Peak memory 210320 kb
Host smart-90157403-ca38-4ef5-aeb5-f5d5f2ab8796
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=415503686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.415503686
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.3048654067
Short name T269
Test name
Test status
Simulation time 42770383 ps
CPU time 2.51 seconds
Started Mar 21 03:26:00 PM PDT 24
Finished Mar 21 03:26:03 PM PDT 24
Peak memory 207120 kb
Host smart-a489e041-bf54-499e-952a-64e792516bcd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048654067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.3048654067
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.2120912512
Short name T848
Test name
Test status
Simulation time 1649260904 ps
CPU time 7.5 seconds
Started Mar 21 03:26:02 PM PDT 24
Finished Mar 21 03:26:09 PM PDT 24
Peak memory 208524 kb
Host smart-5a15dee7-8024-470c-8d02-cad677243d15
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120912512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.2120912512
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.4264926820
Short name T672
Test name
Test status
Simulation time 257936873 ps
CPU time 3.17 seconds
Started Mar 21 03:26:14 PM PDT 24
Finished Mar 21 03:26:17 PM PDT 24
Peak memory 207340 kb
Host smart-6aa8fba9-ffad-4e8f-9ff9-9ae5b0daa10c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4264926820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.4264926820
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.1003846333
Short name T506
Test name
Test status
Simulation time 226787598 ps
CPU time 2.87 seconds
Started Mar 21 03:25:59 PM PDT 24
Finished Mar 21 03:26:02 PM PDT 24
Peak memory 207268 kb
Host smart-b6de2883-0960-4a7c-a03e-36f07b960094
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1003846333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.1003846333
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.162837080
Short name T315
Test name
Test status
Simulation time 381775206 ps
CPU time 3.67 seconds
Started Mar 21 03:26:05 PM PDT 24
Finished Mar 21 03:26:08 PM PDT 24
Peak memory 218872 kb
Host smart-fe452741-2083-4374-9399-4c4a5d02549d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162837080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.162837080
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.4152653537
Short name T411
Test name
Test status
Simulation time 51867848 ps
CPU time 2.86 seconds
Started Mar 21 03:26:06 PM PDT 24
Finished Mar 21 03:26:09 PM PDT 24
Peak memory 209100 kb
Host smart-e6abd1f2-2efe-4740-8ee8-d18f34cd3586
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4152653537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.4152653537
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.1705136047
Short name T795
Test name
Test status
Simulation time 359013122 ps
CPU time 18.55 seconds
Started Mar 21 03:26:01 PM PDT 24
Finished Mar 21 03:26:20 PM PDT 24
Peak memory 216448 kb
Host smart-17e523e2-6934-4ec6-b410-2d9f5e526c9f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705136047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.1705136047
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.3302062520
Short name T238
Test name
Test status
Simulation time 253778864 ps
CPU time 4.68 seconds
Started Mar 21 03:26:05 PM PDT 24
Finished Mar 21 03:26:10 PM PDT 24
Peak memory 208756 kb
Host smart-eabf72d6-c481-42ad-80c1-98280ffb7b5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302062520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.3302062520
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.2229020214
Short name T165
Test name
Test status
Simulation time 207266061 ps
CPU time 2.03 seconds
Started Mar 21 03:26:13 PM PDT 24
Finished Mar 21 03:26:15 PM PDT 24
Peak memory 210056 kb
Host smart-cd268ac3-e182-44aa-b6d0-229b4868c2e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229020214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.2229020214
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.2647641489
Short name T583
Test name
Test status
Simulation time 13256243 ps
CPU time 0.94 seconds
Started Mar 21 03:26:11 PM PDT 24
Finished Mar 21 03:26:12 PM PDT 24
Peak memory 206540 kb
Host smart-9c837fd2-baaf-47f0-924c-11e4ddc624bc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2647641489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.2647641489
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.2030519534
Short name T397
Test name
Test status
Simulation time 460877835 ps
CPU time 5.15 seconds
Started Mar 21 03:26:14 PM PDT 24
Finished Mar 21 03:26:20 PM PDT 24
Peak memory 223024 kb
Host smart-55ef0da5-1610-4185-bce6-2f8e4c731e8d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2030519534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.2030519534
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.2776403750
Short name T665
Test name
Test status
Simulation time 16690698 ps
CPU time 1.5 seconds
Started Mar 21 03:26:04 PM PDT 24
Finished Mar 21 03:26:06 PM PDT 24
Peak memory 209932 kb
Host smart-e46ed2f1-3a92-42e6-9d6b-40f40a8df6da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776403750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.2776403750
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.3856018258
Short name T524
Test name
Test status
Simulation time 58384470 ps
CPU time 3.95 seconds
Started Mar 21 03:26:08 PM PDT 24
Finished Mar 21 03:26:12 PM PDT 24
Peak memory 210352 kb
Host smart-d2aae21d-5f08-4146-969b-34b7decc9ab2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856018258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.3856018258
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.3135055820
Short name T201
Test name
Test status
Simulation time 690253318 ps
CPU time 7.3 seconds
Started Mar 21 03:26:09 PM PDT 24
Finished Mar 21 03:26:16 PM PDT 24
Peak memory 208668 kb
Host smart-ccd49571-6d13-441b-8492-b83ee7caaeb8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3135055820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.3135055820
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.2037009382
Short name T563
Test name
Test status
Simulation time 1064552004 ps
CPU time 12.65 seconds
Started Mar 21 03:26:13 PM PDT 24
Finished Mar 21 03:26:26 PM PDT 24
Peak memory 208428 kb
Host smart-36712062-b1d5-4aaa-9dac-3e2a461fc3b9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037009382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.2037009382
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.778570250
Short name T363
Test name
Test status
Simulation time 90867985 ps
CPU time 3.73 seconds
Started Mar 21 03:26:01 PM PDT 24
Finished Mar 21 03:26:05 PM PDT 24
Peak memory 208584 kb
Host smart-7b532668-bae4-4b96-8254-dbc9140b3267
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778570250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.778570250
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.3044731210
Short name T550
Test name
Test status
Simulation time 124009945 ps
CPU time 3.5 seconds
Started Mar 21 03:26:08 PM PDT 24
Finished Mar 21 03:26:12 PM PDT 24
Peak memory 207348 kb
Host smart-5b1922ae-e25e-4677-b206-03e1c96d5246
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3044731210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.3044731210
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.61606253
Short name T816
Test name
Test status
Simulation time 2166251060 ps
CPU time 29.75 seconds
Started Mar 21 03:26:02 PM PDT 24
Finished Mar 21 03:26:32 PM PDT 24
Peak memory 209680 kb
Host smart-3481e1c4-f2d4-4b32-a7c3-0bec7a0421b0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61606253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.61606253
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.2819619442
Short name T872
Test name
Test status
Simulation time 632970338 ps
CPU time 4.82 seconds
Started Mar 21 03:26:03 PM PDT 24
Finished Mar 21 03:26:08 PM PDT 24
Peak memory 207068 kb
Host smart-cb123793-c3b5-449b-a688-9caad4e069d5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819619442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.2819619442
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.1835486964
Short name T802
Test name
Test status
Simulation time 274582339 ps
CPU time 2.86 seconds
Started Mar 21 03:26:11 PM PDT 24
Finished Mar 21 03:26:14 PM PDT 24
Peak memory 209112 kb
Host smart-3f8a9cd1-d2e3-4223-a987-9bf4124b8277
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1835486964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.1835486964
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.510497298
Short name T581
Test name
Test status
Simulation time 4432406905 ps
CPU time 44.52 seconds
Started Mar 21 03:26:03 PM PDT 24
Finished Mar 21 03:26:48 PM PDT 24
Peak memory 209148 kb
Host smart-2a8b82a6-1259-410a-a0ed-4a219ef5e6bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510497298 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.510497298
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.590705283
Short name T71
Test name
Test status
Simulation time 756239583 ps
CPU time 10.73 seconds
Started Mar 21 03:26:11 PM PDT 24
Finished Mar 21 03:26:22 PM PDT 24
Peak memory 222856 kb
Host smart-4fdc1068-055f-48d4-a168-6d26493bc40e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590705283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.590705283
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.3447497519
Short name T196
Test name
Test status
Simulation time 1519414764 ps
CPU time 36.99 seconds
Started Mar 21 03:26:09 PM PDT 24
Finished Mar 21 03:26:46 PM PDT 24
Peak memory 210100 kb
Host smart-edca34e6-0b7c-4a01-a3b4-b5b1a3d83ca1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3447497519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.3447497519
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.2669796020
Short name T763
Test name
Test status
Simulation time 120873603 ps
CPU time 2.37 seconds
Started Mar 21 03:26:04 PM PDT 24
Finished Mar 21 03:26:07 PM PDT 24
Peak memory 210472 kb
Host smart-b48f3814-df60-4437-a295-a2ca8afcb713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2669796020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.2669796020
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.154694036
Short name T900
Test name
Test status
Simulation time 20748970 ps
CPU time 0.77 seconds
Started Mar 21 03:26:14 PM PDT 24
Finished Mar 21 03:26:15 PM PDT 24
Peak memory 206388 kb
Host smart-23f4df58-be73-430a-b40a-8c8557bb1e06
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154694036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.154694036
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.3620347650
Short name T899
Test name
Test status
Simulation time 134837027 ps
CPU time 3.01 seconds
Started Mar 21 03:26:00 PM PDT 24
Finished Mar 21 03:26:04 PM PDT 24
Peak memory 214808 kb
Host smart-aa83d0cb-fd7f-4840-834a-afc226326135
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3620347650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.3620347650
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.2460275443
Short name T7
Test name
Test status
Simulation time 222834671 ps
CPU time 2.92 seconds
Started Mar 21 03:26:15 PM PDT 24
Finished Mar 21 03:26:18 PM PDT 24
Peak memory 219924 kb
Host smart-551525e5-ddb7-45b7-8912-d7971e719c58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2460275443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.2460275443
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.345127858
Short name T904
Test name
Test status
Simulation time 65989810 ps
CPU time 2.1 seconds
Started Mar 21 03:26:06 PM PDT 24
Finished Mar 21 03:26:08 PM PDT 24
Peak memory 209428 kb
Host smart-16c95a51-eee9-445d-a05e-028816f3b342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=345127858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.345127858
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.3540358665
Short name T87
Test name
Test status
Simulation time 422446675 ps
CPU time 9.89 seconds
Started Mar 21 03:26:26 PM PDT 24
Finished Mar 21 03:26:37 PM PDT 24
Peak memory 222476 kb
Host smart-92e8383c-a31d-4004-92e7-f9fada230b8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540358665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.3540358665
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.712123670
Short name T273
Test name
Test status
Simulation time 123060870 ps
CPU time 5.98 seconds
Started Mar 21 03:26:16 PM PDT 24
Finished Mar 21 03:26:22 PM PDT 24
Peak memory 214768 kb
Host smart-42051e6c-f383-452d-b4e7-32650a80f158
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=712123670 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.712123670
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.2413146866
Short name T427
Test name
Test status
Simulation time 407604028 ps
CPU time 2.3 seconds
Started Mar 21 03:26:08 PM PDT 24
Finished Mar 21 03:26:11 PM PDT 24
Peak memory 216024 kb
Host smart-ed3418c0-7885-4791-9fe5-9bb9337d71dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413146866 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.2413146866
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.1578282175
Short name T632
Test name
Test status
Simulation time 647988925 ps
CPU time 8.09 seconds
Started Mar 21 03:26:02 PM PDT 24
Finished Mar 21 03:26:11 PM PDT 24
Peak memory 214904 kb
Host smart-9c0b2103-8412-4232-b494-078be3a8f668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578282175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.1578282175
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.2660252452
Short name T613
Test name
Test status
Simulation time 465324677 ps
CPU time 4.05 seconds
Started Mar 21 03:26:11 PM PDT 24
Finished Mar 21 03:26:16 PM PDT 24
Peak memory 208404 kb
Host smart-db251cd2-1ac8-4232-a552-9586e3593d66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660252452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.2660252452
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.186775912
Short name T484
Test name
Test status
Simulation time 68513640 ps
CPU time 3.41 seconds
Started Mar 21 03:26:00 PM PDT 24
Finished Mar 21 03:26:04 PM PDT 24
Peak memory 207356 kb
Host smart-825f4d1e-34bc-475a-b3eb-72aca11c7dae
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=186775912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.186775912
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.3837925058
Short name T621
Test name
Test status
Simulation time 147181260 ps
CPU time 4.87 seconds
Started Mar 21 03:26:06 PM PDT 24
Finished Mar 21 03:26:11 PM PDT 24
Peak memory 207252 kb
Host smart-9cd5963a-2b27-4c8f-93e0-768da5e242e7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3837925058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.3837925058
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.1206164155
Short name T533
Test name
Test status
Simulation time 331284646 ps
CPU time 4.08 seconds
Started Mar 21 03:26:13 PM PDT 24
Finished Mar 21 03:26:18 PM PDT 24
Peak memory 209180 kb
Host smart-2058ab9a-6b8b-4f4a-9b63-a0e7a74d00c9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1206164155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.1206164155
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.455421510
Short name T530
Test name
Test status
Simulation time 205186887 ps
CPU time 2.32 seconds
Started Mar 21 03:26:16 PM PDT 24
Finished Mar 21 03:26:19 PM PDT 24
Peak memory 214736 kb
Host smart-98fde158-73c4-45d7-8e6a-cb7bb630c08b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=455421510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.455421510
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.1845932586
Short name T441
Test name
Test status
Simulation time 51500529 ps
CPU time 2.26 seconds
Started Mar 21 03:26:01 PM PDT 24
Finished Mar 21 03:26:04 PM PDT 24
Peak memory 208780 kb
Host smart-2b9d0cfc-0757-4354-882b-2454be835999
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1845932586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.1845932586
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.4025059012
Short name T442
Test name
Test status
Simulation time 200295185 ps
CPU time 7.34 seconds
Started Mar 21 03:26:13 PM PDT 24
Finished Mar 21 03:26:21 PM PDT 24
Peak memory 207724 kb
Host smart-fe468168-8dbc-495d-8c8f-026fa69435c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025059012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.4025059012
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.2354987788
Short name T96
Test name
Test status
Simulation time 64795370 ps
CPU time 0.75 seconds
Started Mar 21 03:26:15 PM PDT 24
Finished Mar 21 03:26:16 PM PDT 24
Peak memory 206460 kb
Host smart-970cc51b-9ac5-4147-b89d-be701c7cd232
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2354987788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.2354987788
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.2564239704
Short name T371
Test name
Test status
Simulation time 726887220 ps
CPU time 9.2 seconds
Started Mar 21 03:26:15 PM PDT 24
Finished Mar 21 03:26:24 PM PDT 24
Peak memory 210224 kb
Host smart-d5f62b9b-dc8a-4ceb-b8b0-cf2cb792bcbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564239704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.2564239704
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.150006901
Short name T301
Test name
Test status
Simulation time 121728723 ps
CPU time 4.56 seconds
Started Mar 21 03:26:18 PM PDT 24
Finished Mar 21 03:26:23 PM PDT 24
Peak memory 211560 kb
Host smart-eab0e20d-a135-4bfc-a3df-f93bd3757858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150006901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.150006901
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.1312482037
Short name T198
Test name
Test status
Simulation time 125890451 ps
CPU time 3.6 seconds
Started Mar 21 03:26:15 PM PDT 24
Finished Mar 21 03:26:19 PM PDT 24
Peak memory 222948 kb
Host smart-d4e7cfa7-4deb-425d-9d9f-bfba33ead8dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1312482037 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.1312482037
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.259960435
Short name T472
Test name
Test status
Simulation time 455664646 ps
CPU time 5.52 seconds
Started Mar 21 03:26:14 PM PDT 24
Finished Mar 21 03:26:20 PM PDT 24
Peak memory 210620 kb
Host smart-d0111d93-e0d4-49d7-8c72-d50a5bc7514a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=259960435 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.259960435
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.618156667
Short name T246
Test name
Test status
Simulation time 72037859 ps
CPU time 1.85 seconds
Started Mar 21 03:26:13 PM PDT 24
Finished Mar 21 03:26:15 PM PDT 24
Peak memory 207088 kb
Host smart-0cdd35c9-6c30-4ac9-b66f-21784f1a364e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=618156667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.618156667
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.1819700577
Short name T760
Test name
Test status
Simulation time 80848944 ps
CPU time 3.58 seconds
Started Mar 21 03:26:15 PM PDT 24
Finished Mar 21 03:26:19 PM PDT 24
Peak memory 209104 kb
Host smart-58e81cc1-d072-4eb9-b4be-cd32c2753bec
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819700577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.1819700577
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.2633303927
Short name T605
Test name
Test status
Simulation time 231424517 ps
CPU time 8.43 seconds
Started Mar 21 03:26:12 PM PDT 24
Finished Mar 21 03:26:21 PM PDT 24
Peak memory 209020 kb
Host smart-cd5e3046-5e33-49f5-8045-be5ea9b95d52
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2633303927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.2633303927
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.1329783736
Short name T343
Test name
Test status
Simulation time 22500436 ps
CPU time 1.86 seconds
Started Mar 21 03:26:17 PM PDT 24
Finished Mar 21 03:26:19 PM PDT 24
Peak memory 207168 kb
Host smart-4f888f12-e9e4-4de4-9722-fd881dcab1ed
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1329783736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.1329783736
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.1665037798
Short name T557
Test name
Test status
Simulation time 573533062 ps
CPU time 5.9 seconds
Started Mar 21 03:26:15 PM PDT 24
Finished Mar 21 03:26:20 PM PDT 24
Peak memory 209828 kb
Host smart-ced94850-a7d4-433f-b26e-a03053769e9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1665037798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.1665037798
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.1560489377
Short name T504
Test name
Test status
Simulation time 141612532 ps
CPU time 2.53 seconds
Started Mar 21 03:26:14 PM PDT 24
Finished Mar 21 03:26:16 PM PDT 24
Peak memory 207168 kb
Host smart-7d584ab8-7f8d-4bac-be68-1cdf715fbde1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560489377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.1560489377
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.3655105229
Short name T868
Test name
Test status
Simulation time 24007447403 ps
CPU time 101.17 seconds
Started Mar 21 03:26:17 PM PDT 24
Finished Mar 21 03:27:58 PM PDT 24
Peak memory 219120 kb
Host smart-b0d25570-ac82-480b-a891-64e12c0791f3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655105229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.3655105229
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_stress_all_with_rand_reset.2347275888
Short name T695
Test name
Test status
Simulation time 692449391 ps
CPU time 10.3 seconds
Started Mar 21 03:26:15 PM PDT 24
Finished Mar 21 03:26:26 PM PDT 24
Peak memory 223020 kb
Host smart-c7547e0b-6805-4258-8ead-f2fabe22a101
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2347275888 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_reset.2347275888
Directory /workspace/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.3646598155
Short name T534
Test name
Test status
Simulation time 42989898 ps
CPU time 3.03 seconds
Started Mar 21 03:26:17 PM PDT 24
Finished Mar 21 03:26:21 PM PDT 24
Peak memory 208276 kb
Host smart-d2909c37-aa88-41ed-9b0a-9c03aa0d38ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3646598155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.3646598155
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.2572690119
Short name T171
Test name
Test status
Simulation time 2540870468 ps
CPU time 18.32 seconds
Started Mar 21 03:26:17 PM PDT 24
Finished Mar 21 03:26:35 PM PDT 24
Peak memory 211600 kb
Host smart-5a20f686-ba9b-4b00-8a07-a3d204c062c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2572690119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.2572690119
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.792440341
Short name T856
Test name
Test status
Simulation time 14396289 ps
CPU time 0.78 seconds
Started Mar 21 03:23:54 PM PDT 24
Finished Mar 21 03:23:54 PM PDT 24
Peak memory 206440 kb
Host smart-9f51adbe-301a-40c5-8b6b-d201c6370546
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=792440341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.792440341
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.3286199446
Short name T83
Test name
Test status
Simulation time 1460341467 ps
CPU time 9.2 seconds
Started Mar 21 03:23:55 PM PDT 24
Finished Mar 21 03:24:04 PM PDT 24
Peak memory 214832 kb
Host smart-60378f24-9647-44fa-8bde-4535e4d62ef0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3286199446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.3286199446
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.927967683
Short name T309
Test name
Test status
Simulation time 400475261 ps
CPU time 7.13 seconds
Started Mar 21 03:23:52 PM PDT 24
Finished Mar 21 03:23:59 PM PDT 24
Peak memory 217476 kb
Host smart-73599ea1-fb30-4f43-ba4e-70bc405eb68e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=927967683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.927967683
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.3725414519
Short name T756
Test name
Test status
Simulation time 347110221 ps
CPU time 2.91 seconds
Started Mar 21 03:23:55 PM PDT 24
Finished Mar 21 03:23:58 PM PDT 24
Peak memory 208544 kb
Host smart-28096410-e545-4856-9fb5-f5f23d07afcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3725414519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.3725414519
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.304516242
Short name T91
Test name
Test status
Simulation time 736599723 ps
CPU time 7.84 seconds
Started Mar 21 03:23:55 PM PDT 24
Finished Mar 21 03:24:03 PM PDT 24
Peak memory 214764 kb
Host smart-8a086fd6-980a-4f3a-af46-ef7a7f3d9e8e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304516242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.304516242
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.2576157647
Short name T181
Test name
Test status
Simulation time 55797218 ps
CPU time 3.04 seconds
Started Mar 21 03:23:55 PM PDT 24
Finished Mar 21 03:23:58 PM PDT 24
Peak memory 211772 kb
Host smart-a76fb918-b468-4a88-b03e-858be68ca6a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576157647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.2576157647
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.3455050263
Short name T555
Test name
Test status
Simulation time 355498011 ps
CPU time 3.35 seconds
Started Mar 21 03:23:54 PM PDT 24
Finished Mar 21 03:23:58 PM PDT 24
Peak memory 214836 kb
Host smart-a63641ae-e733-4e9f-8ca1-f269205f8ee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3455050263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.3455050263
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.315224047
Short name T220
Test name
Test status
Simulation time 439684423 ps
CPU time 3.25 seconds
Started Mar 21 03:23:52 PM PDT 24
Finished Mar 21 03:23:55 PM PDT 24
Peak memory 210368 kb
Host smart-bf21b7c7-73a2-4088-adb5-f2e11e100fdb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315224047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.315224047
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.3604674279
Short name T11
Test name
Test status
Simulation time 679422166 ps
CPU time 16.82 seconds
Started Mar 21 03:23:58 PM PDT 24
Finished Mar 21 03:24:15 PM PDT 24
Peak memory 234432 kb
Host smart-5ff25ee9-4410-49de-bba9-8ab879b59d76
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604674279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.3604674279
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.3247774198
Short name T75
Test name
Test status
Simulation time 807270203 ps
CPU time 9.26 seconds
Started Mar 21 03:23:58 PM PDT 24
Finished Mar 21 03:24:07 PM PDT 24
Peak memory 208236 kb
Host smart-1953fbfe-d6c7-45fc-8d49-74139e8c654e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3247774198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.3247774198
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.2341244305
Short name T507
Test name
Test status
Simulation time 434409863 ps
CPU time 2.24 seconds
Started Mar 21 03:23:53 PM PDT 24
Finished Mar 21 03:23:55 PM PDT 24
Peak memory 207744 kb
Host smart-9d073f11-0ca9-48e2-8537-660855ffc975
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2341244305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.2341244305
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.3266572226
Short name T516
Test name
Test status
Simulation time 1085597506 ps
CPU time 6.3 seconds
Started Mar 21 03:23:54 PM PDT 24
Finished Mar 21 03:24:00 PM PDT 24
Peak memory 209252 kb
Host smart-31aaea45-e155-4a41-aff5-5ea19d5039fd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3266572226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.3266572226
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.4136844577
Short name T243
Test name
Test status
Simulation time 74811533 ps
CPU time 3.55 seconds
Started Mar 21 03:23:57 PM PDT 24
Finished Mar 21 03:24:00 PM PDT 24
Peak memory 207328 kb
Host smart-509be1ce-bef5-4998-99c5-5314bbbab886
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4136844577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.4136844577
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.3856085626
Short name T678
Test name
Test status
Simulation time 39935273 ps
CPU time 2.09 seconds
Started Mar 21 03:23:55 PM PDT 24
Finished Mar 21 03:23:58 PM PDT 24
Peak memory 210332 kb
Host smart-c50a938e-c283-4022-80e2-e7e24fead1b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856085626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.3856085626
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.4184021394
Short name T723
Test name
Test status
Simulation time 68341817 ps
CPU time 2.76 seconds
Started Mar 21 03:23:57 PM PDT 24
Finished Mar 21 03:24:00 PM PDT 24
Peak memory 207088 kb
Host smart-e36ae0cc-9af1-4653-88ad-3cb0677d0cff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4184021394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.4184021394
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.551189074
Short name T178
Test name
Test status
Simulation time 1097117581 ps
CPU time 39.62 seconds
Started Mar 21 03:23:57 PM PDT 24
Finished Mar 21 03:24:37 PM PDT 24
Peak memory 222752 kb
Host smart-920915f8-df47-45e0-abdc-894922941fde
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=551189074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.551189074
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_stress_all_with_rand_reset.488540589
Short name T797
Test name
Test status
Simulation time 613346384 ps
CPU time 13.5 seconds
Started Mar 21 03:23:54 PM PDT 24
Finished Mar 21 03:24:07 PM PDT 24
Peak memory 223108 kb
Host smart-ef24e0ea-5cda-477b-807a-c0a8efaa5228
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=488540589 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all_with_rand_reset.488540589
Directory /workspace/4.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.3905701276
Short name T266
Test name
Test status
Simulation time 66393175 ps
CPU time 2.81 seconds
Started Mar 21 03:23:57 PM PDT 24
Finished Mar 21 03:24:00 PM PDT 24
Peak memory 208208 kb
Host smart-8e3c3297-c977-49c8-a9ab-1025d0f37825
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905701276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.3905701276
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.1188489822
Short name T377
Test name
Test status
Simulation time 199176622 ps
CPU time 2.92 seconds
Started Mar 21 03:23:56 PM PDT 24
Finished Mar 21 03:23:59 PM PDT 24
Peak memory 210884 kb
Host smart-abeccac1-027f-49b2-8996-0f585b418cb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1188489822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.1188489822
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.3076307551
Short name T437
Test name
Test status
Simulation time 15629630 ps
CPU time 1.01 seconds
Started Mar 21 03:26:28 PM PDT 24
Finished Mar 21 03:26:30 PM PDT 24
Peak memory 206624 kb
Host smart-c357dd14-4f61-40ec-872e-995c4ed64c36
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3076307551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.3076307551
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.580042591
Short name T707
Test name
Test status
Simulation time 40891577 ps
CPU time 1.79 seconds
Started Mar 21 03:26:28 PM PDT 24
Finished Mar 21 03:26:30 PM PDT 24
Peak memory 207752 kb
Host smart-b015d362-9dc4-4ba6-a66b-b32ad027a1e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=580042591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.580042591
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.538392025
Short name T556
Test name
Test status
Simulation time 937637125 ps
CPU time 13.32 seconds
Started Mar 21 03:26:16 PM PDT 24
Finished Mar 21 03:26:29 PM PDT 24
Peak memory 209900 kb
Host smart-40ffce82-3ef5-4fef-b517-7f9a9cd11858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538392025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.538392025
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.1415781361
Short name T883
Test name
Test status
Simulation time 445844657 ps
CPU time 3.76 seconds
Started Mar 21 03:26:14 PM PDT 24
Finished Mar 21 03:26:18 PM PDT 24
Peak memory 214864 kb
Host smart-86c40183-5cbc-4cbc-a746-b330f8fba5f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415781361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.1415781361
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.760814200
Short name T80
Test name
Test status
Simulation time 1020590933 ps
CPU time 12.01 seconds
Started Mar 21 03:26:32 PM PDT 24
Finished Mar 21 03:26:44 PM PDT 24
Peak memory 222748 kb
Host smart-96811cbd-11fa-4fa9-ae9f-25ced5501eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=760814200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.760814200
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.3350278186
Short name T748
Test name
Test status
Simulation time 392185699 ps
CPU time 2.44 seconds
Started Mar 21 03:26:14 PM PDT 24
Finished Mar 21 03:26:17 PM PDT 24
Peak memory 214844 kb
Host smart-3c73801a-058a-423d-9abe-07f245515a0a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350278186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.3350278186
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.737177698
Short name T517
Test name
Test status
Simulation time 517466086 ps
CPU time 4.05 seconds
Started Mar 21 03:26:13 PM PDT 24
Finished Mar 21 03:26:17 PM PDT 24
Peak memory 208412 kb
Host smart-659e1369-02c2-40dc-9d9d-1fefe47a3444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=737177698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.737177698
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.1838962189
Short name T319
Test name
Test status
Simulation time 1711707584 ps
CPU time 12.53 seconds
Started Mar 21 03:26:18 PM PDT 24
Finished Mar 21 03:26:31 PM PDT 24
Peak memory 209224 kb
Host smart-afaf6293-b00f-4fd3-adf8-9d2a6c3f8b9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1838962189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.1838962189
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.364139414
Short name T436
Test name
Test status
Simulation time 242196792 ps
CPU time 3.83 seconds
Started Mar 21 03:26:13 PM PDT 24
Finished Mar 21 03:26:17 PM PDT 24
Peak memory 207176 kb
Host smart-471318c3-6703-4bc6-a23c-0b3898d7bd6f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=364139414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.364139414
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.2819134877
Short name T250
Test name
Test status
Simulation time 5930318501 ps
CPU time 60.1 seconds
Started Mar 21 03:26:17 PM PDT 24
Finished Mar 21 03:27:18 PM PDT 24
Peak memory 208520 kb
Host smart-dd33943c-02ec-46f6-804b-200e9a01879c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2819134877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.2819134877
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.2766341558
Short name T336
Test name
Test status
Simulation time 429975538 ps
CPU time 11.09 seconds
Started Mar 21 03:26:14 PM PDT 24
Finished Mar 21 03:26:25 PM PDT 24
Peak memory 208812 kb
Host smart-e275b35a-d8ce-48cc-a9ff-16c4f79c7401
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2766341558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.2766341558
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.586644638
Short name T492
Test name
Test status
Simulation time 114699239 ps
CPU time 2.15 seconds
Started Mar 21 03:26:25 PM PDT 24
Finished Mar 21 03:26:27 PM PDT 24
Peak memory 216108 kb
Host smart-8dbd5ca8-e8c8-48b6-8669-0a31882eda31
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=586644638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.586644638
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.2328083246
Short name T106
Test name
Test status
Simulation time 51594680 ps
CPU time 2.64 seconds
Started Mar 21 03:26:12 PM PDT 24
Finished Mar 21 03:26:14 PM PDT 24
Peak memory 209244 kb
Host smart-414dd2e8-0149-4fac-a344-56b4c041fe45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2328083246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.2328083246
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.658070339
Short name T69
Test name
Test status
Simulation time 73882917 ps
CPU time 4.35 seconds
Started Mar 21 03:26:29 PM PDT 24
Finished Mar 21 03:26:33 PM PDT 24
Peak memory 219928 kb
Host smart-aa37fb07-b08d-420f-80e3-cc23cad1b262
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658070339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.658070339
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_stress_all_with_rand_reset.1391211500
Short name T869
Test name
Test status
Simulation time 3173553810 ps
CPU time 18.77 seconds
Started Mar 21 03:26:31 PM PDT 24
Finished Mar 21 03:26:50 PM PDT 24
Peak memory 223184 kb
Host smart-5310081f-30c4-445c-8934-6deb2770327c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391211500 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all_with_rand_reset.1391211500
Directory /workspace/40.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.1690448857
Short name T617
Test name
Test status
Simulation time 2115049288 ps
CPU time 7.63 seconds
Started Mar 21 03:26:15 PM PDT 24
Finished Mar 21 03:26:23 PM PDT 24
Peak memory 218872 kb
Host smart-27661d53-123b-4aea-8ee3-b11c1e47d1b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1690448857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.1690448857
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.1311261119
Short name T808
Test name
Test status
Simulation time 125852815 ps
CPU time 3.66 seconds
Started Mar 21 03:26:34 PM PDT 24
Finished Mar 21 03:26:38 PM PDT 24
Peak memory 210664 kb
Host smart-55f5ecb7-99f6-42b5-8e35-8a5d367820c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1311261119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.1311261119
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.2070976741
Short name T462
Test name
Test status
Simulation time 31860177 ps
CPU time 0.84 seconds
Started Mar 21 03:26:28 PM PDT 24
Finished Mar 21 03:26:29 PM PDT 24
Peak memory 206448 kb
Host smart-7d915272-0e29-4dca-a439-b170183211a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2070976741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.2070976741
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.10979835
Short name T104
Test name
Test status
Simulation time 1063213583 ps
CPU time 53.39 seconds
Started Mar 21 03:26:29 PM PDT 24
Finished Mar 21 03:27:23 PM PDT 24
Peak memory 215776 kb
Host smart-78ddd1e7-0edc-4097-8771-20f3d51b9e8d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=10979835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.10979835
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.542012043
Short name T638
Test name
Test status
Simulation time 65120843 ps
CPU time 2.18 seconds
Started Mar 21 03:26:26 PM PDT 24
Finished Mar 21 03:26:28 PM PDT 24
Peak memory 208944 kb
Host smart-384c63a9-385f-48d5-8c98-6b6fec217b43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=542012043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.542012043
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.3322240679
Short name T65
Test name
Test status
Simulation time 81251167 ps
CPU time 3.28 seconds
Started Mar 21 03:26:29 PM PDT 24
Finished Mar 21 03:26:32 PM PDT 24
Peak memory 210172 kb
Host smart-c1aeb4d1-6ca8-44ef-a5fd-3278b3c5b16e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3322240679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.3322240679
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.3577395925
Short name T282
Test name
Test status
Simulation time 429716137 ps
CPU time 5.59 seconds
Started Mar 21 03:26:30 PM PDT 24
Finished Mar 21 03:26:36 PM PDT 24
Peak memory 210444 kb
Host smart-3fc21d32-4d42-4788-9bc8-1bc4991ec994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3577395925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.3577395925
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.4038820285
Short name T211
Test name
Test status
Simulation time 410167504 ps
CPU time 6.18 seconds
Started Mar 21 03:26:32 PM PDT 24
Finished Mar 21 03:26:38 PM PDT 24
Peak memory 214836 kb
Host smart-a5ce0c07-8466-4c85-853e-d97754698476
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038820285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.4038820285
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.1934604245
Short name T493
Test name
Test status
Simulation time 10253135908 ps
CPU time 68.54 seconds
Started Mar 21 03:26:29 PM PDT 24
Finished Mar 21 03:27:38 PM PDT 24
Peak memory 221516 kb
Host smart-86605bac-f48f-49ab-a697-9298c3773601
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934604245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.1934604245
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.2270281092
Short name T222
Test name
Test status
Simulation time 242509354 ps
CPU time 6.81 seconds
Started Mar 21 03:26:27 PM PDT 24
Finished Mar 21 03:26:34 PM PDT 24
Peak memory 208324 kb
Host smart-b934041f-abbf-4ce8-897b-da80d1fda72c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2270281092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.2270281092
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.644377693
Short name T511
Test name
Test status
Simulation time 110337442 ps
CPU time 3.78 seconds
Started Mar 21 03:26:26 PM PDT 24
Finished Mar 21 03:26:30 PM PDT 24
Peak memory 208792 kb
Host smart-04f2bca4-f194-4e13-b19f-23d04383d6ec
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=644377693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.644377693
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.3327757654
Short name T906
Test name
Test status
Simulation time 269299983 ps
CPU time 2.96 seconds
Started Mar 21 03:26:25 PM PDT 24
Finished Mar 21 03:26:28 PM PDT 24
Peak memory 207404 kb
Host smart-f6d29e25-42e4-4ffa-a173-2fc194119f21
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327757654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.3327757654
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.1900464160
Short name T774
Test name
Test status
Simulation time 53023155 ps
CPU time 2.76 seconds
Started Mar 21 03:26:29 PM PDT 24
Finished Mar 21 03:26:32 PM PDT 24
Peak memory 207428 kb
Host smart-91b4f845-f635-459c-b271-5d7f8446a9bc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1900464160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.1900464160
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.2476735166
Short name T16
Test name
Test status
Simulation time 388002416 ps
CPU time 9.21 seconds
Started Mar 21 03:26:30 PM PDT 24
Finished Mar 21 03:26:39 PM PDT 24
Peak memory 214820 kb
Host smart-7a71093f-8227-4413-a7ee-b83555d1c114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476735166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.2476735166
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.1504071855
Short name T656
Test name
Test status
Simulation time 21803486 ps
CPU time 1.86 seconds
Started Mar 21 03:26:28 PM PDT 24
Finished Mar 21 03:26:30 PM PDT 24
Peak memory 207280 kb
Host smart-cdf85628-cf28-40d5-8df0-a7b27a4f4841
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1504071855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.1504071855
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.1761367389
Short name T239
Test name
Test status
Simulation time 1778531997 ps
CPU time 28.51 seconds
Started Mar 21 03:26:29 PM PDT 24
Finished Mar 21 03:26:58 PM PDT 24
Peak memory 223040 kb
Host smart-c937b1b5-d2e9-49e5-a346-54473c8b93a5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761367389 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.1761367389
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.2925373653
Short name T842
Test name
Test status
Simulation time 502950499 ps
CPU time 11.39 seconds
Started Mar 21 03:26:28 PM PDT 24
Finished Mar 21 03:26:40 PM PDT 24
Peak memory 218916 kb
Host smart-561c0807-af10-4581-b9c4-dd9a72046d90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2925373653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.2925373653
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.1746234101
Short name T460
Test name
Test status
Simulation time 74656409 ps
CPU time 1.53 seconds
Started Mar 21 03:26:26 PM PDT 24
Finished Mar 21 03:26:28 PM PDT 24
Peak memory 210440 kb
Host smart-537bb17d-ddd8-469f-9a00-749f2c229a7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1746234101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.1746234101
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.347786780
Short name T779
Test name
Test status
Simulation time 10479749 ps
CPU time 0.89 seconds
Started Mar 21 03:26:28 PM PDT 24
Finished Mar 21 03:26:29 PM PDT 24
Peak memory 206376 kb
Host smart-0c5b226f-e50f-4d42-ad77-1e89c4526d22
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=347786780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.347786780
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.1183323694
Short name T403
Test name
Test status
Simulation time 363816791 ps
CPU time 5.91 seconds
Started Mar 21 03:26:30 PM PDT 24
Finished Mar 21 03:26:37 PM PDT 24
Peak memory 215764 kb
Host smart-de4ed300-d0e2-414a-823c-2f865e8b6fa0
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1183323694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.1183323694
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.1735230578
Short name T768
Test name
Test status
Simulation time 92309444 ps
CPU time 2.87 seconds
Started Mar 21 03:26:30 PM PDT 24
Finished Mar 21 03:26:34 PM PDT 24
Peak memory 210720 kb
Host smart-6eb36865-062d-48ae-a887-1c6efeaecdcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735230578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.1735230578
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.301599360
Short name T385
Test name
Test status
Simulation time 2925933217 ps
CPU time 25.58 seconds
Started Mar 21 03:26:34 PM PDT 24
Finished Mar 21 03:27:00 PM PDT 24
Peak memory 208112 kb
Host smart-83b3199f-1e6c-430e-b5fc-6c31e0285f65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=301599360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.301599360
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.3950521459
Short name T771
Test name
Test status
Simulation time 171711878 ps
CPU time 7.39 seconds
Started Mar 21 03:26:30 PM PDT 24
Finished Mar 21 03:26:37 PM PDT 24
Peak memory 220692 kb
Host smart-c70bf718-ede0-4098-a99f-4b51f653c1fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950521459 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.3950521459
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.2628905974
Short name T254
Test name
Test status
Simulation time 149916352 ps
CPU time 5.61 seconds
Started Mar 21 03:26:27 PM PDT 24
Finished Mar 21 03:26:33 PM PDT 24
Peak memory 222988 kb
Host smart-4ef1e0c3-9e75-4d6a-b8ae-b795ddd9fe5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628905974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.2628905974
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.965587215
Short name T864
Test name
Test status
Simulation time 452244163 ps
CPU time 5.28 seconds
Started Mar 21 03:26:33 PM PDT 24
Finished Mar 21 03:26:39 PM PDT 24
Peak memory 218976 kb
Host smart-7ac39051-6ff6-47ad-b339-e4d3e9c1e5ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965587215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.965587215
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.1891034732
Short name T299
Test name
Test status
Simulation time 64838382 ps
CPU time 3.54 seconds
Started Mar 21 03:26:28 PM PDT 24
Finished Mar 21 03:26:32 PM PDT 24
Peak memory 207908 kb
Host smart-f1dad289-d730-443c-a9ad-5ad4010d3954
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891034732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.1891034732
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.1365421243
Short name T599
Test name
Test status
Simulation time 39709312 ps
CPU time 2.46 seconds
Started Mar 21 03:26:28 PM PDT 24
Finished Mar 21 03:26:31 PM PDT 24
Peak memory 207236 kb
Host smart-bfa4e7cf-cb25-4d5f-83e3-e770c3651a64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1365421243 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.1365421243
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.3342016378
Short name T124
Test name
Test status
Simulation time 968720293 ps
CPU time 5.24 seconds
Started Mar 21 03:26:34 PM PDT 24
Finished Mar 21 03:26:40 PM PDT 24
Peak memory 208404 kb
Host smart-6b5a38d0-8da4-499e-8881-1809b5063c7b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3342016378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.3342016378
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.3806651988
Short name T348
Test name
Test status
Simulation time 35802680 ps
CPU time 2.57 seconds
Started Mar 21 03:26:29 PM PDT 24
Finished Mar 21 03:26:32 PM PDT 24
Peak memory 208880 kb
Host smart-d02e22bf-023d-44dc-98dc-1ec86d073d32
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3806651988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.3806651988
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.1036926598
Short name T835
Test name
Test status
Simulation time 5638739229 ps
CPU time 40.57 seconds
Started Mar 21 03:26:32 PM PDT 24
Finished Mar 21 03:27:13 PM PDT 24
Peak memory 208904 kb
Host smart-78b90910-b432-43b9-b910-a716ef2e650e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036926598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.1036926598
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.4271231638
Short name T644
Test name
Test status
Simulation time 106910371 ps
CPU time 4.9 seconds
Started Mar 21 03:26:28 PM PDT 24
Finished Mar 21 03:26:33 PM PDT 24
Peak memory 214844 kb
Host smart-6b7a065a-c3fe-4f59-bbec-90433d6e83e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4271231638 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.4271231638
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.2748153578
Short name T19
Test name
Test status
Simulation time 445809267 ps
CPU time 3.85 seconds
Started Mar 21 03:26:29 PM PDT 24
Finished Mar 21 03:26:33 PM PDT 24
Peak memory 209224 kb
Host smart-4ef5f74c-cd2b-4fe7-a779-ba82d0cddd91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2748153578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.2748153578
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.3728544880
Short name T714
Test name
Test status
Simulation time 590951222 ps
CPU time 8.81 seconds
Started Mar 21 03:26:34 PM PDT 24
Finished Mar 21 03:26:43 PM PDT 24
Peak memory 222904 kb
Host smart-905d694d-4686-4bb6-a76f-934343b73842
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3728544880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.3728544880
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.3512056769
Short name T382
Test name
Test status
Simulation time 636320179 ps
CPU time 5.78 seconds
Started Mar 21 03:26:32 PM PDT 24
Finished Mar 21 03:26:37 PM PDT 24
Peak memory 214756 kb
Host smart-bc734e83-d677-4dbd-8e22-c55d404cf4f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3512056769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.3512056769
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.2697194240
Short name T480
Test name
Test status
Simulation time 41603543 ps
CPU time 2.55 seconds
Started Mar 21 03:26:30 PM PDT 24
Finished Mar 21 03:26:33 PM PDT 24
Peak memory 210344 kb
Host smart-d3bcbe90-37f1-4490-a3a2-d28215fba7f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2697194240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.2697194240
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.3177275592
Short name T859
Test name
Test status
Simulation time 45477422 ps
CPU time 0.95 seconds
Started Mar 21 03:26:31 PM PDT 24
Finished Mar 21 03:26:32 PM PDT 24
Peak memory 206664 kb
Host smart-d9b8fcec-f562-47eb-a535-7802ae9aebbc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3177275592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.3177275592
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.2088896209
Short name T327
Test name
Test status
Simulation time 146140100 ps
CPU time 3.22 seconds
Started Mar 21 03:26:27 PM PDT 24
Finished Mar 21 03:26:30 PM PDT 24
Peak memory 215768 kb
Host smart-7c53cf18-8a4a-413d-927a-f82bce05a950
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2088896209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.2088896209
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.3052444745
Short name T854
Test name
Test status
Simulation time 130935910 ps
CPU time 2.33 seconds
Started Mar 21 03:26:35 PM PDT 24
Finished Mar 21 03:26:37 PM PDT 24
Peak memory 209364 kb
Host smart-92edc7c9-4c37-4ffb-9976-79ad857f0fc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052444745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.3052444745
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.2995871447
Short name T838
Test name
Test status
Simulation time 49604473 ps
CPU time 1.71 seconds
Started Mar 21 03:26:27 PM PDT 24
Finished Mar 21 03:26:29 PM PDT 24
Peak memory 207428 kb
Host smart-5ccf0658-248c-4db0-ae38-e0253fd0e100
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2995871447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.2995871447
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.1177575005
Short name T776
Test name
Test status
Simulation time 2240802311 ps
CPU time 36.11 seconds
Started Mar 21 03:26:32 PM PDT 24
Finished Mar 21 03:27:08 PM PDT 24
Peak memory 219668 kb
Host smart-5af2660d-a3ec-4b72-9d75-fddaa90cbf06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1177575005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.1177575005
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.3573878766
Short name T509
Test name
Test status
Simulation time 391328060 ps
CPU time 5.82 seconds
Started Mar 21 03:26:31 PM PDT 24
Finished Mar 21 03:26:37 PM PDT 24
Peak memory 211304 kb
Host smart-a6d201e3-1360-4e79-a60b-f3231b3cd5b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573878766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.3573878766
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.2042408189
Short name T461
Test name
Test status
Simulation time 147462621 ps
CPU time 7.62 seconds
Started Mar 21 03:26:30 PM PDT 24
Finished Mar 21 03:26:38 PM PDT 24
Peak memory 221048 kb
Host smart-5b6bc103-7bb3-41ba-b82d-cb2a07f280d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2042408189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.2042408189
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.2293487320
Short name T602
Test name
Test status
Simulation time 35430879 ps
CPU time 2.73 seconds
Started Mar 21 03:26:28 PM PDT 24
Finished Mar 21 03:26:31 PM PDT 24
Peak memory 209068 kb
Host smart-74450dd2-1807-492c-b931-adf8ff5f6f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293487320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.2293487320
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.4193560382
Short name T726
Test name
Test status
Simulation time 197928544 ps
CPU time 6.03 seconds
Started Mar 21 03:26:26 PM PDT 24
Finished Mar 21 03:26:33 PM PDT 24
Peak memory 207276 kb
Host smart-3f7d7549-712c-4af8-8717-1ec2e2ebb43b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4193560382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.4193560382
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.2877626072
Short name T453
Test name
Test status
Simulation time 119528244 ps
CPU time 2.41 seconds
Started Mar 21 03:26:27 PM PDT 24
Finished Mar 21 03:26:29 PM PDT 24
Peak memory 207252 kb
Host smart-54fe66a0-aea5-42ab-a490-4b59693b9cb7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2877626072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.2877626072
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.3984800863
Short name T490
Test name
Test status
Simulation time 64010887 ps
CPU time 3.41 seconds
Started Mar 21 03:26:28 PM PDT 24
Finished Mar 21 03:26:32 PM PDT 24
Peak memory 208964 kb
Host smart-7e75d86f-bc8e-4309-8491-7aabf182233f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3984800863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.3984800863
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.4099593885
Short name T783
Test name
Test status
Simulation time 97441677 ps
CPU time 2.25 seconds
Started Mar 21 03:26:27 PM PDT 24
Finished Mar 21 03:26:30 PM PDT 24
Peak memory 209096 kb
Host smart-aa23bd0f-77f6-4996-a58d-997c81c43b31
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099593885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.4099593885
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.2293669294
Short name T588
Test name
Test status
Simulation time 228176603 ps
CPU time 5.53 seconds
Started Mar 21 03:26:27 PM PDT 24
Finished Mar 21 03:26:32 PM PDT 24
Peak memory 214896 kb
Host smart-dc0e408c-744e-4f3e-8bd8-ef986471047f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2293669294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.2293669294
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.2945037818
Short name T496
Test name
Test status
Simulation time 239655412 ps
CPU time 2.86 seconds
Started Mar 21 03:26:28 PM PDT 24
Finished Mar 21 03:26:31 PM PDT 24
Peak memory 207140 kb
Host smart-96de7083-e197-4893-915a-548519e4fbbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945037818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.2945037818
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all_with_rand_reset.3696719796
Short name T1
Test name
Test status
Simulation time 1612308158 ps
CPU time 9.96 seconds
Started Mar 21 03:26:32 PM PDT 24
Finished Mar 21 03:26:42 PM PDT 24
Peak memory 222940 kb
Host smart-145ecaf4-5b42-4d6d-a5f9-144468484fbd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3696719796 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all_with_rand_reset.3696719796
Directory /workspace/43.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.2651646761
Short name T750
Test name
Test status
Simulation time 1360602622 ps
CPU time 15.41 seconds
Started Mar 21 03:26:30 PM PDT 24
Finished Mar 21 03:26:46 PM PDT 24
Peak memory 214784 kb
Host smart-0008b292-66ac-4570-b7f5-b52a3df28aa5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651646761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.2651646761
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.1389943102
Short name T162
Test name
Test status
Simulation time 944171552 ps
CPU time 6.38 seconds
Started Mar 21 03:26:32 PM PDT 24
Finished Mar 21 03:26:38 PM PDT 24
Peak memory 210532 kb
Host smart-00a396b8-bb77-4bbe-84c5-b6d226cfbf3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1389943102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.1389943102
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.798747661
Short name T103
Test name
Test status
Simulation time 62738040 ps
CPU time 0.82 seconds
Started Mar 21 03:26:43 PM PDT 24
Finished Mar 21 03:26:44 PM PDT 24
Peak memory 206376 kb
Host smart-a2744bd4-d610-44c7-a6f8-008978c2d7aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=798747661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.798747661
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.1822947232
Short name T401
Test name
Test status
Simulation time 277972545 ps
CPU time 4.37 seconds
Started Mar 21 03:26:42 PM PDT 24
Finished Mar 21 03:26:47 PM PDT 24
Peak memory 215852 kb
Host smart-9368427e-9f24-4b2f-8994-da92f8575e15
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1822947232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.1822947232
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.39148472
Short name T329
Test name
Test status
Simulation time 577406911 ps
CPU time 3.29 seconds
Started Mar 21 03:26:44 PM PDT 24
Finished Mar 21 03:26:47 PM PDT 24
Peak memory 209232 kb
Host smart-644e45da-95b3-4e32-8c55-f51fc800b81d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39148472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.39148472
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.1964936490
Short name T92
Test name
Test status
Simulation time 347370955 ps
CPU time 6.82 seconds
Started Mar 21 03:26:44 PM PDT 24
Finished Mar 21 03:26:50 PM PDT 24
Peak memory 211436 kb
Host smart-5a15c2f3-c424-4c83-b7d0-40747ce46591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964936490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.1964936490
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.3628273187
Short name T542
Test name
Test status
Simulation time 94846740 ps
CPU time 3.01 seconds
Started Mar 21 03:26:42 PM PDT 24
Finished Mar 21 03:26:45 PM PDT 24
Peak memory 215552 kb
Host smart-aae8acf9-42c2-4678-860f-cc4823c12925
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3628273187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.3628273187
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.3967283524
Short name T623
Test name
Test status
Simulation time 2005865715 ps
CPU time 5.49 seconds
Started Mar 21 03:26:48 PM PDT 24
Finished Mar 21 03:26:54 PM PDT 24
Peak memory 208896 kb
Host smart-c7fba32d-256c-41cf-a109-ba9ff2690af7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3967283524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.3967283524
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.2402064391
Short name T341
Test name
Test status
Simulation time 342723174 ps
CPU time 4.96 seconds
Started Mar 21 03:26:41 PM PDT 24
Finished Mar 21 03:26:46 PM PDT 24
Peak memory 209064 kb
Host smart-b50fe605-04c4-4ec2-b410-bf94924e40a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2402064391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.2402064391
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.1450554963
Short name T772
Test name
Test status
Simulation time 63579701 ps
CPU time 2.92 seconds
Started Mar 21 03:26:43 PM PDT 24
Finished Mar 21 03:26:46 PM PDT 24
Peak memory 207320 kb
Host smart-ea3dd6fe-40f2-490c-9358-9f7c3f57737c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1450554963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.1450554963
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.4216020897
Short name T244
Test name
Test status
Simulation time 100847338 ps
CPU time 3.05 seconds
Started Mar 21 03:26:41 PM PDT 24
Finished Mar 21 03:26:44 PM PDT 24
Peak memory 207292 kb
Host smart-9483a775-6869-4004-a0d0-906708d5eb7e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4216020897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.4216020897
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.1024015653
Short name T787
Test name
Test status
Simulation time 235250270 ps
CPU time 3.73 seconds
Started Mar 21 03:26:48 PM PDT 24
Finished Mar 21 03:26:52 PM PDT 24
Peak memory 208972 kb
Host smart-33177fcf-bbc9-4c51-9df5-c1fae7867d6d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1024015653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.1024015653
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.1024385083
Short name T527
Test name
Test status
Simulation time 49421073 ps
CPU time 1.85 seconds
Started Mar 21 03:26:49 PM PDT 24
Finished Mar 21 03:26:51 PM PDT 24
Peak memory 208268 kb
Host smart-5ba8cbc2-d366-4a33-a8a8-25f6dc58f4b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1024385083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.1024385083
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.3381439778
Short name T736
Test name
Test status
Simulation time 58442225 ps
CPU time 2.77 seconds
Started Mar 21 03:26:33 PM PDT 24
Finished Mar 21 03:26:36 PM PDT 24
Peak memory 207660 kb
Host smart-aaa5504b-d99e-470e-b230-0fba5096b332
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3381439778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.3381439778
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.1047376444
Short name T50
Test name
Test status
Simulation time 2009312437 ps
CPU time 18.44 seconds
Started Mar 21 03:26:47 PM PDT 24
Finished Mar 21 03:27:06 PM PDT 24
Peak memory 215544 kb
Host smart-1e51b872-8e61-40d2-bdd3-07c477a9373c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047376444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.1047376444
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.891348387
Short name T537
Test name
Test status
Simulation time 976130957 ps
CPU time 4.91 seconds
Started Mar 21 03:26:43 PM PDT 24
Finished Mar 21 03:26:48 PM PDT 24
Peak memory 210284 kb
Host smart-4ef8ef7f-1b98-4c5f-ab1c-aad385cf1f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891348387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.891348387
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.687428173
Short name T822
Test name
Test status
Simulation time 587374718 ps
CPU time 4.41 seconds
Started Mar 21 03:26:42 PM PDT 24
Finished Mar 21 03:26:47 PM PDT 24
Peak memory 210576 kb
Host smart-e1e93c96-1cc9-4708-a199-105804056b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=687428173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.687428173
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.4213907750
Short name T745
Test name
Test status
Simulation time 64743152 ps
CPU time 0.88 seconds
Started Mar 21 03:26:48 PM PDT 24
Finished Mar 21 03:26:49 PM PDT 24
Peak memory 206428 kb
Host smart-6b853634-2b94-447a-b7a8-5453cf161f4f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4213907750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.4213907750
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.1882239283
Short name T681
Test name
Test status
Simulation time 221453726 ps
CPU time 2.12 seconds
Started Mar 21 03:26:46 PM PDT 24
Finished Mar 21 03:26:48 PM PDT 24
Peak memory 218988 kb
Host smart-340f2314-f1d0-4ffc-bcf9-46679fbe70f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1882239283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.1882239283
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.4242541169
Short name T90
Test name
Test status
Simulation time 195368291 ps
CPU time 5.73 seconds
Started Mar 21 03:26:47 PM PDT 24
Finished Mar 21 03:26:53 PM PDT 24
Peak memory 222848 kb
Host smart-7616f3ea-33c0-48a8-a18d-5d0c39d1d6c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4242541169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.4242541169
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.2126077179
Short name T39
Test name
Test status
Simulation time 4283618383 ps
CPU time 57.52 seconds
Started Mar 21 03:26:45 PM PDT 24
Finished Mar 21 03:27:43 PM PDT 24
Peak memory 218616 kb
Host smart-b4e77fda-7322-4b35-94a4-11a8ed63ffb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2126077179 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.2126077179
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.2000394350
Short name T821
Test name
Test status
Simulation time 361635023 ps
CPU time 3.1 seconds
Started Mar 21 03:26:46 PM PDT 24
Finished Mar 21 03:26:49 PM PDT 24
Peak memory 214908 kb
Host smart-257020b1-4881-4154-b851-a759771e1ce2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2000394350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.2000394350
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.1692456388
Short name T224
Test name
Test status
Simulation time 273353353 ps
CPU time 5.65 seconds
Started Mar 21 03:26:47 PM PDT 24
Finished Mar 21 03:26:53 PM PDT 24
Peak memory 209728 kb
Host smart-e3092fe1-d975-46c1-8ca0-0cc267668e13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1692456388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.1692456388
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.1523441342
Short name T345
Test name
Test status
Simulation time 308239838 ps
CPU time 3.04 seconds
Started Mar 21 03:26:49 PM PDT 24
Finished Mar 21 03:26:52 PM PDT 24
Peak memory 207484 kb
Host smart-0a142532-fc0e-467b-99fd-843928c95166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1523441342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.1523441342
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.2386683214
Short name T839
Test name
Test status
Simulation time 221104472 ps
CPU time 3.34 seconds
Started Mar 21 03:26:49 PM PDT 24
Finished Mar 21 03:26:53 PM PDT 24
Peak memory 208724 kb
Host smart-1498659b-0c47-4db2-b424-0149f70cc574
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2386683214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.2386683214
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.3490017795
Short name T796
Test name
Test status
Simulation time 349793201 ps
CPU time 3.73 seconds
Started Mar 21 03:26:48 PM PDT 24
Finished Mar 21 03:26:52 PM PDT 24
Peak memory 209372 kb
Host smart-6c478b78-a061-44ff-a7fa-0fa96bf74df4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490017795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.3490017795
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.967321463
Short name T671
Test name
Test status
Simulation time 509405408 ps
CPU time 4.67 seconds
Started Mar 21 03:26:47 PM PDT 24
Finished Mar 21 03:26:52 PM PDT 24
Peak memory 207884 kb
Host smart-9c10f6b6-6ecb-40fc-b0b3-a232ab504a35
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=967321463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.967321463
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.2040503410
Short name T759
Test name
Test status
Simulation time 51968787 ps
CPU time 2.92 seconds
Started Mar 21 03:26:46 PM PDT 24
Finished Mar 21 03:26:50 PM PDT 24
Peak memory 209272 kb
Host smart-ecfa0336-6398-402e-b2fc-4a6c5fc7143b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040503410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.2040503410
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.2055784028
Short name T809
Test name
Test status
Simulation time 40196357 ps
CPU time 2.27 seconds
Started Mar 21 03:26:44 PM PDT 24
Finished Mar 21 03:26:47 PM PDT 24
Peak memory 207120 kb
Host smart-677f3815-1c2a-4018-907e-55b69f8c3cfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2055784028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.2055784028
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.384301224
Short name T877
Test name
Test status
Simulation time 357773484 ps
CPU time 15.64 seconds
Started Mar 21 03:26:46 PM PDT 24
Finished Mar 21 03:27:03 PM PDT 24
Peak memory 220880 kb
Host smart-28385a2c-9ec1-48a4-880b-34651d6219a6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=384301224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.384301224
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.3429880566
Short name T126
Test name
Test status
Simulation time 47247461 ps
CPU time 3.38 seconds
Started Mar 21 03:26:47 PM PDT 24
Finished Mar 21 03:26:51 PM PDT 24
Peak memory 214748 kb
Host smart-a8985d68-145f-45f8-912d-b6c8c9e2d584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3429880566 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.3429880566
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.868328344
Short name T827
Test name
Test status
Simulation time 159383874 ps
CPU time 1.8 seconds
Started Mar 21 03:26:48 PM PDT 24
Finished Mar 21 03:26:50 PM PDT 24
Peak memory 211032 kb
Host smart-a064ae65-b9e0-4e6c-bfee-c994f6c8c4e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=868328344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.868328344
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.4272118395
Short name T420
Test name
Test status
Simulation time 42170790 ps
CPU time 0.9 seconds
Started Mar 21 03:26:45 PM PDT 24
Finished Mar 21 03:26:46 PM PDT 24
Peak memory 206360 kb
Host smart-9cf546b4-cbbf-4091-bc21-efb713ca8afe
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4272118395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.4272118395
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.276577810
Short name T404
Test name
Test status
Simulation time 192503026 ps
CPU time 3.44 seconds
Started Mar 21 03:26:48 PM PDT 24
Finished Mar 21 03:26:52 PM PDT 24
Peak memory 215132 kb
Host smart-bcb55db4-1c26-4852-b35f-452b436e88fa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=276577810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.276577810
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.2010907106
Short name T676
Test name
Test status
Simulation time 186533478 ps
CPU time 3.2 seconds
Started Mar 21 03:26:48 PM PDT 24
Finished Mar 21 03:26:51 PM PDT 24
Peak memory 210176 kb
Host smart-32b825ae-832a-4627-935e-cfcf06f2f12a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2010907106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.2010907106
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.417268133
Short name T390
Test name
Test status
Simulation time 6239928002 ps
CPU time 10.61 seconds
Started Mar 21 03:26:46 PM PDT 24
Finished Mar 21 03:26:58 PM PDT 24
Peak memory 214944 kb
Host smart-67cfd457-1622-4447-b1ea-b93c11a3efcb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417268133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.417268133
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.391469486
Short name T828
Test name
Test status
Simulation time 376662464 ps
CPU time 3.6 seconds
Started Mar 21 03:26:45 PM PDT 24
Finished Mar 21 03:26:48 PM PDT 24
Peak memory 209164 kb
Host smart-d7706c19-6b61-4229-9b9e-9df2c9fad858
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391469486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.391469486
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.376324355
Short name T741
Test name
Test status
Simulation time 322282552 ps
CPU time 4.33 seconds
Started Mar 21 03:26:47 PM PDT 24
Finished Mar 21 03:26:52 PM PDT 24
Peak memory 209272 kb
Host smart-3c5d9c2c-6111-4d3e-8af2-4fd1e2b2e519
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376324355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.376324355
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.1803377590
Short name T454
Test name
Test status
Simulation time 978747449 ps
CPU time 5.3 seconds
Started Mar 21 03:26:48 PM PDT 24
Finished Mar 21 03:26:54 PM PDT 24
Peak memory 209868 kb
Host smart-d377cf23-dcaa-47f2-bcfa-0fab222e6f63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1803377590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.1803377590
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.3972618517
Short name T833
Test name
Test status
Simulation time 631333614 ps
CPU time 14.49 seconds
Started Mar 21 03:26:47 PM PDT 24
Finished Mar 21 03:27:02 PM PDT 24
Peak memory 207080 kb
Host smart-8bcc5150-e9ab-45b4-9c4a-4475cc964a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972618517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.3972618517
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.3052365741
Short name T270
Test name
Test status
Simulation time 128641798 ps
CPU time 2.47 seconds
Started Mar 21 03:26:50 PM PDT 24
Finished Mar 21 03:26:52 PM PDT 24
Peak memory 207316 kb
Host smart-35ba0939-a7b0-4a82-8411-32ca4f3a9b50
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3052365741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.3052365741
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.37825477
Short name T686
Test name
Test status
Simulation time 19996756 ps
CPU time 1.77 seconds
Started Mar 21 03:26:49 PM PDT 24
Finished Mar 21 03:26:52 PM PDT 24
Peak memory 207172 kb
Host smart-64efc8e1-262b-44c7-95b8-a0b0ad4ec792
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37825477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.37825477
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.2674088901
Short name T880
Test name
Test status
Simulation time 3140822018 ps
CPU time 19.33 seconds
Started Mar 21 03:26:47 PM PDT 24
Finished Mar 21 03:27:06 PM PDT 24
Peak memory 209196 kb
Host smart-5a6797f0-7179-4f72-9923-245ef77d16a8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674088901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.2674088901
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.1587930964
Short name T235
Test name
Test status
Simulation time 41015578 ps
CPU time 2.23 seconds
Started Mar 21 03:26:45 PM PDT 24
Finished Mar 21 03:26:48 PM PDT 24
Peak memory 214796 kb
Host smart-d061bd6d-c0a4-4f0f-b950-a30ee2f9351d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587930964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.1587930964
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.3515663778
Short name T439
Test name
Test status
Simulation time 563786914 ps
CPU time 19.74 seconds
Started Mar 21 03:26:49 PM PDT 24
Finished Mar 21 03:27:09 PM PDT 24
Peak memory 209120 kb
Host smart-2731db3e-2d50-4951-88ab-ae05b0235f36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3515663778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.3515663778
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.3911293138
Short name T199
Test name
Test status
Simulation time 17927008367 ps
CPU time 112.33 seconds
Started Mar 21 03:26:44 PM PDT 24
Finished Mar 21 03:28:36 PM PDT 24
Peak memory 217512 kb
Host smart-0556d77e-8bf3-4efb-adaa-2b1f28689474
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911293138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.3911293138
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_stress_all_with_rand_reset.189135249
Short name T113
Test name
Test status
Simulation time 688026907 ps
CPU time 12.68 seconds
Started Mar 21 03:26:41 PM PDT 24
Finished Mar 21 03:26:54 PM PDT 24
Peak memory 223128 kb
Host smart-c0d03523-4734-4e1b-b4be-c1d989870eab
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=189135249 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all_with_rand_reset.189135249
Directory /workspace/46.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.1259551418
Short name T387
Test name
Test status
Simulation time 85835299 ps
CPU time 3.09 seconds
Started Mar 21 03:26:46 PM PDT 24
Finished Mar 21 03:26:50 PM PDT 24
Peak memory 207760 kb
Host smart-a8a471d3-8008-4be4-8944-1fe1b6fa9df1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1259551418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.1259551418
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.809086291
Short name T765
Test name
Test status
Simulation time 55006948 ps
CPU time 0.75 seconds
Started Mar 21 03:26:45 PM PDT 24
Finished Mar 21 03:26:46 PM PDT 24
Peak memory 206460 kb
Host smart-f8d622aa-b2df-45a2-8279-7c32ed51056a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=809086291 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.809086291
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.1769628947
Short name T394
Test name
Test status
Simulation time 55443623 ps
CPU time 3.83 seconds
Started Mar 21 03:26:45 PM PDT 24
Finished Mar 21 03:26:49 PM PDT 24
Peak memory 215912 kb
Host smart-3259aefe-22fc-4ab2-9f2f-bfc8ee6bfe49
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1769628947 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.1769628947
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.4081109095
Short name T353
Test name
Test status
Simulation time 318605986 ps
CPU time 6.55 seconds
Started Mar 21 03:26:44 PM PDT 24
Finished Mar 21 03:26:51 PM PDT 24
Peak memory 222404 kb
Host smart-479adfaf-d2b5-4224-8e3c-df5b9fcbff0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4081109095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.4081109095
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.1617365474
Short name T347
Test name
Test status
Simulation time 194467737 ps
CPU time 5.27 seconds
Started Mar 21 03:26:46 PM PDT 24
Finished Mar 21 03:26:52 PM PDT 24
Peak memory 207828 kb
Host smart-b6497373-adf5-4a1a-85c8-c51324768047
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617365474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.1617365474
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.1052243577
Short name T486
Test name
Test status
Simulation time 42631939 ps
CPU time 3.09 seconds
Started Mar 21 03:26:45 PM PDT 24
Finished Mar 21 03:26:48 PM PDT 24
Peak memory 214724 kb
Host smart-95c56e1c-a392-4ed2-b24b-5dda72baacd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052243577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.1052243577
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.2706671964
Short name T107
Test name
Test status
Simulation time 170583071 ps
CPU time 7.11 seconds
Started Mar 21 03:26:50 PM PDT 24
Finished Mar 21 03:26:57 PM PDT 24
Peak memory 210728 kb
Host smart-30cfdb26-1a14-4631-bc66-0f38c94b6464
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2706671964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.2706671964
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.3708677626
Short name T577
Test name
Test status
Simulation time 365918476 ps
CPU time 7.18 seconds
Started Mar 21 03:26:42 PM PDT 24
Finished Mar 21 03:26:49 PM PDT 24
Peak memory 214844 kb
Host smart-a1924231-ec9e-4d4b-87e3-f9316a697994
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3708677626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.3708677626
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.3665267960
Short name T412
Test name
Test status
Simulation time 237098817 ps
CPU time 8.9 seconds
Started Mar 21 03:26:43 PM PDT 24
Finished Mar 21 03:26:52 PM PDT 24
Peak memory 208348 kb
Host smart-2f891663-2352-4a16-8253-3dbfbc8b1a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3665267960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.3665267960
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.775572711
Short name T450
Test name
Test status
Simulation time 309279814 ps
CPU time 3.1 seconds
Started Mar 21 03:26:51 PM PDT 24
Finished Mar 21 03:26:54 PM PDT 24
Peak memory 208832 kb
Host smart-939482e8-a9d5-4859-a902-8a8dcf42f3b2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=775572711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.775572711
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.2651241665
Short name T424
Test name
Test status
Simulation time 2622018831 ps
CPU time 30.2 seconds
Started Mar 21 03:26:45 PM PDT 24
Finished Mar 21 03:27:16 PM PDT 24
Peak memory 209660 kb
Host smart-17a45928-ed06-4a15-8b83-d6909f72e16c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2651241665 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.2651241665
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.4280505437
Short name T733
Test name
Test status
Simulation time 308427344 ps
CPU time 8.06 seconds
Started Mar 21 03:26:42 PM PDT 24
Finished Mar 21 03:26:50 PM PDT 24
Peak memory 209184 kb
Host smart-604668d0-0579-45e9-bb8d-611b7a2a8271
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4280505437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.4280505437
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.2909540172
Short name T820
Test name
Test status
Simulation time 495974863 ps
CPU time 4.63 seconds
Started Mar 21 03:26:48 PM PDT 24
Finished Mar 21 03:26:53 PM PDT 24
Peak memory 218700 kb
Host smart-5ab67740-e0ff-4324-b671-9b962d6de04c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2909540172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.2909540172
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.1166199652
Short name T416
Test name
Test status
Simulation time 346799017 ps
CPU time 6.33 seconds
Started Mar 21 03:26:43 PM PDT 24
Finished Mar 21 03:26:50 PM PDT 24
Peak memory 207060 kb
Host smart-a776242c-1251-462b-9033-2b54396fabb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166199652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.1166199652
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.2929734971
Short name T592
Test name
Test status
Simulation time 1802646468 ps
CPU time 14.9 seconds
Started Mar 21 03:26:48 PM PDT 24
Finished Mar 21 03:27:04 PM PDT 24
Peak memory 215696 kb
Host smart-57ecaceb-5d53-40f9-b82e-4cd08a900907
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2929734971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.2929734971
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.574560016
Short name T740
Test name
Test status
Simulation time 776664598 ps
CPU time 25.7 seconds
Started Mar 21 03:26:43 PM PDT 24
Finished Mar 21 03:27:09 PM PDT 24
Peak memory 209200 kb
Host smart-1ad260df-2b3b-444c-a497-34abff572f81
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=574560016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.574560016
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.1574584498
Short name T853
Test name
Test status
Simulation time 308388659 ps
CPU time 2.92 seconds
Started Mar 21 03:26:49 PM PDT 24
Finished Mar 21 03:26:52 PM PDT 24
Peak memory 210444 kb
Host smart-b042aed8-55e2-4a04-b515-be6f6ff34b6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1574584498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.1574584498
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.2562366597
Short name T654
Test name
Test status
Simulation time 77994310 ps
CPU time 0.78 seconds
Started Mar 21 03:26:43 PM PDT 24
Finished Mar 21 03:26:44 PM PDT 24
Peak memory 206508 kb
Host smart-053d489f-533b-4be5-acf2-7fa81bee2a63
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2562366597 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.2562366597
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.3324598265
Short name T297
Test name
Test status
Simulation time 4621923509 ps
CPU time 58.17 seconds
Started Mar 21 03:26:43 PM PDT 24
Finished Mar 21 03:27:41 PM PDT 24
Peak memory 216540 kb
Host smart-fd1dd5cd-2a88-4428-9eb7-147d5e4a80a6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3324598265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.3324598265
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.1624833337
Short name T34
Test name
Test status
Simulation time 123639181 ps
CPU time 4.38 seconds
Started Mar 21 03:26:44 PM PDT 24
Finished Mar 21 03:26:49 PM PDT 24
Peak memory 210820 kb
Host smart-0acfc123-48e9-4fb1-9c8a-284c2f36aa79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1624833337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.1624833337
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.315652686
Short name T67
Test name
Test status
Simulation time 18215740 ps
CPU time 1.49 seconds
Started Mar 21 03:26:47 PM PDT 24
Finished Mar 21 03:26:49 PM PDT 24
Peak memory 207504 kb
Host smart-15e273dd-42da-4355-96f6-043ff8fab2a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315652686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.315652686
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.3981172138
Short name T364
Test name
Test status
Simulation time 717706717 ps
CPU time 7.82 seconds
Started Mar 21 03:26:44 PM PDT 24
Finished Mar 21 03:26:52 PM PDT 24
Peak memory 222844 kb
Host smart-326a3b89-f575-4bb2-b715-18f9be58d87e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3981172138 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.3981172138
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.2932541136
Short name T697
Test name
Test status
Simulation time 46459518 ps
CPU time 2.1 seconds
Started Mar 21 03:26:44 PM PDT 24
Finished Mar 21 03:26:46 PM PDT 24
Peak memory 209904 kb
Host smart-339004a4-2b07-41b0-9285-4cba7eca797b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2932541136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.2932541136
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.2765140405
Short name T320
Test name
Test status
Simulation time 1537442016 ps
CPU time 8.33 seconds
Started Mar 21 03:26:42 PM PDT 24
Finished Mar 21 03:26:51 PM PDT 24
Peak memory 208708 kb
Host smart-ad9cb3d4-0ed4-4383-a340-9b4abee10371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765140405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.2765140405
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.2183608725
Short name T734
Test name
Test status
Simulation time 1076058915 ps
CPU time 4.54 seconds
Started Mar 21 03:26:41 PM PDT 24
Finished Mar 21 03:26:45 PM PDT 24
Peak memory 207036 kb
Host smart-f8707f2d-e6c1-449d-b6ea-e5a952a8153e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2183608725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.2183608725
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.485204176
Short name T573
Test name
Test status
Simulation time 183279303 ps
CPU time 2.79 seconds
Started Mar 21 03:26:44 PM PDT 24
Finished Mar 21 03:26:47 PM PDT 24
Peak memory 208616 kb
Host smart-64c145f5-dc2d-4dbd-88e0-fe343d0ebe23
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485204176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.485204176
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.411159923
Short name T633
Test name
Test status
Simulation time 136980716 ps
CPU time 5.2 seconds
Started Mar 21 03:26:43 PM PDT 24
Finished Mar 21 03:26:49 PM PDT 24
Peak memory 209520 kb
Host smart-fd004cea-1220-497e-99a5-b827cc032498
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=411159923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.411159923
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.1114263851
Short name T826
Test name
Test status
Simulation time 130992173 ps
CPU time 3.64 seconds
Started Mar 21 03:26:45 PM PDT 24
Finished Mar 21 03:26:49 PM PDT 24
Peak memory 209520 kb
Host smart-caa4b777-e4d7-4228-94b0-2f8ac79fc0dc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114263851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.1114263851
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.1009934083
Short name T849
Test name
Test status
Simulation time 169423066 ps
CPU time 5.84 seconds
Started Mar 21 03:26:42 PM PDT 24
Finished Mar 21 03:26:48 PM PDT 24
Peak memory 218976 kb
Host smart-5503c7ae-d199-4b9d-82c6-7e85ca3e4459
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1009934083 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.1009934083
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.3493270406
Short name T428
Test name
Test status
Simulation time 658991970 ps
CPU time 15.26 seconds
Started Mar 21 03:26:46 PM PDT 24
Finished Mar 21 03:27:02 PM PDT 24
Peak memory 208152 kb
Host smart-6fb385cb-6fc9-44d8-aefc-6e877810c7c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493270406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.3493270406
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.3497599245
Short name T780
Test name
Test status
Simulation time 3567556543 ps
CPU time 33.54 seconds
Started Mar 21 03:26:43 PM PDT 24
Finished Mar 21 03:27:16 PM PDT 24
Peak memory 215864 kb
Host smart-498f72e0-ff9e-45a7-9aee-5f7638b1ccc2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3497599245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.3497599245
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.1964751780
Short name T123
Test name
Test status
Simulation time 113083226 ps
CPU time 6.97 seconds
Started Mar 21 03:26:43 PM PDT 24
Finished Mar 21 03:26:50 PM PDT 24
Peak memory 223148 kb
Host smart-59cacb37-72f4-4dd9-b2f7-d6832545d7ef
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1964751780 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.1964751780
Directory /workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.2168577971
Short name T846
Test name
Test status
Simulation time 124102124 ps
CPU time 3.53 seconds
Started Mar 21 03:26:40 PM PDT 24
Finished Mar 21 03:26:44 PM PDT 24
Peak memory 208088 kb
Host smart-30d17a88-61e0-4e54-baab-b8c49b1a7d72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168577971 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.2168577971
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.1775576110
Short name T896
Test name
Test status
Simulation time 88425213 ps
CPU time 2.76 seconds
Started Mar 21 03:26:43 PM PDT 24
Finished Mar 21 03:26:46 PM PDT 24
Peak memory 210780 kb
Host smart-a1de28e8-bd95-4871-b79f-a886821c2612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1775576110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.1775576110
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.863590979
Short name T433
Test name
Test status
Simulation time 26336456 ps
CPU time 0.79 seconds
Started Mar 21 03:27:01 PM PDT 24
Finished Mar 21 03:27:02 PM PDT 24
Peak memory 206444 kb
Host smart-9af1b693-d9ad-465f-9562-269c5ed21606
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863590979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.863590979
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.1080644436
Short name T140
Test name
Test status
Simulation time 291320605 ps
CPU time 4.55 seconds
Started Mar 21 03:26:57 PM PDT 24
Finished Mar 21 03:27:01 PM PDT 24
Peak memory 216092 kb
Host smart-b436d6c7-0a0d-4224-9e76-51da81b5906f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1080644436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.1080644436
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.4089313684
Short name T8
Test name
Test status
Simulation time 64316998 ps
CPU time 3.06 seconds
Started Mar 21 03:26:58 PM PDT 24
Finished Mar 21 03:27:01 PM PDT 24
Peak memory 219872 kb
Host smart-85d8b38c-9371-4877-9abd-47ea2b405ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089313684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.4089313684
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.955892047
Short name T109
Test name
Test status
Simulation time 97635946 ps
CPU time 1.6 seconds
Started Mar 21 03:26:56 PM PDT 24
Finished Mar 21 03:26:58 PM PDT 24
Peak memory 209744 kb
Host smart-34b8fada-89db-47a2-a7c5-a0dea9870b20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=955892047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.955892047
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.2054439579
Short name T603
Test name
Test status
Simulation time 132041203 ps
CPU time 3.58 seconds
Started Mar 21 03:26:58 PM PDT 24
Finished Mar 21 03:27:02 PM PDT 24
Peak memory 209084 kb
Host smart-3996e051-4a21-4a75-a158-4e28863e33a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054439579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.2054439579
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.1798999926
Short name T886
Test name
Test status
Simulation time 688132928 ps
CPU time 11.91 seconds
Started Mar 21 03:26:58 PM PDT 24
Finished Mar 21 03:27:10 PM PDT 24
Peak memory 211544 kb
Host smart-2a2ae499-2f48-4f0b-818b-79b434d7d577
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1798999926 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.1798999926
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.2443465895
Short name T200
Test name
Test status
Simulation time 70671464 ps
CPU time 3.4 seconds
Started Mar 21 03:26:58 PM PDT 24
Finished Mar 21 03:27:01 PM PDT 24
Peak memory 214752 kb
Host smart-b04fd041-9123-40cf-abc2-d1a263c245df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2443465895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.2443465895
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.4200997867
Short name T688
Test name
Test status
Simulation time 90788652 ps
CPU time 4.01 seconds
Started Mar 21 03:26:55 PM PDT 24
Finished Mar 21 03:26:59 PM PDT 24
Peak memory 214720 kb
Host smart-21b47899-72a9-48ae-8d54-220a72f638e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4200997867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.4200997867
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.295198648
Short name T641
Test name
Test status
Simulation time 63849358 ps
CPU time 3.07 seconds
Started Mar 21 03:26:41 PM PDT 24
Finished Mar 21 03:26:44 PM PDT 24
Peak memory 208816 kb
Host smart-fab270a0-b85f-44e8-a8dd-bb5c03603e4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=295198648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.295198648
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.1307624857
Short name T673
Test name
Test status
Simulation time 599116246 ps
CPU time 14.66 seconds
Started Mar 21 03:26:42 PM PDT 24
Finished Mar 21 03:26:57 PM PDT 24
Peak memory 208308 kb
Host smart-6fe030af-16e0-4e10-899d-e30a17e651dc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1307624857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.1307624857
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.436222969
Short name T722
Test name
Test status
Simulation time 1621212947 ps
CPU time 28.52 seconds
Started Mar 21 03:26:43 PM PDT 24
Finished Mar 21 03:27:12 PM PDT 24
Peak memory 209004 kb
Host smart-5395278e-9348-4f74-8300-984a8bc52496
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=436222969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.436222969
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.759294847
Short name T463
Test name
Test status
Simulation time 104723872 ps
CPU time 4.21 seconds
Started Mar 21 03:26:43 PM PDT 24
Finished Mar 21 03:26:47 PM PDT 24
Peak memory 209240 kb
Host smart-937673b5-6c35-4ea7-b536-d421ab010b7f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=759294847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.759294847
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.3746410533
Short name T717
Test name
Test status
Simulation time 113464099 ps
CPU time 3.21 seconds
Started Mar 21 03:26:58 PM PDT 24
Finished Mar 21 03:27:01 PM PDT 24
Peak memory 210284 kb
Host smart-41d818c4-be78-4f48-b377-6f2ba4afbf1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746410533 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.3746410533
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.874128989
Short name T905
Test name
Test status
Simulation time 83283299 ps
CPU time 2.39 seconds
Started Mar 21 03:26:40 PM PDT 24
Finished Mar 21 03:26:43 PM PDT 24
Peak memory 207188 kb
Host smart-6ad51a6f-8d55-4e9f-834f-f6f4759d28ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=874128989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.874128989
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all_with_rand_reset.1944371001
Short name T45
Test name
Test status
Simulation time 267660784 ps
CPU time 10.07 seconds
Started Mar 21 03:26:59 PM PDT 24
Finished Mar 21 03:27:09 PM PDT 24
Peak memory 223124 kb
Host smart-15ae907c-d826-41c1-b289-8e641697bbb7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1944371001 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all_with_rand_reset.1944371001
Directory /workspace/49.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.1956216785
Short name T532
Test name
Test status
Simulation time 163065510 ps
CPU time 6.09 seconds
Started Mar 21 03:26:55 PM PDT 24
Finished Mar 21 03:27:02 PM PDT 24
Peak memory 209664 kb
Host smart-494fed70-d15b-4cef-b3cb-43437a27c964
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1956216785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.1956216785
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.1994155837
Short name T614
Test name
Test status
Simulation time 14865514 ps
CPU time 0.9 seconds
Started Mar 21 03:23:54 PM PDT 24
Finished Mar 21 03:23:55 PM PDT 24
Peak memory 206652 kb
Host smart-a5b0fb77-ad05-4cc5-ab16-4a401d41a052
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994155837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.1994155837
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.2206483304
Short name T20
Test name
Test status
Simulation time 92430750 ps
CPU time 4.05 seconds
Started Mar 21 03:23:56 PM PDT 24
Finished Mar 21 03:24:00 PM PDT 24
Peak memory 211256 kb
Host smart-227fd673-917a-4387-ab23-a14c028aca5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2206483304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.2206483304
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.4172742467
Short name T689
Test name
Test status
Simulation time 916919688 ps
CPU time 11.8 seconds
Started Mar 21 03:23:52 PM PDT 24
Finished Mar 21 03:24:04 PM PDT 24
Peak memory 209604 kb
Host smart-087084de-44d5-4a31-8d0f-72e773ae3d12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172742467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.4172742467
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.3252835096
Short name T285
Test name
Test status
Simulation time 384689644 ps
CPU time 5.67 seconds
Started Mar 21 03:23:53 PM PDT 24
Finished Mar 21 03:23:59 PM PDT 24
Peak memory 214840 kb
Host smart-ee6e5bae-57ee-489a-9ab4-7d2baeb19fbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252835096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.3252835096
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.2100344125
Short name T875
Test name
Test status
Simulation time 330563773 ps
CPU time 2.57 seconds
Started Mar 21 03:23:51 PM PDT 24
Finished Mar 21 03:23:54 PM PDT 24
Peak memory 215228 kb
Host smart-11ea863f-9af1-497a-b2e5-cc40c771cd3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2100344125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.2100344125
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.751414379
Short name T804
Test name
Test status
Simulation time 89804469 ps
CPU time 3.55 seconds
Started Mar 21 03:23:55 PM PDT 24
Finished Mar 21 03:23:59 PM PDT 24
Peak memory 209472 kb
Host smart-6e0d47a6-ab84-4632-8140-f042e0121040
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=751414379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.751414379
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.2136389653
Short name T739
Test name
Test status
Simulation time 323256337 ps
CPU time 4.07 seconds
Started Mar 21 03:23:56 PM PDT 24
Finished Mar 21 03:24:00 PM PDT 24
Peak memory 207244 kb
Host smart-69d36e3a-7040-4ae6-b1eb-e71f75f5defd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136389653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.2136389653
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.660924410
Short name T429
Test name
Test status
Simulation time 310929490 ps
CPU time 4.25 seconds
Started Mar 21 03:23:54 PM PDT 24
Finished Mar 21 03:23:59 PM PDT 24
Peak memory 209160 kb
Host smart-07d77cba-eef5-4383-94df-3c486051bd46
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=660924410 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.660924410
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.1703369806
Short name T531
Test name
Test status
Simulation time 159356629 ps
CPU time 4.04 seconds
Started Mar 21 03:23:57 PM PDT 24
Finished Mar 21 03:24:01 PM PDT 24
Peak memory 209548 kb
Host smart-d64c0457-14fb-4bf4-96df-7e38578be801
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1703369806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.1703369806
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.1530426043
Short name T895
Test name
Test status
Simulation time 38869089 ps
CPU time 2.84 seconds
Started Mar 21 03:23:55 PM PDT 24
Finished Mar 21 03:23:58 PM PDT 24
Peak memory 209376 kb
Host smart-368733a2-d926-44f9-bd0a-3e4c8c4ba431
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1530426043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.1530426043
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.2035807985
Short name T902
Test name
Test status
Simulation time 22118279 ps
CPU time 1.44 seconds
Started Mar 21 03:23:55 PM PDT 24
Finished Mar 21 03:23:56 PM PDT 24
Peak memory 208292 kb
Host smart-b71b6805-2529-44bf-8257-044e35a8a48b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2035807985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.2035807985
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.298796191
Short name T866
Test name
Test status
Simulation time 72071319 ps
CPU time 1.79 seconds
Started Mar 21 03:23:53 PM PDT 24
Finished Mar 21 03:23:55 PM PDT 24
Peak memory 207556 kb
Host smart-12c45f96-280d-443a-bf04-fccba82bee51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298796191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.298796191
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.82332254
Short name T720
Test name
Test status
Simulation time 5121582391 ps
CPU time 38.82 seconds
Started Mar 21 03:23:53 PM PDT 24
Finished Mar 21 03:24:32 PM PDT 24
Peak memory 217124 kb
Host smart-227abcb7-620b-46f4-9003-4b6373082f4d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82332254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.82332254
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.328939573
Short name T785
Test name
Test status
Simulation time 132581813 ps
CPU time 5.65 seconds
Started Mar 21 03:23:52 PM PDT 24
Finished Mar 21 03:23:58 PM PDT 24
Peak memory 214820 kb
Host smart-55faa77d-e034-4b76-9784-4bc269274b64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328939573 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.328939573
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.561539527
Short name T469
Test name
Test status
Simulation time 234531177 ps
CPU time 2.93 seconds
Started Mar 21 03:23:58 PM PDT 24
Finished Mar 21 03:24:01 PM PDT 24
Peak memory 210736 kb
Host smart-d7e65392-0a82-491b-8a9a-954ce320bd61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=561539527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.561539527
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.372768544
Short name T735
Test name
Test status
Simulation time 29449172 ps
CPU time 1.16 seconds
Started Mar 21 03:23:57 PM PDT 24
Finished Mar 21 03:23:59 PM PDT 24
Peak memory 206524 kb
Host smart-fbfca6aa-b7ad-4c0f-aa7d-a486c00e3ce9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=372768544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.372768544
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.3254325428
Short name T131
Test name
Test status
Simulation time 56586581 ps
CPU time 4.35 seconds
Started Mar 21 03:23:57 PM PDT 24
Finished Mar 21 03:24:02 PM PDT 24
Peak memory 215492 kb
Host smart-f1dac9d7-f89e-4dae-abdd-40b32297d4b6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3254325428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.3254325428
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.4215553831
Short name T668
Test name
Test status
Simulation time 614852870 ps
CPU time 10.94 seconds
Started Mar 21 03:23:55 PM PDT 24
Finished Mar 21 03:24:06 PM PDT 24
Peak memory 210652 kb
Host smart-18c33fbd-8aa5-49eb-baf6-fb3d7282fe63
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215553831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.4215553831
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.1021659765
Short name T300
Test name
Test status
Simulation time 41416970 ps
CPU time 2.06 seconds
Started Mar 21 03:23:53 PM PDT 24
Finished Mar 21 03:23:55 PM PDT 24
Peak memory 214752 kb
Host smart-f051d619-5349-4750-a93f-cc4cf1b79847
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1021659765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.1021659765
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.2292171030
Short name T89
Test name
Test status
Simulation time 826906823 ps
CPU time 14.52 seconds
Started Mar 21 03:23:55 PM PDT 24
Finished Mar 21 03:24:10 PM PDT 24
Peak memory 210224 kb
Host smart-efb3f617-dd62-4e7d-baab-01d63ce2c6f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2292171030 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.2292171030
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.3384481836
Short name T283
Test name
Test status
Simulation time 176255454 ps
CPU time 6.72 seconds
Started Mar 21 03:23:53 PM PDT 24
Finished Mar 21 03:23:59 PM PDT 24
Peak memory 214772 kb
Host smart-0f573f68-2fc0-4f8c-8aa8-f329e090577e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384481836 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.3384481836
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.3435987582
Short name T338
Test name
Test status
Simulation time 131992022 ps
CPU time 3.96 seconds
Started Mar 21 03:23:55 PM PDT 24
Finished Mar 21 03:23:59 PM PDT 24
Peak memory 214840 kb
Host smart-0b280dda-d6aa-465b-bc90-862e862f5004
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3435987582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.3435987582
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.3660198848
Short name T323
Test name
Test status
Simulation time 190587459 ps
CPU time 5.81 seconds
Started Mar 21 03:23:55 PM PDT 24
Finished Mar 21 03:24:01 PM PDT 24
Peak memory 210112 kb
Host smart-b9b1ce13-b76a-4f81-8c82-664f6f9db88e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3660198848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.3660198848
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.1785538008
Short name T225
Test name
Test status
Simulation time 3366226130 ps
CPU time 43.38 seconds
Started Mar 21 03:23:54 PM PDT 24
Finished Mar 21 03:24:38 PM PDT 24
Peak memory 208348 kb
Host smart-d2afae9d-66e6-4c6f-836b-357f3185cb5d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1785538008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.1785538008
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.781807259
Short name T837
Test name
Test status
Simulation time 31437383 ps
CPU time 2.42 seconds
Started Mar 21 03:23:54 PM PDT 24
Finished Mar 21 03:23:57 PM PDT 24
Peak memory 209180 kb
Host smart-7b5b4483-1016-480e-93ad-d83cce41563b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781807259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.781807259
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.1580864700
Short name T664
Test name
Test status
Simulation time 80094292 ps
CPU time 3.63 seconds
Started Mar 21 03:23:55 PM PDT 24
Finished Mar 21 03:23:58 PM PDT 24
Peak memory 209100 kb
Host smart-14847b4c-b26d-4ae7-91a3-4889a78002b2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1580864700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.1580864700
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.3038668413
Short name T892
Test name
Test status
Simulation time 532211242 ps
CPU time 3.62 seconds
Started Mar 21 03:23:52 PM PDT 24
Finished Mar 21 03:23:56 PM PDT 24
Peak memory 208668 kb
Host smart-be8e592c-0a7f-47ab-b1bc-a5a084698db5
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3038668413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.3038668413
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.364213696
Short name T396
Test name
Test status
Simulation time 349916108 ps
CPU time 3.67 seconds
Started Mar 21 03:23:57 PM PDT 24
Finished Mar 21 03:24:01 PM PDT 24
Peak memory 218592 kb
Host smart-32238b63-ec16-45be-80de-e363f0d40e94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=364213696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.364213696
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.81961863
Short name T455
Test name
Test status
Simulation time 2737753842 ps
CPU time 17.27 seconds
Started Mar 21 03:23:57 PM PDT 24
Finished Mar 21 03:24:15 PM PDT 24
Peak memory 209124 kb
Host smart-d77723c9-5860-4dc3-b249-4fd05beb209c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=81961863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.81961863
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.684612340
Short name T252
Test name
Test status
Simulation time 2002535637 ps
CPU time 64.55 seconds
Started Mar 21 03:23:54 PM PDT 24
Finished Mar 21 03:24:59 PM PDT 24
Peak memory 215964 kb
Host smart-b434129c-39c8-49f7-a1f5-3f89ad29f83b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=684612340 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.684612340
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.3385046493
Short name T657
Test name
Test status
Simulation time 402277790 ps
CPU time 3.79 seconds
Started Mar 21 03:23:55 PM PDT 24
Finished Mar 21 03:23:59 PM PDT 24
Peak memory 208000 kb
Host smart-f45b7d38-82b4-47fb-a052-440a0cc05f30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385046493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.3385046493
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.3535283456
Short name T77
Test name
Test status
Simulation time 34863475 ps
CPU time 2 seconds
Started Mar 21 03:23:56 PM PDT 24
Finished Mar 21 03:23:58 PM PDT 24
Peak memory 210124 kb
Host smart-9e02a347-5ea0-477d-9a01-d43963213712
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535283456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.3535283456
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.1412223158
Short name T670
Test name
Test status
Simulation time 44876307 ps
CPU time 0.76 seconds
Started Mar 21 03:23:55 PM PDT 24
Finished Mar 21 03:23:56 PM PDT 24
Peak memory 206468 kb
Host smart-3d898e06-f3a3-4746-9182-0376ecb62a5a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1412223158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.1412223158
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.1808953781
Short name T595
Test name
Test status
Simulation time 404830473 ps
CPU time 4.9 seconds
Started Mar 21 03:23:55 PM PDT 24
Finished Mar 21 03:24:00 PM PDT 24
Peak memory 218940 kb
Host smart-0739e37c-87c6-4565-add1-94d181c82624
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808953781 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.1808953781
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.3337777655
Short name T369
Test name
Test status
Simulation time 212579579 ps
CPU time 2.53 seconds
Started Mar 21 03:23:57 PM PDT 24
Finished Mar 21 03:24:00 PM PDT 24
Peak memory 209104 kb
Host smart-1ec2e4d6-b9ef-4b57-9ae3-42cb33ee5831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3337777655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.3337777655
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.3955405142
Short name T863
Test name
Test status
Simulation time 116039875 ps
CPU time 2.28 seconds
Started Mar 21 03:23:58 PM PDT 24
Finished Mar 21 03:24:00 PM PDT 24
Peak memory 208776 kb
Host smart-e175f49d-abf8-4683-b66d-7242b5a1aa87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955405142 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.3955405142
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_random.3554326594
Short name T818
Test name
Test status
Simulation time 254551702 ps
CPU time 7.57 seconds
Started Mar 21 03:23:56 PM PDT 24
Finished Mar 21 03:24:04 PM PDT 24
Peak memory 209172 kb
Host smart-c78f3abe-9ef0-4731-b123-66eaa3a84ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3554326594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.3554326594
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.3909699024
Short name T240
Test name
Test status
Simulation time 872146489 ps
CPU time 6.71 seconds
Started Mar 21 03:23:59 PM PDT 24
Finished Mar 21 03:24:06 PM PDT 24
Peak memory 208924 kb
Host smart-61fdce9e-10fc-4ee2-80d2-fc2288380abd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3909699024 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.3909699024
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.1383716568
Short name T590
Test name
Test status
Simulation time 57518615 ps
CPU time 3.12 seconds
Started Mar 21 03:23:56 PM PDT 24
Finished Mar 21 03:23:59 PM PDT 24
Peak memory 208972 kb
Host smart-f2b7632e-25dc-4f66-a0bb-0d67f9e15920
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1383716568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.1383716568
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.1600530622
Short name T841
Test name
Test status
Simulation time 16356135476 ps
CPU time 59.65 seconds
Started Mar 21 03:23:56 PM PDT 24
Finished Mar 21 03:24:56 PM PDT 24
Peak memory 209056 kb
Host smart-16ba186f-8017-41ac-9e60-7a7800cf8b8c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1600530622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.1600530622
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.1955328752
Short name T549
Test name
Test status
Simulation time 151914609 ps
CPU time 2.69 seconds
Started Mar 21 03:23:57 PM PDT 24
Finished Mar 21 03:24:00 PM PDT 24
Peak memory 207732 kb
Host smart-2c878a70-6578-4d58-85b2-1a04d3184b32
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1955328752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.1955328752
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.2564994418
Short name T553
Test name
Test status
Simulation time 68955835 ps
CPU time 1.96 seconds
Started Mar 21 03:23:56 PM PDT 24
Finished Mar 21 03:23:58 PM PDT 24
Peak memory 214988 kb
Host smart-9168bd33-9557-4491-a172-bc22745278c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2564994418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.2564994418
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.2332081750
Short name T417
Test name
Test status
Simulation time 87692883 ps
CPU time 1.78 seconds
Started Mar 21 03:23:57 PM PDT 24
Finished Mar 21 03:23:58 PM PDT 24
Peak memory 207116 kb
Host smart-cce42c98-9c5f-4cc9-b1a0-17536f7f8a62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2332081750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.2332081750
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.62163257
Short name T179
Test name
Test status
Simulation time 3788502350 ps
CPU time 84.66 seconds
Started Mar 21 03:24:01 PM PDT 24
Finished Mar 21 03:25:26 PM PDT 24
Peak memory 218792 kb
Host smart-b908d9fd-412f-4c44-8308-4dd3fd256035
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62163257 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.62163257
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.862059321
Short name T855
Test name
Test status
Simulation time 307933994 ps
CPU time 4.27 seconds
Started Mar 21 03:23:54 PM PDT 24
Finished Mar 21 03:23:58 PM PDT 24
Peak memory 208980 kb
Host smart-75764a9c-45d7-4cf9-a177-dbd6913e30c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=862059321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.862059321
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.3869857898
Short name T682
Test name
Test status
Simulation time 298936340 ps
CPU time 2.73 seconds
Started Mar 21 03:23:55 PM PDT 24
Finished Mar 21 03:23:58 PM PDT 24
Peak memory 210260 kb
Host smart-f96c9b1c-551b-42ba-864b-baa9ac03ce2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3869857898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.3869857898
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.3999168190
Short name T514
Test name
Test status
Simulation time 11755452 ps
CPU time 0.86 seconds
Started Mar 21 03:24:13 PM PDT 24
Finished Mar 21 03:24:14 PM PDT 24
Peak memory 206356 kb
Host smart-82367cec-3f92-4e3d-8668-732a9fb1c951
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3999168190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.3999168190
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.3456164535
Short name T391
Test name
Test status
Simulation time 26674421 ps
CPU time 2.28 seconds
Started Mar 21 03:24:15 PM PDT 24
Finished Mar 21 03:24:17 PM PDT 24
Peak memory 214600 kb
Host smart-7e9d543e-a7ff-4f34-8919-4afaf06e0cd1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3456164535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.3456164535
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.2389295754
Short name T37
Test name
Test status
Simulation time 57223057 ps
CPU time 2.02 seconds
Started Mar 21 03:24:06 PM PDT 24
Finished Mar 21 03:24:09 PM PDT 24
Peak memory 221648 kb
Host smart-dbee4733-eb2f-49cb-8dd0-0e664d442dec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2389295754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.2389295754
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.1880360212
Short name T292
Test name
Test status
Simulation time 345280647 ps
CPU time 3.14 seconds
Started Mar 21 03:24:15 PM PDT 24
Finished Mar 21 03:24:18 PM PDT 24
Peak memory 210128 kb
Host smart-d0e0ad9d-249d-4cd9-87b5-246347755eda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1880360212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.1880360212
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.1960583934
Short name T370
Test name
Test status
Simulation time 399160804 ps
CPU time 4.56 seconds
Started Mar 21 03:24:10 PM PDT 24
Finished Mar 21 03:24:15 PM PDT 24
Peak memory 221424 kb
Host smart-9b4d10c5-aeaf-486e-9bc3-b76d71343113
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1960583934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.1960583934
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.2958946071
Short name T275
Test name
Test status
Simulation time 2471711112 ps
CPU time 10.18 seconds
Started Mar 21 03:24:09 PM PDT 24
Finished Mar 21 03:24:19 PM PDT 24
Peak memory 214888 kb
Host smart-aa7d7000-acad-44aa-8c10-9fe2308f087a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2958946071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.2958946071
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.2404312887
Short name T587
Test name
Test status
Simulation time 216871832 ps
CPU time 2.29 seconds
Started Mar 21 03:24:14 PM PDT 24
Finished Mar 21 03:24:17 PM PDT 24
Peak memory 206812 kb
Host smart-67e9d3cb-dcda-4089-a847-f6367e739398
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2404312887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.2404312887
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.1157386231
Short name T620
Test name
Test status
Simulation time 101147967 ps
CPU time 4.1 seconds
Started Mar 21 03:24:13 PM PDT 24
Finished Mar 21 03:24:18 PM PDT 24
Peak memory 222936 kb
Host smart-dab64256-07c8-4c4f-8935-57a1e5dffe4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157386231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.1157386231
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.1163877062
Short name T764
Test name
Test status
Simulation time 183595606 ps
CPU time 3.08 seconds
Started Mar 21 03:24:15 PM PDT 24
Finished Mar 21 03:24:19 PM PDT 24
Peak memory 207132 kb
Host smart-b4c18927-60ba-4a5b-802a-197f326c2f0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1163877062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.1163877062
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.1979130512
Short name T386
Test name
Test status
Simulation time 166466278 ps
CPU time 4.46 seconds
Started Mar 21 03:24:15 PM PDT 24
Finished Mar 21 03:24:20 PM PDT 24
Peak memory 208220 kb
Host smart-7be20425-257c-4523-815d-b54e0a9bc2c5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1979130512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.1979130512
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.2909358739
Short name T713
Test name
Test status
Simulation time 505853519 ps
CPU time 9.48 seconds
Started Mar 21 03:24:07 PM PDT 24
Finished Mar 21 03:24:17 PM PDT 24
Peak memory 208372 kb
Host smart-e57ffe08-4f7f-49fb-8c18-1f934862a043
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2909358739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.2909358739
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.918217875
Short name T105
Test name
Test status
Simulation time 576156337 ps
CPU time 4.39 seconds
Started Mar 21 03:24:09 PM PDT 24
Finished Mar 21 03:24:13 PM PDT 24
Peak memory 208960 kb
Host smart-af081d0f-0ef3-4886-9f96-806410c9aeed
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918217875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.918217875
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.931307090
Short name T541
Test name
Test status
Simulation time 231288580 ps
CPU time 3.11 seconds
Started Mar 21 03:24:06 PM PDT 24
Finished Mar 21 03:24:10 PM PDT 24
Peak memory 209716 kb
Host smart-5eda80ea-e770-4ecb-a8b4-2c28ac89da6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=931307090 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.931307090
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.208840293
Short name T512
Test name
Test status
Simulation time 794111263 ps
CPU time 19.9 seconds
Started Mar 21 03:24:04 PM PDT 24
Finished Mar 21 03:24:25 PM PDT 24
Peak memory 208016 kb
Host smart-1e0bef01-50b3-4a07-89e1-cfe3e91a2c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=208840293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.208840293
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.2248523516
Short name T313
Test name
Test status
Simulation time 3406457645 ps
CPU time 25.57 seconds
Started Mar 21 03:24:18 PM PDT 24
Finished Mar 21 03:24:43 PM PDT 24
Peak memory 223104 kb
Host smart-36d619cc-6279-4da9-b9d6-05c5508581b7
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2248523516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.2248523516
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.3807269766
Short name T102
Test name
Test status
Simulation time 106269602 ps
CPU time 4.85 seconds
Started Mar 21 03:24:18 PM PDT 24
Finished Mar 21 03:24:23 PM PDT 24
Peak memory 207688 kb
Host smart-9326a65c-dab0-4180-946b-5d95f4564591
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3807269766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.3807269766
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.4158171983
Short name T606
Test name
Test status
Simulation time 226317515 ps
CPU time 2.97 seconds
Started Mar 21 03:24:13 PM PDT 24
Finished Mar 21 03:24:16 PM PDT 24
Peak memory 210732 kb
Host smart-698d306c-dcb8-435a-ac72-1c3180438ba1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158171983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.4158171983
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.1785239788
Short name T466
Test name
Test status
Simulation time 14012462 ps
CPU time 0.81 seconds
Started Mar 21 03:24:07 PM PDT 24
Finished Mar 21 03:24:09 PM PDT 24
Peak memory 206428 kb
Host smart-165c0d69-7800-40b8-a3d1-bb653a51c825
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1785239788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.1785239788
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.2667209862
Short name T908
Test name
Test status
Simulation time 665057105 ps
CPU time 9.8 seconds
Started Mar 21 03:24:10 PM PDT 24
Finished Mar 21 03:24:20 PM PDT 24
Peak memory 215564 kb
Host smart-0baa6bfc-a566-4a9e-856d-998684b7b62b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2667209862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.2667209862
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.2234267851
Short name T312
Test name
Test status
Simulation time 231820741 ps
CPU time 3.47 seconds
Started Mar 21 03:24:08 PM PDT 24
Finished Mar 21 03:24:12 PM PDT 24
Peak memory 218668 kb
Host smart-7117e1b9-1c97-4441-854d-1ec5b2458680
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2234267851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.2234267851
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.4000289125
Short name T604
Test name
Test status
Simulation time 47782502 ps
CPU time 1.24 seconds
Started Mar 21 03:24:07 PM PDT 24
Finished Mar 21 03:24:09 PM PDT 24
Peak memory 208436 kb
Host smart-b27cb8eb-7cb1-4735-8c40-93bad54a2f32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4000289125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.4000289125
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.29960388
Short name T234
Test name
Test status
Simulation time 398147575 ps
CPU time 4.59 seconds
Started Mar 21 03:24:06 PM PDT 24
Finished Mar 21 03:24:11 PM PDT 24
Peak memory 214816 kb
Host smart-f5b445bb-afb7-47db-acb9-53553172dfed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=29960388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.29960388
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.2688454997
Short name T279
Test name
Test status
Simulation time 323305590 ps
CPU time 4.2 seconds
Started Mar 21 03:24:05 PM PDT 24
Finished Mar 21 03:24:10 PM PDT 24
Peak memory 211412 kb
Host smart-79888533-08ea-42a1-af86-420ce142daf8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2688454997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.2688454997
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.2053560423
Short name T384
Test name
Test status
Simulation time 78637492 ps
CPU time 4 seconds
Started Mar 21 03:24:15 PM PDT 24
Finished Mar 21 03:24:19 PM PDT 24
Peak memory 221032 kb
Host smart-ea20da4a-4841-4011-a8c7-cd2b136ca11b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053560423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.2053560423
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.50013775
Short name T597
Test name
Test status
Simulation time 379610731 ps
CPU time 4.76 seconds
Started Mar 21 03:24:06 PM PDT 24
Finished Mar 21 03:24:11 PM PDT 24
Peak memory 208108 kb
Host smart-f7eeb720-3348-4048-b9ec-d0daee501c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50013775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.50013775
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.4038234752
Short name T709
Test name
Test status
Simulation time 115809358 ps
CPU time 2.35 seconds
Started Mar 21 03:24:09 PM PDT 24
Finished Mar 21 03:24:12 PM PDT 24
Peak memory 209408 kb
Host smart-39b80852-5482-4ee6-ac49-7f5116a4747d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038234752 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.4038234752
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.2768422640
Short name T788
Test name
Test status
Simulation time 36917752 ps
CPU time 2.48 seconds
Started Mar 21 03:24:07 PM PDT 24
Finished Mar 21 03:24:09 PM PDT 24
Peak memory 207928 kb
Host smart-bf6ab419-1a94-4119-ad70-7d53cd4de424
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768422640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.2768422640
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.1980473019
Short name T423
Test name
Test status
Simulation time 198157261 ps
CPU time 3.74 seconds
Started Mar 21 03:24:15 PM PDT 24
Finished Mar 21 03:24:19 PM PDT 24
Peak memory 207140 kb
Host smart-599be47a-6878-4435-8344-0dae09ffc0c7
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980473019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.1980473019
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.288920731
Short name T465
Test name
Test status
Simulation time 106602643 ps
CPU time 2.27 seconds
Started Mar 21 03:24:18 PM PDT 24
Finished Mar 21 03:24:20 PM PDT 24
Peak memory 207228 kb
Host smart-fb8fdd8c-7473-4198-9102-59a2d6430b8d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=288920731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.288920731
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.2344826287
Short name T755
Test name
Test status
Simulation time 38361171 ps
CPU time 2.01 seconds
Started Mar 21 03:24:08 PM PDT 24
Finished Mar 21 03:24:11 PM PDT 24
Peak memory 207588 kb
Host smart-ecf19576-b2ab-4bd0-b0ea-3368a98630be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2344826287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.2344826287
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.1318477810
Short name T535
Test name
Test status
Simulation time 489984603 ps
CPU time 3.86 seconds
Started Mar 21 03:24:08 PM PDT 24
Finished Mar 21 03:24:13 PM PDT 24
Peak memory 207084 kb
Host smart-dc6b68b7-eb0a-40d3-b982-c209aac00864
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318477810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.1318477810
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all_with_rand_reset.1990154718
Short name T153
Test name
Test status
Simulation time 1760534339 ps
CPU time 16.35 seconds
Started Mar 21 03:24:18 PM PDT 24
Finished Mar 21 03:24:34 PM PDT 24
Peak memory 222708 kb
Host smart-d8db9306-4cdb-42dd-8cf3-b70a30b8afa2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1990154718 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all_with_rand_reset.1990154718
Directory /workspace/9.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.170096400
Short name T447
Test name
Test status
Simulation time 364232809 ps
CPU time 8.11 seconds
Started Mar 21 03:24:07 PM PDT 24
Finished Mar 21 03:24:17 PM PDT 24
Peak memory 218760 kb
Host smart-964741b8-a70d-46ec-ab56-0a9a259cca14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=170096400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.170096400
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.1314639981
Short name T48
Test name
Test status
Simulation time 45750577 ps
CPU time 2.23 seconds
Started Mar 21 03:24:18 PM PDT 24
Finished Mar 21 03:24:20 PM PDT 24
Peak memory 210396 kb
Host smart-6e25f909-e6f8-48c7-a483-44a2c7a3539e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314639981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.1314639981
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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