Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
80.58	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	51	0	51	100.00
Crosses	330	74	256	77.58

Variables for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
aes_sl_avail	2	0	2	100.00	100	1	1	2
aes_sl_avail_cp	2	0	2	100.00	100	1	1	2
kmac_sl_avail	2	0	2	100.00	100	1	1	2
kmac_sl_avail_cp	2	0	2	100.00	100	1	1	2
op	5	0	5	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
otbn_sl_avail	2	0	2	100.00	100	1	1	2
otbn_sl_avail_cp	2	0	2	100.00	100	1	1	2
regwen_cp	2	0	2	100.00	100	1	1	2
sideload_clear	8	0	8	100.00	100	1	1	8
sideload_clear_cp	5	0	5	100.00	100	1	1	0
state	7	0	7	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sideload_clear_x_state_op_cross	280	55	225	80.36	100	1	1	0
sideload_clear_x_sl_avail_cross	40	19	21	52.50	100	1	1	0
sideload_clear_x_regwen_cross	10	0	10	100.00	100	1	1	0

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4818

1

T1

12

T2

4

T3

16

auto[1]

520

1

T1

1

T3

3

T5

2

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4818

1

T1

12

T2

4

T3

16

auto[1]

520

1

T1

1

T3

3

T5

2

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4796

1

T1

13

T2

4

T3

16

auto[1]

542

1

T3

3

T5

3

T48

1

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4796

1

T1

13

T2

4

T3

16

auto[1]

542

1

T3

3

T5

3

T48

1

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	404	1			T3	2		T18	1		T5	3
auto[OpGenId]	1111	1			T2	1		T3	7		T4	1
auto[OpGenSwOut]	1153	1			T2	3		T3	5		T4	2
auto[OpGenHwOut]	2594	1			T1	13		T3	5		T4	1
auto[OpDisable]	76	1			T4	1		T5	2		T53	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	404	1			T3	2		T18	1		T5	3
auto[OpGenId]	1111	1			T2	1		T3	7		T4	1
auto[OpGenSwOut]	1153	1			T2	3		T3	5		T4	2
auto[OpGenHwOut]	2594	1			T1	13		T3	5		T4	1
auto[OpDisable]	76	1			T4	1		T5	2		T53	1

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4796

1

T1

13

T2

3

T3

15

auto[1]

542

1

T2

1

T3

4

T19

5

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4796

1

T1

13

T2

3

T3

15

auto[1]

542

1

T2

1

T3

4

T19

5

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5084

1

T1

13

T2

4

T3

19

auto[1]

254

1

T69

3

T226

7

T227

10

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1861	1			T1	2		T2	2		T3	7
auto[1]	668	1			T1	6		T3	1		T4	2
auto[2]	719	1			T1	1		T2	1		T3	4
auto[3]	676	1			T3	3		T4	1		T16	1
auto[4]	340	1			T1	1		T2	1		T3	2
auto[5]	354	1			T1	2		T4	1		T33	1
auto[6]	375	1			T19	1		T5	2		T76	1
auto[7]	345	1			T1	1		T3	2		T16	2

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1414	1			T1	4		T2	1		T3	4
clear_one[1]	668	1			T1	6		T3	1		T4	2
clear_one[2]	719	1			T1	1		T2	1		T3	4
clear_one[3]	676	1			T3	3		T4	1		T16	1
clear_none	1861	1			T1	2		T2	2		T3	7

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1019	1			T1	5		T3	1		T4	2
auto[StInit]	760	1			T1	1		T2	1		T3	3
auto[StCreatorRootKey]	573	1			T1	1		T3	2		T4	1
auto[StOwnerIntKey]	508	1			T1	1		T3	1		T4	1
auto[StOwnerKey]	503	1			T1	1		T2	1		T3	4
auto[StDisabled]	1825	1			T1	4		T2	2		T3	8
auto[StInvalid]	150	1			T14	5		T35	2		T36	4

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1019	1			T1	5		T3	1		T4	2
auto[StInit]	760	1			T1	1		T2	1		T3	3
auto[StCreatorRootKey]	573	1			T1	1		T3	2		T4	1
auto[StOwnerIntKey]	508	1			T1	1		T3	1		T4	1
auto[StOwnerKey]	503	1			T1	1		T2	1		T3	4
auto[StDisabled]	1825	1			T1	4		T2	2		T3	8
auto[StInvalid]	150	1			T14	5		T35	2		T36	4

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	55	225	80.36	55

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	10
[auto[0] - auto[1]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	2
[auto[2] - auto[6]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	5
[auto[2] - auto[6]]	[auto[StReset]]	[auto[OpDisable]]	--	--	5
[auto[2] - auto[6]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	20
[auto[2] - auto[6]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	5
[auto[7]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[7]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[7]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[7]]	[auto[StInvalid]]	[auto[OpAdvance]]	0	1	1
[auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpAdvance]	7	1			T136	1		T138	1		T228	1
auto[0]	auto[StReset]	auto[OpGenId]	170	1			T4	1		T15	1		T5	1
auto[0]	auto[StReset]	auto[OpGenSwOut]	151	1			T15	1		T48	1		T35	1
auto[0]	auto[StReset]	auto[OpGenHwOut]	274	1			T1	1		T3	1		T16	1
auto[0]	auto[StInit]	auto[OpAdvance]	48	1			T18	1		T47	1		T42	1
auto[0]	auto[StInit]	auto[OpGenId]	103	1			T3	2		T18	1		T5	1
auto[0]	auto[StInit]	auto[OpGenSwOut]	114	1			T2	1		T33	1		T5	3
auto[0]	auto[StInit]	auto[OpGenHwOut]	192	1			T14	1		T5	1		T23	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	16	1			T3	1		T47	1		T134	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	47	1			T47	1		T42	2		T6	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	40	1			T3	1		T5	1		T23	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	77	1			T5	1		T128	1		T130	1
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	14	1			T42	1		T229	1		T230	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	31	1			T3	1		T122	1		T58	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	28	1			T5	2		T42	2		T59	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	51	1			T203	1		T68	1		T231	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	13	1			T223	1		T185	4		T232	1
auto[0]	auto[StOwnerKey]	auto[OpGenId]	19	1			T42	1		T134	1		T189	1
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	28	1			T2	1		T47	2		T42	1
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	51	1			T128	1		T47	1		T233	1
auto[0]	auto[StDisabled]	auto[OpAdvance]	23	1			T69	1		T215	1		T234	1
auto[0]	auto[StDisabled]	auto[OpGenId]	60	1			T132	1		T235	1		T236	1
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	66	1			T5	1		T47	1		T42	1
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	167	1			T1	1		T3	1		T19	2
auto[0]	auto[StDisabled]	auto[OpDisable]	29	1			T5	1		T237	1		T42	2
auto[0]	auto[StInvalid]	auto[OpAdvance]	7	1			T41	1		T238	1		T239	1
auto[0]	auto[StInvalid]	auto[OpGenId]	10	1			T14	1		T40	2		T240	1
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	10	1			T14	1		T241	1		T242	2
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	15	1			T36	1		T40	1		T202	1
auto[1]	auto[StReset]	auto[OpAdvance]	1	1			T243	1		-	-		-	-
auto[1]	auto[StReset]	auto[OpGenId]	16	1			T46	1		T59	1		T230	1
auto[1]	auto[StReset]	auto[OpGenSwOut]	22	1			T36	1		T52	1		T210	1
auto[1]	auto[StReset]	auto[OpGenHwOut]	46	1			T1	3		T4	1		T48	1
auto[1]	auto[StInit]	auto[OpAdvance]	3	1			T244	1		T245	1		T246	1
auto[1]	auto[StInit]	auto[OpGenId]	17	1			T18	1		T48	2		T83	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	15	1			T25	1		T53	1		T47	1
auto[1]	auto[StInit]	auto[OpGenHwOut]	26	1			T247	1		T120	1		T244	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T248	1		T249	1		T250	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	8	1			T76	1		T251	1		T136	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	12	1			T52	2		T136	1		T191	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	41	1			T1	1		T19	1		T131	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T215	1		T136	1		T252	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	11	1			T48	1		T188	1		T114	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	14	1			T5	1		T134	2		T111	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	42	1			T19	1		T253	1		T254	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	6	1			T76	1		T52	1		T255	1
auto[1]	auto[StOwnerKey]	auto[OpGenId]	17	1			T7	1		T215	1		T101	1
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	12	1			T248	1		T211	1		T256	1
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	42	1			T48	1		T70	1		T74	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	28	1			T47	1		T42	1		T69	1
auto[1]	auto[StDisabled]	auto[OpGenId]	53	1			T5	1		T47	1		T59	4
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	51	1			T5	1		T48	1		T132	2
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	150	1			T1	2		T3	1		T5	1
auto[1]	auto[StDisabled]	auto[OpDisable]	8	1			T4	1		T134	1		T215	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	3	1			T199	1		T257	1		T258	1
auto[1]	auto[StInvalid]	auto[OpGenId]	6	1			T36	1		T242	1		T259	1
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	2	1			T201	1		T242	1		-	-
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	7	1			T14	1		T238	1		T260	1
auto[2]	auto[StReset]	auto[OpGenId]	22	1			T42	1		T189	1		T261	1
auto[2]	auto[StReset]	auto[OpGenSwOut]	14	1			T47	1		T207	1		T52	1
auto[2]	auto[StReset]	auto[OpGenHwOut]	55	1			T131	2		T47	1		T233	1
auto[2]	auto[StInit]	auto[OpAdvance]	7	1			T7	1		T82	1		T227	1
auto[2]	auto[StInit]	auto[OpGenId]	23	1			T3	1		T25	1		T203	1
auto[2]	auto[StInit]	auto[OpGenSwOut]	12	1			T206	1		T262	1		T252	1
auto[2]	auto[StInit]	auto[OpGenHwOut]	30	1			T1	1		T16	1		T19	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	12	1			T69	1		T137	1		T190	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	11	1			T47	1		T42	1		T263	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	18	1			T97	1		T99	1		T59	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	35	1			T5	1		T119	1		T120	1
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	12	1			T5	1		T227	2		T215	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	16	1			T42	1		T264	2		T265	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	11	1			T42	1		T227	1		T234	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	49	1			T48	1		T204	1		T266	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	12	1			T5	1		T47	1		T211	1
auto[2]	auto[StOwnerKey]	auto[OpGenId]	14	1			T3	1		T42	1		T187	1
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	10	1			T3	1		T53	1		T69	1
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	36	1			T266	1		T120	1		T94	1
auto[2]	auto[StDisabled]	auto[OpAdvance]	14	1			T59	1		T227	1		T215	1
auto[2]	auto[StDisabled]	auto[OpGenId]	47	1			T236	1		T98	1		T100	1
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	60	1			T2	1		T3	1		T5	1
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	170	1			T19	1		T76	1		T128	1
auto[2]	auto[StDisabled]	auto[OpDisable]	8	1			T58	1		T134	1		T267	1
auto[2]	auto[StInvalid]	auto[OpAdvance]	3	1			T199	1		T268	1		T269	1
auto[2]	auto[StInvalid]	auto[OpGenId]	5	1			T14	1		T199	1		T270	1
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	10	1			T41	1		T199	1		T238	1
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	3	1			T201	1		T271	1		T272	1
auto[3]	auto[StReset]	auto[OpGenId]	20	1			T52	1		T97	1		T58	1
auto[3]	auto[StReset]	auto[OpGenSwOut]	19	1			T48	1		T35	1		T36	1
auto[3]	auto[StReset]	auto[OpGenHwOut]	37	1			T196	1		T233	2		T251	1
auto[3]	auto[StInit]	auto[OpAdvance]	5	1			T196	1		T42	1		T137	1
auto[3]	auto[StInit]	auto[OpGenId]	18	1			T82	1		T273	1		T189	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	14	1			T82	1		T274	1		T188	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	26	1			T24	1		T187	1		T52	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	6	1			T122	1		T39	1		T275	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	14	1			T53	1		T211	1		T276	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	15	1			T33	1		T23	1		T277	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	40	1			T5	1		T266	1		T278	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T59	1		T274	1		T279	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	9	1			T52	1		T188	1		T137	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	21	1			T4	1		T47	1		T215	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	31	1			T16	1		T42	1		T56	1
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	10	1			T280	1		T226	1		T274	1
auto[3]	auto[StOwnerKey]	auto[OpGenId]	11	1			T42	1		T281	1		T193	1
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	15	1			T3	1		T42	1		T68	1
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	43	1			T247	1		T119	1		T59	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	21	1			T47	1		T280	1		T251	1
auto[3]	auto[StDisabled]	auto[OpGenId]	38	1			T48	1		T130	1		T47	1
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	60	1			T3	1		T23	1		T47	1
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	159	1			T3	1		T19	1		T53	1
auto[3]	auto[StDisabled]	auto[OpDisable]	15	1			T235	1		T282	1		T43	1
auto[3]	auto[StInvalid]	auto[OpAdvance]	2	1			T201	1		T283	1		-	-
auto[3]	auto[StInvalid]	auto[OpGenId]	3	1			T36	1		T241	1		T284	1
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	9	1			T40	2		T87	1		T270	1
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	11	1			T241	1		T285	2		T286	1
auto[4]	auto[StReset]	auto[OpGenId]	12	1			T48	1		T52	1		T189	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	11	1			T42	1		T52	1		T276	1
auto[4]	auto[StReset]	auto[OpGenHwOut]	23	1			T1	1		T19	2		T278	1
auto[4]	auto[StInit]	auto[OpAdvance]	1	1			T287	1		-	-		-	-
auto[4]	auto[StInit]	auto[OpGenId]	1	1			T78	1		-	-		-	-
auto[4]	auto[StInit]	auto[OpGenSwOut]	7	1			T83	1		T288	1		T289	1
auto[4]	auto[StInit]	auto[OpGenHwOut]	10	1			T24	1		T47	1		T290	1
auto[4]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T5	1		T206	1		T291	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	4	1			T7	1		T58	1		T292	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	7	1			T42	1		T59	1		T43	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	17	1			T74	1		T247	1		T59	1
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	2	1			T293	1		T294	1		-	-
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	8	1			T295	1		T296	2		T297	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	9	1			T187	1		T100	1		T189	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	19	1			T33	1		T128	1		T233	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	2	1			T298	1		T224	1		-	-
auto[4]	auto[StOwnerKey]	auto[OpGenId]	11	1			T134	1		T43	1		T299	1
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	12	1			T196	1		T300	1		T301	1
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	17	1			T204	1		T253	1		T134	1
auto[4]	auto[StDisabled]	auto[OpAdvance]	7	1			T59	1		T301	1		T302	2
auto[4]	auto[StDisabled]	auto[OpGenId]	36	1			T2	1		T3	1		T47	1
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	22	1			T42	1		T59	2		T134	1
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	80	1			T3	1		T128	1		T47	1
auto[4]	auto[StDisabled]	auto[OpDisable]	1	1			T303	1		-	-		-	-
auto[4]	auto[StInvalid]	auto[OpAdvance]	3	1			T284	1		T304	1		T305	1
auto[4]	auto[StInvalid]	auto[OpGenId]	4	1			T41	1		T199	1		T260	1
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	6	1			T35	1		T36	1		T202	1
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	4	1			T14	1		T35	1		T41	1
auto[5]	auto[StReset]	auto[OpGenId]	11	1			T56	1		T206	1		T306	1
auto[5]	auto[StReset]	auto[OpGenSwOut]	7	1			T7	2		T202	1		T89	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	26	1			T131	1		T307	1		T59	1
auto[5]	auto[StInit]	auto[OpAdvance]	7	1			T207	1		T82	1		T197	1
auto[5]	auto[StInit]	auto[OpGenId]	7	1			T25	1		T97	1		T308	1
auto[5]	auto[StInit]	auto[OpGenSwOut]	11	1			T134	1		T84	1		T230	1
auto[5]	auto[StInit]	auto[OpGenHwOut]	11	1			T42	1		T307	1		T244	1
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T189	1		T309	1		T298	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	6	1			T101	1		T310	1		T311	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	4	1			T4	1		T216	1		T219	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	18	1			T23	1		T133	1		T307	1
auto[5]	auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T196	1		T276	1		T63	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	5	1			T312	1		T313	1		T314	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	8	1			T42	1		T315	1		T316	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	18	1			T1	1		T131	1		T132	1
auto[5]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T47	1		T203	1		T191	1
auto[5]	auto[StOwnerKey]	auto[OpGenId]	6	1			T33	1		T59	1		T276	1
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	8	1			T47	1		T236	1		T295	1
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	19	1			T59	1		T317	1		T318	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	13	1			T59	1		T77	1		T319	3
auto[5]	auto[StDisabled]	auto[OpGenId]	26	1			T42	1		T59	1		T135	1
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	32	1			T48	1		T47	1		T124	1
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	80	1			T1	1		T5	1		T204	1
auto[5]	auto[StDisabled]	auto[OpDisable]	8	1			T59	1		T215	1		T320	1
auto[5]	auto[StInvalid]	auto[OpAdvance]	1	1			T271	1		-	-		-	-
auto[5]	auto[StInvalid]	auto[OpGenId]	3	1			T202	1		T259	1		T283	1
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	3	1			T321	1		T258	1		T322	1
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	3	1			T240	1		T286	1		T257	1
auto[6]	auto[StReset]	auto[OpGenId]	11	1			T47	1		T134	2		T306	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	8	1			T76	1		T47	1		T134	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	19	1			T323	2		T324	1		T190	1
auto[6]	auto[StInit]	auto[OpAdvance]	7	1			T52	1		T226	2		T308	1
auto[6]	auto[StInit]	auto[OpGenId]	8	1			T80	1		T83	1		T59	1
auto[6]	auto[StInit]	auto[OpGenSwOut]	11	1			T251	1		T325	1		T313	1
auto[6]	auto[StInit]	auto[OpGenHwOut]	6	1			T43	1		T276	1		T326	1
auto[6]	auto[StCreatorRootKey]	auto[OpAdvance]	5	1			T280	1		T138	1		T327	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	12	1			T42	1		T226	1		T328	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	18	1			T69	1		T329	1		T189	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	30	1			T254	1		T231	1		T330	1
auto[6]	auto[StOwnerIntKey]	auto[OpAdvance]	2	1			T291	1		T331	1		-	-
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	7	1			T226	2		T188	2		T332	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	8	1			T48	1		T47	1		T263	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	31	1			T319	2		T333	1		T43	1
auto[6]	auto[StOwnerKey]	auto[OpAdvance]	3	1			T138	1		T316	1		T334	1
auto[6]	auto[StOwnerKey]	auto[OpGenId]	9	1			T47	1		T52	1		T59	1
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	10	1			T216	1		T335	1		T327	1
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	21	1			T19	1		T59	1		T336	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	10	1			T203	1		T42	1		T43	1
auto[6]	auto[StDisabled]	auto[OpGenId]	29	1			T48	1		T124	1		T215	2
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	24	1			T5	1		T48	1		T42	1
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	72	1			T204	1		T233	1		T42	1
auto[6]	auto[StDisabled]	auto[OpDisable]	5	1			T5	1		T47	1		T58	1
auto[6]	auto[StInvalid]	auto[OpAdvance]	1	1			T40	1		-	-		-	-
auto[6]	auto[StInvalid]	auto[OpGenId]	4	1			T337	1		T238	2		T338	1
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	1	1			T41	1		-	-		-	-
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	3	1			T199	1		T271	1		T304	1
auto[7]	auto[StReset]	auto[OpGenId]	15	1			T16	1		T25	1		T339	1
auto[7]	auto[StReset]	auto[OpGenSwOut]	6	1			T7	1		T226	1		T189	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	16	1			T278	1		T340	1		T341	1
auto[7]	auto[StInit]	auto[OpAdvance]	5	1			T308	1		T197	1		T214	1
auto[7]	auto[StInit]	auto[OpGenId]	3	1			T84	1		T246	1		T342	1
auto[7]	auto[StInit]	auto[OpGenSwOut]	1	1			T343	1		-	-		-	-
auto[7]	auto[StInit]	auto[OpGenHwOut]	11	1			T131	1		T244	1		T39	1
auto[7]	auto[StCreatorRootKey]	auto[OpAdvance]	2	1			T42	1		T218	1		-	-
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	15	1			T16	1		T47	1		T59	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	12	1			T134	1		T344	1		T192	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	20	1			T233	1		T203	1		T345	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T76	1		T228	1		T346	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	5	1			T59	1		T276	1		T347	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	8	1			T59	1		T215	1		T101	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	21	1			T348	1		T323	1		T349	1
auto[7]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T99	1		T230	1		T287	1
auto[7]	auto[StOwnerKey]	auto[OpGenId]	4	1			T3	1		T350	1		T63	1
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	10	1			T42	1		T43	1		T115	1
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	22	1			T1	1		T131	1		T254	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	22	1			T3	1		T315	1		T230	1
auto[7]	auto[StDisabled]	auto[OpGenId]	26	1			T48	1		T68	2		T59	1
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	34	1			T47	1		T42	1		T187	1
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	69	1			T128	1		T233	1		T70	2
auto[7]	auto[StDisabled]	auto[OpDisable]	2	1			T53	1		T65	1		-	-
auto[7]	auto[StInvalid]	auto[OpGenId]	4	1			T337	1		T284	1		T351	1
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	2	1			T284	1		T272	1		-	-
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	2	1			T337	1		T239	1		-	-

---

Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1414

1

T1

4

T2

1

T3

4

clear_one[1]

auto[0]

auto[0]

auto[0]

397

1

T1

6

T4

2

T14

1

clear_one[1]

auto[0]

auto[0]

auto[1]

107

1

T19

2

T5

2

T128

1

clear_one[1]

auto[0]

auto[1]

auto[0]

129

1

T48

1

T132

1

T204

1

clear_one[1]

auto[0]

auto[1]

auto[1]

35

1

T3

1

T5

1

T187

1

clear_one[2]

auto[0]

auto[0]

auto[0]

434

1

T1

1

T3

2

T14

1

clear_one[2]

auto[0]

auto[0]

auto[1]

127

1

T2

1

T3

1

T19

1

clear_one[2]

auto[1]

auto[0]

auto[0]

125

1

T3

1

T48

1

T131

3

clear_one[2]

auto[1]

auto[0]

auto[1]

33

1

T5

1

T59

2

T227

1

clear_one[3]

auto[0]

auto[0]

auto[0]

405

1

T3

1

T4

1

T16

1

clear_one[3]

auto[0]

auto[1]

auto[0]

125

1

T3

1

T5

1

T53

1

clear_one[3]

auto[1]

auto[0]

auto[0]

113

1

T23

1

T130

1

T47

3

clear_one[3]

auto[1]

auto[1]

auto[0]

33

1

T3

1

T7

1

T59

1

clear_none

auto[0]

auto[0]

auto[0]

1349

1

T1

1

T2

2

T3

5

clear_none

auto[0]

auto[0]

auto[1]

139

1

T3

1

T19

2

T128

2

clear_none

auto[0]

auto[1]

auto[0]

124

1

T5

1

T204

1

T253

1

clear_none

auto[0]

auto[1]

auto[1]

33

1

T47

1

T58

1

T77

1

clear_none

auto[1]

auto[0]

auto[0]

115

1

T1

1

T5

1

T130

1

clear_none

auto[1]

auto[0]

auto[1]

38

1

T3

1

T215

1

T229

1

clear_none

auto[1]

auto[1]

auto[0]

33

1

T42

1

T59

1

T352

1

clear_none

auto[1]

auto[1]

auto[1]

30

1

T59

1

T353

1

T134

2

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1316	1			T1	4		T2	1		T3	4
clear_all	auto[1]	98	1			T226	5		T227	1		T319	3
clear_one[1]	auto[0]	641	1			T1	6		T3	1		T4	2
clear_one[1]	auto[1]	27	1			T136	1		T264	3		T138	3
clear_one[2]	auto[0]	680	1			T1	1		T2	1		T3	4
clear_one[2]	auto[1]	39	1			T69	1		T226	2		T227	8
clear_one[3]	auto[0]	640	1			T3	3		T4	1		T16	1
clear_one[3]	auto[1]	36	1			T69	1		T319	7		T135	1
clear_none	auto[0]	1807	1			T1	2		T2	2		T3	7
clear_none	auto[1]	54	1			T69	1		T227	1		T319	1