Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
43.16	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	360	216	144	40.00

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	168	112	40.00	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11716

1

T1

16

T2

5

T3

43

auto[Attestation]

8613

1

T1

4

T2

3

T3

36

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	3054	1			T2	2		T3	7		T4	2
auto[Aes]	3541	1			T1	20		T2	2		T3	14
auto[Kmac]	3596	1			T3	15		T4	2		T14	3
auto[Otbn]	3780	1			T2	1		T3	19		T4	2

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	8216	1			T1	8		T2	8		T3	26
auto[OpGenId]	6358	1			T2	3		T3	24		T4	8
auto[OpGenSwOut]	6383	1			T2	4		T3	27		T4	5
auto[OpGenHwOut]	7588	1			T1	20		T2	1		T3	28
auto[OpDisable]	142	1			T3	2		T4	1		T5	2

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10918

1

T1

8

T2

8

T3

49

auto[OpDoneFail]

17769

1

T1

20

T2

8

T3

58

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6476	1			T1	13		T2	1		T3	8
auto[StInit]	4603	1			T1	2		T2	2		T3	21
auto[StCreatorRootKey]	3269	1			T1	2		T2	2		T3	12
auto[StOwnerIntKey]	2855	1			T1	2		T2	2		T3	18
auto[StOwnerKey]	2496	1			T1	2		T2	2		T3	9
auto[StDisabled]	8065	1			T1	7		T2	7		T3	39
auto[StInvalid]	923	1			T14	20		T35	35		T36	22

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	168	112	40.00	168

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	295	1			T16	1		T18	1		T5	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	113	1			T18	1		T5	1		T24	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	85	1			T4	1		T5	2		T47	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	86	1			T5	1		T23	1		T53	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	59	1			T75	1		T132	2		T42	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	241	1			T2	1		T5	7		T23	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	26	1			T35	1		T36	1		T40	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	290	1			T4	1		T15	1		T16	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	129	1			T2	1		T3	2		T33	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	66	1			T3	1		T15	1		T42	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	64	1			T5	2		T48	1		T47	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	73	1			T2	1		T3	1		T196	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	219	1			T3	3		T5	1		T48	3
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	37	1			T14	1		T35	2		T36	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	300	1			T18	1		T5	2		T46	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	118	1			T33	1		T24	1		T25	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	85	1			T3	1		T4	1		T5	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	76	1			T3	2		T48	2		T47	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	62	1			T3	1		T75	1		T23	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	235	1			T5	3		T76	1		T48	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	30	1			T14	2		T35	1		T36	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	304	1			T16	1		T5	1		T46	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	128	1			T24	1		T48	1		T71	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	97	1			T5	1		T48	1		T42	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	83	1			T5	1		T130	1		T47	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	62	1			T47	1		T42	2		T56	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	212	1			T3	4		T5	7		T76	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	27	1			T14	1		T36	1		T40	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	73	1			T5	2		T35	2		T52	2
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	146	1			T5	4		T25	1		T129	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	91	1			T76	1		T48	1		T133	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	75	1			T5	3		T48	2		T47	4
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	51	1			T33	1		T5	1		T48	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	229	1			T2	1		T3	2		T5	3
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	24	1			T35	2		T40	1		T197	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	87	1			T5	8		T48	1		T36	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	125	1			T3	1		T5	1		T23	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	101	1			T3	1		T14	1		T33	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	74	1			T4	1		T47	1		T198	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	63	1			T48	1		T47	2		T187	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	203	1			T5	1		T75	1		T76	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	27	1			T35	1		T36	1		T199	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	88	1			T5	6		T48	2		T35	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	131	1			T3	2		T4	1		T24	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	78	1			T3	1		T15	1		T16	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	74	1			T3	1		T5	1		T48	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	63	1			T129	1		T47	1		T200	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	225	1			T16	1		T5	3		T75	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	25	1			T35	1		T36	2		T41	4
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	90	1			T5	2		T48	3		T35	3
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	170	1			T14	1		T16	1		T18	3
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	82	1			T3	1		T33	1		T48	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	64	1			T3	1		T5	4		T47	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	63	1			T5	1		T132	1		T47	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	234	1			T3	2		T5	2		T76	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	25	1			T36	1		T40	1		T201	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	286	1			T3	1		T4	1		T18	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	111	1			T3	1		T14	1		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	90	1			T15	1		T5	1		T48	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	61	1			T3	1		T16	1		T33	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	64	1			T33	1		T48	1		T42	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	199	1			T3	1		T16	1		T5	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	36	1			T14	4		T35	1		T40	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	440	1			T1	12		T4	3		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	133	1			T25	1		T130	1		T131	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	96	1			T1	1		T15	1		T131	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	126	1			T3	2		T5	1		T48	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	94	1			T23	1		T53	1		T133	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	278	1			T1	3		T5	2		T75	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	22	1			T35	3		T40	1		T202	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	436	1			T16	2		T5	1		T46	3
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	151	1			T3	1		T5	2		T25	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	128	1			T15	1		T5	1		T42	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	87	1			T3	1		T5	1		T132	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	87	1			T3	1		T48	1		T47	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	281	1			T3	2		T5	3		T48	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	22	1			T35	1		T40	1		T201	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	515	1			T16	1		T18	1		T19	5
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	154	1			T4	1		T5	4		T24	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	105	1			T3	1		T19	1		T47	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	107	1			T3	1		T19	1		T5	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	85	1			T48	1		T128	1		T47	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	289	1			T3	4		T5	1		T128	3
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	38	1			T35	1		T40	1		T41	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	55	1			T7	1		T52	2		T59	3
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	102	1			T3	1		T16	1		T5	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	88	1			T5	1		T48	2		T47	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	84	1			T33	1		T47	1		T68	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	50	1			T53	1		T124	1		T98	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	204	1			T5	4		T76	2		T48	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	30	1			T14	1		T35	1		T36	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	66	1			T5	1		T48	1		T35	3
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	135	1			T1	1		T5	2		T75	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	90	1			T5	2		T130	1		T73	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	98	1			T1	1		T5	1		T47	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	83	1			T1	1		T5	2		T75	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	290	1			T1	1		T3	3		T16	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	32	1			T35	1		T40	1		T41	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	80	1			T5	3		T35	1		T52	5
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	129	1			T33	1		T24	2		T48	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	107	1			T16	1		T5	1		T132	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	94	1			T3	1		T47	1		T203	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	96	1			T133	1		T204	1		T47	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	276	1			T3	1		T16	1		T5	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	32	1			T14	1		T35	1		T36	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	81	1			T5	4		T48	1		T35	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	136	1			T3	1		T4	1		T19	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	131	1			T3	1		T5	1		T23	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	93	1			T3	1		T128	1		T47	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	85	1			T16	1		T19	1		T196	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	295	1			T2	1		T3	2		T19	4
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	25	1			T35	2		T36	1		T41	2

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	220	1			T4	1		T5	3		T23	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	685	1			T2	1		T16	1		T18	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	190	1			T2	1		T3	2		T15	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	688	1			T2	1		T3	5		T4	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	214	1			T3	4		T4	1		T5	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	692	1			T14	2		T18	1		T33	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	224	1			T5	2		T48	1		T130	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	689	1			T3	4		T14	1		T16	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	204	1			T33	1		T5	4		T76	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	485	1			T2	1		T3	2		T5	9
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	221	1			T3	1		T4	1		T33	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	459	1			T3	1		T14	1		T5	10
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	205	1			T3	2		T15	1		T16	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	479	1			T3	2		T4	1		T16	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	193	1			T3	2		T33	1		T5	5
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	535	1			T3	2		T14	1		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	198	1			T3	1		T15	1		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	649	1			T3	3		T4	1		T14	5
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	301	1			T1	1		T3	2		T15	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	888	1			T1	15		T4	3		T16	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	293	1			T3	2		T15	1		T5	2
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	899	1			T3	3		T16	2		T5	6
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	279	1			T3	2		T19	2		T5	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	1014	1			T3	4		T4	1		T16	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	215	1			T33	1		T5	1		T48	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	398	1			T3	1		T14	1		T16	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	265	1			T1	2		T5	5		T75	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	529	1			T1	2		T3	3		T16	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	282	1			T3	1		T16	1		T5	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	532	1			T3	1		T14	1		T16	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	297	1			T3	2		T16	1		T19	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	549	1			T2	1		T3	3		T4	1