Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

32897

1

T1

31

T2

21

T3

122

auto[1]

275

1

T69

3

T226

8

T227

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	32900	1			T1	31		T2	21		T3	122
auto[134217728:268435455]	6	1			T226	1		T136	1		T138	1
auto[268435456:402653183]	9	1			T226	1		T136	1		T252	1
auto[402653184:536870911]	12	1			T69	1		T234	1		T135	1
auto[536870912:671088639]	7	1			T319	1		T234	1		T138	1
auto[671088640:805306367]	7	1			T226	1		T264	1		T262	1
auto[805306368:939524095]	10	1			T135	1		T228	1		T327	1
auto[939524096:1073741823]	7	1			T328	2		T252	1		T365	1
auto[1073741824:1207959551]	7	1			T319	2		T252	1		T243	1
auto[1207959552:1342177279]	10	1			T319	1		T228	2		T252	1
auto[1342177280:1476395007]	7	1			T264	1		T252	1		T185	1
auto[1476395008:1610612735]	12	1			T227	1		T319	1		T340	1
auto[1610612736:1744830463]	8	1			T135	1		T340	1		T228	1
auto[1744830464:1879048191]	7	1			T365	1		T296	2		T245	1
auto[1879048192:2013265919]	6	1			T375	1		T376	1		T342	1
auto[2013265920:2147483647]	9	1			T135	1		T262	1		T252	1
auto[2147483648:2281701375]	4	1			T226	1		T340	1		T262	1
auto[2281701376:2415919103]	5	1			T264	1		T302	1		T365	1
auto[2415919104:2550136831]	13	1			T69	1		T226	1		T234	1
auto[2550136832:2684354559]	12	1			T319	1		T136	1		T340	1
auto[2684354560:2818572287]	12	1			T69	1		T138	1		T252	1
auto[2818572288:2952790015]	11	1			T226	1		T228	1		T185	2
auto[2952790016:3087007743]	11	1			T262	1		T252	2		T365	1
auto[3087007744:3221225471]	11	1			T226	1		T234	1		T262	1
auto[3221225472:3355443199]	5	1			T135	1		T136	1		T302	1
auto[3355443200:3489660927]	8	1			T138	1		T228	1		T252	1
auto[3489660928:3623878655]	10	1			T138	1		T328	1		T364	1
auto[3623878656:3758096383]	6	1			T328	1		T228	1		T252	1
auto[3758096384:3892314111]	5	1			T138	1		T296	1		T375	1
auto[3892314112:4026531839]	14	1			T226	1		T319	1		T136	1
auto[4026531840:4160749567]	11	1			T319	1		T135	1		T136	1
auto[4160749568:4294967295]	10	1			T227	1		T136	1		T138	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	32897	1			T1	31		T2	21		T3	122
auto[0:134217727]	auto[1]	3	1			T227	1		T365	1		T377	1
auto[134217728:268435455]	auto[1]	6	1			T226	1		T136	1		T138	1
auto[268435456:402653183]	auto[1]	9	1			T226	1		T136	1		T252	1
auto[402653184:536870911]	auto[1]	12	1			T69	1		T234	1		T135	1
auto[536870912:671088639]	auto[1]	7	1			T319	1		T234	1		T138	1
auto[671088640:805306367]	auto[1]	7	1			T226	1		T264	1		T262	1
auto[805306368:939524095]	auto[1]	10	1			T135	1		T228	1		T327	1
auto[939524096:1073741823]	auto[1]	7	1			T328	2		T252	1		T365	1
auto[1073741824:1207959551]	auto[1]	7	1			T319	2		T252	1		T243	1
auto[1207959552:1342177279]	auto[1]	10	1			T319	1		T228	2		T252	1
auto[1342177280:1476395007]	auto[1]	7	1			T264	1		T252	1		T185	1
auto[1476395008:1610612735]	auto[1]	12	1			T227	1		T319	1		T340	1
auto[1610612736:1744830463]	auto[1]	8	1			T135	1		T340	1		T228	1
auto[1744830464:1879048191]	auto[1]	7	1			T365	1		T296	2		T245	1
auto[1879048192:2013265919]	auto[1]	6	1			T375	1		T376	1		T342	1
auto[2013265920:2147483647]	auto[1]	9	1			T135	1		T262	1		T252	1
auto[2147483648:2281701375]	auto[1]	4	1			T226	1		T340	1		T262	1
auto[2281701376:2415919103]	auto[1]	5	1			T264	1		T302	1		T365	1
auto[2415919104:2550136831]	auto[1]	13	1			T69	1		T226	1		T234	1
auto[2550136832:2684354559]	auto[1]	12	1			T319	1		T136	1		T340	1
auto[2684354560:2818572287]	auto[1]	12	1			T69	1		T138	1		T252	1
auto[2818572288:2952790015]	auto[1]	11	1			T226	1		T228	1		T185	2
auto[2952790016:3087007743]	auto[1]	11	1			T262	1		T252	2		T365	1
auto[3087007744:3221225471]	auto[1]	11	1			T226	1		T234	1		T262	1
auto[3221225472:3355443199]	auto[1]	5	1			T135	1		T136	1		T302	1
auto[3355443200:3489660927]	auto[1]	8	1			T138	1		T228	1		T252	1
auto[3489660928:3623878655]	auto[1]	10	1			T138	1		T328	1		T364	1
auto[3623878656:3758096383]	auto[1]	6	1			T328	1		T228	1		T252	1
auto[3758096384:3892314111]	auto[1]	5	1			T138	1		T296	1		T375	1
auto[3892314112:4026531839]	auto[1]	14	1			T226	1		T319	1		T136	1
auto[4026531840:4160749567]	auto[1]	11	1			T319	1		T135	1		T136	1
auto[4160749568:4294967295]	auto[1]	10	1			T227	1		T136	1		T138	2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1668

1

T3

7

T4

1

T14

3

auto[1]

1812

1

T3

14

T4

3

T14

1

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	99	1			T4	1		T33	1		T5	1
auto[134217728:268435455]	118	1			T3	1		T35	1		T47	2
auto[268435456:402653183]	110	1			T24	1		T48	1		T28	1
auto[402653184:536870911]	98	1			T14	1		T5	2		T47	1
auto[536870912:671088639]	113	1			T14	1		T33	1		T5	2
auto[671088640:805306367]	100	1			T3	1		T5	4		T25	1
auto[805306368:939524095]	127	1			T3	1		T47	1		T196	1
auto[939524096:1073741823]	113	1			T5	1		T24	1		T25	1
auto[1073741824:1207959551]	115	1			T18	1		T5	2		T76	1
auto[1207959552:1342177279]	117	1			T3	5		T5	1		T48	1
auto[1342177280:1476395007]	128	1			T5	6		T47	2		T196	2
auto[1476395008:1610612735]	123	1			T33	1		T5	1		T48	2
auto[1610612736:1744830463]	96	1			T4	1		T15	1		T5	2
auto[1744830464:1879048191]	99	1			T3	1		T5	3		T46	1
auto[1879048192:2013265919]	109	1			T3	1		T18	1		T5	4
auto[2013265920:2147483647]	119	1			T16	2		T132	1		T47	3
auto[2147483648:2281701375]	104	1			T14	1		T48	1		T133	1
auto[2281701376:2415919103]	89	1			T3	3		T16	1		T33	2
auto[2415919104:2550136831]	129	1			T18	1		T5	2		T76	1
auto[2550136832:2684354559]	86	1			T5	3		T75	1		T47	2
auto[2684354560:2818572287]	102	1			T3	1		T4	1		T5	1
auto[2818572288:2952790015]	116	1			T3	1		T18	1		T5	3
auto[2952790016:3087007743]	111	1			T3	1		T5	2		T25	1
auto[3087007744:3221225471]	90	1			T5	1		T76	1		T48	1
auto[3221225472:3355443199]	110	1			T3	1		T18	1		T76	1
auto[3355443200:3489660927]	109	1			T5	2		T48	1		T40	1
auto[3489660928:3623878655]	114	1			T14	1		T33	1		T5	1
auto[3623878656:3758096383]	113	1			T3	1		T16	1		T5	3
auto[3758096384:3892314111]	97	1			T4	1		T24	1		T47	2
auto[3892314112:4026531839]	97	1			T3	2		T5	3		T46	1
auto[4026531840:4160749567]	115	1			T3	1		T18	1		T5	1
auto[4160749568:4294967295]	114	1			T5	2		T53	1		T133	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	48	1			T4	1		T47	1		T196	1
auto[0:134217727]	auto[1]	51	1			T33	1		T5	1		T47	2
auto[134217728:268435455]	auto[0]	48	1			T35	1		T47	1		T207	1
auto[134217728:268435455]	auto[1]	70	1			T3	1		T47	1		T42	1
auto[268435456:402653183]	auto[0]	56	1			T24	1		T35	1		T47	2
auto[268435456:402653183]	auto[1]	54	1			T48	1		T28	1		T47	3
auto[402653184:536870911]	auto[0]	51	1			T5	1		T47	1		T42	1
auto[402653184:536870911]	auto[1]	47	1			T14	1		T5	1		T42	1
auto[536870912:671088639]	auto[0]	63	1			T14	1		T5	2		T132	1
auto[536870912:671088639]	auto[1]	50	1			T33	1		T75	1		T53	1
auto[671088640:805306367]	auto[0]	44	1			T3	1		T5	2		T25	1
auto[671088640:805306367]	auto[1]	56	1			T5	2		T53	1		T203	1
auto[805306368:939524095]	auto[0]	60	1			T80	1		T42	3		T371	1
auto[805306368:939524095]	auto[1]	67	1			T3	1		T47	1		T196	1
auto[939524096:1073741823]	auto[0]	57	1			T5	1		T24	1		T25	1
auto[939524096:1073741823]	auto[1]	56	1			T47	4		T42	1		T58	2
auto[1073741824:1207959551]	auto[0]	49	1			T5	1		T48	1		T35	1
auto[1073741824:1207959551]	auto[1]	66	1			T18	1		T5	1		T76	1
auto[1207959552:1342177279]	auto[0]	57	1			T3	2		T5	1		T48	1
auto[1207959552:1342177279]	auto[1]	60	1			T3	3		T80	1		T371	1
auto[1342177280:1476395007]	auto[0]	74	1			T5	6		T47	1		T196	1
auto[1342177280:1476395007]	auto[1]	54	1			T47	1		T196	1		T42	1
auto[1476395008:1610612735]	auto[0]	65	1			T33	1		T25	1		T42	1
auto[1476395008:1610612735]	auto[1]	58	1			T5	1		T48	2		T35	1
auto[1610612736:1744830463]	auto[0]	42	1			T5	1		T25	1		T42	1
auto[1610612736:1744830463]	auto[1]	54	1			T4	1		T15	1		T5	1
auto[1744830464:1879048191]	auto[0]	57	1			T5	1		T48	1		T35	1
auto[1744830464:1879048191]	auto[1]	42	1			T3	1		T5	2		T46	1
auto[1879048192:2013265919]	auto[0]	45	1			T18	1		T5	1		T47	1
auto[1879048192:2013265919]	auto[1]	64	1			T3	1		T5	3		T75	1
auto[2013265920:2147483647]	auto[0]	53	1			T132	1		T47	1		T7	1
auto[2013265920:2147483647]	auto[1]	66	1			T16	2		T47	2		T40	1
auto[2147483648:2281701375]	auto[0]	44	1			T14	1		T48	1		T207	1
auto[2147483648:2281701375]	auto[1]	60	1			T133	1		T47	1		T40	1
auto[2281701376:2415919103]	auto[0]	26	1			T5	1		T48	1		T59	2
auto[2281701376:2415919103]	auto[1]	63	1			T3	3		T16	1		T33	2
auto[2415919104:2550136831]	auto[0]	60	1			T47	1		T187	1		T280	1
auto[2415919104:2550136831]	auto[1]	69	1			T18	1		T5	2		T76	1
auto[2550136832:2684354559]	auto[0]	38	1			T47	1		T280	1		T7	2
auto[2550136832:2684354559]	auto[1]	48	1			T5	3		T75	1		T47	1
auto[2684354560:2818572287]	auto[0]	54	1			T5	1		T24	2		T29	1
auto[2684354560:2818572287]	auto[1]	48	1			T3	1		T4	1		T42	1
auto[2818572288:2952790015]	auto[0]	55	1			T3	1		T5	1		T29	1
auto[2818572288:2952790015]	auto[1]	61	1			T18	1		T5	2		T46	1
auto[2952790016:3087007743]	auto[0]	51	1			T25	1		T35	1		T47	1
auto[2952790016:3087007743]	auto[1]	60	1			T3	1		T5	2		T133	1
auto[3087007744:3221225471]	auto[0]	46	1			T5	1		T48	1		T47	1
auto[3087007744:3221225471]	auto[1]	44	1			T76	1		T73	1		T251	1
auto[3221225472:3355443199]	auto[0]	47	1			T18	1		T76	1		T35	1
auto[3221225472:3355443199]	auto[1]	63	1			T3	1		T133	1		T35	1
auto[3355443200:3489660927]	auto[0]	49	1			T5	1		T42	2		T41	1
auto[3355443200:3489660927]	auto[1]	60	1			T5	1		T48	1		T40	1
auto[3489660928:3623878655]	auto[0]	61	1			T14	1		T33	1		T35	1
auto[3489660928:3623878655]	auto[1]	53	1			T5	1		T47	1		T203	1
auto[3623878656:3758096383]	auto[0]	55	1			T3	1		T16	1		T5	1
auto[3623878656:3758096383]	auto[1]	58	1			T5	2		T23	1		T42	2
auto[3758096384:3892314111]	auto[0]	46	1			T24	1		T47	1		T42	1
auto[3758096384:3892314111]	auto[1]	51	1			T4	1		T47	1		T187	1
auto[3892314112:4026531839]	auto[0]	54	1			T3	2		T5	1		T132	1
auto[3892314112:4026531839]	auto[1]	43	1			T5	2		T46	1		T48	1
auto[4026531840:4160749567]	auto[0]	58	1			T18	1		T5	1		T75	1
auto[4026531840:4160749567]	auto[1]	57	1			T3	1		T76	1		T47	1
auto[4160749568:4294967295]	auto[0]	55	1			T5	2		T53	1		T196	1
auto[4160749568:4294967295]	auto[1]	59	1			T133	1		T28	1		T47	2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1661

1

T3

10

T4

1

T14

2

auto[1]

1819

1

T3

11

T4

3

T14

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	106	1			T5	2		T53	1		T203	1
auto[134217728:268435455]	97	1			T33	1		T5	2		T42	1
auto[268435456:402653183]	124	1			T3	2		T5	3		T76	1
auto[402653184:536870911]	110	1			T4	1		T5	2		T48	1
auto[536870912:671088639]	106	1			T4	1		T18	1		T5	2
auto[671088640:805306367]	114	1			T33	1		T29	1		T47	1
auto[805306368:939524095]	106	1			T33	2		T47	3		T203	1
auto[939524096:1073741823]	117	1			T3	1		T14	1		T5	1
auto[1073741824:1207959551]	128	1			T3	1		T4	1		T25	1
auto[1207959552:1342177279]	101	1			T3	1		T18	1		T5	2
auto[1342177280:1476395007]	109	1			T18	1		T23	1		T132	1
auto[1476395008:1610612735]	116	1			T5	3		T75	1		T48	1
auto[1610612736:1744830463]	108	1			T16	1		T5	3		T46	1
auto[1744830464:1879048191]	113	1			T5	2		T75	1		T46	1
auto[1879048192:2013265919]	112	1			T5	2		T132	1		T133	1
auto[2013265920:2147483647]	108	1			T3	1		T16	2		T5	4
auto[2147483648:2281701375]	115	1			T3	2		T23	1		T76	1
auto[2281701376:2415919103]	108	1			T5	2		T35	1		T47	1
auto[2415919104:2550136831]	115	1			T3	1		T18	1		T5	3
auto[2550136832:2684354559]	113	1			T3	2		T16	1		T18	1
auto[2684354560:2818572287]	95	1			T3	2		T4	1		T5	3
auto[2818572288:2952790015]	116	1			T5	2		T46	1		T47	1
auto[2952790016:3087007743]	102	1			T3	2		T14	1		T5	1
auto[3087007744:3221225471]	115	1			T5	1		T24	1		T53	1
auto[3221225472:3355443199]	91	1			T3	1		T15	1		T18	1
auto[3355443200:3489660927]	97	1			T3	1		T5	3		T48	1
auto[3489660928:3623878655]	104	1			T3	1		T5	1		T25	1
auto[3623878656:3758096383]	95	1			T3	1		T5	1		T24	1
auto[3758096384:3892314111]	103	1			T3	1		T33	1		T5	2
auto[3892314112:4026531839]	107	1			T14	2		T5	2		T76	1
auto[4026531840:4160749567]	122	1			T3	1		T35	1		T47	1
auto[4160749568:4294967295]	107	1			T75	1		T35	1		T47	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	47	1			T371	1		T59	2		T134	1
auto[0:134217727]	auto[1]	59	1			T5	2		T53	1		T203	1
auto[134217728:268435455]	auto[0]	41	1			T5	1		T42	1		T371	1
auto[134217728:268435455]	auto[1]	56	1			T33	1		T5	1		T371	1
auto[268435456:402653183]	auto[0]	67	1			T5	2		T48	1		T47	1
auto[268435456:402653183]	auto[1]	57	1			T3	2		T5	1		T76	1
auto[402653184:536870911]	auto[0]	53	1			T48	1		T25	1		T35	1
auto[402653184:536870911]	auto[1]	57	1			T4	1		T5	2		T47	1
auto[536870912:671088639]	auto[0]	44	1			T18	1		T36	1		T52	1
auto[536870912:671088639]	auto[1]	62	1			T4	1		T5	2		T48	1
auto[671088640:805306367]	auto[0]	55	1			T47	1		T36	3		T42	3
auto[671088640:805306367]	auto[1]	59	1			T33	1		T29	1		T42	1
auto[805306368:939524095]	auto[0]	52	1			T33	1		T47	2		T42	1
auto[805306368:939524095]	auto[1]	54	1			T33	1		T47	1		T203	1
auto[939524096:1073741823]	auto[0]	52	1			T3	1		T14	1		T5	1
auto[939524096:1073741823]	auto[1]	65	1			T133	1		T28	1		T47	1
auto[1073741824:1207959551]	auto[0]	62	1			T25	1		T47	1		T42	1
auto[1073741824:1207959551]	auto[1]	66	1			T3	1		T4	1		T35	1
auto[1207959552:1342177279]	auto[0]	52	1			T3	1		T5	2		T48	1
auto[1207959552:1342177279]	auto[1]	49	1			T18	1		T47	1		T6	1
auto[1342177280:1476395007]	auto[0]	57	1			T18	1		T132	1		T36	1
auto[1342177280:1476395007]	auto[1]	52	1			T23	1		T47	3		T36	1
auto[1476395008:1610612735]	auto[0]	52	1			T5	2		T25	1		T47	2
auto[1476395008:1610612735]	auto[1]	64	1			T5	1		T75	1		T48	1
auto[1610612736:1744830463]	auto[0]	54	1			T5	2		T47	1		T196	1
auto[1610612736:1744830463]	auto[1]	54	1			T16	1		T5	1		T46	1
auto[1744830464:1879048191]	auto[0]	51	1			T5	2		T25	1		T35	1
auto[1744830464:1879048191]	auto[1]	62	1			T75	1		T46	1		T48	3
auto[1879048192:2013265919]	auto[0]	48	1			T5	1		T132	1		T47	1
auto[1879048192:2013265919]	auto[1]	64	1			T5	1		T133	1		T42	2
auto[2013265920:2147483647]	auto[0]	58	1			T3	1		T16	1		T24	1
auto[2013265920:2147483647]	auto[1]	50	1			T16	1		T5	4		T133	1
auto[2147483648:2281701375]	auto[0]	57	1			T76	1		T29	1		T207	1
auto[2147483648:2281701375]	auto[1]	58	1			T3	2		T23	1		T47	1
auto[2281701376:2415919103]	auto[0]	45	1			T5	1		T47	1		T42	1
auto[2281701376:2415919103]	auto[1]	63	1			T5	1		T35	1		T36	1
auto[2415919104:2550136831]	auto[0]	52	1			T3	1		T18	1		T5	1
auto[2415919104:2550136831]	auto[1]	63	1			T5	2		T133	1		T47	1
auto[2550136832:2684354559]	auto[0]	57	1			T3	2		T33	1		T5	3
auto[2550136832:2684354559]	auto[1]	56	1			T16	1		T18	1		T5	1
auto[2684354560:2818572287]	auto[0]	48	1			T3	1		T4	1		T5	1
auto[2684354560:2818572287]	auto[1]	47	1			T3	1		T5	2		T48	1
auto[2818572288:2952790015]	auto[0]	52	1			T5	1		T71	1		T97	1
auto[2818572288:2952790015]	auto[1]	64	1			T5	1		T46	1		T47	1
auto[2952790016:3087007743]	auto[0]	47	1			T3	1		T5	1		T75	1
auto[2952790016:3087007743]	auto[1]	55	1			T3	1		T14	1		T76	1
auto[3087007744:3221225471]	auto[0]	57	1			T24	1		T47	1		T71	1
auto[3087007744:3221225471]	auto[1]	58	1			T5	1		T53	1		T47	1
auto[3221225472:3355443199]	auto[0]	40	1			T207	1		T71	1		T187	1
auto[3221225472:3355443199]	auto[1]	51	1			T3	1		T15	1		T18	1
auto[3355443200:3489660927]	auto[0]	46	1			T5	1		T47	1		T207	1
auto[3355443200:3489660927]	auto[1]	51	1			T3	1		T5	2		T48	1
auto[3489660928:3623878655]	auto[0]	49	1			T5	1		T25	1		T42	2
auto[3489660928:3623878655]	auto[1]	55	1			T3	1		T28	1		T47	1
auto[3623878656:3758096383]	auto[0]	47	1			T3	1		T24	1		T48	1
auto[3623878656:3758096383]	auto[1]	48	1			T5	1		T132	1		T47	1
auto[3758096384:3892314111]	auto[0]	49	1			T5	2		T76	1		T35	1
auto[3758096384:3892314111]	auto[1]	54	1			T3	1		T33	1		T47	2
auto[3892314112:4026531839]	auto[0]	63	1			T14	1		T76	1		T47	2
auto[3892314112:4026531839]	auto[1]	44	1			T14	1		T5	2		T35	1
auto[4026531840:4160749567]	auto[0]	61	1			T3	1		T196	1		T205	1
auto[4026531840:4160749567]	auto[1]	61	1			T35	1		T47	1		T56	1
auto[4160749568:4294967295]	auto[0]	46	1			T75	1		T35	1		T207	1
auto[4160749568:4294967295]	auto[1]	61	1			T47	2		T203	1		T42	4

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1670

1

T3

9

T4

1

T14

2

auto[1]

1810

1

T3

12

T4

3

T14

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	100	1			T4	1		T18	1		T5	5
auto[134217728:268435455]	119	1			T5	1		T24	1		T76	2
auto[268435456:402653183]	103	1			T14	1		T33	1		T5	3
auto[402653184:536870911]	119	1			T5	3		T46	1		T48	1
auto[536870912:671088639]	110	1			T3	1		T33	1		T75	1
auto[671088640:805306367]	95	1			T3	1		T4	1		T18	1
auto[805306368:939524095]	130	1			T3	1		T18	1		T5	1
auto[939524096:1073741823]	118	1			T3	3		T33	1		T5	1
auto[1073741824:1207959551]	98	1			T47	1		T36	1		T42	5
auto[1207959552:1342177279]	103	1			T14	1		T15	1		T18	1
auto[1342177280:1476395007]	101	1			T3	1		T5	2		T28	1
auto[1476395008:1610612735]	100	1			T3	1		T14	1		T5	2
auto[1610612736:1744830463]	119	1			T3	1		T5	1		T24	1
auto[1744830464:1879048191]	108	1			T3	2		T33	1		T5	1
auto[1879048192:2013265919]	136	1			T3	2		T14	1		T5	2
auto[2013265920:2147483647]	92	1			T133	1		T35	1		T47	2
auto[2147483648:2281701375]	119	1			T3	1		T16	1		T5	1
auto[2281701376:2415919103]	120	1			T3	1		T5	4		T48	1
auto[2415919104:2550136831]	104	1			T3	1		T16	1		T5	2
auto[2550136832:2684354559]	111	1			T3	1		T5	4		T29	1
auto[2684354560:2818572287]	106	1			T33	1		T5	3		T47	2
auto[2818572288:2952790015]	124	1			T3	1		T4	1		T5	1
auto[2952790016:3087007743]	116	1			T4	1		T33	1		T5	1
auto[3087007744:3221225471]	109	1			T18	1		T5	2		T24	1
auto[3221225472:3355443199]	116	1			T16	1		T5	1		T133	1
auto[3355443200:3489660927]	115	1			T3	1		T5	1		T48	1
auto[3489660928:3623878655]	89	1			T16	1		T25	1		T35	1
auto[3623878656:3758096383]	100	1			T18	1		T5	4		T46	1
auto[3758096384:3892314111]	97	1			T3	1		T5	1		T48	2
auto[3892314112:4026531839]	113	1			T5	1		T53	1		T132	1
auto[4026531840:4160749567]	100	1			T5	1		T48	1		T47	1
auto[4160749568:4294967295]	90	1			T3	1		T5	2		T29	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	51	1			T4	1		T18	1		T5	3
auto[0:134217727]	auto[1]	49	1			T5	2		T187	1		T7	1
auto[134217728:268435455]	auto[0]	59	1			T5	1		T24	1		T76	2
auto[134217728:268435455]	auto[1]	60	1			T47	2		T280	1		T7	1
auto[268435456:402653183]	auto[0]	47	1			T14	1		T5	1		T48	1
auto[268435456:402653183]	auto[1]	56	1			T33	1		T5	2		T36	1
auto[402653184:536870911]	auto[0]	65	1			T5	2		T48	1		T132	1
auto[402653184:536870911]	auto[1]	54	1			T5	1		T46	1		T40	1
auto[536870912:671088639]	auto[0]	60	1			T33	1		T48	1		T47	3
auto[536870912:671088639]	auto[1]	50	1			T3	1		T75	1		T23	1
auto[671088640:805306367]	auto[0]	49	1			T18	1		T5	1		T25	1
auto[671088640:805306367]	auto[1]	46	1			T3	1		T4	1		T5	2
auto[805306368:939524095]	auto[0]	60	1			T3	1		T48	1		T47	1
auto[805306368:939524095]	auto[1]	70	1			T18	1		T5	1		T75	1
auto[939524096:1073741823]	auto[0]	57	1			T3	2		T25	1		T47	1
auto[939524096:1073741823]	auto[1]	61	1			T3	1		T33	1		T5	1
auto[1073741824:1207959551]	auto[0]	35	1			T36	1		T42	2		T82	2
auto[1073741824:1207959551]	auto[1]	63	1			T47	1		T42	3		T244	1
auto[1207959552:1342177279]	auto[0]	50	1			T75	1		T53	1		T42	1
auto[1207959552:1342177279]	auto[1]	53	1			T14	1		T15	1		T18	1
auto[1342177280:1476395007]	auto[0]	47	1			T5	2		T80	1		T42	4
auto[1342177280:1476395007]	auto[1]	54	1			T3	1		T28	1		T47	1
auto[1476395008:1610612735]	auto[0]	54	1			T5	1		T47	1		T36	1
auto[1476395008:1610612735]	auto[1]	46	1			T3	1		T14	1		T5	1
auto[1610612736:1744830463]	auto[0]	45	1			T24	1		T42	1		T187	1
auto[1610612736:1744830463]	auto[1]	74	1			T3	1		T5	1		T47	3
auto[1744830464:1879048191]	auto[0]	57	1			T5	1		T25	1		T47	1
auto[1744830464:1879048191]	auto[1]	51	1			T3	2		T33	1		T75	1
auto[1879048192:2013265919]	auto[0]	67	1			T3	1		T14	1		T5	1
auto[1879048192:2013265919]	auto[1]	69	1			T3	1		T5	1		T58	1
auto[2013265920:2147483647]	auto[0]	39	1			T47	1		T7	1		T58	1
auto[2013265920:2147483647]	auto[1]	53	1			T133	1		T35	1		T47	1
auto[2147483648:2281701375]	auto[0]	62	1			T5	1		T76	1		T48	1
auto[2147483648:2281701375]	auto[1]	57	1			T3	1		T16	1		T133	1
auto[2281701376:2415919103]	auto[0]	53	1			T5	2		T48	1		T132	1
auto[2281701376:2415919103]	auto[1]	67	1			T3	1		T5	2		T47	2
auto[2415919104:2550136831]	auto[0]	47	1			T3	1		T47	1		T71	1
auto[2415919104:2550136831]	auto[1]	57	1			T16	1		T5	2		T47	1
auto[2550136832:2684354559]	auto[0]	58	1			T3	1		T5	3		T47	1
auto[2550136832:2684354559]	auto[1]	53	1			T5	1		T29	1		T47	1
auto[2684354560:2818572287]	auto[0]	52	1			T33	1		T5	1		T47	2
auto[2684354560:2818572287]	auto[1]	54	1			T5	2		T196	1		T42	2
auto[2818572288:2952790015]	auto[0]	57	1			T80	1		T42	1		T71	1
auto[2818572288:2952790015]	auto[1]	67	1			T3	1		T4	1		T5	1
auto[2952790016:3087007743]	auto[0]	64	1			T33	1		T5	1		T24	1
auto[2952790016:3087007743]	auto[1]	52	1			T4	1		T76	1		T48	2
auto[3087007744:3221225471]	auto[0]	52	1			T18	1		T24	1		T25	1
auto[3087007744:3221225471]	auto[1]	57	1			T5	2		T47	3		T42	1
auto[3221225472:3355443199]	auto[0]	53	1			T5	1		T35	2		T47	1
auto[3221225472:3355443199]	auto[1]	63	1			T16	1		T133	1		T40	1
auto[3355443200:3489660927]	auto[0]	56	1			T3	1		T5	1		T48	1
auto[3355443200:3489660927]	auto[1]	59	1			T47	1		T7	1		T58	1
auto[3489660928:3623878655]	auto[0]	48	1			T16	1		T25	1		T42	1
auto[3489660928:3623878655]	auto[1]	41	1			T35	1		T280	1		T7	2
auto[3623878656:3758096383]	auto[0]	52	1			T5	3		T48	1		T47	2
auto[3623878656:3758096383]	auto[1]	48	1			T18	1		T5	1		T46	1
auto[3758096384:3892314111]	auto[0]	49	1			T3	1		T48	1		T280	1
auto[3758096384:3892314111]	auto[1]	48	1			T5	1		T48	1		T47	2
auto[3892314112:4026531839]	auto[0]	44	1			T5	1		T132	1		T47	1
auto[3892314112:4026531839]	auto[1]	69	1			T53	1		T35	1		T47	2
auto[4026531840:4160749567]	auto[0]	37	1			T47	1		T207	1		T42	1
auto[4026531840:4160749567]	auto[1]	63	1			T5	1		T48	1		T42	3
auto[4160749568:4294967295]	auto[0]	44	1			T3	1		T29	1		T7	1
auto[4160749568:4294967295]	auto[1]	46	1			T5	2		T47	2		T73	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1667

1

T3

7

T4

1

T14

1

auto[1]

1813

1

T3

14

T4

3

T14

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	124	1			T3	1		T5	1		T48	2
auto[134217728:268435455]	118	1			T47	2		T196	1		T42	3
auto[268435456:402653183]	99	1			T3	1		T5	1		T76	1
auto[402653184:536870911]	121	1			T4	1		T5	2		T23	1
auto[536870912:671088639]	101	1			T76	1		T48	1		T47	2
auto[671088640:805306367]	117	1			T3	1		T5	2		T24	1
auto[805306368:939524095]	108	1			T3	1		T14	1		T15	1
auto[939524096:1073741823]	121	1			T3	1		T14	1		T5	6
auto[1073741824:1207959551]	108	1			T5	3		T47	2		T42	2
auto[1207959552:1342177279]	127	1			T18	1		T5	1		T47	1
auto[1342177280:1476395007]	97	1			T3	1		T5	2		T76	1
auto[1476395008:1610612735]	108	1			T3	1		T4	1		T48	2
auto[1610612736:1744830463]	95	1			T5	2		T47	3		T56	1
auto[1744830464:1879048191]	113	1			T3	1		T5	2		T75	1
auto[1879048192:2013265919]	106	1			T16	1		T18	1		T33	1
auto[2013265920:2147483647]	108	1			T4	1		T5	5		T53	1
auto[2147483648:2281701375]	107	1			T5	1		T75	1		T48	1
auto[2281701376:2415919103]	94	1			T18	1		T5	1		T48	1
auto[2415919104:2550136831]	115	1			T3	1		T33	1		T47	2
auto[2550136832:2684354559]	107	1			T33	1		T5	2		T75	1
auto[2684354560:2818572287]	112	1			T3	1		T14	1		T5	2
auto[2818572288:2952790015]	119	1			T3	3		T4	1		T5	1
auto[2952790016:3087007743]	103	1			T33	1		T48	1		T133	1
auto[3087007744:3221225471]	88	1			T18	1		T24	1		T47	3
auto[3221225472:3355443199]	108	1			T3	1		T16	1		T33	1
auto[3355443200:3489660927]	115	1			T3	1		T16	1		T5	1
auto[3489660928:3623878655]	127	1			T16	1		T33	1		T5	1
auto[3623878656:3758096383]	91	1			T3	2		T5	2		T24	1
auto[3758096384:3892314111]	120	1			T3	1		T5	1		T48	1
auto[3892314112:4026531839]	99	1			T3	2		T5	6		T23	1
auto[4026531840:4160749567]	110	1			T5	3		T48	1		T47	1
auto[4160749568:4294967295]	94	1			T3	1		T14	1		T35	1