Unified Coverage Report :: Group Instance : salt_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3022

1

T3

20

T4

4

T14

4

auto[1]

271

1

T69

3

T226

11

T227

8

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	114	1			T3	1		T23	1		T132	1
auto[134217728:268435455]	110	1			T3	2		T5	2		T76	1
auto[268435456:402653183]	99	1			T5	3		T48	1		T42	1
auto[402653184:536870911]	106	1			T3	2		T18	1		T5	2
auto[536870912:671088639]	99	1			T3	1		T48	1		T35	1
auto[671088640:805306367]	108	1			T18	1		T5	1		T23	1
auto[805306368:939524095]	109	1			T3	1		T16	1		T5	2
auto[939524096:1073741823]	97	1			T47	2		T196	1		T36	1
auto[1073741824:1207959551]	113	1			T33	1		T5	2		T75	1
auto[1207959552:1342177279]	105	1			T5	1		T25	1		T47	2
auto[1342177280:1476395007]	97	1			T18	1		T24	1		T47	1
auto[1476395008:1610612735]	91	1			T3	1		T14	1		T5	1
auto[1610612736:1744830463]	105	1			T3	1		T5	1		T48	1
auto[1744830464:1879048191]	102	1			T14	1		T5	2		T75	1
auto[1879048192:2013265919]	107	1			T3	1		T35	1		T40	1
auto[2013265920:2147483647]	112	1			T3	1		T16	1		T5	2
auto[2147483648:2281701375]	76	1			T3	1		T18	1		T5	1
auto[2281701376:2415919103]	105	1			T3	2		T16	1		T5	2
auto[2415919104:2550136831]	94	1			T48	1		T53	1		T47	1
auto[2550136832:2684354559]	111	1			T5	2		T35	1		T47	1
auto[2684354560:2818572287]	105	1			T14	1		T25	1		T47	3
auto[2818572288:2952790015]	108	1			T5	1		T47	1		T42	3
auto[2952790016:3087007743]	102	1			T18	1		T5	3		T24	1
auto[3087007744:3221225471]	93	1			T4	2		T5	1		T75	1
auto[3221225472:3355443199]	99	1			T76	1		T48	1		T132	1
auto[3355443200:3489660927]	106	1			T3	1		T4	2		T5	1
auto[3489660928:3623878655]	124	1			T3	1		T5	1		T24	1
auto[3623878656:3758096383]	104	1			T3	1		T75	1		T76	1
auto[3758096384:3892314111]	111	1			T33	1		T25	1		T53	1
auto[3892314112:4026531839]	94	1			T3	2		T15	1		T5	1
auto[4026531840:4160749567]	91	1			T14	1		T16	1		T33	1
auto[4160749568:4294967295]	96	1			T3	1		T18	1		T5	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	101	1			T3	1		T23	1		T132	1
auto[0:134217727]	auto[1]	13	1			T226	1		T136	1		T138	1
auto[134217728:268435455]	auto[0]	100	1			T3	2		T5	2		T76	1
auto[134217728:268435455]	auto[1]	10	1			T234	1		T252	2		T185	1
auto[268435456:402653183]	auto[0]	92	1			T5	3		T48	1		T42	1
auto[268435456:402653183]	auto[1]	7	1			T69	1		T226	1		T227	1
auto[402653184:536870911]	auto[0]	99	1			T3	2		T18	1		T5	2
auto[402653184:536870911]	auto[1]	7	1			T136	1		T276	1		T262	1
auto[536870912:671088639]	auto[0]	92	1			T3	1		T48	1		T35	1
auto[536870912:671088639]	auto[1]	7	1			T135	1		T252	1		T366	1
auto[671088640:805306367]	auto[0]	100	1			T18	1		T5	1		T23	1
auto[671088640:805306367]	auto[1]	8	1			T226	1		T227	1		T136	1
auto[805306368:939524095]	auto[0]	100	1			T3	1		T16	1		T5	2
auto[805306368:939524095]	auto[1]	9	1			T227	1		T234	1		T136	1
auto[939524096:1073741823]	auto[0]	89	1			T47	2		T196	1		T36	1
auto[939524096:1073741823]	auto[1]	8	1			T262	1		T252	1		T366	1
auto[1073741824:1207959551]	auto[0]	106	1			T33	1		T5	2		T75	1
auto[1073741824:1207959551]	auto[1]	7	1			T69	1		T226	1		T138	1
auto[1207959552:1342177279]	auto[0]	99	1			T5	1		T25	1		T47	2
auto[1207959552:1342177279]	auto[1]	6	1			T262	1		T366	1		T378	1
auto[1342177280:1476395007]	auto[0]	88	1			T18	1		T24	1		T47	1
auto[1342177280:1476395007]	auto[1]	9	1			T340	1		T252	1		T366	1
auto[1476395008:1610612735]	auto[0]	80	1			T3	1		T14	1		T5	1
auto[1476395008:1610612735]	auto[1]	11	1			T264	1		T252	1		T364	1
auto[1610612736:1744830463]	auto[0]	93	1			T3	1		T5	1		T48	1
auto[1610612736:1744830463]	auto[1]	12	1			T227	1		T319	1		T328	1
auto[1744830464:1879048191]	auto[0]	90	1			T14	1		T5	2		T75	1
auto[1744830464:1879048191]	auto[1]	12	1			T234	1		T340	1		T328	1
auto[1879048192:2013265919]	auto[0]	101	1			T3	1		T35	1		T40	1
auto[1879048192:2013265919]	auto[1]	6	1			T328	1		T252	1		T185	1
auto[2013265920:2147483647]	auto[0]	107	1			T3	1		T16	1		T5	2
auto[2013265920:2147483647]	auto[1]	5	1			T319	1		T302	1		T243	1
auto[2147483648:2281701375]	auto[0]	73	1			T3	1		T18	1		T5	1
auto[2147483648:2281701375]	auto[1]	3	1			T136	1		T389	1		T383	1
auto[2281701376:2415919103]	auto[0]	92	1			T3	2		T16	1		T5	2
auto[2281701376:2415919103]	auto[1]	13	1			T264	1		T276	1		T281	1
auto[2415919104:2550136831]	auto[0]	85	1			T48	1		T53	1		T47	1
auto[2415919104:2550136831]	auto[1]	9	1			T138	1		T262	1		T228	1
auto[2550136832:2684354559]	auto[0]	106	1			T5	2		T35	1		T47	1
auto[2550136832:2684354559]	auto[1]	5	1			T226	1		T135	1		T296	1
auto[2684354560:2818572287]	auto[0]	99	1			T14	1		T25	1		T47	3
auto[2684354560:2818572287]	auto[1]	6	1			T228	2		T185	1		T378	1
auto[2818572288:2952790015]	auto[0]	95	1			T5	1		T47	1		T42	3
auto[2818572288:2952790015]	auto[1]	13	1			T226	3		T276	1		T262	1
auto[2952790016:3087007743]	auto[0]	95	1			T18	1		T5	3		T24	1
auto[2952790016:3087007743]	auto[1]	7	1			T252	2		T296	1		T375	1
auto[3087007744:3221225471]	auto[0]	88	1			T4	2		T5	1		T75	1
auto[3087007744:3221225471]	auto[1]	5	1			T227	2		T264	2		T342	1
auto[3221225472:3355443199]	auto[0]	92	1			T76	1		T48	1		T132	1
auto[3221225472:3355443199]	auto[1]	7	1			T228	1		T382	1		T296	1
auto[3355443200:3489660927]	auto[0]	97	1			T3	1		T4	2		T5	1
auto[3355443200:3489660927]	auto[1]	9	1			T226	1		T227	1		T138	1
auto[3489660928:3623878655]	auto[0]	113	1			T3	1		T5	1		T24	1
auto[3489660928:3623878655]	auto[1]	11	1			T226	2		T340	1		T276	1
auto[3623878656:3758096383]	auto[0]	94	1			T3	1		T75	1		T76	1
auto[3623878656:3758096383]	auto[1]	10	1			T252	1		T364	1		T281	1
auto[3758096384:3892314111]	auto[0]	96	1			T33	1		T25	1		T53	1
auto[3758096384:3892314111]	auto[1]	15	1			T69	1		T227	1		T319	1
auto[3892314112:4026531839]	auto[0]	84	1			T3	2		T15	1		T5	1
auto[3892314112:4026531839]	auto[1]	10	1			T319	1		T138	2		T366	1
auto[4026531840:4160749567]	auto[0]	84	1			T14	1		T16	1		T33	1
auto[4026531840:4160749567]	auto[1]	7	1			T264	1		T252	1		T281	1
auto[4160749568:4294967295]	auto[0]	92	1			T3	1		T18	1		T5	1
auto[4160749568:4294967295]	auto[1]	4	1			T319	1		T136	1		T252	1