Unified Coverage Report :: Group Instance : max_owner_int_key_ver_shadowed

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4740

1

T3

34

T14

6

T16

8

auto[1]

2220

1

T3

8

T4

8

T14

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	206	1			T3	4		T5	2		T75	2
auto[134217728:268435455]	186	1			T3	2		T5	4		T24	2
auto[268435456:402653183]	248	1			T14	2		T5	6		T24	2
auto[402653184:536870911]	228	1			T3	6		T4	2		T16	2
auto[536870912:671088639]	216	1			T3	2		T5	6		T35	2
auto[671088640:805306367]	200	1			T3	2		T14	2		T5	2
auto[805306368:939524095]	224	1			T4	2		T48	4		T47	2
auto[939524096:1073741823]	224	1			T3	4		T5	2		T25	2
auto[1073741824:1207959551]	198	1			T4	2		T5	6		T76	2
auto[1207959552:1342177279]	180	1			T47	2		T42	2		T124	2
auto[1342177280:1476395007]	252	1			T14	2		T5	4		T75	2
auto[1476395008:1610612735]	184	1			T3	2		T4	2		T5	2
auto[1610612736:1744830463]	254	1			T16	2		T5	8		T47	8
auto[1744830464:1879048191]	218	1			T3	2		T5	6		T48	2
auto[1879048192:2013265919]	198	1			T3	2		T5	4		T133	2
auto[2013265920:2147483647]	238	1			T3	2		T33	2		T75	2
auto[2147483648:2281701375]	196	1			T33	2		T5	6		T35	4
auto[2281701376:2415919103]	208	1			T5	2		T29	2		T47	4
auto[2415919104:2550136831]	216	1			T18	2		T33	2		T75	2
auto[2550136832:2684354559]	236	1			T3	2		T5	6		T28	2
auto[2684354560:2818572287]	246	1			T15	2		T16	2		T46	2
auto[2818572288:2952790015]	208	1			T5	4		T48	2		T133	2
auto[2952790016:3087007743]	192	1			T14	2		T16	2		T5	6
auto[3087007744:3221225471]	280	1			T3	4		T33	2		T76	2
auto[3221225472:3355443199]	208	1			T18	2		T5	2		T23	2
auto[3355443200:3489660927]	242	1			T18	2		T5	4		T25	2
auto[3489660928:3623878655]	210	1			T3	2		T33	4		T5	2
auto[3623878656:3758096383]	202	1			T5	2		T48	2		T133	4
auto[3758096384:3892314111]	200	1			T18	2		T5	4		T47	4
auto[3892314112:4026531839]	218	1			T18	2		T23	2		T24	2
auto[4026531840:4160749567]	240	1			T3	4		T18	2		T5	4
auto[4160749568:4294967295]	204	1			T3	2		T5	6		T76	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	146	1			T3	2		T5	2		T47	4
auto[0:134217727]	auto[1]	60	1			T3	2		T75	2		T53	2
auto[134217728:268435455]	auto[0]	130	1			T3	2		T5	4		T24	2
auto[134217728:268435455]	auto[1]	56	1			T40	2		T251	2		T244	2
auto[268435456:402653183]	auto[0]	166	1			T14	2		T5	2		T24	2
auto[268435456:402653183]	auto[1]	82	1			T5	4		T47	2		T40	2
auto[402653184:536870911]	auto[0]	170	1			T3	4		T16	2		T5	8
auto[402653184:536870911]	auto[1]	58	1			T3	2		T4	2		T82	2
auto[536870912:671088639]	auto[0]	164	1			T5	4		T35	2		T47	6
auto[536870912:671088639]	auto[1]	52	1			T3	2		T5	2		T42	2
auto[671088640:805306367]	auto[0]	136	1			T3	2		T14	2		T5	2
auto[671088640:805306367]	auto[1]	64	1			T56	2		T58	2		T215	4
auto[805306368:939524095]	auto[0]	144	1			T48	2		T196	2		T42	8
auto[805306368:939524095]	auto[1]	80	1			T4	2		T48	2		T47	2
auto[939524096:1073741823]	auto[0]	152	1			T3	4		T5	2		T25	2
auto[939524096:1073741823]	auto[1]	72	1			T53	2		T56	2		T295	2
auto[1073741824:1207959551]	auto[0]	106	1			T5	2		T76	2		T47	2
auto[1073741824:1207959551]	auto[1]	92	1			T4	2		T5	4		T48	2
auto[1207959552:1342177279]	auto[0]	136	1			T47	2		T42	2		T236	2
auto[1207959552:1342177279]	auto[1]	44	1			T124	2		T8	2		T58	2
auto[1342177280:1476395007]	auto[0]	166	1			T14	2		T75	2		T48	2
auto[1342177280:1476395007]	auto[1]	86	1			T5	4		T35	2		T47	2
auto[1476395008:1610612735]	auto[0]	130	1			T3	2		T5	2		T47	2
auto[1476395008:1610612735]	auto[1]	54	1			T4	2		T36	2		T41	2
auto[1610612736:1744830463]	auto[0]	176	1			T16	2		T5	6		T47	6
auto[1610612736:1744830463]	auto[1]	78	1			T5	2		T47	2		T69	2
auto[1744830464:1879048191]	auto[0]	160	1			T5	2		T47	4		T203	2
auto[1744830464:1879048191]	auto[1]	58	1			T3	2		T5	4		T48	2
auto[1879048192:2013265919]	auto[0]	116	1			T3	2		T5	2		T133	2
auto[1879048192:2013265919]	auto[1]	82	1			T5	2		T42	2		T7	2
auto[2013265920:2147483647]	auto[0]	178	1			T3	2		T33	2		T75	2
auto[2013265920:2147483647]	auto[1]	60	1			T46	2		T69	2		T41	2
auto[2147483648:2281701375]	auto[0]	146	1			T33	2		T5	4		T35	4
auto[2147483648:2281701375]	auto[1]	50	1			T5	2		T40	2		T205	2
auto[2281701376:2415919103]	auto[0]	134	1			T5	2		T29	2		T47	2
auto[2281701376:2415919103]	auto[1]	74	1			T47	2		T59	2		T134	4
auto[2415919104:2550136831]	auto[0]	164	1			T18	2		T33	2		T75	2
auto[2415919104:2550136831]	auto[1]	52	1			T48	4		T215	2		T386	2
auto[2550136832:2684354559]	auto[0]	152	1			T3	2		T5	2		T47	2
auto[2550136832:2684354559]	auto[1]	84	1			T5	4		T28	2		T97	2
auto[2684354560:2818572287]	auto[0]	160	1			T16	2		T132	4		T47	2
auto[2684354560:2818572287]	auto[1]	86	1			T15	2		T46	2		T207	2
auto[2818572288:2952790015]	auto[0]	148	1			T5	2		T48	2		T133	2
auto[2818572288:2952790015]	auto[1]	60	1			T5	2		T47	2		T58	4
auto[2952790016:3087007743]	auto[0]	140	1			T16	2		T5	2		T46	2
auto[2952790016:3087007743]	auto[1]	52	1			T14	2		T5	4		T28	2
auto[3087007744:3221225471]	auto[0]	182	1			T3	4		T33	2		T76	2
auto[3087007744:3221225471]	auto[1]	98	1			T48	2		T73	2		T7	2
auto[3221225472:3355443199]	auto[0]	134	1			T47	2		T42	4		T82	2
auto[3221225472:3355443199]	auto[1]	74	1			T18	2		T5	2		T23	2
auto[3355443200:3489660927]	auto[0]	168	1			T18	2		T5	4		T25	2
auto[3355443200:3489660927]	auto[1]	74	1			T42	2		T20	2		T200	2
auto[3489660928:3623878655]	auto[0]	138	1			T3	2		T33	2		T5	2
auto[3489660928:3623878655]	auto[1]	72	1			T33	2		T25	2		T7	2
auto[3623878656:3758096383]	auto[0]	138	1			T5	2		T48	2		T133	2
auto[3623878656:3758096383]	auto[1]	64	1			T133	2		T47	2		T58	2
auto[3758096384:3892314111]	auto[0]	122	1			T5	2		T47	2		T207	2
auto[3758096384:3892314111]	auto[1]	78	1			T18	2		T5	2		T47	2
auto[3892314112:4026531839]	auto[0]	148	1			T23	2		T24	2		T48	2
auto[3892314112:4026531839]	auto[1]	70	1			T18	2		T36	2		T42	2
auto[4026531840:4160749567]	auto[0]	156	1			T3	4		T18	2		T40	2
auto[4026531840:4160749567]	auto[1]	84	1			T5	4		T48	4		T42	2
auto[4160749568:4294967295]	auto[0]	134	1			T3	2		T5	2		T76	2
auto[4160749568:4294967295]	auto[1]	70	1			T5	4		T35	2		T47	2