Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.81 99.07 98.06 98.42 100.00 99.11 98.41 91.61


Total test records in report: 1078
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T1007 /workspace/coverage/cover_reg_top/17.keymgr_intr_test.3393365464 Mar 24 12:41:59 PM PDT 24 Mar 24 12:42:02 PM PDT 24 17334742 ps
T1008 /workspace/coverage/cover_reg_top/46.keymgr_intr_test.2845990569 Mar 24 12:42:02 PM PDT 24 Mar 24 12:42:04 PM PDT 24 70528316 ps
T1009 /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.572152581 Mar 24 12:41:35 PM PDT 24 Mar 24 12:41:36 PM PDT 24 138918719 ps
T1010 /workspace/coverage/cover_reg_top/38.keymgr_intr_test.1050373558 Mar 24 12:42:00 PM PDT 24 Mar 24 12:42:01 PM PDT 24 25859451 ps
T1011 /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.2228903265 Mar 24 12:41:51 PM PDT 24 Mar 24 12:41:52 PM PDT 24 72688624 ps
T156 /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.497821126 Mar 24 12:41:56 PM PDT 24 Mar 24 12:42:06 PM PDT 24 1681101685 ps
T1012 /workspace/coverage/cover_reg_top/37.keymgr_intr_test.3987422863 Mar 24 12:42:09 PM PDT 24 Mar 24 12:42:10 PM PDT 24 14336345 ps
T1013 /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.1278246388 Mar 24 12:41:35 PM PDT 24 Mar 24 12:41:36 PM PDT 24 30450319 ps
T1014 /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.87138937 Mar 24 12:41:45 PM PDT 24 Mar 24 12:41:48 PM PDT 24 209303507 ps
T157 /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.2674114615 Mar 24 12:41:56 PM PDT 24 Mar 24 12:42:00 PM PDT 24 230831697 ps
T1015 /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.1257626594 Mar 24 12:41:53 PM PDT 24 Mar 24 12:41:56 PM PDT 24 537843525 ps
T1016 /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.1103799456 Mar 24 12:41:52 PM PDT 24 Mar 24 12:41:55 PM PDT 24 397105657 ps
T1017 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.1721713921 Mar 24 12:41:47 PM PDT 24 Mar 24 12:41:53 PM PDT 24 200801441 ps
T161 /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.3247485557 Mar 24 12:42:03 PM PDT 24 Mar 24 12:42:12 PM PDT 24 1689997776 ps
T1018 /workspace/coverage/cover_reg_top/31.keymgr_intr_test.1640595825 Mar 24 12:42:06 PM PDT 24 Mar 24 12:42:07 PM PDT 24 11186085 ps
T1019 /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.2385508207 Mar 24 12:41:44 PM PDT 24 Mar 24 12:42:01 PM PDT 24 2692522933 ps
T1020 /workspace/coverage/cover_reg_top/20.keymgr_intr_test.965194948 Mar 24 12:42:00 PM PDT 24 Mar 24 12:42:02 PM PDT 24 36557302 ps
T1021 /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.2314036124 Mar 24 12:41:44 PM PDT 24 Mar 24 12:41:50 PM PDT 24 747241922 ps
T158 /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.253951608 Mar 24 12:41:53 PM PDT 24 Mar 24 12:41:59 PM PDT 24 233182304 ps
T1022 /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.1698482299 Mar 24 12:41:42 PM PDT 24 Mar 24 12:41:47 PM PDT 24 696412644 ps
T1023 /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.136183894 Mar 24 12:42:02 PM PDT 24 Mar 24 12:42:05 PM PDT 24 102384133 ps
T1024 /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.1380069879 Mar 24 12:41:46 PM PDT 24 Mar 24 12:41:47 PM PDT 24 124245651 ps
T1025 /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.4223754116 Mar 24 12:41:47 PM PDT 24 Mar 24 12:41:49 PM PDT 24 229548164 ps
T1026 /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.2425741122 Mar 24 12:41:53 PM PDT 24 Mar 24 12:41:57 PM PDT 24 319025659 ps
T1027 /workspace/coverage/cover_reg_top/8.keymgr_intr_test.1049866130 Mar 24 12:41:48 PM PDT 24 Mar 24 12:41:49 PM PDT 24 53152615 ps
T1028 /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.1440670116 Mar 24 12:41:50 PM PDT 24 Mar 24 12:41:52 PM PDT 24 73705280 ps
T169 /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.2177822654 Mar 24 12:41:59 PM PDT 24 Mar 24 12:42:06 PM PDT 24 440298604 ps
T1029 /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.2274480814 Mar 24 12:41:53 PM PDT 24 Mar 24 12:41:55 PM PDT 24 45265311 ps
T1030 /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.3007385936 Mar 24 12:41:40 PM PDT 24 Mar 24 12:41:41 PM PDT 24 59832801 ps
T1031 /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.1657601735 Mar 24 12:41:39 PM PDT 24 Mar 24 12:41:41 PM PDT 24 76336077 ps
T1032 /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.2442786381 Mar 24 12:41:52 PM PDT 24 Mar 24 12:42:06 PM PDT 24 803175958 ps
T1033 /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.2750128114 Mar 24 12:41:56 PM PDT 24 Mar 24 12:41:58 PM PDT 24 176319870 ps
T1034 /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.2858756943 Mar 24 12:41:36 PM PDT 24 Mar 24 12:41:39 PM PDT 24 167714746 ps
T1035 /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.2045661629 Mar 24 12:42:03 PM PDT 24 Mar 24 12:42:05 PM PDT 24 116667647 ps
T1036 /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.59037967 Mar 24 12:41:53 PM PDT 24 Mar 24 12:41:57 PM PDT 24 115342939 ps
T1037 /workspace/coverage/cover_reg_top/25.keymgr_intr_test.2195190123 Mar 24 12:42:00 PM PDT 24 Mar 24 12:42:02 PM PDT 24 13816127 ps
T1038 /workspace/coverage/cover_reg_top/30.keymgr_intr_test.3796044979 Mar 24 12:42:04 PM PDT 24 Mar 24 12:42:05 PM PDT 24 14593883 ps
T1039 /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.1021237669 Mar 24 12:41:50 PM PDT 24 Mar 24 12:41:54 PM PDT 24 52274106 ps
T1040 /workspace/coverage/cover_reg_top/45.keymgr_intr_test.85569152 Mar 24 12:42:02 PM PDT 24 Mar 24 12:42:04 PM PDT 24 63456085 ps
T1041 /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.270552210 Mar 24 12:41:33 PM PDT 24 Mar 24 12:41:35 PM PDT 24 118923544 ps
T1042 /workspace/coverage/cover_reg_top/19.keymgr_intr_test.2178320422 Mar 24 12:42:02 PM PDT 24 Mar 24 12:42:04 PM PDT 24 11247231 ps
T1043 /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.3876632842 Mar 24 12:41:41 PM PDT 24 Mar 24 12:41:44 PM PDT 24 48926002 ps
T1044 /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.1459660848 Mar 24 12:42:01 PM PDT 24 Mar 24 12:42:04 PM PDT 24 56297818 ps
T1045 /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.237845128 Mar 24 12:41:54 PM PDT 24 Mar 24 12:41:57 PM PDT 24 38668914 ps
T1046 /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.3685618607 Mar 24 12:41:39 PM PDT 24 Mar 24 12:41:53 PM PDT 24 1491346477 ps
T1047 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.3932845963 Mar 24 12:41:59 PM PDT 24 Mar 24 12:42:10 PM PDT 24 1812935189 ps
T1048 /workspace/coverage/cover_reg_top/0.keymgr_intr_test.2776841707 Mar 24 12:41:39 PM PDT 24 Mar 24 12:41:40 PM PDT 24 10652819 ps
T1049 /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.2238902018 Mar 24 12:41:42 PM PDT 24 Mar 24 12:41:43 PM PDT 24 31558301 ps
T1050 /workspace/coverage/cover_reg_top/33.keymgr_intr_test.317803445 Mar 24 12:42:04 PM PDT 24 Mar 24 12:42:10 PM PDT 24 18573316 ps
T1051 /workspace/coverage/cover_reg_top/28.keymgr_intr_test.756908970 Mar 24 12:42:03 PM PDT 24 Mar 24 12:42:04 PM PDT 24 9358365 ps
T1052 /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.266827676 Mar 24 12:41:35 PM PDT 24 Mar 24 12:41:36 PM PDT 24 22217218 ps
T1053 /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.2866509227 Mar 24 12:41:46 PM PDT 24 Mar 24 12:41:48 PM PDT 24 37307642 ps
T1054 /workspace/coverage/cover_reg_top/26.keymgr_intr_test.3982592843 Mar 24 12:42:07 PM PDT 24 Mar 24 12:42:08 PM PDT 24 18061583 ps
T159 /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.1297842523 Mar 24 12:41:53 PM PDT 24 Mar 24 12:42:03 PM PDT 24 442344162 ps
T1055 /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.2823319719 Mar 24 12:41:58 PM PDT 24 Mar 24 12:42:00 PM PDT 24 19921650 ps
T1056 /workspace/coverage/cover_reg_top/22.keymgr_intr_test.3286205374 Mar 24 12:42:07 PM PDT 24 Mar 24 12:42:08 PM PDT 24 60638487 ps
T1057 /workspace/coverage/cover_reg_top/14.keymgr_intr_test.3212477015 Mar 24 12:41:50 PM PDT 24 Mar 24 12:41:51 PM PDT 24 50298905 ps
T1058 /workspace/coverage/cover_reg_top/11.keymgr_intr_test.2709487038 Mar 24 12:41:53 PM PDT 24 Mar 24 12:41:55 PM PDT 24 8469260 ps
T1059 /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.902612691 Mar 24 12:42:02 PM PDT 24 Mar 24 12:42:08 PM PDT 24 1016235077 ps
T1060 /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.2061420524 Mar 24 12:42:01 PM PDT 24 Mar 24 12:42:15 PM PDT 24 378632372 ps
T1061 /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.939237360 Mar 24 12:41:52 PM PDT 24 Mar 24 12:41:56 PM PDT 24 197752383 ps
T1062 /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.3872311065 Mar 24 12:41:40 PM PDT 24 Mar 24 12:41:41 PM PDT 24 10413713 ps
T1063 /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.2321205136 Mar 24 12:41:52 PM PDT 24 Mar 24 12:41:59 PM PDT 24 631484412 ps
T1064 /workspace/coverage/cover_reg_top/5.keymgr_intr_test.1679205705 Mar 24 12:41:47 PM PDT 24 Mar 24 12:41:48 PM PDT 24 23654550 ps
T1065 /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.1626438497 Mar 24 12:42:17 PM PDT 24 Mar 24 12:42:22 PM PDT 24 435196587 ps
T1066 /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.2945422686 Mar 24 12:41:46 PM PDT 24 Mar 24 12:41:47 PM PDT 24 145146048 ps
T1067 /workspace/coverage/cover_reg_top/34.keymgr_intr_test.1960914973 Mar 24 12:42:03 PM PDT 24 Mar 24 12:42:04 PM PDT 24 13314835 ps
T1068 /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.1859236858 Mar 24 12:41:55 PM PDT 24 Mar 24 12:41:56 PM PDT 24 14949870 ps
T1069 /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.3244577252 Mar 24 12:41:54 PM PDT 24 Mar 24 12:41:56 PM PDT 24 299090767 ps
T1070 /workspace/coverage/cover_reg_top/7.keymgr_intr_test.3490744832 Mar 24 12:41:49 PM PDT 24 Mar 24 12:41:50 PM PDT 24 12530465 ps
T1071 /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.3596264388 Mar 24 12:41:59 PM PDT 24 Mar 24 12:42:01 PM PDT 24 71924583 ps
T1072 /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.3939736998 Mar 24 12:42:02 PM PDT 24 Mar 24 12:42:05 PM PDT 24 142590381 ps
T1073 /workspace/coverage/cover_reg_top/44.keymgr_intr_test.235091034 Mar 24 12:42:03 PM PDT 24 Mar 24 12:42:04 PM PDT 24 38449571 ps
T1074 /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.128310908 Mar 24 12:41:51 PM PDT 24 Mar 24 12:41:53 PM PDT 24 56436856 ps
T1075 /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.2878421672 Mar 24 12:41:56 PM PDT 24 Mar 24 12:41:57 PM PDT 24 22369058 ps
T1076 /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.2558439484 Mar 24 12:41:47 PM PDT 24 Mar 24 12:41:53 PM PDT 24 229340457 ps
T1077 /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.771517850 Mar 24 12:42:05 PM PDT 24 Mar 24 12:42:11 PM PDT 24 2095618708 ps
T1078 /workspace/coverage/cover_reg_top/27.keymgr_intr_test.1884973080 Mar 24 12:42:04 PM PDT 24 Mar 24 12:42:05 PM PDT 24 14489184 ps

Test location /workspace/coverage/default/33.keymgr_stress_all.1994207218
Short name T3
Test name
Test status
Simulation time 935443372 ps
CPU time 26.93 seconds
Started Mar 24 01:53:24 PM PDT 24
Finished Mar 24 01:53:52 PM PDT 24
Peak memory 221588 kb
Host smart-175ea319-a25b-4e3e-87ae-ed916a895868
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994207218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.1994207218
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.1032970984
Short name T5
Test name
Test status
Simulation time 4646914664 ps
CPU time 50.38 seconds
Started Mar 24 01:50:51 PM PDT 24
Finished Mar 24 01:51:42 PM PDT 24
Peak memory 216576 kb
Host smart-dca1236a-2a38-4499-afb5-309b7b68db42
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1032970984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.1032970984
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.4135134381
Short name T11
Test name
Test status
Simulation time 1474333926 ps
CPU time 23.75 seconds
Started Mar 24 01:50:01 PM PDT 24
Finished Mar 24 01:50:25 PM PDT 24
Peak memory 232924 kb
Host smart-ba0ec1ed-ca4f-46df-84f7-287fbbdbadb6
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135134381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.4135134381
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.1048218837
Short name T42
Test name
Test status
Simulation time 72455455295 ps
CPU time 92.9 seconds
Started Mar 24 01:50:55 PM PDT 24
Finished Mar 24 01:52:28 PM PDT 24
Peak memory 221536 kb
Host smart-f47a612e-8775-4e51-bf94-23fd79dccb18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1048218837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.1048218837
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_stress_all_with_rand_reset.1460866276
Short name T117
Test name
Test status
Simulation time 731431085 ps
CPU time 6.84 seconds
Started Mar 24 01:53:25 PM PDT 24
Finished Mar 24 01:53:32 PM PDT 24
Peak memory 219156 kb
Host smart-55e65bb0-5126-4908-b916-620c874cf4c8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1460866276 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all_with_rand_reset.1460866276
Directory /workspace/33.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.110186784
Short name T24
Test name
Test status
Simulation time 1999529753 ps
CPU time 39.82 seconds
Started Mar 24 01:53:52 PM PDT 24
Finished Mar 24 01:54:32 PM PDT 24
Peak memory 210248 kb
Host smart-97841b72-fd61-4357-923c-14fd0401d2fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=110186784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.110186784
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_stress_all.2885278788
Short name T59
Test name
Test status
Simulation time 3295050936 ps
CPU time 64.82 seconds
Started Mar 24 01:54:21 PM PDT 24
Finished Mar 24 01:55:26 PM PDT 24
Peak memory 223096 kb
Host smart-447eaa29-32d3-493a-ac6b-668caa22b436
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885278788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all.2885278788
Directory /workspace/45.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_stress_all_with_rand_reset.3199953506
Short name T52
Test name
Test status
Simulation time 2792152024 ps
CPU time 21.06 seconds
Started Mar 24 01:53:45 PM PDT 24
Finished Mar 24 01:54:06 PM PDT 24
Peak memory 223208 kb
Host smart-13b07fce-24aa-446d-9b10-7d6ce071b0f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3199953506 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all_with_rand_reset.3199953506
Directory /workspace/37.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.3230919113
Short name T105
Test name
Test status
Simulation time 94269164 ps
CPU time 4 seconds
Started Mar 24 12:41:50 PM PDT 24
Finished Mar 24 12:41:55 PM PDT 24
Peak memory 220576 kb
Host smart-20c0e0a9-4074-430d-9717-46b2adc1817a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3230919113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
keymgr_shadow_reg_errors_with_csr_rw.3230919113
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.1489723210
Short name T252
Test name
Test status
Simulation time 2351444592 ps
CPU time 14.44 seconds
Started Mar 24 01:53:59 PM PDT 24
Finished Mar 24 01:54:14 PM PDT 24
Peak memory 216300 kb
Host smart-a92b48cb-edaa-4060-b295-14a7f7898074
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1489723210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.1489723210
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.2557789624
Short name T43
Test name
Test status
Simulation time 4241116731 ps
CPU time 42.5 seconds
Started Mar 24 01:53:41 PM PDT 24
Finished Mar 24 01:54:23 PM PDT 24
Peak memory 217512 kb
Host smart-893f9944-d2c8-4e16-80b4-669a9c48f99a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2557789624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.2557789624
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.4192436732
Short name T9
Test name
Test status
Simulation time 555726406 ps
CPU time 6.57 seconds
Started Mar 24 01:54:08 PM PDT 24
Finished Mar 24 01:54:15 PM PDT 24
Peak memory 218060 kb
Host smart-a1eff3c5-da2d-47fd-832b-39dc3bbc9af0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4192436732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.4192436732
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.1673193301
Short name T226
Test name
Test status
Simulation time 223169036 ps
CPU time 7.05 seconds
Started Mar 24 01:53:03 PM PDT 24
Finished Mar 24 01:53:10 PM PDT 24
Peak memory 216080 kb
Host smart-cbc75c4e-c5b4-41da-bbff-8b2543afd1ba
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1673193301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.1673193301
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.1613641148
Short name T36
Test name
Test status
Simulation time 1103986821 ps
CPU time 7.05 seconds
Started Mar 24 01:53:49 PM PDT 24
Finished Mar 24 01:53:56 PM PDT 24
Peak memory 214748 kb
Host smart-6a9e7395-d864-4e4e-8871-1629a439066d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1613641148 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.1613641148
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.3485710359
Short name T228
Test name
Test status
Simulation time 210346955 ps
CPU time 11.11 seconds
Started Mar 24 01:53:40 PM PDT 24
Finished Mar 24 01:53:52 PM PDT 24
Peak memory 215332 kb
Host smart-36138881-b5e9-4799-b1e9-eebe26568daf
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3485710359 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.3485710359
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_stress_all_with_rand_reset.3718943436
Short name T7
Test name
Test status
Simulation time 441164351 ps
CPU time 21.05 seconds
Started Mar 24 01:49:58 PM PDT 24
Finished Mar 24 01:50:20 PM PDT 24
Peak memory 223120 kb
Host smart-b286e9cc-ceb5-4a83-9aa6-d31667eb66d4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718943436 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all_with_rand_reset.3718943436
Directory /workspace/0.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.734860353
Short name T342
Test name
Test status
Simulation time 2962377092 ps
CPU time 19 seconds
Started Mar 24 01:54:05 PM PDT 24
Finished Mar 24 01:54:24 PM PDT 24
Peak memory 216276 kb
Host smart-08866ffe-2650-4554-ade0-c16e5597fd25
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=734860353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.734860353
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.3718391345
Short name T138
Test name
Test status
Simulation time 288465978 ps
CPU time 4.81 seconds
Started Mar 24 01:53:53 PM PDT 24
Finished Mar 24 01:53:58 PM PDT 24
Peak memory 222900 kb
Host smart-5021135a-70ae-4cd6-a389-559bb58af222
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3718391345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.3718391345
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.2287782623
Short name T47
Test name
Test status
Simulation time 1323051944 ps
CPU time 48.59 seconds
Started Mar 24 01:54:07 PM PDT 24
Finished Mar 24 01:54:56 PM PDT 24
Peak memory 223000 kb
Host smart-65695b00-5b0d-4038-9375-ed765ca8e134
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2287782623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.2287782623
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.3573454073
Short name T306
Test name
Test status
Simulation time 78385636 ps
CPU time 2.99 seconds
Started Mar 24 01:52:28 PM PDT 24
Finished Mar 24 01:52:31 PM PDT 24
Peak memory 218724 kb
Host smart-3b70c6ef-48d9-4ffa-a90c-b14a89ed60b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3573454073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.3573454073
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.4106998676
Short name T922
Test name
Test status
Simulation time 373647169 ps
CPU time 5.61 seconds
Started Mar 24 12:41:34 PM PDT 24
Finished Mar 24 12:41:40 PM PDT 24
Peak memory 214504 kb
Host smart-6ab2f78e-3394-4b62-a79d-eba8ff81a92b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4106998676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.4106998676
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.3733228109
Short name T388
Test name
Test status
Simulation time 582143100 ps
CPU time 14.65 seconds
Started Mar 24 01:50:12 PM PDT 24
Finished Mar 24 01:50:27 PM PDT 24
Peak memory 215348 kb
Host smart-f0fd6513-2aed-4ffc-a0aa-dc3f9e279add
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3733228109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.3733228109
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.583040414
Short name T356
Test name
Test status
Simulation time 198447686 ps
CPU time 5.17 seconds
Started Mar 24 01:53:15 PM PDT 24
Finished Mar 24 01:53:22 PM PDT 24
Peak memory 222956 kb
Host smart-62bc3383-d620-4f98-9dd3-db9dc18f0d75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=583040414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.583040414
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_stress_all.726081048
Short name T134
Test name
Test status
Simulation time 48571811936 ps
CPU time 182.3 seconds
Started Mar 24 01:52:00 PM PDT 24
Finished Mar 24 01:55:03 PM PDT 24
Peak memory 217560 kb
Host smart-0d8ef802-5574-4749-a972-14addcf9b331
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=726081048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all.726081048
Directory /workspace/14.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.2937934693
Short name T28
Test name
Test status
Simulation time 117093483 ps
CPU time 5.29 seconds
Started Mar 24 01:52:08 PM PDT 24
Finished Mar 24 01:52:13 PM PDT 24
Peak memory 221912 kb
Host smart-a418605b-b367-4be4-8738-846cd28add1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937934693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.2937934693
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.2001237302
Short name T136
Test name
Test status
Simulation time 118788634 ps
CPU time 6.6 seconds
Started Mar 24 01:54:19 PM PDT 24
Finished Mar 24 01:54:26 PM PDT 24
Peak memory 215236 kb
Host smart-b779fa7c-9f11-4bae-8da6-fdcb61e49b90
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2001237302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.2001237302
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.4211288388
Short name T227
Test name
Test status
Simulation time 633479816 ps
CPU time 9.36 seconds
Started Mar 24 01:53:28 PM PDT 24
Finished Mar 24 01:53:38 PM PDT 24
Peak memory 214888 kb
Host smart-debb2b72-cf05-4491-ae72-a346c0b547be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4211288388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.4211288388
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.1172765275
Short name T147
Test name
Test status
Simulation time 101054324 ps
CPU time 4.58 seconds
Started Mar 24 01:52:42 PM PDT 24
Finished Mar 24 01:52:46 PM PDT 24
Peak memory 223192 kb
Host smart-92f8d2e5-2fb6-4c96-b615-100978759bc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1172765275 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.1172765275
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.1113697130
Short name T49
Test name
Test status
Simulation time 418027266 ps
CPU time 7.37 seconds
Started Mar 24 01:54:02 PM PDT 24
Finished Mar 24 01:54:10 PM PDT 24
Peak memory 211288 kb
Host smart-8e44372d-f20a-4a01-9401-63b11551cd75
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1113697130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.1113697130
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.2611923501
Short name T90
Test name
Test status
Simulation time 28856828 ps
CPU time 0.77 seconds
Started Mar 24 01:51:43 PM PDT 24
Finished Mar 24 01:51:44 PM PDT 24
Peak memory 206336 kb
Host smart-56e43a34-836d-4178-8d4b-881885d63ed3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2611923501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.2611923501
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.1297842523
Short name T159
Test name
Test status
Simulation time 442344162 ps
CPU time 9.43 seconds
Started Mar 24 12:41:53 PM PDT 24
Finished Mar 24 12:42:03 PM PDT 24
Peak memory 214124 kb
Host smart-f25b0efd-038f-4731-8f23-2e611ef88486
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1297842523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_er
r.1297842523
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.2643215004
Short name T40
Test name
Test status
Simulation time 9583307604 ps
CPU time 24.06 seconds
Started Mar 24 01:53:40 PM PDT 24
Finished Mar 24 01:54:04 PM PDT 24
Peak memory 214816 kb
Host smart-824b4423-2c67-4d5b-a8e4-b8316461709b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643215004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.2643215004
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.3655708035
Short name T152
Test name
Test status
Simulation time 551260804 ps
CPU time 13.1 seconds
Started Mar 24 12:41:42 PM PDT 24
Finished Mar 24 12:41:56 PM PDT 24
Peak memory 209476 kb
Host smart-03b8f34f-eb90-4280-b250-25a58a0f37c6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655708035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err
.3655708035
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.2146620816
Short name T89
Test name
Test status
Simulation time 56378233 ps
CPU time 3.37 seconds
Started Mar 24 01:51:39 PM PDT 24
Finished Mar 24 01:51:42 PM PDT 24
Peak memory 214804 kb
Host smart-5069a475-0d8c-4f9e-8474-4020ebef6f40
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146620816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.2146620816
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.3182393399
Short name T57
Test name
Test status
Simulation time 993109396 ps
CPU time 9.12 seconds
Started Mar 24 01:52:04 PM PDT 24
Finished Mar 24 01:52:13 PM PDT 24
Peak memory 210760 kb
Host smart-e35d021e-1cc3-4a3a-ad0d-915fe49398c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182393399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.3182393399
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.676767503
Short name T250
Test name
Test status
Simulation time 153695631 ps
CPU time 4.15 seconds
Started Mar 24 01:51:34 PM PDT 24
Finished Mar 24 01:51:38 PM PDT 24
Peak memory 214720 kb
Host smart-8804b826-259f-4780-9fb4-b8402335952f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=676767503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.676767503
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/1.keymgr_kmac_rsp_err.1061471437
Short name T199
Test name
Test status
Simulation time 169212620 ps
CPU time 3.27 seconds
Started Mar 24 01:50:13 PM PDT 24
Finished Mar 24 01:50:17 PM PDT 24
Peak memory 211940 kb
Host smart-ba021afe-bc21-40ac-a77e-3d5a11fcba1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061471437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_kmac_rsp_err.1061471437
Directory /workspace/1.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.3154009022
Short name T276
Test name
Test status
Simulation time 68141211 ps
CPU time 4.39 seconds
Started Mar 24 01:52:05 PM PDT 24
Finished Mar 24 01:52:09 PM PDT 24
Peak memory 222928 kb
Host smart-ada04a8f-0942-4cad-afda-87ec4d0e006a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3154009022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.3154009022
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.2633973581
Short name T328
Test name
Test status
Simulation time 179211113 ps
CPU time 9.54 seconds
Started Mar 24 01:53:29 PM PDT 24
Finished Mar 24 01:53:39 PM PDT 24
Peak memory 214840 kb
Host smart-6bd0a7b9-8a0f-4a3b-a9db-be26036baabe
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2633973581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.2633973581
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.1127390998
Short name T146
Test name
Test status
Simulation time 188692996 ps
CPU time 4.01 seconds
Started Mar 24 01:53:45 PM PDT 24
Finished Mar 24 01:53:49 PM PDT 24
Peak memory 223204 kb
Host smart-2e07c27b-2944-4ed2-838b-cb75375866f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1127390998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.1127390998
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.272880258
Short name T218
Test name
Test status
Simulation time 1604347710 ps
CPU time 62.46 seconds
Started Mar 24 01:50:29 PM PDT 24
Finished Mar 24 01:51:32 PM PDT 24
Peak memory 222868 kb
Host smart-3595a986-edbd-4c65-af71-1f9dad5a7a7c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=272880258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.272880258
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.497821126
Short name T156
Test name
Test status
Simulation time 1681101685 ps
CPU time 10.41 seconds
Started Mar 24 12:41:56 PM PDT 24
Finished Mar 24 12:42:06 PM PDT 24
Peak memory 209616 kb
Host smart-a0543a18-564b-4efd-8787-77bac7e2a8e0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=497821126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err.
497821126
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.803821149
Short name T55
Test name
Test status
Simulation time 99745139 ps
CPU time 3.61 seconds
Started Mar 24 01:52:05 PM PDT 24
Finished Mar 24 01:52:09 PM PDT 24
Peak memory 211020 kb
Host smart-8d752d4e-fa74-428b-ae82-c45613dea6c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=803821149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.803821149
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_stress_all_with_rand_reset.433507437
Short name T101
Test name
Test status
Simulation time 416708466 ps
CPU time 19.52 seconds
Started Mar 24 01:53:59 PM PDT 24
Finished Mar 24 01:54:18 PM PDT 24
Peak memory 220712 kb
Host smart-3b4d566b-2a79-41cc-a7e4-4136e3e6e977
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433507437 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all_with_rand_reset.433507437
Directory /workspace/40.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.3247485557
Short name T161
Test name
Test status
Simulation time 1689997776 ps
CPU time 8.78 seconds
Started Mar 24 12:42:03 PM PDT 24
Finished Mar 24 12:42:12 PM PDT 24
Peak memory 209344 kb
Host smart-3acc3363-5b37-49cd-a58e-de43c837be18
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3247485557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.3247485557
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.428615658
Short name T148
Test name
Test status
Simulation time 54000547 ps
CPU time 2.55 seconds
Started Mar 24 01:51:19 PM PDT 24
Finished Mar 24 01:51:22 PM PDT 24
Peak memory 218144 kb
Host smart-26454d94-f3c2-4dda-8441-975851d0c0ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=428615658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.428615658
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.1386181332
Short name T340
Test name
Test status
Simulation time 71603827 ps
CPU time 4.93 seconds
Started Mar 24 01:51:25 PM PDT 24
Finished Mar 24 01:51:30 PM PDT 24
Peak memory 215624 kb
Host smart-ba291d0b-0bd9-49a6-bc58-cfa6b1737cac
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1386181332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.1386181332
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.2937614807
Short name T283
Test name
Test status
Simulation time 79197566 ps
CPU time 4.63 seconds
Started Mar 24 01:52:00 PM PDT 24
Finished Mar 24 01:52:06 PM PDT 24
Peak memory 211960 kb
Host smart-5db42584-2cde-4f88-a81e-514d77d9811c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2937614807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.2937614807
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.629782099
Short name T150
Test name
Test status
Simulation time 330679940 ps
CPU time 3.77 seconds
Started Mar 24 01:54:19 PM PDT 24
Finished Mar 24 01:54:23 PM PDT 24
Peak memory 218156 kb
Host smart-d738cad9-a891-4368-96e0-280c1c13fcec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=629782099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.629782099
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.839219403
Short name T137
Test name
Test status
Simulation time 87508436022 ps
CPU time 885.84 seconds
Started Mar 24 01:52:34 PM PDT 24
Finished Mar 24 02:07:20 PM PDT 24
Peak memory 231220 kb
Host smart-4699c0cd-aa7c-4b74-a9b2-6e9eb931d5d5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=839219403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.839219403
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.2666063376
Short name T41
Test name
Test status
Simulation time 108982988 ps
CPU time 3.82 seconds
Started Mar 24 01:51:51 PM PDT 24
Finished Mar 24 01:51:55 PM PDT 24
Peak memory 210964 kb
Host smart-9412a5fd-8e8d-484b-b46e-cd1e073381f1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666063376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.2666063376
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.1732709099
Short name T391
Test name
Test status
Simulation time 201084822 ps
CPU time 3.83 seconds
Started Mar 24 01:52:03 PM PDT 24
Finished Mar 24 01:52:07 PM PDT 24
Peak memory 215820 kb
Host smart-ab315576-a46f-488e-8cb6-b3054bcb95c4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1732709099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.1732709099
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.2809209229
Short name T378
Test name
Test status
Simulation time 334016197 ps
CPU time 18.8 seconds
Started Mar 24 01:52:09 PM PDT 24
Finished Mar 24 01:52:28 PM PDT 24
Peak memory 216652 kb
Host smart-d75ccda2-2e02-4293-8273-bc266c624590
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2809209229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.2809209229
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.1238208336
Short name T338
Test name
Test status
Simulation time 12485074857 ps
CPU time 71.74 seconds
Started Mar 24 01:52:21 PM PDT 24
Finished Mar 24 01:53:33 PM PDT 24
Peak memory 223284 kb
Host smart-76528c82-1389-4e31-b86d-2f229f6dc3a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1238208336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.1238208336
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.493827197
Short name T65
Test name
Test status
Simulation time 284203835 ps
CPU time 15.82 seconds
Started Mar 24 01:52:22 PM PDT 24
Finished Mar 24 01:52:37 PM PDT 24
Peak memory 217756 kb
Host smart-84a9ce19-f2e4-4f82-8dd6-96cdafdbdace
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=493827197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.493827197
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.3957763069
Short name T216
Test name
Test status
Simulation time 493921839 ps
CPU time 21.65 seconds
Started Mar 24 01:53:26 PM PDT 24
Finished Mar 24 01:53:47 PM PDT 24
Peak memory 215876 kb
Host smart-5a5926da-1262-42be-886d-23de5f9c68a4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957763069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.3957763069
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.3677268461
Short name T284
Test name
Test status
Simulation time 148270846 ps
CPU time 7.18 seconds
Started Mar 24 01:53:50 PM PDT 24
Finished Mar 24 01:53:57 PM PDT 24
Peak memory 214728 kb
Host smart-aee067fb-6be5-4be3-840e-1feb77a39ca4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677268461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.3677268461
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.3406545702
Short name T224
Test name
Test status
Simulation time 808769937 ps
CPU time 29.72 seconds
Started Mar 24 01:51:00 PM PDT 24
Finished Mar 24 01:51:30 PM PDT 24
Peak memory 223004 kb
Host smart-de568fda-6960-4737-b4f8-11a37a03fb18
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3406545702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.3406545702
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.3452900510
Short name T324
Test name
Test status
Simulation time 297516349 ps
CPU time 3.64 seconds
Started Mar 24 01:51:17 PM PDT 24
Finished Mar 24 01:51:20 PM PDT 24
Peak memory 208096 kb
Host smart-53866e14-cbb1-42b8-bcd6-378742cc39f7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3452900510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.3452900510
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.3479393018
Short name T34
Test name
Test status
Simulation time 419250238 ps
CPU time 12.62 seconds
Started Mar 24 01:53:29 PM PDT 24
Finished Mar 24 01:53:41 PM PDT 24
Peak memory 216908 kb
Host smart-dfc862cf-4159-4c69-b7f1-69b11925c481
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479393018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.3479393018
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.1036968987
Short name T131
Test name
Test status
Simulation time 4330211478 ps
CPU time 29.86 seconds
Started Mar 24 01:49:41 PM PDT 24
Finished Mar 24 01:50:11 PM PDT 24
Peak memory 209180 kb
Host smart-7a99757d-0e51-42fe-a4f2-feb57c741a7b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1036968987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.1036968987
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.1666918202
Short name T364
Test name
Test status
Simulation time 118027185 ps
CPU time 4.22 seconds
Started Mar 24 01:51:41 PM PDT 24
Finished Mar 24 01:51:46 PM PDT 24
Peak memory 214624 kb
Host smart-409088fb-4b08-4c55-83de-6fcb8cd833aa
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1666918202 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.1666918202
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_stress_all_with_rand_reset.2848951292
Short name T287
Test name
Test status
Simulation time 1150741708 ps
CPU time 19.5 seconds
Started Mar 24 01:51:52 PM PDT 24
Finished Mar 24 01:52:13 PM PDT 24
Peak memory 223056 kb
Host smart-c29397e3-c49a-4446-9b83-23cc7150ee92
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2848951292 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all_with_rand_reset.2848951292
Directory /workspace/13.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.2989792526
Short name T271
Test name
Test status
Simulation time 4769884449 ps
CPU time 39.02 seconds
Started Mar 24 01:52:18 PM PDT 24
Finished Mar 24 01:52:57 PM PDT 24
Peak memory 223060 kb
Host smart-e3e42cc5-873c-471a-b039-144e3981a885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989792526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.2989792526
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.2570366374
Short name T354
Test name
Test status
Simulation time 1413470584 ps
CPU time 11.97 seconds
Started Mar 24 01:52:19 PM PDT 24
Finished Mar 24 01:52:31 PM PDT 24
Peak memory 214756 kb
Host smart-8abbe843-3900-495f-b698-14c66fb02a8c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2570366374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.2570366374
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.1965262546
Short name T770
Test name
Test status
Simulation time 5535940880 ps
CPU time 56.48 seconds
Started Mar 24 01:52:53 PM PDT 24
Finished Mar 24 01:53:49 PM PDT 24
Peak memory 223100 kb
Host smart-18aef2e8-b2d3-4e9f-95de-81f9d81ec1e5
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1965262546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.1965262546
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.4118518428
Short name T375
Test name
Test status
Simulation time 407672950 ps
CPU time 12.15 seconds
Started Mar 24 01:53:59 PM PDT 24
Finished Mar 24 01:54:12 PM PDT 24
Peak memory 222972 kb
Host smart-65c95774-aa17-47d8-bdd5-ce94d4831818
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4118518428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.4118518428
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.4177572898
Short name T294
Test name
Test status
Simulation time 66093937 ps
CPU time 3.22 seconds
Started Mar 24 01:51:16 PM PDT 24
Finished Mar 24 01:51:19 PM PDT 24
Peak memory 214720 kb
Host smart-50e2f52c-4114-4824-8a41-9197c4c60296
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4177572898 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.4177572898
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.2674114615
Short name T157
Test name
Test status
Simulation time 230831697 ps
CPU time 3.5 seconds
Started Mar 24 12:41:56 PM PDT 24
Finished Mar 24 12:42:00 PM PDT 24
Peak memory 209672 kb
Host smart-c32f8172-954a-41e8-8b1e-7dba79bd4498
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2674114615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.2674114615
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.659521483
Short name T171
Test name
Test status
Simulation time 810796244 ps
CPU time 8.89 seconds
Started Mar 24 12:41:53 PM PDT 24
Finished Mar 24 12:42:03 PM PDT 24
Peak memory 214276 kb
Host smart-4d89c104-e07f-4b71-972a-a61bc9da419f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659521483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_err
.659521483
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.2489119907
Short name T164
Test name
Test status
Simulation time 152897103 ps
CPU time 4.82 seconds
Started Mar 24 12:42:00 PM PDT 24
Finished Mar 24 12:42:06 PM PDT 24
Peak memory 209552 kb
Host smart-8f5fbd12-1a81-4c6b-a24e-271c4371df84
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2489119907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.2489119907
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.3300810812
Short name T153
Test name
Test status
Simulation time 1688619096 ps
CPU time 10.42 seconds
Started Mar 24 12:42:03 PM PDT 24
Finished Mar 24 12:42:14 PM PDT 24
Peak memory 209704 kb
Host smart-f551b295-484b-4fe7-ba8b-c6897aa52e4a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3300810812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.3300810812
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.2177822654
Short name T169
Test name
Test status
Simulation time 440298604 ps
CPU time 6.29 seconds
Started Mar 24 12:41:59 PM PDT 24
Finished Mar 24 12:42:06 PM PDT 24
Peak memory 209268 kb
Host smart-3e6909dc-28f2-4ebc-8766-73ec54553824
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2177822654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.2177822654
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.581343538
Short name T155
Test name
Test status
Simulation time 643237476 ps
CPU time 5.04 seconds
Started Mar 24 12:41:53 PM PDT 24
Finished Mar 24 12:41:59 PM PDT 24
Peak memory 210012 kb
Host smart-062df9a8-0764-4f0b-b9c8-7f06612dee1e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=581343538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err.
581343538
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.1664057137
Short name T149
Test name
Test status
Simulation time 82972378 ps
CPU time 4.33 seconds
Started Mar 24 01:53:26 PM PDT 24
Finished Mar 24 01:53:30 PM PDT 24
Peak memory 218420 kb
Host smart-2fd07d94-562c-4dbb-a55d-1c1ca4674efb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664057137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.1664057137
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.815678726
Short name T187
Test name
Test status
Simulation time 23216092109 ps
CPU time 94.94 seconds
Started Mar 24 01:50:13 PM PDT 24
Finished Mar 24 01:51:49 PM PDT 24
Peak memory 223072 kb
Host smart-6f05468c-fd24-44db-825f-b565b6305e79
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=815678726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.815678726
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_stress_all_with_rand_reset.2399985739
Short name T115
Test name
Test status
Simulation time 171749033 ps
CPU time 5.73 seconds
Started Mar 24 01:51:39 PM PDT 24
Finished Mar 24 01:51:45 PM PDT 24
Peak memory 223128 kb
Host smart-c276eea0-f0e8-4e01-b35a-079571749088
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2399985739 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all_with_rand_reset.2399985739
Directory /workspace/11.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.3420006540
Short name T258
Test name
Test status
Simulation time 240479836 ps
CPU time 4.01 seconds
Started Mar 24 01:51:43 PM PDT 24
Finished Mar 24 01:51:48 PM PDT 24
Peak memory 214832 kb
Host smart-23f47a0e-85c4-4059-a374-d058d40a1016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420006540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.3420006540
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.4001770571
Short name T58
Test name
Test status
Simulation time 2046428559 ps
CPU time 28.81 seconds
Started Mar 24 01:51:53 PM PDT 24
Finished Mar 24 01:52:23 PM PDT 24
Peak memory 222940 kb
Host smart-33f90df8-82c2-4d95-91b4-74db1dd2bc9e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001770571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.4001770571
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.1765332225
Short name T563
Test name
Test status
Simulation time 141512330 ps
CPU time 3.65 seconds
Started Mar 24 01:51:52 PM PDT 24
Finished Mar 24 01:51:56 PM PDT 24
Peak memory 210784 kb
Host smart-e3c0c1d7-b919-4634-b951-d16dd1f42c6d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1765332225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.1765332225
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.564369086
Short name T365
Test name
Test status
Simulation time 51221091 ps
CPU time 3.72 seconds
Started Mar 24 01:51:52 PM PDT 24
Finished Mar 24 01:51:57 PM PDT 24
Peak memory 214768 kb
Host smart-ee9fda28-693e-4832-9fe7-22f2447b9bf2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=564369086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.564369086
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.473406805
Short name T206
Test name
Test status
Simulation time 221787876 ps
CPU time 4.26 seconds
Started Mar 24 01:52:22 PM PDT 24
Finished Mar 24 01:52:26 PM PDT 24
Peak memory 223052 kb
Host smart-cac5f683-ffc7-4769-9f4c-46646201cc6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473406805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.473406805
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.3704506837
Short name T242
Test name
Test status
Simulation time 669363841 ps
CPU time 9.12 seconds
Started Mar 24 01:52:40 PM PDT 24
Finished Mar 24 01:52:49 PM PDT 24
Peak memory 210300 kb
Host smart-f55f3845-7279-4a6f-90eb-6beacba066a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3704506837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.3704506837
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_stress_all_with_rand_reset.1285920615
Short name T66
Test name
Test status
Simulation time 870950221 ps
CPU time 10.25 seconds
Started Mar 24 01:52:43 PM PDT 24
Finished Mar 24 01:52:54 PM PDT 24
Peak memory 221984 kb
Host smart-627f557a-dd93-48e9-b31d-55ea291392cb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1285920615 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all_with_rand_reset.1285920615
Directory /workspace/22.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.257892905
Short name T239
Test name
Test status
Simulation time 567540147 ps
CPU time 5.85 seconds
Started Mar 24 01:52:47 PM PDT 24
Finished Mar 24 01:52:54 PM PDT 24
Peak memory 210808 kb
Host smart-9cbae60c-1cda-4cc8-b502-d364a8442c6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=257892905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.257892905
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_random.4094698515
Short name T343
Test name
Test status
Simulation time 196381110 ps
CPU time 5.83 seconds
Started Mar 24 01:52:49 PM PDT 24
Finished Mar 24 01:52:55 PM PDT 24
Peak memory 218636 kb
Host smart-30712b6f-513a-4db6-8531-a69f9af8c51d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4094698515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.4094698515
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.2580219731
Short name T819
Test name
Test status
Simulation time 166826158 ps
CPU time 4.71 seconds
Started Mar 24 01:52:52 PM PDT 24
Finished Mar 24 01:52:57 PM PDT 24
Peak memory 223212 kb
Host smart-64e6604f-f42b-45ec-bda2-0e1ae77d4c36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2580219731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.2580219731
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.1692414451
Short name T245
Test name
Test status
Simulation time 109453486 ps
CPU time 4.2 seconds
Started Mar 24 01:53:14 PM PDT 24
Finished Mar 24 01:53:18 PM PDT 24
Peak memory 214808 kb
Host smart-5c4ffafc-f6cd-44f9-98f2-bf04b6952254
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1692414451 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.1692414451
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.3092611326
Short name T39
Test name
Test status
Simulation time 712808287 ps
CPU time 4.84 seconds
Started Mar 24 01:53:16 PM PDT 24
Finished Mar 24 01:53:21 PM PDT 24
Peak memory 210236 kb
Host smart-dc203410-701e-4740-8f9c-520ef4239452
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092611326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.3092611326
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/30.keymgr_stress_all_with_rand_reset.1387509676
Short name T331
Test name
Test status
Simulation time 1467029695 ps
CPU time 20.44 seconds
Started Mar 24 01:53:15 PM PDT 24
Finished Mar 24 01:53:37 PM PDT 24
Peak memory 223044 kb
Host smart-611fbd57-b864-4ecf-91e2-6033bdf47e28
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1387509676 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all_with_rand_reset.1387509676
Directory /workspace/30.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.3124099966
Short name T78
Test name
Test status
Simulation time 1644344077 ps
CPU time 6.93 seconds
Started Mar 24 01:53:20 PM PDT 24
Finished Mar 24 01:53:27 PM PDT 24
Peak memory 214820 kb
Host smart-c1a184ab-3936-4819-850d-e43b570e714a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3124099966 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.3124099966
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.1869066917
Short name T189
Test name
Test status
Simulation time 1707935538 ps
CPU time 51.62 seconds
Started Mar 24 01:53:21 PM PDT 24
Finished Mar 24 01:54:13 PM PDT 24
Peak memory 220968 kb
Host smart-689954a3-2227-4458-b202-169d904a8238
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1869066917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.1869066917
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.3958740539
Short name T257
Test name
Test status
Simulation time 8594513123 ps
CPU time 63.51 seconds
Started Mar 24 01:53:21 PM PDT 24
Finished Mar 24 01:54:24 PM PDT 24
Peak memory 223068 kb
Host smart-9c02ce72-e189-43f3-ab4a-d53332e0ea39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3958740539 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.3958740539
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.266691441
Short name T221
Test name
Test status
Simulation time 711666823 ps
CPU time 5.87 seconds
Started Mar 24 01:53:27 PM PDT 24
Finished Mar 24 01:53:34 PM PDT 24
Peak memory 209916 kb
Host smart-17210416-dcf7-4e0a-8f9f-cad292584bc8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266691441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.266691441
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.2057719774
Short name T303
Test name
Test status
Simulation time 1768803461 ps
CPU time 10.81 seconds
Started Mar 24 01:54:06 PM PDT 24
Finished Mar 24 01:54:17 PM PDT 24
Peak memory 210744 kb
Host smart-9cde3f16-7ce6-4dd1-acae-c3c71afef6e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2057719774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.2057719774
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.2624755666
Short name T243
Test name
Test status
Simulation time 58147388 ps
CPU time 3.99 seconds
Started Mar 24 01:50:54 PM PDT 24
Finished Mar 24 01:50:58 PM PDT 24
Peak memory 216252 kb
Host smart-c0b72373-d2c0-47ac-8951-6626936edf07
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2624755666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.2624755666
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_stress_all_with_rand_reset.2487837397
Short name T219
Test name
Test status
Simulation time 677741778 ps
CPU time 8.97 seconds
Started Mar 24 01:51:26 PM PDT 24
Finished Mar 24 01:51:35 PM PDT 24
Peak memory 220988 kb
Host smart-0d775899-edea-4500-ad42-e6d77419f70a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487837397 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all_with_rand_reset.2487837397
Directory /workspace/9.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.4012575043
Short name T925
Test name
Test status
Simulation time 2135530877 ps
CPU time 10.64 seconds
Started Mar 24 12:41:39 PM PDT 24
Finished Mar 24 12:41:50 PM PDT 24
Peak memory 206040 kb
Host smart-f32b4cb5-81a5-4370-b43a-31ce2b9ed049
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012575043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.4
012575043
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.628060787
Short name T941
Test name
Test status
Simulation time 538217382 ps
CPU time 7.88 seconds
Started Mar 24 12:41:36 PM PDT 24
Finished Mar 24 12:41:44 PM PDT 24
Peak memory 206068 kb
Host smart-4a1d6839-cd9b-49ec-975b-861773aac344
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=628060787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.628060787
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.1080161727
Short name T973
Test name
Test status
Simulation time 62328320 ps
CPU time 1.4 seconds
Started Mar 24 12:41:39 PM PDT 24
Finished Mar 24 12:41:40 PM PDT 24
Peak memory 206132 kb
Host smart-54ffbcb6-1791-4478-a1ab-c594b402b07d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1080161727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.1
080161727
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.2166184520
Short name T997
Test name
Test status
Simulation time 297340330 ps
CPU time 2.04 seconds
Started Mar 24 12:41:37 PM PDT 24
Finished Mar 24 12:41:39 PM PDT 24
Peak memory 214352 kb
Host smart-0923c928-a27a-44ef-8e05-ec372ca44ab1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2166184520 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.2166184520
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.266827676
Short name T1052
Test name
Test status
Simulation time 22217218 ps
CPU time 1.17 seconds
Started Mar 24 12:41:35 PM PDT 24
Finished Mar 24 12:41:36 PM PDT 24
Peak memory 205880 kb
Host smart-8e0e19e1-5976-44b5-9643-cbd4690357db
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266827676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.266827676
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.2776841707
Short name T1048
Test name
Test status
Simulation time 10652819 ps
CPU time 0.76 seconds
Started Mar 24 12:41:39 PM PDT 24
Finished Mar 24 12:41:40 PM PDT 24
Peak memory 205600 kb
Host smart-e88105ec-1a73-4f3c-9d53-9f3a883848fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2776841707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.2776841707
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.1537877034
Short name T141
Test name
Test status
Simulation time 414058445 ps
CPU time 3.97 seconds
Started Mar 24 12:41:39 PM PDT 24
Finished Mar 24 12:41:43 PM PDT 24
Peak memory 206084 kb
Host smart-67361a1c-3160-42ee-abcf-89f93e164341
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1537877034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.1537877034
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.560051392
Short name T949
Test name
Test status
Simulation time 702249979 ps
CPU time 14.22 seconds
Started Mar 24 12:41:34 PM PDT 24
Finished Mar 24 12:41:49 PM PDT 24
Peak memory 214592 kb
Host smart-5c6f315d-fdd2-46ce-8c79-bff643a89730
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=560051392 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.k
eymgr_shadow_reg_errors_with_csr_rw.560051392
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.1139367530
Short name T1005
Test name
Test status
Simulation time 62012317 ps
CPU time 2.34 seconds
Started Mar 24 12:41:37 PM PDT 24
Finished Mar 24 12:41:39 PM PDT 24
Peak memory 216152 kb
Host smart-b69f4bd0-060d-4368-8cdc-f38092986290
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1139367530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.1139367530
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.510813745
Short name T962
Test name
Test status
Simulation time 1002025354 ps
CPU time 13.32 seconds
Started Mar 24 12:41:38 PM PDT 24
Finished Mar 24 12:41:52 PM PDT 24
Peak memory 214248 kb
Host smart-79c41749-0226-4947-876d-425cb4d491c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=510813745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err.
510813745
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.3685618607
Short name T1046
Test name
Test status
Simulation time 1491346477 ps
CPU time 14.66 seconds
Started Mar 24 12:41:39 PM PDT 24
Finished Mar 24 12:41:53 PM PDT 24
Peak memory 206044 kb
Host smart-f9699b3d-7127-477d-b2ed-4d518a95c25f
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3685618607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.3
685618607
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.2412692528
Short name T967
Test name
Test status
Simulation time 456806153 ps
CPU time 12.91 seconds
Started Mar 24 12:41:37 PM PDT 24
Finished Mar 24 12:41:50 PM PDT 24
Peak memory 205864 kb
Host smart-ee512c7b-75eb-49ed-af7a-fd60671f835a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2412692528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.2
412692528
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.270552210
Short name T1041
Test name
Test status
Simulation time 118923544 ps
CPU time 1.48 seconds
Started Mar 24 12:41:33 PM PDT 24
Finished Mar 24 12:41:35 PM PDT 24
Peak memory 205852 kb
Host smart-af8ee2aa-026f-4928-abf3-e3f57d51d408
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270552210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.270552210
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.1278246388
Short name T1013
Test name
Test status
Simulation time 30450319 ps
CPU time 1.21 seconds
Started Mar 24 12:41:35 PM PDT 24
Finished Mar 24 12:41:36 PM PDT 24
Peak memory 205940 kb
Host smart-ff253288-7af9-4de9-b8fa-691326273ebd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1278246388 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.1278246388
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.2628938316
Short name T140
Test name
Test status
Simulation time 47266762 ps
CPU time 1.46 seconds
Started Mar 24 12:41:43 PM PDT 24
Finished Mar 24 12:41:44 PM PDT 24
Peak memory 205924 kb
Host smart-c45b309a-deb4-45b1-b71a-76ea97732ee6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2628938316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.2628938316
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.1064188959
Short name T1006
Test name
Test status
Simulation time 33185302 ps
CPU time 0.73 seconds
Started Mar 24 12:41:36 PM PDT 24
Finished Mar 24 12:41:37 PM PDT 24
Peak memory 205560 kb
Host smart-052196a1-8699-4388-bc01-7c19de346170
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1064188959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.1064188959
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.572152581
Short name T1009
Test name
Test status
Simulation time 138918719 ps
CPU time 1.41 seconds
Started Mar 24 12:41:35 PM PDT 24
Finished Mar 24 12:41:36 PM PDT 24
Peak memory 205928 kb
Host smart-d9e77f76-c3a5-4621-b4e6-a07c45d165e0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=572152581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sam
e_csr_outstanding.572152581
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.2371372140
Short name T976
Test name
Test status
Simulation time 163858916 ps
CPU time 2.85 seconds
Started Mar 24 12:41:38 PM PDT 24
Finished Mar 24 12:41:41 PM PDT 24
Peak memory 218944 kb
Host smart-ad4f46d0-0038-4d9c-b694-f13d34211389
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2371372140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.2371372140
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.1749920995
Short name T979
Test name
Test status
Simulation time 747714292 ps
CPU time 12.86 seconds
Started Mar 24 12:41:36 PM PDT 24
Finished Mar 24 12:41:48 PM PDT 24
Peak memory 214456 kb
Host smart-9d172689-14a1-4293-b46f-2d29ce291a4a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1749920995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.1749920995
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.2858756943
Short name T1034
Test name
Test status
Simulation time 167714746 ps
CPU time 3.45 seconds
Started Mar 24 12:41:36 PM PDT 24
Finished Mar 24 12:41:39 PM PDT 24
Peak memory 216208 kb
Host smart-4aa85930-6244-4b45-8c4f-c853b27aa36b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2858756943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.2858756943
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.3781030757
Short name T162
Test name
Test status
Simulation time 118664002 ps
CPU time 6.26 seconds
Started Mar 24 12:41:37 PM PDT 24
Finished Mar 24 12:41:43 PM PDT 24
Peak memory 214220 kb
Host smart-c812c005-09bc-4862-b181-b44cd1a3ad6d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781030757 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err
.3781030757
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.128310908
Short name T1074
Test name
Test status
Simulation time 56436856 ps
CPU time 1.29 seconds
Started Mar 24 12:41:51 PM PDT 24
Finished Mar 24 12:41:53 PM PDT 24
Peak memory 205844 kb
Host smart-ea8337f5-303e-4039-82b9-d63aba832b4f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=128310908 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.128310908
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.2055739506
Short name T160
Test name
Test status
Simulation time 58742252 ps
CPU time 0.92 seconds
Started Mar 24 12:41:50 PM PDT 24
Finished Mar 24 12:41:52 PM PDT 24
Peak memory 205808 kb
Host smart-b4ba8d5a-5b39-4943-a673-c8f3510e4378
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2055739506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.2055739506
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.2898792237
Short name T1003
Test name
Test status
Simulation time 26979160 ps
CPU time 0.75 seconds
Started Mar 24 12:41:57 PM PDT 24
Finished Mar 24 12:41:58 PM PDT 24
Peak memory 205680 kb
Host smart-6ddcaacc-7f09-4a6b-b4fa-fcb82da39f4b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898792237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.2898792237
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.3182246528
Short name T972
Test name
Test status
Simulation time 73010624 ps
CPU time 2.4 seconds
Started Mar 24 12:41:52 PM PDT 24
Finished Mar 24 12:41:54 PM PDT 24
Peak memory 214200 kb
Host smart-500be598-4e73-4ccc-b551-74776675db62
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3182246528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_s
ame_csr_outstanding.3182246528
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.2558439484
Short name T1076
Test name
Test status
Simulation time 229340457 ps
CPU time 5.32 seconds
Started Mar 24 12:41:47 PM PDT 24
Finished Mar 24 12:41:53 PM PDT 24
Peak memory 214576 kb
Host smart-1bbe9188-bb36-4bf2-88fb-fa0e38a12cf3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558439484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.2558439484
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.3234207613
Short name T1001
Test name
Test status
Simulation time 86026266 ps
CPU time 3.99 seconds
Started Mar 24 12:41:53 PM PDT 24
Finished Mar 24 12:41:58 PM PDT 24
Peak memory 214900 kb
Host smart-41860b04-a0e9-4940-9657-0f55a0d23300
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3234207613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.keymgr_shadow_reg_errors_with_csr_rw.3234207613
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.731450095
Short name T998
Test name
Test status
Simulation time 72837889 ps
CPU time 2.78 seconds
Started Mar 24 12:41:48 PM PDT 24
Finished Mar 24 12:41:51 PM PDT 24
Peak memory 214052 kb
Host smart-2a8456f5-11c9-401c-8ff7-162fb9bec313
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=731450095 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.731450095
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.1968729929
Short name T359
Test name
Test status
Simulation time 485034358 ps
CPU time 3.33 seconds
Started Mar 24 12:41:46 PM PDT 24
Finished Mar 24 12:41:49 PM PDT 24
Peak memory 209652 kb
Host smart-605d65d9-7b46-4a5a-9a92-ff2bcb67fb5e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968729929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_er
r.1968729929
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.2768367041
Short name T987
Test name
Test status
Simulation time 50029125 ps
CPU time 1.06 seconds
Started Mar 24 12:41:53 PM PDT 24
Finished Mar 24 12:41:54 PM PDT 24
Peak memory 205728 kb
Host smart-ed3a3a8c-f97b-49c2-a5ab-c5035985a784
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2768367041 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.2768367041
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.2152405873
Short name T978
Test name
Test status
Simulation time 16675477 ps
CPU time 0.91 seconds
Started Mar 24 12:41:49 PM PDT 24
Finished Mar 24 12:41:50 PM PDT 24
Peak memory 205708 kb
Host smart-5da0f1c7-1f0b-4915-a1a9-7245b75995d4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152405873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.2152405873
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.2709487038
Short name T1058
Test name
Test status
Simulation time 8469260 ps
CPU time 0.73 seconds
Started Mar 24 12:41:53 PM PDT 24
Finished Mar 24 12:41:55 PM PDT 24
Peak memory 205548 kb
Host smart-bb42b847-b3fa-4ae1-be2e-954fadb45582
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709487038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.2709487038
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.4277261692
Short name T144
Test name
Test status
Simulation time 94078015 ps
CPU time 1.44 seconds
Started Mar 24 12:41:50 PM PDT 24
Finished Mar 24 12:41:52 PM PDT 24
Peak memory 205920 kb
Host smart-4c84ba11-aafb-4949-a021-18e719a25c05
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4277261692 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s
ame_csr_outstanding.4277261692
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.1498843165
Short name T926
Test name
Test status
Simulation time 244345632 ps
CPU time 4.92 seconds
Started Mar 24 12:41:51 PM PDT 24
Finished Mar 24 12:41:56 PM PDT 24
Peak memory 222648 kb
Host smart-0b94e851-8804-4ed9-b075-a80d7dd4d74d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1498843165 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.1498843165
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.2442786381
Short name T1032
Test name
Test status
Simulation time 803175958 ps
CPU time 13.99 seconds
Started Mar 24 12:41:52 PM PDT 24
Finished Mar 24 12:42:06 PM PDT 24
Peak memory 214644 kb
Host smart-ea02a07e-ece4-4a59-a629-7d95d1d24340
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2442786381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.2442786381
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.1021237669
Short name T1039
Test name
Test status
Simulation time 52274106 ps
CPU time 3.37 seconds
Started Mar 24 12:41:50 PM PDT 24
Finished Mar 24 12:41:54 PM PDT 24
Peak memory 217152 kb
Host smart-da284526-4041-4bc1-85b7-266fc01a01e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1021237669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.1021237669
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.3033336489
Short name T165
Test name
Test status
Simulation time 1603615833 ps
CPU time 5.49 seconds
Started Mar 24 12:41:52 PM PDT 24
Finished Mar 24 12:41:58 PM PDT 24
Peak memory 209488 kb
Host smart-91e2d8a1-8917-4d6d-b8ee-d45145b5a002
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3033336489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.3033336489
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.2274480814
Short name T1029
Test name
Test status
Simulation time 45265311 ps
CPU time 1.13 seconds
Started Mar 24 12:41:53 PM PDT 24
Finished Mar 24 12:41:55 PM PDT 24
Peak memory 206012 kb
Host smart-49d5df42-49d3-47a5-bf69-953a176e4a93
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2274480814 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.2274480814
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.4207186259
Short name T932
Test name
Test status
Simulation time 34250647 ps
CPU time 1.04 seconds
Started Mar 24 12:41:52 PM PDT 24
Finished Mar 24 12:41:55 PM PDT 24
Peak memory 205660 kb
Host smart-95944615-9c3f-4793-836a-adc7bfb8a663
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4207186259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.4207186259
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.3444246213
Short name T1000
Test name
Test status
Simulation time 37166765 ps
CPU time 0.84 seconds
Started Mar 24 12:41:59 PM PDT 24
Finished Mar 24 12:42:01 PM PDT 24
Peak memory 205516 kb
Host smart-63160d84-76dd-4e7d-a2fd-2a8e21b596a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3444246213 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.3444246213
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.2878421672
Short name T1075
Test name
Test status
Simulation time 22369058 ps
CPU time 1.33 seconds
Started Mar 24 12:41:56 PM PDT 24
Finished Mar 24 12:41:57 PM PDT 24
Peak memory 206000 kb
Host smart-e4c2f0b6-fd20-4d97-8788-29a1d5633fa7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878421672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.2878421672
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.59037967
Short name T1036
Test name
Test status
Simulation time 115342939 ps
CPU time 3.29 seconds
Started Mar 24 12:41:53 PM PDT 24
Finished Mar 24 12:41:57 PM PDT 24
Peak memory 214428 kb
Host smart-2bb536ed-ed7d-48ac-9a9f-422656e24317
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59037967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shadow
_reg_errors.59037967
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.2709695501
Short name T980
Test name
Test status
Simulation time 812017369 ps
CPU time 3.16 seconds
Started Mar 24 12:41:51 PM PDT 24
Finished Mar 24 12:41:55 PM PDT 24
Peak memory 214580 kb
Host smart-7d1d7c97-50a2-4205-85e1-d9eeaad02b70
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2709695501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.2709695501
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.939237360
Short name T1061
Test name
Test status
Simulation time 197752383 ps
CPU time 3.92 seconds
Started Mar 24 12:41:52 PM PDT 24
Finished Mar 24 12:41:56 PM PDT 24
Peak memory 214028 kb
Host smart-878f33a0-bfde-4bda-8e53-45ab23022ff4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=939237360 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.939237360
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.253951608
Short name T158
Test name
Test status
Simulation time 233182304 ps
CPU time 5.23 seconds
Started Mar 24 12:41:53 PM PDT 24
Finished Mar 24 12:41:59 PM PDT 24
Peak memory 214520 kb
Host smart-892d094e-b06e-45a0-8af5-f569f4fde9e3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253951608 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_err
.253951608
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.237845128
Short name T1045
Test name
Test status
Simulation time 38668914 ps
CPU time 2.51 seconds
Started Mar 24 12:41:54 PM PDT 24
Finished Mar 24 12:41:57 PM PDT 24
Peak memory 214020 kb
Host smart-cd8a3a4b-aca4-457e-b29b-4c90b2b449a4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237845128 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.237845128
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.1859236858
Short name T1068
Test name
Test status
Simulation time 14949870 ps
CPU time 1.12 seconds
Started Mar 24 12:41:55 PM PDT 24
Finished Mar 24 12:41:56 PM PDT 24
Peak memory 205984 kb
Host smart-e93853d5-3ba4-47a6-af7f-ea6691502d90
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1859236858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.1859236858
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.452887159
Short name T944
Test name
Test status
Simulation time 13062073 ps
CPU time 0.73 seconds
Started Mar 24 12:41:53 PM PDT 24
Finished Mar 24 12:41:55 PM PDT 24
Peak memory 205768 kb
Host smart-cd4ffd59-b14f-4c1b-bb64-7e89ab6a5210
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=452887159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.452887159
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.937706361
Short name T935
Test name
Test status
Simulation time 95716830 ps
CPU time 1.51 seconds
Started Mar 24 12:41:51 PM PDT 24
Finished Mar 24 12:41:53 PM PDT 24
Peak memory 206016 kb
Host smart-c5a96ecb-1e0a-4839-add3-f41a45095db2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=937706361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_sa
me_csr_outstanding.937706361
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.4239321259
Short name T109
Test name
Test status
Simulation time 314121401 ps
CPU time 5.48 seconds
Started Mar 24 12:41:52 PM PDT 24
Finished Mar 24 12:41:58 PM PDT 24
Peak memory 214480 kb
Host smart-ab2eaeec-ad89-4d93-b1cf-cefebf3c0996
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4239321259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.4239321259
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.2989819294
Short name T143
Test name
Test status
Simulation time 746730296 ps
CPU time 5.24 seconds
Started Mar 24 12:41:57 PM PDT 24
Finished Mar 24 12:42:02 PM PDT 24
Peak memory 220588 kb
Host smart-a0f9fd63-7474-453d-8d9e-5140154e08d6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2989819294 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.2989819294
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.1103799456
Short name T1016
Test name
Test status
Simulation time 397105657 ps
CPU time 3.07 seconds
Started Mar 24 12:41:52 PM PDT 24
Finished Mar 24 12:41:55 PM PDT 24
Peak memory 214076 kb
Host smart-10806d58-c28e-4a3b-8b39-a7771fa1b729
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1103799456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.1103799456
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.2228903265
Short name T1011
Test name
Test status
Simulation time 72688624 ps
CPU time 1.08 seconds
Started Mar 24 12:41:51 PM PDT 24
Finished Mar 24 12:41:52 PM PDT 24
Peak memory 206004 kb
Host smart-a6b60e08-a589-412b-9219-ee6c21d91c53
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2228903265 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.2228903265
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.3691001012
Short name T945
Test name
Test status
Simulation time 84062139 ps
CPU time 1.26 seconds
Started Mar 24 12:41:50 PM PDT 24
Finished Mar 24 12:41:52 PM PDT 24
Peak memory 205852 kb
Host smart-18b8d1a3-f4e2-460d-91bc-35f4de418efc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3691001012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.3691001012
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.3212477015
Short name T1057
Test name
Test status
Simulation time 50298905 ps
CPU time 0.78 seconds
Started Mar 24 12:41:50 PM PDT 24
Finished Mar 24 12:41:51 PM PDT 24
Peak memory 206008 kb
Host smart-623f6481-3982-4fa1-8e8a-3d9510edcaab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3212477015 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.3212477015
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.3402548544
Short name T927
Test name
Test status
Simulation time 49762998 ps
CPU time 2.19 seconds
Started Mar 24 12:41:56 PM PDT 24
Finished Mar 24 12:41:59 PM PDT 24
Peak memory 206084 kb
Host smart-f80df990-d8fa-46e6-bfe3-d90123b48045
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3402548544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s
ame_csr_outstanding.3402548544
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.1257626594
Short name T1015
Test name
Test status
Simulation time 537843525 ps
CPU time 1.99 seconds
Started Mar 24 12:41:53 PM PDT 24
Finished Mar 24 12:41:56 PM PDT 24
Peak memory 214608 kb
Host smart-0de98541-cd23-4b02-b3f8-cf4ca8165965
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257626594 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shad
ow_reg_errors.1257626594
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.1294338685
Short name T956
Test name
Test status
Simulation time 288146516 ps
CPU time 4.29 seconds
Started Mar 24 12:41:56 PM PDT 24
Finished Mar 24 12:42:01 PM PDT 24
Peak memory 220500 kb
Host smart-be5006b4-f1a3-4cce-82a2-d207a2878b17
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294338685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.1294338685
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.3244577252
Short name T1069
Test name
Test status
Simulation time 299090767 ps
CPU time 1.82 seconds
Started Mar 24 12:41:54 PM PDT 24
Finished Mar 24 12:41:56 PM PDT 24
Peak memory 217112 kb
Host smart-196fa780-2457-4201-a42d-b0ce4c3b007d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3244577252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.3244577252
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.1702611321
Short name T951
Test name
Test status
Simulation time 124671103 ps
CPU time 1.74 seconds
Started Mar 24 12:41:52 PM PDT 24
Finished Mar 24 12:41:54 PM PDT 24
Peak memory 214204 kb
Host smart-b807762a-d431-4c31-b586-a6bf6ed5e259
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1702611321 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.1702611321
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.2823319719
Short name T1055
Test name
Test status
Simulation time 19921650 ps
CPU time 0.87 seconds
Started Mar 24 12:41:58 PM PDT 24
Finished Mar 24 12:42:00 PM PDT 24
Peak memory 205688 kb
Host smart-cdc7492f-117c-49a6-9787-dc3985b89447
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823319719 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.2823319719
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.2763129176
Short name T919
Test name
Test status
Simulation time 11715815 ps
CPU time 0.87 seconds
Started Mar 24 12:41:56 PM PDT 24
Finished Mar 24 12:41:57 PM PDT 24
Peak memory 205600 kb
Host smart-35a2356a-9951-488f-97cd-1ae0bae1d261
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763129176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.2763129176
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.3235148283
Short name T938
Test name
Test status
Simulation time 250938506 ps
CPU time 2.06 seconds
Started Mar 24 12:41:54 PM PDT 24
Finished Mar 24 12:41:56 PM PDT 24
Peak memory 205828 kb
Host smart-c2dcff16-df7f-41c8-bc65-c7cc1b1f53d9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235148283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.3235148283
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.2425741122
Short name T1026
Test name
Test status
Simulation time 319025659 ps
CPU time 3.01 seconds
Started Mar 24 12:41:53 PM PDT 24
Finished Mar 24 12:41:57 PM PDT 24
Peak memory 214448 kb
Host smart-1b6d724d-4ad1-4858-bc44-bf9ece8a12d0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2425741122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.2425741122
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.2903139513
Short name T110
Test name
Test status
Simulation time 413444458 ps
CPU time 5.12 seconds
Started Mar 24 12:41:51 PM PDT 24
Finished Mar 24 12:41:56 PM PDT 24
Peak memory 220368 kb
Host smart-cf90aea4-3d2d-4b2e-8448-e2caa84a1830
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2903139513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.2903139513
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.1252077940
Short name T999
Test name
Test status
Simulation time 60212575 ps
CPU time 2.16 seconds
Started Mar 24 12:41:54 PM PDT 24
Finished Mar 24 12:41:56 PM PDT 24
Peak memory 214120 kb
Host smart-a0e5d04f-1d9e-4da5-8d61-cebe282ab0c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1252077940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.1252077940
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.1459660848
Short name T1044
Test name
Test status
Simulation time 56297818 ps
CPU time 1.52 seconds
Started Mar 24 12:42:01 PM PDT 24
Finished Mar 24 12:42:04 PM PDT 24
Peak memory 205972 kb
Host smart-c7774d82-9590-44c5-97be-d8b8931db5ef
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1459660848 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.1459660848
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.4253711025
Short name T970
Test name
Test status
Simulation time 31209937 ps
CPU time 1.51 seconds
Started Mar 24 12:42:00 PM PDT 24
Finished Mar 24 12:42:02 PM PDT 24
Peak memory 205988 kb
Host smart-4f4526c3-ca38-4a1d-9be3-607095169ec4
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4253711025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.4253711025
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.3486874181
Short name T991
Test name
Test status
Simulation time 9314184 ps
CPU time 0.81 seconds
Started Mar 24 12:42:08 PM PDT 24
Finished Mar 24 12:42:09 PM PDT 24
Peak memory 205676 kb
Host smart-a5a5e3f4-9362-472b-9da3-b118cfa3a17f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3486874181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.3486874181
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.3939736998
Short name T1072
Test name
Test status
Simulation time 142590381 ps
CPU time 2.67 seconds
Started Mar 24 12:42:02 PM PDT 24
Finished Mar 24 12:42:05 PM PDT 24
Peak memory 206064 kb
Host smart-98082546-56d1-4ee2-810b-e07019b72c3a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3939736998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.3939736998
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.902612691
Short name T1059
Test name
Test status
Simulation time 1016235077 ps
CPU time 5.38 seconds
Started Mar 24 12:42:02 PM PDT 24
Finished Mar 24 12:42:08 PM PDT 24
Peak memory 214464 kb
Host smart-15ccf9ed-b131-4b5d-b042-4d0fea9b883c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=902612691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shado
w_reg_errors.902612691
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.2977400159
Short name T929
Test name
Test status
Simulation time 434454954 ps
CPU time 4.95 seconds
Started Mar 24 12:41:59 PM PDT 24
Finished Mar 24 12:42:05 PM PDT 24
Peak memory 214488 kb
Host smart-1ae32638-c8c2-4003-8edb-31a2f3062034
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2977400159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.2977400159
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.4009650780
Short name T909
Test name
Test status
Simulation time 205511091 ps
CPU time 2.73 seconds
Started Mar 24 12:42:03 PM PDT 24
Finished Mar 24 12:42:06 PM PDT 24
Peak memory 222304 kb
Host smart-a9621cff-83e8-49b5-a310-36a01c93fb06
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4009650780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.4009650780
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.1499365217
Short name T172
Test name
Test status
Simulation time 670761207 ps
CPU time 4.98 seconds
Started Mar 24 12:42:01 PM PDT 24
Finished Mar 24 12:42:07 PM PDT 24
Peak memory 209284 kb
Host smart-0cfa90d7-86b7-4f89-9cd7-bb8c5f1563e4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499365217 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_er
r.1499365217
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.1645327958
Short name T971
Test name
Test status
Simulation time 324343457 ps
CPU time 1.26 seconds
Started Mar 24 12:42:19 PM PDT 24
Finished Mar 24 12:42:20 PM PDT 24
Peak memory 214184 kb
Host smart-e1bf7054-fd63-4cc0-8f5a-b263f1d48d44
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1645327958 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.1645327958
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.3506830622
Short name T142
Test name
Test status
Simulation time 100031550 ps
CPU time 1.12 seconds
Started Mar 24 12:42:03 PM PDT 24
Finished Mar 24 12:42:05 PM PDT 24
Peak memory 205968 kb
Host smart-c3cac6ab-11af-4a40-9799-51d0fed9d1d1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3506830622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.3506830622
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.3393365464
Short name T1007
Test name
Test status
Simulation time 17334742 ps
CPU time 0.71 seconds
Started Mar 24 12:41:59 PM PDT 24
Finished Mar 24 12:42:02 PM PDT 24
Peak memory 205604 kb
Host smart-23ee6a5f-f970-463e-acb0-87d6f90c4f4f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393365464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.3393365464
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.1083871333
Short name T959
Test name
Test status
Simulation time 18368514 ps
CPU time 1.34 seconds
Started Mar 24 12:42:11 PM PDT 24
Finished Mar 24 12:42:13 PM PDT 24
Peak memory 206072 kb
Host smart-f9293ab3-4467-4c09-9d70-f7d4c41b4b1e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1083871333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.1083871333
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.771517850
Short name T1077
Test name
Test status
Simulation time 2095618708 ps
CPU time 4.79 seconds
Started Mar 24 12:42:05 PM PDT 24
Finished Mar 24 12:42:11 PM PDT 24
Peak memory 222588 kb
Host smart-65c4f3da-aa64-4164-889f-9b298239ef95
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=771517850 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shado
w_reg_errors.771517850
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.1294983096
Short name T948
Test name
Test status
Simulation time 1409311864 ps
CPU time 8.45 seconds
Started Mar 24 12:42:03 PM PDT 24
Finished Mar 24 12:42:12 PM PDT 24
Peak memory 214452 kb
Host smart-ef0040c1-cbc3-4cbd-9de8-a9ba5b235c5a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1294983096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.keymgr_shadow_reg_errors_with_csr_rw.1294983096
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.53674494
Short name T914
Test name
Test status
Simulation time 34714382 ps
CPU time 2.42 seconds
Started Mar 24 12:42:01 PM PDT 24
Finished Mar 24 12:42:05 PM PDT 24
Peak memory 214136 kb
Host smart-4d841509-49cc-4cbe-a21c-bc54ae778dcb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53674494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.53674494
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.1667789421
Short name T955
Test name
Test status
Simulation time 56367676 ps
CPU time 1.06 seconds
Started Mar 24 12:42:11 PM PDT 24
Finished Mar 24 12:42:12 PM PDT 24
Peak memory 205728 kb
Host smart-e1223f16-3385-4533-ae95-29d71265e385
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1667789421 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.1667789421
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.3979899348
Short name T965
Test name
Test status
Simulation time 26621683 ps
CPU time 1.2 seconds
Started Mar 24 12:41:59 PM PDT 24
Finished Mar 24 12:42:01 PM PDT 24
Peak memory 206052 kb
Host smart-e0bd3706-8f5a-444e-b964-1cdd88062bb3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979899348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.3979899348
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.449599405
Short name T908
Test name
Test status
Simulation time 41864870 ps
CPU time 0.73 seconds
Started Mar 24 12:42:02 PM PDT 24
Finished Mar 24 12:42:04 PM PDT 24
Peak memory 205564 kb
Host smart-1f71d839-bd1d-4e6d-a1b5-3a51b44162af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449599405 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.449599405
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.1626438497
Short name T1065
Test name
Test status
Simulation time 435196587 ps
CPU time 3.78 seconds
Started Mar 24 12:42:17 PM PDT 24
Finished Mar 24 12:42:22 PM PDT 24
Peak memory 205924 kb
Host smart-ca9e6bf1-f10c-4f75-8d27-c534d651f176
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1626438497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_s
ame_csr_outstanding.1626438497
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.1971206672
Short name T933
Test name
Test status
Simulation time 463632312 ps
CPU time 5.65 seconds
Started Mar 24 12:42:10 PM PDT 24
Finished Mar 24 12:42:16 PM PDT 24
Peak memory 214552 kb
Host smart-21d1200f-7977-419a-8f40-ce6af4642206
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1971206672 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.1971206672
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.2061420524
Short name T1060
Test name
Test status
Simulation time 378632372 ps
CPU time 13.13 seconds
Started Mar 24 12:42:01 PM PDT 24
Finished Mar 24 12:42:15 PM PDT 24
Peak memory 221040 kb
Host smart-37ef1e59-4488-458e-b34e-89705e72a623
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061420524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.2061420524
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.136183894
Short name T1023
Test name
Test status
Simulation time 102384133 ps
CPU time 2.21 seconds
Started Mar 24 12:42:02 PM PDT 24
Finished Mar 24 12:42:05 PM PDT 24
Peak memory 214208 kb
Host smart-eea5b51e-378c-4048-857a-a1a2624e0f73
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=136183894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.136183894
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.3496029180
Short name T918
Test name
Test status
Simulation time 151382390 ps
CPU time 1.5 seconds
Started Mar 24 12:42:06 PM PDT 24
Finished Mar 24 12:42:08 PM PDT 24
Peak memory 214256 kb
Host smart-f3fed71d-b847-4859-b528-ce527f47b8e0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3496029180 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.3496029180
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.2045661629
Short name T1035
Test name
Test status
Simulation time 116667647 ps
CPU time 1.6 seconds
Started Mar 24 12:42:03 PM PDT 24
Finished Mar 24 12:42:05 PM PDT 24
Peak memory 205920 kb
Host smart-698d1ffd-d888-4857-a7f3-b66a8b70c592
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2045661629 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.2045661629
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.2178320422
Short name T1042
Test name
Test status
Simulation time 11247231 ps
CPU time 0.9 seconds
Started Mar 24 12:42:02 PM PDT 24
Finished Mar 24 12:42:04 PM PDT 24
Peak memory 205604 kb
Host smart-a5fc8f3d-3f25-409b-b348-4417595199ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2178320422 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.2178320422
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.3034654935
Short name T989
Test name
Test status
Simulation time 80918852 ps
CPU time 1.4 seconds
Started Mar 24 12:42:00 PM PDT 24
Finished Mar 24 12:42:02 PM PDT 24
Peak memory 205904 kb
Host smart-6099c819-a9ac-4178-9505-626a050de07d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3034654935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.3034654935
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.3205238803
Short name T1004
Test name
Test status
Simulation time 9567905361 ps
CPU time 54.91 seconds
Started Mar 24 12:42:11 PM PDT 24
Finished Mar 24 12:43:06 PM PDT 24
Peak memory 232096 kb
Host smart-78b82848-b00d-4029-bbfc-0ccbba4f0bab
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3205238803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.3205238803
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.3932845963
Short name T1047
Test name
Test status
Simulation time 1812935189 ps
CPU time 10.17 seconds
Started Mar 24 12:41:59 PM PDT 24
Finished Mar 24 12:42:10 PM PDT 24
Peak memory 214436 kb
Host smart-ab5f0c5d-3560-4b8b-961d-2c5624496f47
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932845963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.3932845963
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.169441184
Short name T975
Test name
Test status
Simulation time 1078015824 ps
CPU time 4.43 seconds
Started Mar 24 12:42:04 PM PDT 24
Finished Mar 24 12:42:09 PM PDT 24
Peak memory 217204 kb
Host smart-0ab3a842-256c-4966-b3f4-1fcd9fb6ae51
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=169441184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.169441184
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.13890022
Short name T930
Test name
Test status
Simulation time 182815735 ps
CPU time 5.02 seconds
Started Mar 24 12:41:38 PM PDT 24
Finished Mar 24 12:41:43 PM PDT 24
Peak memory 206084 kb
Host smart-70751704-6712-40b4-800a-51c6eb382b39
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13890022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.13890022
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.4185057902
Short name T995
Test name
Test status
Simulation time 1737725103 ps
CPU time 12.87 seconds
Started Mar 24 12:41:41 PM PDT 24
Finished Mar 24 12:41:54 PM PDT 24
Peak memory 205868 kb
Host smart-bfdf3981-890b-4142-bc9a-45e499dfccfe
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185057902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.4
185057902
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.2945422686
Short name T1066
Test name
Test status
Simulation time 145146048 ps
CPU time 1.23 seconds
Started Mar 24 12:41:46 PM PDT 24
Finished Mar 24 12:41:47 PM PDT 24
Peak memory 205996 kb
Host smart-8789ae6d-7e8e-4f63-87b0-c1df2d70256c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2945422686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.2
945422686
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.2866509227
Short name T1053
Test name
Test status
Simulation time 37307642 ps
CPU time 1.84 seconds
Started Mar 24 12:41:46 PM PDT 24
Finished Mar 24 12:41:48 PM PDT 24
Peak memory 214332 kb
Host smart-3d3762b6-d7f5-41e8-889a-257e6eb5ea65
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2866509227 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.2866509227
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.3872311065
Short name T1062
Test name
Test status
Simulation time 10413713 ps
CPU time 0.92 seconds
Started Mar 24 12:41:40 PM PDT 24
Finished Mar 24 12:41:41 PM PDT 24
Peak memory 205740 kb
Host smart-bcc94863-d53d-4d8d-a389-1447c3733711
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3872311065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.3872311065
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.4228826780
Short name T981
Test name
Test status
Simulation time 61442672 ps
CPU time 0.75 seconds
Started Mar 24 12:41:44 PM PDT 24
Finished Mar 24 12:41:45 PM PDT 24
Peak memory 205512 kb
Host smart-ebf8dfe3-8784-4b3a-9354-f7c85e265532
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4228826780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.4228826780
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.222353072
Short name T983
Test name
Test status
Simulation time 356989179 ps
CPU time 2.62 seconds
Started Mar 24 12:41:38 PM PDT 24
Finished Mar 24 12:41:41 PM PDT 24
Peak memory 205984 kb
Host smart-8def03be-06bf-42a7-9096-f90036348caf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=222353072 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sam
e_csr_outstanding.222353072
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.4126319859
Short name T106
Test name
Test status
Simulation time 148160426 ps
CPU time 4.46 seconds
Started Mar 24 12:41:40 PM PDT 24
Finished Mar 24 12:41:44 PM PDT 24
Peak memory 214544 kb
Host smart-fd1fd157-d9ee-46a0-bcd5-1204e630ad83
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126319859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.4126319859
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.568021205
Short name T966
Test name
Test status
Simulation time 746545414 ps
CPU time 4.97 seconds
Started Mar 24 12:41:40 PM PDT 24
Finished Mar 24 12:41:45 PM PDT 24
Peak memory 214484 kb
Host smart-56ca05db-2607-44c7-979e-6500d9995006
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=568021205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.k
eymgr_shadow_reg_errors_with_csr_rw.568021205
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.671823511
Short name T993
Test name
Test status
Simulation time 166932817 ps
CPU time 2.41 seconds
Started Mar 24 12:41:35 PM PDT 24
Finished Mar 24 12:41:38 PM PDT 24
Peak memory 214152 kb
Host smart-551703fb-74df-4c64-84bd-6772d93efde4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=671823511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.671823511
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.1522879538
Short name T167
Test name
Test status
Simulation time 1157975517 ps
CPU time 9.65 seconds
Started Mar 24 12:41:37 PM PDT 24
Finished Mar 24 12:41:46 PM PDT 24
Peak memory 214180 kb
Host smart-2517c796-299e-4b1d-8703-35e180fb287c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1522879538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.1522879538
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.965194948
Short name T1020
Test name
Test status
Simulation time 36557302 ps
CPU time 0.78 seconds
Started Mar 24 12:42:00 PM PDT 24
Finished Mar 24 12:42:02 PM PDT 24
Peak memory 205680 kb
Host smart-304faec8-ad57-4442-af8f-7a069e1b8b6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=965194948 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.965194948
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.2751237887
Short name T920
Test name
Test status
Simulation time 36598517 ps
CPU time 0.76 seconds
Started Mar 24 12:42:01 PM PDT 24
Finished Mar 24 12:42:02 PM PDT 24
Peak memory 205628 kb
Host smart-f2bccbc4-d1b1-4a47-8bd0-c501312c30f0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2751237887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.2751237887
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.3286205374
Short name T1056
Test name
Test status
Simulation time 60638487 ps
CPU time 0.87 seconds
Started Mar 24 12:42:07 PM PDT 24
Finished Mar 24 12:42:08 PM PDT 24
Peak memory 205636 kb
Host smart-e9ff7efa-f5e6-4ea8-a271-a29ec4968db2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3286205374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.3286205374
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.1274209207
Short name T968
Test name
Test status
Simulation time 41481215 ps
CPU time 0.83 seconds
Started Mar 24 12:42:14 PM PDT 24
Finished Mar 24 12:42:15 PM PDT 24
Peak memory 205676 kb
Host smart-47b5252f-5a62-44b6-8585-8964126ac6e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1274209207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.1274209207
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.2315535644
Short name T958
Test name
Test status
Simulation time 15265547 ps
CPU time 0.88 seconds
Started Mar 24 12:41:59 PM PDT 24
Finished Mar 24 12:42:01 PM PDT 24
Peak memory 205732 kb
Host smart-362be7a0-d451-4712-9cb1-c1710f4a3cde
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2315535644 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.2315535644
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.2195190123
Short name T1037
Test name
Test status
Simulation time 13816127 ps
CPU time 0.85 seconds
Started Mar 24 12:42:00 PM PDT 24
Finished Mar 24 12:42:02 PM PDT 24
Peak memory 205616 kb
Host smart-6619c804-1230-4aee-aff1-7f0647dc44ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195190123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.2195190123
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.3982592843
Short name T1054
Test name
Test status
Simulation time 18061583 ps
CPU time 0.7 seconds
Started Mar 24 12:42:07 PM PDT 24
Finished Mar 24 12:42:08 PM PDT 24
Peak memory 205548 kb
Host smart-969dba73-f249-4cd2-b509-b351458bd7aa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982592843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.3982592843
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.1884973080
Short name T1078
Test name
Test status
Simulation time 14489184 ps
CPU time 0.84 seconds
Started Mar 24 12:42:04 PM PDT 24
Finished Mar 24 12:42:05 PM PDT 24
Peak memory 205560 kb
Host smart-6374b37c-1a82-4685-b9f4-6860cc6c109d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1884973080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.1884973080
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.756908970
Short name T1051
Test name
Test status
Simulation time 9358365 ps
CPU time 0.83 seconds
Started Mar 24 12:42:03 PM PDT 24
Finished Mar 24 12:42:04 PM PDT 24
Peak memory 205676 kb
Host smart-3b5f90fc-a488-4062-9bea-2a9260097749
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=756908970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.756908970
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.4138396559
Short name T915
Test name
Test status
Simulation time 16758042 ps
CPU time 0.8 seconds
Started Mar 24 12:42:03 PM PDT 24
Finished Mar 24 12:42:04 PM PDT 24
Peak memory 205684 kb
Host smart-fcf9c4a0-8f0c-46b0-8ac4-33eb9f6107e3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138396559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.4138396559
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.1474604501
Short name T985
Test name
Test status
Simulation time 378533417 ps
CPU time 7.25 seconds
Started Mar 24 12:41:46 PM PDT 24
Finished Mar 24 12:41:53 PM PDT 24
Peak memory 205996 kb
Host smart-4a9c0754-4e93-42ad-9eb7-d7a2885df589
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1474604501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.1
474604501
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.2313772560
Short name T994
Test name
Test status
Simulation time 446009359 ps
CPU time 8.97 seconds
Started Mar 24 12:41:43 PM PDT 24
Finished Mar 24 12:41:52 PM PDT 24
Peak memory 206064 kb
Host smart-b44cb10a-3ef4-4063-8af3-a6b2c1ea87ef
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2313772560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.2
313772560
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.2822303375
Short name T194
Test name
Test status
Simulation time 34575461 ps
CPU time 1.59 seconds
Started Mar 24 12:41:40 PM PDT 24
Finished Mar 24 12:41:42 PM PDT 24
Peak memory 206064 kb
Host smart-501b0539-501c-47ad-856e-9b2b63d134ff
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2822303375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.2
822303375
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.1657601735
Short name T1031
Test name
Test status
Simulation time 76336077 ps
CPU time 1.53 seconds
Started Mar 24 12:41:39 PM PDT 24
Finished Mar 24 12:41:41 PM PDT 24
Peak memory 205912 kb
Host smart-daa802fd-84c2-4448-9004-2a62050bbc7e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1657601735 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.1657601735
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.2238902018
Short name T1049
Test name
Test status
Simulation time 31558301 ps
CPU time 1.08 seconds
Started Mar 24 12:41:42 PM PDT 24
Finished Mar 24 12:41:43 PM PDT 24
Peak memory 205988 kb
Host smart-d332fa75-1dc7-44b3-b1e5-8208b919cf00
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2238902018 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.2238902018
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.1184071650
Short name T934
Test name
Test status
Simulation time 38224402 ps
CPU time 0.85 seconds
Started Mar 24 12:41:46 PM PDT 24
Finished Mar 24 12:41:47 PM PDT 24
Peak memory 205676 kb
Host smart-92b97310-4ed9-429a-bf80-420fa2fe6704
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1184071650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.1184071650
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.3876632842
Short name T1043
Test name
Test status
Simulation time 48926002 ps
CPU time 2.08 seconds
Started Mar 24 12:41:41 PM PDT 24
Finished Mar 24 12:41:44 PM PDT 24
Peak memory 205924 kb
Host smart-bd8fb489-4801-4434-9ee0-6b476cf10eca
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3876632842 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.3876632842
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.2012562901
Short name T103
Test name
Test status
Simulation time 67461555 ps
CPU time 2.81 seconds
Started Mar 24 12:41:40 PM PDT 24
Finished Mar 24 12:41:43 PM PDT 24
Peak memory 214496 kb
Host smart-b8f84375-e60c-4abe-974f-a94c52729b90
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2012562901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.2012562901
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.1058611292
Short name T104
Test name
Test status
Simulation time 100542942 ps
CPU time 3.77 seconds
Started Mar 24 12:41:44 PM PDT 24
Finished Mar 24 12:41:48 PM PDT 24
Peak memory 214520 kb
Host smart-9cff7b7e-e8c8-4b52-8535-f2f9a4668395
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1058611292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.1058611292
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.1627367899
Short name T990
Test name
Test status
Simulation time 151952946 ps
CPU time 5.1 seconds
Started Mar 24 12:41:46 PM PDT 24
Finished Mar 24 12:41:51 PM PDT 24
Peak memory 214220 kb
Host smart-509bb4f8-984b-47c5-9fc2-dab75945d4ed
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1627367899 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.1627367899
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.3796044979
Short name T1038
Test name
Test status
Simulation time 14593883 ps
CPU time 0.79 seconds
Started Mar 24 12:42:04 PM PDT 24
Finished Mar 24 12:42:05 PM PDT 24
Peak memory 205676 kb
Host smart-4c5df685-62c6-4f9b-a1a0-788e617584ed
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3796044979 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.3796044979
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.1640595825
Short name T1018
Test name
Test status
Simulation time 11186085 ps
CPU time 0.72 seconds
Started Mar 24 12:42:06 PM PDT 24
Finished Mar 24 12:42:07 PM PDT 24
Peak memory 205624 kb
Host smart-cba08e9d-3f18-4950-8ca2-0563cc52bfe1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640595825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.1640595825
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.4229007267
Short name T917
Test name
Test status
Simulation time 13008520 ps
CPU time 0.93 seconds
Started Mar 24 12:42:02 PM PDT 24
Finished Mar 24 12:42:04 PM PDT 24
Peak memory 205628 kb
Host smart-2a1aa2c7-ee62-4546-b3fd-a97f8d1551f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4229007267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.4229007267
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.317803445
Short name T1050
Test name
Test status
Simulation time 18573316 ps
CPU time 0.73 seconds
Started Mar 24 12:42:04 PM PDT 24
Finished Mar 24 12:42:10 PM PDT 24
Peak memory 205584 kb
Host smart-cc446756-5888-47d6-bdad-d517f9684502
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=317803445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.317803445
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.1960914973
Short name T1067
Test name
Test status
Simulation time 13314835 ps
CPU time 0.75 seconds
Started Mar 24 12:42:03 PM PDT 24
Finished Mar 24 12:42:04 PM PDT 24
Peak memory 205536 kb
Host smart-6193a7b2-fa27-42e2-8c3f-66b8026e4a41
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1960914973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.1960914973
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.339043344
Short name T950
Test name
Test status
Simulation time 16282183 ps
CPU time 0.78 seconds
Started Mar 24 12:42:02 PM PDT 24
Finished Mar 24 12:42:04 PM PDT 24
Peak memory 205600 kb
Host smart-6bb78043-d1e6-4684-937b-f74cb2973152
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=339043344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.339043344
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.1098937880
Short name T912
Test name
Test status
Simulation time 15363965 ps
CPU time 0.88 seconds
Started Mar 24 12:42:02 PM PDT 24
Finished Mar 24 12:42:04 PM PDT 24
Peak memory 205676 kb
Host smart-efad2532-a6b9-4902-9bb3-930805cbc62e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1098937880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.1098937880
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.3987422863
Short name T1012
Test name
Test status
Simulation time 14336345 ps
CPU time 0.91 seconds
Started Mar 24 12:42:09 PM PDT 24
Finished Mar 24 12:42:10 PM PDT 24
Peak memory 205772 kb
Host smart-44f9d3d1-cfc6-4dad-ab2d-8fafdc3d4d42
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3987422863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.3987422863
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.1050373558
Short name T1010
Test name
Test status
Simulation time 25859451 ps
CPU time 0.79 seconds
Started Mar 24 12:42:00 PM PDT 24
Finished Mar 24 12:42:01 PM PDT 24
Peak memory 205656 kb
Host smart-68208dfe-7850-4be3-8f36-76d2f2634271
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1050373558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.1050373558
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.3130946839
Short name T960
Test name
Test status
Simulation time 61058388 ps
CPU time 0.86 seconds
Started Mar 24 12:42:02 PM PDT 24
Finished Mar 24 12:42:04 PM PDT 24
Peak memory 205676 kb
Host smart-c814f156-43f4-453c-8a4e-1e49408beaf4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3130946839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.3130946839
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.3332910326
Short name T963
Test name
Test status
Simulation time 366460220 ps
CPU time 13.67 seconds
Started Mar 24 12:41:40 PM PDT 24
Finished Mar 24 12:41:54 PM PDT 24
Peak memory 205976 kb
Host smart-05052f81-a378-45dc-b000-e3a5f45794bb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3332910326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.3
332910326
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.2385508207
Short name T1019
Test name
Test status
Simulation time 2692522933 ps
CPU time 16.92 seconds
Started Mar 24 12:41:44 PM PDT 24
Finished Mar 24 12:42:01 PM PDT 24
Peak memory 205884 kb
Host smart-c64e773a-562b-4b10-9784-5377cc71779f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2385508207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.2
385508207
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.3007385936
Short name T1030
Test name
Test status
Simulation time 59832801 ps
CPU time 1.49 seconds
Started Mar 24 12:41:40 PM PDT 24
Finished Mar 24 12:41:41 PM PDT 24
Peak memory 205968 kb
Host smart-f5bfdc3c-5e09-4b8b-b1e5-579c2d063985
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3007385936 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.3
007385936
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.4219177565
Short name T952
Test name
Test status
Simulation time 165981373 ps
CPU time 2.05 seconds
Started Mar 24 12:41:42 PM PDT 24
Finished Mar 24 12:41:45 PM PDT 24
Peak memory 214188 kb
Host smart-93497549-4add-4556-862e-d665caaea540
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4219177565 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.4219177565
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.1830112669
Short name T924
Test name
Test status
Simulation time 148675911 ps
CPU time 1.05 seconds
Started Mar 24 12:41:43 PM PDT 24
Finished Mar 24 12:41:44 PM PDT 24
Peak memory 205784 kb
Host smart-3107e719-fff5-432f-b004-755393114860
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830112669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.1830112669
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.291749680
Short name T964
Test name
Test status
Simulation time 26871742 ps
CPU time 0.89 seconds
Started Mar 24 12:41:41 PM PDT 24
Finished Mar 24 12:41:42 PM PDT 24
Peak memory 206216 kb
Host smart-d85f58a6-51e8-4dd2-bffc-d701ce46948a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=291749680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.291749680
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.1194252449
Short name T984
Test name
Test status
Simulation time 72683599 ps
CPU time 2.07 seconds
Started Mar 24 12:41:41 PM PDT 24
Finished Mar 24 12:41:43 PM PDT 24
Peak memory 205908 kb
Host smart-178e961e-1027-4f26-9efb-147992d47c86
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1194252449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.1194252449
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.1335697615
Short name T936
Test name
Test status
Simulation time 1021350606 ps
CPU time 5.93 seconds
Started Mar 24 12:41:42 PM PDT 24
Finished Mar 24 12:41:48 PM PDT 24
Peak memory 214508 kb
Host smart-a7f617fe-cfa1-419e-8858-7ea6d856154f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1335697615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.1335697615
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.1698482299
Short name T1022
Test name
Test status
Simulation time 696412644 ps
CPU time 4.55 seconds
Started Mar 24 12:41:42 PM PDT 24
Finished Mar 24 12:41:47 PM PDT 24
Peak memory 220312 kb
Host smart-89d725a0-7bf0-450f-bbf6-7b2b0c220cf9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1698482299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.1698482299
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.952987351
Short name T954
Test name
Test status
Simulation time 110654172 ps
CPU time 2.2 seconds
Started Mar 24 12:41:41 PM PDT 24
Finished Mar 24 12:41:44 PM PDT 24
Peak memory 214140 kb
Host smart-6d33ff20-d655-487a-be26-d427dbedfb07
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952987351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.952987351
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.1716526274
Short name T163
Test name
Test status
Simulation time 240283518 ps
CPU time 3.27 seconds
Started Mar 24 12:41:41 PM PDT 24
Finished Mar 24 12:41:44 PM PDT 24
Peak memory 209300 kb
Host smart-7e3ca032-ad9f-4c53-90b8-5b8bcac0a2ed
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716526274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.1716526274
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.4270661480
Short name T974
Test name
Test status
Simulation time 41690504 ps
CPU time 0.82 seconds
Started Mar 24 12:42:02 PM PDT 24
Finished Mar 24 12:42:04 PM PDT 24
Peak memory 205552 kb
Host smart-68d2b586-98f1-4f03-a01a-9f9fb13da7f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4270661480 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.4270661480
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.314723896
Short name T910
Test name
Test status
Simulation time 13217079 ps
CPU time 0.88 seconds
Started Mar 24 12:41:59 PM PDT 24
Finished Mar 24 12:42:01 PM PDT 24
Peak memory 205756 kb
Host smart-c85f17fc-a8a5-4e7d-92fd-803d12018b63
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=314723896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.314723896
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.2752396280
Short name T931
Test name
Test status
Simulation time 59705953 ps
CPU time 0.75 seconds
Started Mar 24 12:42:06 PM PDT 24
Finished Mar 24 12:42:07 PM PDT 24
Peak memory 205656 kb
Host smart-2e4e6db8-2499-4959-8432-406aa577f3b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2752396280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.2752396280
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.120672020
Short name T969
Test name
Test status
Simulation time 43910028 ps
CPU time 0.81 seconds
Started Mar 24 12:42:04 PM PDT 24
Finished Mar 24 12:42:05 PM PDT 24
Peak memory 206004 kb
Host smart-a03333d6-8ec5-4a9c-a4b9-c24bb4693988
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=120672020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.120672020
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.235091034
Short name T1073
Test name
Test status
Simulation time 38449571 ps
CPU time 0.79 seconds
Started Mar 24 12:42:03 PM PDT 24
Finished Mar 24 12:42:04 PM PDT 24
Peak memory 205684 kb
Host smart-61cdfec7-80f5-4796-a996-6a2eaeabf6c1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=235091034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.235091034
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.85569152
Short name T1040
Test name
Test status
Simulation time 63456085 ps
CPU time 0.77 seconds
Started Mar 24 12:42:02 PM PDT 24
Finished Mar 24 12:42:04 PM PDT 24
Peak memory 205676 kb
Host smart-3aa4d0c4-8e35-4206-9b21-4285e6c36a17
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85569152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.85569152
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.2845990569
Short name T1008
Test name
Test status
Simulation time 70528316 ps
CPU time 0.85 seconds
Started Mar 24 12:42:02 PM PDT 24
Finished Mar 24 12:42:04 PM PDT 24
Peak memory 205680 kb
Host smart-5ca38810-c251-4660-87fd-da29fea6283a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2845990569 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.2845990569
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.1908528553
Short name T916
Test name
Test status
Simulation time 12192084 ps
CPU time 0.78 seconds
Started Mar 24 12:42:05 PM PDT 24
Finished Mar 24 12:42:06 PM PDT 24
Peak memory 205664 kb
Host smart-02439686-4606-4f3f-a9e8-5c192670fd57
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1908528553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.1908528553
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.1847127732
Short name T911
Test name
Test status
Simulation time 9367664 ps
CPU time 0.77 seconds
Started Mar 24 12:42:05 PM PDT 24
Finished Mar 24 12:42:06 PM PDT 24
Peak memory 205620 kb
Host smart-0ec12b41-633b-482d-bf0f-e91791338ff6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847127732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.1847127732
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.177187051
Short name T939
Test name
Test status
Simulation time 21798833 ps
CPU time 0.72 seconds
Started Mar 24 12:42:06 PM PDT 24
Finished Mar 24 12:42:07 PM PDT 24
Peak memory 205628 kb
Host smart-72b8258d-67f9-4cc7-9b47-d9d6f1b9354c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177187051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.177187051
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.141489772
Short name T953
Test name
Test status
Simulation time 137465566 ps
CPU time 1.49 seconds
Started Mar 24 12:41:46 PM PDT 24
Finished Mar 24 12:41:47 PM PDT 24
Peak memory 217624 kb
Host smart-faf17776-0b9d-4c64-8105-1ebf52daaa16
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=141489772 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.141489772
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.820127267
Short name T947
Test name
Test status
Simulation time 17733290 ps
CPU time 1.18 seconds
Started Mar 24 12:41:47 PM PDT 24
Finished Mar 24 12:41:49 PM PDT 24
Peak memory 205980 kb
Host smart-1552e3d7-ea5d-45ca-aefb-15cfb7720208
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=820127267 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.820127267
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.1679205705
Short name T1064
Test name
Test status
Simulation time 23654550 ps
CPU time 0.69 seconds
Started Mar 24 12:41:47 PM PDT 24
Finished Mar 24 12:41:48 PM PDT 24
Peak memory 205672 kb
Host smart-efdbbbd8-7564-414d-96dc-6d8746de200d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1679205705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.1679205705
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.359772760
Short name T937
Test name
Test status
Simulation time 91668809 ps
CPU time 3.74 seconds
Started Mar 24 12:41:53 PM PDT 24
Finished Mar 24 12:41:57 PM PDT 24
Peak memory 206332 kb
Host smart-154b09d1-18ab-45f1-9d1d-004070d0fdf1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=359772760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sam
e_csr_outstanding.359772760
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.45807436
Short name T957
Test name
Test status
Simulation time 111867211 ps
CPU time 3.78 seconds
Started Mar 24 12:41:56 PM PDT 24
Finished Mar 24 12:42:00 PM PDT 24
Peak memory 214424 kb
Host smart-fa3fb98e-3808-490e-9c65-dc7745720d05
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45807436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shadow_
reg_errors.45807436
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.709588472
Short name T145
Test name
Test status
Simulation time 246079285 ps
CPU time 5.63 seconds
Started Mar 24 12:41:59 PM PDT 24
Finished Mar 24 12:42:05 PM PDT 24
Peak memory 214548 kb
Host smart-b3b8145a-89b3-43c7-b07a-79756edd384b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=709588472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.k
eymgr_shadow_reg_errors_with_csr_rw.709588472
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.3624689696
Short name T913
Test name
Test status
Simulation time 130679944 ps
CPU time 4.14 seconds
Started Mar 24 12:41:50 PM PDT 24
Finished Mar 24 12:41:55 PM PDT 24
Peak memory 214104 kb
Host smart-9f308e89-d596-409d-a917-249ba68cb157
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624689696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.3624689696
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.3327571739
Short name T923
Test name
Test status
Simulation time 107119157 ps
CPU time 1.86 seconds
Started Mar 24 12:41:45 PM PDT 24
Finished Mar 24 12:41:47 PM PDT 24
Peak memory 214252 kb
Host smart-de61954b-2c2b-41bf-93a0-66c7cbaf09f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3327571739 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.3327571739
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.1380069879
Short name T1024
Test name
Test status
Simulation time 124245651 ps
CPU time 1.28 seconds
Started Mar 24 12:41:46 PM PDT 24
Finished Mar 24 12:41:47 PM PDT 24
Peak memory 205860 kb
Host smart-25b28b6f-8ab2-484d-8022-cb35420ef603
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380069879 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.1380069879
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.1508074432
Short name T942
Test name
Test status
Simulation time 41833633 ps
CPU time 0.71 seconds
Started Mar 24 12:41:47 PM PDT 24
Finished Mar 24 12:41:48 PM PDT 24
Peak memory 205604 kb
Host smart-e20edad9-1470-46fc-b4db-2ba9d8c9bb95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508074432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.1508074432
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.4173404381
Short name T1002
Test name
Test status
Simulation time 360488759 ps
CPU time 1.95 seconds
Started Mar 24 12:41:45 PM PDT 24
Finished Mar 24 12:41:47 PM PDT 24
Peak memory 205968 kb
Host smart-90080677-5078-44fe-b18b-1616ab34ca4f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4173404381 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.4173404381
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.2314036124
Short name T1021
Test name
Test status
Simulation time 747241922 ps
CPU time 5.48 seconds
Started Mar 24 12:41:44 PM PDT 24
Finished Mar 24 12:41:50 PM PDT 24
Peak memory 214460 kb
Host smart-d5f86e42-62fc-4a76-b16c-af7f1403e894
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314036124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.2314036124
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.2825112432
Short name T108
Test name
Test status
Simulation time 1707632271 ps
CPU time 8.29 seconds
Started Mar 24 12:41:59 PM PDT 24
Finished Mar 24 12:42:08 PM PDT 24
Peak memory 220556 kb
Host smart-c0ea1c82-7618-4fc1-8f55-7427f3cb6e30
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825112432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
keymgr_shadow_reg_errors_with_csr_rw.2825112432
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.3389203500
Short name T961
Test name
Test status
Simulation time 164794425 ps
CPU time 1.89 seconds
Started Mar 24 12:41:46 PM PDT 24
Finished Mar 24 12:41:48 PM PDT 24
Peak memory 214160 kb
Host smart-5f84fc1e-e459-4dab-bbf3-8d4572967738
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3389203500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.3389203500
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.1816288761
Short name T982
Test name
Test status
Simulation time 797826640 ps
CPU time 8.7 seconds
Started Mar 24 12:41:48 PM PDT 24
Finished Mar 24 12:41:56 PM PDT 24
Peak memory 214176 kb
Host smart-fe0f93e4-b617-4b1a-b86c-319d1a258c85
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1816288761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.1816288761
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.4223754116
Short name T1025
Test name
Test status
Simulation time 229548164 ps
CPU time 1.8 seconds
Started Mar 24 12:41:47 PM PDT 24
Finished Mar 24 12:41:49 PM PDT 24
Peak memory 214056 kb
Host smart-ff01d082-aabe-4105-ae40-d30121aaa6f4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4223754116 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.4223754116
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.3596264388
Short name T1071
Test name
Test status
Simulation time 71924583 ps
CPU time 1.23 seconds
Started Mar 24 12:41:59 PM PDT 24
Finished Mar 24 12:42:01 PM PDT 24
Peak memory 205904 kb
Host smart-76539f45-4e27-4567-8149-a80fabe122c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596264388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.3596264388
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.3490744832
Short name T1070
Test name
Test status
Simulation time 12530465 ps
CPU time 0.76 seconds
Started Mar 24 12:41:49 PM PDT 24
Finished Mar 24 12:41:50 PM PDT 24
Peak memory 205616 kb
Host smart-76ceee00-95ce-42bb-a925-51977c10375d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3490744832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.3490744832
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.3653042669
Short name T996
Test name
Test status
Simulation time 281449027 ps
CPU time 1.88 seconds
Started Mar 24 12:41:46 PM PDT 24
Finished Mar 24 12:41:48 PM PDT 24
Peak memory 206016 kb
Host smart-6d43e41f-da9d-4c66-8064-c6445eac5eee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3653042669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.3653042669
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.2681556384
Short name T977
Test name
Test status
Simulation time 226240095 ps
CPU time 4.43 seconds
Started Mar 24 12:41:59 PM PDT 24
Finished Mar 24 12:42:04 PM PDT 24
Peak memory 214520 kb
Host smart-630ed6da-8326-4eab-b0a3-56610cae0707
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2681556384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.2681556384
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.165490650
Short name T943
Test name
Test status
Simulation time 87350334 ps
CPU time 4.13 seconds
Started Mar 24 12:41:45 PM PDT 24
Finished Mar 24 12:41:49 PM PDT 24
Peak memory 214492 kb
Host smart-5623b573-a777-477b-bd59-0b5e7a2b6068
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=165490650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.k
eymgr_shadow_reg_errors_with_csr_rw.165490650
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.2321205136
Short name T1063
Test name
Test status
Simulation time 631484412 ps
CPU time 5.4 seconds
Started Mar 24 12:41:52 PM PDT 24
Finished Mar 24 12:41:59 PM PDT 24
Peak memory 214440 kb
Host smart-6a134fe2-0cfc-4377-bed9-ba8491630e9e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2321205136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.2321205136
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.87138937
Short name T1014
Test name
Test status
Simulation time 209303507 ps
CPU time 2.21 seconds
Started Mar 24 12:41:45 PM PDT 24
Finished Mar 24 12:41:48 PM PDT 24
Peak memory 214160 kb
Host smart-bb58f050-5226-497b-a254-5d134cb4aaf6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87138937 -assert nopostproc +UVM_TESTNAME=k
eymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.87138937
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.781461669
Short name T921
Test name
Test status
Simulation time 33608908 ps
CPU time 0.92 seconds
Started Mar 24 12:41:49 PM PDT 24
Finished Mar 24 12:41:50 PM PDT 24
Peak memory 205584 kb
Host smart-6a3d8161-1f82-4ce2-a96f-2b1fd376269e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=781461669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.781461669
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.1049866130
Short name T1027
Test name
Test status
Simulation time 53152615 ps
CPU time 0.9 seconds
Started Mar 24 12:41:48 PM PDT 24
Finished Mar 24 12:41:49 PM PDT 24
Peak memory 205768 kb
Host smart-bd1ba45f-1414-4246-bd60-15e2fba951ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1049866130 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.1049866130
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.1672006424
Short name T988
Test name
Test status
Simulation time 264080440 ps
CPU time 1.98 seconds
Started Mar 24 12:41:48 PM PDT 24
Finished Mar 24 12:41:50 PM PDT 24
Peak memory 205992 kb
Host smart-ed3728bf-b791-433a-90d7-f200dec0968f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1672006424 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sa
me_csr_outstanding.1672006424
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.1721713921
Short name T1017
Test name
Test status
Simulation time 200801441 ps
CPU time 5.17 seconds
Started Mar 24 12:41:47 PM PDT 24
Finished Mar 24 12:41:53 PM PDT 24
Peak memory 214456 kb
Host smart-77e7a533-b9bc-4ca7-bbed-b84fc8ef1bf9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721713921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shado
w_reg_errors.1721713921
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.1216599295
Short name T992
Test name
Test status
Simulation time 496879666 ps
CPU time 3.53 seconds
Started Mar 24 12:41:56 PM PDT 24
Finished Mar 24 12:42:00 PM PDT 24
Peak memory 214216 kb
Host smart-416c689d-d5a3-4a53-b261-dd34eb6c10d2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1216599295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.1216599295
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.2203570045
Short name T168
Test name
Test status
Simulation time 2796684450 ps
CPU time 5.85 seconds
Started Mar 24 12:41:47 PM PDT 24
Finished Mar 24 12:41:54 PM PDT 24
Peak memory 209668 kb
Host smart-62f6daab-03cc-45fd-b501-dbccf3da177c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2203570045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.2203570045
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.1737282779
Short name T986
Test name
Test status
Simulation time 53855382 ps
CPU time 2.21 seconds
Started Mar 24 12:41:56 PM PDT 24
Finished Mar 24 12:41:58 PM PDT 24
Peak memory 214192 kb
Host smart-63c88051-bc2b-4af4-b82c-2a035bd1c3ec
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1737282779 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.1737282779
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.303948534
Short name T946
Test name
Test status
Simulation time 36189699 ps
CPU time 0.98 seconds
Started Mar 24 12:41:50 PM PDT 24
Finished Mar 24 12:41:51 PM PDT 24
Peak memory 205728 kb
Host smart-35b5c2f9-0063-43e9-b951-d8b7122266ea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=303948534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.303948534
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.3139009116
Short name T940
Test name
Test status
Simulation time 38173983 ps
CPU time 0.68 seconds
Started Mar 24 12:41:51 PM PDT 24
Finished Mar 24 12:41:52 PM PDT 24
Peak memory 205688 kb
Host smart-01db23fe-3eea-45b1-b213-768d533d8551
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3139009116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.3139009116
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.2750128114
Short name T1033
Test name
Test status
Simulation time 176319870 ps
CPU time 1.52 seconds
Started Mar 24 12:41:56 PM PDT 24
Finished Mar 24 12:41:58 PM PDT 24
Peak memory 205980 kb
Host smart-63d5644a-256a-4fa3-850c-efc1834a0c73
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2750128114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.2750128114
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.1648381147
Short name T107
Test name
Test status
Simulation time 5232987042 ps
CPU time 10.52 seconds
Started Mar 24 12:41:49 PM PDT 24
Finished Mar 24 12:41:59 PM PDT 24
Peak memory 214472 kb
Host smart-d1800585-f4cc-424f-ad8f-e74ce65b310d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1648381147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.1648381147
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.3529245877
Short name T928
Test name
Test status
Simulation time 1495791775 ps
CPU time 15.76 seconds
Started Mar 24 12:41:53 PM PDT 24
Finished Mar 24 12:42:09 PM PDT 24
Peak memory 214828 kb
Host smart-a35f45c6-061c-4963-a199-2ac145403365
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3529245877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
keymgr_shadow_reg_errors_with_csr_rw.3529245877
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.1440670116
Short name T1028
Test name
Test status
Simulation time 73705280 ps
CPU time 1.95 seconds
Started Mar 24 12:41:50 PM PDT 24
Finished Mar 24 12:41:52 PM PDT 24
Peak memory 214160 kb
Host smart-38ce9d88-4631-4e40-914e-7af1aa87ae2e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1440670116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.1440670116
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.3275465673
Short name T654
Test name
Test status
Simulation time 11807149 ps
CPU time 0.78 seconds
Started Mar 24 01:49:58 PM PDT 24
Finished Mar 24 01:50:00 PM PDT 24
Peak memory 206432 kb
Host smart-9776bf5a-57b0-43c5-9eaf-952ec071984e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3275465673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.3275465673
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.492558489
Short name T758
Test name
Test status
Simulation time 33841128 ps
CPU time 2.55 seconds
Started Mar 24 01:49:43 PM PDT 24
Finished Mar 24 01:49:45 PM PDT 24
Peak memory 215700 kb
Host smart-06616f29-4e2a-435d-90c4-2bb37a5f6d09
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=492558489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.492558489
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.1735272301
Short name T703
Test name
Test status
Simulation time 2996695050 ps
CPU time 14.43 seconds
Started Mar 24 01:49:48 PM PDT 24
Finished Mar 24 01:50:03 PM PDT 24
Peak memory 217244 kb
Host smart-e8a62a8f-844a-4179-903c-2de15e058829
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735272301 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.1735272301
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.381832368
Short name T753
Test name
Test status
Simulation time 80304720 ps
CPU time 2.5 seconds
Started Mar 24 01:49:46 PM PDT 24
Finished Mar 24 01:49:48 PM PDT 24
Peak memory 208304 kb
Host smart-a4a5ad78-a14c-486d-8557-03831ff9e978
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381832368 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.381832368
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.3824336529
Short name T649
Test name
Test status
Simulation time 79578046 ps
CPU time 3.59 seconds
Started Mar 24 01:49:50 PM PDT 24
Finished Mar 24 01:49:54 PM PDT 24
Peak memory 210916 kb
Host smart-f8b51234-9c70-45fe-b6a9-43c91388db06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3824336529 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.3824336529
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.503848886
Short name T779
Test name
Test status
Simulation time 5625132921 ps
CPU time 9.67 seconds
Started Mar 24 01:49:48 PM PDT 24
Finished Mar 24 01:49:58 PM PDT 24
Peak memory 216964 kb
Host smart-2e3db38e-80ff-483e-ac5f-941bed3fd068
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=503848886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.503848886
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.487869805
Short name T538
Test name
Test status
Simulation time 450567134 ps
CPU time 4.5 seconds
Started Mar 24 01:49:45 PM PDT 24
Finished Mar 24 01:49:49 PM PDT 24
Peak memory 221384 kb
Host smart-813ba598-683a-4267-8d33-c1f5da20bfe1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487869805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.487869805
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.641926490
Short name T620
Test name
Test status
Simulation time 19857892988 ps
CPU time 64.9 seconds
Started Mar 24 01:49:46 PM PDT 24
Finished Mar 24 01:50:51 PM PDT 24
Peak memory 209852 kb
Host smart-9ae6c0e7-d827-477e-88a4-8456cc6b9b37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=641926490 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.641926490
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sideload.169093686
Short name T880
Test name
Test status
Simulation time 203162379 ps
CPU time 3.35 seconds
Started Mar 24 01:49:39 PM PDT 24
Finished Mar 24 01:49:43 PM PDT 24
Peak memory 207144 kb
Host smart-6ab968f4-bc2c-4524-ab9d-4ebdb223cc3b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=169093686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.169093686
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.440840702
Short name T541
Test name
Test status
Simulation time 360407551 ps
CPU time 4.68 seconds
Started Mar 24 01:49:39 PM PDT 24
Finished Mar 24 01:49:44 PM PDT 24
Peak memory 207304 kb
Host smart-d6c2696e-0782-4ef7-af32-c88f6323fc61
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=440840702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.440840702
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.3317742906
Short name T537
Test name
Test status
Simulation time 142583832 ps
CPU time 3.06 seconds
Started Mar 24 01:49:41 PM PDT 24
Finished Mar 24 01:49:44 PM PDT 24
Peak memory 209044 kb
Host smart-1853a845-86b4-44e2-b267-dec4ac7a8241
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3317742906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.3317742906
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.690005136
Short name T712
Test name
Test status
Simulation time 190100074 ps
CPU time 3.66 seconds
Started Mar 24 01:49:52 PM PDT 24
Finished Mar 24 01:49:56 PM PDT 24
Peak memory 218636 kb
Host smart-f93686f1-c49b-4a94-8266-fac979897130
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=690005136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.690005136
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.2609827720
Short name T548
Test name
Test status
Simulation time 33586988 ps
CPU time 1.84 seconds
Started Mar 24 01:49:39 PM PDT 24
Finished Mar 24 01:49:40 PM PDT 24
Peak memory 208720 kb
Host smart-1735be07-8a69-4949-bbe9-6a65f5864478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2609827720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.2609827720
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.3907196156
Short name T61
Test name
Test status
Simulation time 1274623018 ps
CPU time 27.33 seconds
Started Mar 24 01:49:53 PM PDT 24
Finished Mar 24 01:50:20 PM PDT 24
Peak memory 217432 kb
Host smart-ed4e4580-30c8-48f7-b1e5-9b0fb03d48ff
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3907196156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.3907196156
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.974436155
Short name T481
Test name
Test status
Simulation time 275082917 ps
CPU time 8.6 seconds
Started Mar 24 01:49:44 PM PDT 24
Finished Mar 24 01:49:53 PM PDT 24
Peak memory 208824 kb
Host smart-630c452e-5edf-4783-a790-b0e01421f8a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974436155 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.974436155
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.323838902
Short name T700
Test name
Test status
Simulation time 8172098441 ps
CPU time 30.3 seconds
Started Mar 24 01:49:53 PM PDT 24
Finished Mar 24 01:50:23 PM PDT 24
Peak memory 212080 kb
Host smart-73c69937-0247-4d07-92e0-15dc09ed1cb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=323838902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.323838902
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.2479011113
Short name T521
Test name
Test status
Simulation time 17298027 ps
CPU time 0.76 seconds
Started Mar 24 01:50:13 PM PDT 24
Finished Mar 24 01:50:13 PM PDT 24
Peak memory 206372 kb
Host smart-cf792557-297f-4628-9577-7aa106edd1c5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479011113 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.2479011113
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.1530245446
Short name T21
Test name
Test status
Simulation time 2803965184 ps
CPU time 5.86 seconds
Started Mar 24 01:50:14 PM PDT 24
Finished Mar 24 01:50:20 PM PDT 24
Peak memory 215444 kb
Host smart-ffb0b19b-59b0-48e8-9e7f-b74cd2e221ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530245446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.1530245446
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.3935572468
Short name T726
Test name
Test status
Simulation time 353444829 ps
CPU time 12.61 seconds
Started Mar 24 01:50:14 PM PDT 24
Finished Mar 24 01:50:27 PM PDT 24
Peak memory 214752 kb
Host smart-b3696198-6dbb-47ab-9c7a-e6e5e679ef92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935572468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.3935572468
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.1032140962
Short name T80
Test name
Test status
Simulation time 414354867 ps
CPU time 5.3 seconds
Started Mar 24 01:50:13 PM PDT 24
Finished Mar 24 01:50:19 PM PDT 24
Peak memory 218908 kb
Host smart-e07beed4-1178-4ca3-a2c0-200dbc43cddb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1032140962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.1032140962
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.4162976215
Short name T672
Test name
Test status
Simulation time 98625373 ps
CPU time 4.34 seconds
Started Mar 24 01:50:13 PM PDT 24
Finished Mar 24 01:50:18 PM PDT 24
Peak memory 209780 kb
Host smart-fe72f8dd-f5e4-4d2b-96f0-6327c8c17df6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4162976215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.4162976215
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.369300493
Short name T628
Test name
Test status
Simulation time 501918239 ps
CPU time 5.63 seconds
Started Mar 24 01:50:08 PM PDT 24
Finished Mar 24 01:50:14 PM PDT 24
Peak memory 208528 kb
Host smart-a23f9798-4e6b-4cee-bb11-d9bc056fe4d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=369300493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.369300493
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.338876919
Short name T13
Test name
Test status
Simulation time 742949954 ps
CPU time 23.26 seconds
Started Mar 24 01:50:14 PM PDT 24
Finished Mar 24 01:50:37 PM PDT 24
Peak memory 233316 kb
Host smart-e6ed603b-526f-4ebd-80fc-c04104d63bd0
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=338876919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.338876919
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload.3298649029
Short name T299
Test name
Test status
Simulation time 604213472 ps
CPU time 3.17 seconds
Started Mar 24 01:50:07 PM PDT 24
Finished Mar 24 01:50:10 PM PDT 24
Peak memory 207172 kb
Host smart-25428e54-6519-46ef-ac58-6351dda1e7c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298649029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.3298649029
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.3966566831
Short name T808
Test name
Test status
Simulation time 272803380 ps
CPU time 3.26 seconds
Started Mar 24 01:50:07 PM PDT 24
Finished Mar 24 01:50:10 PM PDT 24
Peak memory 207292 kb
Host smart-d3597deb-096e-40e5-ae17-5ea883e16d4c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966566831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.3966566831
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.4217703681
Short name T330
Test name
Test status
Simulation time 42074759 ps
CPU time 2.5 seconds
Started Mar 24 01:50:04 PM PDT 24
Finished Mar 24 01:50:06 PM PDT 24
Peak memory 208388 kb
Host smart-6a23e7d9-eeb0-45b0-bc81-52eaab005908
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217703681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.4217703681
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.1879738464
Short name T882
Test name
Test status
Simulation time 921470354 ps
CPU time 9.3 seconds
Started Mar 24 01:50:08 PM PDT 24
Finished Mar 24 01:50:17 PM PDT 24
Peak memory 209600 kb
Host smart-0ac57d5b-f211-4fcc-aecd-3d4483200ef4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1879738464 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.1879738464
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.805300524
Short name T417
Test name
Test status
Simulation time 13869916 ps
CPU time 1.4 seconds
Started Mar 24 01:50:12 PM PDT 24
Finished Mar 24 01:50:13 PM PDT 24
Peak memory 207572 kb
Host smart-e1cf42d0-9173-4019-ad66-ed686f1da3af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805300524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.805300524
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.2935799754
Short name T728
Test name
Test status
Simulation time 80631591 ps
CPU time 1.94 seconds
Started Mar 24 01:50:04 PM PDT 24
Finished Mar 24 01:50:07 PM PDT 24
Peak memory 208860 kb
Host smart-a481d727-2784-46cf-8036-dba384365203
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2935799754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.2935799754
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.1510314671
Short name T293
Test name
Test status
Simulation time 407128246 ps
CPU time 9.49 seconds
Started Mar 24 01:50:13 PM PDT 24
Finished Mar 24 01:50:22 PM PDT 24
Peak memory 207732 kb
Host smart-4ff29f87-9384-4402-b505-15d0fc9a2a72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1510314671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.1510314671
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.2792196413
Short name T54
Test name
Test status
Simulation time 49439068 ps
CPU time 2.67 seconds
Started Mar 24 01:50:13 PM PDT 24
Finished Mar 24 01:50:17 PM PDT 24
Peak memory 210200 kb
Host smart-0ed5f785-bec0-4d6d-9a2d-adf1164830e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2792196413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.2792196413
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.2653989496
Short name T460
Test name
Test status
Simulation time 14738385 ps
CPU time 0.79 seconds
Started Mar 24 01:51:34 PM PDT 24
Finished Mar 24 01:51:35 PM PDT 24
Peak memory 206432 kb
Host smart-40a5c33d-2bbc-4ba5-b2a5-480b5d84aeaf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2653989496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.2653989496
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.2048973029
Short name T591
Test name
Test status
Simulation time 1062261827 ps
CPU time 40.3 seconds
Started Mar 24 01:51:28 PM PDT 24
Finished Mar 24 01:52:09 PM PDT 24
Peak memory 222912 kb
Host smart-e38a1a86-3475-4123-8fbe-efe8bff8a50a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048973029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.2048973029
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.3386924028
Short name T385
Test name
Test status
Simulation time 1742109505 ps
CPU time 4.11 seconds
Started Mar 24 01:51:30 PM PDT 24
Finished Mar 24 01:51:34 PM PDT 24
Peak memory 209668 kb
Host smart-8a4bdee7-6307-4cb9-9a5e-e5849eaeb944
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386924028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.3386924028
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.3604059589
Short name T775
Test name
Test status
Simulation time 967504162 ps
CPU time 9.16 seconds
Started Mar 24 01:51:30 PM PDT 24
Finished Mar 24 01:51:39 PM PDT 24
Peak memory 214840 kb
Host smart-7ab1f701-c2f2-4427-953b-4d9866f676cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3604059589 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.3604059589
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.1426313045
Short name T202
Test name
Test status
Simulation time 13124178207 ps
CPU time 38.15 seconds
Started Mar 24 01:51:29 PM PDT 24
Finished Mar 24 01:52:07 PM PDT 24
Peak memory 221164 kb
Host smart-1d2e2efd-0841-49c9-86b1-cf5f6cb1ddc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426313045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.1426313045
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.478969630
Short name T515
Test name
Test status
Simulation time 291657681 ps
CPU time 3.01 seconds
Started Mar 24 01:51:30 PM PDT 24
Finished Mar 24 01:51:33 PM PDT 24
Peak memory 210316 kb
Host smart-619b7f15-a50b-418e-af83-780d4c73b5c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=478969630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.478969630
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/10.keymgr_random.1554338698
Short name T543
Test name
Test status
Simulation time 121397921 ps
CPU time 5.39 seconds
Started Mar 24 01:51:26 PM PDT 24
Finished Mar 24 01:51:32 PM PDT 24
Peak memory 210428 kb
Host smart-99ada12e-288b-4909-9db3-04b06cb3758f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1554338698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.1554338698
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.1475101870
Short name T656
Test name
Test status
Simulation time 143267924 ps
CPU time 2.36 seconds
Started Mar 24 01:51:26 PM PDT 24
Finished Mar 24 01:51:29 PM PDT 24
Peak memory 207160 kb
Host smart-5505abd7-5e1b-44b3-b30c-01e15b1dbeab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1475101870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.1475101870
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.805897441
Short name T586
Test name
Test status
Simulation time 55787721 ps
CPU time 3.08 seconds
Started Mar 24 01:51:27 PM PDT 24
Finished Mar 24 01:51:32 PM PDT 24
Peak memory 208864 kb
Host smart-b16437df-4f20-4a2b-ba8c-2f62fedb4ed5
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=805897441 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.805897441
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.1388911188
Short name T696
Test name
Test status
Simulation time 1137514779 ps
CPU time 3.49 seconds
Started Mar 24 01:51:26 PM PDT 24
Finished Mar 24 01:51:30 PM PDT 24
Peak memory 207124 kb
Host smart-3a529c67-3157-4d1d-86df-8aba37777629
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1388911188 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.1388911188
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.2044593468
Short name T233
Test name
Test status
Simulation time 177818884 ps
CPU time 5.23 seconds
Started Mar 24 01:51:29 PM PDT 24
Finished Mar 24 01:51:34 PM PDT 24
Peak memory 209264 kb
Host smart-4620db8c-b0b6-4805-af4b-f86513eb2864
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2044593468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.2044593468
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.4293875775
Short name T727
Test name
Test status
Simulation time 85695569 ps
CPU time 1.97 seconds
Started Mar 24 01:51:33 PM PDT 24
Finished Mar 24 01:51:36 PM PDT 24
Peak memory 216140 kb
Host smart-7f72bd1e-7b5d-4496-b736-e448860f4d9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4293875775 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.4293875775
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.1118906695
Short name T601
Test name
Test status
Simulation time 30791399 ps
CPU time 2.22 seconds
Started Mar 24 01:51:26 PM PDT 24
Finished Mar 24 01:51:29 PM PDT 24
Peak memory 207080 kb
Host smart-402b11d6-0461-4055-ad60-40090b3f24aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118906695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.1118906695
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.468606302
Short name T225
Test name
Test status
Simulation time 5707318380 ps
CPU time 116.61 seconds
Started Mar 24 01:51:28 PM PDT 24
Finished Mar 24 01:53:25 PM PDT 24
Peak memory 223104 kb
Host smart-6858a9af-8c0f-4b4b-9187-ea0ff232cf4a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468606302 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.468606302
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.480773738
Short name T248
Test name
Test status
Simulation time 50029483 ps
CPU time 2.44 seconds
Started Mar 24 01:51:29 PM PDT 24
Finished Mar 24 01:51:32 PM PDT 24
Peak memory 208496 kb
Host smart-8d860a28-563e-494c-ba50-ed071ee0d105
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480773738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.480773738
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.2098327366
Short name T553
Test name
Test status
Simulation time 67612603 ps
CPU time 1.45 seconds
Started Mar 24 01:51:29 PM PDT 24
Finished Mar 24 01:51:31 PM PDT 24
Peak memory 210192 kb
Host smart-c02272a0-14f3-446f-b538-7fc43569e8f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098327366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.2098327366
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.76209400
Short name T636
Test name
Test status
Simulation time 15117219 ps
CPU time 0.75 seconds
Started Mar 24 01:51:39 PM PDT 24
Finished Mar 24 01:51:40 PM PDT 24
Peak memory 206360 kb
Host smart-ea85191e-ed11-4c7b-a5a9-045376d01df5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76209400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.76209400
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.165921801
Short name T692
Test name
Test status
Simulation time 101481321 ps
CPU time 4.28 seconds
Started Mar 24 01:51:38 PM PDT 24
Finished Mar 24 01:51:43 PM PDT 24
Peak memory 209512 kb
Host smart-38dc4675-abae-4a0f-9d85-c07efc6450f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165921801 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.165921801
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.438188946
Short name T746
Test name
Test status
Simulation time 41730702 ps
CPU time 1.84 seconds
Started Mar 24 01:51:34 PM PDT 24
Finished Mar 24 01:51:36 PM PDT 24
Peak memory 207856 kb
Host smart-438e02d1-1dac-4248-a383-2628238c3e9e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=438188946 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.438188946
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.2288132923
Short name T269
Test name
Test status
Simulation time 841469385 ps
CPU time 7.27 seconds
Started Mar 24 01:51:40 PM PDT 24
Finished Mar 24 01:51:47 PM PDT 24
Peak memory 214660 kb
Host smart-5cf872be-6974-48b3-a17d-802da837434a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288132923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.2288132923
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.1771263637
Short name T217
Test name
Test status
Simulation time 47343935 ps
CPU time 2.47 seconds
Started Mar 24 01:51:36 PM PDT 24
Finished Mar 24 01:51:38 PM PDT 24
Peak memory 209644 kb
Host smart-c9b81e62-fcd5-4807-8a48-58d266b86176
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771263637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.1771263637
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.93273828
Short name T821
Test name
Test status
Simulation time 176107933 ps
CPU time 3.22 seconds
Started Mar 24 01:51:35 PM PDT 24
Finished Mar 24 01:51:38 PM PDT 24
Peak memory 209380 kb
Host smart-28f416bb-9841-4323-9f0a-fcb8643af757
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93273828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.93273828
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.3605546737
Short name T749
Test name
Test status
Simulation time 123988608 ps
CPU time 3.22 seconds
Started Mar 24 01:51:39 PM PDT 24
Finished Mar 24 01:51:42 PM PDT 24
Peak memory 209232 kb
Host smart-0589cb17-f206-4396-8014-bb85248aafb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3605546737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.3605546737
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.3612077929
Short name T473
Test name
Test status
Simulation time 518877319 ps
CPU time 8.35 seconds
Started Mar 24 01:51:33 PM PDT 24
Finished Mar 24 01:51:42 PM PDT 24
Peak memory 209200 kb
Host smart-0cf826cd-1fa6-4287-9b31-75832424d4f7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3612077929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.3612077929
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.511010065
Short name T204
Test name
Test status
Simulation time 675380648 ps
CPU time 5.12 seconds
Started Mar 24 01:51:33 PM PDT 24
Finished Mar 24 01:51:38 PM PDT 24
Peak memory 208344 kb
Host smart-70d128fc-b079-4889-abc3-e21334b5ea78
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=511010065 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.511010065
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.2112290406
Short name T436
Test name
Test status
Simulation time 466163047 ps
CPU time 8.13 seconds
Started Mar 24 01:51:35 PM PDT 24
Finished Mar 24 01:51:43 PM PDT 24
Peak memory 207468 kb
Host smart-ce694d5a-2397-4a2d-9a3d-c5ac804211cd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2112290406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.2112290406
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.616322487
Short name T393
Test name
Test status
Simulation time 120745652 ps
CPU time 2.36 seconds
Started Mar 24 01:51:38 PM PDT 24
Finished Mar 24 01:51:40 PM PDT 24
Peak memory 215748 kb
Host smart-35b2bdbe-5273-4433-adf4-8395f93a12eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=616322487 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.616322487
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.2632118012
Short name T546
Test name
Test status
Simulation time 120273489 ps
CPU time 3.09 seconds
Started Mar 24 01:51:37 PM PDT 24
Finished Mar 24 01:51:40 PM PDT 24
Peak memory 208708 kb
Host smart-81f52e3c-93eb-4599-97b6-2f09f58735fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2632118012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.2632118012
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.2924213050
Short name T604
Test name
Test status
Simulation time 6382856098 ps
CPU time 106.48 seconds
Started Mar 24 01:51:41 PM PDT 24
Finished Mar 24 01:53:28 PM PDT 24
Peak memory 223104 kb
Host smart-99e3057a-91e7-4585-984f-27b0020cdf05
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2924213050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.2924213050
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.923782196
Short name T559
Test name
Test status
Simulation time 5486882544 ps
CPU time 58.99 seconds
Started Mar 24 01:51:34 PM PDT 24
Finished Mar 24 01:52:33 PM PDT 24
Peak memory 210352 kb
Host smart-b928c703-f31d-48d3-95e1-0c5ef1cac4fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923782196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.923782196
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.165778965
Short name T777
Test name
Test status
Simulation time 64680143 ps
CPU time 1.25 seconds
Started Mar 24 01:51:38 PM PDT 24
Finished Mar 24 01:51:40 PM PDT 24
Peak memory 210516 kb
Host smart-8f13f259-2e66-4e7f-91d3-1608bdac977b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=165778965 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.165778965
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.3941206400
Short name T475
Test name
Test status
Simulation time 84174708 ps
CPU time 3.77 seconds
Started Mar 24 01:51:43 PM PDT 24
Finished Mar 24 01:51:47 PM PDT 24
Peak memory 223368 kb
Host smart-0b26aee1-6ef4-4636-ad67-3a60d465c119
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3941206400 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.3941206400
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.3412783654
Short name T409
Test name
Test status
Simulation time 38811997 ps
CPU time 2.12 seconds
Started Mar 24 01:51:38 PM PDT 24
Finished Mar 24 01:51:41 PM PDT 24
Peak memory 207596 kb
Host smart-32e3ec79-c8f1-493c-b279-88b03fbf1c05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3412783654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.3412783654
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.1450168796
Short name T839
Test name
Test status
Simulation time 852346226 ps
CPU time 8.56 seconds
Started Mar 24 01:51:43 PM PDT 24
Finished Mar 24 01:51:52 PM PDT 24
Peak memory 222388 kb
Host smart-15f07d69-9a2b-4705-a03a-8547d7bfc649
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1450168796 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.1450168796
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.2134569352
Short name T774
Test name
Test status
Simulation time 270257385 ps
CPU time 3.6 seconds
Started Mar 24 01:51:41 PM PDT 24
Finished Mar 24 01:51:45 PM PDT 24
Peak memory 222924 kb
Host smart-1098677c-060f-4b88-ae6c-43f5b9b41605
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134569352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.2134569352
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.2454495516
Short name T428
Test name
Test status
Simulation time 295642256 ps
CPU time 9.54 seconds
Started Mar 24 01:51:39 PM PDT 24
Finished Mar 24 01:51:49 PM PDT 24
Peak memory 218832 kb
Host smart-61461961-7cff-4685-bd8f-2833ee9ea35f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2454495516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.2454495516
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload.3442545255
Short name T693
Test name
Test status
Simulation time 232686126 ps
CPU time 2.46 seconds
Started Mar 24 01:51:40 PM PDT 24
Finished Mar 24 01:51:43 PM PDT 24
Peak memory 208852 kb
Host smart-cd860343-7934-450d-97c9-ce72901a14b7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3442545255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.3442545255
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.2556897455
Short name T587
Test name
Test status
Simulation time 182376185 ps
CPU time 2.74 seconds
Started Mar 24 01:51:38 PM PDT 24
Finished Mar 24 01:51:42 PM PDT 24
Peak memory 207228 kb
Host smart-66f7dd3e-b7c9-4e65-ac4c-bc293d756343
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2556897455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.2556897455
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.2558363586
Short name T466
Test name
Test status
Simulation time 127469726 ps
CPU time 3.32 seconds
Started Mar 24 01:51:38 PM PDT 24
Finished Mar 24 01:51:42 PM PDT 24
Peak memory 209044 kb
Host smart-1b6fab37-06cf-4a08-b97c-a73ff62faec1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2558363586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.2558363586
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_otbn.2041002050
Short name T748
Test name
Test status
Simulation time 270594893 ps
CPU time 3.19 seconds
Started Mar 24 01:51:39 PM PDT 24
Finished Mar 24 01:51:42 PM PDT 24
Peak memory 207232 kb
Host smart-ce15f82d-e5f7-45c2-88fd-a4205a2cc47d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2041002050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_otbn.2041002050
Directory /workspace/12.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.3364675590
Short name T695
Test name
Test status
Simulation time 23335104 ps
CPU time 1.85 seconds
Started Mar 24 01:51:46 PM PDT 24
Finished Mar 24 01:51:48 PM PDT 24
Peak memory 208064 kb
Host smart-c44d1668-0eea-4ca8-b101-87ed2cc40689
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364675590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.3364675590
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.3799221380
Short name T639
Test name
Test status
Simulation time 210847445 ps
CPU time 3.1 seconds
Started Mar 24 01:51:38 PM PDT 24
Finished Mar 24 01:51:42 PM PDT 24
Peak memory 208392 kb
Host smart-65cff275-b238-45b7-9272-8ce72c87fcd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799221380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.3799221380
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.2345260312
Short name T599
Test name
Test status
Simulation time 41034676824 ps
CPU time 145.87 seconds
Started Mar 24 01:51:44 PM PDT 24
Finished Mar 24 01:54:10 PM PDT 24
Peak memory 221828 kb
Host smart-9eaa4f86-b23a-4690-9e98-f25b20203ee2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2345260312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.2345260312
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/12.keymgr_stress_all_with_rand_reset.224429879
Short name T691
Test name
Test status
Simulation time 750212393 ps
CPU time 21.14 seconds
Started Mar 24 01:51:45 PM PDT 24
Finished Mar 24 01:52:07 PM PDT 24
Peak memory 223068 kb
Host smart-97db2a6c-01ce-43f4-aa62-b5f1ac132dc7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=224429879 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all_with_rand_reset.224429879
Directory /workspace/12.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.117495426
Short name T352
Test name
Test status
Simulation time 1195606072 ps
CPU time 23.8 seconds
Started Mar 24 01:51:42 PM PDT 24
Finished Mar 24 01:52:06 PM PDT 24
Peak memory 208884 kb
Host smart-a8378ac4-a1ce-45b2-a074-8cb7a6a2ad30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=117495426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.117495426
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.2940161390
Short name T814
Test name
Test status
Simulation time 2184352996 ps
CPU time 13.88 seconds
Started Mar 24 01:51:42 PM PDT 24
Finished Mar 24 01:51:56 PM PDT 24
Peak memory 219672 kb
Host smart-44e7532e-60f5-4e2c-b6a8-4560f02437e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2940161390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.2940161390
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.648521476
Short name T536
Test name
Test status
Simulation time 22635750 ps
CPU time 0.87 seconds
Started Mar 24 01:51:53 PM PDT 24
Finished Mar 24 01:51:55 PM PDT 24
Peak memory 206376 kb
Host smart-4d99613b-7316-45e4-ba9c-fc4bbf93f7a1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=648521476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.648521476
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.2168477103
Short name T10
Test name
Test status
Simulation time 86554303 ps
CPU time 4.45 seconds
Started Mar 24 01:51:53 PM PDT 24
Finished Mar 24 01:51:59 PM PDT 24
Peak memory 222064 kb
Host smart-8158b181-ae92-494b-86c7-b97b655f5b87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168477103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.2168477103
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.3559706071
Short name T235
Test name
Test status
Simulation time 140788273 ps
CPU time 2.88 seconds
Started Mar 24 01:51:47 PM PDT 24
Finished Mar 24 01:51:51 PM PDT 24
Peak memory 215028 kb
Host smart-31b2d85d-b477-4548-95e0-943ea511cb8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3559706071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.3559706071
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.2763394476
Short name T85
Test name
Test status
Simulation time 105004546 ps
CPU time 5.2 seconds
Started Mar 24 01:51:53 PM PDT 24
Finished Mar 24 01:51:59 PM PDT 24
Peak memory 210324 kb
Host smart-c5f05c7b-c536-47a0-9ef2-7d10792f77f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763394476 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.2763394476
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.828685973
Short name T139
Test name
Test status
Simulation time 73756052 ps
CPU time 3.81 seconds
Started Mar 24 01:51:49 PM PDT 24
Finished Mar 24 01:51:54 PM PDT 24
Peak memory 220596 kb
Host smart-6b7bc72d-4a71-4bd0-8cf4-13011eeb01b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828685973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.828685973
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.1076463753
Short name T557
Test name
Test status
Simulation time 1615236220 ps
CPU time 31.98 seconds
Started Mar 24 01:51:49 PM PDT 24
Finished Mar 24 01:52:21 PM PDT 24
Peak memory 208748 kb
Host smart-7463d63f-2fd4-41c1-ad6e-448704a06a69
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1076463753 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.1076463753
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.989211136
Short name T585
Test name
Test status
Simulation time 2414206230 ps
CPU time 6.41 seconds
Started Mar 24 01:51:43 PM PDT 24
Finished Mar 24 01:51:49 PM PDT 24
Peak memory 208412 kb
Host smart-68e6508f-0ebc-420d-a927-e8d56f62e3de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=989211136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.989211136
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.669219538
Short name T878
Test name
Test status
Simulation time 43938409 ps
CPU time 1.91 seconds
Started Mar 24 01:51:44 PM PDT 24
Finished Mar 24 01:51:46 PM PDT 24
Peak memory 207280 kb
Host smart-3d18891a-c437-4353-bb27-ff20dd064958
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=669219538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.669219538
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.323642518
Short name T556
Test name
Test status
Simulation time 230242564 ps
CPU time 5.08 seconds
Started Mar 24 01:51:45 PM PDT 24
Finished Mar 24 01:51:50 PM PDT 24
Peak memory 209112 kb
Host smart-a55f2156-fd49-4a45-9c48-2275a2059690
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=323642518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.323642518
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.3597184076
Short name T718
Test name
Test status
Simulation time 249001814 ps
CPU time 3.13 seconds
Started Mar 24 01:51:47 PM PDT 24
Finished Mar 24 01:51:50 PM PDT 24
Peak memory 207260 kb
Host smart-92a5c3f6-12ff-405d-bc33-8241d8b6e730
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3597184076 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.3597184076
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.3603060861
Short name T582
Test name
Test status
Simulation time 50751492 ps
CPU time 2.76 seconds
Started Mar 24 01:51:53 PM PDT 24
Finished Mar 24 01:51:57 PM PDT 24
Peak memory 208716 kb
Host smart-73399717-392f-4e8d-b56d-6c75fbfc6f3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603060861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.3603060861
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.3154015927
Short name T744
Test name
Test status
Simulation time 62350221 ps
CPU time 2.21 seconds
Started Mar 24 01:51:46 PM PDT 24
Finished Mar 24 01:51:48 PM PDT 24
Peak memory 207196 kb
Host smart-41ae95b4-7d85-4dd5-8545-5e89d555ba5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3154015927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.3154015927
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.249147637
Short name T75
Test name
Test status
Simulation time 2304630156 ps
CPU time 5.61 seconds
Started Mar 24 01:51:48 PM PDT 24
Finished Mar 24 01:51:54 PM PDT 24
Peak memory 207780 kb
Host smart-7f79caf6-6c53-4433-8669-49cb9b91d204
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=249147637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.249147637
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.4719454
Short name T655
Test name
Test status
Simulation time 11720753 ps
CPU time 0.78 seconds
Started Mar 24 01:52:02 PM PDT 24
Finished Mar 24 01:52:03 PM PDT 24
Peak memory 206436 kb
Host smart-dff43a42-8466-4f68-b46c-2f4de490d90c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4719454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.4719454
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.832021484
Short name T605
Test name
Test status
Simulation time 121820593 ps
CPU time 3.38 seconds
Started Mar 24 01:52:00 PM PDT 24
Finished Mar 24 01:52:04 PM PDT 24
Peak memory 223344 kb
Host smart-e22fb6e5-6981-4cd1-aa2f-07e8786acb97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=832021484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.832021484
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.2886592992
Short name T799
Test name
Test status
Simulation time 45345345 ps
CPU time 1.48 seconds
Started Mar 24 01:51:56 PM PDT 24
Finished Mar 24 01:51:59 PM PDT 24
Peak memory 208392 kb
Host smart-5da79e07-0cdb-4f93-b582-13ecccb8ee2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886592992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.2886592992
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.2059413326
Short name T879
Test name
Test status
Simulation time 256872606 ps
CPU time 3.44 seconds
Started Mar 24 01:52:02 PM PDT 24
Finished Mar 24 01:52:06 PM PDT 24
Peak memory 208308 kb
Host smart-9da5506c-3a52-4c68-9eea-e620cc44b117
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2059413326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.2059413326
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.3127979785
Short name T618
Test name
Test status
Simulation time 92596535 ps
CPU time 3.07 seconds
Started Mar 24 01:51:58 PM PDT 24
Finished Mar 24 01:52:02 PM PDT 24
Peak memory 209748 kb
Host smart-f165871c-9f56-4ada-a258-99be6e5e719a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127979785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.3127979785
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.3877893697
Short name T534
Test name
Test status
Simulation time 301747343 ps
CPU time 8.08 seconds
Started Mar 24 01:51:54 PM PDT 24
Finished Mar 24 01:52:05 PM PDT 24
Peak memory 214776 kb
Host smart-703ca957-e026-47c2-a767-fbb48d9286d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3877893697 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.3877893697
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.3582221669
Short name T277
Test name
Test status
Simulation time 108904555 ps
CPU time 4.64 seconds
Started Mar 24 01:51:54 PM PDT 24
Finished Mar 24 01:52:01 PM PDT 24
Peak memory 208836 kb
Host smart-31ee5f56-9882-4276-9c94-5b338ae258f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582221669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.3582221669
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.1754455462
Short name T661
Test name
Test status
Simulation time 34008275 ps
CPU time 2.39 seconds
Started Mar 24 01:51:52 PM PDT 24
Finished Mar 24 01:51:55 PM PDT 24
Peak memory 207304 kb
Host smart-77346f09-a9f9-4713-8cab-b8ff7c452666
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1754455462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.1754455462
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.1391409149
Short name T333
Test name
Test status
Simulation time 427121713 ps
CPU time 6.7 seconds
Started Mar 24 01:51:52 PM PDT 24
Finished Mar 24 01:52:00 PM PDT 24
Peak memory 209228 kb
Host smart-13f225ff-b2be-4b6a-a728-fe0dd6b1692f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1391409149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.1391409149
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.4008139265
Short name T552
Test name
Test status
Simulation time 2128278760 ps
CPU time 38.37 seconds
Started Mar 24 01:51:56 PM PDT 24
Finished Mar 24 01:52:35 PM PDT 24
Peak memory 209388 kb
Host smart-341cb628-a323-4416-92c0-b6e67e492225
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008139265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.4008139265
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.2223636226
Short name T647
Test name
Test status
Simulation time 543604813 ps
CPU time 5.99 seconds
Started Mar 24 01:51:59 PM PDT 24
Finished Mar 24 01:52:05 PM PDT 24
Peak memory 209952 kb
Host smart-496f7ba4-59b0-476d-8b00-3980cb42a5fa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2223636226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.2223636226
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.158666527
Short name T400
Test name
Test status
Simulation time 413127019 ps
CPU time 5.43 seconds
Started Mar 24 01:51:56 PM PDT 24
Finished Mar 24 01:52:03 PM PDT 24
Peak memory 207084 kb
Host smart-3e1129e3-59dd-49a9-abb4-8271cbff75e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158666527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.158666527
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.739177904
Short name T407
Test name
Test status
Simulation time 3631556901 ps
CPU time 47.9 seconds
Started Mar 24 01:52:00 PM PDT 24
Finished Mar 24 01:52:49 PM PDT 24
Peak memory 211016 kb
Host smart-61fc0e81-814e-4533-8bf0-be5dfafbcb4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739177904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.739177904
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.1060764450
Short name T757
Test name
Test status
Simulation time 484022011 ps
CPU time 4.08 seconds
Started Mar 24 01:52:02 PM PDT 24
Finished Mar 24 01:52:07 PM PDT 24
Peak memory 211152 kb
Host smart-bbdaa557-f42e-4e3d-bfff-c3f7d1671c4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1060764450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.1060764450
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.3893783681
Short name T551
Test name
Test status
Simulation time 38708467 ps
CPU time 0.76 seconds
Started Mar 24 01:52:08 PM PDT 24
Finished Mar 24 01:52:09 PM PDT 24
Peak memory 206444 kb
Host smart-27450dd4-968d-4b2a-8db5-7ce268bd11b3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3893783681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.3893783681
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.2155001932
Short name T539
Test name
Test status
Simulation time 514407771 ps
CPU time 17.34 seconds
Started Mar 24 01:52:03 PM PDT 24
Finished Mar 24 01:52:20 PM PDT 24
Peak memory 209124 kb
Host smart-83f9be48-110a-4e03-81df-6d195c4c3b9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2155001932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.2155001932
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.1182370119
Short name T640
Test name
Test status
Simulation time 545584003 ps
CPU time 4.45 seconds
Started Mar 24 01:52:06 PM PDT 24
Finished Mar 24 01:52:11 PM PDT 24
Peak memory 208604 kb
Host smart-91d1829b-af86-486e-a94e-ded5bead9584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1182370119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.1182370119
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.2912141981
Short name T209
Test name
Test status
Simulation time 286486938 ps
CPU time 3.39 seconds
Started Mar 24 01:52:05 PM PDT 24
Finished Mar 24 01:52:08 PM PDT 24
Peak memory 214836 kb
Host smart-d099b6ca-ace4-4854-b1c1-f01758ae8ce8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2912141981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.2912141981
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_random.3600448634
Short name T236
Test name
Test status
Simulation time 1495229710 ps
CPU time 15.87 seconds
Started Mar 24 01:52:03 PM PDT 24
Finished Mar 24 01:52:19 PM PDT 24
Peak memory 218812 kb
Host smart-074fa5d9-5327-4800-8d02-e045162475ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3600448634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.3600448634
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.923360112
Short name T263
Test name
Test status
Simulation time 216697719 ps
CPU time 7.62 seconds
Started Mar 24 01:52:03 PM PDT 24
Finished Mar 24 01:52:10 PM PDT 24
Peak memory 208864 kb
Host smart-6b1f0435-41fe-4319-bbe4-c8bf861cad3d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=923360112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.923360112
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.2158478773
Short name T544
Test name
Test status
Simulation time 41121811 ps
CPU time 2.33 seconds
Started Mar 24 01:52:05 PM PDT 24
Finished Mar 24 01:52:07 PM PDT 24
Peak memory 207736 kb
Host smart-66e30388-b580-4a75-aea1-46c21d71a95b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2158478773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.2158478773
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.617941724
Short name T823
Test name
Test status
Simulation time 253520421 ps
CPU time 5.93 seconds
Started Mar 24 01:51:59 PM PDT 24
Finished Mar 24 01:52:05 PM PDT 24
Peak memory 208360 kb
Host smart-adbf6275-8c28-49de-8c20-ef7158f741e1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617941724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.617941724
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.4032922938
Short name T19
Test name
Test status
Simulation time 233401510 ps
CPU time 3.11 seconds
Started Mar 24 01:52:05 PM PDT 24
Finished Mar 24 01:52:09 PM PDT 24
Peak memory 208900 kb
Host smart-74a98bd1-8bdb-465c-8a25-821ed9c0ace3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4032922938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.4032922938
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.204026455
Short name T603
Test name
Test status
Simulation time 33001377 ps
CPU time 2.44 seconds
Started Mar 24 01:52:04 PM PDT 24
Finished Mar 24 01:52:06 PM PDT 24
Peak memory 209608 kb
Host smart-ec9efde5-fca8-4ec2-b69d-aefb044db1ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204026455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.204026455
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/15.keymgr_smoke.2796272552
Short name T851
Test name
Test status
Simulation time 423804428 ps
CPU time 3.74 seconds
Started Mar 24 01:52:00 PM PDT 24
Finished Mar 24 01:52:04 PM PDT 24
Peak memory 207088 kb
Host smart-e76309f7-e4a1-4981-8843-c871d1d92e8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796272552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.2796272552
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.1489790218
Short name T191
Test name
Test status
Simulation time 7666017586 ps
CPU time 46.11 seconds
Started Mar 24 01:52:08 PM PDT 24
Finished Mar 24 01:52:54 PM PDT 24
Peak memory 223092 kb
Host smart-ddd4c509-bebc-40d1-8b08-21cab97f941b
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1489790218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.1489790218
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.4255446339
Short name T426
Test name
Test status
Simulation time 905459580 ps
CPU time 4.8 seconds
Started Mar 24 01:52:06 PM PDT 24
Finished Mar 24 01:52:11 PM PDT 24
Peak memory 209044 kb
Host smart-6b749c83-08d9-4d4a-802a-f7d2f5787ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4255446339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.4255446339
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.3513529452
Short name T127
Test name
Test status
Simulation time 126865970 ps
CPU time 3.44 seconds
Started Mar 24 01:52:04 PM PDT 24
Finished Mar 24 01:52:08 PM PDT 24
Peak memory 210556 kb
Host smart-120e0ea3-2968-417c-89e6-1e7b604f4777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513529452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.3513529452
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.3966871975
Short name T708
Test name
Test status
Simulation time 17070281 ps
CPU time 0.94 seconds
Started Mar 24 01:52:09 PM PDT 24
Finished Mar 24 01:52:10 PM PDT 24
Peak memory 206356 kb
Host smart-92f46010-310f-4e88-b717-939f35acdb4e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966871975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.3966871975
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.2539782818
Short name T332
Test name
Test status
Simulation time 589208425 ps
CPU time 4.6 seconds
Started Mar 24 01:52:05 PM PDT 24
Finished Mar 24 01:52:10 PM PDT 24
Peak memory 214848 kb
Host smart-7863c798-ee09-45da-b8f9-866d8bc1eff7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2539782818 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.2539782818
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.512657000
Short name T876
Test name
Test status
Simulation time 148374866 ps
CPU time 4.11 seconds
Started Mar 24 01:52:04 PM PDT 24
Finished Mar 24 01:52:09 PM PDT 24
Peak memory 214704 kb
Host smart-1c3c41d8-ae0d-405c-9538-37aeac801a0c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512657000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.512657000
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.3961550867
Short name T305
Test name
Test status
Simulation time 105266640 ps
CPU time 4.95 seconds
Started Mar 24 01:52:04 PM PDT 24
Finished Mar 24 01:52:09 PM PDT 24
Peak memory 222908 kb
Host smart-83dbf163-ffb4-4b39-a615-f05d13cf24cc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3961550867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.3961550867
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.3385783345
Short name T554
Test name
Test status
Simulation time 93678482 ps
CPU time 4.31 seconds
Started Mar 24 01:52:05 PM PDT 24
Finished Mar 24 01:52:09 PM PDT 24
Peak memory 219076 kb
Host smart-9d2fb9ee-2951-4232-80c2-4caef9346cf7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3385783345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.3385783345
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.1576261262
Short name T533
Test name
Test status
Simulation time 1210904339 ps
CPU time 9.69 seconds
Started Mar 24 01:52:06 PM PDT 24
Finished Mar 24 01:52:16 PM PDT 24
Peak memory 209508 kb
Host smart-7d4216f2-d34c-49bf-aebc-a0c9cb36138d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1576261262 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.1576261262
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.2666855421
Short name T511
Test name
Test status
Simulation time 108969500 ps
CPU time 2.79 seconds
Started Mar 24 01:52:04 PM PDT 24
Finished Mar 24 01:52:07 PM PDT 24
Peak memory 208260 kb
Host smart-9e1f7cd2-1011-42c3-ac15-28c1a0fa4384
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2666855421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.2666855421
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.3368840788
Short name T867
Test name
Test status
Simulation time 1622168628 ps
CPU time 21.72 seconds
Started Mar 24 01:52:05 PM PDT 24
Finished Mar 24 01:52:27 PM PDT 24
Peak memory 208276 kb
Host smart-41e67b3b-c390-40f8-bee9-fe3c17761959
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3368840788 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.3368840788
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.3181392035
Short name T754
Test name
Test status
Simulation time 35309515 ps
CPU time 2.48 seconds
Started Mar 24 01:52:08 PM PDT 24
Finished Mar 24 01:52:10 PM PDT 24
Peak memory 209148 kb
Host smart-f87690eb-ecf9-4c86-ac9c-d46a911ea549
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3181392035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.3181392035
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.1575582651
Short name T759
Test name
Test status
Simulation time 267994367 ps
CPU time 6.32 seconds
Started Mar 24 01:52:07 PM PDT 24
Finished Mar 24 01:52:14 PM PDT 24
Peak memory 209196 kb
Host smart-079c1c85-6929-4b0c-9c69-679f835d3429
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1575582651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.1575582651
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.4053092181
Short name T15
Test name
Test status
Simulation time 236327989 ps
CPU time 2.03 seconds
Started Mar 24 01:52:10 PM PDT 24
Finished Mar 24 01:52:12 PM PDT 24
Peak memory 209044 kb
Host smart-a183b1c7-d68f-4934-87e4-eab6cfdd5982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053092181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.4053092181
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.3731006068
Short name T401
Test name
Test status
Simulation time 908306289 ps
CPU time 3.2 seconds
Started Mar 24 01:52:08 PM PDT 24
Finished Mar 24 01:52:11 PM PDT 24
Peak memory 207144 kb
Host smart-730b1778-daaa-4890-b973-04f22da2555e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731006068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.3731006068
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.3918572003
Short name T629
Test name
Test status
Simulation time 1593883960 ps
CPU time 33.76 seconds
Started Mar 24 01:52:11 PM PDT 24
Finished Mar 24 01:52:45 PM PDT 24
Peak memory 217360 kb
Host smart-5fdaea49-5586-42f2-9064-f286b3949b7f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3918572003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.3918572003
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.1117215838
Short name T315
Test name
Test status
Simulation time 1470941804 ps
CPU time 4.92 seconds
Started Mar 24 01:52:04 PM PDT 24
Finished Mar 24 01:52:09 PM PDT 24
Peak memory 214840 kb
Host smart-a1952bb2-8b40-4ff8-8387-2f60862edbed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117215838 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.1117215838
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.1788605427
Short name T451
Test name
Test status
Simulation time 16480941 ps
CPU time 0.78 seconds
Started Mar 24 01:52:13 PM PDT 24
Finished Mar 24 01:52:14 PM PDT 24
Peak memory 206472 kb
Host smart-78b9a4cb-33c9-4f67-a497-9078b51dcee2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1788605427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.1788605427
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.3625068486
Short name T37
Test name
Test status
Simulation time 650148391 ps
CPU time 7.17 seconds
Started Mar 24 01:52:10 PM PDT 24
Finished Mar 24 01:52:17 PM PDT 24
Peak memory 209392 kb
Host smart-127c78eb-1fab-4467-9a86-7867e58f950a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625068486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.3625068486
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.2007087690
Short name T310
Test name
Test status
Simulation time 694015426 ps
CPU time 24.9 seconds
Started Mar 24 01:52:08 PM PDT 24
Finished Mar 24 01:52:33 PM PDT 24
Peak memory 210640 kb
Host smart-3ae06328-381a-4ded-a33e-905840e6da2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2007087690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.2007087690
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.2962700379
Short name T526
Test name
Test status
Simulation time 911503892 ps
CPU time 8.84 seconds
Started Mar 24 01:52:09 PM PDT 24
Finished Mar 24 01:52:18 PM PDT 24
Peak memory 218892 kb
Host smart-aae78c30-e1ef-492a-9aa4-2d2d9cfc7e53
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962700379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.2962700379
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.3880201316
Short name T35
Test name
Test status
Simulation time 703564371 ps
CPU time 7.89 seconds
Started Mar 24 01:52:10 PM PDT 24
Finished Mar 24 01:52:18 PM PDT 24
Peak memory 214716 kb
Host smart-daacf101-c3f6-4d58-abc6-2202cdde0a19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880201316 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.3880201316
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.2197095945
Short name T773
Test name
Test status
Simulation time 34582530 ps
CPU time 2.82 seconds
Started Mar 24 01:52:09 PM PDT 24
Finished Mar 24 01:52:12 PM PDT 24
Peak memory 216844 kb
Host smart-703f2a5f-f532-4ffd-b186-d12200262721
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2197095945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.2197095945
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.995261219
Short name T593
Test name
Test status
Simulation time 3470199996 ps
CPU time 25.57 seconds
Started Mar 24 01:52:07 PM PDT 24
Finished Mar 24 01:52:33 PM PDT 24
Peak memory 210168 kb
Host smart-339c13bb-70ec-40fa-a465-bbdcb0e060e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995261219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.995261219
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.3490073994
Short name T431
Test name
Test status
Simulation time 92558888 ps
CPU time 3.12 seconds
Started Mar 24 01:52:08 PM PDT 24
Finished Mar 24 01:52:11 PM PDT 24
Peak memory 207156 kb
Host smart-59196cf4-0f37-41b7-adb2-f4a5a91b0b0e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490073994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.3490073994
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.199687727
Short name T487
Test name
Test status
Simulation time 151013708 ps
CPU time 2.9 seconds
Started Mar 24 01:52:08 PM PDT 24
Finished Mar 24 01:52:11 PM PDT 24
Peak memory 208756 kb
Host smart-7b11161c-2757-42c2-94e4-1f9b54331494
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=199687727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.199687727
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.4246580795
Short name T890
Test name
Test status
Simulation time 91132736 ps
CPU time 3.68 seconds
Started Mar 24 01:52:09 PM PDT 24
Finished Mar 24 01:52:13 PM PDT 24
Peak memory 208492 kb
Host smart-342f868c-27f7-462c-8f63-bdea0788a26c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4246580795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.4246580795
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.3911211491
Short name T368
Test name
Test status
Simulation time 209195462 ps
CPU time 2.96 seconds
Started Mar 24 01:52:10 PM PDT 24
Finished Mar 24 01:52:13 PM PDT 24
Peak memory 207284 kb
Host smart-bfb9eb14-1de4-4fc8-92d6-dfe56e73cf64
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3911211491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.3911211491
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.3739786654
Short name T531
Test name
Test status
Simulation time 353179990 ps
CPU time 4.42 seconds
Started Mar 24 01:52:08 PM PDT 24
Finished Mar 24 01:52:12 PM PDT 24
Peak memory 210160 kb
Host smart-340076db-a9b8-4575-9ee9-bc651226bd8d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3739786654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.3739786654
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.3902724054
Short name T625
Test name
Test status
Simulation time 283783132 ps
CPU time 3.9 seconds
Started Mar 24 01:52:08 PM PDT 24
Finished Mar 24 01:52:12 PM PDT 24
Peak memory 209100 kb
Host smart-f0599998-bbc0-4ad0-82fd-110cbde51ebb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3902724054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.3902724054
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.3587677707
Short name T792
Test name
Test status
Simulation time 5003019253 ps
CPU time 19.7 seconds
Started Mar 24 01:52:12 PM PDT 24
Finished Mar 24 01:52:32 PM PDT 24
Peak memory 215612 kb
Host smart-b24c1b50-d965-45bb-8931-78092c778913
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3587677707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.3587677707
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_stress_all_with_rand_reset.4212145670
Short name T126
Test name
Test status
Simulation time 2161823890 ps
CPU time 18.29 seconds
Started Mar 24 01:52:12 PM PDT 24
Finished Mar 24 01:52:31 PM PDT 24
Peak memory 221556 kb
Host smart-de75de17-ee5d-4dfc-a40a-2fb2b704a3e0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4212145670 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all_with_rand_reset.4212145670
Directory /workspace/17.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.185796997
Short name T606
Test name
Test status
Simulation time 51698713 ps
CPU time 2.13 seconds
Started Mar 24 01:52:10 PM PDT 24
Finished Mar 24 01:52:12 PM PDT 24
Peak memory 208808 kb
Host smart-cb952957-4015-4e2a-8147-ceef2e102e97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185796997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.185796997
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.2522235145
Short name T861
Test name
Test status
Simulation time 127253737 ps
CPU time 2.23 seconds
Started Mar 24 01:52:09 PM PDT 24
Finished Mar 24 01:52:11 PM PDT 24
Peak memory 210584 kb
Host smart-de0fa7f4-dd2e-42d0-a8f5-689c15cff3b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2522235145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.2522235145
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.1303868508
Short name T569
Test name
Test status
Simulation time 28170833 ps
CPU time 0.82 seconds
Started Mar 24 01:52:18 PM PDT 24
Finished Mar 24 01:52:19 PM PDT 24
Peak memory 206336 kb
Host smart-92fa0c22-1d94-4454-b927-b62b3158a45d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1303868508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.1303868508
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.544006295
Short name T232
Test name
Test status
Simulation time 406345400 ps
CPU time 10.78 seconds
Started Mar 24 01:52:14 PM PDT 24
Finished Mar 24 01:52:25 PM PDT 24
Peak memory 214820 kb
Host smart-bc5dd45b-9ba4-4622-8df0-1ad977fc4218
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=544006295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.544006295
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.1218090206
Short name T899
Test name
Test status
Simulation time 183421335 ps
CPU time 3.88 seconds
Started Mar 24 01:52:19 PM PDT 24
Finished Mar 24 01:52:23 PM PDT 24
Peak memory 210060 kb
Host smart-195e68e0-60b9-439e-89ca-26abf850214b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1218090206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.1218090206
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.2850705658
Short name T716
Test name
Test status
Simulation time 55574448 ps
CPU time 3 seconds
Started Mar 24 01:52:15 PM PDT 24
Finished Mar 24 01:52:18 PM PDT 24
Peak memory 208008 kb
Host smart-8286529c-d3f4-4bf6-a05b-426cc988850a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2850705658 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.2850705658
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.1642364158
Short name T84
Test name
Test status
Simulation time 232390845 ps
CPU time 3.69 seconds
Started Mar 24 01:52:15 PM PDT 24
Finished Mar 24 01:52:18 PM PDT 24
Peak memory 210132 kb
Host smart-713043bd-e985-4e99-9533-b2997e8c05e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642364158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.1642364158
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.3585874270
Short name T829
Test name
Test status
Simulation time 466338378 ps
CPU time 3.72 seconds
Started Mar 24 01:52:14 PM PDT 24
Finished Mar 24 01:52:18 PM PDT 24
Peak memory 214860 kb
Host smart-862bb8a6-8aaa-4cbf-8af4-d991ff896baf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3585874270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.3585874270
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.2369981555
Short name T496
Test name
Test status
Simulation time 1089875750 ps
CPU time 11.54 seconds
Started Mar 24 01:52:14 PM PDT 24
Finished Mar 24 01:52:26 PM PDT 24
Peak memory 209444 kb
Host smart-ef0d4b40-e658-478d-abe8-7edeea1a13d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369981555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.2369981555
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.2448027694
Short name T732
Test name
Test status
Simulation time 143672379 ps
CPU time 4.97 seconds
Started Mar 24 01:52:15 PM PDT 24
Finished Mar 24 01:52:20 PM PDT 24
Peak memory 208324 kb
Host smart-a6149e5c-fbbc-4e3a-91e5-6ff06a08234b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448027694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.2448027694
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.3249361034
Short name T119
Test name
Test status
Simulation time 999181915 ps
CPU time 3.64 seconds
Started Mar 24 01:52:15 PM PDT 24
Finished Mar 24 01:52:19 PM PDT 24
Peak memory 207264 kb
Host smart-8a928d5e-9895-4990-9483-d4abce849a44
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3249361034 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.3249361034
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.66290695
Short name T836
Test name
Test status
Simulation time 70305058 ps
CPU time 3.58 seconds
Started Mar 24 01:52:14 PM PDT 24
Finished Mar 24 01:52:17 PM PDT 24
Peak memory 209148 kb
Host smart-8ae9bcc6-f580-42a3-866a-8910a87a495f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66290695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.66290695
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.2523709304
Short name T711
Test name
Test status
Simulation time 24359083 ps
CPU time 1.97 seconds
Started Mar 24 01:52:13 PM PDT 24
Finished Mar 24 01:52:16 PM PDT 24
Peak memory 209032 kb
Host smart-b5f86b18-e978-48ac-914c-18bbdfa34e0a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523709304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.2523709304
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.929918974
Short name T133
Test name
Test status
Simulation time 36870659 ps
CPU time 2.37 seconds
Started Mar 24 01:52:20 PM PDT 24
Finished Mar 24 01:52:22 PM PDT 24
Peak memory 214812 kb
Host smart-81d909dc-e6ea-44a4-8ff3-30623ff7fef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929918974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.929918974
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.393520345
Short name T863
Test name
Test status
Simulation time 267189450 ps
CPU time 4.75 seconds
Started Mar 24 01:52:14 PM PDT 24
Finished Mar 24 01:52:19 PM PDT 24
Peak memory 207208 kb
Host smart-610281a6-5f0b-44a8-bb84-1b5cd5621a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=393520345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.393520345
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.977493047
Short name T568
Test name
Test status
Simulation time 1040618397 ps
CPU time 20.74 seconds
Started Mar 24 01:52:18 PM PDT 24
Finished Mar 24 01:52:39 PM PDT 24
Peak memory 222740 kb
Host smart-f4ecdb5a-83b9-4827-890a-21f7ed83b978
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=977493047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.977493047
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.3182287043
Short name T778
Test name
Test status
Simulation time 127227508 ps
CPU time 3.62 seconds
Started Mar 24 01:52:12 PM PDT 24
Finished Mar 24 01:52:16 PM PDT 24
Peak memory 209540 kb
Host smart-adc87970-b344-4deb-8ad3-24259e65d215
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3182287043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.3182287043
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.1219337508
Short name T363
Test name
Test status
Simulation time 53971128 ps
CPU time 2.21 seconds
Started Mar 24 01:52:21 PM PDT 24
Finished Mar 24 01:52:23 PM PDT 24
Peak memory 210280 kb
Host smart-40419740-bf1b-45b6-a43e-583af9684dda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1219337508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.1219337508
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.2383497229
Short name T852
Test name
Test status
Simulation time 15580615 ps
CPU time 0.82 seconds
Started Mar 24 01:52:23 PM PDT 24
Finished Mar 24 01:52:24 PM PDT 24
Peak memory 206328 kb
Host smart-91a2065d-6109-4ad4-a9be-3cb0f76847cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2383497229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.2383497229
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.3507374486
Short name T381
Test name
Test status
Simulation time 352005206 ps
CPU time 7.87 seconds
Started Mar 24 01:52:21 PM PDT 24
Finished Mar 24 01:52:29 PM PDT 24
Peak memory 214924 kb
Host smart-2174d5e9-4c11-4527-a760-0dbeb00d9005
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3507374486 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.3507374486
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.1640620428
Short name T833
Test name
Test status
Simulation time 434669229 ps
CPU time 3.08 seconds
Started Mar 24 01:52:19 PM PDT 24
Finished Mar 24 01:52:22 PM PDT 24
Peak memory 211144 kb
Host smart-6a006506-49b3-45d2-af74-daec7b443ad6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1640620428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.1640620428
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.2278036071
Short name T892
Test name
Test status
Simulation time 44741182 ps
CPU time 1.84 seconds
Started Mar 24 01:52:20 PM PDT 24
Finished Mar 24 01:52:22 PM PDT 24
Peak memory 208380 kb
Host smart-75145864-787f-458c-88aa-ca237003fa79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2278036071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.2278036071
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_random.1935273233
Short name T100
Test name
Test status
Simulation time 1270946098 ps
CPU time 12.76 seconds
Started Mar 24 01:52:18 PM PDT 24
Finished Mar 24 01:52:31 PM PDT 24
Peak memory 210224 kb
Host smart-b89d69be-86a4-4c1c-a383-e68ce140646b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935273233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.1935273233
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.660920140
Short name T747
Test name
Test status
Simulation time 566508235 ps
CPU time 3.99 seconds
Started Mar 24 01:52:19 PM PDT 24
Finished Mar 24 01:52:23 PM PDT 24
Peak memory 209340 kb
Host smart-2c0b0237-7bf5-4b82-b009-a21884f1b860
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660920140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.660920140
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.4222496511
Short name T755
Test name
Test status
Simulation time 552850323 ps
CPU time 6.22 seconds
Started Mar 24 01:52:18 PM PDT 24
Finished Mar 24 01:52:25 PM PDT 24
Peak memory 207308 kb
Host smart-3bd53572-174a-41ab-8acb-7a5db41b0e52
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222496511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.4222496511
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.3410452723
Short name T456
Test name
Test status
Simulation time 294146428 ps
CPU time 8.77 seconds
Started Mar 24 01:52:19 PM PDT 24
Finished Mar 24 01:52:28 PM PDT 24
Peak memory 208424 kb
Host smart-8ef56520-6eaf-41fd-9417-aed303d27fe0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3410452723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.3410452723
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.3298101069
Short name T756
Test name
Test status
Simulation time 207716692 ps
CPU time 3.05 seconds
Started Mar 24 01:52:22 PM PDT 24
Finished Mar 24 01:52:25 PM PDT 24
Peak memory 207248 kb
Host smart-c88555dd-27f1-43c3-b04a-5985f842ad11
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3298101069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.3298101069
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.2421052585
Short name T794
Test name
Test status
Simulation time 311108598 ps
CPU time 6.11 seconds
Started Mar 24 01:52:20 PM PDT 24
Finished Mar 24 01:52:27 PM PDT 24
Peak memory 209504 kb
Host smart-a4dd192e-ceef-4df1-8591-7849cb0718c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2421052585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.2421052585
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.1855201203
Short name T486
Test name
Test status
Simulation time 199689648 ps
CPU time 5.18 seconds
Started Mar 24 01:52:21 PM PDT 24
Finished Mar 24 01:52:27 PM PDT 24
Peak memory 208716 kb
Host smart-f4210c02-3ccc-4e0e-ac15-673823a10fce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855201203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.1855201203
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.4272449518
Short name T858
Test name
Test status
Simulation time 299534867 ps
CPU time 2.95 seconds
Started Mar 24 01:52:20 PM PDT 24
Finished Mar 24 01:52:23 PM PDT 24
Peak memory 207728 kb
Host smart-3fb1233f-da4e-4533-9bf3-0e3773a94152
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4272449518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.4272449518
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.3315944353
Short name T570
Test name
Test status
Simulation time 238301987 ps
CPU time 2.59 seconds
Started Mar 24 01:52:19 PM PDT 24
Finished Mar 24 01:52:21 PM PDT 24
Peak memory 210228 kb
Host smart-d71a2788-89e3-4463-b261-1552acb2f8f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3315944353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.3315944353
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.2625298614
Short name T422
Test name
Test status
Simulation time 10364890 ps
CPU time 0.79 seconds
Started Mar 24 01:50:29 PM PDT 24
Finished Mar 24 01:50:30 PM PDT 24
Peak memory 206368 kb
Host smart-a76559d5-c73e-43d2-b268-1458b033cc57
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2625298614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.2625298614
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.1652236525
Short name T783
Test name
Test status
Simulation time 31938606 ps
CPU time 2.57 seconds
Started Mar 24 01:50:19 PM PDT 24
Finished Mar 24 01:50:22 PM PDT 24
Peak memory 214872 kb
Host smart-de1fe4e4-a30c-4a45-a5ac-b441c76484ae
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1652236525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.1652236525
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.3426529785
Short name T579
Test name
Test status
Simulation time 1028184556 ps
CPU time 5.95 seconds
Started Mar 24 01:50:23 PM PDT 24
Finished Mar 24 01:50:29 PM PDT 24
Peak memory 209412 kb
Host smart-92d1d06d-5cf2-4b72-9add-cb9ce7e4a5c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426529785 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.3426529785
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.4037098997
Short name T180
Test name
Test status
Simulation time 411772106 ps
CPU time 2.15 seconds
Started Mar 24 01:50:17 PM PDT 24
Finished Mar 24 01:50:20 PM PDT 24
Peak memory 207828 kb
Host smart-432ffa53-54d2-41a9-83e4-3582b8841022
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037098997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.4037098997
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.108391335
Short name T289
Test name
Test status
Simulation time 93661826 ps
CPU time 3.53 seconds
Started Mar 24 01:50:22 PM PDT 24
Finished Mar 24 01:50:26 PM PDT 24
Peak memory 209508 kb
Host smart-f1cf1184-3fff-436c-813c-692aa6ab82b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=108391335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.108391335
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.1277115126
Short name T14
Test name
Test status
Simulation time 86808342 ps
CPU time 4.44 seconds
Started Mar 24 01:50:23 PM PDT 24
Finished Mar 24 01:50:27 PM PDT 24
Peak memory 211080 kb
Host smart-ba06307c-89ad-426b-99c4-b95b3439ff9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277115126 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.1277115126
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.60545149
Short name T452
Test name
Test status
Simulation time 58270468 ps
CPU time 1.38 seconds
Started Mar 24 01:50:24 PM PDT 24
Finished Mar 24 01:50:25 PM PDT 24
Peak memory 206544 kb
Host smart-ba94c1fa-61cf-4cf0-8542-6d5bae337378
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=60545149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.60545149
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.1232422403
Short name T555
Test name
Test status
Simulation time 214948744 ps
CPU time 5.85 seconds
Started Mar 24 01:50:17 PM PDT 24
Finished Mar 24 01:50:24 PM PDT 24
Peak memory 210492 kb
Host smart-c8c9b7ec-0952-4fbc-b3ef-d8146ca26379
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1232422403 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.1232422403
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.2446429514
Short name T92
Test name
Test status
Simulation time 1402248234 ps
CPU time 12.23 seconds
Started Mar 24 01:50:26 PM PDT 24
Finished Mar 24 01:50:39 PM PDT 24
Peak memory 238240 kb
Host smart-47911c69-8415-45bf-a1b6-07287432c57c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446429514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.2446429514
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.1367408046
Short name T2
Test name
Test status
Simulation time 30006249 ps
CPU time 2.23 seconds
Started Mar 24 01:50:17 PM PDT 24
Finished Mar 24 01:50:19 PM PDT 24
Peak memory 207084 kb
Host smart-384a0d7b-070b-4c6a-86d8-62f1ba2ec095
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367408046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.1367408046
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.1007175718
Short name T547
Test name
Test status
Simulation time 458808459 ps
CPU time 7.08 seconds
Started Mar 24 01:50:17 PM PDT 24
Finished Mar 24 01:50:24 PM PDT 24
Peak memory 208356 kb
Host smart-c1375d33-a73f-4bee-b63a-f09998b25d8d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1007175718 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.1007175718
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.952510647
Short name T524
Test name
Test status
Simulation time 63875574 ps
CPU time 3.16 seconds
Started Mar 24 01:50:18 PM PDT 24
Finished Mar 24 01:50:21 PM PDT 24
Peak memory 208888 kb
Host smart-290185b4-4698-4d7b-869b-e5e30704ac97
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=952510647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.952510647
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.4284537950
Short name T676
Test name
Test status
Simulation time 455897253 ps
CPU time 4.3 seconds
Started Mar 24 01:50:16 PM PDT 24
Finished Mar 24 01:50:21 PM PDT 24
Peak memory 209128 kb
Host smart-9f439d7d-3250-439c-a9fd-207931b77cb7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4284537950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.4284537950
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.1515757632
Short name T648
Test name
Test status
Simulation time 445857557 ps
CPU time 7.44 seconds
Started Mar 24 01:50:29 PM PDT 24
Finished Mar 24 01:50:37 PM PDT 24
Peak memory 214700 kb
Host smart-6c8224eb-a672-4613-8de8-6ec0956e9cf2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1515757632 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.1515757632
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.387819628
Short name T786
Test name
Test status
Simulation time 469052647 ps
CPU time 3.56 seconds
Started Mar 24 01:50:14 PM PDT 24
Finished Mar 24 01:50:17 PM PDT 24
Peak memory 208952 kb
Host smart-144bcd03-4399-4027-b0f5-c637bfefe16b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=387819628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.387819628
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.1860109387
Short name T745
Test name
Test status
Simulation time 128613839 ps
CPU time 5.54 seconds
Started Mar 24 01:50:24 PM PDT 24
Finished Mar 24 01:50:29 PM PDT 24
Peak memory 210276 kb
Host smart-29d7cb8b-be7f-445d-99da-660d4ae535a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1860109387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.1860109387
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.679440984
Short name T113
Test name
Test status
Simulation time 605706185 ps
CPU time 3.46 seconds
Started Mar 24 01:50:26 PM PDT 24
Finished Mar 24 01:50:30 PM PDT 24
Peak memory 210696 kb
Host smart-4593652e-e550-442a-9833-66eb3c86e27a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=679440984 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.679440984
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.1277602865
Short name T679
Test name
Test status
Simulation time 10761144 ps
CPU time 0.76 seconds
Started Mar 24 01:52:29 PM PDT 24
Finished Mar 24 01:52:30 PM PDT 24
Peak memory 206340 kb
Host smart-fd6923a9-4c0c-4de1-965e-3cf8352037e7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1277602865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.1277602865
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.1511219923
Short name T379
Test name
Test status
Simulation time 145243836 ps
CPU time 7.78 seconds
Started Mar 24 01:52:23 PM PDT 24
Finished Mar 24 01:52:31 PM PDT 24
Peak memory 215668 kb
Host smart-db121aeb-920a-42e9-927e-cfee295a1a85
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1511219923 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.1511219923
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.2452783040
Short name T60
Test name
Test status
Simulation time 39552701 ps
CPU time 2.37 seconds
Started Mar 24 01:52:23 PM PDT 24
Finished Mar 24 01:52:26 PM PDT 24
Peak memory 214700 kb
Host smart-c6796658-9dd1-4320-8e19-b73bb295f1ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2452783040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.2452783040
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.3417146800
Short name T79
Test name
Test status
Simulation time 2425140600 ps
CPU time 27.73 seconds
Started Mar 24 01:52:29 PM PDT 24
Finished Mar 24 01:52:56 PM PDT 24
Peak memory 214932 kb
Host smart-c25f5881-dce9-4fdf-b9cb-98add06a78b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3417146800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.3417146800
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.3663143216
Short name T322
Test name
Test status
Simulation time 358178328 ps
CPU time 3.32 seconds
Started Mar 24 01:52:22 PM PDT 24
Finished Mar 24 01:52:25 PM PDT 24
Peak memory 211788 kb
Host smart-a0d9c040-28a8-4011-98e6-854facccefb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663143216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.3663143216
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.2646968698
Short name T207
Test name
Test status
Simulation time 41016338 ps
CPU time 2.74 seconds
Started Mar 24 01:52:23 PM PDT 24
Finished Mar 24 01:52:26 PM PDT 24
Peak memory 206548 kb
Host smart-fd3bf864-1a7f-41cf-9f1b-5c375f067777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2646968698 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.2646968698
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.2504397501
Short name T875
Test name
Test status
Simulation time 85041140 ps
CPU time 4.22 seconds
Started Mar 24 01:52:23 PM PDT 24
Finished Mar 24 01:52:28 PM PDT 24
Peak memory 210336 kb
Host smart-2183d446-20b9-4359-8f2c-b85027f7c732
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2504397501 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.2504397501
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.894121949
Short name T810
Test name
Test status
Simulation time 744817972 ps
CPU time 8.74 seconds
Started Mar 24 01:52:24 PM PDT 24
Finished Mar 24 01:52:32 PM PDT 24
Peak memory 208296 kb
Host smart-2777e261-a9bc-4306-acf2-a1974d52e341
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=894121949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.894121949
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.2330571779
Short name T862
Test name
Test status
Simulation time 525059422 ps
CPU time 7.48 seconds
Started Mar 24 01:52:23 PM PDT 24
Finished Mar 24 01:52:31 PM PDT 24
Peak memory 208344 kb
Host smart-4ed841a0-c1f3-4014-bd60-6db2f0305a33
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2330571779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.2330571779
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.216605061
Short name T675
Test name
Test status
Simulation time 61862402 ps
CPU time 3.02 seconds
Started Mar 24 01:52:25 PM PDT 24
Finished Mar 24 01:52:29 PM PDT 24
Peak memory 208872 kb
Host smart-f105588f-9e66-433d-bd58-ae0ce34c6244
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=216605061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.216605061
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.1462466349
Short name T458
Test name
Test status
Simulation time 750819755 ps
CPU time 19.75 seconds
Started Mar 24 01:52:23 PM PDT 24
Finished Mar 24 01:52:43 PM PDT 24
Peak memory 209208 kb
Host smart-4b23ce50-ac5f-4b39-9f00-170462266c21
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1462466349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.1462466349
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.3867525038
Short name T807
Test name
Test status
Simulation time 91764835 ps
CPU time 2.06 seconds
Started Mar 24 01:52:30 PM PDT 24
Finished Mar 24 01:52:32 PM PDT 24
Peak memory 216328 kb
Host smart-1390117c-b639-43b0-9f4c-583c58605c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3867525038 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.3867525038
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.1561623523
Short name T438
Test name
Test status
Simulation time 57751956 ps
CPU time 2.89 seconds
Started Mar 24 01:52:25 PM PDT 24
Finished Mar 24 01:52:28 PM PDT 24
Peak memory 208932 kb
Host smart-b2309adc-56d1-4ef2-ad7d-4ff24913431f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1561623523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.1561623523
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.263226452
Short name T208
Test name
Test status
Simulation time 3331137125 ps
CPU time 28.97 seconds
Started Mar 24 01:52:28 PM PDT 24
Finished Mar 24 01:52:57 PM PDT 24
Peak memory 217984 kb
Host smart-25d56ad6-b423-4440-ad6e-9da04a180bc8
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=263226452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.263226452
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.607021031
Short name T697
Test name
Test status
Simulation time 303565401 ps
CPU time 4.47 seconds
Started Mar 24 01:52:23 PM PDT 24
Finished Mar 24 01:52:28 PM PDT 24
Peak memory 207416 kb
Host smart-6ea9be87-3531-4e8f-94cc-872e44d3c6db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=607021031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.607021031
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.2541563736
Short name T513
Test name
Test status
Simulation time 678383871 ps
CPU time 3.58 seconds
Started Mar 24 01:52:27 PM PDT 24
Finished Mar 24 01:52:31 PM PDT 24
Peak memory 211124 kb
Host smart-2bd35619-574e-4a03-921b-e86a9c26249c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541563736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.2541563736
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.2322051253
Short name T822
Test name
Test status
Simulation time 32548486 ps
CPU time 0.71 seconds
Started Mar 24 01:52:41 PM PDT 24
Finished Mar 24 01:52:42 PM PDT 24
Peak memory 206460 kb
Host smart-ff237538-9741-46d3-ab5a-51df2d82aa85
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2322051253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.2322051253
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.1748704941
Short name T881
Test name
Test status
Simulation time 253658307 ps
CPU time 3.69 seconds
Started Mar 24 01:52:33 PM PDT 24
Finished Mar 24 01:52:36 PM PDT 24
Peak memory 214820 kb
Host smart-be6d1169-5f3a-4a6f-a718-62a67dcc3a38
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1748704941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.1748704941
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.3752218481
Short name T831
Test name
Test status
Simulation time 207700324 ps
CPU time 5.82 seconds
Started Mar 24 01:52:34 PM PDT 24
Finished Mar 24 01:52:40 PM PDT 24
Peak memory 222364 kb
Host smart-933cdaa2-a3be-4abc-9148-2202f71f33c0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3752218481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.3752218481
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.1101762462
Short name T373
Test name
Test status
Simulation time 136277272 ps
CPU time 3.22 seconds
Started Mar 24 01:52:41 PM PDT 24
Finished Mar 24 01:52:44 PM PDT 24
Peak memory 207872 kb
Host smart-a5722a5e-8788-4404-8d72-c53dcec882b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101762462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.1101762462
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.395591685
Short name T898
Test name
Test status
Simulation time 40224339 ps
CPU time 2.81 seconds
Started Mar 24 01:52:41 PM PDT 24
Finished Mar 24 01:52:44 PM PDT 24
Peak memory 221408 kb
Host smart-00badf67-0546-451e-be74-c012fc47bf14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395591685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.395591685
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.3898452778
Short name T578
Test name
Test status
Simulation time 180491624 ps
CPU time 4.69 seconds
Started Mar 24 01:52:41 PM PDT 24
Finished Mar 24 01:52:46 PM PDT 24
Peak memory 210164 kb
Host smart-c31fb33a-4836-451f-a22c-8eb97ea6db91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898452778 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.3898452778
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.537295508
Short name T608
Test name
Test status
Simulation time 162328690 ps
CPU time 2.92 seconds
Started Mar 24 01:52:41 PM PDT 24
Finished Mar 24 01:52:44 PM PDT 24
Peak memory 208164 kb
Host smart-b1a9330b-d843-4ac5-a54f-fbf41f81b297
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=537295508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.537295508
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.3486771864
Short name T660
Test name
Test status
Simulation time 209373108 ps
CPU time 5.27 seconds
Started Mar 24 01:52:33 PM PDT 24
Finished Mar 24 01:52:38 PM PDT 24
Peak memory 207276 kb
Host smart-ef52b6a9-8d5d-4489-90bc-1939cb7f16de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486771864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.3486771864
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.512487877
Short name T470
Test name
Test status
Simulation time 90333450 ps
CPU time 2.82 seconds
Started Mar 24 01:52:32 PM PDT 24
Finished Mar 24 01:52:35 PM PDT 24
Peak memory 207292 kb
Host smart-3a13addc-6841-4bba-875d-4f68439faad7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512487877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.512487877
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.2491633519
Short name T796
Test name
Test status
Simulation time 7715750963 ps
CPU time 55.13 seconds
Started Mar 24 01:52:33 PM PDT 24
Finished Mar 24 01:53:28 PM PDT 24
Peak memory 208404 kb
Host smart-cf391d64-7d90-45ec-b24a-1818901acf6e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2491633519 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.2491633519
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.1047810346
Short name T94
Test name
Test status
Simulation time 147859944 ps
CPU time 2.55 seconds
Started Mar 24 01:52:32 PM PDT 24
Finished Mar 24 01:52:35 PM PDT 24
Peak memory 207140 kb
Host smart-e04e17d5-9e5c-4536-a3ce-bc64adf8361d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1047810346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.1047810346
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.2043750843
Short name T435
Test name
Test status
Simulation time 159423867 ps
CPU time 2.42 seconds
Started Mar 24 01:52:34 PM PDT 24
Finished Mar 24 01:52:36 PM PDT 24
Peak memory 216316 kb
Host smart-7bcd0458-23d7-41c7-bee8-73ae6bfb46d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2043750843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.2043750843
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.2120626761
Short name T395
Test name
Test status
Simulation time 178113360 ps
CPU time 2.99 seconds
Started Mar 24 01:52:27 PM PDT 24
Finished Mar 24 01:52:31 PM PDT 24
Peak memory 207136 kb
Host smart-104f6bbc-c9ee-4a1b-8bb2-6d71c1388646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120626761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.2120626761
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.2671792197
Short name T99
Test name
Test status
Simulation time 1581255594 ps
CPU time 56.22 seconds
Started Mar 24 01:52:32 PM PDT 24
Finished Mar 24 01:53:29 PM PDT 24
Peak memory 210212 kb
Host smart-8a29d7fa-9cb0-406c-af85-31ebe17425cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671792197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.2671792197
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.1372594514
Short name T887
Test name
Test status
Simulation time 147817608 ps
CPU time 1.89 seconds
Started Mar 24 01:52:32 PM PDT 24
Finished Mar 24 01:52:34 PM PDT 24
Peak memory 210184 kb
Host smart-e6b4b438-6c50-4b7d-9024-6f8d56c95890
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1372594514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.1372594514
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.1380306741
Short name T617
Test name
Test status
Simulation time 13746740 ps
CPU time 0.94 seconds
Started Mar 24 01:52:40 PM PDT 24
Finished Mar 24 01:52:41 PM PDT 24
Peak memory 206628 kb
Host smart-41850214-bdd0-43f5-a3ff-c850545baa8d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380306741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.1380306741
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.1189187071
Short name T366
Test name
Test status
Simulation time 71743440 ps
CPU time 4.38 seconds
Started Mar 24 01:52:37 PM PDT 24
Finished Mar 24 01:52:41 PM PDT 24
Peak memory 214728 kb
Host smart-98f5a1f9-b260-4083-bf11-92c9952dc712
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1189187071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.1189187071
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.2205461922
Short name T38
Test name
Test status
Simulation time 127352370 ps
CPU time 3.75 seconds
Started Mar 24 01:52:43 PM PDT 24
Finished Mar 24 01:52:48 PM PDT 24
Peak memory 209728 kb
Host smart-a8bf4c05-ba6e-47fe-ba17-042140c28f58
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2205461922 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.2205461922
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.1040093384
Short name T826
Test name
Test status
Simulation time 382839075 ps
CPU time 3.07 seconds
Started Mar 24 01:52:35 PM PDT 24
Finished Mar 24 01:52:39 PM PDT 24
Peak memory 218764 kb
Host smart-9267b205-7569-489d-bf23-1fc9d669f3c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1040093384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.1040093384
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.3972951551
Short name T77
Test name
Test status
Simulation time 72278215 ps
CPU time 3.79 seconds
Started Mar 24 01:52:37 PM PDT 24
Finished Mar 24 01:52:41 PM PDT 24
Peak memory 214808 kb
Host smart-a7ff1296-78e1-492e-bf68-a8cdb9722a94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3972951551 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.3972951551
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.3638767306
Short name T214
Test name
Test status
Simulation time 678198688 ps
CPU time 5.39 seconds
Started Mar 24 01:52:38 PM PDT 24
Finished Mar 24 01:52:44 PM PDT 24
Peak memory 210256 kb
Host smart-ea2e5c8e-42fa-4830-9451-b4a62246f787
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3638767306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.3638767306
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.2841068772
Short name T797
Test name
Test status
Simulation time 735885526 ps
CPU time 9.4 seconds
Started Mar 24 01:52:37 PM PDT 24
Finished Mar 24 01:52:46 PM PDT 24
Peak memory 209628 kb
Host smart-5e6cfe4f-1b0a-49d8-8b70-bf9a8f8d5ae6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2841068772 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.2841068772
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.1941151201
Short name T573
Test name
Test status
Simulation time 26579867 ps
CPU time 2.04 seconds
Started Mar 24 01:52:34 PM PDT 24
Finished Mar 24 01:52:36 PM PDT 24
Peak memory 208812 kb
Host smart-1996c07b-2cb9-40d5-ae03-80dfee4f5c56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941151201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.1941151201
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.2529189097
Short name T74
Test name
Test status
Simulation time 611073994 ps
CPU time 7 seconds
Started Mar 24 01:52:37 PM PDT 24
Finished Mar 24 01:52:45 PM PDT 24
Peak memory 208352 kb
Host smart-b86b2569-0911-4e49-b316-a7a8e1623ba4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2529189097 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.2529189097
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.4232527221
Short name T278
Test name
Test status
Simulation time 91242677 ps
CPU time 4.23 seconds
Started Mar 24 01:52:37 PM PDT 24
Finished Mar 24 01:52:41 PM PDT 24
Peak memory 209336 kb
Host smart-a2052217-5689-44a7-a810-c865e08da822
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4232527221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.4232527221
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.3578957224
Short name T318
Test name
Test status
Simulation time 90259185 ps
CPU time 2.37 seconds
Started Mar 24 01:52:40 PM PDT 24
Finished Mar 24 01:52:42 PM PDT 24
Peak memory 207144 kb
Host smart-bbd784f6-5896-4625-aa57-2ec781703000
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3578957224 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.3578957224
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.2054159989
Short name T825
Test name
Test status
Simulation time 50568707 ps
CPU time 2.69 seconds
Started Mar 24 01:52:43 PM PDT 24
Finished Mar 24 01:52:46 PM PDT 24
Peak memory 208276 kb
Host smart-51e65d9c-3650-497b-880d-c88bcc75a02b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2054159989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.2054159989
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.3658874221
Short name T891
Test name
Test status
Simulation time 590848235 ps
CPU time 6.48 seconds
Started Mar 24 01:52:38 PM PDT 24
Finished Mar 24 01:52:44 PM PDT 24
Peak memory 208744 kb
Host smart-ca32d442-fabe-4c1a-88a1-22905f466fc4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658874221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.3658874221
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.4222253279
Short name T211
Test name
Test status
Simulation time 820118521 ps
CPU time 36.52 seconds
Started Mar 24 01:52:44 PM PDT 24
Finished Mar 24 01:53:20 PM PDT 24
Peak memory 222892 kb
Host smart-40209662-ddb0-4a32-9d86-d19acd1146ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4222253279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.4222253279
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.4289157895
Short name T813
Test name
Test status
Simulation time 14036024072 ps
CPU time 85.1 seconds
Started Mar 24 01:52:37 PM PDT 24
Finished Mar 24 01:54:02 PM PDT 24
Peak memory 209240 kb
Host smart-edc83552-5c36-4c52-8197-4dc5a4d1c80f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289157895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.4289157895
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.366023370
Short name T186
Test name
Test status
Simulation time 73573897 ps
CPU time 3.18 seconds
Started Mar 24 01:52:40 PM PDT 24
Finished Mar 24 01:52:44 PM PDT 24
Peak memory 210620 kb
Host smart-2734b160-d9f5-4402-8576-00164b4125d0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=366023370 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.366023370
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.3966377743
Short name T509
Test name
Test status
Simulation time 13639676 ps
CPU time 0.72 seconds
Started Mar 24 01:52:45 PM PDT 24
Finished Mar 24 01:52:46 PM PDT 24
Peak memory 206436 kb
Host smart-4aca37c1-66a9-41de-89c4-03c740287b2f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966377743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.3966377743
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.977261659
Short name T376
Test name
Test status
Simulation time 176938075 ps
CPU time 7.73 seconds
Started Mar 24 01:52:42 PM PDT 24
Finished Mar 24 01:52:50 PM PDT 24
Peak memory 214924 kb
Host smart-63967efd-0c23-4371-8fcb-a2b7799345c1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=977261659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.977261659
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.853049925
Short name T816
Test name
Test status
Simulation time 34283614 ps
CPU time 2.39 seconds
Started Mar 24 01:52:42 PM PDT 24
Finished Mar 24 01:52:45 PM PDT 24
Peak memory 209412 kb
Host smart-fc1e40cd-776b-40d5-82cd-aad697b44d2e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853049925 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.853049925
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.91381897
Short name T884
Test name
Test status
Simulation time 258391186 ps
CPU time 5.99 seconds
Started Mar 24 01:52:44 PM PDT 24
Finished Mar 24 01:52:50 PM PDT 24
Peak memory 214764 kb
Host smart-0686692d-6d6c-4d17-9d48-763588a91f42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91381897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.91381897
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.3822746859
Short name T572
Test name
Test status
Simulation time 443656097 ps
CPU time 4.76 seconds
Started Mar 24 01:52:43 PM PDT 24
Finished Mar 24 01:52:48 PM PDT 24
Peak memory 220716 kb
Host smart-926215f7-221b-4318-b0e8-9e40f687c24e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3822746859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.3822746859
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.1426504195
Short name T720
Test name
Test status
Simulation time 212759746 ps
CPU time 5.04 seconds
Started Mar 24 01:52:40 PM PDT 24
Finished Mar 24 01:52:45 PM PDT 24
Peak memory 210220 kb
Host smart-20f1f57b-8178-42b7-8a3b-d7f43183e7c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426504195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.1426504195
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.3565293811
Short name T574
Test name
Test status
Simulation time 218100293 ps
CPU time 6.44 seconds
Started Mar 24 01:52:42 PM PDT 24
Finished Mar 24 01:52:48 PM PDT 24
Peak memory 207140 kb
Host smart-fce8155f-ddf7-414e-b484-93796922895f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3565293811 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.3565293811
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.1040644710
Short name T854
Test name
Test status
Simulation time 79162248 ps
CPU time 2.89 seconds
Started Mar 24 01:52:43 PM PDT 24
Finished Mar 24 01:52:47 PM PDT 24
Peak memory 207312 kb
Host smart-bd2c8b22-3a41-48a3-81d4-82aff546626b
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040644710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.1040644710
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.1445773716
Short name T737
Test name
Test status
Simulation time 338301825 ps
CPU time 1.97 seconds
Started Mar 24 01:52:43 PM PDT 24
Finished Mar 24 01:52:45 PM PDT 24
Peak memory 207984 kb
Host smart-cdf63a1f-b390-4ec1-a55d-d21a4946e3d1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1445773716 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.1445773716
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.1726134679
Short name T624
Test name
Test status
Simulation time 163594479 ps
CPU time 4.93 seconds
Started Mar 24 01:52:41 PM PDT 24
Finished Mar 24 01:52:46 PM PDT 24
Peak memory 208344 kb
Host smart-81aeb5e1-cb0d-4c79-b609-02ca138ece82
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1726134679 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.1726134679
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.2813122634
Short name T329
Test name
Test status
Simulation time 103289358 ps
CPU time 2.36 seconds
Started Mar 24 01:52:42 PM PDT 24
Finished Mar 24 01:52:45 PM PDT 24
Peak memory 216300 kb
Host smart-4cb33491-5375-40aa-9b56-20b83d9021e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2813122634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.2813122634
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.1704452009
Short name T394
Test name
Test status
Simulation time 69611526 ps
CPU time 3.23 seconds
Started Mar 24 01:52:41 PM PDT 24
Finished Mar 24 01:52:45 PM PDT 24
Peak memory 209016 kb
Host smart-12dfb3fa-afc5-4889-b0d2-bbf63ce91ce3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1704452009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.1704452009
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.3535855595
Short name T48
Test name
Test status
Simulation time 1597560608 ps
CPU time 41.19 seconds
Started Mar 24 01:52:42 PM PDT 24
Finished Mar 24 01:53:24 PM PDT 24
Peak memory 216820 kb
Host smart-ef34a61e-fcc1-4ed8-bc94-be22154542cc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535855595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.3535855595
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.2435279998
Short name T702
Test name
Test status
Simulation time 122523971 ps
CPU time 5.29 seconds
Started Mar 24 01:52:41 PM PDT 24
Finished Mar 24 01:52:46 PM PDT 24
Peak memory 218920 kb
Host smart-8830b783-791f-485b-86db-bee63de1a7f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2435279998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.2435279998
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.382467814
Short name T667
Test name
Test status
Simulation time 154701011 ps
CPU time 2.65 seconds
Started Mar 24 01:52:41 PM PDT 24
Finished Mar 24 01:52:44 PM PDT 24
Peak memory 210696 kb
Host smart-d613518f-8eff-4088-83ce-fd9bef00405f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=382467814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.382467814
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.2466613755
Short name T594
Test name
Test status
Simulation time 6975206 ps
CPU time 0.72 seconds
Started Mar 24 01:52:48 PM PDT 24
Finished Mar 24 01:52:49 PM PDT 24
Peak memory 206372 kb
Host smart-de8a32c3-49de-43f0-9c2e-089c5d9148cf
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2466613755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.2466613755
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.3498626889
Short name T135
Test name
Test status
Simulation time 47218576 ps
CPU time 3.64 seconds
Started Mar 24 01:52:48 PM PDT 24
Finished Mar 24 01:52:52 PM PDT 24
Peak memory 223044 kb
Host smart-7cdbda06-e88d-43ec-922c-2480d44ba3fd
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3498626889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.3498626889
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.2383113767
Short name T719
Test name
Test status
Simulation time 57859616 ps
CPU time 3.4 seconds
Started Mar 24 01:52:46 PM PDT 24
Finished Mar 24 01:52:49 PM PDT 24
Peak memory 208916 kb
Host smart-5f3c6174-03e9-4fea-95c0-d866e0026444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383113767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.2383113767
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.2546127545
Short name T529
Test name
Test status
Simulation time 94434640 ps
CPU time 2.29 seconds
Started Mar 24 01:52:46 PM PDT 24
Finished Mar 24 01:52:48 PM PDT 24
Peak memory 208124 kb
Host smart-3467a85d-5703-4ef9-afc3-21916e1c7016
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546127545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.2546127545
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.4170301924
Short name T803
Test name
Test status
Simulation time 92794857 ps
CPU time 4.19 seconds
Started Mar 24 01:52:47 PM PDT 24
Finished Mar 24 01:52:52 PM PDT 24
Peak memory 209136 kb
Host smart-e8465b2f-24cb-4777-b6fc-37315459a698
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170301924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.4170301924
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.5804230
Short name T6
Test name
Test status
Simulation time 413506026 ps
CPU time 3.6 seconds
Started Mar 24 01:52:46 PM PDT 24
Finished Mar 24 01:52:50 PM PDT 24
Peak memory 209480 kb
Host smart-e38ead15-ce22-4a85-a125-97dfc84574c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=5804230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.5804230
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_sideload.258511119
Short name T504
Test name
Test status
Simulation time 64960987 ps
CPU time 3.46 seconds
Started Mar 24 01:52:47 PM PDT 24
Finished Mar 24 01:52:51 PM PDT 24
Peak memory 209116 kb
Host smart-192ed697-a3d0-454a-9ea8-134a26465b3c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=258511119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.258511119
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.2665537743
Short name T420
Test name
Test status
Simulation time 71288433 ps
CPU time 3.61 seconds
Started Mar 24 01:52:47 PM PDT 24
Finished Mar 24 01:52:51 PM PDT 24
Peak memory 207324 kb
Host smart-c2e9d071-0f79-47cd-a06d-64269d246eeb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2665537743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.2665537743
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.512495041
Short name T682
Test name
Test status
Simulation time 1795821592 ps
CPU time 54.3 seconds
Started Mar 24 01:52:46 PM PDT 24
Finished Mar 24 01:53:40 PM PDT 24
Peak memory 208704 kb
Host smart-c668e625-7fac-4f4e-8da1-f2ecab50496f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=512495041 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.512495041
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.3425240115
Short name T762
Test name
Test status
Simulation time 135206454 ps
CPU time 2.82 seconds
Started Mar 24 01:52:50 PM PDT 24
Finished Mar 24 01:52:53 PM PDT 24
Peak memory 208960 kb
Host smart-4e5c2f14-8cf3-4b7e-8a8c-73d417b2ac70
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3425240115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.3425240115
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.2710109509
Short name T646
Test name
Test status
Simulation time 164443814 ps
CPU time 3.75 seconds
Started Mar 24 01:52:46 PM PDT 24
Finished Mar 24 01:52:50 PM PDT 24
Peak memory 208860 kb
Host smart-5cc0f05e-edd5-47bd-9a06-cbbd61028a99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2710109509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.2710109509
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.2910797867
Short name T414
Test name
Test status
Simulation time 41848057 ps
CPU time 1.93 seconds
Started Mar 24 01:52:43 PM PDT 24
Finished Mar 24 01:52:46 PM PDT 24
Peak memory 207200 kb
Host smart-2165b39c-3d9a-40ce-8509-ec2ba10c9ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2910797867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.2910797867
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.1591803508
Short name T736
Test name
Test status
Simulation time 1479813291 ps
CPU time 30.42 seconds
Started Mar 24 01:52:46 PM PDT 24
Finished Mar 24 01:53:17 PM PDT 24
Peak memory 216064 kb
Host smart-6a8aebae-37fd-4599-81f4-603654bb78f6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591803508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.1591803508
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/24.keymgr_stress_all_with_rand_reset.1316305798
Short name T874
Test name
Test status
Simulation time 493704903 ps
CPU time 8.97 seconds
Started Mar 24 01:52:47 PM PDT 24
Finished Mar 24 01:52:56 PM PDT 24
Peak memory 223064 kb
Host smart-f68753e0-7444-4d33-ad81-fb3ce4d35b3a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1316305798 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all_with_rand_reset.1316305798
Directory /workspace/24.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.42806864
Short name T840
Test name
Test status
Simulation time 529095147 ps
CPU time 6.28 seconds
Started Mar 24 01:52:46 PM PDT 24
Finished Mar 24 01:52:53 PM PDT 24
Peak memory 210436 kb
Host smart-b5dec668-4dce-407a-8342-0bf8a381d227
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42806864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.42806864
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.3369713032
Short name T91
Test name
Test status
Simulation time 207195369 ps
CPU time 1.85 seconds
Started Mar 24 01:52:47 PM PDT 24
Finished Mar 24 01:52:49 PM PDT 24
Peak memory 210268 kb
Host smart-4d99a644-885d-4061-97d6-000673bca2dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369713032 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.3369713032
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.67194705
Short name T789
Test name
Test status
Simulation time 9013124 ps
CPU time 0.86 seconds
Started Mar 24 01:52:54 PM PDT 24
Finished Mar 24 01:52:55 PM PDT 24
Peak memory 206396 kb
Host smart-3b3c89c7-c3bc-495c-8a6b-28f4f11d14d3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67194705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.67194705
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.2528403969
Short name T857
Test name
Test status
Simulation time 1645888574 ps
CPU time 90.75 seconds
Started Mar 24 01:52:47 PM PDT 24
Finished Mar 24 01:54:18 PM PDT 24
Peak memory 215868 kb
Host smart-24a724e6-c37b-404c-bd96-5b484a433b40
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2528403969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.2528403969
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.3527731241
Short name T837
Test name
Test status
Simulation time 2115164758 ps
CPU time 44.13 seconds
Started Mar 24 01:52:47 PM PDT 24
Finished Mar 24 01:53:31 PM PDT 24
Peak memory 218548 kb
Host smart-1dcf729a-2645-4109-920b-d9078eb053cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3527731241 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.3527731241
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.2619341681
Short name T292
Test name
Test status
Simulation time 180271075 ps
CPU time 6.54 seconds
Started Mar 24 01:52:54 PM PDT 24
Finished Mar 24 01:53:01 PM PDT 24
Peak memory 221516 kb
Host smart-6672642f-817b-4d3e-a640-d5071a6bf520
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619341681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.2619341681
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.502901884
Short name T274
Test name
Test status
Simulation time 264081177 ps
CPU time 3.89 seconds
Started Mar 24 01:52:54 PM PDT 24
Finished Mar 24 01:52:58 PM PDT 24
Peak memory 210188 kb
Host smart-f061cd59-3805-4859-9db0-c74773260069
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502901884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.502901884
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.627113244
Short name T733
Test name
Test status
Simulation time 401831582 ps
CPU time 5 seconds
Started Mar 24 01:52:47 PM PDT 24
Finished Mar 24 01:52:53 PM PDT 24
Peak memory 207736 kb
Host smart-b51c9fcd-6393-4e9e-8d31-f2943ea889d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=627113244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.627113244
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.550703755
Short name T781
Test name
Test status
Simulation time 252568540 ps
CPU time 2.64 seconds
Started Mar 24 01:52:47 PM PDT 24
Finished Mar 24 01:52:50 PM PDT 24
Peak memory 208908 kb
Host smart-ba437c55-7943-41c5-8b45-33680024d26e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=550703755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.550703755
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.3360641348
Short name T528
Test name
Test status
Simulation time 823693069 ps
CPU time 3.21 seconds
Started Mar 24 01:52:46 PM PDT 24
Finished Mar 24 01:52:50 PM PDT 24
Peak memory 207184 kb
Host smart-710b8710-987d-442f-b841-c7b434268146
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3360641348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.3360641348
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.1075594263
Short name T478
Test name
Test status
Simulation time 237506288 ps
CPU time 3.24 seconds
Started Mar 24 01:52:51 PM PDT 24
Finished Mar 24 01:52:55 PM PDT 24
Peak memory 207244 kb
Host smart-44dd46e3-981d-4949-ad44-bb899964bce3
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1075594263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.1075594263
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.1989403686
Short name T616
Test name
Test status
Simulation time 310270725 ps
CPU time 7.47 seconds
Started Mar 24 01:52:45 PM PDT 24
Finished Mar 24 01:52:53 PM PDT 24
Peak memory 209252 kb
Host smart-d9604797-285f-443e-b6eb-487b5cfdc5fc
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1989403686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.1989403686
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.2730880027
Short name T200
Test name
Test status
Simulation time 678208002 ps
CPU time 4.19 seconds
Started Mar 24 01:52:55 PM PDT 24
Finished Mar 24 01:52:59 PM PDT 24
Peak memory 209728 kb
Host smart-8b126d9d-a0c0-41a1-85fc-3ad38cf3f81c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2730880027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.2730880027
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.3365237163
Short name T707
Test name
Test status
Simulation time 362238939 ps
CPU time 4.85 seconds
Started Mar 24 01:52:47 PM PDT 24
Finished Mar 24 01:52:52 PM PDT 24
Peak memory 208832 kb
Host smart-e74ace03-ca6f-4d8f-b8b0-5fc2d366ca44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3365237163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.3365237163
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.137161776
Short name T705
Test name
Test status
Simulation time 388055217 ps
CPU time 8.16 seconds
Started Mar 24 01:52:52 PM PDT 24
Finished Mar 24 01:53:00 PM PDT 24
Peak memory 208276 kb
Host smart-f017c52f-0482-412b-b795-642fab44493d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137161776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.137161776
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.959336333
Short name T50
Test name
Test status
Simulation time 373006338 ps
CPU time 1.55 seconds
Started Mar 24 01:52:50 PM PDT 24
Finished Mar 24 01:52:52 PM PDT 24
Peak memory 210340 kb
Host smart-fb92b361-05f6-46d1-af47-ea4d68d2434e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=959336333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.959336333
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.2445153758
Short name T577
Test name
Test status
Simulation time 24963785 ps
CPU time 0.89 seconds
Started Mar 24 01:52:58 PM PDT 24
Finished Mar 24 01:52:59 PM PDT 24
Peak memory 206328 kb
Host smart-38d24cb4-8e42-48e8-9e70-4be7406bdfb0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2445153758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.2445153758
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.2822105929
Short name T234
Test name
Test status
Simulation time 99828074 ps
CPU time 3.26 seconds
Started Mar 24 01:52:54 PM PDT 24
Finished Mar 24 01:52:57 PM PDT 24
Peak memory 214836 kb
Host smart-70738de1-3d7b-46ee-98fd-0a812a0b1c96
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2822105929 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.2822105929
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.7566705
Short name T896
Test name
Test status
Simulation time 258805544 ps
CPU time 4.98 seconds
Started Mar 24 01:52:56 PM PDT 24
Finished Mar 24 01:53:02 PM PDT 24
Peak memory 223372 kb
Host smart-c83991a8-f2a1-4ad1-9815-629436698543
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=7566705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.7566705
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.3922119863
Short name T4
Test name
Test status
Simulation time 325915216 ps
CPU time 3.92 seconds
Started Mar 24 01:52:50 PM PDT 24
Finished Mar 24 01:52:54 PM PDT 24
Peak memory 214912 kb
Host smart-3f339578-034f-4d9e-866b-d5158d190302
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3922119863 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.3922119863
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.1950724461
Short name T889
Test name
Test status
Simulation time 265058605 ps
CPU time 6.4 seconds
Started Mar 24 01:52:57 PM PDT 24
Finished Mar 24 01:53:03 PM PDT 24
Peak memory 214708 kb
Host smart-07610a9c-2114-499e-baec-42316fe5a6b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1950724461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.1950724461
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.2907421231
Short name T868
Test name
Test status
Simulation time 5011962422 ps
CPU time 32.8 seconds
Started Mar 24 01:52:58 PM PDT 24
Finished Mar 24 01:53:30 PM PDT 24
Peak memory 223120 kb
Host smart-936aa311-5d53-4be8-996c-2c0846f36b9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2907421231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.2907421231
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.1094781613
Short name T465
Test name
Test status
Simulation time 30192610 ps
CPU time 1.84 seconds
Started Mar 24 01:52:52 PM PDT 24
Finished Mar 24 01:52:54 PM PDT 24
Peak memory 206524 kb
Host smart-a79878ed-8305-4dd5-89a1-d7d5c8983784
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094781613 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.1094781613
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.4292982961
Short name T255
Test name
Test status
Simulation time 207118645 ps
CPU time 6.78 seconds
Started Mar 24 01:52:53 PM PDT 24
Finished Mar 24 01:53:00 PM PDT 24
Peak memory 210332 kb
Host smart-e221bff8-fe5f-4bce-bbd7-17c4d2cf3185
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4292982961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.4292982961
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.4068697759
Short name T765
Test name
Test status
Simulation time 147708968 ps
CPU time 3.31 seconds
Started Mar 24 01:52:49 PM PDT 24
Finished Mar 24 01:52:53 PM PDT 24
Peak memory 207312 kb
Host smart-5f85ff3a-b7cf-4205-b443-8e1bb3d7739f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068697759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.4068697759
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.2846026894
Short name T817
Test name
Test status
Simulation time 3597035909 ps
CPU time 38.45 seconds
Started Mar 24 01:52:50 PM PDT 24
Finished Mar 24 01:53:28 PM PDT 24
Peak memory 209036 kb
Host smart-d4c7d38d-6047-4a04-a90e-75554d228fb2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2846026894 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.2846026894
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.2935547574
Short name T472
Test name
Test status
Simulation time 59799849 ps
CPU time 3.01 seconds
Started Mar 24 01:52:51 PM PDT 24
Finished Mar 24 01:52:54 PM PDT 24
Peak memory 208996 kb
Host smart-5aa7429d-82be-49dc-ba78-719644da0c84
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935547574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.2935547574
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.1817086091
Short name T266
Test name
Test status
Simulation time 471998972 ps
CPU time 5.7 seconds
Started Mar 24 01:52:50 PM PDT 24
Finished Mar 24 01:52:56 PM PDT 24
Peak memory 207144 kb
Host smart-f337b9c6-37ad-47e3-8126-20793d3360ff
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1817086091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.1817086091
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.4265740414
Short name T179
Test name
Test status
Simulation time 140792976 ps
CPU time 3.77 seconds
Started Mar 24 01:52:56 PM PDT 24
Finished Mar 24 01:53:00 PM PDT 24
Peak memory 209084 kb
Host smart-5076cdd6-d482-404e-9739-f9d7d6ffe26c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4265740414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.4265740414
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.86455805
Short name T118
Test name
Test status
Simulation time 96669687 ps
CPU time 2.7 seconds
Started Mar 24 01:52:54 PM PDT 24
Finished Mar 24 01:52:57 PM PDT 24
Peak memory 209096 kb
Host smart-87db00f6-724f-4a60-b46b-1256665619a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86455805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.86455805
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.2117680933
Short name T743
Test name
Test status
Simulation time 282377614 ps
CPU time 11.01 seconds
Started Mar 24 01:52:57 PM PDT 24
Finished Mar 24 01:53:08 PM PDT 24
Peak memory 222936 kb
Host smart-5e8ae63e-88ef-41f3-8283-d07f78f316dc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117680933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.2117680933
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.3202988040
Short name T740
Test name
Test status
Simulation time 519360333 ps
CPU time 6.16 seconds
Started Mar 24 01:52:57 PM PDT 24
Finished Mar 24 01:53:03 PM PDT 24
Peak memory 208360 kb
Host smart-b73d54cc-092e-42a8-95af-3cdf298454d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3202988040 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.3202988040
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.3761721454
Short name T769
Test name
Test status
Simulation time 740242030 ps
CPU time 2.21 seconds
Started Mar 24 01:52:57 PM PDT 24
Finished Mar 24 01:52:59 PM PDT 24
Peak memory 210372 kb
Host smart-81e00e86-f3f9-4b34-93ad-dda9cfbbcf97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3761721454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.3761721454
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.3967281448
Short name T406
Test name
Test status
Simulation time 28624637 ps
CPU time 0.79 seconds
Started Mar 24 01:53:01 PM PDT 24
Finished Mar 24 01:53:02 PM PDT 24
Peak memory 206668 kb
Host smart-7e59cded-eaab-472a-935e-9bdc70c32fa3
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3967281448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.3967281448
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.2012432203
Short name T721
Test name
Test status
Simulation time 139945915 ps
CPU time 2.51 seconds
Started Mar 24 01:53:03 PM PDT 24
Finished Mar 24 01:53:06 PM PDT 24
Peak memory 209844 kb
Host smart-aa9c1289-8c4d-4c01-b773-3fb1f88dece5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2012432203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.2012432203
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.2971945423
Short name T588
Test name
Test status
Simulation time 529019674 ps
CPU time 15.16 seconds
Started Mar 24 01:53:01 PM PDT 24
Finished Mar 24 01:53:16 PM PDT 24
Peak memory 208960 kb
Host smart-ce9c57f7-6d5e-43e1-82eb-d03cd67e42ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2971945423 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.2971945423
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.4089740806
Short name T849
Test name
Test status
Simulation time 262740505 ps
CPU time 4.42 seconds
Started Mar 24 01:53:02 PM PDT 24
Finished Mar 24 01:53:07 PM PDT 24
Peak memory 210016 kb
Host smart-c0a2213b-9dad-4564-be38-222202b403a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089740806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.4089740806
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.3147371324
Short name T270
Test name
Test status
Simulation time 1528538065 ps
CPU time 8.75 seconds
Started Mar 24 01:53:01 PM PDT 24
Finished Mar 24 01:53:09 PM PDT 24
Peak memory 222816 kb
Host smart-f167f672-99fa-4830-a47b-dcc16d8fac65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3147371324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.3147371324
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.1971683637
Short name T44
Test name
Test status
Simulation time 283717022 ps
CPU time 5.97 seconds
Started Mar 24 01:53:01 PM PDT 24
Finished Mar 24 01:53:08 PM PDT 24
Peak memory 208064 kb
Host smart-85cbb0f0-d745-4df5-bdd4-b8874258c8f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1971683637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.1971683637
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.511174906
Short name T621
Test name
Test status
Simulation time 7309346837 ps
CPU time 87.52 seconds
Started Mar 24 01:52:56 PM PDT 24
Finished Mar 24 01:54:25 PM PDT 24
Peak memory 221964 kb
Host smart-dd7799b5-1dcf-42bd-a017-148499505b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=511174906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.511174906
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.1456701062
Short name T341
Test name
Test status
Simulation time 318383959 ps
CPU time 1.97 seconds
Started Mar 24 01:52:55 PM PDT 24
Finished Mar 24 01:52:58 PM PDT 24
Peak memory 208932 kb
Host smart-d2e54837-36d5-41eb-9ee5-0835c58e4f11
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1456701062 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.1456701062
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.2060949571
Short name T686
Test name
Test status
Simulation time 135862701 ps
CPU time 3.14 seconds
Started Mar 24 01:52:56 PM PDT 24
Finished Mar 24 01:53:00 PM PDT 24
Peak memory 208384 kb
Host smart-c76aba0b-3e09-4693-b904-95bf3d55a03f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2060949571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.2060949571
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.2343437810
Short name T657
Test name
Test status
Simulation time 1142233809 ps
CPU time 6.53 seconds
Started Mar 24 01:52:56 PM PDT 24
Finished Mar 24 01:53:03 PM PDT 24
Peak memory 208436 kb
Host smart-453ea183-02af-4d2a-b5fb-46fd8547378c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2343437810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.2343437810
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.1791881773
Short name T714
Test name
Test status
Simulation time 29532768 ps
CPU time 2.19 seconds
Started Mar 24 01:52:56 PM PDT 24
Finished Mar 24 01:52:58 PM PDT 24
Peak memory 207200 kb
Host smart-1573a196-d994-4463-b038-aba7a91db5f8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791881773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.1791881773
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.3736305740
Short name T339
Test name
Test status
Simulation time 146156372 ps
CPU time 2.87 seconds
Started Mar 24 01:53:03 PM PDT 24
Finished Mar 24 01:53:06 PM PDT 24
Peak memory 218472 kb
Host smart-c948fa76-7623-4954-a4d1-43cc32a7a6f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736305740 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.3736305740
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.3779277457
Short name T522
Test name
Test status
Simulation time 63369935 ps
CPU time 2.85 seconds
Started Mar 24 01:52:56 PM PDT 24
Finished Mar 24 01:53:00 PM PDT 24
Peak memory 208324 kb
Host smart-e57369f9-f6ba-414c-8002-f1b98f1fb3b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779277457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.3779277457
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.232768100
Short name T413
Test name
Test status
Simulation time 1425931412 ps
CPU time 10.26 seconds
Started Mar 24 01:53:01 PM PDT 24
Finished Mar 24 01:53:12 PM PDT 24
Peak memory 207268 kb
Host smart-338ba155-26b1-45e5-95dc-a619ff344d30
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=232768100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.232768100
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_stress_all_with_rand_reset.824600773
Short name T626
Test name
Test status
Simulation time 758009186 ps
CPU time 12.22 seconds
Started Mar 24 01:53:04 PM PDT 24
Finished Mar 24 01:53:16 PM PDT 24
Peak memory 222980 kb
Host smart-b4e673ee-507f-4f77-ada3-ce4049efa8ec
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824600773 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all_with_rand_reset.824600773
Directory /workspace/27.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.1748226177
Short name T369
Test name
Test status
Simulation time 63310274 ps
CPU time 3.03 seconds
Started Mar 24 01:53:01 PM PDT 24
Finished Mar 24 01:53:04 PM PDT 24
Peak memory 208200 kb
Host smart-4d43153e-5bbd-481a-8dc7-1287a30ef5e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748226177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.1748226177
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.69001008
Short name T170
Test name
Test status
Simulation time 31597064 ps
CPU time 1.8 seconds
Started Mar 24 01:52:59 PM PDT 24
Finished Mar 24 01:53:01 PM PDT 24
Peak memory 210332 kb
Host smart-6ea21f09-ba5d-4e24-a3e6-a3751d7c3c68
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69001008 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.69001008
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.2906856421
Short name T459
Test name
Test status
Simulation time 108860309 ps
CPU time 0.95 seconds
Started Mar 24 01:53:08 PM PDT 24
Finished Mar 24 01:53:10 PM PDT 24
Peak memory 206416 kb
Host smart-a094d3c0-a7d7-4aad-b0ad-6e27f909e431
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2906856421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.2906856421
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.3362914967
Short name T380
Test name
Test status
Simulation time 36456454 ps
CPU time 2.81 seconds
Started Mar 24 01:53:02 PM PDT 24
Finished Mar 24 01:53:04 PM PDT 24
Peak memory 214772 kb
Host smart-22a39c59-e7d9-44ab-9ec3-9c7a9a6ebed9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3362914967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.3362914967
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.1460552921
Short name T30
Test name
Test status
Simulation time 341461255 ps
CPU time 7.6 seconds
Started Mar 24 01:53:07 PM PDT 24
Finished Mar 24 01:53:16 PM PDT 24
Peak memory 208200 kb
Host smart-5ea42a3f-0c5b-4061-b5e3-ad0f8fead153
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460552921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.1460552921
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.1783102870
Short name T864
Test name
Test status
Simulation time 107051998 ps
CPU time 1.82 seconds
Started Mar 24 01:53:01 PM PDT 24
Finished Mar 24 01:53:03 PM PDT 24
Peak memory 207300 kb
Host smart-495a7413-b240-4b0b-89c9-472f2712d0be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1783102870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.1783102870
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.1884330379
Short name T308
Test name
Test status
Simulation time 2139152072 ps
CPU time 21.41 seconds
Started Mar 24 01:53:00 PM PDT 24
Finished Mar 24 01:53:21 PM PDT 24
Peak memory 214728 kb
Host smart-f5054cc8-f35a-4153-9c5e-cb6995ac3980
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1884330379 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.1884330379
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.2660620238
Short name T673
Test name
Test status
Simulation time 63384415 ps
CPU time 4.18 seconds
Started Mar 24 01:53:01 PM PDT 24
Finished Mar 24 01:53:05 PM PDT 24
Peak memory 210288 kb
Host smart-fd5a88a8-f488-4fc5-85cf-3c5869891dc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2660620238 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.2660620238
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.289102662
Short name T856
Test name
Test status
Simulation time 401727885 ps
CPU time 6.25 seconds
Started Mar 24 01:53:00 PM PDT 24
Finished Mar 24 01:53:07 PM PDT 24
Peak memory 210244 kb
Host smart-54e242e6-a45f-4949-9346-9cef8d871548
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=289102662 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.289102662
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.3673491046
Short name T843
Test name
Test status
Simulation time 128491444 ps
CPU time 5.43 seconds
Started Mar 24 01:53:03 PM PDT 24
Finished Mar 24 01:53:09 PM PDT 24
Peak memory 209140 kb
Host smart-8bb5995e-c241-446c-9364-a1b6e6e2c09e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673491046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.3673491046
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.2061782603
Short name T68
Test name
Test status
Simulation time 471599323 ps
CPU time 6.56 seconds
Started Mar 24 01:53:03 PM PDT 24
Finished Mar 24 01:53:09 PM PDT 24
Peak memory 207168 kb
Host smart-100c649b-6aed-45a8-a544-36beeb349339
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2061782603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.2061782603
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.296860654
Short name T760
Test name
Test status
Simulation time 74725237 ps
CPU time 1.9 seconds
Started Mar 24 01:53:01 PM PDT 24
Finished Mar 24 01:53:03 PM PDT 24
Peak memory 207256 kb
Host smart-e670407d-b7cc-4bd9-a391-4158db3229ad
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=296860654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.296860654
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.2623681058
Short name T564
Test name
Test status
Simulation time 874296257 ps
CPU time 7.18 seconds
Started Mar 24 01:53:01 PM PDT 24
Finished Mar 24 01:53:08 PM PDT 24
Peak memory 209040 kb
Host smart-1c06a455-32cf-4da3-ad47-43ff2661463f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623681058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.2623681058
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.2872375860
Short name T307
Test name
Test status
Simulation time 80900681 ps
CPU time 3.82 seconds
Started Mar 24 01:53:02 PM PDT 24
Finished Mar 24 01:53:06 PM PDT 24
Peak memory 209288 kb
Host smart-b0bd50f5-ac98-4bf4-a7da-e26f74627e4d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2872375860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.2872375860
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.391676504
Short name T517
Test name
Test status
Simulation time 96915487 ps
CPU time 2.13 seconds
Started Mar 24 01:53:05 PM PDT 24
Finished Mar 24 01:53:07 PM PDT 24
Peak memory 214828 kb
Host smart-9b6df18c-e986-4172-8869-70f866e999b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391676504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.391676504
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.921018510
Short name T419
Test name
Test status
Simulation time 25871594 ps
CPU time 2.18 seconds
Started Mar 24 01:53:01 PM PDT 24
Finished Mar 24 01:53:04 PM PDT 24
Peak memory 208900 kb
Host smart-5f0cc69f-df28-40bd-bb77-eacb9d9404f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=921018510 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.921018510
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.3558534272
Short name T223
Test name
Test status
Simulation time 769293123 ps
CPU time 10.06 seconds
Started Mar 24 01:53:05 PM PDT 24
Finished Mar 24 01:53:15 PM PDT 24
Peak memory 217072 kb
Host smart-9d72b456-0919-4a38-a763-53304045f3a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3558534272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.3558534272
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/28.keymgr_stress_all_with_rand_reset.262314723
Short name T67
Test name
Test status
Simulation time 1615583647 ps
CPU time 11.57 seconds
Started Mar 24 01:53:06 PM PDT 24
Finished Mar 24 01:53:18 PM PDT 24
Peak memory 223084 kb
Host smart-439024c8-596e-49ec-aace-57d83589bae7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262314723 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all_with_rand_reset.262314723
Directory /workspace/28.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.890503983
Short name T316
Test name
Test status
Simulation time 268802522 ps
CPU time 8.52 seconds
Started Mar 24 01:53:02 PM PDT 24
Finished Mar 24 01:53:10 PM PDT 24
Peak memory 209084 kb
Host smart-74dd96ed-3fe5-49a2-b41c-a9f6b616c4ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890503983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.890503983
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.2038809319
Short name T370
Test name
Test status
Simulation time 2277242259 ps
CPU time 18.55 seconds
Started Mar 24 01:53:10 PM PDT 24
Finished Mar 24 01:53:29 PM PDT 24
Peak memory 211280 kb
Host smart-d1ca2446-8177-4068-9a5f-efb0a2f455bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2038809319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.2038809319
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.3442893458
Short name T454
Test name
Test status
Simulation time 33970999 ps
CPU time 0.73 seconds
Started Mar 24 01:53:11 PM PDT 24
Finished Mar 24 01:53:12 PM PDT 24
Peak memory 206436 kb
Host smart-2b64a41c-d6eb-4a53-8218-d5406f4531d5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3442893458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.3442893458
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.2706932102
Short name T377
Test name
Test status
Simulation time 177596879 ps
CPU time 3.79 seconds
Started Mar 24 01:53:07 PM PDT 24
Finished Mar 24 01:53:12 PM PDT 24
Peak memory 214636 kb
Host smart-2f65670a-490f-4abf-8426-2037a14ea1b1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2706932102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.2706932102
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.2200598989
Short name T26
Test name
Test status
Simulation time 103112408 ps
CPU time 4.51 seconds
Started Mar 24 01:53:09 PM PDT 24
Finished Mar 24 01:53:14 PM PDT 24
Peak memory 223332 kb
Host smart-6b7dc945-9bc8-4782-8b36-dfe405de06c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2200598989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.2200598989
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.338827907
Short name T53
Test name
Test status
Simulation time 513170098 ps
CPU time 13.84 seconds
Started Mar 24 01:53:07 PM PDT 24
Finished Mar 24 01:53:22 PM PDT 24
Peak memory 214708 kb
Host smart-6d45fb7c-1b5e-421c-8788-01b69f37e8b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338827907 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.338827907
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.3174959831
Short name T386
Test name
Test status
Simulation time 437899588 ps
CPU time 3.52 seconds
Started Mar 24 01:53:07 PM PDT 24
Finished Mar 24 01:53:12 PM PDT 24
Peak memory 214740 kb
Host smart-2e5fadb5-5cc2-4152-8b8b-013499b1e571
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3174959831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.3174959831
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.3324860903
Short name T212
Test name
Test status
Simulation time 437025595 ps
CPU time 3.54 seconds
Started Mar 24 01:53:06 PM PDT 24
Finished Mar 24 01:53:11 PM PDT 24
Peak memory 223004 kb
Host smart-826e4399-2828-4819-a88a-f573cee5cbe4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3324860903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.3324860903
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.3410605088
Short name T830
Test name
Test status
Simulation time 132966969 ps
CPU time 4.95 seconds
Started Mar 24 01:53:06 PM PDT 24
Finished Mar 24 01:53:12 PM PDT 24
Peak memory 222980 kb
Host smart-f29bbd5f-6342-4447-9ede-345175c395d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3410605088 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.3410605088
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.473404721
Short name T480
Test name
Test status
Simulation time 354711279 ps
CPU time 5.11 seconds
Started Mar 24 01:53:05 PM PDT 24
Finished Mar 24 01:53:11 PM PDT 24
Peak memory 208404 kb
Host smart-8c186080-b72c-419e-9c55-29d0932af9ff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=473404721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.473404721
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.2515914848
Short name T633
Test name
Test status
Simulation time 1034302501 ps
CPU time 7.71 seconds
Started Mar 24 01:53:06 PM PDT 24
Finished Mar 24 01:53:14 PM PDT 24
Peak memory 209364 kb
Host smart-6b88e730-f84a-4cbb-86c2-a780f59cf97c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2515914848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.2515914848
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.2210745306
Short name T447
Test name
Test status
Simulation time 254327043 ps
CPU time 7.82 seconds
Started Mar 24 01:53:05 PM PDT 24
Finished Mar 24 01:53:13 PM PDT 24
Peak memory 208716 kb
Host smart-5155def4-4f10-4558-8468-135a9632626f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210745306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.2210745306
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.3482053648
Short name T741
Test name
Test status
Simulation time 3163915805 ps
CPU time 23.85 seconds
Started Mar 24 01:53:06 PM PDT 24
Finished Mar 24 01:53:30 PM PDT 24
Peak memory 208588 kb
Host smart-7b9e68bd-a3da-4929-b4f8-1d4847a8678a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3482053648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.3482053648
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.260481369
Short name T793
Test name
Test status
Simulation time 119028295 ps
CPU time 4.66 seconds
Started Mar 24 01:53:07 PM PDT 24
Finished Mar 24 01:53:12 PM PDT 24
Peak memory 214740 kb
Host smart-48073bd0-c6bf-4d9f-9ca0-c211812c3bff
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=260481369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.260481369
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.2802497525
Short name T713
Test name
Test status
Simulation time 717343282 ps
CPU time 9.25 seconds
Started Mar 24 01:53:07 PM PDT 24
Finished Mar 24 01:53:17 PM PDT 24
Peak memory 207240 kb
Host smart-d65e0f32-7b28-4bd6-8992-3b2243129892
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2802497525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.2802497525
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.719497398
Short name T761
Test name
Test status
Simulation time 2101329249 ps
CPU time 21.43 seconds
Started Mar 24 01:53:10 PM PDT 24
Finished Mar 24 01:53:33 PM PDT 24
Peak memory 221316 kb
Host smart-bf81552e-5681-4da3-915c-1a617ffa4ad1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=719497398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.719497398
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_stress_all_with_rand_reset.1709154790
Short name T114
Test name
Test status
Simulation time 474527573 ps
CPU time 16.02 seconds
Started Mar 24 01:53:11 PM PDT 24
Finished Mar 24 01:53:27 PM PDT 24
Peak memory 221100 kb
Host smart-a3aa0ed5-894a-424e-a1ba-8be9e2beab97
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1709154790 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all_with_rand_reset.1709154790
Directory /workspace/29.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.869345970
Short name T347
Test name
Test status
Simulation time 285845311 ps
CPU time 8.22 seconds
Started Mar 24 01:53:06 PM PDT 24
Finished Mar 24 01:53:15 PM PDT 24
Peak memory 210028 kb
Host smart-ef356b66-65f5-4309-971c-efc5307c17d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=869345970 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.869345970
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.1511149207
Short name T698
Test name
Test status
Simulation time 57551489 ps
CPU time 2.93 seconds
Started Mar 24 01:53:10 PM PDT 24
Finished Mar 24 01:53:14 PM PDT 24
Peak memory 210204 kb
Host smart-64b1b3b5-291e-490d-b879-d8b49ad42f14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511149207 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.1511149207
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.2063836700
Short name T510
Test name
Test status
Simulation time 154924701 ps
CPU time 0.94 seconds
Started Mar 24 01:50:45 PM PDT 24
Finished Mar 24 01:50:46 PM PDT 24
Peak memory 206444 kb
Host smart-1a39d5a0-76ed-4f80-9350-5957a02cab1a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2063836700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.2063836700
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.1478725869
Short name T382
Test name
Test status
Simulation time 1012205424 ps
CPU time 15.02 seconds
Started Mar 24 01:50:31 PM PDT 24
Finished Mar 24 01:50:48 PM PDT 24
Peak memory 215932 kb
Host smart-bcab898a-5a4b-4634-8088-ba9972031e1f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1478725869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.1478725869
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.2424853331
Short name T512
Test name
Test status
Simulation time 193643196 ps
CPU time 5.46 seconds
Started Mar 24 01:50:36 PM PDT 24
Finished Mar 24 01:50:42 PM PDT 24
Peak memory 221240 kb
Host smart-a7efabb9-26a1-4ad7-9ae8-ae47ab0dda76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424853331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.2424853331
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.720913212
Short name T62
Test name
Test status
Simulation time 303293850 ps
CPU time 3.88 seconds
Started Mar 24 01:50:32 PM PDT 24
Finished Mar 24 01:50:37 PM PDT 24
Peak memory 210232 kb
Host smart-90ee5eb2-36cf-4a7b-9850-38f7dac8cdfd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720913212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.720913212
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.3650017636
Short name T623
Test name
Test status
Simulation time 40650869 ps
CPU time 2.66 seconds
Started Mar 24 01:50:31 PM PDT 24
Finished Mar 24 01:50:35 PM PDT 24
Peak memory 219740 kb
Host smart-3e8577bd-0d13-4363-9545-b9bf6bd944b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3650017636 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.3650017636
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_kmac_rsp_err.3420362383
Short name T272
Test name
Test status
Simulation time 169793833 ps
CPU time 6.08 seconds
Started Mar 24 01:50:31 PM PDT 24
Finished Mar 24 01:50:39 PM PDT 24
Peak memory 222036 kb
Host smart-8e865b3c-75e6-4b90-a5d3-671ff2d21db3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3420362383 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_kmac_rsp_err.3420362383
Directory /workspace/3.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.2687743912
Short name T815
Test name
Test status
Simulation time 348994420 ps
CPU time 4.45 seconds
Started Mar 24 01:50:32 PM PDT 24
Finished Mar 24 01:50:37 PM PDT 24
Peak memory 210000 kb
Host smart-9cf8226d-502d-4700-b994-8a4902fa33c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687743912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.2687743912
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.4020658447
Short name T132
Test name
Test status
Simulation time 324784649 ps
CPU time 10.44 seconds
Started Mar 24 01:50:31 PM PDT 24
Finished Mar 24 01:50:41 PM PDT 24
Peak memory 208800 kb
Host smart-78504064-093d-4ca3-bb2d-e3d2de64c9bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020658447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.4020658447
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.3251138693
Short name T12
Test name
Test status
Simulation time 1037380172 ps
CPU time 28.78 seconds
Started Mar 24 01:50:41 PM PDT 24
Finished Mar 24 01:51:10 PM PDT 24
Peak memory 241076 kb
Host smart-3b8d1469-05d6-43a3-bc93-eed76154829c
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3251138693 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.3251138693
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/3.keymgr_sideload.1813844163
Short name T488
Test name
Test status
Simulation time 241112645 ps
CPU time 4.16 seconds
Started Mar 24 01:50:30 PM PDT 24
Finished Mar 24 01:50:35 PM PDT 24
Peak memory 208504 kb
Host smart-c2f7f21c-38b1-4bbc-8760-3603d6afece4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1813844163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.1813844163
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.1152563995
Short name T590
Test name
Test status
Simulation time 615256953 ps
CPU time 6.68 seconds
Started Mar 24 01:50:31 PM PDT 24
Finished Mar 24 01:50:39 PM PDT 24
Peak memory 208188 kb
Host smart-9e2a41ff-a73e-43bb-b3ac-2db034f9feb2
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1152563995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.1152563995
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.3757368854
Short name T247
Test name
Test status
Simulation time 128548704 ps
CPU time 3.32 seconds
Started Mar 24 01:50:31 PM PDT 24
Finished Mar 24 01:50:36 PM PDT 24
Peak memory 208048 kb
Host smart-da10f5b3-5e2d-4504-830b-b63d77904052
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757368854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.3757368854
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.84905614
Short name T805
Test name
Test status
Simulation time 426116495 ps
CPU time 7.42 seconds
Started Mar 24 01:50:30 PM PDT 24
Finished Mar 24 01:50:38 PM PDT 24
Peak memory 208712 kb
Host smart-7bf9b373-8a98-426a-80fb-aee1fb046327
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84905614 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.84905614
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.2833249729
Short name T444
Test name
Test status
Simulation time 34827304 ps
CPU time 2.27 seconds
Started Mar 24 01:50:36 PM PDT 24
Finished Mar 24 01:50:39 PM PDT 24
Peak memory 210956 kb
Host smart-ebba4941-5028-4c61-b372-f2547181f544
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2833249729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.2833249729
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.486911162
Short name T637
Test name
Test status
Simulation time 53945466 ps
CPU time 2.76 seconds
Started Mar 24 01:50:30 PM PDT 24
Finished Mar 24 01:50:34 PM PDT 24
Peak memory 208948 kb
Host smart-467da670-cabb-4bb6-9820-fb6313da8044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486911162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.486911162
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.377004981
Short name T301
Test name
Test status
Simulation time 876816986 ps
CPU time 13.94 seconds
Started Mar 24 01:50:37 PM PDT 24
Finished Mar 24 01:50:51 PM PDT 24
Peak memory 222856 kb
Host smart-6ab7a9b2-1802-457a-b20e-3f48dd0df488
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377004981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.377004981
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_stress_all_with_rand_reset.3526932836
Short name T116
Test name
Test status
Simulation time 2842911268 ps
CPU time 24.97 seconds
Started Mar 24 01:50:37 PM PDT 24
Finished Mar 24 01:51:02 PM PDT 24
Peak memory 223164 kb
Host smart-b7a58b37-d9b6-4d80-89e5-1b30cf39077c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3526932836 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all_with_rand_reset.3526932836
Directory /workspace/3.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.3494892204
Short name T430
Test name
Test status
Simulation time 30050215 ps
CPU time 2.51 seconds
Started Mar 24 01:50:33 PM PDT 24
Finished Mar 24 01:50:36 PM PDT 24
Peak memory 208380 kb
Host smart-3959067e-9cfd-41fe-b2b6-11755e554b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3494892204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.3494892204
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.885404864
Short name T905
Test name
Test status
Simulation time 6693952636 ps
CPU time 58.28 seconds
Started Mar 24 01:50:37 PM PDT 24
Finished Mar 24 01:51:36 PM PDT 24
Peak memory 212084 kb
Host smart-9808bdd3-6946-4c5d-8679-338e9417ede1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=885404864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.885404864
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.3610534766
Short name T650
Test name
Test status
Simulation time 13999414 ps
CPU time 0.86 seconds
Started Mar 24 01:53:14 PM PDT 24
Finished Mar 24 01:53:15 PM PDT 24
Peak memory 206432 kb
Host smart-e6f0e0d8-6e04-42e1-a69f-697a7b298dd8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3610534766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.3610534766
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.935559525
Short name T520
Test name
Test status
Simulation time 162813979 ps
CPU time 2.18 seconds
Started Mar 24 01:53:11 PM PDT 24
Finished Mar 24 01:53:13 PM PDT 24
Peak memory 208644 kb
Host smart-ba38d1f6-8160-48b3-97c3-86e8d394c777
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=935559525 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.935559525
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.3440359543
Short name T197
Test name
Test status
Simulation time 63132654 ps
CPU time 3.66 seconds
Started Mar 24 01:53:14 PM PDT 24
Finished Mar 24 01:53:18 PM PDT 24
Peak memory 222904 kb
Host smart-17b718c8-555e-4040-ad29-63ccd9354df4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3440359543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.3440359543
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.834263690
Short name T425
Test name
Test status
Simulation time 112875644 ps
CPU time 2.77 seconds
Started Mar 24 01:53:11 PM PDT 24
Finished Mar 24 01:53:14 PM PDT 24
Peak memory 208316 kb
Host smart-13600d69-37be-4127-9a33-ba15051750eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=834263690 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.834263690
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.1579289815
Short name T527
Test name
Test status
Simulation time 833129177 ps
CPU time 7.87 seconds
Started Mar 24 01:53:10 PM PDT 24
Finished Mar 24 01:53:19 PM PDT 24
Peak memory 209108 kb
Host smart-cfdc7349-b109-4b30-aa89-a72cf2d9450d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1579289815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.1579289815
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.2945076945
Short name T764
Test name
Test status
Simulation time 63831830 ps
CPU time 3.13 seconds
Started Mar 24 01:53:11 PM PDT 24
Finished Mar 24 01:53:15 PM PDT 24
Peak memory 208972 kb
Host smart-76073414-a7ae-42b1-974c-9050edb1e7a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945076945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.2945076945
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.1867034271
Short name T571
Test name
Test status
Simulation time 411916810 ps
CPU time 8.78 seconds
Started Mar 24 01:53:09 PM PDT 24
Finished Mar 24 01:53:19 PM PDT 24
Peak memory 209144 kb
Host smart-d7aead8b-834b-4370-b215-eac3aa09d99a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1867034271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.1867034271
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.3829216816
Short name T717
Test name
Test status
Simulation time 241882132 ps
CPU time 3.08 seconds
Started Mar 24 01:53:11 PM PDT 24
Finished Mar 24 01:53:15 PM PDT 24
Peak memory 207112 kb
Host smart-f66efe82-73bd-474e-ac78-7b8f2534181e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829216816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.3829216816
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.2526796477
Short name T811
Test name
Test status
Simulation time 774831251 ps
CPU time 17.71 seconds
Started Mar 24 01:53:10 PM PDT 24
Finished Mar 24 01:53:28 PM PDT 24
Peak memory 208692 kb
Host smart-f1e63f0c-d86b-41f5-908e-a4822f9d261f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2526796477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.2526796477
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.3613025544
Short name T71
Test name
Test status
Simulation time 356775869 ps
CPU time 3.55 seconds
Started Mar 24 01:53:14 PM PDT 24
Finished Mar 24 01:53:18 PM PDT 24
Peak memory 210256 kb
Host smart-7fde085c-3ce1-4372-9002-6fbfbbcdd3c3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3613025544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.3613025544
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.2217754843
Short name T642
Test name
Test status
Simulation time 103713702 ps
CPU time 2.73 seconds
Started Mar 24 01:53:11 PM PDT 24
Finished Mar 24 01:53:14 PM PDT 24
Peak memory 208656 kb
Host smart-faa2665d-ade2-458a-a410-4800917e0f25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2217754843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.2217754843
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.195594535
Short name T335
Test name
Test status
Simulation time 501860026 ps
CPU time 7.52 seconds
Started Mar 24 01:53:15 PM PDT 24
Finished Mar 24 01:53:23 PM PDT 24
Peak memory 216380 kb
Host smart-7e9bc8cd-0c01-462f-9437-adb880749bf4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=195594535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.195594535
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.4021819691
Short name T602
Test name
Test status
Simulation time 920534959 ps
CPU time 4.73 seconds
Started Mar 24 01:53:13 PM PDT 24
Finished Mar 24 01:53:18 PM PDT 24
Peak memory 214772 kb
Host smart-1bfd953d-380b-4dff-b2ed-ff4be32e3a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4021819691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.4021819691
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.526861013
Short name T788
Test name
Test status
Simulation time 161306438 ps
CPU time 3.33 seconds
Started Mar 24 01:53:14 PM PDT 24
Finished Mar 24 01:53:18 PM PDT 24
Peak memory 210940 kb
Host smart-8b02dfed-a0dc-448a-b4b4-ff9971a21063
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526861013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.526861013
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.1164579314
Short name T506
Test name
Test status
Simulation time 22188738 ps
CPU time 0.91 seconds
Started Mar 24 01:53:25 PM PDT 24
Finished Mar 24 01:53:26 PM PDT 24
Peak memory 206340 kb
Host smart-3c6adcaa-906c-4375-ac28-1fbe931c1394
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164579314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.1164579314
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.3491576567
Short name T327
Test name
Test status
Simulation time 233538139 ps
CPU time 4.61 seconds
Started Mar 24 01:53:22 PM PDT 24
Finished Mar 24 01:53:27 PM PDT 24
Peak memory 215848 kb
Host smart-c9448a4f-cda4-4839-8783-6dc284c87cf6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3491576567 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.3491576567
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.3506324958
Short name T32
Test name
Test status
Simulation time 171589636 ps
CPU time 2.51 seconds
Started Mar 24 01:53:20 PM PDT 24
Finished Mar 24 01:53:23 PM PDT 24
Peak memory 215248 kb
Host smart-a61b99e3-f686-48dc-b810-ef5547f60066
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3506324958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.3506324958
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.1575945843
Short name T787
Test name
Test status
Simulation time 123799415 ps
CPU time 3.19 seconds
Started Mar 24 01:53:22 PM PDT 24
Finished Mar 24 01:53:25 PM PDT 24
Peak memory 209020 kb
Host smart-cf1357f5-ad3e-4333-8769-7a972a7f6edf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575945843 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.1575945843
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.381279790
Short name T33
Test name
Test status
Simulation time 401054846 ps
CPU time 19.34 seconds
Started Mar 24 01:53:23 PM PDT 24
Finished Mar 24 01:53:43 PM PDT 24
Peak memory 214816 kb
Host smart-f5915c89-a864-46c0-9340-0244e437b54b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=381279790 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.381279790
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.4028186393
Short name T595
Test name
Test status
Simulation time 204585415 ps
CPU time 3.7 seconds
Started Mar 24 01:53:21 PM PDT 24
Finished Mar 24 01:53:25 PM PDT 24
Peak memory 218980 kb
Host smart-50531854-20de-47ca-b8cc-1c64c2b18686
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4028186393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.4028186393
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.2160564760
Short name T265
Test name
Test status
Simulation time 108920861 ps
CPU time 3.68 seconds
Started Mar 24 01:53:14 PM PDT 24
Finished Mar 24 01:53:19 PM PDT 24
Peak memory 207180 kb
Host smart-d75d9844-3ed3-4065-898a-8cd9316843c4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160564760 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.2160564760
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.894764455
Short name T580
Test name
Test status
Simulation time 1431862305 ps
CPU time 20.29 seconds
Started Mar 24 01:53:19 PM PDT 24
Finished Mar 24 01:53:39 PM PDT 24
Peak memory 208340 kb
Host smart-c74ad20e-8480-4a27-bb4e-21ab8bf3ddc0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=894764455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.894764455
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.2487750777
Short name T474
Test name
Test status
Simulation time 140268150 ps
CPU time 3.27 seconds
Started Mar 24 01:53:19 PM PDT 24
Finished Mar 24 01:53:22 PM PDT 24
Peak memory 209108 kb
Host smart-b82197ef-f2bc-4078-823e-aeeb6a82548e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2487750777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.2487750777
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.629190981
Short name T689
Test name
Test status
Simulation time 89206947 ps
CPU time 1.92 seconds
Started Mar 24 01:53:13 PM PDT 24
Finished Mar 24 01:53:15 PM PDT 24
Peak memory 207172 kb
Host smart-28d78c15-5601-432b-bdf9-b0ebe60f0362
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=629190981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.629190981
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.1688733920
Short name T545
Test name
Test status
Simulation time 114132577 ps
CPU time 3.37 seconds
Started Mar 24 01:53:21 PM PDT 24
Finished Mar 24 01:53:25 PM PDT 24
Peak memory 209316 kb
Host smart-16a5f5d4-cafa-4390-9f55-6e59f843e0b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1688733920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.1688733920
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.3029785871
Short name T651
Test name
Test status
Simulation time 496490383 ps
CPU time 4.08 seconds
Started Mar 24 01:53:17 PM PDT 24
Finished Mar 24 01:53:22 PM PDT 24
Peak memory 207016 kb
Host smart-17080b9c-01c7-477d-9cb1-d96c64d8f342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029785871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.3029785871
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.1338519282
Short name T730
Test name
Test status
Simulation time 34864727 ps
CPU time 2.57 seconds
Started Mar 24 01:53:23 PM PDT 24
Finished Mar 24 01:53:26 PM PDT 24
Peak memory 209752 kb
Host smart-040660a6-b082-4a77-93a9-5460716a8ee3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1338519282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.1338519282
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.1582655372
Short name T151
Test name
Test status
Simulation time 36988990 ps
CPU time 1.55 seconds
Started Mar 24 01:53:21 PM PDT 24
Finished Mar 24 01:53:23 PM PDT 24
Peak memory 210412 kb
Host smart-96805b7a-f946-48c6-8e35-2400e3eee9ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1582655372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.1582655372
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.1966629248
Short name T17
Test name
Test status
Simulation time 12388316 ps
CPU time 0.79 seconds
Started Mar 24 01:53:28 PM PDT 24
Finished Mar 24 01:53:29 PM PDT 24
Peak memory 206344 kb
Host smart-ce54c04e-329f-46d8-8df6-6c752714e0f6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966629248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.1966629248
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.2588709119
Short name T383
Test name
Test status
Simulation time 594700416 ps
CPU time 7.84 seconds
Started Mar 24 01:53:21 PM PDT 24
Finished Mar 24 01:53:29 PM PDT 24
Peak memory 214764 kb
Host smart-9c387114-e04f-4feb-8ce1-a80753987281
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2588709119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.2588709119
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_custom_cm.4128788279
Short name T463
Test name
Test status
Simulation time 170232900 ps
CPU time 4.52 seconds
Started Mar 24 01:53:23 PM PDT 24
Finished Mar 24 01:53:28 PM PDT 24
Peak memory 209932 kb
Host smart-03c5672b-8a1f-42b7-a401-ecda8f58813c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4128788279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_custom_cm.4128788279
Directory /workspace/32.keymgr_custom_cm/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.2196809522
Short name T492
Test name
Test status
Simulation time 574810700 ps
CPU time 4.5 seconds
Started Mar 24 01:53:21 PM PDT 24
Finished Mar 24 01:53:26 PM PDT 24
Peak memory 208972 kb
Host smart-7c2e0ec6-ea61-4383-8806-6a75456bf21b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196809522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.2196809522
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.3048280640
Short name T790
Test name
Test status
Simulation time 1154936696 ps
CPU time 8.13 seconds
Started Mar 24 01:53:22 PM PDT 24
Finished Mar 24 01:53:30 PM PDT 24
Peak memory 221884 kb
Host smart-114d213c-a20b-45a7-82be-1557a1c9f2f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3048280640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.3048280640
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.107156467
Short name T442
Test name
Test status
Simulation time 279725909 ps
CPU time 3.64 seconds
Started Mar 24 01:53:22 PM PDT 24
Finished Mar 24 01:53:25 PM PDT 24
Peak memory 210224 kb
Host smart-e1200545-4c46-4db4-8a0b-67cf22389324
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=107156467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.107156467
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.517486885
Short name T309
Test name
Test status
Simulation time 441420613 ps
CPU time 2.97 seconds
Started Mar 24 01:53:20 PM PDT 24
Finished Mar 24 01:53:23 PM PDT 24
Peak memory 208560 kb
Host smart-e09b311f-c9f4-4a2c-a4d2-5de350401ad3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=517486885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.517486885
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.3744305886
Short name T848
Test name
Test status
Simulation time 111233793 ps
CPU time 2.85 seconds
Started Mar 24 01:53:21 PM PDT 24
Finished Mar 24 01:53:24 PM PDT 24
Peak memory 208904 kb
Host smart-6833ea6c-e4a1-4cd7-ba72-b5ff653a7d0f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744305886 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.3744305886
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.768386810
Short name T859
Test name
Test status
Simulation time 138718866 ps
CPU time 4.24 seconds
Started Mar 24 01:53:24 PM PDT 24
Finished Mar 24 01:53:29 PM PDT 24
Peak memory 208968 kb
Host smart-91ce27ca-2a11-4834-a118-0b1600aef3aa
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768386810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.768386810
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.3544825641
Short name T461
Test name
Test status
Simulation time 142192631 ps
CPU time 2.58 seconds
Started Mar 24 01:53:22 PM PDT 24
Finished Mar 24 01:53:25 PM PDT 24
Peak memory 207212 kb
Host smart-d2a89404-4849-4069-8f2e-d39de51d1f4b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3544825641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.3544825641
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.1620966432
Short name T177
Test name
Test status
Simulation time 200319480 ps
CPU time 7.07 seconds
Started Mar 24 01:53:20 PM PDT 24
Finished Mar 24 01:53:27 PM PDT 24
Peak memory 208400 kb
Host smart-198a7f84-9442-438f-8af8-7aafd078fc6f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620966432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.1620966432
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.392506579
Short name T709
Test name
Test status
Simulation time 123612250 ps
CPU time 3.61 seconds
Started Mar 24 01:53:25 PM PDT 24
Finished Mar 24 01:53:28 PM PDT 24
Peak memory 216184 kb
Host smart-c1b7c26f-874b-4dd9-b7de-46ef430ae3f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392506579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.392506579
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.3964374763
Short name T498
Test name
Test status
Simulation time 673098520 ps
CPU time 2.4 seconds
Started Mar 24 01:53:20 PM PDT 24
Finished Mar 24 01:53:23 PM PDT 24
Peak memory 208320 kb
Host smart-5ee1a63b-ebdf-48ef-826a-458013cf9f37
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3964374763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.3964374763
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.150113880
Short name T457
Test name
Test status
Simulation time 84727962 ps
CPU time 4.15 seconds
Started Mar 24 01:53:21 PM PDT 24
Finished Mar 24 01:53:25 PM PDT 24
Peak memory 208376 kb
Host smart-6034e3a8-9e6e-4741-8465-b91c05779dcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=150113880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.150113880
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.3737280520
Short name T51
Test name
Test status
Simulation time 77665183 ps
CPU time 3.06 seconds
Started Mar 24 01:53:26 PM PDT 24
Finished Mar 24 01:53:29 PM PDT 24
Peak memory 210528 kb
Host smart-461728ac-9658-4acf-970c-aa7521295599
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3737280520 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.3737280520
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.4103798512
Short name T635
Test name
Test status
Simulation time 15668286 ps
CPU time 0.76 seconds
Started Mar 24 01:53:26 PM PDT 24
Finished Mar 24 01:53:27 PM PDT 24
Peak memory 206436 kb
Host smart-a119888a-b90c-455b-8384-93bb695f93bd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4103798512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.4103798512
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.1121234985
Short name T627
Test name
Test status
Simulation time 72487747 ps
CPU time 1.81 seconds
Started Mar 24 01:53:26 PM PDT 24
Finished Mar 24 01:53:28 PM PDT 24
Peak memory 210400 kb
Host smart-1c023fdf-240f-4ce5-a188-25adeedbadde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121234985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.1121234985
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.3684743306
Short name T469
Test name
Test status
Simulation time 166474507 ps
CPU time 4.13 seconds
Started Mar 24 01:53:24 PM PDT 24
Finished Mar 24 01:53:29 PM PDT 24
Peak memory 221336 kb
Host smart-768128c6-ce67-40e5-a8e8-aeb153bb0b7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3684743306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.3684743306
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.2581248242
Short name T260
Test name
Test status
Simulation time 184562753 ps
CPU time 6.06 seconds
Started Mar 24 01:53:28 PM PDT 24
Finished Mar 24 01:53:34 PM PDT 24
Peak memory 214760 kb
Host smart-74f91e60-a1c1-4e5f-ad87-523c7d72aeca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581248242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.2581248242
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_random.3035920354
Short name T344
Test name
Test status
Simulation time 704293027 ps
CPU time 6.46 seconds
Started Mar 24 01:53:28 PM PDT 24
Finished Mar 24 01:53:35 PM PDT 24
Peak memory 207632 kb
Host smart-ccdfeb39-20da-47d0-9c51-fd31d1a28930
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3035920354 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.3035920354
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.2512722779
Short name T798
Test name
Test status
Simulation time 3263752242 ps
CPU time 22.95 seconds
Started Mar 24 01:53:25 PM PDT 24
Finished Mar 24 01:53:48 PM PDT 24
Peak memory 209416 kb
Host smart-2fa666d6-b5f2-4c1a-8144-4ec55cfae9a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2512722779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.2512722779
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.1512693667
Short name T622
Test name
Test status
Simulation time 222242446 ps
CPU time 5.6 seconds
Started Mar 24 01:53:25 PM PDT 24
Finished Mar 24 01:53:31 PM PDT 24
Peak memory 209044 kb
Host smart-6db6c562-f234-4789-980c-31c746793183
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1512693667 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.1512693667
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.298430686
Short name T253
Test name
Test status
Simulation time 119397316 ps
CPU time 4.78 seconds
Started Mar 24 01:53:25 PM PDT 24
Finished Mar 24 01:53:30 PM PDT 24
Peak memory 207280 kb
Host smart-9b958662-7dc8-45b4-923f-61170bae04aa
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=298430686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.298430686
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.2242436727
Short name T254
Test name
Test status
Simulation time 100886981 ps
CPU time 2.96 seconds
Started Mar 24 01:53:28 PM PDT 24
Finished Mar 24 01:53:31 PM PDT 24
Peak memory 207328 kb
Host smart-ad9b896d-e530-433a-ba3b-4b512da2f6da
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2242436727 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.2242436727
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.399811448
Short name T439
Test name
Test status
Simulation time 77195636 ps
CPU time 2.34 seconds
Started Mar 24 01:53:26 PM PDT 24
Finished Mar 24 01:53:29 PM PDT 24
Peak memory 207388 kb
Host smart-c2768181-560c-49cc-a092-00607da6cf87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=399811448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.399811448
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.2184348387
Short name T581
Test name
Test status
Simulation time 261319190 ps
CPU time 3.37 seconds
Started Mar 24 01:53:26 PM PDT 24
Finished Mar 24 01:53:30 PM PDT 24
Peak memory 208728 kb
Host smart-399f48b6-6e89-4f85-902d-7db6672ef779
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2184348387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.2184348387
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.3954981273
Short name T124
Test name
Test status
Simulation time 109295218 ps
CPU time 3.46 seconds
Started Mar 24 01:53:23 PM PDT 24
Finished Mar 24 01:53:27 PM PDT 24
Peak memory 208220 kb
Host smart-e3d5b3d0-b1eb-4bb7-9016-a135f54bd96c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954981273 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.3954981273
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.2349706254
Short name T690
Test name
Test status
Simulation time 83813409 ps
CPU time 1.92 seconds
Started Mar 24 01:53:26 PM PDT 24
Finished Mar 24 01:53:28 PM PDT 24
Peak memory 210388 kb
Host smart-2b1b7c88-bbf4-4963-9010-829da1277dde
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2349706254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.2349706254
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.750674931
Short name T490
Test name
Test status
Simulation time 16329446 ps
CPU time 0.81 seconds
Started Mar 24 01:53:29 PM PDT 24
Finished Mar 24 01:53:30 PM PDT 24
Peak memory 206436 kb
Host smart-f73e2167-41eb-4fde-9bdd-1ec63941adc7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750674931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.750674931
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.113927534
Short name T865
Test name
Test status
Simulation time 47133431 ps
CPU time 3.4 seconds
Started Mar 24 01:53:26 PM PDT 24
Finished Mar 24 01:53:30 PM PDT 24
Peak memory 214864 kb
Host smart-89786d89-4c5c-4d76-95be-ed23d8741358
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=113927534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.113927534
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.1101794831
Short name T313
Test name
Test status
Simulation time 182813272 ps
CPU time 4.32 seconds
Started Mar 24 01:53:28 PM PDT 24
Finished Mar 24 01:53:33 PM PDT 24
Peak memory 210292 kb
Host smart-31916c94-4125-4908-925a-a860d3b85de0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1101794831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.1101794831
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.1308170109
Short name T907
Test name
Test status
Simulation time 437684122 ps
CPU time 5.17 seconds
Started Mar 24 01:53:33 PM PDT 24
Finished Mar 24 01:53:39 PM PDT 24
Peak memory 210136 kb
Host smart-374e9802-1516-4e42-a2ce-43c776a2c38f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1308170109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.1308170109
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.1457373094
Short name T286
Test name
Test status
Simulation time 567917863 ps
CPU time 7.13 seconds
Started Mar 24 01:53:30 PM PDT 24
Finished Mar 24 01:53:37 PM PDT 24
Peak memory 222824 kb
Host smart-185336f0-b868-41ac-a4f3-b96777afbe70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1457373094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.1457373094
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.1072241624
Short name T525
Test name
Test status
Simulation time 204835010 ps
CPU time 3.63 seconds
Started Mar 24 01:53:30 PM PDT 24
Finished Mar 24 01:53:33 PM PDT 24
Peak memory 215724 kb
Host smart-7a998724-fcfc-428c-8597-57cd030b938f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1072241624 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.1072241624
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.645816066
Short name T845
Test name
Test status
Simulation time 383065900 ps
CPU time 8.17 seconds
Started Mar 24 01:53:26 PM PDT 24
Finished Mar 24 01:53:34 PM PDT 24
Peak memory 208320 kb
Host smart-5fa257d9-34a7-42ae-b2ad-f7ce647480c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645816066 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.645816066
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.4138982264
Short name T500
Test name
Test status
Simulation time 3062282196 ps
CPU time 31.57 seconds
Started Mar 24 01:53:26 PM PDT 24
Finished Mar 24 01:53:57 PM PDT 24
Peak memory 209052 kb
Host smart-ee6e22ee-233b-42e1-8296-b04aa5fa41b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138982264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.4138982264
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.4251024387
Short name T345
Test name
Test status
Simulation time 57014524 ps
CPU time 3.19 seconds
Started Mar 24 01:53:24 PM PDT 24
Finished Mar 24 01:53:28 PM PDT 24
Peak memory 208420 kb
Host smart-08d49181-d05f-47e1-b465-5cb9dbac5e4c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4251024387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.4251024387
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.2251232897
Short name T841
Test name
Test status
Simulation time 83773706 ps
CPU time 1.78 seconds
Started Mar 24 01:53:25 PM PDT 24
Finished Mar 24 01:53:27 PM PDT 24
Peak memory 207116 kb
Host smart-186d0bd6-8ef3-464f-b4be-67f72d9be63d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2251232897 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.2251232897
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.1622850433
Short name T317
Test name
Test status
Simulation time 221194357 ps
CPU time 6.69 seconds
Started Mar 24 01:53:23 PM PDT 24
Finished Mar 24 01:53:31 PM PDT 24
Peak memory 208928 kb
Host smart-269c84ef-db99-45aa-bab6-20294d5f7d70
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622850433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.1622850433
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.3116460103
Short name T678
Test name
Test status
Simulation time 198597006 ps
CPU time 1.92 seconds
Started Mar 24 01:53:33 PM PDT 24
Finished Mar 24 01:53:35 PM PDT 24
Peak memory 215828 kb
Host smart-028a5e6c-decf-4bc6-afa4-3a3e25e8b6fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116460103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.3116460103
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.1491873084
Short name T685
Test name
Test status
Simulation time 67924302 ps
CPU time 3.01 seconds
Started Mar 24 01:53:24 PM PDT 24
Finished Mar 24 01:53:28 PM PDT 24
Peak memory 208872 kb
Host smart-c29802b6-f3e9-4b13-9de9-63c4a7608f17
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1491873084 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.1491873084
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.524577643
Short name T64
Test name
Test status
Simulation time 441347346 ps
CPU time 21.96 seconds
Started Mar 24 01:53:30 PM PDT 24
Finished Mar 24 01:53:52 PM PDT 24
Peak memory 222968 kb
Host smart-e24f4390-b8e3-456c-903f-e8b44f928162
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=524577643 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.524577643
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_stress_all_with_rand_reset.591985224
Short name T174
Test name
Test status
Simulation time 295032350 ps
CPU time 11.16 seconds
Started Mar 24 01:53:33 PM PDT 24
Finished Mar 24 01:53:44 PM PDT 24
Peak memory 220844 kb
Host smart-87d3897f-f68e-48e7-a541-08da31b63290
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=591985224 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all_with_rand_reset.591985224
Directory /workspace/34.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.769619194
Short name T516
Test name
Test status
Simulation time 76297881 ps
CPU time 3.84 seconds
Started Mar 24 01:53:29 PM PDT 24
Finished Mar 24 01:53:33 PM PDT 24
Peak memory 214648 kb
Host smart-db1ae1be-3f09-47c8-86fc-77d068bf9852
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=769619194 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.769619194
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.3955785556
Short name T897
Test name
Test status
Simulation time 162340170 ps
CPU time 2.17 seconds
Started Mar 24 01:53:29 PM PDT 24
Finished Mar 24 01:53:31 PM PDT 24
Peak memory 210292 kb
Host smart-fdf3c26c-5f98-45f1-bc14-725b49b58b91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3955785556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.3955785556
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.4126859792
Short name T123
Test name
Test status
Simulation time 35682912 ps
CPU time 0.72 seconds
Started Mar 24 01:53:37 PM PDT 24
Finished Mar 24 01:53:38 PM PDT 24
Peak memory 206444 kb
Host smart-df47e4c7-f19e-4012-8ed9-e1db5c5d56c4
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4126859792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.4126859792
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.4055541516
Short name T27
Test name
Test status
Simulation time 545712623 ps
CPU time 3.52 seconds
Started Mar 24 01:53:36 PM PDT 24
Finished Mar 24 01:53:39 PM PDT 24
Peak memory 210572 kb
Host smart-8596df9c-df43-4fa7-8085-cd35c035f314
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055541516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.4055541516
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.291365548
Short name T477
Test name
Test status
Simulation time 123684290 ps
CPU time 4.35 seconds
Started Mar 24 01:53:29 PM PDT 24
Finished Mar 24 01:53:33 PM PDT 24
Peak memory 209100 kb
Host smart-72f42a85-648e-489f-981a-8ed7008de450
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291365548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.291365548
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.1714773637
Short name T468
Test name
Test status
Simulation time 357286003 ps
CPU time 4.56 seconds
Started Mar 24 01:53:34 PM PDT 24
Finished Mar 24 01:53:39 PM PDT 24
Peak memory 221832 kb
Host smart-92039779-88af-40d5-8eaa-9da006bcfa72
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1714773637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.1714773637
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.818920798
Short name T201
Test name
Test status
Simulation time 833667305 ps
CPU time 7.45 seconds
Started Mar 24 01:53:37 PM PDT 24
Finished Mar 24 01:53:45 PM PDT 24
Peak memory 212548 kb
Host smart-a260563b-14df-4259-b0cb-36f5f68a0c62
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=818920798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.818920798
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.3770321133
Short name T464
Test name
Test status
Simulation time 635001711 ps
CPU time 3.46 seconds
Started Mar 24 01:53:36 PM PDT 24
Finished Mar 24 01:53:40 PM PDT 24
Peak memory 215548 kb
Host smart-1f5fd21b-4e4e-43af-a1a1-cdf4f65f85c8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3770321133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.3770321133
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.407988324
Short name T256
Test name
Test status
Simulation time 3007732562 ps
CPU time 39.32 seconds
Started Mar 24 01:53:31 PM PDT 24
Finished Mar 24 01:54:10 PM PDT 24
Peak memory 210060 kb
Host smart-ff0ca24b-30d3-4226-8b52-542d01dc24a8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=407988324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.407988324
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.2643480191
Short name T410
Test name
Test status
Simulation time 820262980 ps
CPU time 16.83 seconds
Started Mar 24 01:53:28 PM PDT 24
Finished Mar 24 01:53:45 PM PDT 24
Peak memory 208416 kb
Host smart-cd421103-82b6-4e1c-8b57-7035feb209af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2643480191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.2643480191
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.2610733140
Short name T893
Test name
Test status
Simulation time 183806770 ps
CPU time 4.9 seconds
Started Mar 24 01:53:31 PM PDT 24
Finished Mar 24 01:53:36 PM PDT 24
Peak memory 208176 kb
Host smart-b1ed3d3b-0140-48c8-9d76-327895e1cfb6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2610733140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.2610733140
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.2339538255
Short name T638
Test name
Test status
Simulation time 4338875433 ps
CPU time 7.48 seconds
Started Mar 24 01:53:29 PM PDT 24
Finished Mar 24 01:53:36 PM PDT 24
Peak memory 208612 kb
Host smart-bf98c156-58e6-4318-84ce-9533346063d0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2339538255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.2339538255
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.1054641944
Short name T432
Test name
Test status
Simulation time 26982475 ps
CPU time 1.88 seconds
Started Mar 24 01:53:28 PM PDT 24
Finished Mar 24 01:53:30 PM PDT 24
Peak memory 207456 kb
Host smart-00a99b70-4132-45bb-a19d-7069cf696b33
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1054641944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.1054641944
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.1029937335
Short name T229
Test name
Test status
Simulation time 28054619 ps
CPU time 1.96 seconds
Started Mar 24 01:53:37 PM PDT 24
Finished Mar 24 01:53:39 PM PDT 24
Peak memory 223000 kb
Host smart-e643e80d-c491-49ec-b749-7fa1baacc869
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1029937335 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.1029937335
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.1967294517
Short name T802
Test name
Test status
Simulation time 65703244 ps
CPU time 3.21 seconds
Started Mar 24 01:53:31 PM PDT 24
Finished Mar 24 01:53:35 PM PDT 24
Peak memory 207184 kb
Host smart-85199dd4-efbf-4cfa-b8d3-35be477d5366
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967294517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.1967294517
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.1280969187
Short name T750
Test name
Test status
Simulation time 1218769510 ps
CPU time 6.3 seconds
Started Mar 24 01:53:36 PM PDT 24
Finished Mar 24 01:53:43 PM PDT 24
Peak memory 209532 kb
Host smart-1d982e02-33b1-470b-9648-bfd705f13ba6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1280969187 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.1280969187
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_stress_all_with_rand_reset.3417268072
Short name T173
Test name
Test status
Simulation time 660936140 ps
CPU time 14.69 seconds
Started Mar 24 01:53:34 PM PDT 24
Finished Mar 24 01:53:49 PM PDT 24
Peak memory 223044 kb
Host smart-81b75dd6-d487-415d-99e5-8164352f0cc1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3417268072 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all_with_rand_reset.3417268072
Directory /workspace/35.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.2569889455
Short name T280
Test name
Test status
Simulation time 254074914 ps
CPU time 7.52 seconds
Started Mar 24 01:53:36 PM PDT 24
Finished Mar 24 01:53:44 PM PDT 24
Peak memory 219052 kb
Host smart-cfa92812-d620-4b0e-b023-7c4e7996ea88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2569889455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.2569889455
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.203112960
Short name T663
Test name
Test status
Simulation time 160560706 ps
CPU time 2.54 seconds
Started Mar 24 01:53:38 PM PDT 24
Finished Mar 24 01:53:41 PM PDT 24
Peak memory 210444 kb
Host smart-a1f179a5-62eb-4291-b12e-93ecb9b31dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=203112960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.203112960
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.478057590
Short name T471
Test name
Test status
Simulation time 14497546 ps
CPU time 0.78 seconds
Started Mar 24 01:53:40 PM PDT 24
Finished Mar 24 01:53:41 PM PDT 24
Peak memory 206364 kb
Host smart-7f8f2b86-a008-466b-a000-7cbebf84be14
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=478057590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.478057590
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.969440382
Short name T319
Test name
Test status
Simulation time 475386453 ps
CPU time 13.41 seconds
Started Mar 24 01:53:35 PM PDT 24
Finished Mar 24 01:53:48 PM PDT 24
Peak memory 216476 kb
Host smart-c947a2b0-02e3-4642-ac15-160df2b4df81
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=969440382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.969440382
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.2106702105
Short name T612
Test name
Test status
Simulation time 692068974 ps
CPU time 3.23 seconds
Started Mar 24 01:53:40 PM PDT 24
Finished Mar 24 01:53:43 PM PDT 24
Peak memory 221016 kb
Host smart-77643f03-64ed-4a92-be68-5f252a95e2ee
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2106702105 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.2106702105
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.3481745673
Short name T267
Test name
Test status
Simulation time 334173421 ps
CPU time 4.26 seconds
Started Mar 24 01:53:36 PM PDT 24
Finished Mar 24 01:53:41 PM PDT 24
Peak memory 214824 kb
Host smart-98fef9c6-87cc-4789-b507-987ad5edc55e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481745673 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.3481745673
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.1619530724
Short name T273
Test name
Test status
Simulation time 172339505 ps
CPU time 4.9 seconds
Started Mar 24 01:53:40 PM PDT 24
Finished Mar 24 01:53:45 PM PDT 24
Peak memory 214776 kb
Host smart-bb622703-01de-497b-8f78-766ea9a1b718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619530724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.1619530724
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.1233564180
Short name T222
Test name
Test status
Simulation time 590301740 ps
CPU time 3.84 seconds
Started Mar 24 01:53:37 PM PDT 24
Finished Mar 24 01:53:42 PM PDT 24
Peak memory 210124 kb
Host smart-0c758fdd-f0ed-4088-898d-ed5a455d353d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1233564180 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.1233564180
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.2044067751
Short name T739
Test name
Test status
Simulation time 1157675210 ps
CPU time 31.24 seconds
Started Mar 24 01:53:36 PM PDT 24
Finished Mar 24 01:54:07 PM PDT 24
Peak memory 214700 kb
Host smart-c2c7cff2-4b20-4e37-8462-8414bad6e33b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2044067751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.2044067751
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.3166851523
Short name T613
Test name
Test status
Simulation time 194296280 ps
CPU time 4.31 seconds
Started Mar 24 01:53:36 PM PDT 24
Finished Mar 24 01:53:41 PM PDT 24
Peak memory 209004 kb
Host smart-a751ed86-9ebe-4de8-8e1d-4930cdc46804
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3166851523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.3166851523
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.3652486870
Short name T423
Test name
Test status
Simulation time 7000038611 ps
CPU time 72.73 seconds
Started Mar 24 01:53:36 PM PDT 24
Finished Mar 24 01:54:49 PM PDT 24
Peak memory 208908 kb
Host smart-59e0b322-085c-4430-acbf-b96004deca9a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3652486870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.3652486870
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.2194446687
Short name T70
Test name
Test status
Simulation time 86143544 ps
CPU time 1.96 seconds
Started Mar 24 01:53:36 PM PDT 24
Finished Mar 24 01:53:38 PM PDT 24
Peak memory 207940 kb
Host smart-1af133bb-1e22-403d-bfa9-095099cd0158
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2194446687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.2194446687
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.173195968
Short name T404
Test name
Test status
Simulation time 2219511419 ps
CPU time 29.51 seconds
Started Mar 24 01:53:35 PM PDT 24
Finished Mar 24 01:54:05 PM PDT 24
Peak memory 208672 kb
Host smart-8a113f72-0657-4df1-b9d8-3a27267b5b24
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=173195968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.173195968
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.3321989014
Short name T433
Test name
Test status
Simulation time 288679513 ps
CPU time 3.37 seconds
Started Mar 24 01:53:41 PM PDT 24
Finished Mar 24 01:53:44 PM PDT 24
Peak memory 209652 kb
Host smart-1434f845-7542-4371-a19c-fd0a3fdee6cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3321989014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.3321989014
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.3335989395
Short name T396
Test name
Test status
Simulation time 124775207 ps
CPU time 2.26 seconds
Started Mar 24 01:53:38 PM PDT 24
Finished Mar 24 01:53:40 PM PDT 24
Peak memory 207708 kb
Host smart-8ef76fe8-8652-40c9-9348-0fda009fd056
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3335989395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.3335989395
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.3885938312
Short name T724
Test name
Test status
Simulation time 1066337426 ps
CPU time 5.79 seconds
Started Mar 24 01:53:35 PM PDT 24
Finished Mar 24 01:53:41 PM PDT 24
Peak memory 209984 kb
Host smart-a022de56-5d74-4e40-83e2-d8c24219b69f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3885938312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.3885938312
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.3973407504
Short name T609
Test name
Test status
Simulation time 101273563 ps
CPU time 1.25 seconds
Started Mar 24 01:53:42 PM PDT 24
Finished Mar 24 01:53:43 PM PDT 24
Peak memory 210164 kb
Host smart-f192a39c-3006-4a4c-997a-68f6779bf878
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973407504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.3973407504
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.588252282
Short name T844
Test name
Test status
Simulation time 16231204 ps
CPU time 0.76 seconds
Started Mar 24 01:53:45 PM PDT 24
Finished Mar 24 01:53:46 PM PDT 24
Peak memory 206380 kb
Host smart-762315b6-9250-4972-b981-0aee0a76e89b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=588252282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.588252282
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.395917021
Short name T412
Test name
Test status
Simulation time 15483692 ps
CPU time 1.54 seconds
Started Mar 24 01:53:42 PM PDT 24
Finished Mar 24 01:53:44 PM PDT 24
Peak memory 208192 kb
Host smart-c2076085-6a6b-48c3-90e9-99d90d823b76
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=395917021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.395917021
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.1333726166
Short name T355
Test name
Test status
Simulation time 171752842 ps
CPU time 2.83 seconds
Started Mar 24 01:53:40 PM PDT 24
Finished Mar 24 01:53:42 PM PDT 24
Peak memory 221248 kb
Host smart-a6ba0534-48f3-4ab8-b380-80705d0ea885
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1333726166 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.1333726166
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.1388675219
Short name T337
Test name
Test status
Simulation time 117082929 ps
CPU time 4.96 seconds
Started Mar 24 01:53:43 PM PDT 24
Finished Mar 24 01:53:48 PM PDT 24
Peak memory 212348 kb
Host smart-37f70029-f024-4bd6-b91d-a7e7ded102bb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1388675219 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.1388675219
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.233281209
Short name T782
Test name
Test status
Simulation time 127255079 ps
CPU time 3.51 seconds
Started Mar 24 01:53:42 PM PDT 24
Finished Mar 24 01:53:46 PM PDT 24
Peak memory 218728 kb
Host smart-9c118ae7-e78c-4280-8fc9-cfac2e54b85d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=233281209 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.233281209
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.2398403695
Short name T729
Test name
Test status
Simulation time 391837214 ps
CPU time 3.99 seconds
Started Mar 24 01:53:40 PM PDT 24
Finished Mar 24 01:53:44 PM PDT 24
Peak memory 209260 kb
Host smart-0b470b7d-3e81-4ed6-b502-e5cb210d51c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2398403695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.2398403695
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.262389532
Short name T860
Test name
Test status
Simulation time 205895026 ps
CPU time 2.85 seconds
Started Mar 24 01:53:43 PM PDT 24
Finished Mar 24 01:53:46 PM PDT 24
Peak memory 207172 kb
Host smart-33c22c69-d283-4a76-8e9c-432de68ed6a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=262389532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.262389532
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.3477340070
Short name T583
Test name
Test status
Simulation time 8199392867 ps
CPU time 18.86 seconds
Started Mar 24 01:53:41 PM PDT 24
Finished Mar 24 01:53:59 PM PDT 24
Peak memory 208412 kb
Host smart-b9e9fe3a-4cb3-4d0d-afe5-2c6fc1ddd8c9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477340070 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.3477340070
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.1176816052
Short name T772
Test name
Test status
Simulation time 116277216 ps
CPU time 3.27 seconds
Started Mar 24 01:53:40 PM PDT 24
Finished Mar 24 01:53:44 PM PDT 24
Peak memory 207344 kb
Host smart-205a1c83-03cc-4450-89f0-126c178b51f6
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176816052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.1176816052
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.123433068
Short name T832
Test name
Test status
Simulation time 914526983 ps
CPU time 24.13 seconds
Started Mar 24 01:53:43 PM PDT 24
Finished Mar 24 01:54:07 PM PDT 24
Peak memory 209208 kb
Host smart-1559de92-61fa-42fd-92bc-4b7bc0c2ae68
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=123433068 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.123433068
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.702196893
Short name T800
Test name
Test status
Simulation time 192547680 ps
CPU time 2.57 seconds
Started Mar 24 01:53:44 PM PDT 24
Finished Mar 24 01:53:47 PM PDT 24
Peak memory 210068 kb
Host smart-210e8ce7-e809-4676-b085-7272e007aa7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702196893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.702196893
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/37.keymgr_smoke.1498340795
Short name T491
Test name
Test status
Simulation time 429751971 ps
CPU time 5.68 seconds
Started Mar 24 01:53:39 PM PDT 24
Finished Mar 24 01:53:44 PM PDT 24
Peak memory 207172 kb
Host smart-bacddf03-2529-4560-8cec-3d18b8b77a67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498340795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.1498340795
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.2325629887
Short name T188
Test name
Test status
Simulation time 7033805396 ps
CPU time 38.02 seconds
Started Mar 24 01:53:46 PM PDT 24
Finished Mar 24 01:54:24 PM PDT 24
Peak memory 216016 kb
Host smart-f0546044-51cf-4945-ba11-bd1c88c9864a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2325629887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.2325629887
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.3865664349
Short name T418
Test name
Test status
Simulation time 3836062720 ps
CPU time 22.57 seconds
Started Mar 24 01:53:41 PM PDT 24
Finished Mar 24 01:54:04 PM PDT 24
Peak memory 210860 kb
Host smart-a199164c-bf1b-4c37-b3a6-f32e51162ab5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3865664349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.3865664349
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.678637506
Short name T834
Test name
Test status
Simulation time 437505066 ps
CPU time 9.83 seconds
Started Mar 24 01:53:45 PM PDT 24
Finished Mar 24 01:53:55 PM PDT 24
Peak memory 211340 kb
Host smart-622fe804-e0e1-4f7a-a6a0-1f799c95ddcf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=678637506 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.678637506
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.1173232417
Short name T666
Test name
Test status
Simulation time 40523681 ps
CPU time 0.76 seconds
Started Mar 24 01:53:51 PM PDT 24
Finished Mar 24 01:53:52 PM PDT 24
Peak memory 206460 kb
Host smart-e4206372-efb9-4985-aea0-66482cfbd0b7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1173232417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.1173232417
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.679549413
Short name T392
Test name
Test status
Simulation time 38571248 ps
CPU time 3.03 seconds
Started Mar 24 01:53:51 PM PDT 24
Finished Mar 24 01:53:54 PM PDT 24
Peak memory 214828 kb
Host smart-e6b0e120-a1db-4326-8458-7393733afc7b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=679549413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.679549413
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.33407216
Short name T877
Test name
Test status
Simulation time 296207530 ps
CPU time 5.27 seconds
Started Mar 24 01:53:51 PM PDT 24
Finished Mar 24 01:53:56 PM PDT 24
Peak memory 221700 kb
Host smart-ceda2685-1cf0-4132-b324-86b334198e44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=33407216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.33407216
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.3747445720
Short name T710
Test name
Test status
Simulation time 83481017 ps
CPU time 3.07 seconds
Started Mar 24 01:53:45 PM PDT 24
Finished Mar 24 01:53:48 PM PDT 24
Peak memory 208036 kb
Host smart-52439f60-44a1-4f35-b9ad-b295957af7fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747445720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.3747445720
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.2291654472
Short name T205
Test name
Test status
Simulation time 247121689 ps
CPU time 2.86 seconds
Started Mar 24 01:53:49 PM PDT 24
Finished Mar 24 01:53:52 PM PDT 24
Peak memory 214784 kb
Host smart-cc772d90-24f8-453f-b246-18beb0ca466f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2291654472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.2291654472
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.725284784
Short name T424
Test name
Test status
Simulation time 135260672 ps
CPU time 5.81 seconds
Started Mar 24 01:53:49 PM PDT 24
Finished Mar 24 01:53:55 PM PDT 24
Peak memory 207656 kb
Host smart-5fd0ad4e-c09d-4d5f-a11a-40453568e79e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725284784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.725284784
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.2014311244
Short name T290
Test name
Test status
Simulation time 2319670550 ps
CPU time 4.35 seconds
Started Mar 24 01:53:45 PM PDT 24
Finished Mar 24 01:53:49 PM PDT 24
Peak memory 209132 kb
Host smart-5078cce8-7a1c-417a-a5f1-8bc9d48006c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2014311244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.2014311244
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.954048583
Short name T677
Test name
Test status
Simulation time 10409137964 ps
CPU time 34.31 seconds
Started Mar 24 01:53:45 PM PDT 24
Finished Mar 24 01:54:20 PM PDT 24
Peak memory 208640 kb
Host smart-578df8f4-1f9b-42ab-a080-79bbf20040b6
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954048583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.954048583
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.1213559707
Short name T408
Test name
Test status
Simulation time 38322674 ps
CPU time 2.4 seconds
Started Mar 24 01:53:46 PM PDT 24
Finished Mar 24 01:53:48 PM PDT 24
Peak memory 207336 kb
Host smart-19d06b4c-59da-483f-bb44-b56a9cd032ff
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1213559707 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.1213559707
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.516277019
Short name T614
Test name
Test status
Simulation time 147625358 ps
CPU time 2.73 seconds
Started Mar 24 01:53:46 PM PDT 24
Finished Mar 24 01:53:49 PM PDT 24
Peak memory 208960 kb
Host smart-9301451b-cf7b-44d8-a68d-2d693eab05b7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=516277019 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.516277019
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.718546045
Short name T96
Test name
Test status
Simulation time 19632355 ps
CPU time 1.67 seconds
Started Mar 24 01:53:51 PM PDT 24
Finished Mar 24 01:53:53 PM PDT 24
Peak memory 207980 kb
Host smart-334caf6e-9544-434b-845e-99e078854112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=718546045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.718546045
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.3540684895
Short name T824
Test name
Test status
Simulation time 99790882 ps
CPU time 3.61 seconds
Started Mar 24 01:53:44 PM PDT 24
Finished Mar 24 01:53:48 PM PDT 24
Peak memory 208992 kb
Host smart-deaf2dcb-204a-4962-b31c-44ed4e76492e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3540684895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.3540684895
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.433084111
Short name T190
Test name
Test status
Simulation time 3005666282 ps
CPU time 18.05 seconds
Started Mar 24 01:53:50 PM PDT 24
Finished Mar 24 01:54:08 PM PDT 24
Peak memory 217784 kb
Host smart-294bbc1d-f1c5-4a76-8ede-6ddb06775762
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433084111 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.433084111
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/38.keymgr_stress_all_with_rand_reset.2029941347
Short name T111
Test name
Test status
Simulation time 251112751 ps
CPU time 8.07 seconds
Started Mar 24 01:53:57 PM PDT 24
Finished Mar 24 01:54:05 PM PDT 24
Peak memory 223060 kb
Host smart-2504230c-4d15-44ba-a3a7-2ec5f6e809c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2029941347 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all_with_rand_reset.2029941347
Directory /workspace/38.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.2546931678
Short name T610
Test name
Test status
Simulation time 391569990 ps
CPU time 5.93 seconds
Started Mar 24 01:53:45 PM PDT 24
Finished Mar 24 01:53:51 PM PDT 24
Peak memory 209544 kb
Host smart-7e9310e4-57dd-44fa-afb2-d9bddd232b2c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2546931678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.2546931678
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.3081832146
Short name T125
Test name
Test status
Simulation time 94264052 ps
CPU time 3.73 seconds
Started Mar 24 01:53:51 PM PDT 24
Finished Mar 24 01:53:55 PM PDT 24
Peak memory 210324 kb
Host smart-ae2ee398-654d-42bd-bd34-53ee0246c70d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3081832146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.3081832146
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.2009965806
Short name T121
Test name
Test status
Simulation time 38679957 ps
CPU time 0.72 seconds
Started Mar 24 01:53:54 PM PDT 24
Finished Mar 24 01:53:54 PM PDT 24
Peak memory 206372 kb
Host smart-e89e9ee5-a19b-4b49-b2b7-a934ea2ed517
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2009965806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.2009965806
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.3196390816
Short name T674
Test name
Test status
Simulation time 330299496 ps
CPU time 4.83 seconds
Started Mar 24 01:53:51 PM PDT 24
Finished Mar 24 01:53:56 PM PDT 24
Peak memory 211700 kb
Host smart-8edc91c3-118b-4135-9df8-a10236ea6e7d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3196390816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.3196390816
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.1011176450
Short name T619
Test name
Test status
Simulation time 409023999 ps
CPU time 5.1 seconds
Started Mar 24 01:53:50 PM PDT 24
Finished Mar 24 01:53:55 PM PDT 24
Peak memory 218472 kb
Host smart-9b54bd6f-f9e1-40e0-8aac-b1a551adde22
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1011176450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.1011176450
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.2448751593
Short name T23
Test name
Test status
Simulation time 337010755 ps
CPU time 5.01 seconds
Started Mar 24 01:53:54 PM PDT 24
Finished Mar 24 01:53:59 PM PDT 24
Peak memory 222960 kb
Host smart-67f1df34-6d89-49f5-bb77-f1d2dfa6aee9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2448751593 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.2448751593
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.3171023792
Short name T715
Test name
Test status
Simulation time 222082482 ps
CPU time 7.45 seconds
Started Mar 24 01:53:55 PM PDT 24
Finished Mar 24 01:54:03 PM PDT 24
Peak memory 220776 kb
Host smart-e902f041-1082-482b-87f0-8b4f5962cc18
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3171023792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.3171023792
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.1315186738
Short name T76
Test name
Test status
Simulation time 475590772 ps
CPU time 5.51 seconds
Started Mar 24 01:53:51 PM PDT 24
Finished Mar 24 01:53:57 PM PDT 24
Peak memory 214740 kb
Host smart-4e9bd5c5-c6c6-478b-9efd-db4fc15acede
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315186738 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.1315186738
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.2947590622
Short name T448
Test name
Test status
Simulation time 19389219 ps
CPU time 1.77 seconds
Started Mar 24 01:53:51 PM PDT 24
Finished Mar 24 01:53:52 PM PDT 24
Peak memory 207100 kb
Host smart-a2223529-ad1d-48b5-9eea-9076376ca1f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2947590622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.2947590622
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.2037028119
Short name T120
Test name
Test status
Simulation time 232132412 ps
CPU time 3.94 seconds
Started Mar 24 01:53:56 PM PDT 24
Finished Mar 24 01:54:00 PM PDT 24
Peak memory 209200 kb
Host smart-339d5cd6-ad1c-4bae-95f2-cf72671396cb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2037028119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.2037028119
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.3381300990
Short name T508
Test name
Test status
Simulation time 219193487 ps
CPU time 3.04 seconds
Started Mar 24 01:53:55 PM PDT 24
Finished Mar 24 01:53:58 PM PDT 24
Peak memory 208996 kb
Host smart-c3e64e9e-eeb1-4a94-bd10-76aa0143e316
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381300990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.3381300990
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.378946319
Short name T128
Test name
Test status
Simulation time 192955391 ps
CPU time 2.59 seconds
Started Mar 24 01:53:51 PM PDT 24
Finished Mar 24 01:53:54 PM PDT 24
Peak memory 207160 kb
Host smart-cc224c69-b311-406b-ae7f-0bdab71095c1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378946319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.378946319
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.2532822617
Short name T584
Test name
Test status
Simulation time 134698886 ps
CPU time 4.77 seconds
Started Mar 24 01:53:49 PM PDT 24
Finished Mar 24 01:53:54 PM PDT 24
Peak memory 208704 kb
Host smart-34ba37d5-d6a8-47e2-baed-a78f4bb6be1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532822617 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.2532822617
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.2385864943
Short name T684
Test name
Test status
Simulation time 191961572 ps
CPU time 3.21 seconds
Started Mar 24 01:53:51 PM PDT 24
Finished Mar 24 01:53:54 PM PDT 24
Peak memory 209096 kb
Host smart-a26a46e7-17dd-494f-9005-c556514e7f7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2385864943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.2385864943
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.2841197201
Short name T63
Test name
Test status
Simulation time 21377899477 ps
CPU time 617.89 seconds
Started Mar 24 01:53:51 PM PDT 24
Finished Mar 24 02:04:09 PM PDT 24
Peak memory 235420 kb
Host smart-24add29e-29b3-49d6-9df6-a30695af77b6
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2841197201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.2841197201
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/39.keymgr_stress_all_with_rand_reset.2057959223
Short name T176
Test name
Test status
Simulation time 319693803 ps
CPU time 8.93 seconds
Started Mar 24 01:53:55 PM PDT 24
Finished Mar 24 01:54:04 PM PDT 24
Peak memory 223028 kb
Host smart-b98baf41-9daa-41f8-92f4-1377d8f476dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2057959223 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all_with_rand_reset.2057959223
Directory /workspace/39.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.1691743159
Short name T532
Test name
Test status
Simulation time 302463794 ps
CPU time 4.03 seconds
Started Mar 24 01:53:51 PM PDT 24
Finished Mar 24 01:53:56 PM PDT 24
Peak memory 218748 kb
Host smart-1f936af1-7547-49ed-8b51-605a325af693
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1691743159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.1691743159
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.3856480260
Short name T900
Test name
Test status
Simulation time 414142139 ps
CPU time 3.79 seconds
Started Mar 24 01:53:49 PM PDT 24
Finished Mar 24 01:53:53 PM PDT 24
Peak memory 210920 kb
Host smart-442c9472-c3cf-40fa-97dc-8003aa24e09d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3856480260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.3856480260
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.4067924955
Short name T866
Test name
Test status
Simulation time 67970759 ps
CPU time 0.76 seconds
Started Mar 24 01:50:51 PM PDT 24
Finished Mar 24 01:50:51 PM PDT 24
Peak memory 206344 kb
Host smart-16d340f4-233b-40d1-bd48-f8db3cf1580e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067924955 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.4067924955
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.933729399
Short name T264
Test name
Test status
Simulation time 101391873 ps
CPU time 5.75 seconds
Started Mar 24 01:50:43 PM PDT 24
Finished Mar 24 01:50:49 PM PDT 24
Peak memory 214812 kb
Host smart-1ee56e80-5aa1-4e91-b38a-2be8a482fb5b
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=933729399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.933729399
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.358688412
Short name T20
Test name
Test status
Simulation time 505439211 ps
CPU time 3.94 seconds
Started Mar 24 01:50:44 PM PDT 24
Finished Mar 24 01:50:48 PM PDT 24
Peak memory 219060 kb
Host smart-386d31f8-834e-4a5d-b275-6c7d6da83456
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=358688412 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.358688412
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.4263486564
Short name T855
Test name
Test status
Simulation time 29831798 ps
CPU time 1.4 seconds
Started Mar 24 01:50:47 PM PDT 24
Finished Mar 24 01:50:49 PM PDT 24
Peak memory 207148 kb
Host smart-8af50b70-e031-4fe0-b04f-c1e28311b011
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263486564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.4263486564
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.3534700793
Short name T291
Test name
Test status
Simulation time 1295787803 ps
CPU time 5.29 seconds
Started Mar 24 01:50:47 PM PDT 24
Finished Mar 24 01:50:52 PM PDT 24
Peak memory 214844 kb
Host smart-df532579-2f6b-426b-9405-d60ac1abb1d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534700793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.3534700793
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.950933082
Short name T351
Test name
Test status
Simulation time 292660610 ps
CPU time 8.9 seconds
Started Mar 24 01:50:45 PM PDT 24
Finished Mar 24 01:50:54 PM PDT 24
Peak memory 214768 kb
Host smart-62fd4623-bdaf-4911-9b4d-6003b7746074
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=950933082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.950933082
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.2773970939
Short name T298
Test name
Test status
Simulation time 313816676 ps
CPU time 3.94 seconds
Started Mar 24 01:50:45 PM PDT 24
Finished Mar 24 01:50:49 PM PDT 24
Peak memory 209136 kb
Host smart-4432912c-edcb-41b8-8cc3-755e1e4c70ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2773970939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.2773970939
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.4121159807
Short name T505
Test name
Test status
Simulation time 10118858451 ps
CPU time 63.82 seconds
Started Mar 24 01:50:42 PM PDT 24
Finished Mar 24 01:51:46 PM PDT 24
Peak memory 210208 kb
Host smart-f0b8c52b-a7cc-4fcd-a65d-e856dfa19589
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4121159807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.4121159807
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.2484580479
Short name T93
Test name
Test status
Simulation time 825073292 ps
CPU time 21.93 seconds
Started Mar 24 01:50:49 PM PDT 24
Finished Mar 24 01:51:11 PM PDT 24
Peak memory 237444 kb
Host smart-f36fd99c-9213-40b3-96b7-06a20c7c961b
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2484580479 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.2484580479
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.2682990858
Short name T130
Test name
Test status
Simulation time 226091572 ps
CPU time 4.18 seconds
Started Mar 24 01:50:40 PM PDT 24
Finished Mar 24 01:50:45 PM PDT 24
Peak memory 207172 kb
Host smart-61b5a975-12b7-402b-a85b-5ae12a5b194c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2682990858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.2682990858
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.3347918036
Short name T514
Test name
Test status
Simulation time 64838840 ps
CPU time 3.3 seconds
Started Mar 24 01:50:40 PM PDT 24
Finished Mar 24 01:50:44 PM PDT 24
Peak memory 208824 kb
Host smart-ca3dc54a-394b-4484-80b6-ce9d5c77a0d0
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3347918036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.3347918036
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.3464824377
Short name T518
Test name
Test status
Simulation time 540528624 ps
CPU time 4.67 seconds
Started Mar 24 01:50:45 PM PDT 24
Finished Mar 24 01:50:50 PM PDT 24
Peak memory 208164 kb
Host smart-72c18762-88de-4d90-89f2-f5627e128eb5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3464824377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.3464824377
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.3592257983
Short name T903
Test name
Test status
Simulation time 44973143 ps
CPU time 2.44 seconds
Started Mar 24 01:50:41 PM PDT 24
Finished Mar 24 01:50:44 PM PDT 24
Peak memory 208808 kb
Host smart-3b24ae62-f399-46f1-bdd6-4880af34f75b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3592257983 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.3592257983
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.3271458100
Short name T402
Test name
Test status
Simulation time 136216215 ps
CPU time 2.53 seconds
Started Mar 24 01:50:46 PM PDT 24
Finished Mar 24 01:50:49 PM PDT 24
Peak memory 208488 kb
Host smart-1d770880-8fd1-4cdd-85d2-cc8cd4b1a235
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3271458100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.3271458100
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.1994520216
Short name T681
Test name
Test status
Simulation time 213947814 ps
CPU time 1.71 seconds
Started Mar 24 01:50:44 PM PDT 24
Finished Mar 24 01:50:46 PM PDT 24
Peak memory 207152 kb
Host smart-dc606acd-8c39-418d-bc70-7cf7cdd8e73b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1994520216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.1994520216
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.1245908786
Short name T453
Test name
Test status
Simulation time 131328945 ps
CPU time 5.44 seconds
Started Mar 24 01:50:47 PM PDT 24
Finished Mar 24 01:50:52 PM PDT 24
Peak memory 219116 kb
Host smart-a2f90d34-8e20-4f78-8a85-62f662f39d1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1245908786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.1245908786
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.3810347552
Short name T362
Test name
Test status
Simulation time 98021278 ps
CPU time 1.61 seconds
Started Mar 24 01:50:44 PM PDT 24
Finished Mar 24 01:50:46 PM PDT 24
Peak memory 210600 kb
Host smart-d8783792-d4a4-42f5-949b-65f9b27e3012
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810347552 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.3810347552
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.292735473
Short name T440
Test name
Test status
Simulation time 19213876 ps
CPU time 0.85 seconds
Started Mar 24 01:54:02 PM PDT 24
Finished Mar 24 01:54:03 PM PDT 24
Peak memory 206752 kb
Host smart-6d681ecc-b554-4a3f-af08-ead77e5e6af6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=292735473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.292735473
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.1344500681
Short name T29
Test name
Test status
Simulation time 102448093 ps
CPU time 2.27 seconds
Started Mar 24 01:53:54 PM PDT 24
Finished Mar 24 01:53:57 PM PDT 24
Peak memory 210120 kb
Host smart-7776ba20-ee58-45d4-ba8d-d5ec066e7bb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1344500681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.1344500681
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.3032031
Short name T607
Test name
Test status
Simulation time 40132544 ps
CPU time 1.7 seconds
Started Mar 24 01:53:54 PM PDT 24
Finished Mar 24 01:53:56 PM PDT 24
Peak memory 210336 kb
Host smart-9ea8a1c0-9610-48c3-a042-e0cd1ec992c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3032031 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.3032031
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.4033791437
Short name T88
Test name
Test status
Simulation time 164952799 ps
CPU time 3.19 seconds
Started Mar 24 01:53:54 PM PDT 24
Finished Mar 24 01:53:58 PM PDT 24
Peak memory 209224 kb
Host smart-a5ab9fc4-3bac-4bdc-b0e3-98da217395f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033791437 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.4033791437
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.3876899281
Short name T285
Test name
Test status
Simulation time 1073036875 ps
CPU time 24.73 seconds
Started Mar 24 01:53:55 PM PDT 24
Finished Mar 24 01:54:19 PM PDT 24
Peak memory 222936 kb
Host smart-d3d69b64-9c22-4ebf-88d5-39ddd6adc233
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3876899281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.3876899281
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.1957555127
Short name T847
Test name
Test status
Simulation time 252207345 ps
CPU time 1.61 seconds
Started Mar 24 01:53:55 PM PDT 24
Finished Mar 24 01:53:57 PM PDT 24
Peak memory 206600 kb
Host smart-30843514-a5f2-4565-a0f0-936645f55eb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1957555127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.1957555127
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.1747804225
Short name T895
Test name
Test status
Simulation time 2455478713 ps
CPU time 33.22 seconds
Started Mar 24 01:53:55 PM PDT 24
Finished Mar 24 01:54:28 PM PDT 24
Peak memory 210004 kb
Host smart-46dfa45b-6e3b-4b95-a251-c9c7638abfba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1747804225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.1747804225
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.701559357
Short name T311
Test name
Test status
Simulation time 139815521 ps
CPU time 4.64 seconds
Started Mar 24 01:53:55 PM PDT 24
Finished Mar 24 01:54:00 PM PDT 24
Peak memory 209192 kb
Host smart-1516e879-a58e-4a1f-a564-690f28225ec2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701559357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.701559357
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.1225458001
Short name T495
Test name
Test status
Simulation time 601769675 ps
CPU time 3.11 seconds
Started Mar 24 01:53:56 PM PDT 24
Finished Mar 24 01:53:59 PM PDT 24
Peak memory 208564 kb
Host smart-87794573-edb5-4a85-a8a3-cc292329a2ba
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1225458001 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.1225458001
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.1467174376
Short name T725
Test name
Test status
Simulation time 1289089648 ps
CPU time 9.84 seconds
Started Mar 24 01:53:56 PM PDT 24
Finished Mar 24 01:54:06 PM PDT 24
Peak memory 208624 kb
Host smart-ea62a796-53c6-469a-89a9-6f92fc82ac2b
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467174376 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.1467174376
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.2229528448
Short name T405
Test name
Test status
Simulation time 7921204898 ps
CPU time 55.88 seconds
Started Mar 24 01:53:55 PM PDT 24
Finished Mar 24 01:54:51 PM PDT 24
Peak memory 209624 kb
Host smart-04fba340-7f9c-4f95-9289-49ee977a48ca
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229528448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.2229528448
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.1502125671
Short name T784
Test name
Test status
Simulation time 91936255 ps
CPU time 2.66 seconds
Started Mar 24 01:53:57 PM PDT 24
Finished Mar 24 01:53:59 PM PDT 24
Peak memory 209764 kb
Host smart-f4306588-8267-431f-af09-0c3e797f2e39
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1502125671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.1502125671
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.2916245864
Short name T367
Test name
Test status
Simulation time 57502198 ps
CPU time 2.83 seconds
Started Mar 24 01:53:55 PM PDT 24
Finished Mar 24 01:53:58 PM PDT 24
Peak memory 208888 kb
Host smart-da1636d0-608b-49c3-a664-a551ab40b709
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2916245864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.2916245864
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.3831963935
Short name T275
Test name
Test status
Simulation time 785695966 ps
CPU time 10.38 seconds
Started Mar 24 01:53:58 PM PDT 24
Finished Mar 24 01:54:08 PM PDT 24
Peak memory 222912 kb
Host smart-ef3b8da0-2ac5-4f72-9478-a90e74e6f06c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3831963935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.3831963935
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.2462348272
Short name T295
Test name
Test status
Simulation time 198616145 ps
CPU time 3.88 seconds
Started Mar 24 01:54:01 PM PDT 24
Finished Mar 24 01:54:05 PM PDT 24
Peak memory 207788 kb
Host smart-231bfbd6-f886-42a9-b3d5-21497cdb8135
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2462348272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.2462348272
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.3551543855
Short name T600
Test name
Test status
Simulation time 54203077 ps
CPU time 2.05 seconds
Started Mar 24 01:53:55 PM PDT 24
Finished Mar 24 01:53:57 PM PDT 24
Peak memory 210464 kb
Host smart-6f4accbd-d7e3-4c1c-a9cc-e0d723edd3b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3551543855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.3551543855
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.3136366648
Short name T869
Test name
Test status
Simulation time 16759033 ps
CPU time 0.97 seconds
Started Mar 24 01:53:59 PM PDT 24
Finished Mar 24 01:54:00 PM PDT 24
Peak memory 206600 kb
Host smart-be0c073e-99ef-44a7-a101-a1740e8bb576
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3136366648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.3136366648
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.1787523651
Short name T873
Test name
Test status
Simulation time 483201283 ps
CPU time 3.31 seconds
Started Mar 24 01:54:01 PM PDT 24
Finished Mar 24 01:54:04 PM PDT 24
Peak memory 222104 kb
Host smart-ef266313-844d-4bd2-86e0-b3dcf88a2668
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1787523651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.1787523651
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.780903905
Short name T421
Test name
Test status
Simulation time 80315390 ps
CPU time 2.06 seconds
Started Mar 24 01:53:59 PM PDT 24
Finished Mar 24 01:54:01 PM PDT 24
Peak memory 208232 kb
Host smart-d7dc5f52-7f39-4b6d-b671-343d795b06e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=780903905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.780903905
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.1701905988
Short name T81
Test name
Test status
Simulation time 40049228 ps
CPU time 2.96 seconds
Started Mar 24 01:54:01 PM PDT 24
Finished Mar 24 01:54:04 PM PDT 24
Peak memory 209032 kb
Host smart-bc6dc3e5-1fee-4b35-b704-2db9e3bdd5a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701905988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.1701905988
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.3478206225
Short name T241
Test name
Test status
Simulation time 927238620 ps
CPU time 11.01 seconds
Started Mar 24 01:54:00 PM PDT 24
Finished Mar 24 01:54:11 PM PDT 24
Peak memory 214688 kb
Host smart-bcbae993-c830-4ac5-858c-1fb9c4f92674
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3478206225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.3478206225
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.1636773200
Short name T566
Test name
Test status
Simulation time 781716452 ps
CPU time 3.14 seconds
Started Mar 24 01:54:02 PM PDT 24
Finished Mar 24 01:54:05 PM PDT 24
Peak memory 210872 kb
Host smart-2b80ae84-c5b9-476a-aa78-f3b6f710af65
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1636773200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.1636773200
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.2615818691
Short name T658
Test name
Test status
Simulation time 237040308 ps
CPU time 5.64 seconds
Started Mar 24 01:54:17 PM PDT 24
Finished Mar 24 01:54:23 PM PDT 24
Peak memory 209376 kb
Host smart-3638a2b3-2ab5-4fa8-8a88-945be527875d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2615818691 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.2615818691
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.2073549122
Short name T497
Test name
Test status
Simulation time 296913807 ps
CPU time 4.2 seconds
Started Mar 24 01:53:59 PM PDT 24
Finished Mar 24 01:54:03 PM PDT 24
Peak memory 208780 kb
Host smart-051cee22-57e1-414a-8241-f4ceb0e35cad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2073549122 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.2073549122
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.3539756227
Short name T519
Test name
Test status
Simulation time 1140328308 ps
CPU time 7.14 seconds
Started Mar 24 01:53:59 PM PDT 24
Finished Mar 24 01:54:06 PM PDT 24
Peak memory 209300 kb
Host smart-69f37c27-999a-4316-848c-bd94a8ab394a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3539756227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.3539756227
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.2664545630
Short name T791
Test name
Test status
Simulation time 84826563 ps
CPU time 2.7 seconds
Started Mar 24 01:54:01 PM PDT 24
Finished Mar 24 01:54:04 PM PDT 24
Peak memory 207660 kb
Host smart-1c57631f-12d0-4d11-89bc-41b8a8e9612e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664545630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.2664545630
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.388945477
Short name T751
Test name
Test status
Simulation time 255154648 ps
CPU time 6.78 seconds
Started Mar 24 01:54:17 PM PDT 24
Finished Mar 24 01:54:24 PM PDT 24
Peak memory 208872 kb
Host smart-88cba339-3b99-46d0-9df4-ddf2af4651ed
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=388945477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.388945477
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.1415525508
Short name T644
Test name
Test status
Simulation time 131514801 ps
CPU time 5.32 seconds
Started Mar 24 01:53:57 PM PDT 24
Finished Mar 24 01:54:03 PM PDT 24
Peak memory 208376 kb
Host smart-ae296ac5-0a40-471f-9aea-78de974b1374
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415525508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.1415525508
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.739243580
Short name T446
Test name
Test status
Simulation time 505534129 ps
CPU time 5.38 seconds
Started Mar 24 01:54:02 PM PDT 24
Finished Mar 24 01:54:08 PM PDT 24
Peak memory 207128 kb
Host smart-7bf68a22-16e7-4732-a1cf-54f997164718
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=739243580 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.739243580
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.2247665687
Short name T193
Test name
Test status
Simulation time 684313058 ps
CPU time 15.73 seconds
Started Mar 24 01:54:00 PM PDT 24
Finished Mar 24 01:54:16 PM PDT 24
Peak memory 217208 kb
Host smart-3090a599-d3fd-4d1f-8f1f-de1be888c324
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2247665687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.2247665687
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.4286681659
Short name T669
Test name
Test status
Simulation time 3448477257 ps
CPU time 25.58 seconds
Started Mar 24 01:54:17 PM PDT 24
Finished Mar 24 01:54:43 PM PDT 24
Peak memory 218940 kb
Host smart-ea38b39d-9a71-4b45-ba40-4b508bc0743c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4286681659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.4286681659
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.3313384647
Short name T542
Test name
Test status
Simulation time 20204806 ps
CPU time 0.87 seconds
Started Mar 24 01:54:08 PM PDT 24
Finished Mar 24 01:54:10 PM PDT 24
Peak memory 206460 kb
Host smart-c5530df0-b1bf-4f36-be3d-0fddd0751cdc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313384647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.3313384647
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.2546056099
Short name T262
Test name
Test status
Simulation time 79330193 ps
CPU time 4.59 seconds
Started Mar 24 01:54:17 PM PDT 24
Finished Mar 24 01:54:22 PM PDT 24
Peak memory 215592 kb
Host smart-46c110ea-d747-4f78-be2f-30092f098a55
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2546056099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.2546056099
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.487240976
Short name T780
Test name
Test status
Simulation time 148709900 ps
CPU time 2.19 seconds
Started Mar 24 01:54:06 PM PDT 24
Finished Mar 24 01:54:08 PM PDT 24
Peak memory 210208 kb
Host smart-f218aaa8-8a12-4578-9f8b-60c2357fc5f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487240976 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.487240976
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.2232003426
Short name T771
Test name
Test status
Simulation time 35588790 ps
CPU time 1.6 seconds
Started Mar 24 01:54:01 PM PDT 24
Finished Mar 24 01:54:02 PM PDT 24
Peak memory 208196 kb
Host smart-04bfe4ee-21d0-4d14-a89c-6b6cbf6960c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2232003426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.2232003426
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.1268616231
Short name T668
Test name
Test status
Simulation time 215418596 ps
CPU time 7.48 seconds
Started Mar 24 01:54:06 PM PDT 24
Finished Mar 24 01:54:14 PM PDT 24
Peak memory 209620 kb
Host smart-bef47580-7d08-4c36-b310-8350ea9ebcb4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1268616231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.1268616231
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.1418473717
Short name T86
Test name
Test status
Simulation time 5092315667 ps
CPU time 33.99 seconds
Started Mar 24 01:54:07 PM PDT 24
Finished Mar 24 01:54:41 PM PDT 24
Peak memory 222880 kb
Host smart-bd7f0fbd-63cf-40b5-9943-e76df3e99889
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1418473717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.1418473717
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.787174937
Short name T768
Test name
Test status
Simulation time 338934519 ps
CPU time 2.82 seconds
Started Mar 24 01:54:06 PM PDT 24
Finished Mar 24 01:54:09 PM PDT 24
Peak memory 214708 kb
Host smart-e1f68054-6ab0-4dbe-a566-c796128f00b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787174937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.787174937
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.3663717930
Short name T615
Test name
Test status
Simulation time 363719942 ps
CPU time 3.34 seconds
Started Mar 24 01:54:02 PM PDT 24
Finished Mar 24 01:54:05 PM PDT 24
Peak memory 208628 kb
Host smart-704eed5c-809f-4dcd-985f-2f697ca636aa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663717930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.3663717930
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.764566835
Short name T489
Test name
Test status
Simulation time 94335540 ps
CPU time 2.59 seconds
Started Mar 24 01:54:17 PM PDT 24
Finished Mar 24 01:54:20 PM PDT 24
Peak memory 208500 kb
Host smart-184af61e-16a0-48d5-a317-ae6d9c4397bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764566835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.764566835
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.2098984110
Short name T827
Test name
Test status
Simulation time 53797113 ps
CPU time 2.96 seconds
Started Mar 24 01:54:17 PM PDT 24
Finished Mar 24 01:54:20 PM PDT 24
Peak memory 208684 kb
Host smart-c4b7c54e-45d6-4843-9781-f61e68193a5d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2098984110 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.2098984110
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.1124452196
Short name T592
Test name
Test status
Simulation time 60877643 ps
CPU time 3.37 seconds
Started Mar 24 01:54:17 PM PDT 24
Finished Mar 24 01:54:20 PM PDT 24
Peak memory 209108 kb
Host smart-11f6ed10-9b52-46ac-ba21-2ff34f0e83a4
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1124452196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.1124452196
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.1511323906
Short name T683
Test name
Test status
Simulation time 613624797 ps
CPU time 15.53 seconds
Started Mar 24 01:54:01 PM PDT 24
Finished Mar 24 01:54:16 PM PDT 24
Peak memory 209184 kb
Host smart-8590f408-a07a-485d-94a8-8356222ee053
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1511323906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.1511323906
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.630843077
Short name T576
Test name
Test status
Simulation time 37386700 ps
CPU time 1.98 seconds
Started Mar 24 01:54:04 PM PDT 24
Finished Mar 24 01:54:06 PM PDT 24
Peak memory 209152 kb
Host smart-a4b9e251-4db2-4be9-9aaa-267f77ffc275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630843077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.630843077
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.3099439042
Short name T434
Test name
Test status
Simulation time 630221415 ps
CPU time 3.33 seconds
Started Mar 24 01:54:01 PM PDT 24
Finished Mar 24 01:54:04 PM PDT 24
Peak memory 208840 kb
Host smart-76104516-b876-4ec3-8967-08e40943a15f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3099439042 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.3099439042
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.299245472
Short name T597
Test name
Test status
Simulation time 1063364274 ps
CPU time 6.56 seconds
Started Mar 24 01:54:04 PM PDT 24
Finished Mar 24 01:54:11 PM PDT 24
Peak memory 209948 kb
Host smart-acc38e1e-067d-4602-afb9-58394b6efbb4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=299245472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.299245472
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/42.keymgr_stress_all_with_rand_reset.448631113
Short name T776
Test name
Test status
Simulation time 507904274 ps
CPU time 14.94 seconds
Started Mar 24 01:54:04 PM PDT 24
Finished Mar 24 01:54:19 PM PDT 24
Peak memory 223140 kb
Host smart-e149999f-ef74-44bf-81ff-0b0fad4a274c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=448631113 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all_with_rand_reset.448631113
Directory /workspace/42.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.keymgr_sw_invalid_input.483382518
Short name T902
Test name
Test status
Simulation time 68039171 ps
CPU time 3.92 seconds
Started Mar 24 01:54:06 PM PDT 24
Finished Mar 24 01:54:11 PM PDT 24
Peak memory 214828 kb
Host smart-b041e923-6dce-481f-902b-0e297ea5bb92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=483382518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sw_invalid_input.483382518
Directory /workspace/42.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.2948072295
Short name T904
Test name
Test status
Simulation time 1129765972 ps
CPU time 2.9 seconds
Started Mar 24 01:54:03 PM PDT 24
Finished Mar 24 01:54:06 PM PDT 24
Peak memory 210732 kb
Host smart-f03a86fc-5f9f-4099-8d95-584071ddb684
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2948072295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.2948072295
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.1860605352
Short name T722
Test name
Test status
Simulation time 11414173 ps
CPU time 0.81 seconds
Started Mar 24 01:54:07 PM PDT 24
Finished Mar 24 01:54:08 PM PDT 24
Peak memory 206436 kb
Host smart-9c10721a-ff7d-4097-92aa-b4633a5f9d07
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860605352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.1860605352
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.2727792124
Short name T389
Test name
Test status
Simulation time 159711420 ps
CPU time 7.69 seconds
Started Mar 24 01:54:04 PM PDT 24
Finished Mar 24 01:54:12 PM PDT 24
Peak memory 215320 kb
Host smart-fc07fbc2-c0ff-4f12-9e54-b3e629cbf2d9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2727792124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.2727792124
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.1651268610
Short name T752
Test name
Test status
Simulation time 461547564 ps
CPU time 10.86 seconds
Started Mar 24 01:54:05 PM PDT 24
Finished Mar 24 01:54:16 PM PDT 24
Peak memory 220720 kb
Host smart-171ec1af-864f-4e73-bd8d-7ff70c8e03cb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1651268610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.1651268610
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.3364966365
Short name T87
Test name
Test status
Simulation time 227834333 ps
CPU time 7.05 seconds
Started Mar 24 01:54:06 PM PDT 24
Finished Mar 24 01:54:13 PM PDT 24
Peak memory 211124 kb
Host smart-c94f4585-c685-48f1-8ca5-969f33d144ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3364966365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.3364966365
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.2492945992
Short name T427
Test name
Test status
Simulation time 124123534 ps
CPU time 3.46 seconds
Started Mar 24 01:54:08 PM PDT 24
Finished Mar 24 01:54:12 PM PDT 24
Peak memory 221160 kb
Host smart-090d0fc1-7301-4125-8480-cdcd1eb79d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2492945992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.2492945992
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.884999112
Short name T842
Test name
Test status
Simulation time 217099229 ps
CPU time 4.88 seconds
Started Mar 24 01:54:08 PM PDT 24
Finished Mar 24 01:54:13 PM PDT 24
Peak memory 218852 kb
Host smart-d7fd0625-faad-406b-b276-6c6768f24bfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=884999112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.884999112
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.154444350
Short name T812
Test name
Test status
Simulation time 375285627 ps
CPU time 3.46 seconds
Started Mar 24 01:54:06 PM PDT 24
Finished Mar 24 01:54:09 PM PDT 24
Peak memory 207220 kb
Host smart-37551365-98cd-443a-b832-08867c136ff2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=154444350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.154444350
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.114656943
Short name T95
Test name
Test status
Simulation time 26033535 ps
CPU time 1.95 seconds
Started Mar 24 01:54:04 PM PDT 24
Finished Mar 24 01:54:06 PM PDT 24
Peak memory 207296 kb
Host smart-dee7d03d-8ce1-4c5a-b4c4-ad47578e9410
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=114656943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.114656943
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.4162613345
Short name T687
Test name
Test status
Simulation time 250598493 ps
CPU time 3.34 seconds
Started Mar 24 01:54:04 PM PDT 24
Finished Mar 24 01:54:07 PM PDT 24
Peak memory 207280 kb
Host smart-2b278de5-2178-46e4-98bf-af451edd5248
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4162613345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.4162613345
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.874966466
Short name T482
Test name
Test status
Simulation time 110653029 ps
CPU time 3.81 seconds
Started Mar 24 01:54:04 PM PDT 24
Finished Mar 24 01:54:08 PM PDT 24
Peak memory 207916 kb
Host smart-c8099b94-35a8-42fc-a5d6-84670d1e96ee
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=874966466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.874966466
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.2889413512
Short name T853
Test name
Test status
Simulation time 89079617 ps
CPU time 2.61 seconds
Started Mar 24 01:54:04 PM PDT 24
Finished Mar 24 01:54:07 PM PDT 24
Peak memory 218716 kb
Host smart-97661197-2979-4d3c-989b-084355820f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2889413512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.2889413512
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.756920457
Short name T499
Test name
Test status
Simulation time 73881551 ps
CPU time 1.7 seconds
Started Mar 24 01:54:07 PM PDT 24
Finished Mar 24 01:54:09 PM PDT 24
Peak memory 207416 kb
Host smart-ce1f3139-e941-401e-9c7b-7863dd9f1ceb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=756920457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.756920457
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.842073229
Short name T246
Test name
Test status
Simulation time 903704491 ps
CPU time 10.61 seconds
Started Mar 24 01:54:05 PM PDT 24
Finished Mar 24 01:54:16 PM PDT 24
Peak memory 217004 kb
Host smart-54e26e91-94ad-4e28-bfde-dd786378b53f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842073229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.842073229
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_stress_all_with_rand_reset.2229866644
Short name T45
Test name
Test status
Simulation time 493736189 ps
CPU time 18.49 seconds
Started Mar 24 01:54:05 PM PDT 24
Finished Mar 24 01:54:24 PM PDT 24
Peak memory 223016 kb
Host smart-538b544d-3fba-4502-adbc-64235c76a0cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229866644 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all_with_rand_reset.2229866644
Directory /workspace/43.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.4063325127
Short name T598
Test name
Test status
Simulation time 141562972 ps
CPU time 3.03 seconds
Started Mar 24 01:54:07 PM PDT 24
Finished Mar 24 01:54:10 PM PDT 24
Peak memory 207648 kb
Host smart-8e60fa20-ba71-444e-83b3-770d819094c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4063325127 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.4063325127
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.2373433176
Short name T102
Test name
Test status
Simulation time 204436218 ps
CPU time 2.25 seconds
Started Mar 24 01:54:05 PM PDT 24
Finished Mar 24 01:54:08 PM PDT 24
Peak memory 210340 kb
Host smart-6a5df4de-2a13-465b-a0e5-18dc6820581f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373433176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.2373433176
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.2314489544
Short name T694
Test name
Test status
Simulation time 20501141 ps
CPU time 0.74 seconds
Started Mar 24 01:54:10 PM PDT 24
Finished Mar 24 01:54:11 PM PDT 24
Peak memory 206460 kb
Host smart-87d66124-1701-4b90-b151-5bfca0d173dc
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2314489544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.2314489544
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.1097476822
Short name T22
Test name
Test status
Simulation time 33954004 ps
CPU time 2.24 seconds
Started Mar 24 01:54:10 PM PDT 24
Finished Mar 24 01:54:12 PM PDT 24
Peak memory 223260 kb
Host smart-2e36130c-378c-421b-abb9-8db36aadd642
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097476822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.1097476822
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.114107623
Short name T320
Test name
Test status
Simulation time 217333370 ps
CPU time 3.13 seconds
Started Mar 24 01:54:03 PM PDT 24
Finished Mar 24 01:54:07 PM PDT 24
Peak memory 208492 kb
Host smart-3ef44379-0c42-4b5c-afa1-4e1392ddb3b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114107623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.114107623
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.1460540388
Short name T244
Test name
Test status
Simulation time 1415049683 ps
CPU time 7.33 seconds
Started Mar 24 01:54:08 PM PDT 24
Finished Mar 24 01:54:16 PM PDT 24
Peak memory 209472 kb
Host smart-7d7a2da3-5572-4fa9-ab54-4b33e6634abc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1460540388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.1460540388
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.2286172266
Short name T806
Test name
Test status
Simulation time 222599092 ps
CPU time 8.12 seconds
Started Mar 24 01:54:07 PM PDT 24
Finished Mar 24 01:54:15 PM PDT 24
Peak memory 210968 kb
Host smart-078bf9f8-d3aa-4a59-87cc-71dc9030e792
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2286172266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.2286172266
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.1251799409
Short name T16
Test name
Test status
Simulation time 773985316 ps
CPU time 5.78 seconds
Started Mar 24 01:54:04 PM PDT 24
Finished Mar 24 01:54:09 PM PDT 24
Peak memory 209600 kb
Host smart-9ef644f4-61e6-4060-bdbd-c3fd43b4003a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251799409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.1251799409
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.3305892944
Short name T479
Test name
Test status
Simulation time 81677955 ps
CPU time 2.02 seconds
Started Mar 24 01:54:04 PM PDT 24
Finished Mar 24 01:54:06 PM PDT 24
Peak memory 207844 kb
Host smart-a2a63442-8000-4bc5-a2c4-8b6fcecacc9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3305892944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.3305892944
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.2446728151
Short name T704
Test name
Test status
Simulation time 301568474 ps
CPU time 7.87 seconds
Started Mar 24 01:54:05 PM PDT 24
Finished Mar 24 01:54:13 PM PDT 24
Peak memory 209020 kb
Host smart-21b6952b-4d41-4326-8081-65984e7490ec
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2446728151 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.2446728151
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.1649856641
Short name T688
Test name
Test status
Simulation time 95759813 ps
CPU time 3.56 seconds
Started Mar 24 01:54:07 PM PDT 24
Finished Mar 24 01:54:10 PM PDT 24
Peak memory 207336 kb
Host smart-784981c8-ef3c-4ed2-8657-5509dd493c04
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1649856641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.1649856641
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.30627150
Short name T611
Test name
Test status
Simulation time 71538745 ps
CPU time 2.77 seconds
Started Mar 24 01:54:08 PM PDT 24
Finished Mar 24 01:54:12 PM PDT 24
Peak memory 209100 kb
Host smart-4a54159a-443d-46d1-96d5-747657d27c32
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30627150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.30627150
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.1179163949
Short name T122
Test name
Test status
Simulation time 357360801 ps
CPU time 3.08 seconds
Started Mar 24 01:54:07 PM PDT 24
Finished Mar 24 01:54:10 PM PDT 24
Peak memory 209492 kb
Host smart-f37bb783-056e-427e-8fac-fa457f6e6014
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1179163949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.1179163949
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.3314155951
Short name T523
Test name
Test status
Simulation time 40497332 ps
CPU time 2.08 seconds
Started Mar 24 01:54:03 PM PDT 24
Finished Mar 24 01:54:05 PM PDT 24
Peak memory 207272 kb
Host smart-266c3182-4b09-46e6-9814-68f2e647fc6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3314155951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.3314155951
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_stress_all_with_rand_reset.99936527
Short name T643
Test name
Test status
Simulation time 190064279 ps
CPU time 7.97 seconds
Started Mar 24 01:54:07 PM PDT 24
Finished Mar 24 01:54:15 PM PDT 24
Peak memory 223088 kb
Host smart-1d47b70f-be38-4607-8711-359c5a7968fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99936527 -assert nopostp
roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all_with_rand_reset.99936527
Directory /workspace/44.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.327255355
Short name T203
Test name
Test status
Simulation time 672291281 ps
CPU time 20.09 seconds
Started Mar 24 01:54:06 PM PDT 24
Finished Mar 24 01:54:26 PM PDT 24
Peak memory 210292 kb
Host smart-431f7bac-7685-46de-9026-f6009185b57f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=327255355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.327255355
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.1416090858
Short name T358
Test name
Test status
Simulation time 108632740 ps
CPU time 1.58 seconds
Started Mar 24 01:54:11 PM PDT 24
Finished Mar 24 01:54:13 PM PDT 24
Peak memory 210044 kb
Host smart-d24082d4-e0f0-4b9e-a50c-829286bc66ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1416090858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.1416090858
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.2499461063
Short name T838
Test name
Test status
Simulation time 46475241 ps
CPU time 0.88 seconds
Started Mar 24 01:54:19 PM PDT 24
Finished Mar 24 01:54:20 PM PDT 24
Peak memory 206460 kb
Host smart-babfe5a7-fbcf-4a32-bc6c-c2c12fbf60f7
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499461063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.2499461063
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.1814855221
Short name T297
Test name
Test status
Simulation time 268978315 ps
CPU time 3.37 seconds
Started Mar 24 01:54:22 PM PDT 24
Finished Mar 24 01:54:26 PM PDT 24
Peak memory 218612 kb
Host smart-f09af3fd-5b79-4e49-860d-65a349f0ffa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814855221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.1814855221
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.1056811795
Short name T181
Test name
Test status
Simulation time 14681323 ps
CPU time 1.39 seconds
Started Mar 24 01:54:22 PM PDT 24
Finished Mar 24 01:54:24 PM PDT 24
Peak memory 208020 kb
Host smart-19fef853-a1ec-46ac-834a-a4b98e90f134
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1056811795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.1056811795
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.235187728
Short name T653
Test name
Test status
Simulation time 11623535375 ps
CPU time 118.91 seconds
Started Mar 24 01:54:20 PM PDT 24
Finished Mar 24 01:56:19 PM PDT 24
Peak memory 214884 kb
Host smart-8b6b9aba-9263-4861-ac78-d82746cb32a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=235187728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.235187728
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_kmac_rsp_err.872591559
Short name T680
Test name
Test status
Simulation time 1084156738 ps
CPU time 8.91 seconds
Started Mar 24 01:54:22 PM PDT 24
Finished Mar 24 01:54:31 PM PDT 24
Peak memory 212460 kb
Host smart-f4680dfc-1fdd-4556-974e-3485ca10c044
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=872591559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_kmac_rsp_err.872591559
Directory /workspace/45.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.1634657466
Short name T502
Test name
Test status
Simulation time 337702668 ps
CPU time 3.99 seconds
Started Mar 24 01:54:18 PM PDT 24
Finished Mar 24 01:54:22 PM PDT 24
Peak memory 214800 kb
Host smart-8d6f4d13-08b2-4094-826d-aee77ce296ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1634657466 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.1634657466
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.2926375124
Short name T98
Test name
Test status
Simulation time 295037118 ps
CPU time 4.49 seconds
Started Mar 24 01:54:08 PM PDT 24
Finished Mar 24 01:54:13 PM PDT 24
Peak memory 210036 kb
Host smart-2a770b0a-cfa5-484d-82bf-8bd40493e342
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2926375124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.2926375124
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.2826068586
Short name T493
Test name
Test status
Simulation time 187911079 ps
CPU time 6.16 seconds
Started Mar 24 01:54:11 PM PDT 24
Finished Mar 24 01:54:18 PM PDT 24
Peak memory 208432 kb
Host smart-0a4c4e3a-2181-41b5-a430-ee3f2362c8dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826068586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.2826068586
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.1895421017
Short name T1
Test name
Test status
Simulation time 277194980 ps
CPU time 3.65 seconds
Started Mar 24 01:54:09 PM PDT 24
Finished Mar 24 01:54:13 PM PDT 24
Peak memory 209184 kb
Host smart-c6f61c5e-b9f4-421c-8772-2263eb9bc2d4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895421017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.1895421017
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.1471215710
Short name T671
Test name
Test status
Simulation time 31322843 ps
CPU time 2.17 seconds
Started Mar 24 01:54:09 PM PDT 24
Finished Mar 24 01:54:11 PM PDT 24
Peak memory 208968 kb
Host smart-218f1f9b-d23b-4a8b-8093-aab0df5d4d85
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1471215710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.1471215710
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.2136725815
Short name T323
Test name
Test status
Simulation time 346617826 ps
CPU time 7.36 seconds
Started Mar 24 01:54:08 PM PDT 24
Finished Mar 24 01:54:15 PM PDT 24
Peak memory 208928 kb
Host smart-e6f4be68-c16b-43b0-977e-92064ce69f1c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2136725815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.2136725815
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.876019176
Short name T476
Test name
Test status
Simulation time 47821491 ps
CPU time 2.06 seconds
Started Mar 24 01:54:21 PM PDT 24
Finished Mar 24 01:54:23 PM PDT 24
Peak memory 209708 kb
Host smart-f8663691-56d3-448e-adbf-8eb4d3d75d51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876019176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.876019176
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.1966996205
Short name T828
Test name
Test status
Simulation time 318345264 ps
CPU time 3.05 seconds
Started Mar 24 01:54:09 PM PDT 24
Finished Mar 24 01:54:12 PM PDT 24
Peak memory 208892 kb
Host smart-b95f413e-8be0-4f6e-b60a-c7c29d3b5fdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1966996205 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.1966996205
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_stress_all_with_rand_reset.3281633424
Short name T767
Test name
Test status
Simulation time 1244198945 ps
CPU time 23.1 seconds
Started Mar 24 01:54:23 PM PDT 24
Finished Mar 24 01:54:47 PM PDT 24
Peak memory 224224 kb
Host smart-6383c7c2-53bd-44f4-a8c2-f71b085055c4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3281633424 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 45.keymgr_stress_all_with_rand_reset.3281633424
Directory /workspace/45.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.3222789223
Short name T558
Test name
Test status
Simulation time 476647190 ps
CPU time 6.26 seconds
Started Mar 24 01:54:19 PM PDT 24
Finished Mar 24 01:54:26 PM PDT 24
Peak memory 210084 kb
Host smart-a127feb9-ce13-4a20-b204-de250871991c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3222789223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.3222789223
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.2786311173
Short name T360
Test name
Test status
Simulation time 59664846 ps
CPU time 2.08 seconds
Started Mar 24 01:54:23 PM PDT 24
Finished Mar 24 01:54:26 PM PDT 24
Peak memory 210748 kb
Host smart-05d8438e-eec6-4832-a181-581d100118ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2786311173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.2786311173
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.4097899750
Short name T820
Test name
Test status
Simulation time 22598380 ps
CPU time 0.86 seconds
Started Mar 24 01:54:19 PM PDT 24
Finished Mar 24 01:54:20 PM PDT 24
Peak memory 206472 kb
Host smart-7a7128b5-43ba-4be9-a497-5d14457779c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4097899750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.4097899750
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.3599387596
Short name T281
Test name
Test status
Simulation time 196118145 ps
CPU time 10.91 seconds
Started Mar 24 01:54:19 PM PDT 24
Finished Mar 24 01:54:30 PM PDT 24
Peak memory 214860 kb
Host smart-c25c2b86-f15e-4475-9ef0-758257816c6e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3599387596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.3599387596
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.1476857903
Short name T888
Test name
Test status
Simulation time 10310543398 ps
CPU time 70.07 seconds
Started Mar 24 01:54:23 PM PDT 24
Finished Mar 24 01:55:34 PM PDT 24
Peak memory 215288 kb
Host smart-08451736-f585-4582-a3c5-0ecf254f6a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476857903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.1476857903
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.3991039761
Short name T535
Test name
Test status
Simulation time 163274466 ps
CPU time 3.43 seconds
Started Mar 24 01:54:21 PM PDT 24
Finished Mar 24 01:54:24 PM PDT 24
Peak memory 214804 kb
Host smart-87e0eb28-dc23-4885-8c6d-5a97319b4293
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3991039761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.3991039761
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.1493260774
Short name T738
Test name
Test status
Simulation time 335420451 ps
CPU time 4.44 seconds
Started Mar 24 01:54:23 PM PDT 24
Finished Mar 24 01:54:28 PM PDT 24
Peak memory 214792 kb
Host smart-e84f0788-3b66-4812-80af-beac70e44ba7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493260774 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.1493260774
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.1098189870
Short name T210
Test name
Test status
Simulation time 156196412 ps
CPU time 4.11 seconds
Started Mar 24 01:54:12 PM PDT 24
Finished Mar 24 01:54:17 PM PDT 24
Peak memory 214728 kb
Host smart-f770afd9-0982-4531-9bf5-818a83581d0b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1098189870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.1098189870
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.2503722129
Short name T701
Test name
Test status
Simulation time 726679491 ps
CPU time 6.47 seconds
Started Mar 24 01:54:25 PM PDT 24
Finished Mar 24 01:54:32 PM PDT 24
Peak memory 209304 kb
Host smart-a50caab2-717f-4c21-bbb9-c1f814bbc659
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2503722129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.2503722129
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.882389332
Short name T742
Test name
Test status
Simulation time 173417618 ps
CPU time 4.75 seconds
Started Mar 24 01:54:21 PM PDT 24
Finished Mar 24 01:54:26 PM PDT 24
Peak memory 208892 kb
Host smart-cb4f9032-93af-4457-b69c-c2d7749c97e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=882389332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.882389332
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.3581828174
Short name T871
Test name
Test status
Simulation time 122269870 ps
CPU time 4.08 seconds
Started Mar 24 01:54:22 PM PDT 24
Finished Mar 24 01:54:26 PM PDT 24
Peak memory 209104 kb
Host smart-d7f771f7-f42c-4f00-a5b3-d2676faab53f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3581828174 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.3581828174
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.1716195366
Short name T575
Test name
Test status
Simulation time 36541090 ps
CPU time 2.43 seconds
Started Mar 24 01:54:13 PM PDT 24
Finished Mar 24 01:54:15 PM PDT 24
Peak memory 209120 kb
Host smart-7d199457-b063-4a70-ae5b-e78a5dae0fc0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716195366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.1716195366
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.2170664349
Short name T441
Test name
Test status
Simulation time 547667543 ps
CPU time 15.95 seconds
Started Mar 24 01:54:14 PM PDT 24
Finished Mar 24 01:54:30 PM PDT 24
Peak memory 208932 kb
Host smart-e0aa2015-5c27-4373-8b47-5e9b509f103c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170664349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.2170664349
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.330168578
Short name T353
Test name
Test status
Simulation time 210793789 ps
CPU time 3.35 seconds
Started Mar 24 01:54:22 PM PDT 24
Finished Mar 24 01:54:26 PM PDT 24
Peak memory 207572 kb
Host smart-7eedd2be-8c10-4580-9b09-150bfb4ff7b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=330168578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.330168578
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.582053308
Short name T560
Test name
Test status
Simulation time 104394275 ps
CPU time 4 seconds
Started Mar 24 01:54:19 PM PDT 24
Finished Mar 24 01:54:23 PM PDT 24
Peak memory 207684 kb
Host smart-51b5717f-59b8-480f-90e6-f2a9bb69bf59
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582053308 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.582053308
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.3468227901
Short name T192
Test name
Test status
Simulation time 7985855427 ps
CPU time 95.66 seconds
Started Mar 24 01:54:19 PM PDT 24
Finished Mar 24 01:55:55 PM PDT 24
Peak memory 217732 kb
Host smart-1f9a8a35-cfbc-44e5-bd08-2d33a30e66f9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3468227901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.3468227901
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_stress_all_with_rand_reset.1257358853
Short name T175
Test name
Test status
Simulation time 3323684116 ps
CPU time 23.37 seconds
Started Mar 24 01:54:19 PM PDT 24
Finished Mar 24 01:54:43 PM PDT 24
Peak memory 223156 kb
Host smart-2f7eabf5-51c3-4b8b-947c-338ece09ad54
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257358853 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all_with_rand_reset.1257358853
Directory /workspace/46.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.945133067
Short name T795
Test name
Test status
Simulation time 6570558186 ps
CPU time 38.22 seconds
Started Mar 24 01:54:26 PM PDT 24
Finished Mar 24 01:55:04 PM PDT 24
Peak memory 209792 kb
Host smart-c5603b68-72e6-40da-a483-11f7cc0abbd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=945133067 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.945133067
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.2229633941
Short name T634
Test name
Test status
Simulation time 860094919 ps
CPU time 2.19 seconds
Started Mar 24 01:54:23 PM PDT 24
Finished Mar 24 01:54:25 PM PDT 24
Peak memory 210416 kb
Host smart-b2a3ddea-b2d0-4b6e-9864-91e21121ef6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229633941 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.2229633941
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.1431057163
Short name T72
Test name
Test status
Simulation time 56942445 ps
CPU time 0.77 seconds
Started Mar 24 01:54:22 PM PDT 24
Finished Mar 24 01:54:23 PM PDT 24
Peak memory 206420 kb
Host smart-3e3b7b07-084f-47a8-b1c0-429b51a08ed0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1431057163 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.1431057163
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.2188825201
Short name T296
Test name
Test status
Simulation time 3387360291 ps
CPU time 44.3 seconds
Started Mar 24 01:54:24 PM PDT 24
Finished Mar 24 01:55:08 PM PDT 24
Peak memory 214908 kb
Host smart-c6111d3d-8ecf-4d5c-8b84-efa5b86b40f8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2188825201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.2188825201
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.1946083952
Short name T282
Test name
Test status
Simulation time 657126171 ps
CPU time 8.26 seconds
Started Mar 24 01:54:24 PM PDT 24
Finished Mar 24 01:54:32 PM PDT 24
Peak memory 207704 kb
Host smart-a6cbda8b-149b-43f0-9477-e26b543fcd6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1946083952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.1946083952
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.555243882
Short name T25
Test name
Test status
Simulation time 62835427 ps
CPU time 3.87 seconds
Started Mar 24 01:54:23 PM PDT 24
Finished Mar 24 01:54:27 PM PDT 24
Peak memory 214732 kb
Host smart-595f6b4f-2258-437d-82c0-b83a0dcce94e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555243882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.555243882
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.1555927651
Short name T259
Test name
Test status
Simulation time 202563031 ps
CPU time 6.26 seconds
Started Mar 24 01:54:23 PM PDT 24
Finished Mar 24 01:54:29 PM PDT 24
Peak memory 214740 kb
Host smart-3c508149-5b86-4991-b5e5-da923edfdb7b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555927651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.1555927651
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.1930258960
Short name T371
Test name
Test status
Simulation time 76914397 ps
CPU time 3.42 seconds
Started Mar 24 01:54:23 PM PDT 24
Finished Mar 24 01:54:26 PM PDT 24
Peak memory 222904 kb
Host smart-c07ed249-7c4b-400a-8a4a-01e2b4123c06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1930258960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.1930258960
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.1791215755
Short name T450
Test name
Test status
Simulation time 334097814 ps
CPU time 7.31 seconds
Started Mar 24 01:54:22 PM PDT 24
Finished Mar 24 01:54:30 PM PDT 24
Peak memory 209836 kb
Host smart-16b88d17-9b10-4111-a34c-48a04832e5c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1791215755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.1791215755
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.939695087
Short name T397
Test name
Test status
Simulation time 544068261 ps
CPU time 3.9 seconds
Started Mar 24 01:54:19 PM PDT 24
Finished Mar 24 01:54:23 PM PDT 24
Peak memory 208860 kb
Host smart-34bb223b-0558-4399-89e7-86fb13301dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=939695087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.939695087
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.3784865557
Short name T349
Test name
Test status
Simulation time 7300372911 ps
CPU time 70.98 seconds
Started Mar 24 01:54:21 PM PDT 24
Finished Mar 24 01:55:33 PM PDT 24
Peak memory 209852 kb
Host smart-df6536d0-621a-4d8c-803a-c541c8aaf069
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3784865557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.3784865557
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.1004570129
Short name T403
Test name
Test status
Simulation time 194626671 ps
CPU time 2.7 seconds
Started Mar 24 01:54:23 PM PDT 24
Finished Mar 24 01:54:26 PM PDT 24
Peak memory 207252 kb
Host smart-f5682836-447c-4a5b-aa03-68a461c21a42
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004570129 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.1004570129
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.1420264652
Short name T818
Test name
Test status
Simulation time 47924325 ps
CPU time 2.88 seconds
Started Mar 24 01:54:18 PM PDT 24
Finished Mar 24 01:54:21 PM PDT 24
Peak memory 207344 kb
Host smart-6cb3efd0-3d9e-4310-b70c-6b2a164a2985
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1420264652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.1420264652
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.4088727250
Short name T374
Test name
Test status
Simulation time 7094795018 ps
CPU time 44.67 seconds
Started Mar 24 01:54:21 PM PDT 24
Finished Mar 24 01:55:06 PM PDT 24
Peak memory 219016 kb
Host smart-b2004fcb-889e-4b91-8adb-0250131bc7f8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4088727250 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.4088727250
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.847410344
Short name T411
Test name
Test status
Simulation time 139505655 ps
CPU time 3.55 seconds
Started Mar 24 01:54:21 PM PDT 24
Finished Mar 24 01:54:25 PM PDT 24
Peak memory 207644 kb
Host smart-84bc1eae-31ae-458f-a322-5ed74c24542f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=847410344 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.847410344
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.3223947816
Short name T230
Test name
Test status
Simulation time 4939130657 ps
CPU time 62.03 seconds
Started Mar 24 01:54:22 PM PDT 24
Finished Mar 24 01:55:24 PM PDT 24
Peak memory 219336 kb
Host smart-78f2e67a-726e-40ad-ae77-c99252091bf1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3223947816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.3223947816
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_stress_all_with_rand_reset.3548967209
Short name T326
Test name
Test status
Simulation time 1061411254 ps
CPU time 9.23 seconds
Started Mar 24 01:54:24 PM PDT 24
Finished Mar 24 01:54:34 PM PDT 24
Peak memory 220124 kb
Host smart-5f34d292-4f03-4973-92e0-c8621e1f60ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3548967209 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all_with_rand_reset.3548967209
Directory /workspace/47.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.3423049193
Short name T462
Test name
Test status
Simulation time 80382882 ps
CPU time 3.14 seconds
Started Mar 24 01:54:21 PM PDT 24
Finished Mar 24 01:54:25 PM PDT 24
Peak memory 210556 kb
Host smart-16685797-e853-46ea-a5bc-94a6eacb5248
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423049193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.3423049193
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.2154999274
Short name T361
Test name
Test status
Simulation time 133177695 ps
CPU time 2.37 seconds
Started Mar 24 01:54:25 PM PDT 24
Finished Mar 24 01:54:27 PM PDT 24
Peak memory 210480 kb
Host smart-1b707765-b8eb-4f04-8bf1-df823b758adb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154999274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.2154999274
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.1622598646
Short name T630
Test name
Test status
Simulation time 19750387 ps
CPU time 0.81 seconds
Started Mar 24 01:54:32 PM PDT 24
Finished Mar 24 01:54:33 PM PDT 24
Peak memory 206448 kb
Host smart-c32c2e2e-d328-47ce-9807-a75ecb8602d0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1622598646 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.1622598646
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.1193069311
Short name T390
Test name
Test status
Simulation time 961528765 ps
CPU time 12.31 seconds
Started Mar 24 01:54:23 PM PDT 24
Finished Mar 24 01:54:35 PM PDT 24
Peak memory 214808 kb
Host smart-01f91321-aa16-4338-8b0b-a9ecf280a2bc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1193069311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.1193069311
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.3301416453
Short name T31
Test name
Test status
Simulation time 290358721 ps
CPU time 7.89 seconds
Started Mar 24 01:54:25 PM PDT 24
Finished Mar 24 01:54:33 PM PDT 24
Peak memory 222032 kb
Host smart-bde76c3f-b03f-46ac-b5bf-71569ad91d99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3301416453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.3301416453
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.883732655
Short name T325
Test name
Test status
Simulation time 1213486005 ps
CPU time 28.18 seconds
Started Mar 24 01:54:27 PM PDT 24
Finished Mar 24 01:54:55 PM PDT 24
Peak memory 222944 kb
Host smart-a7b22842-9003-4540-ad74-a356cadf9ce5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=883732655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.883732655
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.3246871514
Short name T334
Test name
Test status
Simulation time 162378705 ps
CPU time 6.26 seconds
Started Mar 24 01:54:25 PM PDT 24
Finished Mar 24 01:54:31 PM PDT 24
Peak memory 214780 kb
Host smart-a42e2e8d-28bd-49b6-a6a2-f2259c7be5e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246871514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.3246871514
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_kmac_rsp_err.846091988
Short name T268
Test name
Test status
Simulation time 388601380 ps
CPU time 10.71 seconds
Started Mar 24 01:54:24 PM PDT 24
Finished Mar 24 01:54:36 PM PDT 24
Peak memory 222848 kb
Host smart-2f8f37d2-ada1-46a0-ab63-c64429c2bf2d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=846091988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_kmac_rsp_err.846091988
Directory /workspace/48.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.2990758173
Short name T346
Test name
Test status
Simulation time 54378632 ps
CPU time 3.42 seconds
Started Mar 24 01:54:24 PM PDT 24
Finished Mar 24 01:54:28 PM PDT 24
Peak memory 214728 kb
Host smart-fa1341b3-c296-45b4-a236-dad5b9ac6e26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2990758173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.2990758173
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.3260048893
Short name T530
Test name
Test status
Simulation time 2754357536 ps
CPU time 20.65 seconds
Started Mar 24 01:54:21 PM PDT 24
Finished Mar 24 01:54:42 PM PDT 24
Peak memory 208760 kb
Host smart-60b7a02d-fe1d-4dfc-aaa2-dfa01009388d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3260048893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.3260048893
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.813592974
Short name T763
Test name
Test status
Simulation time 1454073617 ps
CPU time 19.17 seconds
Started Mar 24 01:54:24 PM PDT 24
Finished Mar 24 01:54:44 PM PDT 24
Peak memory 208308 kb
Host smart-5e6a76fa-1b8c-4270-93d1-5ead9e3f4ef1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=813592974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.813592974
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.3932274723
Short name T699
Test name
Test status
Simulation time 875936856 ps
CPU time 6.36 seconds
Started Mar 24 01:54:24 PM PDT 24
Finished Mar 24 01:54:31 PM PDT 24
Peak memory 209152 kb
Host smart-86d6b9d7-2abd-4459-bd4e-75e19f6658eb
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932274723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.3932274723
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.286374119
Short name T348
Test name
Test status
Simulation time 64701489 ps
CPU time 3.38 seconds
Started Mar 24 01:54:24 PM PDT 24
Finished Mar 24 01:54:28 PM PDT 24
Peak memory 208956 kb
Host smart-714a0ff8-8fae-4e83-ac13-6cef93a7f603
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=286374119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.286374119
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.3864694378
Short name T549
Test name
Test status
Simulation time 126636774 ps
CPU time 3.35 seconds
Started Mar 24 01:54:24 PM PDT 24
Finished Mar 24 01:54:28 PM PDT 24
Peak memory 207420 kb
Host smart-d71c6624-0a0a-4e7f-ab9d-c94410ca37e1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864694378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.3864694378
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.2174975005
Short name T387
Test name
Test status
Simulation time 741588894 ps
CPU time 8.09 seconds
Started Mar 24 01:54:26 PM PDT 24
Finished Mar 24 01:54:34 PM PDT 24
Peak memory 209620 kb
Host smart-144b1d85-b851-4ef4-a9f6-01b01e505244
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174975005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.2174975005
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.219026156
Short name T540
Test name
Test status
Simulation time 133347561 ps
CPU time 3.86 seconds
Started Mar 24 01:54:26 PM PDT 24
Finished Mar 24 01:54:30 PM PDT 24
Peak memory 208732 kb
Host smart-a7f14d20-b89f-471c-a399-e2ead84e1a89
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=219026156 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.219026156
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.617913875
Short name T350
Test name
Test status
Simulation time 1466588292 ps
CPU time 21.56 seconds
Started Mar 24 01:54:24 PM PDT 24
Finished Mar 24 01:54:45 PM PDT 24
Peak memory 222864 kb
Host smart-fa7f6ed2-93ac-490b-8f13-78a5e2591abc
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=617913875 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.617913875
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.273502337
Short name T112
Test name
Test status
Simulation time 762881307 ps
CPU time 24.41 seconds
Started Mar 24 01:54:27 PM PDT 24
Finished Mar 24 01:54:51 PM PDT 24
Peak memory 220968 kb
Host smart-673a1a6b-52f8-4121-9ff9-9618d7f35857
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=273502337 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.273502337
Directory /workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.1923704133
Short name T314
Test name
Test status
Simulation time 910159174 ps
CPU time 4.04 seconds
Started Mar 24 01:54:22 PM PDT 24
Finished Mar 24 01:54:26 PM PDT 24
Peak memory 207692 kb
Host smart-15261e80-a807-472b-a18c-ca1c19bdb163
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1923704133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.1923704133
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.506100312
Short name T166
Test name
Test status
Simulation time 103452185 ps
CPU time 2.57 seconds
Started Mar 24 01:54:27 PM PDT 24
Finished Mar 24 01:54:30 PM PDT 24
Peak memory 210144 kb
Host smart-396c0482-6705-4583-ba4b-cf9527ed5c88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=506100312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.506100312
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.2205024063
Short name T416
Test name
Test status
Simulation time 17688172 ps
CPU time 0.81 seconds
Started Mar 24 01:54:32 PM PDT 24
Finished Mar 24 01:54:33 PM PDT 24
Peak memory 206368 kb
Host smart-29c0e6eb-c967-478a-a7cc-8bb541a2630f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2205024063 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.2205024063
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.1003076660
Short name T69
Test name
Test status
Simulation time 88775663 ps
CPU time 3.69 seconds
Started Mar 24 01:54:32 PM PDT 24
Finished Mar 24 01:54:36 PM PDT 24
Peak memory 214736 kb
Host smart-b3ea13f8-e0d5-48c2-b7fd-74f2d73fe641
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1003076660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.1003076660
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.231679587
Short name T809
Test name
Test status
Simulation time 917354353 ps
CPU time 16.58 seconds
Started Mar 24 01:54:33 PM PDT 24
Finished Mar 24 01:54:49 PM PDT 24
Peak memory 210940 kb
Host smart-c3fe3858-6433-4a0f-adbb-79d0561ea755
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=231679587 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.231679587
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.1902093734
Short name T804
Test name
Test status
Simulation time 40078793 ps
CPU time 1.54 seconds
Started Mar 24 01:54:28 PM PDT 24
Finished Mar 24 01:54:30 PM PDT 24
Peak memory 208640 kb
Host smart-ddd606e6-9950-40ae-a16b-a48a9a04b5ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1902093734 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.1902093734
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.1435476172
Short name T83
Test name
Test status
Simulation time 290117751 ps
CPU time 4.11 seconds
Started Mar 24 01:54:27 PM PDT 24
Finished Mar 24 01:54:31 PM PDT 24
Peak memory 210084 kb
Host smart-e6a59b5e-97e0-4837-8e3c-9c1b06246d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1435476172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.1435476172
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.2513473940
Short name T182
Test name
Test status
Simulation time 74244706 ps
CPU time 2.51 seconds
Started Mar 24 01:54:29 PM PDT 24
Finished Mar 24 01:54:32 PM PDT 24
Peak memory 216552 kb
Host smart-1fe4e2b3-c841-4987-a525-21bb98dbc982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2513473940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.2513473940
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.3535046668
Short name T652
Test name
Test status
Simulation time 7709773679 ps
CPU time 53.74 seconds
Started Mar 24 01:54:29 PM PDT 24
Finished Mar 24 01:55:23 PM PDT 24
Peak memory 209388 kb
Host smart-edad45e8-a57f-4b99-b913-0305cadb3e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3535046668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.3535046668
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.1505015253
Short name T300
Test name
Test status
Simulation time 53140821 ps
CPU time 2.82 seconds
Started Mar 24 01:54:27 PM PDT 24
Finished Mar 24 01:54:30 PM PDT 24
Peak memory 208348 kb
Host smart-6bb60106-950b-44e2-b6e7-7bad965d86ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1505015253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.1505015253
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.3626755526
Short name T336
Test name
Test status
Simulation time 5080045364 ps
CPU time 55.88 seconds
Started Mar 24 01:54:29 PM PDT 24
Finished Mar 24 01:55:25 PM PDT 24
Peak memory 208624 kb
Host smart-aae66960-d844-4a8d-b113-36ad2de46119
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3626755526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.3626755526
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.782765266
Short name T184
Test name
Test status
Simulation time 9408891825 ps
CPU time 56.67 seconds
Started Mar 24 01:54:31 PM PDT 24
Finished Mar 24 01:55:28 PM PDT 24
Peak memory 209336 kb
Host smart-29df4b3d-f4c1-42a2-a549-d5d74b62ff03
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=782765266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.782765266
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.2048859353
Short name T659
Test name
Test status
Simulation time 369355540 ps
CPU time 5.85 seconds
Started Mar 24 01:54:27 PM PDT 24
Finished Mar 24 01:54:34 PM PDT 24
Peak memory 208840 kb
Host smart-1b5da8de-a8ae-483e-9daf-c19b31fc2d6a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2048859353 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.2048859353
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.3826949782
Short name T734
Test name
Test status
Simulation time 39172042 ps
CPU time 1.63 seconds
Started Mar 24 01:54:26 PM PDT 24
Finished Mar 24 01:54:28 PM PDT 24
Peak memory 208276 kb
Host smart-e93373ed-3973-420a-8780-dec9cfeb6f6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3826949782 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.3826949782
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.1373439823
Short name T766
Test name
Test status
Simulation time 59481560 ps
CPU time 3.04 seconds
Started Mar 24 01:54:28 PM PDT 24
Finished Mar 24 01:54:31 PM PDT 24
Peak memory 207656 kb
Host smart-13d517ec-d40e-473c-a9c4-a8630d2370ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1373439823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.1373439823
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all_with_rand_reset.1238211984
Short name T220
Test name
Test status
Simulation time 1305232076 ps
CPU time 26.26 seconds
Started Mar 24 01:54:27 PM PDT 24
Finished Mar 24 01:54:54 PM PDT 24
Peak memory 223088 kb
Host smart-430cbcc6-d49b-48a2-b520-79035e01917e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238211984 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all_with_rand_reset.1238211984
Directory /workspace/49.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.3052551332
Short name T251
Test name
Test status
Simulation time 192803021 ps
CPU time 5.86 seconds
Started Mar 24 01:54:28 PM PDT 24
Finished Mar 24 01:54:34 PM PDT 24
Peak memory 214780 kb
Host smart-4b41f175-0a1a-4054-b798-66eadbc046a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052551332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.3052551332
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.3945517135
Short name T632
Test name
Test status
Simulation time 279017831 ps
CPU time 2.89 seconds
Started Mar 24 01:54:29 PM PDT 24
Finished Mar 24 01:54:33 PM PDT 24
Peak memory 210464 kb
Host smart-4914fcc3-7e2c-4298-84b5-5a47476eb351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3945517135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.3945517135
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.377202596
Short name T398
Test name
Test status
Simulation time 30012124 ps
CPU time 0.69 seconds
Started Mar 24 01:51:04 PM PDT 24
Finished Mar 24 01:51:04 PM PDT 24
Peak memory 206344 kb
Host smart-7e9a3ec6-6339-49bd-a708-ba41949ec0f0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=377202596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.377202596
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.1526933950
Short name T872
Test name
Test status
Simulation time 44285832 ps
CPU time 2.85 seconds
Started Mar 24 01:50:56 PM PDT 24
Finished Mar 24 01:50:59 PM PDT 24
Peak memory 215244 kb
Host smart-2a5478e1-4cb9-4e5a-9abf-c620cfd24224
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1526933950 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.1526933950
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.3809898988
Short name T894
Test name
Test status
Simulation time 111256162 ps
CPU time 3.92 seconds
Started Mar 24 01:50:55 PM PDT 24
Finished Mar 24 01:50:59 PM PDT 24
Peak memory 210384 kb
Host smart-ea3c1a2c-9f2c-46a5-a91b-b63ab9759661
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809898988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.3809898988
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.1438851028
Short name T18
Test name
Test status
Simulation time 413658780 ps
CPU time 4.15 seconds
Started Mar 24 01:50:54 PM PDT 24
Finished Mar 24 01:50:58 PM PDT 24
Peak memory 214784 kb
Host smart-eb5a5c15-24ff-413e-a7c8-a7af73cec9ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1438851028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.1438851028
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.3204893890
Short name T240
Test name
Test status
Simulation time 947687464 ps
CPU time 10.57 seconds
Started Mar 24 01:50:55 PM PDT 24
Finished Mar 24 01:51:05 PM PDT 24
Peak memory 214768 kb
Host smart-1d65fac0-f262-4275-8aa0-e79866b36670
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3204893890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.3204893890
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.10165395
Short name T56
Test name
Test status
Simulation time 47690322 ps
CPU time 3.64 seconds
Started Mar 24 01:50:55 PM PDT 24
Finished Mar 24 01:50:59 PM PDT 24
Peak memory 210816 kb
Host smart-67f6d11a-94d7-4abf-8449-697bb2b53d87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=10165395 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.10165395
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.2372132295
Short name T731
Test name
Test status
Simulation time 785681731 ps
CPU time 10.16 seconds
Started Mar 24 01:50:54 PM PDT 24
Finished Mar 24 01:51:04 PM PDT 24
Peak memory 219084 kb
Host smart-01798598-e473-44e1-9ec6-2bdfcaace299
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2372132295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.2372132295
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.4066658952
Short name T846
Test name
Test status
Simulation time 232329417 ps
CPU time 5.16 seconds
Started Mar 24 01:50:54 PM PDT 24
Finished Mar 24 01:50:59 PM PDT 24
Peak memory 207784 kb
Host smart-066e767d-4a64-4904-91d9-b68443c56aa3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4066658952 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.4066658952
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.4099035233
Short name T835
Test name
Test status
Simulation time 56308548 ps
CPU time 3.04 seconds
Started Mar 24 01:50:58 PM PDT 24
Finished Mar 24 01:51:01 PM PDT 24
Peak memory 207164 kb
Host smart-6b3a94f2-fb77-4c5b-91ee-adb60c62e568
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099035233 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.4099035233
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.2144554176
Short name T415
Test name
Test status
Simulation time 169940637 ps
CPU time 2.44 seconds
Started Mar 24 01:50:54 PM PDT 24
Finished Mar 24 01:50:56 PM PDT 24
Peak memory 208612 kb
Host smart-37973563-5ab3-4ba0-b48e-abd416f97391
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144554176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.2144554176
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.1578224723
Short name T785
Test name
Test status
Simulation time 446173633 ps
CPU time 2.35 seconds
Started Mar 24 01:51:03 PM PDT 24
Finished Mar 24 01:51:06 PM PDT 24
Peak memory 209080 kb
Host smart-fc93ede4-7bdd-4359-9413-7fd2edf9bf30
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1578224723 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.1578224723
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.104395559
Short name T662
Test name
Test status
Simulation time 427440936 ps
CPU time 3.93 seconds
Started Mar 24 01:50:57 PM PDT 24
Finished Mar 24 01:51:01 PM PDT 24
Peak memory 208428 kb
Host smart-cf45addd-4692-4ead-9fe5-38d7ae999af6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=104395559 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.104395559
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.3661928158
Short name T901
Test name
Test status
Simulation time 98863341 ps
CPU time 4.06 seconds
Started Mar 24 01:50:49 PM PDT 24
Finished Mar 24 01:50:53 PM PDT 24
Peak memory 208792 kb
Host smart-62f2b148-c53b-4e34-8650-6328f2f58f5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3661928158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.3661928158
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all_with_rand_reset.2170009217
Short name T723
Test name
Test status
Simulation time 315351225 ps
CPU time 12.99 seconds
Started Mar 24 01:50:55 PM PDT 24
Finished Mar 24 01:51:08 PM PDT 24
Peak memory 223080 kb
Host smart-c0e95cde-43ed-4334-b71e-6c961d14c52d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2170009217 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all_with_rand_reset.2170009217
Directory /workspace/5.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.1114504215
Short name T670
Test name
Test status
Simulation time 17249271465 ps
CPU time 37.19 seconds
Started Mar 24 01:50:54 PM PDT 24
Finished Mar 24 01:51:31 PM PDT 24
Peak memory 214928 kb
Host smart-c165e02a-0b2c-47d4-b699-18e043702b4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1114504215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.1114504215
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.2776457591
Short name T561
Test name
Test status
Simulation time 1849363657 ps
CPU time 3.86 seconds
Started Mar 24 01:51:03 PM PDT 24
Finished Mar 24 01:51:07 PM PDT 24
Peak memory 210252 kb
Host smart-5768c2df-3317-4a2f-907a-8221b0780bfa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2776457591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.2776457591
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.3983943779
Short name T665
Test name
Test status
Simulation time 15919694 ps
CPU time 0.94 seconds
Started Mar 24 01:51:00 PM PDT 24
Finished Mar 24 01:51:01 PM PDT 24
Peak memory 206608 kb
Host smart-c63a138f-c338-48b9-bc6d-1c5265eed967
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3983943779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.3983943779
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.1157534139
Short name T384
Test name
Test status
Simulation time 151559691 ps
CPU time 2.93 seconds
Started Mar 24 01:50:59 PM PDT 24
Finished Mar 24 01:51:02 PM PDT 24
Peak memory 214816 kb
Host smart-1f4b53e9-cfbd-4099-9b67-a6614f105a9a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1157534139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.1157534139
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.1300936603
Short name T641
Test name
Test status
Simulation time 540934899 ps
CPU time 3.81 seconds
Started Mar 24 01:51:01 PM PDT 24
Finished Mar 24 01:51:05 PM PDT 24
Peak memory 218548 kb
Host smart-7c5e285a-67a8-4462-9d96-42303bc1ec98
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1300936603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.1300936603
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.355656087
Short name T467
Test name
Test status
Simulation time 4141629609 ps
CPU time 24.25 seconds
Started Mar 24 01:51:02 PM PDT 24
Finished Mar 24 01:51:26 PM PDT 24
Peak memory 210192 kb
Host smart-131b4e3d-a5f0-45dd-a2de-3d6aff09f5c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355656087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.355656087
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.2382848428
Short name T82
Test name
Test status
Simulation time 143021496 ps
CPU time 5.35 seconds
Started Mar 24 01:51:03 PM PDT 24
Finished Mar 24 01:51:08 PM PDT 24
Peak memory 215020 kb
Host smart-a2222bfb-5806-492a-8b80-6b28c55b528d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2382848428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.2382848428
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.3746584514
Short name T321
Test name
Test status
Simulation time 180787249 ps
CPU time 5.84 seconds
Started Mar 24 01:51:02 PM PDT 24
Finished Mar 24 01:51:08 PM PDT 24
Peak memory 222868 kb
Host smart-6373d022-9b81-4778-8831-a4e8b5fa6516
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3746584514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.3746584514
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.1319368230
Short name T46
Test name
Test status
Simulation time 445939253 ps
CPU time 3.81 seconds
Started Mar 24 01:51:01 PM PDT 24
Finished Mar 24 01:51:05 PM PDT 24
Peak memory 215212 kb
Host smart-704745c9-79ef-487a-b30c-ecde1f01940f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1319368230 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.1319368230
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.1073708730
Short name T483
Test name
Test status
Simulation time 839291957 ps
CPU time 4.8 seconds
Started Mar 24 01:51:01 PM PDT 24
Finished Mar 24 01:51:06 PM PDT 24
Peak memory 209640 kb
Host smart-ad088e73-e22b-48ac-bffe-7e3c6ca1565a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1073708730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.1073708730
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.1617597039
Short name T565
Test name
Test status
Simulation time 139310801 ps
CPU time 3.14 seconds
Started Mar 24 01:50:56 PM PDT 24
Finished Mar 24 01:50:59 PM PDT 24
Peak memory 208912 kb
Host smart-6a49bb54-88dd-4816-8517-61ed94a4a7b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617597039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.1617597039
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.740105006
Short name T399
Test name
Test status
Simulation time 67081355 ps
CPU time 3.32 seconds
Started Mar 24 01:50:59 PM PDT 24
Finished Mar 24 01:51:02 PM PDT 24
Peak memory 207344 kb
Host smart-fd793e16-fc8a-4270-92f6-049c485a000c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=740105006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.740105006
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.692760455
Short name T850
Test name
Test status
Simulation time 1039648787 ps
CPU time 14.85 seconds
Started Mar 24 01:50:54 PM PDT 24
Finished Mar 24 01:51:09 PM PDT 24
Peak memory 209232 kb
Host smart-79a4a601-6d6a-47b2-8e1d-38b19b703667
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=692760455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.692760455
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.2644897158
Short name T231
Test name
Test status
Simulation time 1452882550 ps
CPU time 33.95 seconds
Started Mar 24 01:51:01 PM PDT 24
Finished Mar 24 01:51:35 PM PDT 24
Peak memory 208512 kb
Host smart-708452a9-8c45-4edf-a5ae-45ce1611e591
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2644897158 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.2644897158
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.3164752810
Short name T73
Test name
Test status
Simulation time 1086500602 ps
CPU time 13.25 seconds
Started Mar 24 01:51:02 PM PDT 24
Finished Mar 24 01:51:15 PM PDT 24
Peak memory 208492 kb
Host smart-34eccd03-9766-4566-951d-2023fde1123b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3164752810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.3164752810
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.2041557598
Short name T485
Test name
Test status
Simulation time 136536863 ps
CPU time 2.54 seconds
Started Mar 24 01:50:57 PM PDT 24
Finished Mar 24 01:51:00 PM PDT 24
Peak memory 207592 kb
Host smart-2fe47e68-011c-4b60-8229-5fe7ea26f264
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2041557598 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.2041557598
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.1151075793
Short name T279
Test name
Test status
Simulation time 577361578 ps
CPU time 6.8 seconds
Started Mar 24 01:50:59 PM PDT 24
Finished Mar 24 01:51:06 PM PDT 24
Peak memory 210348 kb
Host smart-c18f1358-a935-4c57-99a8-046806645d14
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1151075793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.1151075793
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.3726491915
Short name T154
Test name
Test status
Simulation time 112905765 ps
CPU time 2.55 seconds
Started Mar 24 01:51:00 PM PDT 24
Finished Mar 24 01:51:02 PM PDT 24
Peak memory 210096 kb
Host smart-85d43549-8e70-461d-a50b-3fc59c5f6bce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726491915 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.3726491915
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.1378087456
Short name T645
Test name
Test status
Simulation time 46367100 ps
CPU time 0.94 seconds
Started Mar 24 01:51:15 PM PDT 24
Finished Mar 24 01:51:16 PM PDT 24
Peak memory 206528 kb
Host smart-9dfc6ff8-009d-4622-81ad-023b60e6238c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378087456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.1378087456
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.4031202212
Short name T302
Test name
Test status
Simulation time 54409589 ps
CPU time 3.79 seconds
Started Mar 24 01:51:05 PM PDT 24
Finished Mar 24 01:51:09 PM PDT 24
Peak memory 215124 kb
Host smart-2370096d-5086-452d-be22-bcff6bad2ac4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4031202212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.4031202212
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.4046441173
Short name T906
Test name
Test status
Simulation time 494043974 ps
CPU time 5.96 seconds
Started Mar 24 01:51:10 PM PDT 24
Finished Mar 24 01:51:16 PM PDT 24
Peak memory 210044 kb
Host smart-0cc8daa0-0f43-4dc2-adf8-9ebd21a06c83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046441173 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.4046441173
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.55005190
Short name T445
Test name
Test status
Simulation time 50298709 ps
CPU time 2.36 seconds
Started Mar 24 01:51:11 PM PDT 24
Finished Mar 24 01:51:13 PM PDT 24
Peak memory 207968 kb
Host smart-cb4b3b2d-81c5-4b17-855e-55f648f06f94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55005190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.55005190
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.204567678
Short name T567
Test name
Test status
Simulation time 192513114 ps
CPU time 6.18 seconds
Started Mar 24 01:51:11 PM PDT 24
Finished Mar 24 01:51:17 PM PDT 24
Peak memory 214732 kb
Host smart-37493894-3432-4908-9030-61072c857694
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=204567678 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.204567678
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.3467709270
Short name T735
Test name
Test status
Simulation time 126095163 ps
CPU time 5.62 seconds
Started Mar 24 01:51:11 PM PDT 24
Finished Mar 24 01:51:16 PM PDT 24
Peak memory 214708 kb
Host smart-95bc9aa3-e392-4c03-98de-6aaeda58b8fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3467709270 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.3467709270
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.1810381176
Short name T801
Test name
Test status
Simulation time 208689710 ps
CPU time 3 seconds
Started Mar 24 01:51:14 PM PDT 24
Finished Mar 24 01:51:17 PM PDT 24
Peak memory 220772 kb
Host smart-ce81c083-32fd-41e9-9554-83ca7eb5f7a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1810381176 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.1810381176
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.1423283903
Short name T312
Test name
Test status
Simulation time 1078931235 ps
CPU time 8.26 seconds
Started Mar 24 01:51:03 PM PDT 24
Finished Mar 24 01:51:12 PM PDT 24
Peak memory 214848 kb
Host smart-1124178e-0c3b-4bcb-af55-591c14738fc5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1423283903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.1423283903
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.3846330924
Short name T261
Test name
Test status
Simulation time 206127445 ps
CPU time 5.41 seconds
Started Mar 24 01:51:04 PM PDT 24
Finished Mar 24 01:51:09 PM PDT 24
Peak memory 209084 kb
Host smart-577f24f0-fde2-4bec-be38-a587dd36ae4c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846330924 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.3846330924
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.1513208985
Short name T494
Test name
Test status
Simulation time 997770480 ps
CPU time 6.58 seconds
Started Mar 24 01:51:04 PM PDT 24
Finished Mar 24 01:51:11 PM PDT 24
Peak memory 208140 kb
Host smart-f290282f-0baf-4da1-9763-09621aa7fc88
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1513208985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.1513208985
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.2667781570
Short name T503
Test name
Test status
Simulation time 430303756 ps
CPU time 7.88 seconds
Started Mar 24 01:51:08 PM PDT 24
Finished Mar 24 01:51:16 PM PDT 24
Peak memory 208972 kb
Host smart-98ad013a-6eab-4ecc-9841-8e129a5116fd
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2667781570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.2667781570
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.2971147374
Short name T507
Test name
Test status
Simulation time 2174877851 ps
CPU time 15.14 seconds
Started Mar 24 01:51:06 PM PDT 24
Finished Mar 24 01:51:21 PM PDT 24
Peak memory 209168 kb
Host smart-a4d65de9-7feb-4dbf-a4b6-5c74abefb56e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2971147374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.2971147374
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.435845572
Short name T885
Test name
Test status
Simulation time 1405482643 ps
CPU time 16.64 seconds
Started Mar 24 01:51:10 PM PDT 24
Finished Mar 24 01:51:27 PM PDT 24
Peak memory 222948 kb
Host smart-712446b4-8a1d-4c77-a8df-ce0f595fd679
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=435845572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.435845572
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.3189087069
Short name T129
Test name
Test status
Simulation time 1320668832 ps
CPU time 43.58 seconds
Started Mar 24 01:51:07 PM PDT 24
Finished Mar 24 01:51:51 PM PDT 24
Peak memory 208624 kb
Host smart-b5d16b4f-f4d2-4095-b64c-b221690f2369
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3189087069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.3189087069
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.3276196784
Short name T883
Test name
Test status
Simulation time 910967722 ps
CPU time 18.33 seconds
Started Mar 24 01:51:14 PM PDT 24
Finished Mar 24 01:51:32 PM PDT 24
Peak memory 221928 kb
Host smart-b0ccfa90-d915-4ba7-98d1-a6d04aa34457
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276196784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.3276196784
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.1653296795
Short name T288
Test name
Test status
Simulation time 514356768 ps
CPU time 5.7 seconds
Started Mar 24 01:51:10 PM PDT 24
Finished Mar 24 01:51:16 PM PDT 24
Peak memory 210200 kb
Host smart-d5d864f7-a169-4dc7-9566-675f0a52eba6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1653296795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.1653296795
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.2147765853
Short name T706
Test name
Test status
Simulation time 454231284 ps
CPU time 2.46 seconds
Started Mar 24 01:51:11 PM PDT 24
Finished Mar 24 01:51:14 PM PDT 24
Peak memory 210648 kb
Host smart-40040ca3-e0f2-4342-9fcb-c3ace73eefd7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2147765853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.2147765853
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.3498652467
Short name T455
Test name
Test status
Simulation time 29266010 ps
CPU time 0.98 seconds
Started Mar 24 01:51:19 PM PDT 24
Finished Mar 24 01:51:21 PM PDT 24
Peak memory 206520 kb
Host smart-049e54eb-092e-4167-b4ee-24a3cab52898
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3498652467 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.3498652467
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.2933761921
Short name T237
Test name
Test status
Simulation time 45898143 ps
CPU time 1.58 seconds
Started Mar 24 01:51:15 PM PDT 24
Finished Mar 24 01:51:17 PM PDT 24
Peak memory 207596 kb
Host smart-1ce6f6fd-cf71-427a-b7d6-6ddca6e583fc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2933761921 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.2933761921
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.1027306885
Short name T596
Test name
Test status
Simulation time 34006338 ps
CPU time 2.53 seconds
Started Mar 24 01:51:16 PM PDT 24
Finished Mar 24 01:51:19 PM PDT 24
Peak memory 209636 kb
Host smart-0dec6ff6-e8c3-44c6-a74f-a22dcb12d972
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1027306885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.1027306885
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.45306428
Short name T304
Test name
Test status
Simulation time 3150168756 ps
CPU time 46.17 seconds
Started Mar 24 01:51:19 PM PDT 24
Finished Mar 24 01:52:05 PM PDT 24
Peak memory 218544 kb
Host smart-da5b7e4b-85f2-4672-924c-77c3d80ead16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=45306428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.45306428
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.554823140
Short name T213
Test name
Test status
Simulation time 254633519 ps
CPU time 2.82 seconds
Started Mar 24 01:51:19 PM PDT 24
Finished Mar 24 01:51:22 PM PDT 24
Peak memory 220332 kb
Host smart-518196e9-7ed5-4487-a103-900ab89bcc5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=554823140 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.554823140
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.2474075590
Short name T437
Test name
Test status
Simulation time 90216843 ps
CPU time 3.14 seconds
Started Mar 24 01:51:14 PM PDT 24
Finished Mar 24 01:51:18 PM PDT 24
Peak memory 215484 kb
Host smart-4e6a5569-e897-443f-b7aa-79454e3bd9e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2474075590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.2474075590
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.3290384713
Short name T198
Test name
Test status
Simulation time 55607584 ps
CPU time 2.52 seconds
Started Mar 24 01:51:17 PM PDT 24
Finished Mar 24 01:51:20 PM PDT 24
Peak memory 208828 kb
Host smart-7bb75f2a-b2f5-4cf0-b895-15ac170f3f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290384713 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.3290384713
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.2782231199
Short name T484
Test name
Test status
Simulation time 1714346380 ps
CPU time 8.47 seconds
Started Mar 24 01:51:16 PM PDT 24
Finished Mar 24 01:51:25 PM PDT 24
Peak memory 208640 kb
Host smart-c5bedc2b-1395-4735-87af-dcc588085938
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782231199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.2782231199
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.3800128824
Short name T501
Test name
Test status
Simulation time 167400168 ps
CPU time 6.47 seconds
Started Mar 24 01:51:17 PM PDT 24
Finished Mar 24 01:51:23 PM PDT 24
Peak memory 209400 kb
Host smart-4b1790c2-02d8-4704-8298-3857a30ee90f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3800128824 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.3800128824
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.3243533631
Short name T562
Test name
Test status
Simulation time 466271140 ps
CPU time 2.94 seconds
Started Mar 24 01:51:21 PM PDT 24
Finished Mar 24 01:51:24 PM PDT 24
Peak memory 216284 kb
Host smart-302be7f4-6185-4c74-86ed-9e1281e27660
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243533631 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.3243533631
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.391426588
Short name T429
Test name
Test status
Simulation time 1168625429 ps
CPU time 4.47 seconds
Started Mar 24 01:51:19 PM PDT 24
Finished Mar 24 01:51:23 PM PDT 24
Peak memory 208656 kb
Host smart-0964824c-de24-45d8-9d0a-55d022d8b84b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391426588 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.391426588
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.1895655531
Short name T215
Test name
Test status
Simulation time 3504283645 ps
CPU time 39.29 seconds
Started Mar 24 01:51:20 PM PDT 24
Finished Mar 24 01:51:59 PM PDT 24
Peak memory 216448 kb
Host smart-50856f13-3461-4bc4-8142-4f45ee2113b2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895655531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.1895655531
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.694386882
Short name T249
Test name
Test status
Simulation time 123697642 ps
CPU time 4.68 seconds
Started Mar 24 01:51:17 PM PDT 24
Finished Mar 24 01:51:21 PM PDT 24
Peak memory 208676 kb
Host smart-10eb2a92-9a8e-4316-afc5-b8da8bbcd2d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=694386882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.694386882
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.729880206
Short name T195
Test name
Test status
Simulation time 1610932237 ps
CPU time 5.97 seconds
Started Mar 24 01:51:21 PM PDT 24
Finished Mar 24 01:51:27 PM PDT 24
Peak memory 210680 kb
Host smart-8870821b-8df8-4fd6-9078-7ba8a203b876
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729880206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.729880206
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.1540680195
Short name T449
Test name
Test status
Simulation time 17162219 ps
CPU time 0.78 seconds
Started Mar 24 01:51:29 PM PDT 24
Finished Mar 24 01:51:30 PM PDT 24
Peak memory 206444 kb
Host smart-91bf238e-a2ae-407e-a865-1d11200c7798
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1540680195 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.1540680195
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.1019611413
Short name T185
Test name
Test status
Simulation time 427758894 ps
CPU time 4.9 seconds
Started Mar 24 01:51:27 PM PDT 24
Finished Mar 24 01:51:34 PM PDT 24
Peak memory 214728 kb
Host smart-465c8ba1-c3e4-4a55-aa1d-efaaf90093f4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1019611413 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.1019611413
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.2721799963
Short name T8
Test name
Test status
Simulation time 359682489 ps
CPU time 7.89 seconds
Started Mar 24 01:51:28 PM PDT 24
Finished Mar 24 01:51:37 PM PDT 24
Peak memory 215144 kb
Host smart-3176b9d1-9d84-4f97-a125-bd80642a9155
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2721799963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.2721799963
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.2187651807
Short name T178
Test name
Test status
Simulation time 115902756 ps
CPU time 4.26 seconds
Started Mar 24 01:51:26 PM PDT 24
Finished Mar 24 01:51:31 PM PDT 24
Peak memory 209548 kb
Host smart-f8b3187a-4f1f-4bc7-961d-f48d9f480061
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187651807 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.2187651807
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.1152736599
Short name T870
Test name
Test status
Simulation time 69834942 ps
CPU time 2.8 seconds
Started Mar 24 01:51:28 PM PDT 24
Finished Mar 24 01:51:32 PM PDT 24
Peak memory 208964 kb
Host smart-c6c50183-ccc8-4501-8025-09571d8de278
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1152736599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.1152736599
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.4144444959
Short name T238
Test name
Test status
Simulation time 18048378979 ps
CPU time 40.52 seconds
Started Mar 24 01:51:28 PM PDT 24
Finished Mar 24 01:52:09 PM PDT 24
Peak memory 222940 kb
Host smart-06497a0f-83b0-4bef-bdd9-787c23554a61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4144444959 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.4144444959
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.1983272112
Short name T589
Test name
Test status
Simulation time 134791923 ps
CPU time 3.36 seconds
Started Mar 24 01:51:26 PM PDT 24
Finished Mar 24 01:51:30 PM PDT 24
Peak memory 209368 kb
Host smart-ebe3d19d-07aa-4578-9341-a6e8f9236fba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1983272112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.1983272112
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.3624454989
Short name T372
Test name
Test status
Simulation time 89927961 ps
CPU time 4.35 seconds
Started Mar 24 01:51:20 PM PDT 24
Finished Mar 24 01:51:25 PM PDT 24
Peak memory 207692 kb
Host smart-32207668-973b-4ac9-b73e-ad51fc604958
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3624454989 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.3624454989
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.2314753980
Short name T886
Test name
Test status
Simulation time 98758862 ps
CPU time 3.12 seconds
Started Mar 24 01:51:20 PM PDT 24
Finished Mar 24 01:51:23 PM PDT 24
Peak memory 208452 kb
Host smart-4094b94e-9335-47a9-a41c-8792a19b17b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2314753980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.2314753980
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.3424596949
Short name T631
Test name
Test status
Simulation time 87652062 ps
CPU time 1.92 seconds
Started Mar 24 01:51:21 PM PDT 24
Finished Mar 24 01:51:23 PM PDT 24
Peak memory 207832 kb
Host smart-a6c6caf6-4721-4ceb-8c79-cd52851a0366
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3424596949 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.3424596949
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.2794930739
Short name T664
Test name
Test status
Simulation time 140950922 ps
CPU time 4.94 seconds
Started Mar 24 01:51:20 PM PDT 24
Finished Mar 24 01:51:26 PM PDT 24
Peak memory 208276 kb
Host smart-ea448f14-286d-4a6a-82f5-d563bf8195d0
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2794930739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.2794930739
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.139263315
Short name T443
Test name
Test status
Simulation time 1061817357 ps
CPU time 11.54 seconds
Started Mar 24 01:51:20 PM PDT 24
Finished Mar 24 01:51:32 PM PDT 24
Peak memory 208936 kb
Host smart-190c0f10-12bb-4496-9747-c18090bae66f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=139263315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.139263315
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.1698652568
Short name T196
Test name
Test status
Simulation time 274279505 ps
CPU time 3.73 seconds
Started Mar 24 01:51:26 PM PDT 24
Finished Mar 24 01:51:30 PM PDT 24
Peak memory 210728 kb
Host smart-90f920b1-c71f-495c-b421-be0f115a5fda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1698652568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.1698652568
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.2322969739
Short name T183
Test name
Test status
Simulation time 625448331 ps
CPU time 13.26 seconds
Started Mar 24 01:51:20 PM PDT 24
Finished Mar 24 01:51:34 PM PDT 24
Peak memory 208184 kb
Host smart-65cb51c8-ba3c-47cc-b4f5-4ac1fcc2692c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2322969739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.2322969739
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.3830394497
Short name T97
Test name
Test status
Simulation time 288596286 ps
CPU time 4.36 seconds
Started Mar 24 01:51:26 PM PDT 24
Finished Mar 24 01:51:31 PM PDT 24
Peak memory 220540 kb
Host smart-1929d27f-aeff-4901-88ae-6dcd83a1af1e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3830394497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.3830394497
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.3237031394
Short name T550
Test name
Test status
Simulation time 475148519 ps
CPU time 4.66 seconds
Started Mar 24 01:51:29 PM PDT 24
Finished Mar 24 01:51:34 PM PDT 24
Peak memory 210336 kb
Host smart-74110c88-8719-4412-9e0b-f9be41597d5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237031394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.3237031394
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.1157595571
Short name T357
Test name
Test status
Simulation time 60469960 ps
CPU time 1.76 seconds
Started Mar 24 01:51:28 PM PDT 24
Finished Mar 24 01:51:30 PM PDT 24
Peak memory 210692 kb
Host smart-08ec51c3-7eaa-4bba-bc39-7bd56859ad1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1157595571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.1157595571
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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