Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
81.10	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	51	0	51	100.00
Crosses	330	72	258	78.18

Variables for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
aes_sl_avail	2	0	2	100.00	100	1	1	2
aes_sl_avail_cp	2	0	2	100.00	100	1	1	2
kmac_sl_avail	2	0	2	100.00	100	1	1	2
kmac_sl_avail_cp	2	0	2	100.00	100	1	1	2
op	5	0	5	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
otbn_sl_avail	2	0	2	100.00	100	1	1	2
otbn_sl_avail_cp	2	0	2	100.00	100	1	1	2
regwen_cp	2	0	2	100.00	100	1	1	2
sideload_clear	8	0	8	100.00	100	1	1	8
sideload_clear_cp	5	0	5	100.00	100	1	1	0
state	7	0	7	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sideload_clear_x_state_op_cross	280	53	227	81.07	100	1	1	0
sideload_clear_x_sl_avail_cross	40	19	21	52.50	100	1	1	0
sideload_clear_x_regwen_cross	10	0	10	100.00	100	1	1	0

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4736

1

T1

4

T2

5

T3

7

auto[1]

561

1

T1

1

T2

3

T15

6

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4736

1

T1

4

T2

5

T3

7

auto[1]

561

1

T1

1

T2

3

T15

6

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4776

1

T1

4

T2

8

T3

7

auto[1]

521

1

T1

1

T13

2

T41

6

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4776

1

T1

4

T2

8

T3

7

auto[1]

521

1

T1

1

T13

2

T41

6

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	399	1			T3	3		T106	3		T96	1
auto[OpGenId]	1133	1			T1	2		T13	2		T17	1
auto[OpGenSwOut]	1138	1			T1	2		T3	3		T17	5
auto[OpGenHwOut]	2559	1			T1	1		T2	8		T3	1
auto[OpDisable]	68	1			T60	1		T43	2		T62	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	399	1			T3	3		T106	3		T96	1
auto[OpGenId]	1133	1			T1	2		T13	2		T17	1
auto[OpGenSwOut]	1138	1			T1	2		T3	3		T17	5
auto[OpGenHwOut]	2559	1			T1	1		T2	8		T3	1
auto[OpDisable]	68	1			T60	1		T43	2		T62	1

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4772

1

T1

5

T2

8

T3

7

auto[1]

525

1

T14

3

T41

5

T102

3

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4772

1

T1

5

T2

8

T3

7

auto[1]

525

1

T14

3

T41

5

T102

3

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4998

1

T1

5

T2

8

T3

7

auto[1]

299

1

T41

7

T106

11

T110

5

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1791	1			T1	3		T2	1		T3	1
auto[1]	737	1			T2	1		T17	2		T41	5
auto[2]	677	1			T2	2		T3	3		T14	2
auto[3]	661	1			T1	1		T2	1		T3	1
auto[4]	352	1			T2	2		T3	2		T14	1
auto[5]	375	1			T2	1		T88	1		T27	1
auto[6]	336	1			T14	2		T15	1		T17	2
auto[7]	368	1			T1	1		T13	1		T88	1

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1431	1			T1	1		T2	3		T3	2
clear_one[1]	737	1			T2	1		T17	2		T41	5
clear_one[2]	677	1			T2	2		T3	3		T14	2
clear_one[3]	661	1			T1	1		T2	1		T3	1
clear_none	1791	1			T1	3		T2	1		T3	1

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	994	1			T1	2		T3	1		T17	4
auto[StInit]	771	1			T2	1		T3	6		T14	1
auto[StCreatorRootKey]	550	1			T1	1		T2	1		T13	1
auto[StOwnerIntKey]	510	1			T1	1		T2	1		T13	1
auto[StOwnerKey]	470	1			T2	1		T14	1		T15	1
auto[StDisabled]	1842	1			T1	1		T2	4		T13	2
auto[StInvalid]	160	1			T17	1		T39	4		T23	4

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	994	1			T1	2		T3	1		T17	4
auto[StInit]	771	1			T2	1		T3	6		T14	1
auto[StCreatorRootKey]	550	1			T1	1		T2	1		T13	1
auto[StOwnerIntKey]	510	1			T1	1		T2	1		T13	1
auto[StOwnerKey]	470	1			T2	1		T14	1		T15	1
auto[StDisabled]	1842	1			T1	1		T2	4		T13	2
auto[StInvalid]	160	1			T17	1		T39	4		T23	4

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	53	227	81.07	53

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[0]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[1] - auto[2]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	2
[auto[1] - auto[2]]	[auto[StReset]]	[auto[OpDisable]]	--	--	2
[auto[1] - auto[2]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	8
[auto[1] - auto[2]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	2
[auto[3] - auto[4]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	10
[auto[3] - auto[4]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	2
[auto[5] - auto[7]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	3
[auto[5] - auto[7]]	[auto[StReset]]	[auto[OpDisable]]	--	--	3
[auto[5] - auto[7]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	12
[auto[5] - auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	3

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpAdvance]	1	1			T233	1		-	-		-	-
auto[0]	auto[StReset]	auto[OpGenId]	141	1			T17	1		T41	1		T28	1
auto[0]	auto[StReset]	auto[OpGenSwOut]	167	1			T1	1		T3	1		T17	1
auto[0]	auto[StReset]	auto[OpGenHwOut]	277	1			T27	1		T107	1		T110	1
auto[0]	auto[StInit]	auto[OpAdvance]	42	1			T96	1		T7	1		T94	1
auto[0]	auto[StInit]	auto[OpGenId]	110	1			T102	1		T46	1		T43	1
auto[0]	auto[StInit]	auto[OpGenSwOut]	89	1			T6	3		T46	1		T29	1
auto[0]	auto[StInit]	auto[OpGenHwOut]	174	1			T2	1		T14	1		T15	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	22	1			T234	1		T124	1		T72	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	52	1			T13	1		T6	1		T60	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	51	1			T122	1		T6	1		T43	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	59	1			T88	1		T110	1		T6	1
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	6	1			T110	1		T94	1		T42	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	30	1			T1	1		T46	1		T60	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	24	1			T6	1		T60	1		T43	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	62	1			T14	1		T15	1		T6	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T208	1		T235	1		T236	1
auto[0]	auto[StOwnerKey]	auto[OpGenId]	23	1			T237	1		T58	1		T70	1
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	31	1			T106	4		T62	1		T238	1
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	45	1			T206	1		T239	1		T240	1
auto[0]	auto[StDisabled]	auto[OpAdvance]	19	1			T241	1		T242	1		T31	1
auto[0]	auto[StDisabled]	auto[OpGenId]	61	1			T27	1		T168	1		T43	2
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	71	1			T41	1		T46	1		T243	1
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	166	1			T1	1		T15	1		T88	1
auto[0]	auto[StDisabled]	auto[OpDisable]	23	1			T43	2		T62	1		T244	2
auto[0]	auto[StInvalid]	auto[OpAdvance]	6	1			T207	1		T245	1		T246	1
auto[0]	auto[StInvalid]	auto[OpGenId]	15	1			T203	1		T200	1		T204	1
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	10	1			T199	1		T200	1		T202	1
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	10	1			T39	1		T202	1		T207	1
auto[1]	auto[StReset]	auto[OpGenId]	19	1			T41	1		T45	1		T61	1
auto[1]	auto[StReset]	auto[OpGenSwOut]	14	1			T110	1		T50	1		T93	1
auto[1]	auto[StReset]	auto[OpGenHwOut]	44	1			T27	1		T23	1		T82	1
auto[1]	auto[StInit]	auto[OpAdvance]	12	1			T93	1		T247	3		T248	1
auto[1]	auto[StInit]	auto[OpGenId]	24	1			T6	1		T62	1		T249	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	19	1			T43	1		T47	1		T250	1
auto[1]	auto[StInit]	auto[OpGenHwOut]	39	1			T129	1		T24	1		T139	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	6	1			T250	1		T251	1		T252	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	16	1			T94	1		T43	1		T62	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	16	1			T17	1		T94	1		T201	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	41	1			T175	1		T136	1		T253	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	7	1			T254	1		T58	1		T255	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	24	1			T41	1		T176	1		T43	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	10	1			T102	1		T256	1		T257	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	33	1			T17	1		T107	1		T55	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	10	1			T106	1		T258	1		T259	1
auto[1]	auto[StOwnerKey]	auto[OpGenId]	15	1			T6	1		T43	1		T260	1
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	21	1			T110	1		T24	1		T261	1
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	39	1			T41	3		T102	1		T136	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	31	1			T106	2		T240	1		T250	1
auto[1]	auto[StDisabled]	auto[OpGenId]	56	1			T106	1		T6	1		T60	2
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	57	1			T6	3		T62	2		T262	1
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	154	1			T2	1		T106	1		T107	1
auto[1]	auto[StDisabled]	auto[OpDisable]	6	1			T59	2		T127	1		T263	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	2	1			T205	1		T264	1		-	-
auto[1]	auto[StInvalid]	auto[OpGenId]	8	1			T200	1		T202	1		T245	1
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	8	1			T23	1		T99	1		T265	1
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	6	1			T205	1		T245	1		T99	1
auto[2]	auto[StReset]	auto[OpGenId]	16	1			T130	1		T43	1		T250	1
auto[2]	auto[StReset]	auto[OpGenSwOut]	16	1			T17	1		T106	1		T6	2
auto[2]	auto[StReset]	auto[OpGenHwOut]	40	1			T6	1		T84	1		T201	1
auto[2]	auto[StInit]	auto[OpAdvance]	12	1			T3	2		T95	1		T266	1
auto[2]	auto[StInit]	auto[OpGenId]	16	1			T106	1		T130	1		T267	1
auto[2]	auto[StInit]	auto[OpGenSwOut]	13	1			T3	1		T43	1		T201	1
auto[2]	auto[StInit]	auto[OpGenHwOut]	28	1			T106	2		T6	2		T137	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	8	1			T43	1		T83	1		T261	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	12	1			T96	1		T6	1		T157	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	12	1			T6	1		T103	1		T46	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	34	1			T2	1		T14	1		T107	1
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	11	1			T208	1		T211	1		T268	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	12	1			T168	1		T269	1		T266	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	15	1			T6	1		T43	2		T262	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	41	1			T206	1		T129	1		T82	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	4	1			T157	1		T270	1		T271	1
auto[2]	auto[StOwnerKey]	auto[OpGenId]	7	1			T59	1		T72	1		T272	1
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	18	1			T47	2		T273	1		T274	1
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	40	1			T137	1		T201	1		T275	1
auto[2]	auto[StDisabled]	auto[OpAdvance]	18	1			T276	1		T277	1		T247	1
auto[2]	auto[StDisabled]	auto[OpGenId]	52	1			T41	3		T6	1		T243	1
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	67	1			T6	1		T60	1		T43	1
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	152	1			T2	1		T14	1		T102	2
auto[2]	auto[StDisabled]	auto[OpDisable]	12	1			T73	1		T278	1		T268	1
auto[2]	auto[StInvalid]	auto[OpAdvance]	4	1			T39	1		T279	1		T280	1
auto[2]	auto[StInvalid]	auto[OpGenId]	6	1			T281	1		T282	2		T283	1
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	7	1			T202	1		T284	1		T279	1
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	4	1			T264	1		T285	1		T286	1
auto[3]	auto[StReset]	auto[OpAdvance]	1	1			T287	1		-	-		-	-
auto[3]	auto[StReset]	auto[OpGenId]	23	1			T1	1		T6	1		T7	1
auto[3]	auto[StReset]	auto[OpGenSwOut]	14	1			T60	1		T87	1		T201	1
auto[3]	auto[StReset]	auto[OpGenHwOut]	31	1			T139	2		T201	1		T288	1
auto[3]	auto[StInit]	auto[OpAdvance]	12	1			T81	1		T244	1		T147	2
auto[3]	auto[StInit]	auto[OpGenId]	8	1			T41	1		T289	1		T145	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	12	1			T17	1		T168	1		T24	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	39	1			T3	1		T111	1		T6	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T290	1		T172	1		T291	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	15	1			T79	1		T201	1		T147	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	11	1			T62	1		T292	1		T293	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	34	1			T15	1		T41	2		T129	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T294	1		T295	1		T296	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	14	1			T13	1		T96	1		T208	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	12	1			T46	1		T143	2		T173	2
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	45	1			T108	1		T43	1		T84	1
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	6	1			T29	1		T201	1		T47	1
auto[3]	auto[StOwnerKey]	auto[OpGenId]	9	1			T43	1		T146	2		T42	1
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	18	1			T141	1		T256	1		T143	2
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	41	1			T14	1		T15	1		T107	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	15	1			T43	1		T144	1		T237	1
auto[3]	auto[StDisabled]	auto[OpGenId]	58	1			T27	1		T6	3		T130	1
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	53	1			T6	2		T46	2		T43	2
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	154	1			T2	1		T13	1		T15	2
auto[3]	auto[StDisabled]	auto[OpDisable]	11	1			T60	1		T59	1		T70	1
auto[3]	auto[StInvalid]	auto[OpAdvance]	5	1			T282	1		T297	1		T298	1
auto[3]	auto[StInvalid]	auto[OpGenId]	2	1			T284	1		T265	1		-	-
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	6	1			T204	1		T284	1		T299	1
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	5	1			T297	1		T300	1		T280	1
auto[4]	auto[StReset]	auto[OpAdvance]	1	1			T301	1		-	-		-	-
auto[4]	auto[StReset]	auto[OpGenId]	7	1			T23	1		T7	1		T65	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	12	1			T244	2		T302	1		T303	1
auto[4]	auto[StReset]	auto[OpGenHwOut]	27	1			T43	1		T304	1		T247	1
auto[4]	auto[StInit]	auto[OpAdvance]	4	1			T3	1		T305	1		T306	1
auto[4]	auto[StInit]	auto[OpGenId]	7	1			T25	1		T95	1		T307	1
auto[4]	auto[StInit]	auto[OpGenSwOut]	9	1			T3	1		T6	1		T26	1
auto[4]	auto[StInit]	auto[OpGenHwOut]	8	1			T289	1		T70	1		T308	1
auto[4]	auto[StCreatorRootKey]	auto[OpAdvance]	7	1			T29	1		T43	1		T294	3
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	7	1			T309	1		T249	1		T59	2
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	10	1			T106	1		T261	1		T310	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	15	1			T206	1		T43	1		T311	1
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T145	1		T294	1		T312	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	12	1			T106	2		T43	1		T261	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	6	1			T6	1		T70	1		T313	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	18	1			T2	1		T175	1		T139	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	2	1			T91	1		T65	1		-	-
auto[4]	auto[StOwnerKey]	auto[OpGenId]	9	1			T6	1		T249	1		T268	1
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	6	1			T71	1		T314	1		T291	1
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	20	1			T234	1		T315	1		T316	1
auto[4]	auto[StDisabled]	auto[OpAdvance]	13	1			T141	1		T157	1		T276	1
auto[4]	auto[StDisabled]	auto[OpGenId]	30	1			T201	2		T249	1		T292	1
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	22	1			T6	1		T130	1		T157	1
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	84	1			T2	1		T14	1		T88	1
auto[4]	auto[StDisabled]	auto[OpDisable]	1	1			T317	1		-	-		-	-
auto[4]	auto[StInvalid]	auto[OpAdvance]	2	1			T39	1		T318	1		-	-
auto[4]	auto[StInvalid]	auto[OpGenId]	4	1			T265	1		T319	1		T298	1
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	3	1			T23	1		T203	1		T298	1
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	3	1			T264	1		T320	1		T286	1
auto[5]	auto[StReset]	auto[OpGenId]	10	1			T23	1		T87	1		T321	1
auto[5]	auto[StReset]	auto[OpGenSwOut]	11	1			T322	1		T70	1		T212	1
auto[5]	auto[StReset]	auto[OpGenHwOut]	17	1			T129	1		T137	1		T323	1
auto[5]	auto[StInit]	auto[OpAdvance]	6	1			T324	1		T219	1		T325	2
auto[5]	auto[StInit]	auto[OpGenId]	7	1			T95	1		T90	1		T302	1
auto[5]	auto[StInit]	auto[OpGenSwOut]	10	1			T43	1		T26	1		T90	1
auto[5]	auto[StInit]	auto[OpGenHwOut]	12	1			T175	1		T243	1		T93	1
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	3	1			T47	1		T279	1		T326	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	8	1			T267	1		T327	1		T325	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	6	1			T27	1		T86	1		T269	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	22	1			T43	1		T84	1		T304	1
auto[5]	auto[StOwnerIntKey]	auto[OpAdvance]	11	1			T157	1		T258	1		T270	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	9	1			T226	1		T328	1		T329	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	8	1			T141	1		T261	1		T63	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	20	1			T275	1		T171	1		T330	1
auto[5]	auto[StOwnerKey]	auto[OpAdvance]	7	1			T331	1		T332	1		T147	1
auto[5]	auto[StOwnerKey]	auto[OpGenId]	6	1			T80	1		T71	1		T333	1
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	3	1			T201	1		T334	1		T230	1
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	19	1			T2	1		T88	1		T96	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	12	1			T110	1		T87	1		T174	1
auto[5]	auto[StDisabled]	auto[OpGenId]	26	1			T110	1		T6	1		T46	1
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	31	1			T141	1		T62	1		T171	1
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	90	1			T107	1		T110	1		T6	1
auto[5]	auto[StDisabled]	auto[OpDisable]	4	1			T47	1		T335	1		T78	1
auto[5]	auto[StInvalid]	auto[OpAdvance]	5	1			T203	1		T336	1		T337	1
auto[5]	auto[StInvalid]	auto[OpGenId]	6	1			T203	1		T205	1		T207	1
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	3	1			T297	1		T338	1		T339	1
auto[5]	auto[StInvalid]	auto[OpGenHwOut]	3	1			T202	1		T339	1		T285	1
auto[6]	auto[StReset]	auto[OpGenId]	11	1			T43	1		T340	1		T261	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	10	1			T87	1		T341	1		T302	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	29	1			T17	1		T107	1		T60	1
auto[6]	auto[StInit]	auto[OpAdvance]	2	1			T342	1		T343	1		-	-
auto[6]	auto[StInit]	auto[OpGenId]	4	1			T93	1		T262	1		T326	1
auto[6]	auto[StInit]	auto[OpGenSwOut]	7	1			T93	1		T344	1		T305	1
auto[6]	auto[StInit]	auto[OpGenHwOut]	12	1			T43	1		T82	1		T87	1
auto[6]	auto[StCreatorRootKey]	auto[OpAdvance]	5	1			T243	1		T145	1		T172	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	9	1			T144	1		T58	1		T345	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	5	1			T6	1		T47	1		T277	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	24	1			T6	1		T137	1		T346	1
auto[6]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T347	1		T348	1		T291	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	3	1			T273	1		T349	1		T350	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	6	1			T62	1		T173	1		T351	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	20	1			T346	1		T43	1		T352	1
auto[6]	auto[StOwnerKey]	auto[OpAdvance]	3	1			T261	1		T125	1		T353	1
auto[6]	auto[StOwnerKey]	auto[OpGenId]	3	1			T125	1		T173	1		T229	1
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	4	1			T208	1		T342	1		T78	2
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	10	1			T253	1		T354	1		T242	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	9	1			T355	1		T356	1		T357	1
auto[6]	auto[StDisabled]	auto[OpGenId]	25	1			T6	1		T60	1		T43	1
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	38	1			T108	1		T168	1		T43	1
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	73	1			T14	2		T15	1		T88	1
auto[6]	auto[StDisabled]	auto[OpDisable]	5	1			T59	1		T172	1		T358	1
auto[6]	auto[StInvalid]	auto[OpAdvance]	2	1			T99	1		T318	1		-	-
auto[6]	auto[StInvalid]	auto[OpGenId]	4	1			T39	1		T199	1		T359	1
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	6	1			T17	1		T264	1		T336	1
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	4	1			T23	1		T207	1		T99	1
auto[7]	auto[StReset]	auto[OpGenId]	10	1			T243	2		T244	1		T305	1
auto[7]	auto[StReset]	auto[OpGenSwOut]	13	1			T61	1		T360	1		T47	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	32	1			T6	1		T82	1		T360	1
auto[7]	auto[StInit]	auto[OpAdvance]	4	1			T309	1		T361	1		T232	1
auto[7]	auto[StInit]	auto[OpGenId]	11	1			T362	1		T344	1		T92	1
auto[7]	auto[StInit]	auto[OpGenSwOut]	4	1			T19	1		T363	1		T364	1
auto[7]	auto[StInit]	auto[OpGenHwOut]	15	1			T60	1		T43	1		T67	1
auto[7]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T6	1		T365	1		T224	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	10	1			T44	1		T258	1		T70	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	6	1			T1	1		T111	1		T366	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	17	1			T275	1		T321	1		T63	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T324	1		T367	1		T252	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	10	1			T46	1		T173	1		T174	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	7	1			T65	1		T128	1		T368	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	21	1			T88	1		T309	1		T369	1
auto[7]	auto[StOwnerKey]	auto[OpAdvance]	2	1			T370	1		T371	1		-	-
auto[7]	auto[StOwnerKey]	auto[OpGenId]	10	1			T60	1		T201	1		T148	1
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	7	1			T46	1		T362	1		T47	1
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	28	1			T6	1		T372	1		T373	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	14	1			T6	1		T276	1		T241	1
auto[7]	auto[StDisabled]	auto[OpGenId]	26	1			T6	1		T46	1		T60	1
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	20	1			T96	1		T47	1		T58	1
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	77	1			T13	1		T175	1		T46	2
auto[7]	auto[StDisabled]	auto[OpDisable]	6	1			T67	1		T374	1		T375	1
auto[7]	auto[StInvalid]	auto[OpAdvance]	1	1			T376	1		-	-		-	-
auto[7]	auto[StInvalid]	auto[OpGenId]	5	1			T23	1		T264	1		T318	1
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	3	1			T202	1		T300	1		T377	1
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	2	1			T199	1		T204	1		-	-

---

Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1431

1

T1

1

T2

3

T3

2

clear_one[1]

auto[0]

auto[0]

auto[0]

444

1

T2

1

T17

2

T41

1

clear_one[1]

auto[0]

auto[0]

auto[1]

117

1

T102

1

T106

3

T175

2

clear_one[1]

auto[0]

auto[1]

auto[0]

137

1

T41

3

T110

1

T6

1

clear_one[1]

auto[0]

auto[1]

auto[1]

39

1

T41

1

T106

1

T62

1

clear_one[2]

auto[0]

auto[0]

auto[0]

385

1

T3

3

T17

1

T106

4

clear_one[2]

auto[0]

auto[0]

auto[1]

129

1

T14

2

T41

3

T6

1

clear_one[2]

auto[1]

auto[0]

auto[0]

123

1

T2

2

T107

1

T108

1

clear_one[2]

auto[1]

auto[0]

auto[1]

40

1

T102

2

T6

1

T103

1

clear_one[3]

auto[0]

auto[0]

auto[0]

389

1

T1

1

T3

1

T14

1

clear_one[3]

auto[0]

auto[1]

auto[0]

103

1

T13

2

T27

1

T46

1

clear_one[3]

auto[1]

auto[0]

auto[0]

136

1

T2

1

T15

4

T88

1

clear_one[3]

auto[1]

auto[1]

auto[0]

33

1

T41

1

T108

1

T6

2

clear_none

auto[0]

auto[0]

auto[0]

1305

1

T1

2

T2

1

T3

1

clear_none

auto[0]

auto[0]

auto[1]

109

1

T14

1

T175

1

T129

1

clear_none

auto[0]

auto[1]

auto[0]

117

1

T110

2

T6

3

T168

1

clear_none

auto[0]

auto[1]

auto[1]

31

1

T41

1

T43

1

T87

1

clear_none

auto[1]

auto[0]

auto[0]

132

1

T15

2

T88

2

T107

1

clear_none

auto[1]

auto[0]

auto[1]

36

1

T43

3

T201

1

T47

1

clear_none

auto[1]

auto[1]

auto[0]

37

1

T1

1

T27

1

T108

1

clear_none

auto[1]

auto[1]

auto[1]

24

1

T261

1

T208

2

T59

1

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1342	1			T1	1		T2	3		T3	2
clear_all	auto[1]	89	1			T106	2		T110	3		T157	3
clear_one[1]	auto[0]	681	1			T2	1		T17	2		T41	2
clear_one[1]	auto[1]	56	1			T41	3		T106	4		T143	1
clear_one[2]	auto[0]	629	1			T2	2		T3	3		T14	2
clear_one[2]	auto[1]	48	1			T41	2		T106	2		T157	2
clear_one[3]	auto[0]	608	1			T1	1		T2	1		T3	1
clear_one[3]	auto[1]	53	1			T41	2		T87	1		T143	3
clear_none	auto[0]	1738	1			T1	3		T2	1		T3	1
clear_none	auto[1]	53	1			T106	3		T110	2		T143	5