Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
43.16	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	360	216	144	40.00

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	168	112	40.00	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11217

1

T1

20

T2

5

T3

20

auto[Attestation]

8387

1

T1

11

T2

3

T3

8

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	2957	1			T1	6		T3	4		T4	2
auto[Aes]	3563	1			T1	4		T2	8		T3	7
auto[Kmac]	3462	1			T1	6		T3	5		T4	1
auto[Otbn]	3459	1			T1	2		T3	6		T13	3

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	7902	1			T1	8		T2	8		T3	8
auto[OpGenId]	6163	1			T1	13		T3	6		T4	1
auto[OpGenSwOut]	6230	1			T1	8		T3	12		T4	3
auto[OpGenHwOut]	7211	1			T1	10		T2	8		T3	10
auto[OpDisable]	139	1			T6	1		T45	1		T46	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10289

1

T1

14

T2

8

T3

1

auto[OpDoneFail]

17356

1

T1

25

T2

8

T3

35

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6147	1			T1	8		T2	1		T3	9
auto[StInit]	4497	1			T1	4		T2	2		T3	27
auto[StCreatorRootKey]	3027	1			T1	5		T2	2		T4	2
auto[StOwnerIntKey]	2736	1			T1	2		T2	2		T4	4
auto[StOwnerKey]	2368	1			T1	5		T2	2		T4	2
auto[StDisabled]	7823	1			T1	15		T2	7		T13	12
auto[StInvalid]	1047	1			T17	11		T39	20		T23	23

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	168	112	40.00	168

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	339	1			T1	1		T3	1		T17	3
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	126	1			T1	1		T3	1		T18	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	73	1			T176	1		T103	1		T46	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	72	1			T46	1		T29	1		T60	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	69	1			T41	1		T6	1		T168	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	220	1			T102	1		T6	4		T45	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	26	1			T17	1		T199	2		T200	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	291	1			T3	1		T17	1		T27	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	113	1			T4	1		T6	2		T112	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	70	1			T13	1		T6	2		T112	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	64	1			T41	1		T96	1		T6	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	55	1			T4	1		T40	1		T141	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	205	1			T109	1		T6	4		T103	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	38	1			T39	1		T23	1		T199	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	283	1			T1	1		T17	1		T28	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	120	1			T3	1		T40	1		T23	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	68	1			T106	1		T109	1		T6	3
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	68	1			T13	1		T41	2		T6	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	60	1			T110	1		T43	1		T201	2
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	225	1			T1	3		T35	1		T89	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	38	1			T23	1		T199	3		T202	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	300	1			T3	1		T17	1		T27	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	119	1			T3	2		T89	1		T110	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	90	1			T41	1		T43	2		T201	2
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	75	1			T102	1		T108	1		T6	3
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	55	1			T27	1		T106	1		T62	3
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	214	1			T35	1		T108	1		T110	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	37	1			T39	2		T23	1		T203	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	72	1			T17	1		T6	6		T23	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	146	1			T18	1		T39	1		T6	4
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	98	1			T1	1		T30	1		T176	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	68	1			T4	1		T6	2		T56	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	63	1			T6	3		T46	1		T168	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	218	1			T13	2		T89	1		T106	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	35	1			T17	2		T23	1		T199	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	75	1			T6	2		T46	2		T60	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	138	1			T3	3		T6	2		T46	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	75	1			T35	1		T111	1		T6	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	66	1			T106	1		T109	1		T6	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	70	1			T6	3		T43	1		T201	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	206	1			T6	6		T130	1		T60	2
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	34	1			T23	1		T203	1		T204	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	90	1			T17	1		T6	6		T23	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	134	1			T3	1		T17	1		T41	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	83	1			T17	1		T122	1		T106	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	56	1			T13	1		T106	1		T176	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	50	1			T109	1		T6	2		T47	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	226	1			T13	1		T96	1		T6	5
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	33	1			T39	1		T23	1		T199	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	75	1			T17	2		T6	3		T43	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	120	1			T3	1		T13	1		T17	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	82	1			T27	1		T46	1		T94	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	69	1			T41	1		T43	2		T201	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	74	1			T13	1		T6	2		T7	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	227	1			T1	1		T41	1		T27	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	34	1			T17	1		T39	1		T205	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	259	1			T1	1		T106	1		T110	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	88	1			T3	1		T111	1		T60	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	63	1			T110	1		T60	1		T81	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	69	1			T17	1		T168	1		T24	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	48	1			T40	1		T6	2		T112	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	193	1			T1	1		T41	1		T96	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	32	1			T39	1		T23	2		T200	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	482	1			T17	2		T41	1		T27	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	157	1			T3	3		T27	1		T106	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	96	1			T2	1		T15	1		T122	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	108	1			T17	1		T88	1		T107	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	99	1			T2	1		T88	1		T206	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	270	1			T1	1		T2	3		T15	3
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	22	1			T203	1		T199	2		T205	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	406	1			T3	2		T17	1		T41	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	129	1			T3	1		T39	2		T176	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	91	1			T18	1		T41	1		T108	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	93	1			T4	1		T13	1		T108	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	87	1			T1	1		T96	1		T130	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	264	1			T1	1		T41	1		T106	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	28	1			T39	1		T203	1		T199	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	404	1			T1	1		T3	1		T17	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	154	1			T3	1		T18	1		T27	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	103	1			T6	1		T175	1		T129	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	109	1			T14	1		T40	1		T6	4
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	76	1			T41	1		T96	1		T6	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	250	1			T14	1		T106	2		T96	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	32	1			T199	1		T200	3		T207	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	64	1			T6	3		T23	1		T60	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	130	1			T3	1		T106	1		T110	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	69	1			T1	1		T4	1		T176	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	55	1			T43	2		T201	1		T157	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	45	1			T13	1		T41	1		T6	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	191	1			T41	1		T106	1		T6	6
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	26	1			T39	1		T199	1		T200	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	66	1			T17	2		T6	3		T60	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	141	1			T2	1		T13	1		T15	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	111	1			T17	1		T88	1		T41	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	93	1			T2	1		T15	1		T111	3
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	80	1			T1	1		T4	1		T15	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	304	1			T1	2		T2	1		T15	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	34	1			T23	2		T203	1		T200	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	66	1			T17	2		T6	4		T23	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	148	1			T13	1		T27	1		T6	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	98	1			T122	1		T6	3		T136	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	101	1			T136	1		T43	1		T84	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	86	1			T6	1		T136	1		T24	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	301	1			T13	2		T27	2		T96	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	30	1			T17	1		T39	1		T23	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	48	1			T6	2		T60	1		T43	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	137	1			T14	1		T6	1		T175	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	88	1			T14	1		T18	1		T122	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	91	1			T96	1		T6	1		T176	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	95	1			T14	1		T102	1		T6	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	280	1			T13	1		T14	3		T110	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	21	1			T205	2		T200	1		T202	1

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	203	1			T41	1		T6	1		T176	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	722	1			T1	2		T3	2		T17	4
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	176	1			T4	1		T13	1		T41	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	660	1			T3	1		T4	1		T17	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	181	1			T41	2		T106	1		T109	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	681	1			T1	4		T3	1		T13	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	209	1			T41	1		T102	1		T106	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	681	1			T3	3		T17	1		T35	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	212	1			T1	1		T4	1		T6	3
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	488	1			T13	2		T17	3		T18	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	206	1			T35	1		T106	1		T109	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	458	1			T3	3		T6	10		T23	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	176	1			T17	1		T122	1		T106	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	496	1			T3	1		T13	2		T17	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	217	1			T13	1		T41	1		T27	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	464	1			T1	1		T3	1		T13	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	158	1			T17	1		T40	1		T110	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	594	1			T1	2		T3	1		T41	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	282	1			T2	2		T15	1		T17	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	952	1			T1	1		T2	3		T3	3
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	261	1			T1	1		T4	1		T13	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	837	1			T1	1		T3	3		T17	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	272	1			T14	1		T41	1		T96	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	856	1			T1	1		T3	2		T14	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	153	1			T1	1		T4	1		T13	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	427	1			T3	1		T41	1		T106	2
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	271	1			T1	1		T2	1		T4	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	558	1			T1	2		T2	2		T13	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	272	1			T122	1		T6	4		T136	3
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	558	1			T13	3		T17	3		T27	3
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	252	1			T14	2		T18	1		T122	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	508	1			T13	1		T14	4		T110	1