Unified Coverage Report :: Group Instance : attest_sw_binding_3

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

31660

1

T1

41

T2

20

T3

41

auto[1]

307

1

T41

9

T106

11

T110

7

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	31670	1			T1	41		T2	20		T3	41
auto[134217728:268435455]	10	1			T106	1		T266	1		T324	1
auto[268435456:402653183]	11	1			T110	1		T87	1		T143	1
auto[402653184:536870911]	14	1			T41	1		T110	2		T157	1
auto[536870912:671088639]	6	1			T405	1		T295	1		T314	1
auto[671088640:805306367]	8	1			T106	1		T266	1		T147	1
auto[805306368:939524095]	10	1			T87	1		T247	1		T270	1
auto[939524096:1073741823]	10	1			T106	1		T87	1		T143	2
auto[1073741824:1207959551]	10	1			T41	1		T157	1		T144	1
auto[1207959552:1342177279]	10	1			T266	1		T146	2		T148	1
auto[1342177280:1476395007]	4	1			T143	1		T353	1		T406	1
auto[1476395008:1610612735]	14	1			T106	1		T157	1		T143	1
auto[1610612736:1744830463]	13	1			T41	1		T143	1		T144	1
auto[1744830464:1879048191]	12	1			T143	1		T146	1		T147	2
auto[1879048192:2013265919]	11	1			T157	1		T144	2		T247	1
auto[2013265920:2147483647]	6	1			T143	1		T266	1		T148	1
auto[2147483648:2281701375]	17	1			T106	1		T110	1		T266	2
auto[2281701376:2415919103]	8	1			T157	1		T143	1		T266	1
auto[2415919104:2550136831]	6	1			T143	1		T144	1		T247	1
auto[2550136832:2684354559]	7	1			T270	1		T147	1		T294	1
auto[2684354560:2818572287]	8	1			T106	1		T266	1		T247	1
auto[2818572288:2952790015]	10	1			T41	1		T110	1		T266	1
auto[2952790016:3087007743]	9	1			T110	2		T143	1		T247	1
auto[3087007744:3221225471]	9	1			T144	1		T270	1		T148	1
auto[3221225472:3355443199]	10	1			T41	2		T106	1		T157	1
auto[3355443200:3489660927]	9	1			T41	1		T106	1		T407	1
auto[3489660928:3623878655]	5	1			T87	1		T353	1		T406	1
auto[3623878656:3758096383]	8	1			T147	1		T324	1		T342	1
auto[3758096384:3892314111]	9	1			T143	3		T270	1		T342	1
auto[3892314112:4026531839]	15	1			T41	1		T106	1		T87	1
auto[4026531840:4160749567]	10	1			T106	1		T247	2		T310	1
auto[4160749568:4294967295]	8	1			T41	1		T146	1		T270	2

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	31	33	51.56	31

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Uncovered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[134217728:268435455] - auto[4160749568:4294967295]]	[auto[0]]	--	--	31

Covered bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	31660	1			T1	41		T2	20		T3	41
auto[0:134217727]	auto[1]	10	1			T106	1		T157	1		T144	1
auto[134217728:268435455]	auto[1]	10	1			T106	1		T266	1		T324	1
auto[268435456:402653183]	auto[1]	11	1			T110	1		T87	1		T143	1
auto[402653184:536870911]	auto[1]	14	1			T41	1		T110	2		T157	1
auto[536870912:671088639]	auto[1]	6	1			T405	1		T295	1		T314	1
auto[671088640:805306367]	auto[1]	8	1			T106	1		T266	1		T147	1
auto[805306368:939524095]	auto[1]	10	1			T87	1		T247	1		T270	1
auto[939524096:1073741823]	auto[1]	10	1			T106	1		T87	1		T143	2
auto[1073741824:1207959551]	auto[1]	10	1			T41	1		T157	1		T144	1
auto[1207959552:1342177279]	auto[1]	10	1			T266	1		T146	2		T148	1
auto[1342177280:1476395007]	auto[1]	4	1			T143	1		T353	1		T406	1
auto[1476395008:1610612735]	auto[1]	14	1			T106	1		T157	1		T143	1
auto[1610612736:1744830463]	auto[1]	13	1			T41	1		T143	1		T144	1
auto[1744830464:1879048191]	auto[1]	12	1			T143	1		T146	1		T147	2
auto[1879048192:2013265919]	auto[1]	11	1			T157	1		T144	2		T247	1
auto[2013265920:2147483647]	auto[1]	6	1			T143	1		T266	1		T148	1
auto[2147483648:2281701375]	auto[1]	17	1			T106	1		T110	1		T266	2
auto[2281701376:2415919103]	auto[1]	8	1			T157	1		T143	1		T266	1
auto[2415919104:2550136831]	auto[1]	6	1			T143	1		T144	1		T247	1
auto[2550136832:2684354559]	auto[1]	7	1			T270	1		T147	1		T294	1
auto[2684354560:2818572287]	auto[1]	8	1			T106	1		T266	1		T247	1
auto[2818572288:2952790015]	auto[1]	10	1			T41	1		T110	1		T266	1
auto[2952790016:3087007743]	auto[1]	9	1			T110	2		T143	1		T247	1
auto[3087007744:3221225471]	auto[1]	9	1			T144	1		T270	1		T148	1
auto[3221225472:3355443199]	auto[1]	10	1			T41	2		T106	1		T157	1
auto[3355443200:3489660927]	auto[1]	9	1			T41	1		T106	1		T407	1
auto[3489660928:3623878655]	auto[1]	5	1			T87	1		T353	1		T406	1
auto[3623878656:3758096383]	auto[1]	8	1			T147	1		T324	1		T342	1
auto[3758096384:3892314111]	auto[1]	9	1			T143	3		T270	1		T342	1
auto[3892314112:4026531839]	auto[1]	15	1			T41	1		T106	1		T87	1
auto[4026531840:4160749567]	auto[1]	10	1			T106	1		T247	2		T310	1
auto[4160749568:4294967295]	auto[1]	8	1			T41	1		T146	1		T270	2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1692

1

T1

4

T3

1

T17

8

auto[1]

1764

1

T1

1

T3

4

T13

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	94	1			T96	1		T110	1		T23	1
auto[134217728:268435455]	110	1			T17	1		T122	1		T6	1
auto[268435456:402653183]	126	1			T122	1		T108	1		T39	1
auto[402653184:536870911]	97	1			T7	1		T168	1		T60	1
auto[536870912:671088639]	111	1			T1	1		T27	1		T6	2
auto[671088640:805306367]	123	1			T1	1		T17	1		T106	1
auto[805306368:939524095]	110	1			T17	1		T96	1		T110	1
auto[939524096:1073741823]	106	1			T6	2		T30	1		T7	1
auto[1073741824:1207959551]	117	1			T17	1		T27	1		T103	1
auto[1207959552:1342177279]	120	1			T1	1		T3	1		T96	1
auto[1342177280:1476395007]	94	1			T106	1		T6	1		T24	1
auto[1476395008:1610612735]	117	1			T1	1		T3	1		T17	1
auto[1610612736:1744830463]	106	1			T17	1		T41	1		T28	1
auto[1744830464:1879048191]	108	1			T3	1		T17	1		T106	1
auto[1879048192:2013265919]	124	1			T13	1		T39	1		T111	1
auto[2013265920:2147483647]	102	1			T6	2		T43	1		T62	2
auto[2147483648:2281701375]	96	1			T17	1		T96	1		T6	1
auto[2281701376:2415919103]	115	1			T3	1		T6	5		T7	1
auto[2415919104:2550136831]	110	1			T17	1		T41	1		T96	1
auto[2550136832:2684354559]	96	1			T110	1		T24	1		T60	1
auto[2684354560:2818572287]	102	1			T6	2		T23	1		T94	1
auto[2818572288:2952790015]	114	1			T41	1		T39	1		T6	1
auto[2952790016:3087007743]	91	1			T106	2		T39	1		T6	3
auto[3087007744:3221225471]	101	1			T27	1		T176	1		T7	3
auto[3221225472:3355443199]	127	1			T3	1		T13	1		T29	1
auto[3355443200:3489660927]	96	1			T13	1		T27	1		T110	1
auto[3489660928:3623878655]	109	1			T17	1		T6	2		T60	1
auto[3623878656:3758096383]	106	1			T27	1		T7	2		T45	1
auto[3758096384:3892314111]	114	1			T41	1		T110	1		T6	3
auto[3892314112:4026531839]	103	1			T27	1		T106	1		T7	1
auto[4026531840:4160749567]	101	1			T1	1		T110	1		T6	2
auto[4160749568:4294967295]	110	1			T41	2		T6	2		T7	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	38	1			T23	1		T7	1		T43	1
auto[0:134217727]	auto[1]	56	1			T96	1		T110	1		T7	1
auto[134217728:268435455]	auto[0]	44	1			T17	1		T168	1		T408	1
auto[134217728:268435455]	auto[1]	66	1			T122	1		T6	1		T103	1
auto[268435456:402653183]	auto[0]	65	1			T39	1		T6	2		T23	1
auto[268435456:402653183]	auto[1]	61	1			T122	1		T108	1		T6	2
auto[402653184:536870911]	auto[0]	51	1			T7	1		T60	1		T141	1
auto[402653184:536870911]	auto[1]	46	1			T168	1		T398	1		T43	2
auto[536870912:671088639]	auto[0]	53	1			T1	1		T27	1		T7	1
auto[536870912:671088639]	auto[1]	58	1			T6	2		T103	1		T309	1
auto[671088640:805306367]	auto[0]	59	1			T17	1		T106	1		T6	1
auto[671088640:805306367]	auto[1]	64	1			T1	1		T6	2		T176	1
auto[805306368:939524095]	auto[0]	46	1			T17	1		T6	1		T60	1
auto[805306368:939524095]	auto[1]	64	1			T96	1		T110	1		T6	1
auto[939524096:1073741823]	auto[0]	50	1			T30	1		T7	1		T43	1
auto[939524096:1073741823]	auto[1]	56	1			T6	2		T24	1		T94	1
auto[1073741824:1207959551]	auto[0]	52	1			T17	1		T27	1		T103	1
auto[1073741824:1207959551]	auto[1]	65	1			T43	2		T87	2		T344	1
auto[1207959552:1342177279]	auto[0]	55	1			T1	1		T6	4		T23	1
auto[1207959552:1342177279]	auto[1]	65	1			T3	1		T96	1		T60	1
auto[1342177280:1476395007]	auto[0]	41	1			T6	1		T24	1		T43	2
auto[1342177280:1476395007]	auto[1]	53	1			T106	1		T43	2		T81	1
auto[1476395008:1610612735]	auto[0]	58	1			T1	1		T27	1		T6	2
auto[1476395008:1610612735]	auto[1]	59	1			T3	1		T17	1		T39	1
auto[1610612736:1744830463]	auto[0]	56	1			T17	1		T41	1		T111	1
auto[1610612736:1744830463]	auto[1]	50	1			T28	1		T43	1		T87	2
auto[1744830464:1879048191]	auto[0]	52	1			T3	1		T17	1		T106	1
auto[1744830464:1879048191]	auto[1]	56	1			T108	2		T103	1		T309	1
auto[1879048192:2013265919]	auto[0]	62	1			T39	1		T6	2		T43	3
auto[1879048192:2013265919]	auto[1]	62	1			T13	1		T111	1		T6	1
auto[2013265920:2147483647]	auto[0]	52	1			T199	2		T267	1		T249	1
auto[2013265920:2147483647]	auto[1]	50	1			T6	2		T43	1		T62	2
auto[2147483648:2281701375]	auto[0]	49	1			T23	1		T243	1		T210	1
auto[2147483648:2281701375]	auto[1]	47	1			T17	1		T96	1		T6	1
auto[2281701376:2415919103]	auto[0]	64	1			T6	4		T7	1		T60	1
auto[2281701376:2415919103]	auto[1]	51	1			T3	1		T6	1		T29	1
auto[2415919104:2550136831]	auto[0]	57	1			T17	1		T96	1		T6	1
auto[2415919104:2550136831]	auto[1]	53	1			T41	1		T23	1		T243	1
auto[2550136832:2684354559]	auto[0]	48	1			T24	1		T60	1		T43	1
auto[2550136832:2684354559]	auto[1]	48	1			T110	1		T43	1		T79	1
auto[2684354560:2818572287]	auto[0]	49	1			T6	2		T23	1		T79	2
auto[2684354560:2818572287]	auto[1]	53	1			T94	1		T241	1		T331	1
auto[2818572288:2952790015]	auto[0]	58	1			T41	1		T39	1		T23	1
auto[2818572288:2952790015]	auto[1]	56	1			T6	1		T60	1		T43	1
auto[2952790016:3087007743]	auto[0]	45	1			T106	1		T39	1		T6	2
auto[2952790016:3087007743]	auto[1]	46	1			T106	1		T6	1		T60	1
auto[3087007744:3221225471]	auto[0]	57	1			T176	1		T7	3		T141	1
auto[3087007744:3221225471]	auto[1]	44	1			T27	1		T43	3		T62	1
auto[3221225472:3355443199]	auto[0]	65	1			T29	1		T24	1		T210	1
auto[3221225472:3355443199]	auto[1]	62	1			T3	1		T13	1		T43	2
auto[3355443200:3489660927]	auto[0]	41	1			T6	2		T23	1		T50	1
auto[3355443200:3489660927]	auto[1]	55	1			T13	1		T27	1		T110	1
auto[3489660928:3623878655]	auto[0]	51	1			T17	1		T6	2		T50	1
auto[3489660928:3623878655]	auto[1]	58	1			T60	1		T43	1		T62	1
auto[3623878656:3758096383]	auto[0]	54	1			T7	2		T45	1		T24	1
auto[3623878656:3758096383]	auto[1]	52	1			T27	1		T60	1		T43	1
auto[3758096384:3892314111]	auto[0]	56	1			T110	1		T6	2		T7	1
auto[3758096384:3892314111]	auto[1]	58	1			T41	1		T6	1		T30	1
auto[3892314112:4026531839]	auto[0]	53	1			T27	1		T106	1		T7	1
auto[3892314112:4026531839]	auto[1]	50	1			T94	1		T87	1		T50	1
auto[4026531840:4160749567]	auto[0]	52	1			T1	1		T6	1		T23	1
auto[4026531840:4160749567]	auto[1]	49	1			T110	1		T6	1		T201	2
auto[4160749568:4294967295]	auto[0]	59	1			T41	1		T7	1		T90	1
auto[4160749568:4294967295]	auto[1]	51	1			T41	1		T6	2		T43	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1660

1

T1

4

T3

1

T17

7

auto[1]

1796

1

T1

1

T3

4

T13

3

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	107	1			T39	2		T6	1		T176	1
auto[134217728:268435455]	100	1			T1	1		T111	1		T6	2
auto[268435456:402653183]	106	1			T7	1		T29	2		T243	1
auto[402653184:536870911]	110	1			T3	2		T41	1		T122	1
auto[536870912:671088639]	131	1			T27	2		T96	2		T108	1
auto[671088640:805306367]	117	1			T41	1		T27	1		T60	2
auto[805306368:939524095]	125	1			T1	1		T17	1		T110	1
auto[939524096:1073741823]	111	1			T17	1		T28	1		T111	1
auto[1073741824:1207959551]	117	1			T41	1		T6	2		T7	1
auto[1207959552:1342177279]	98	1			T1	1		T3	1		T6	1
auto[1342177280:1476395007]	95	1			T39	1		T6	1		T7	2
auto[1476395008:1610612735]	90	1			T17	1		T110	1		T6	3
auto[1610612736:1744830463]	106	1			T13	1		T17	1		T41	1
auto[1744830464:1879048191]	114	1			T176	1		T29	1		T60	1
auto[1879048192:2013265919]	95	1			T1	1		T110	1		T6	1
auto[2013265920:2147483647]	109	1			T6	3		T60	2		T398	1
auto[2147483648:2281701375]	120	1			T3	1		T106	1		T6	4
auto[2281701376:2415919103]	95	1			T27	1		T23	1		T43	2
auto[2415919104:2550136831]	93	1			T1	1		T17	1		T122	1
auto[2550136832:2684354559]	101	1			T17	1		T41	1		T106	1
auto[2684354560:2818572287]	111	1			T106	1		T6	1		T23	1
auto[2818572288:2952790015]	102	1			T17	1		T39	1		T6	1
auto[2952790016:3087007743]	116	1			T41	1		T27	1		T6	3
auto[3087007744:3221225471]	100	1			T3	1		T39	1		T30	1
auto[3221225472:3355443199]	126	1			T96	1		T6	3		T23	1
auto[3355443200:3489660927]	114	1			T13	1		T27	1		T106	1
auto[3489660928:3623878655]	107	1			T13	1		T6	3		T23	1
auto[3623878656:3758096383]	124	1			T17	3		T106	1		T96	1
auto[3758096384:3892314111]	106	1			T27	1		T108	1		T176	1
auto[3892314112:4026531839]	103	1			T6	1		T23	1		T94	1
auto[4026531840:4160749567]	107	1			T7	1		T168	1		T24	1
auto[4160749568:4294967295]	100	1			T110	1		T6	4		T23	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	53	1			T39	2		T7	1		T8	1
auto[0:134217727]	auto[1]	54	1			T6	1		T176	1		T60	1
auto[134217728:268435455]	auto[0]	48	1			T6	1		T60	1		T243	1
auto[134217728:268435455]	auto[1]	52	1			T1	1		T111	1		T6	1
auto[268435456:402653183]	auto[0]	47	1			T7	1		T29	2		T94	1
auto[268435456:402653183]	auto[1]	59	1			T243	1		T43	1		T201	1
auto[402653184:536870911]	auto[0]	58	1			T41	1		T6	2		T7	1
auto[402653184:536870911]	auto[1]	52	1			T3	2		T122	1		T106	1
auto[536870912:671088639]	auto[0]	55	1			T27	2		T96	1		T6	1
auto[536870912:671088639]	auto[1]	76	1			T96	1		T108	1		T6	1
auto[671088640:805306367]	auto[0]	57	1			T41	1		T60	2		T50	1
auto[671088640:805306367]	auto[1]	60	1			T27	1		T43	2		T201	3
auto[805306368:939524095]	auto[0]	50	1			T1	1		T17	1		T6	1
auto[805306368:939524095]	auto[1]	75	1			T110	1		T398	1		T43	1
auto[939524096:1073741823]	auto[0]	58	1			T111	1		T6	1		T24	1
auto[939524096:1073741823]	auto[1]	53	1			T17	1		T28	1		T6	1
auto[1073741824:1207959551]	auto[0]	54	1			T41	1		T6	1		T7	1
auto[1073741824:1207959551]	auto[1]	63	1			T6	1		T43	2		T51	1
auto[1207959552:1342177279]	auto[0]	41	1			T1	1		T7	1		T201	2
auto[1207959552:1342177279]	auto[1]	57	1			T3	1		T6	1		T43	3
auto[1342177280:1476395007]	auto[0]	46	1			T6	1		T7	1		T210	1
auto[1342177280:1476395007]	auto[1]	49	1			T39	1		T7	1		T45	1
auto[1476395008:1610612735]	auto[0]	52	1			T17	1		T6	1		T103	2
auto[1476395008:1610612735]	auto[1]	38	1			T110	1		T6	2		T43	1
auto[1610612736:1744830463]	auto[0]	56	1			T17	1		T6	3		T43	1
auto[1610612736:1744830463]	auto[1]	50	1			T13	1		T41	1		T110	2
auto[1744830464:1879048191]	auto[0]	47	1			T29	1		T60	1		T43	1
auto[1744830464:1879048191]	auto[1]	67	1			T176	1		T50	1		T260	1
auto[1879048192:2013265919]	auto[0]	46	1			T1	1		T103	1		T7	1
auto[1879048192:2013265919]	auto[1]	49	1			T110	1		T6	1		T30	1
auto[2013265920:2147483647]	auto[0]	46	1			T43	2		T210	1		T157	1
auto[2013265920:2147483647]	auto[1]	63	1			T6	3		T60	2		T398	1
auto[2147483648:2281701375]	auto[0]	56	1			T3	1		T106	1		T6	3
auto[2147483648:2281701375]	auto[1]	64	1			T6	1		T43	2		T87	1
auto[2281701376:2415919103]	auto[0]	40	1			T43	1		T201	1		T93	1
auto[2281701376:2415919103]	auto[1]	55	1			T27	1		T23	1		T43	1
auto[2415919104:2550136831]	auto[0]	45	1			T1	1		T17	1		T6	1
auto[2415919104:2550136831]	auto[1]	48	1			T122	1		T60	1		T43	1
auto[2550136832:2684354559]	auto[0]	45	1			T17	1		T106	1		T103	1
auto[2550136832:2684354559]	auto[1]	56	1			T41	1		T108	1		T6	1
auto[2684354560:2818572287]	auto[0]	58	1			T6	1		T23	1		T141	2
auto[2684354560:2818572287]	auto[1]	53	1			T106	1		T60	1		T43	2
auto[2818572288:2952790015]	auto[0]	58	1			T17	1		T39	1		T7	1
auto[2818572288:2952790015]	auto[1]	44	1			T6	1		T141	1		T43	1
auto[2952790016:3087007743]	auto[0]	60	1			T41	1		T27	1		T6	3
auto[2952790016:3087007743]	auto[1]	56	1			T43	1		T79	1		T87	1
auto[3087007744:3221225471]	auto[0]	53	1			T39	1		T45	1		T243	1
auto[3087007744:3221225471]	auto[1]	47	1			T3	1		T30	1		T103	1
auto[3221225472:3355443199]	auto[0]	64	1			T6	3		T23	1		T7	1
auto[3221225472:3355443199]	auto[1]	62	1			T96	1		T46	1		T43	2
auto[3355443200:3489660927]	auto[0]	55	1			T106	1		T96	1		T6	2
auto[3355443200:3489660927]	auto[1]	59	1			T13	1		T27	1		T168	1
auto[3489660928:3623878655]	auto[0]	56	1			T23	1		T7	1		T45	1
auto[3489660928:3623878655]	auto[1]	51	1			T13	1		T6	3		T60	1
auto[3623878656:3758096383]	auto[0]	67	1			T17	1		T106	1		T30	1
auto[3623878656:3758096383]	auto[1]	57	1			T17	2		T96	1		T6	1
auto[3758096384:3892314111]	auto[0]	41	1			T27	1		T79	1		T409	1
auto[3758096384:3892314111]	auto[1]	65	1			T108	1		T176	1		T43	2
auto[3892314112:4026531839]	auto[0]	48	1			T6	1		T23	1		T94	1
auto[3892314112:4026531839]	auto[1]	55	1			T43	2		T87	1		T201	1
auto[4026531840:4160749567]	auto[0]	51	1			T7	1		T24	1		T79	1
auto[4026531840:4160749567]	auto[1]	56	1			T168	1		T60	1		T62	1
auto[4160749568:4294967295]	auto[0]	49	1			T110	1		T6	3		T23	1
auto[4160749568:4294967295]	auto[1]	51	1			T6	1		T79	2		T201	2

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1653

1

T1

4

T3

2

T13

1

auto[1]

1804

1

T1

1

T3

3

T13

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	93	1			T17	1		T39	1		T24	1
auto[134217728:268435455]	119	1			T3	1		T17	1		T28	1
auto[268435456:402653183]	99	1			T6	2		T23	1		T7	2
auto[402653184:536870911]	121	1			T6	2		T23	2		T176	1
auto[536870912:671088639]	122	1			T39	1		T6	3		T7	1
auto[671088640:805306367]	109	1			T6	2		T24	1		T60	2
auto[805306368:939524095]	100	1			T17	1		T27	1		T6	1
auto[939524096:1073741823]	103	1			T13	1		T41	1		T96	1
auto[1073741824:1207959551]	107	1			T27	1		T106	1		T110	2
auto[1207959552:1342177279]	110	1			T7	1		T60	1		T43	1
auto[1342177280:1476395007]	99	1			T3	1		T106	1		T6	3
auto[1476395008:1610612735]	99	1			T106	1		T39	1		T6	2
auto[1610612736:1744830463]	95	1			T1	1		T27	1		T106	1
auto[1744830464:1879048191]	117	1			T1	1		T3	1		T13	1
auto[1879048192:2013265919]	119	1			T1	1		T17	1		T110	1
auto[2013265920:2147483647]	110	1			T41	1		T27	1		T111	2
auto[2147483648:2281701375]	124	1			T17	1		T41	1		T27	1
auto[2281701376:2415919103]	104	1			T13	1		T106	1		T96	1
auto[2415919104:2550136831]	111	1			T3	1		T6	3		T176	1
auto[2550136832:2684354559]	118	1			T17	2		T6	3		T29	1
auto[2684354560:2818572287]	100	1			T39	1		T110	1		T103	1
auto[2818572288:2952790015]	106	1			T17	1		T27	1		T111	1
auto[2952790016:3087007743]	114	1			T6	1		T103	1		T43	3
auto[3087007744:3221225471]	113	1			T17	2		T108	1		T6	2
auto[3221225472:3355443199]	91	1			T7	1		T29	1		T141	1
auto[3355443200:3489660927]	111	1			T41	1		T6	1		T45	1
auto[3489660928:3623878655]	93	1			T1	1		T6	2		T23	1
auto[3623878656:3758096383]	119	1			T1	1		T108	1		T60	1
auto[3758096384:3892314111]	108	1			T96	1		T6	1		T7	1
auto[3892314112:4026531839]	112	1			T41	1		T106	1		T96	1
auto[4026531840:4160749567]	109	1			T3	1		T122	1		T96	1
auto[4160749568:4294967295]	102	1			T122	1		T46	1		T60	1

---

Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	64	0	64	100.00

Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins

sw_input_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	auto[0]	52	1			T24	1		T79	1		T240	1
auto[0:134217727]	auto[1]	41	1			T17	1		T39	1		T94	1
auto[134217728:268435455]	auto[0]	52	1			T3	1		T17	1		T6	1
auto[134217728:268435455]	auto[1]	67	1			T28	1		T110	1		T6	2
auto[268435456:402653183]	auto[0]	49	1			T23	1		T7	1		T210	1
auto[268435456:402653183]	auto[1]	50	1			T6	2		T7	1		T43	2
auto[402653184:536870911]	auto[0]	64	1			T6	2		T23	2		T44	1
auto[402653184:536870911]	auto[1]	57	1			T176	1		T60	1		T43	4
auto[536870912:671088639]	auto[0]	55	1			T39	1		T6	1		T7	1
auto[536870912:671088639]	auto[1]	67	1			T6	2		T243	1		T43	1
auto[671088640:805306367]	auto[0]	52	1			T6	1		T24	1		T60	2
auto[671088640:805306367]	auto[1]	57	1			T6	1		T243	1		T86	1
auto[805306368:939524095]	auto[0]	52	1			T17	1		T27	1		T6	1
auto[805306368:939524095]	auto[1]	48	1			T30	1		T60	1		T43	1
auto[939524096:1073741823]	auto[0]	50	1			T6	2		T243	1		T86	1
auto[939524096:1073741823]	auto[1]	53	1			T13	1		T41	1		T96	1
auto[1073741824:1207959551]	auto[0]	56	1			T27	1		T106	1		T6	2
auto[1073741824:1207959551]	auto[1]	51	1			T110	2		T6	1		T87	1
auto[1207959552:1342177279]	auto[0]	53	1			T7	1		T201	1		T209	1
auto[1207959552:1342177279]	auto[1]	57	1			T60	1		T43	1		T201	1
auto[1342177280:1476395007]	auto[0]	54	1			T3	1		T6	2		T7	1
auto[1342177280:1476395007]	auto[1]	45	1			T106	1		T6	1		T83	1
auto[1476395008:1610612735]	auto[0]	43	1			T106	1		T39	1		T6	1
auto[1476395008:1610612735]	auto[1]	56	1			T6	1		T43	1		T309	1
auto[1610612736:1744830463]	auto[0]	38	1			T1	1		T24	1		T43	1
auto[1610612736:1744830463]	auto[1]	57	1			T27	1		T106	1		T6	2
auto[1744830464:1879048191]	auto[0]	57	1			T1	1		T13	1		T27	1
auto[1744830464:1879048191]	auto[1]	60	1			T3	1		T41	1		T94	1
auto[1879048192:2013265919]	auto[0]	60	1			T1	1		T17	1		T6	1
auto[1879048192:2013265919]	auto[1]	59	1			T110	1		T103	1		T243	1
auto[2013265920:2147483647]	auto[0]	48	1			T111	2		T6	2		T30	1
auto[2013265920:2147483647]	auto[1]	62	1			T41	1		T27	1		T45	1
auto[2147483648:2281701375]	auto[0]	56	1			T17	1		T41	1		T6	1
auto[2147483648:2281701375]	auto[1]	68	1			T27	1		T6	1		T94	1
auto[2281701376:2415919103]	auto[0]	55	1			T106	1		T96	1		T7	2
auto[2281701376:2415919103]	auto[1]	49	1			T13	1		T141	1		T55	1
auto[2415919104:2550136831]	auto[0]	46	1			T6	1		T29	1		T141	1
auto[2415919104:2550136831]	auto[1]	65	1			T3	1		T6	2		T176	1
auto[2550136832:2684354559]	auto[0]	66	1			T17	2		T6	2		T43	2
auto[2550136832:2684354559]	auto[1]	52	1			T6	1		T29	1		T43	1
auto[2684354560:2818572287]	auto[0]	50	1			T39	1		T103	1		T7	1
auto[2684354560:2818572287]	auto[1]	50	1			T110	1		T43	1		T62	1
auto[2818572288:2952790015]	auto[0]	52	1			T17	1		T210	1		T209	1
auto[2818572288:2952790015]	auto[1]	54	1			T27	1		T111	1		T6	1
auto[2952790016:3087007743]	auto[0]	49	1			T6	1		T210	1		T25	1
auto[2952790016:3087007743]	auto[1]	65	1			T103	1		T43	3		T50	1
auto[3087007744:3221225471]	auto[0]	59	1			T17	1		T6	1		T23	1
auto[3087007744:3221225471]	auto[1]	54	1			T17	1		T108	1		T6	1
auto[3221225472:3355443199]	auto[0]	45	1			T7	1		T29	1		T43	1
auto[3221225472:3355443199]	auto[1]	46	1			T141	1		T43	1		T50	1
auto[3355443200:3489660927]	auto[0]	51	1			T41	1		T6	1		T45	1
auto[3355443200:3489660927]	auto[1]	60	1			T24	1		T43	2		T267	1
auto[3489660928:3623878655]	auto[0]	55	1			T1	1		T6	1		T23	1
auto[3489660928:3623878655]	auto[1]	38	1			T6	1		T141	1		T209	1
auto[3623878656:3758096383]	auto[0]	50	1			T243	1		T83	1		T171	2
auto[3623878656:3758096383]	auto[1]	69	1			T1	1		T108	1		T60	1
auto[3758096384:3892314111]	auto[0]	41	1			T6	1		T7	1		T201	1
auto[3758096384:3892314111]	auto[1]	67	1			T96	1		T168	1		T60	1
auto[3892314112:4026531839]	auto[0]	47	1			T41	1		T106	1		T6	2
auto[3892314112:4026531839]	auto[1]	65	1			T96	1		T6	2		T7	1
auto[4026531840:4160749567]	auto[0]	47	1			T39	1		T6	2		T243	1
auto[4026531840:4160749567]	auto[1]	62	1			T3	1		T122	1		T96	1
auto[4160749568:4294967295]	auto[0]	49	1			T60	1		T81	1		T210	1
auto[4160749568:4294967295]	auto[1]	53	1			T122	1		T46	1		T43	1

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1653

1

T1

3

T3

2

T13

1

auto[1]

1803

1

T1

2

T3

3

T13

2

---

Summary for Variable sw_input_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	32	0	32	100.00

Automatically Generated Bins for sw_input_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0:134217727]	124	1			T17	1		T27	1		T39	1
auto[134217728:268435455]	115	1			T3	1		T108	1		T110	1
auto[268435456:402653183]	114	1			T6	6		T7	1		T60	1
auto[402653184:536870911]	92	1			T108	1		T6	1		T23	1
auto[536870912:671088639]	123	1			T1	1		T122	1		T96	1
auto[671088640:805306367]	110	1			T1	1		T17	2		T106	1
auto[805306368:939524095]	109	1			T41	1		T39	1		T111	1
auto[939524096:1073741823]	96	1			T106	1		T6	1		T23	1
auto[1073741824:1207959551]	101	1			T110	1		T7	1		T24	1
auto[1207959552:1342177279]	111	1			T17	1		T41	1		T106	1
auto[1342177280:1476395007]	105	1			T108	1		T111	1		T6	2
auto[1476395008:1610612735]	112	1			T17	2		T96	1		T6	1
auto[1610612736:1744830463]	118	1			T96	1		T6	2		T45	1
auto[1744830464:1879048191]	119	1			T106	1		T6	1		T30	1
auto[1879048192:2013265919]	104	1			T41	1		T110	1		T6	4
auto[2013265920:2147483647]	107	1			T3	2		T27	2		T6	2
auto[2147483648:2281701375]	95	1			T6	1		T94	1		T43	2
auto[2281701376:2415919103]	102	1			T3	1		T41	1		T110	1
auto[2415919104:2550136831]	105	1			T3	1		T13	1		T27	1
auto[2550136832:2684354559]	123	1			T27	1		T6	1		T43	5
auto[2684354560:2818572287]	110	1			T122	1		T27	1		T96	1
auto[2818572288:2952790015]	111	1			T6	2		T23	1		T103	1
auto[2952790016:3087007743]	106	1			T13	1		T6	1		T103	1
auto[3087007744:3221225471]	109	1			T13	1		T27	1		T106	2
auto[3221225472:3355443199]	89	1			T39	1		T6	2		T23	1
auto[3355443200:3489660927]	106	1			T17	1		T41	1		T28	1
auto[3489660928:3623878655]	98	1			T1	1		T17	1		T46	1
auto[3623878656:3758096383]	113	1			T6	3		T23	1		T7	1
auto[3758096384:3892314111]	104	1			T17	1		T41	1		T6	4
auto[3892314112:4026531839]	118	1			T17	1		T6	1		T103	1
auto[4026531840:4160749567]	100	1			T6	1		T168	1		T60	1
auto[4160749568:4294967295]	107	1			T1	2		T6	3		T29	1