dashboard | hierarchy | modlist | groups | tests | asserts

Summary for Variable regwen_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for regwen_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 3055 1 T1 5 T3 5 T13 3
auto[1] 275 1 T41 6 T106 8 T110 4



Summary for Variable sw_input_cp

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 32 0 32 100.00


Automatically Generated Bins for sw_input_cp

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] 110 1 T41 1 T86 1 T50 1
auto[134217728:268435455] 103 1 T39 1 T6 1 T30 1
auto[268435456:402653183] 102 1 T17 1 T41 1 T96 1
auto[402653184:536870911] 104 1 T3 1 T13 1 T106 1
auto[536870912:671088639] 94 1 T1 1 T41 1 T122 1
auto[671088640:805306367] 100 1 T41 1 T27 1 T6 1
auto[805306368:939524095] 96 1 T39 1 T6 1 T23 1
auto[939524096:1073741823] 114 1 T3 1 T27 1 T106 1
auto[1073741824:1207959551] 91 1 T41 1 T6 1 T243 1
auto[1207959552:1342177279] 115 1 T17 1 T122 1 T106 1
auto[1342177280:1476395007] 104 1 T110 1 T6 1 T30 1
auto[1476395008:1610612735] 108 1 T108 1 T110 1 T243 2
auto[1610612736:1744830463] 125 1 T106 1 T96 1 T110 1
auto[1744830464:1879048191] 95 1 T3 1 T17 1 T41 1
auto[1879048192:2013265919] 98 1 T106 2 T6 1 T23 1
auto[2013265920:2147483647] 100 1 T41 1 T110 1 T6 2
auto[2147483648:2281701375] 120 1 T3 1 T17 1 T27 1
auto[2281701376:2415919103] 89 1 T17 1 T41 1 T27 1
auto[2415919104:2550136831] 91 1 T41 1 T106 1 T23 1
auto[2550136832:2684354559] 115 1 T13 1 T17 2 T6 3
auto[2684354560:2818572287] 112 1 T1 1 T41 1 T39 1
auto[2818572288:2952790015] 105 1 T17 1 T41 1 T6 3
auto[2952790016:3087007743] 108 1 T28 1 T6 1 T7 1
auto[3087007744:3221225471] 82 1 T17 1 T110 1 T6 1
auto[3221225472:3355443199] 113 1 T1 1 T41 1 T27 1
auto[3355443200:3489660927] 99 1 T1 1 T13 1 T96 1
auto[3489660928:3623878655] 100 1 T108 1 T6 2 T43 3
auto[3623878656:3758096383] 109 1 T3 1 T106 2 T96 1
auto[3758096384:3892314111] 121 1 T27 1 T39 1 T6 1
auto[3892314112:4026531839] 96 1 T106 1 T6 2 T60 1
auto[4026531840:4160749567] 93 1 T1 1 T110 1 T46 1
auto[4160749568:4294967295] 118 1 T17 1 T6 1 T24 1



Summary for Cross sw_input_x_regwen_cr

Samples crossed: sw_input_cp regwen_cp
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
Automatically Generated Cross Bins 64 0 64 100.00


Automatically Generated Cross Bins for sw_input_x_regwen_cr

Bins
sw_input_cpregwen_cpCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0:134217727] auto[0] 101 1 T86 1 T50 1 T25 1
auto[0:134217727] auto[1] 9 1 T41 1 T270 1 T233 1
auto[134217728:268435455] auto[0] 95 1 T39 1 T6 1 T30 1
auto[134217728:268435455] auto[1] 8 1 T247 1 T147 1 T324 1
auto[268435456:402653183] auto[0] 94 1 T17 1 T41 1 T96 1
auto[268435456:402653183] auto[1] 8 1 T146 2 T147 1 T148 1
auto[402653184:536870911] auto[0] 100 1 T3 1 T13 1 T110 1
auto[402653184:536870911] auto[1] 4 1 T106 1 T357 1 T411 1
auto[536870912:671088639] auto[0] 88 1 T1 1 T41 1 T122 1
auto[536870912:671088639] auto[1] 6 1 T148 1 T411 1 T418 2
auto[671088640:805306367] auto[0] 95 1 T41 1 T27 1 T6 1
auto[671088640:805306367] auto[1] 5 1 T143 1 T148 1 T294 1
auto[805306368:939524095] auto[0] 83 1 T39 1 T6 1 T23 1
auto[805306368:939524095] auto[1] 13 1 T143 1 T247 1 T147 1
auto[939524096:1073741823] auto[0] 104 1 T3 1 T27 1 T23 2
auto[939524096:1073741823] auto[1] 10 1 T106 1 T157 2 T266 1
auto[1073741824:1207959551] auto[0] 85 1 T6 1 T243 1 T209 1
auto[1073741824:1207959551] auto[1] 6 1 T41 1 T143 1 T266 1
auto[1207959552:1342177279] auto[0] 108 1 T17 1 T122 1 T106 1
auto[1207959552:1342177279] auto[1] 7 1 T143 1 T144 1 T367 1
auto[1342177280:1476395007] auto[0] 95 1 T6 1 T30 1 T168 1
auto[1342177280:1476395007] auto[1] 9 1 T110 1 T144 1 T147 1
auto[1476395008:1610612735] auto[0] 95 1 T108 1 T110 1 T243 2
auto[1476395008:1610612735] auto[1] 13 1 T143 2 T146 1 T270 1
auto[1610612736:1744830463] auto[0] 113 1 T106 1 T96 1 T110 1
auto[1610612736:1744830463] auto[1] 12 1 T310 1 T412 1 T407 2
auto[1744830464:1879048191] auto[0] 89 1 T3 1 T17 1 T27 1
auto[1744830464:1879048191] auto[1] 6 1 T41 1 T143 1 T144 1
auto[1879048192:2013265919] auto[0] 86 1 T106 1 T6 1 T23 1
auto[1879048192:2013265919] auto[1] 12 1 T106 1 T146 1 T324 1
auto[2013265920:2147483647] auto[0] 92 1 T110 1 T6 2 T24 1
auto[2013265920:2147483647] auto[1] 8 1 T41 1 T146 1 T147 1
auto[2147483648:2281701375] auto[0] 113 1 T3 1 T17 1 T27 1
auto[2147483648:2281701375] auto[1] 7 1 T157 1 T247 2 T342 1
auto[2281701376:2415919103] auto[0] 78 1 T17 1 T41 1 T27 1
auto[2281701376:2415919103] auto[1] 11 1 T106 2 T87 1 T247 1
auto[2415919104:2550136831] auto[0] 86 1 T106 1 T23 1 T176 1
auto[2415919104:2550136831] auto[1] 5 1 T41 1 T413 1 T419 1
auto[2550136832:2684354559] auto[0] 106 1 T13 1 T17 2 T6 3
auto[2550136832:2684354559] auto[1] 9 1 T87 1 T146 1 T310 2
auto[2684354560:2818572287] auto[0] 107 1 T1 1 T41 1 T39 1
auto[2684354560:2818572287] auto[1] 5 1 T270 1 T411 1 T413 1
auto[2818572288:2952790015] auto[0] 98 1 T17 1 T6 3 T45 1
auto[2818572288:2952790015] auto[1] 7 1 T41 1 T411 1 T295 1
auto[2952790016:3087007743] auto[0] 97 1 T28 1 T6 1 T7 1
auto[2952790016:3087007743] auto[1] 11 1 T342 1 T412 1 T386 1
auto[3087007744:3221225471] auto[0] 74 1 T17 1 T6 1 T103 1
auto[3087007744:3221225471] auto[1] 8 1 T110 1 T247 2 T357 1
auto[3221225472:3355443199] auto[0] 102 1 T1 1 T41 1 T27 1
auto[3221225472:3355443199] auto[1] 11 1 T106 1 T266 1 T247 1
auto[3355443200:3489660927] auto[0] 88 1 T1 1 T13 1 T96 1
auto[3355443200:3489660927] auto[1] 11 1 T143 2 T266 1 T147 1
auto[3489660928:3623878655] auto[0] 91 1 T108 1 T6 2 T43 3
auto[3489660928:3623878655] auto[1] 9 1 T143 2 T247 1 T405 1
auto[3623878656:3758096383] auto[0] 98 1 T3 1 T96 1 T6 4
auto[3623878656:3758096383] auto[1] 11 1 T106 2 T110 1 T247 2
auto[3758096384:3892314111] auto[0] 115 1 T27 1 T39 1 T6 1
auto[3758096384:3892314111] auto[1] 6 1 T411 2 T420 1 T387 1
auto[3892314112:4026531839] auto[0] 88 1 T106 1 T6 2 T60 1
auto[3892314112:4026531839] auto[1] 8 1 T143 1 T247 1 T270 1
auto[4026531840:4160749567] auto[0] 83 1 T1 1 T46 1 T24 1
auto[4026531840:4160749567] auto[1] 10 1 T110 1 T157 1 T144 1
auto[4160749568:4294967295] auto[0] 108 1 T17 1 T6 1 T24 1
auto[4160749568:4294967295] auto[1] 10 1 T144 2 T411 1 T418 1

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%