Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.83 99.07 98.22 98.32 100.00 99.11 98.41 91.66


Total test records in report: 1076
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T1008 /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.1002480661 Mar 26 02:40:53 PM PDT 24 Mar 26 02:40:59 PM PDT 24 2631802844 ps
T1009 /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.926188768 Mar 26 02:40:50 PM PDT 24 Mar 26 02:40:51 PM PDT 24 26793131 ps
T1010 /workspace/coverage/cover_reg_top/44.keymgr_intr_test.586916436 Mar 26 02:41:10 PM PDT 24 Mar 26 02:41:12 PM PDT 24 32148862 ps
T1011 /workspace/coverage/cover_reg_top/4.keymgr_intr_test.2111168777 Mar 26 02:40:48 PM PDT 24 Mar 26 02:40:49 PM PDT 24 9824209 ps
T197 /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.513298789 Mar 26 02:40:55 PM PDT 24 Mar 26 02:41:03 PM PDT 24 362948460 ps
T1012 /workspace/coverage/cover_reg_top/11.keymgr_intr_test.1179316124 Mar 26 02:40:51 PM PDT 24 Mar 26 02:40:52 PM PDT 24 7321022 ps
T194 /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.1984970442 Mar 26 02:40:54 PM PDT 24 Mar 26 02:40:57 PM PDT 24 103605126 ps
T1013 /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.1607483990 Mar 26 02:40:48 PM PDT 24 Mar 26 02:40:49 PM PDT 24 20053039 ps
T1014 /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.266245632 Mar 26 02:40:56 PM PDT 24 Mar 26 02:40:58 PM PDT 24 35839190 ps
T190 /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.3736600810 Mar 26 02:40:31 PM PDT 24 Mar 26 02:40:37 PM PDT 24 654565159 ps
T1015 /workspace/coverage/cover_reg_top/48.keymgr_intr_test.2163363859 Mar 26 02:41:12 PM PDT 24 Mar 26 02:41:13 PM PDT 24 46221145 ps
T179 /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.1525957684 Mar 26 02:40:35 PM PDT 24 Mar 26 02:40:41 PM PDT 24 148108961 ps
T1016 /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.3358533639 Mar 26 02:40:46 PM PDT 24 Mar 26 02:40:48 PM PDT 24 34907298 ps
T1017 /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.600010390 Mar 26 02:40:34 PM PDT 24 Mar 26 02:40:36 PM PDT 24 57191843 ps
T1018 /workspace/coverage/cover_reg_top/43.keymgr_intr_test.208391815 Mar 26 02:41:12 PM PDT 24 Mar 26 02:41:13 PM PDT 24 98320703 ps
T1019 /workspace/coverage/cover_reg_top/41.keymgr_intr_test.1576178676 Mar 26 02:41:12 PM PDT 24 Mar 26 02:41:13 PM PDT 24 29228214 ps
T1020 /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.2140871204 Mar 26 02:40:47 PM PDT 24 Mar 26 02:41:02 PM PDT 24 1496932585 ps
T1021 /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.705403010 Mar 26 02:40:48 PM PDT 24 Mar 26 02:40:49 PM PDT 24 89643208 ps
T1022 /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.1255273335 Mar 26 02:40:45 PM PDT 24 Mar 26 02:40:47 PM PDT 24 172617943 ps
T1023 /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.2229852680 Mar 26 02:41:07 PM PDT 24 Mar 26 02:41:11 PM PDT 24 209744360 ps
T1024 /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.2886637585 Mar 26 02:40:33 PM PDT 24 Mar 26 02:40:41 PM PDT 24 483090604 ps
T1025 /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.946563896 Mar 26 02:40:52 PM PDT 24 Mar 26 02:41:00 PM PDT 24 1635355429 ps
T1026 /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.571653468 Mar 26 02:40:51 PM PDT 24 Mar 26 02:40:52 PM PDT 24 15097416 ps
T1027 /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.1721157578 Mar 26 02:40:36 PM PDT 24 Mar 26 02:40:41 PM PDT 24 383594832 ps
T1028 /workspace/coverage/cover_reg_top/29.keymgr_intr_test.717731278 Mar 26 02:41:12 PM PDT 24 Mar 26 02:41:13 PM PDT 24 37809896 ps
T1029 /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.3144305735 Mar 26 02:40:51 PM PDT 24 Mar 26 02:40:56 PM PDT 24 327163114 ps
T1030 /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.267996918 Mar 26 02:40:47 PM PDT 24 Mar 26 02:40:49 PM PDT 24 458311875 ps
T1031 /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.716646544 Mar 26 02:40:36 PM PDT 24 Mar 26 02:40:38 PM PDT 24 58151069 ps
T1032 /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.3575168958 Mar 26 02:40:35 PM PDT 24 Mar 26 02:40:40 PM PDT 24 265968312 ps
T1033 /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.433767355 Mar 26 02:40:48 PM PDT 24 Mar 26 02:40:49 PM PDT 24 39360306 ps
T1034 /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.3477176114 Mar 26 02:40:51 PM PDT 24 Mar 26 02:40:55 PM PDT 24 463811939 ps
T1035 /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.485332468 Mar 26 02:40:33 PM PDT 24 Mar 26 02:40:38 PM PDT 24 424465468 ps
T1036 /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.2109817956 Mar 26 02:40:48 PM PDT 24 Mar 26 02:40:57 PM PDT 24 1957863179 ps
T1037 /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.3352892648 Mar 26 02:40:46 PM PDT 24 Mar 26 02:40:48 PM PDT 24 475882416 ps
T1038 /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.3326054768 Mar 26 02:40:59 PM PDT 24 Mar 26 02:41:07 PM PDT 24 1421717406 ps
T1039 /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.375582058 Mar 26 02:41:13 PM PDT 24 Mar 26 02:41:14 PM PDT 24 10448496 ps
T1040 /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.2604527621 Mar 26 02:40:50 PM PDT 24 Mar 26 02:41:26 PM PDT 24 3505150417 ps
T1041 /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.3411941231 Mar 26 02:40:51 PM PDT 24 Mar 26 02:40:53 PM PDT 24 86841353 ps
T1042 /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.2833839798 Mar 26 02:40:34 PM PDT 24 Mar 26 02:40:43 PM PDT 24 375672150 ps
T1043 /workspace/coverage/cover_reg_top/1.keymgr_intr_test.129184806 Mar 26 02:40:31 PM PDT 24 Mar 26 02:40:32 PM PDT 24 9745365 ps
T1044 /workspace/coverage/cover_reg_top/42.keymgr_intr_test.2101638079 Mar 26 02:41:12 PM PDT 24 Mar 26 02:41:13 PM PDT 24 73477377 ps
T1045 /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.3762439786 Mar 26 02:40:49 PM PDT 24 Mar 26 02:40:51 PM PDT 24 47558118 ps
T1046 /workspace/coverage/cover_reg_top/12.keymgr_intr_test.1620011789 Mar 26 02:40:56 PM PDT 24 Mar 26 02:40:57 PM PDT 24 16781073 ps
T1047 /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.2593624029 Mar 26 02:40:46 PM PDT 24 Mar 26 02:40:47 PM PDT 24 320201868 ps
T1048 /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.2885985200 Mar 26 02:41:00 PM PDT 24 Mar 26 02:41:03 PM PDT 24 228087379 ps
T1049 /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.3949837530 Mar 26 02:40:37 PM PDT 24 Mar 26 02:40:41 PM PDT 24 563825098 ps
T1050 /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.3802629468 Mar 26 02:41:00 PM PDT 24 Mar 26 02:41:02 PM PDT 24 872085310 ps
T1051 /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.1966000101 Mar 26 02:40:35 PM PDT 24 Mar 26 02:40:37 PM PDT 24 166596763 ps
T1052 /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.2452798003 Mar 26 02:40:53 PM PDT 24 Mar 26 02:40:55 PM PDT 24 56760657 ps
T1053 /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.4195374684 Mar 26 02:40:45 PM PDT 24 Mar 26 02:40:48 PM PDT 24 99087175 ps
T1054 /workspace/coverage/cover_reg_top/20.keymgr_intr_test.3141838128 Mar 26 02:40:58 PM PDT 24 Mar 26 02:41:00 PM PDT 24 74867161 ps
T1055 /workspace/coverage/cover_reg_top/27.keymgr_intr_test.1572114766 Mar 26 02:41:08 PM PDT 24 Mar 26 02:41:10 PM PDT 24 32389426 ps
T1056 /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.1690610093 Mar 26 02:40:35 PM PDT 24 Mar 26 02:40:38 PM PDT 24 234145076 ps
T1057 /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.3879128803 Mar 26 02:40:33 PM PDT 24 Mar 26 02:40:34 PM PDT 24 35686297 ps
T1058 /workspace/coverage/cover_reg_top/33.keymgr_intr_test.2273498121 Mar 26 02:41:16 PM PDT 24 Mar 26 02:41:17 PM PDT 24 50053282 ps
T1059 /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.3637734218 Mar 26 02:40:53 PM PDT 24 Mar 26 02:40:56 PM PDT 24 105589697 ps
T1060 /workspace/coverage/cover_reg_top/46.keymgr_intr_test.3861796258 Mar 26 02:41:14 PM PDT 24 Mar 26 02:41:14 PM PDT 24 18396667 ps
T1061 /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.1317496212 Mar 26 02:41:00 PM PDT 24 Mar 26 02:41:02 PM PDT 24 51999876 ps
T1062 /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.2818090840 Mar 26 02:40:48 PM PDT 24 Mar 26 02:40:55 PM PDT 24 2622214564 ps
T1063 /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.329194885 Mar 26 02:40:57 PM PDT 24 Mar 26 02:41:01 PM PDT 24 89083761 ps
T178 /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.2436951366 Mar 26 02:40:50 PM PDT 24 Mar 26 02:40:59 PM PDT 24 897031651 ps
T1064 /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.2692013545 Mar 26 02:40:51 PM PDT 24 Mar 26 02:40:52 PM PDT 24 50193921 ps
T192 /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.2090521147 Mar 26 02:40:33 PM PDT 24 Mar 26 02:40:40 PM PDT 24 229090937 ps
T1065 /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.4273663305 Mar 26 02:40:32 PM PDT 24 Mar 26 02:40:36 PM PDT 24 254802044 ps
T188 /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.3982658762 Mar 26 02:40:51 PM PDT 24 Mar 26 02:40:55 PM PDT 24 98426036 ps
T1066 /workspace/coverage/cover_reg_top/24.keymgr_intr_test.3106493784 Mar 26 02:41:02 PM PDT 24 Mar 26 02:41:03 PM PDT 24 18220936 ps
T1067 /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.3207910268 Mar 26 02:40:49 PM PDT 24 Mar 26 02:41:04 PM PDT 24 995580314 ps
T1068 /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.4026339445 Mar 26 02:40:35 PM PDT 24 Mar 26 02:40:43 PM PDT 24 130612461 ps
T1069 /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.1550827311 Mar 26 02:40:48 PM PDT 24 Mar 26 02:40:51 PM PDT 24 137643011 ps
T1070 /workspace/coverage/cover_reg_top/17.keymgr_intr_test.1028899773 Mar 26 02:40:56 PM PDT 24 Mar 26 02:40:58 PM PDT 24 10325168 ps
T1071 /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.833007776 Mar 26 02:40:47 PM PDT 24 Mar 26 02:40:55 PM PDT 24 1123817911 ps
T1072 /workspace/coverage/cover_reg_top/34.keymgr_intr_test.379517858 Mar 26 02:41:18 PM PDT 24 Mar 26 02:41:18 PM PDT 24 24420739 ps
T1073 /workspace/coverage/cover_reg_top/35.keymgr_intr_test.3726628493 Mar 26 02:41:12 PM PDT 24 Mar 26 02:41:13 PM PDT 24 17214462 ps
T1074 /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.3932560454 Mar 26 02:40:56 PM PDT 24 Mar 26 02:40:59 PM PDT 24 164154336 ps
T1075 /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.1779153934 Mar 26 02:40:35 PM PDT 24 Mar 26 02:40:37 PM PDT 24 149935313 ps
T1076 /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.3040979141 Mar 26 02:40:56 PM PDT 24 Mar 26 02:40:59 PM PDT 24 37531836 ps

Test location /workspace/coverage/default/31.keymgr_kmac_rsp_err.3384962596
Short name T17
Test name
Test status
Simulation time 1167146249 ps
CPU time 32.92 seconds
Started Mar 26 03:29:32 PM PDT 24
Finished Mar 26 03:30:05 PM PDT 24
Peak memory 214528 kb
Host smart-16f8706e-3e05-469d-a6a6-efbbdaece426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384962596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_kmac_rsp_err.3384962596
Directory /workspace/31.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_stress_all.1830850215
Short name T6
Test name
Test status
Simulation time 100593298085 ps
CPU time 423.56 seconds
Started Mar 26 03:29:12 PM PDT 24
Finished Mar 26 03:36:16 PM PDT 24
Peak memory 218224 kb
Host smart-5d9c1b95-012c-4fbb-a62b-ecdb31bd43db
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830850215 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_stress_all.1830850215
Directory /workspace/28.keymgr_stress_all/latest

Test location /workspace/coverage/default/47.keymgr_stress_all.295604659
Short name T43
Test name
Test status
Simulation time 21367457356 ps
CPU time 141.58 seconds
Started Mar 26 03:30:04 PM PDT 24
Finished Mar 26 03:32:26 PM PDT 24
Peak memory 222968 kb
Host smart-b8f38c61-2a1c-470e-9c91-290ea75ef322
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=295604659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_stress_all.295604659
Directory /workspace/47.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_sec_cm.1937037535
Short name T5
Test name
Test status
Simulation time 12158743453 ps
CPU time 40.48 seconds
Started Mar 26 03:28:26 PM PDT 24
Finished Mar 26 03:29:07 PM PDT 24
Peak memory 236100 kb
Host smart-753be19f-8204-4f9c-830b-a64eb483c799
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1937037535 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sec_cm.1937037535
Directory /workspace/3.keymgr_sec_cm/latest

Test location /workspace/coverage/default/16.keymgr_stress_all_with_rand_reset.733820579
Short name T46
Test name
Test status
Simulation time 706333713 ps
CPU time 15.9 seconds
Started Mar 26 03:28:44 PM PDT 24
Finished Mar 26 03:29:00 PM PDT 24
Peak memory 222952 kb
Host smart-9045540d-df9b-49b9-b33a-97ea6dd33545
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=733820579 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all_with_rand_reset.733820579
Directory /workspace/16.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.keymgr_cfg_regwen.1742947581
Short name T41
Test name
Test status
Simulation time 14798593285 ps
CPU time 53.04 seconds
Started Mar 26 03:29:34 PM PDT 24
Finished Mar 26 03:30:27 PM PDT 24
Peak memory 215820 kb
Host smart-4864f78f-8eb5-4500-aa3d-d787c616d87c
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1742947581 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_cfg_regwen.1742947581
Directory /workspace/31.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_stress_all.3774847445
Short name T47
Test name
Test status
Simulation time 749231452 ps
CPU time 27.15 seconds
Started Mar 26 03:28:52 PM PDT 24
Finished Mar 26 03:29:19 PM PDT 24
Peak memory 222832 kb
Host smart-0f0f2c12-5b02-4a85-a382-39e26cea8784
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3774847445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_stress_all.3774847445
Directory /workspace/15.keymgr_stress_all/latest

Test location /workspace/coverage/default/4.keymgr_stress_all.3116890419
Short name T59
Test name
Test status
Simulation time 7440634467 ps
CPU time 75.45 seconds
Started Mar 26 03:28:07 PM PDT 24
Finished Mar 26 03:29:23 PM PDT 24
Peak memory 215500 kb
Host smart-d57bf60d-d663-47b6-ad66-9d3265844257
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3116890419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all.3116890419
Directory /workspace/4.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors_with_csr_rw.2605862192
Short name T115
Test name
Test status
Simulation time 445217769 ps
CPU time 15.2 seconds
Started Mar 26 02:41:00 PM PDT 24
Finished Mar 26 02:41:16 PM PDT 24
Peak memory 220508 kb
Host smart-ead2f7e3-33e8-4879-a3c7-b5283de9a301
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605862192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19
.keymgr_shadow_reg_errors_with_csr_rw.2605862192
Directory /workspace/19.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/12.keymgr_custom_cm.3938928900
Short name T8
Test name
Test status
Simulation time 1780480917 ps
CPU time 11.96 seconds
Started Mar 26 03:28:37 PM PDT 24
Finished Mar 26 03:28:49 PM PDT 24
Peak memory 218032 kb
Host smart-fd9968af-d7c9-41d3-9d89-4d59cb540505
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938928900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_custom_cm.3938928900
Directory /workspace/12.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_cfg_regwen.4283484687
Short name T143
Test name
Test status
Simulation time 12937076822 ps
CPU time 100.87 seconds
Started Mar 26 03:29:56 PM PDT 24
Finished Mar 26 03:31:37 PM PDT 24
Peak memory 222976 kb
Host smart-1916f114-6415-4f19-9084-ab8b9a529e7f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4283484687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_cfg_regwen.4283484687
Directory /workspace/44.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/24.keymgr_cfg_regwen.3809146352
Short name T247
Test name
Test status
Simulation time 1944217690 ps
CPU time 107.71 seconds
Started Mar 26 03:29:02 PM PDT 24
Finished Mar 26 03:30:49 PM PDT 24
Peak memory 218324 kb
Host smart-a73caa4b-fdaa-441d-96b3-148f31027234
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3809146352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_cfg_regwen.3809146352
Directory /workspace/24.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/31.keymgr_hwsw_invalid_input.2883683885
Short name T95
Test name
Test status
Simulation time 293558308 ps
CPU time 6.2 seconds
Started Mar 26 03:29:32 PM PDT 24
Finished Mar 26 03:29:38 PM PDT 24
Peak memory 219396 kb
Host smart-a21ef92f-aa80-47c7-8d1b-b724e2bdcb8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2883683885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_hwsw_invalid_input.2883683885
Directory /workspace/31.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_cfg_regwen.3767384803
Short name T106
Test name
Test status
Simulation time 3068815289 ps
CPU time 40.69 seconds
Started Mar 26 03:29:58 PM PDT 24
Finished Mar 26 03:30:39 PM PDT 24
Peak memory 215680 kb
Host smart-490e5ad3-60df-427e-ae4d-a0dc79a68693
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3767384803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_cfg_regwen.3767384803
Directory /workspace/43.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_kmac_rsp_err.2290548607
Short name T23
Test name
Test status
Simulation time 359685127 ps
CPU time 9.89 seconds
Started Mar 26 03:28:37 PM PDT 24
Finished Mar 26 03:28:47 PM PDT 24
Peak memory 222704 kb
Host smart-116dcf87-9d4a-49b1-9951-b3f1366498f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2290548607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_kmac_rsp_err.2290548607
Directory /workspace/4.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/39.keymgr_stress_all.2911193655
Short name T201
Test name
Test status
Simulation time 1923258733 ps
CPU time 46.45 seconds
Started Mar 26 03:29:56 PM PDT 24
Finished Mar 26 03:30:43 PM PDT 24
Peak memory 222332 kb
Host smart-c7a3a9bd-d4b8-48cd-88ac-7961954a97ab
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2911193655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_stress_all.2911193655
Directory /workspace/39.keymgr_stress_all/latest

Test location /workspace/coverage/default/45.keymgr_cfg_regwen.933464016
Short name T144
Test name
Test status
Simulation time 5079595455 ps
CPU time 47.18 seconds
Started Mar 26 03:29:56 PM PDT 24
Finished Mar 26 03:30:44 PM PDT 24
Peak memory 216244 kb
Host smart-6c87d2d0-fa0b-451b-a1fa-91a011d7b19e
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=933464016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_cfg_regwen.933464016
Directory /workspace/45.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_stress_all_with_rand_reset.1086492339
Short name T72
Test name
Test status
Simulation time 297033501 ps
CPU time 17.31 seconds
Started Mar 26 03:28:04 PM PDT 24
Finished Mar 26 03:28:21 PM PDT 24
Peak memory 222880 kb
Host smart-f8bc571e-0534-4407-942f-44add15c920f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1086492339 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all_with_rand_reset.1086492339
Directory /workspace/0.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors.3722613150
Short name T116
Test name
Test status
Simulation time 479701869 ps
CPU time 5.1 seconds
Started Mar 26 02:40:34 PM PDT 24
Finished Mar 26 02:40:40 PM PDT 24
Peak memory 214360 kb
Host smart-a6af72fe-c764-4503-90f1-b416556110a5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3722613150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_shado
w_reg_errors.3722613150
Directory /workspace/3.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/default/3.keymgr_cfg_regwen.3234325767
Short name T147
Test name
Test status
Simulation time 133722048 ps
CPU time 7.83 seconds
Started Mar 26 03:28:30 PM PDT 24
Finished Mar 26 03:28:38 PM PDT 24
Peak memory 215124 kb
Host smart-724a18c2-0990-4e4b-8a91-2b5be3ef9cb7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3234325767 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_cfg_regwen.3234325767
Directory /workspace/3.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/22.keymgr_hwsw_invalid_input.2711851962
Short name T94
Test name
Test status
Simulation time 1322040956 ps
CPU time 9.08 seconds
Started Mar 26 03:29:04 PM PDT 24
Finished Mar 26 03:29:13 PM PDT 24
Peak memory 210504 kb
Host smart-d86964ae-6321-4a08-965f-2db1622be444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2711851962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_hwsw_invalid_input.2711851962
Directory /workspace/22.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_custom_cm.2447777292
Short name T628
Test name
Test status
Simulation time 149449303 ps
CPU time 3.5 seconds
Started Mar 26 03:28:09 PM PDT 24
Finished Mar 26 03:28:13 PM PDT 24
Peak memory 209364 kb
Host smart-f26529ba-6157-4ccc-b99f-feb59c167acc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2447777292 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_custom_cm.2447777292
Directory /workspace/1.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_cfg_regwen.104372720
Short name T314
Test name
Test status
Simulation time 173378974 ps
CPU time 9.45 seconds
Started Mar 26 03:28:42 PM PDT 24
Finished Mar 26 03:28:51 PM PDT 24
Peak memory 214592 kb
Host smart-36940608-7625-4d64-9cf1-a3d6b424c363
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=104372720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_cfg_regwen.104372720
Directory /workspace/13.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/13.keymgr_custom_cm.442391458
Short name T31
Test name
Test status
Simulation time 145488506 ps
CPU time 2.79 seconds
Started Mar 26 03:28:59 PM PDT 24
Finished Mar 26 03:29:03 PM PDT 24
Peak memory 207856 kb
Host smart-efff43af-5d35-4952-85df-8973befb8775
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=442391458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_custom_cm.442391458
Directory /workspace/13.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_stress_all.340141565
Short name T62
Test name
Test status
Simulation time 42120146983 ps
CPU time 289.85 seconds
Started Mar 26 03:28:13 PM PDT 24
Finished Mar 26 03:33:08 PM PDT 24
Peak memory 222868 kb
Host smart-8221159f-f7a5-4494-baf4-bcb9c8c691a3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340141565 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all.340141565
Directory /workspace/2.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_custom_cm.3502693746
Short name T158
Test name
Test status
Simulation time 149706992 ps
CPU time 5.32 seconds
Started Mar 26 03:28:59 PM PDT 24
Finished Mar 26 03:29:05 PM PDT 24
Peak memory 223020 kb
Host smart-23f00db4-44b9-4fe6-8323-326ec47560a5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502693746 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_custom_cm.3502693746
Directory /workspace/16.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_sync_async_fault_cross.3083446321
Short name T18
Test name
Test status
Simulation time 30938930 ps
CPU time 1.89 seconds
Started Mar 26 03:29:51 PM PDT 24
Finished Mar 26 03:30:03 PM PDT 24
Peak memory 210152 kb
Host smart-8848c2d4-9787-4297-b4d5-bf8ed29eb77a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083446321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sync_async_fault_cross.3083446321
Directory /workspace/35.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_cfg_regwen.390674650
Short name T423
Test name
Test status
Simulation time 159519256 ps
CPU time 5.19 seconds
Started Mar 26 03:29:20 PM PDT 24
Finished Mar 26 03:29:25 PM PDT 24
Peak memory 215684 kb
Host smart-60d4556d-39c6-44d8-aef4-f15d6decc099
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=390674650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_cfg_regwen.390674650
Directory /workspace/27.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_stress_all.2816752457
Short name T261
Test name
Test status
Simulation time 625458141 ps
CPU time 22.68 seconds
Started Mar 26 03:29:44 PM PDT 24
Finished Mar 26 03:30:07 PM PDT 24
Peak memory 216960 kb
Host smart-55b360c6-8dda-4f3e-a483-16f1d3ad81d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2816752457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_stress_all.2816752457
Directory /workspace/38.keymgr_stress_all/latest

Test location /workspace/coverage/default/44.keymgr_stress_all.3525723143
Short name T268
Test name
Test status
Simulation time 2426597334 ps
CPU time 32.36 seconds
Started Mar 26 03:29:54 PM PDT 24
Finished Mar 26 03:30:27 PM PDT 24
Peak memory 223016 kb
Host smart-59d7f27b-616f-483f-8ab8-f0f8af944313
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525723143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_stress_all.3525723143
Directory /workspace/44.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_intg_err.1525957684
Short name T179
Test name
Test status
Simulation time 148108961 ps
CPU time 6.03 seconds
Started Mar 26 02:40:35 PM PDT 24
Finished Mar 26 02:40:41 PM PDT 24
Peak memory 209036 kb
Host smart-b6ef77bb-8bce-4988-915a-e03dba8f1c89
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1525957684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_intg_err
.1525957684
Directory /workspace/2.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/46.keymgr_custom_cm.704057710
Short name T215
Test name
Test status
Simulation time 221593809 ps
CPU time 6.3 seconds
Started Mar 26 03:29:56 PM PDT 24
Finished Mar 26 03:30:03 PM PDT 24
Peak memory 223172 kb
Host smart-38d54e7b-bad4-4b82-ba3b-b3732507b478
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=704057710 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_custom_cm.704057710
Directory /workspace/46.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_alert_test.469646430
Short name T138
Test name
Test status
Simulation time 18329657 ps
CPU time 0.8 seconds
Started Mar 26 03:28:16 PM PDT 24
Finished Mar 26 03:28:17 PM PDT 24
Peak memory 206324 kb
Host smart-cf9f3f5b-e9bc-4578-8e62-20d93948eeb5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469646430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_alert_test.469646430
Directory /workspace/2.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_cfg_regwen.317508702
Short name T294
Test name
Test status
Simulation time 71278056 ps
CPU time 4.03 seconds
Started Mar 26 03:28:58 PM PDT 24
Finished Mar 26 03:29:03 PM PDT 24
Peak memory 214752 kb
Host smart-fd423987-72be-4fbc-a7d7-ef812a8b940d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=317508702 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_cfg_regwen.317508702
Directory /workspace/22.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_kmac_rsp_err.3070943528
Short name T300
Test name
Test status
Simulation time 413982232 ps
CPU time 4.3 seconds
Started Mar 26 03:28:55 PM PDT 24
Finished Mar 26 03:29:00 PM PDT 24
Peak memory 214736 kb
Host smart-6bed73a3-247c-424c-9d17-5d679354016c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070943528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_kmac_rsp_err.3070943528
Directory /workspace/23.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_intg_err.823804312
Short name T167
Test name
Test status
Simulation time 435700065 ps
CPU time 10.19 seconds
Started Mar 26 02:41:00 PM PDT 24
Finished Mar 26 02:41:10 PM PDT 24
Peak memory 214052 kb
Host smart-023f845a-bbd5-478b-a973-544f3d3dbe8b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823804312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_intg_err
.823804312
Directory /workspace/16.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/11.keymgr_cfg_regwen.223108246
Short name T418
Test name
Test status
Simulation time 309999336 ps
CPU time 15.96 seconds
Started Mar 26 03:28:35 PM PDT 24
Finished Mar 26 03:28:51 PM PDT 24
Peak memory 215676 kb
Host smart-4b73ff5b-1678-455d-b2b1-c9137a40b1be
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=223108246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_cfg_regwen.223108246
Directory /workspace/11.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_kmac_rsp_err.3246657120
Short name T202
Test name
Test status
Simulation time 271624595 ps
CPU time 5.88 seconds
Started Mar 26 03:29:56 PM PDT 24
Finished Mar 26 03:30:07 PM PDT 24
Peak memory 214564 kb
Host smart-572314aa-5ff0-4c38-939f-f71cd44c0bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3246657120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_kmac_rsp_err.3246657120
Directory /workspace/39.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_hwsw_invalid_input.3421532649
Short name T289
Test name
Test status
Simulation time 95833400 ps
CPU time 2.99 seconds
Started Mar 26 03:28:20 PM PDT 24
Finished Mar 26 03:28:23 PM PDT 24
Peak memory 222856 kb
Host smart-65673663-b847-4283-8d46-effa3ca2dba9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3421532649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_hwsw_invalid_input.3421532649
Directory /workspace/9.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_cfg_regwen.2605283904
Short name T901
Test name
Test status
Simulation time 580387200 ps
CPU time 8.98 seconds
Started Mar 26 03:28:08 PM PDT 24
Finished Mar 26 03:28:17 PM PDT 24
Peak memory 215948 kb
Host smart-31b13845-33ea-4b2e-b43d-7fca5dc3fdf7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2605283904 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_cfg_regwen.2605283904
Directory /workspace/0.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_stress_all.2876545973
Short name T173
Test name
Test status
Simulation time 3207595094 ps
CPU time 70.89 seconds
Started Mar 26 03:29:59 PM PDT 24
Finished Mar 26 03:31:11 PM PDT 24
Peak memory 217452 kb
Host smart-296275e0-0f44-4cb4-983f-5a2b29d03877
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2876545973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all.2876545973
Directory /workspace/41.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_intg_err.707118675
Short name T186
Test name
Test status
Simulation time 113558894 ps
CPU time 5.71 seconds
Started Mar 26 02:40:49 PM PDT 24
Finished Mar 26 02:40:55 PM PDT 24
Peak memory 214052 kb
Host smart-ecbd1a7f-9964-4e8f-a4b0-5d2e08b88bf8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707118675 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_intg_err.
707118675
Directory /workspace/9.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/32.keymgr_kmac_rsp_err.1706712812
Short name T282
Test name
Test status
Simulation time 52194645 ps
CPU time 3.32 seconds
Started Mar 26 03:29:30 PM PDT 24
Finished Mar 26 03:29:34 PM PDT 24
Peak memory 214540 kb
Host smart-cc90950a-2397-4a35-a6cf-67420f463534
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706712812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_kmac_rsp_err.1706712812
Directory /workspace/32.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_cfg_regwen.2345382787
Short name T287
Test name
Test status
Simulation time 50375449 ps
CPU time 3.25 seconds
Started Mar 26 03:29:42 PM PDT 24
Finished Mar 26 03:29:46 PM PDT 24
Peak memory 215596 kb
Host smart-0a0930e6-0f7f-4440-8436-1877b8dbdfce
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2345382787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_cfg_regwen.2345382787
Directory /workspace/35.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_kmac_rsp_err.282129732
Short name T39
Test name
Test status
Simulation time 1540317294 ps
CPU time 48.88 seconds
Started Mar 26 03:29:55 PM PDT 24
Finished Mar 26 03:30:44 PM PDT 24
Peak memory 219444 kb
Host smart-8499f998-b3e7-4492-bb01-f4342e7eab5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282129732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_kmac_rsp_err.282129732
Directory /workspace/41.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_sync_async_fault_cross.1331388372
Short name T562
Test name
Test status
Simulation time 325128493 ps
CPU time 6.65 seconds
Started Mar 26 03:28:57 PM PDT 24
Finished Mar 26 03:29:04 PM PDT 24
Peak memory 211300 kb
Host smart-2f932478-9265-426a-b6ae-aef3ab69d6d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1331388372 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sync_async_fault_cross.1331388372
Directory /workspace/18.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_custom_cm.277758787
Short name T803
Test name
Test status
Simulation time 175480993 ps
CPU time 2.32 seconds
Started Mar 26 03:29:09 PM PDT 24
Finished Mar 26 03:29:11 PM PDT 24
Peak memory 222028 kb
Host smart-cd80cd69-ad8a-4a2d-9424-ded9130764e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277758787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_custom_cm.277758787
Directory /workspace/28.keymgr_custom_cm/latest

Test location /workspace/coverage/default/20.keymgr_custom_cm.3622015839
Short name T159
Test name
Test status
Simulation time 642201639 ps
CPU time 3.04 seconds
Started Mar 26 03:29:08 PM PDT 24
Finished Mar 26 03:29:11 PM PDT 24
Peak memory 222988 kb
Host smart-463f8eac-60cd-470f-ac52-b51a20e9ca9a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622015839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_custom_cm.3622015839
Directory /workspace/20.keymgr_custom_cm/latest

Test location /workspace/coverage/default/13.keymgr_stress_all.3208593800
Short name T220
Test name
Test status
Simulation time 4797487193 ps
CPU time 68.41 seconds
Started Mar 26 03:29:00 PM PDT 24
Finished Mar 26 03:30:08 PM PDT 24
Peak memory 222848 kb
Host smart-e8048ebb-1132-44e7-aefa-930c2189116e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208593800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_stress_all.3208593800
Directory /workspace/13.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_cfg_regwen.1851693407
Short name T325
Test name
Test status
Simulation time 335167929 ps
CPU time 13.98 seconds
Started Mar 26 03:29:03 PM PDT 24
Finished Mar 26 03:29:17 PM PDT 24
Peak memory 215268 kb
Host smart-7a7c5a66-46e1-43c4-a0c4-899a568c5234
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1851693407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_cfg_regwen.1851693407
Directory /workspace/21.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_sideload_protect.513636384
Short name T321
Test name
Test status
Simulation time 45237852 ps
CPU time 3.07 seconds
Started Mar 26 03:29:53 PM PDT 24
Finished Mar 26 03:29:56 PM PDT 24
Peak memory 214660 kb
Host smart-05546676-b3db-4c6c-a758-9fe59e51c43b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513636384 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_protect.513636384
Directory /workspace/37.keymgr_sideload_protect/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_intg_err.3736600810
Short name T190
Test name
Test status
Simulation time 654565159 ps
CPU time 5.55 seconds
Started Mar 26 02:40:31 PM PDT 24
Finished Mar 26 02:40:37 PM PDT 24
Peak memory 209184 kb
Host smart-fdd40a76-eaee-45b4-a5aa-3dc5b15c1c5c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3736600810 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_intg_err
.3736600810
Directory /workspace/1.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_intg_err.2090521147
Short name T192
Test name
Test status
Simulation time 229090937 ps
CPU time 6.57 seconds
Started Mar 26 02:40:33 PM PDT 24
Finished Mar 26 02:40:40 PM PDT 24
Peak memory 209060 kb
Host smart-ff5188b5-a15c-4760-aec5-f3fe4c21cdab
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2090521147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_intg_err
.2090521147
Directory /workspace/3.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_intg_err.1439696106
Short name T184
Test name
Test status
Simulation time 888504721 ps
CPU time 9.7 seconds
Started Mar 26 02:40:45 PM PDT 24
Finished Mar 26 02:40:55 PM PDT 24
Peak memory 209428 kb
Host smart-89c1ec40-51f2-459a-a883-081cdd10c2cc
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1439696106 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_intg_err
.1439696106
Directory /workspace/6.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_intg_err.1963726137
Short name T187
Test name
Test status
Simulation time 2545513287 ps
CPU time 79.55 seconds
Started Mar 26 02:40:51 PM PDT 24
Finished Mar 26 02:42:11 PM PDT 24
Peak memory 224736 kb
Host smart-3bca7a44-feae-492a-8581-23aa2b233be1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1963726137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_intg_err
.1963726137
Directory /workspace/8.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/31.keymgr_custom_cm.4182014206
Short name T162
Test name
Test status
Simulation time 105746225 ps
CPU time 3.64 seconds
Started Mar 26 03:29:14 PM PDT 24
Finished Mar 26 03:29:17 PM PDT 24
Peak memory 218192 kb
Host smart-f85c8368-7ed0-4085-b3f0-09cb82ece3f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182014206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_custom_cm.4182014206
Directory /workspace/31.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_stress_all.2765800461
Short name T172
Test name
Test status
Simulation time 7024041617 ps
CPU time 41.14 seconds
Started Mar 26 03:29:09 PM PDT 24
Finished Mar 26 03:29:50 PM PDT 24
Peak memory 215792 kb
Host smart-e23cafdb-6d3d-4481-887c-49a2303ce876
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2765800461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all.2765800461
Directory /workspace/24.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_kmac_rsp_err.1283087695
Short name T264
Test name
Test status
Simulation time 218422278 ps
CPU time 9.35 seconds
Started Mar 26 03:29:48 PM PDT 24
Finished Mar 26 03:29:58 PM PDT 24
Peak memory 222716 kb
Host smart-c8bd8c56-a173-4554-b494-80b04ed2c28a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1283087695 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_kmac_rsp_err.1283087695
Directory /workspace/34.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/41.keymgr_stress_all_with_rand_reset.1457583960
Short name T232
Test name
Test status
Simulation time 1666902277 ps
CPU time 23.44 seconds
Started Mar 26 03:29:55 PM PDT 24
Finished Mar 26 03:30:19 PM PDT 24
Peak memory 221412 kb
Host smart-d0df75bc-f983-4294-a44e-e36513483e74
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1457583960 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 41.keymgr_stress_all_with_rand_reset.1457583960
Directory /workspace/41.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.keymgr_sync_async_fault_cross.4069247641
Short name T123
Test name
Test status
Simulation time 101383753 ps
CPU time 1.6 seconds
Started Mar 26 03:30:03 PM PDT 24
Finished Mar 26 03:30:05 PM PDT 24
Peak memory 208620 kb
Host smart-d5189007-e0ef-4045-a413-034cfd0f0aa9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069247641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sync_async_fault_cross.4069247641
Directory /workspace/45.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_cfg_regwen.4028400079
Short name T87
Test name
Test status
Simulation time 122073201 ps
CPU time 4.63 seconds
Started Mar 26 03:30:07 PM PDT 24
Finished Mar 26 03:30:12 PM PDT 24
Peak memory 216072 kb
Host smart-b418d733-4856-4233-8127-60892aa26e00
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4028400079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_cfg_regwen.4028400079
Directory /workspace/48.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/0.keymgr_hwsw_invalid_input.1702354518
Short name T91
Test name
Test status
Simulation time 82713168 ps
CPU time 4.33 seconds
Started Mar 26 03:28:17 PM PDT 24
Finished Mar 26 03:28:22 PM PDT 24
Peak memory 209968 kb
Host smart-0b5c54be-f8a6-4ae4-ad11-5031e61c580b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702354518 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_hwsw_invalid_input.1702354518
Directory /workspace/0.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_custom_cm.3217009884
Short name T161
Test name
Test status
Simulation time 151058941 ps
CPU time 5.21 seconds
Started Mar 26 03:29:23 PM PDT 24
Finished Mar 26 03:29:28 PM PDT 24
Peak memory 216012 kb
Host smart-fdb2ec02-662b-4904-bcf3-ebe9a581d104
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217009884 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_custom_cm.3217009884
Directory /workspace/30.keymgr_custom_cm/latest

Test location /workspace/coverage/default/47.keymgr_custom_cm.98574317
Short name T160
Test name
Test status
Simulation time 73603844 ps
CPU time 2.28 seconds
Started Mar 26 03:30:04 PM PDT 24
Finished Mar 26 03:30:07 PM PDT 24
Peak memory 216344 kb
Host smart-197c504b-3122-471e-a956-1ca44d62cd91
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98574317 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_custom_cm.98574317
Directory /workspace/47.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload_aes.3125117515
Short name T206
Test name
Test status
Simulation time 289247108 ps
CPU time 3.53 seconds
Started Mar 26 03:28:10 PM PDT 24
Finished Mar 26 03:28:14 PM PDT 24
Peak memory 206984 kb
Host smart-ab1fd72a-d9d8-405e-901f-773324dca565
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3125117515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_aes.3125117515
Directory /workspace/0.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_cfg_regwen.3973911485
Short name T357
Test name
Test status
Simulation time 241978975 ps
CPU time 4.55 seconds
Started Mar 26 03:28:13 PM PDT 24
Finished Mar 26 03:28:17 PM PDT 24
Peak memory 214692 kb
Host smart-b15c0323-8801-4380-993a-4f36ab53df9f
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3973911485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_cfg_regwen.3973911485
Directory /workspace/1.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_stress_all.3381251415
Short name T208
Test name
Test status
Simulation time 5071940353 ps
CPU time 117.37 seconds
Started Mar 26 03:28:49 PM PDT 24
Finished Mar 26 03:30:47 PM PDT 24
Peak memory 217924 kb
Host smart-0cae59d8-517c-491b-b920-7d91e2c6c8fd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3381251415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_stress_all.3381251415
Directory /workspace/12.keymgr_stress_all/latest

Test location /workspace/coverage/default/14.keymgr_kmac_rsp_err.1993784060
Short name T727
Test name
Test status
Simulation time 1471023460 ps
CPU time 4.93 seconds
Started Mar 26 03:28:50 PM PDT 24
Finished Mar 26 03:28:55 PM PDT 24
Peak memory 211608 kb
Host smart-e6578628-799e-441e-a661-82eac8ba3249
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993784060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_kmac_rsp_err.1993784060
Directory /workspace/14.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_cfg_regwen.4185222700
Short name T425
Test name
Test status
Simulation time 170035349 ps
CPU time 3.36 seconds
Started Mar 26 03:29:03 PM PDT 24
Finished Mar 26 03:29:06 PM PDT 24
Peak memory 215944 kb
Host smart-b48de195-7230-4d39-bf2e-739260e42ac1
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4185222700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_cfg_regwen.4185222700
Directory /workspace/16.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/20.keymgr_cfg_regwen.3790784324
Short name T148
Test name
Test status
Simulation time 61475148 ps
CPU time 4.25 seconds
Started Mar 26 03:29:03 PM PDT 24
Finished Mar 26 03:29:07 PM PDT 24
Peak memory 215456 kb
Host smart-719324d4-5357-4ec0-9efd-b17202e8b605
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3790784324 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_cfg_regwen.3790784324
Directory /workspace/20.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/21.keymgr_kmac_rsp_err.89469919
Short name T339
Test name
Test status
Simulation time 244790086 ps
CPU time 3.58 seconds
Started Mar 26 03:29:03 PM PDT 24
Finished Mar 26 03:29:06 PM PDT 24
Peak memory 211168 kb
Host smart-8c415466-8d3a-40db-b5de-472f9239939c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=89469919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_kmac_rsp_err.89469919
Directory /workspace/21.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/23.keymgr_sideload_aes.1063862524
Short name T2
Test name
Test status
Simulation time 3134204350 ps
CPU time 6.99 seconds
Started Mar 26 03:29:07 PM PDT 24
Finished Mar 26 03:29:14 PM PDT 24
Peak memory 207272 kb
Host smart-ab26b79d-a01f-4ad6-945a-c574aa8c0263
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1063862524 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_aes.1063862524
Directory /workspace/23.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_cfg_regwen.2232170647
Short name T367
Test name
Test status
Simulation time 205894500 ps
CPU time 11.24 seconds
Started Mar 26 03:29:21 PM PDT 24
Finished Mar 26 03:29:32 PM PDT 24
Peak memory 214576 kb
Host smart-29a4f61a-8f76-472a-b253-2d4e6987e090
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2232170647 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_cfg_regwen.2232170647
Directory /workspace/30.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_stress_all.2389907994
Short name T223
Test name
Test status
Simulation time 2807476016 ps
CPU time 21.87 seconds
Started Mar 26 03:28:21 PM PDT 24
Finished Mar 26 03:28:43 PM PDT 24
Peak memory 222948 kb
Host smart-7f07e399-4700-4efc-851b-affa606a29a2
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2389907994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_stress_all.2389907994
Directory /workspace/7.keymgr_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_intg_err.1984970442
Short name T194
Test name
Test status
Simulation time 103605126 ps
CPU time 3.29 seconds
Started Mar 26 02:40:54 PM PDT 24
Finished Mar 26 02:40:57 PM PDT 24
Peak memory 209020 kb
Host smart-d1f2d18b-41ea-4504-b1fe-0d62138b51ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1984970442 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_intg_er
r.1984970442
Directory /workspace/11.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_intg_err.2436951366
Short name T178
Test name
Test status
Simulation time 897031651 ps
CPU time 8.99 seconds
Started Mar 26 02:40:50 PM PDT 24
Finished Mar 26 02:40:59 PM PDT 24
Peak memory 213984 kb
Host smart-27de651b-f973-4366-a5c5-2357f381e1bb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2436951366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_intg_err
.2436951366
Directory /workspace/7.keymgr_tl_intg_err/latest

Test location /workspace/coverage/default/10.keymgr_sync_async_fault_cross.3718066980
Short name T191
Test name
Test status
Simulation time 35766216 ps
CPU time 2.2 seconds
Started Mar 26 03:28:22 PM PDT 24
Finished Mar 26 03:28:24 PM PDT 24
Peak memory 209984 kb
Host smart-ff1d71f4-f457-41ee-97c8-ba9069f2ff05
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3718066980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sync_async_fault_cross.3718066980
Directory /workspace/10.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_sync_async_fault_cross.137699582
Short name T189
Test name
Test status
Simulation time 106748300 ps
CPU time 1.73 seconds
Started Mar 26 03:28:51 PM PDT 24
Finished Mar 26 03:28:52 PM PDT 24
Peak memory 209008 kb
Host smart-0f37ae56-1603-4c95-b6a9-3ccf5ef98217
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=137699582 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sync_async_fault_cross.137699582
Directory /workspace/12.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_rw.4030075733
Short name T151
Test name
Test status
Simulation time 18676476 ps
CPU time 1.16 seconds
Started Mar 26 02:40:43 PM PDT 24
Finished Mar 26 02:40:45 PM PDT 24
Peak memory 205852 kb
Host smart-e273b60f-6cf2-4e55-91af-1ef0da21e4f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030075733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_rw.4030075733
Directory /workspace/1.keymgr_csr_rw/latest

Test location /workspace/coverage/default/1.keymgr_stress_all.1317674780
Short name T212
Test name
Test status
Simulation time 250056387 ps
CPU time 9.61 seconds
Started Mar 26 03:28:16 PM PDT 24
Finished Mar 26 03:28:25 PM PDT 24
Peak memory 215420 kb
Host smart-3b226078-5e1a-4d6d-a4cd-53983e1d26fb
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317674780 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_stress_all.1317674780
Directory /workspace/1.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_kmac_rsp_err.3745146943
Short name T284
Test name
Test status
Simulation time 4422007499 ps
CPU time 28.54 seconds
Started Mar 26 03:28:27 PM PDT 24
Finished Mar 26 03:28:56 PM PDT 24
Peak memory 222800 kb
Host smart-ee1291e8-cf0c-4f4e-9e0c-f2fdf9674c9c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745146943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_kmac_rsp_err.3745146943
Directory /workspace/10.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/10.keymgr_lc_disable.1758007504
Short name T213
Test name
Test status
Simulation time 2666484213 ps
CPU time 46.02 seconds
Started Mar 26 03:28:19 PM PDT 24
Finished Mar 26 03:29:05 PM PDT 24
Peak memory 209904 kb
Host smart-83a68290-eaae-4312-bf03-98582d66e965
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758007504 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_lc_disable.1758007504
Directory /workspace/10.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_cfg_regwen.2049222338
Short name T110
Test name
Test status
Simulation time 198760271 ps
CPU time 3.71 seconds
Started Mar 26 03:28:37 PM PDT 24
Finished Mar 26 03:28:41 PM PDT 24
Peak memory 215556 kb
Host smart-79545247-56a7-427a-8505-aecc3af853c9
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2049222338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_cfg_regwen.2049222338
Directory /workspace/12.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/12.keymgr_sideload.421181204
Short name T363
Test name
Test status
Simulation time 84579140 ps
CPU time 3.14 seconds
Started Mar 26 03:28:50 PM PDT 24
Finished Mar 26 03:28:54 PM PDT 24
Peak memory 208588 kb
Host smart-d39da566-93f1-4077-ae8a-3dbc8c3ca166
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=421181204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload.421181204
Directory /workspace/12.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_kmac_rsp_err.1628418512
Short name T204
Test name
Test status
Simulation time 117600650 ps
CPU time 5.91 seconds
Started Mar 26 03:28:38 PM PDT 24
Finished Mar 26 03:28:44 PM PDT 24
Peak memory 210804 kb
Host smart-ac09349b-10be-4058-8f0e-7c88c0ea9075
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628418512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_kmac_rsp_err.1628418512
Directory /workspace/13.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_custom_cm.826504689
Short name T10
Test name
Test status
Simulation time 129603436 ps
CPU time 4.7 seconds
Started Mar 26 03:28:54 PM PDT 24
Finished Mar 26 03:29:00 PM PDT 24
Peak memory 215060 kb
Host smart-e638ad8b-a735-46d2-84f4-4465ac17e3f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826504689 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_custom_cm.826504689
Directory /workspace/15.keymgr_custom_cm/latest

Test location /workspace/coverage/default/15.keymgr_hwsw_invalid_input.2413348132
Short name T3
Test name
Test status
Simulation time 63033453 ps
CPU time 3.56 seconds
Started Mar 26 03:28:55 PM PDT 24
Finished Mar 26 03:28:59 PM PDT 24
Peak memory 219548 kb
Host smart-226df613-4870-4ed4-a3f1-e2eb985ba8de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2413348132 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_hwsw_invalid_input.2413348132
Directory /workspace/15.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_lc_disable.520691157
Short name T145
Test name
Test status
Simulation time 644273873 ps
CPU time 17.64 seconds
Started Mar 26 03:29:17 PM PDT 24
Finished Mar 26 03:29:35 PM PDT 24
Peak memory 222804 kb
Host smart-d44b125d-39e6-4beb-acdd-ec9f2555eb6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=520691157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_lc_disable.520691157
Directory /workspace/15.keymgr_lc_disable/latest

Test location /workspace/coverage/default/15.keymgr_sideload_protect.365019917
Short name T371
Test name
Test status
Simulation time 1108619199 ps
CPU time 4.54 seconds
Started Mar 26 03:28:47 PM PDT 24
Finished Mar 26 03:28:52 PM PDT 24
Peak memory 214660 kb
Host smart-c81e3385-e350-4fec-a42e-d99638caabfc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365019917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_protect.365019917
Directory /workspace/15.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_kmac_rsp_err.2823104655
Short name T868
Test name
Test status
Simulation time 1067245798 ps
CPU time 6.73 seconds
Started Mar 26 03:29:06 PM PDT 24
Finished Mar 26 03:29:13 PM PDT 24
Peak memory 221868 kb
Host smart-8fb85df5-2b79-4828-a3cc-e1adb1ad6d4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2823104655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_kmac_rsp_err.2823104655
Directory /workspace/19.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_stress_all_with_rand_reset.4038422463
Short name T847
Test name
Test status
Simulation time 345098718 ps
CPU time 14.07 seconds
Started Mar 26 03:28:06 PM PDT 24
Finished Mar 26 03:28:20 PM PDT 24
Peak memory 222960 kb
Host smart-6e6c7e97-b141-4668-88ce-463831d08a19
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4038422463 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 2.keymgr_stress_all_with_rand_reset.4038422463
Directory /workspace/2.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.keymgr_custom_cm.1888251653
Short name T217
Test name
Test status
Simulation time 495358541 ps
CPU time 14 seconds
Started Mar 26 03:28:59 PM PDT 24
Finished Mar 26 03:29:14 PM PDT 24
Peak memory 210292 kb
Host smart-8cc3b574-81f5-4c07-ac4b-717288a186b8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1888251653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_custom_cm.1888251653
Directory /workspace/22.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_hwsw_invalid_input.1362715017
Short name T391
Test name
Test status
Simulation time 1328276455 ps
CPU time 22.8 seconds
Started Mar 26 03:29:13 PM PDT 24
Finished Mar 26 03:29:36 PM PDT 24
Peak memory 214652 kb
Host smart-f78d27e0-01fc-4359-a75e-17c1339ea171
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1362715017 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_hwsw_invalid_input.1362715017
Directory /workspace/24.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_kmac_rsp_err.2458555576
Short name T376
Test name
Test status
Simulation time 291653756 ps
CPU time 9.68 seconds
Started Mar 26 03:29:11 PM PDT 24
Finished Mar 26 03:29:21 PM PDT 24
Peak memory 216140 kb
Host smart-f5a0f14a-3e5e-4f93-9414-ffc9cd49c5df
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458555576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_kmac_rsp_err.2458555576
Directory /workspace/27.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/3.keymgr_sw_invalid_input.2336645285
Short name T291
Test name
Test status
Simulation time 546391970 ps
CPU time 8.18 seconds
Started Mar 26 03:28:18 PM PDT 24
Finished Mar 26 03:28:26 PM PDT 24
Peak memory 218676 kb
Host smart-16f96bc9-26fc-4431-bbb0-70008228dae9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2336645285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sw_invalid_input.2336645285
Directory /workspace/3.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_cfg_regwen.3173693621
Short name T342
Test name
Test status
Simulation time 838908660 ps
CPU time 12.33 seconds
Started Mar 26 03:29:15 PM PDT 24
Finished Mar 26 03:29:27 PM PDT 24
Peak memory 214608 kb
Host smart-689d75f1-9f98-4d25-996f-052dd235143a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3173693621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_cfg_regwen.3173693621
Directory /workspace/33.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_cfg_regwen.2119622373
Short name T233
Test name
Test status
Simulation time 53231338 ps
CPU time 3.98 seconds
Started Mar 26 03:29:38 PM PDT 24
Finished Mar 26 03:29:43 PM PDT 24
Peak memory 214648 kb
Host smart-cb36b7b0-12f2-45f7-90c8-fd38fd7fecc4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2119622373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_cfg_regwen.2119622373
Directory /workspace/34.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/34.keymgr_custom_cm.1995350540
Short name T228
Test name
Test status
Simulation time 124383520 ps
CPU time 6.05 seconds
Started Mar 26 03:29:33 PM PDT 24
Finished Mar 26 03:29:39 PM PDT 24
Peak memory 218816 kb
Host smart-25d5457d-ca0c-4f19-8c1b-0c0032f706ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995350540 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_custom_cm.1995350540
Directory /workspace/34.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_direct_to_disabled.1864767420
Short name T317
Test name
Test status
Simulation time 1599096715 ps
CPU time 26.94 seconds
Started Mar 26 03:29:49 PM PDT 24
Finished Mar 26 03:30:16 PM PDT 24
Peak memory 209936 kb
Host smart-ae277ceb-f9f5-4308-8204-66c59f8a7820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1864767420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_direct_to_disabled.1864767420
Directory /workspace/39.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_kmac_rsp_err.3544848448
Short name T99
Test name
Test status
Simulation time 1110840910 ps
CPU time 11.75 seconds
Started Mar 26 03:29:56 PM PDT 24
Finished Mar 26 03:30:08 PM PDT 24
Peak memory 214612 kb
Host smart-338d9c68-ac20-460b-b76e-aa4c257198a7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544848448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_kmac_rsp_err.3544848448
Directory /workspace/40.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_stress_all.485057803
Short name T350
Test name
Test status
Simulation time 8338863433 ps
CPU time 56.17 seconds
Started Mar 26 03:30:01 PM PDT 24
Finished Mar 26 03:30:58 PM PDT 24
Peak memory 216924 kb
Host smart-c328ab65-0a8d-404f-a128-aa299c813327
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485057803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_stress_all.485057803
Directory /workspace/42.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_cfg_regwen.1511100481
Short name T301
Test name
Test status
Simulation time 144246867 ps
CPU time 3.07 seconds
Started Mar 26 03:29:57 PM PDT 24
Finished Mar 26 03:30:01 PM PDT 24
Peak memory 215772 kb
Host smart-623eb74e-6788-499f-819e-b2e5591ee6b4
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1511100481 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_cfg_regwen.1511100481
Directory /workspace/46.keymgr_cfg_regwen/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_aliasing.40204225
Short name T971
Test name
Test status
Simulation time 288055320 ps
CPU time 4.76 seconds
Started Mar 26 02:40:35 PM PDT 24
Finished Mar 26 02:40:40 PM PDT 24
Peak memory 205776 kb
Host smart-2b4d9e7f-2ccb-430b-978a-d29f1e43e1fc
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40204225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_aliasing.40204225
Directory /workspace/0.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_bit_bash.4026339445
Short name T1068
Test name
Test status
Simulation time 130612461 ps
CPU time 8.22 seconds
Started Mar 26 02:40:35 PM PDT 24
Finished Mar 26 02:40:43 PM PDT 24
Peak memory 205924 kb
Host smart-daba31d8-c19b-4cc0-a0ef-72fcf3ddc25f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4026339445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_bit_bash.4
026339445
Directory /workspace/0.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_hw_reset.3829924714
Short name T921
Test name
Test status
Simulation time 14686698 ps
CPU time 1.02 seconds
Started Mar 26 02:40:35 PM PDT 24
Finished Mar 26 02:40:36 PM PDT 24
Peak memory 205816 kb
Host smart-b53c978c-744e-41fa-8a48-1091267b54f0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3829924714 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_hw_reset.3
829924714
Directory /workspace/0.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_mem_rw_with_rand_reset.600010390
Short name T1017
Test name
Test status
Simulation time 57191843 ps
CPU time 1.83 seconds
Started Mar 26 02:40:34 PM PDT 24
Finished Mar 26 02:40:36 PM PDT 24
Peak memory 213964 kb
Host smart-33dcd333-1b7d-469e-9939-719f2cefcd4d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600010390 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 0.keymgr_csr_mem_rw_with_rand_reset.600010390
Directory /workspace/0.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_csr_rw.716646544
Short name T1031
Test name
Test status
Simulation time 58151069 ps
CPU time 1.1 seconds
Started Mar 26 02:40:36 PM PDT 24
Finished Mar 26 02:40:38 PM PDT 24
Peak memory 205640 kb
Host smart-3c37817e-8184-4b00-b184-6211bc56d5fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=716646544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_csr_rw.716646544
Directory /workspace/0.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_intr_test.4235489872
Short name T960
Test name
Test status
Simulation time 8126313 ps
CPU time 0.81 seconds
Started Mar 26 02:40:32 PM PDT 24
Finished Mar 26 02:40:33 PM PDT 24
Peak memory 205440 kb
Host smart-d9be58d9-d7ed-41c2-bf66-30c41f951c65
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4235489872 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_intr_test.4235489872
Directory /workspace/0.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_same_csr_outstanding.1779153934
Short name T1075
Test name
Test status
Simulation time 149935313 ps
CPU time 2.48 seconds
Started Mar 26 02:40:35 PM PDT 24
Finished Mar 26 02:40:37 PM PDT 24
Peak memory 205828 kb
Host smart-b5aa4de9-a9ab-4d10-bd24-84b4f59cd8da
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1779153934 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_sa
me_csr_outstanding.1779153934
Directory /workspace/0.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors.3949837530
Short name T1049
Test name
Test status
Simulation time 563825098 ps
CPU time 4.56 seconds
Started Mar 26 02:40:37 PM PDT 24
Finished Mar 26 02:40:41 PM PDT 24
Peak memory 219256 kb
Host smart-5a599f07-91d7-4270-be9b-1b211c466a6d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3949837530 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_shado
w_reg_errors.3949837530
Directory /workspace/0.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_shadow_reg_errors_with_csr_rw.1721157578
Short name T1027
Test name
Test status
Simulation time 383594832 ps
CPU time 5.23 seconds
Started Mar 26 02:40:36 PM PDT 24
Finished Mar 26 02:40:41 PM PDT 24
Peak memory 214340 kb
Host smart-29079cdf-9c63-4ba7-a265-42be98b1b1ab
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721157578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.
keymgr_shadow_reg_errors_with_csr_rw.1721157578
Directory /workspace/0.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_errors.4273663305
Short name T1065
Test name
Test status
Simulation time 254802044 ps
CPU time 3.9 seconds
Started Mar 26 02:40:32 PM PDT 24
Finished Mar 26 02:40:36 PM PDT 24
Peak memory 214068 kb
Host smart-8ceb1126-7c54-473b-907b-5ce3d01e779f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4273663305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_errors.4273663305
Directory /workspace/0.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/0.keymgr_tl_intg_err.398208210
Short name T196
Test name
Test status
Simulation time 156816050 ps
CPU time 5.58 seconds
Started Mar 26 02:40:33 PM PDT 24
Finished Mar 26 02:40:39 PM PDT 24
Peak memory 213984 kb
Host smart-29602ac2-fca5-4697-874b-5c0481f43e90
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398208210 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.keymgr_tl_intg_err.
398208210
Directory /workspace/0.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_aliasing.2833839798
Short name T1042
Test name
Test status
Simulation time 375672150 ps
CPU time 8.7 seconds
Started Mar 26 02:40:34 PM PDT 24
Finished Mar 26 02:40:43 PM PDT 24
Peak memory 205804 kb
Host smart-b752b43e-28a9-4f86-8f72-6e8f38981228
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833839798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_aliasing.2
833839798
Directory /workspace/1.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_bit_bash.2886637585
Short name T1024
Test name
Test status
Simulation time 483090604 ps
CPU time 8.12 seconds
Started Mar 26 02:40:33 PM PDT 24
Finished Mar 26 02:40:41 PM PDT 24
Peak memory 205780 kb
Host smart-22fce914-4474-4b1b-bcc3-9a9f6d635949
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2886637585 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_bit_bash.2
886637585
Directory /workspace/1.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_hw_reset.3879128803
Short name T1057
Test name
Test status
Simulation time 35686297 ps
CPU time 1.19 seconds
Started Mar 26 02:40:33 PM PDT 24
Finished Mar 26 02:40:34 PM PDT 24
Peak memory 205880 kb
Host smart-9e382769-b025-4b7c-acc4-ea4e801c19d6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3879128803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_csr_hw_reset.3
879128803
Directory /workspace/1.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_csr_mem_rw_with_rand_reset.3102453751
Short name T932
Test name
Test status
Simulation time 860267371 ps
CPU time 1.86 seconds
Started Mar 26 02:40:34 PM PDT 24
Finished Mar 26 02:40:36 PM PDT 24
Peak memory 206088 kb
Host smart-bb5c4965-d726-47f3-b745-73ea3f0f6292
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102453751 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 1.keymgr_csr_mem_rw_with_rand_reset.3102453751
Directory /workspace/1.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_intr_test.129184806
Short name T1043
Test name
Test status
Simulation time 9745365 ps
CPU time 0.71 seconds
Started Mar 26 02:40:31 PM PDT 24
Finished Mar 26 02:40:32 PM PDT 24
Peak memory 205460 kb
Host smart-9d4cdeb8-69b1-4dd8-8627-44f18fd99352
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=129184806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_intr_test.129184806
Directory /workspace/1.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_same_csr_outstanding.2935235503
Short name T149
Test name
Test status
Simulation time 199246127 ps
CPU time 1.61 seconds
Started Mar 26 02:40:32 PM PDT 24
Finished Mar 26 02:40:34 PM PDT 24
Peak memory 205856 kb
Host smart-69fe1428-5b1b-4b89-be62-3d6077250a0e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935235503 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_sa
me_csr_outstanding.2935235503
Directory /workspace/1.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors.2893283896
Short name T119
Test name
Test status
Simulation time 305657150 ps
CPU time 2.83 seconds
Started Mar 26 02:40:36 PM PDT 24
Finished Mar 26 02:40:39 PM PDT 24
Peak memory 222528 kb
Host smart-ae47f8c2-a527-4849-91ad-c0651500b631
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2893283896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_shado
w_reg_errors.2893283896
Directory /workspace/1.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_shadow_reg_errors_with_csr_rw.2405608186
Short name T991
Test name
Test status
Simulation time 1173999307 ps
CPU time 5.8 seconds
Started Mar 26 02:40:35 PM PDT 24
Finished Mar 26 02:40:41 PM PDT 24
Peak memory 214276 kb
Host smart-63a5109a-6900-4b0d-b36b-2cbe0f09ab97
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2405608186 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.
keymgr_shadow_reg_errors_with_csr_rw.2405608186
Directory /workspace/1.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.keymgr_tl_errors.1966000101
Short name T1051
Test name
Test status
Simulation time 166596763 ps
CPU time 1.98 seconds
Started Mar 26 02:40:35 PM PDT 24
Finished Mar 26 02:40:37 PM PDT 24
Peak memory 205896 kb
Host smart-8a66f747-b804-4332-b6cd-4c887ce0cb83
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1966000101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.keymgr_tl_errors.1966000101
Directory /workspace/1.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_mem_rw_with_rand_reset.132290229
Short name T1000
Test name
Test status
Simulation time 167094310 ps
CPU time 1.73 seconds
Started Mar 26 02:40:51 PM PDT 24
Finished Mar 26 02:40:53 PM PDT 24
Peak memory 214112 kb
Host smart-b0202479-3e18-4422-b37a-1ac9e9170ad7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=132290229 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 10.keymgr_csr_mem_rw_with_rand_reset.132290229
Directory /workspace/10.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_csr_rw.571653468
Short name T1026
Test name
Test status
Simulation time 15097416 ps
CPU time 0.95 seconds
Started Mar 26 02:40:51 PM PDT 24
Finished Mar 26 02:40:52 PM PDT 24
Peak memory 205584 kb
Host smart-d21fb8c9-1ee1-4a42-8bd2-731a68070683
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571653468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_csr_rw.571653468
Directory /workspace/10.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_intr_test.337416046
Short name T919
Test name
Test status
Simulation time 27196613 ps
CPU time 0.78 seconds
Started Mar 26 02:40:50 PM PDT 24
Finished Mar 26 02:40:51 PM PDT 24
Peak memory 205464 kb
Host smart-46278c62-95cf-4b97-b686-2d51597069ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=337416046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_intr_test.337416046
Directory /workspace/10.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_same_csr_outstanding.289943927
Short name T925
Test name
Test status
Simulation time 87986332 ps
CPU time 2.02 seconds
Started Mar 26 02:40:51 PM PDT 24
Finished Mar 26 02:40:54 PM PDT 24
Peak memory 205808 kb
Host smart-ff52f3a8-8285-4e97-825e-9040c3b8cae6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289943927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_sa
me_csr_outstanding.289943927
Directory /workspace/10.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors.2604527621
Short name T1040
Test name
Test status
Simulation time 3505150417 ps
CPU time 35.72 seconds
Started Mar 26 02:40:50 PM PDT 24
Finished Mar 26 02:41:26 PM PDT 24
Peak memory 219072 kb
Host smart-3aa395ba-74a1-4b9d-a480-ba5614e8ad2c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2604527621 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_shad
ow_reg_errors.2604527621
Directory /workspace/10.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_shadow_reg_errors_with_csr_rw.3144305735
Short name T1029
Test name
Test status
Simulation time 327163114 ps
CPU time 4.71 seconds
Started Mar 26 02:40:51 PM PDT 24
Finished Mar 26 02:40:56 PM PDT 24
Peak memory 214268 kb
Host smart-a98528f8-8e57-43d9-8c1d-6f60aefdb317
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3144305735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.keymgr_shadow_reg_errors_with_csr_rw.3144305735
Directory /workspace/10.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_errors.3477176114
Short name T1034
Test name
Test status
Simulation time 463811939 ps
CPU time 3.39 seconds
Started Mar 26 02:40:51 PM PDT 24
Finished Mar 26 02:40:55 PM PDT 24
Peak memory 214104 kb
Host smart-a1d27345-1a38-4033-88f1-170b7440d370
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477176114 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_errors.3477176114
Directory /workspace/10.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.keymgr_tl_intg_err.3982658762
Short name T188
Test name
Test status
Simulation time 98426036 ps
CPU time 3.4 seconds
Started Mar 26 02:40:51 PM PDT 24
Finished Mar 26 02:40:55 PM PDT 24
Peak memory 209108 kb
Host smart-f25a0b85-8917-498c-82dd-0f2e44b1f7d0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3982658762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.keymgr_tl_intg_er
r.3982658762
Directory /workspace/10.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_mem_rw_with_rand_reset.1258185822
Short name T383
Test name
Test status
Simulation time 37802238 ps
CPU time 2.11 seconds
Started Mar 26 02:40:52 PM PDT 24
Finished Mar 26 02:40:54 PM PDT 24
Peak memory 214108 kb
Host smart-7bb634cc-20ee-4ab7-848f-18ca06a3bdb3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1258185822 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 11.keymgr_csr_mem_rw_with_rand_reset.1258185822
Directory /workspace/11.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_csr_rw.375582058
Short name T1039
Test name
Test status
Simulation time 10448496 ps
CPU time 0.92 seconds
Started Mar 26 02:41:13 PM PDT 24
Finished Mar 26 02:41:14 PM PDT 24
Peak memory 205584 kb
Host smart-63fc1ce0-5b84-47c7-b7e6-bcd8610d0b75
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=375582058 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_csr_rw.375582058
Directory /workspace/11.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_intr_test.1179316124
Short name T1012
Test name
Test status
Simulation time 7321022 ps
CPU time 0.73 seconds
Started Mar 26 02:40:51 PM PDT 24
Finished Mar 26 02:40:52 PM PDT 24
Peak memory 205440 kb
Host smart-ff8496ca-d60e-4ef7-8b8b-d7bf18ac96b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1179316124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_intr_test.1179316124
Directory /workspace/11.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_same_csr_outstanding.3905063764
Short name T150
Test name
Test status
Simulation time 38636287 ps
CPU time 1.57 seconds
Started Mar 26 02:40:53 PM PDT 24
Finished Mar 26 02:40:54 PM PDT 24
Peak memory 205752 kb
Host smart-15ecdea2-a2da-4544-ba33-0f4b5c26556d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3905063764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_s
ame_csr_outstanding.3905063764
Directory /workspace/11.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors.3427461445
Short name T121
Test name
Test status
Simulation time 131163672 ps
CPU time 3.06 seconds
Started Mar 26 02:40:53 PM PDT 24
Finished Mar 26 02:40:56 PM PDT 24
Peak memory 222416 kb
Host smart-564b503f-e28e-46d1-b8ad-d64dc1c0e108
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3427461445 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_shad
ow_reg_errors.3427461445
Directory /workspace/11.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_shadow_reg_errors_with_csr_rw.3023673560
Short name T967
Test name
Test status
Simulation time 73122862 ps
CPU time 3.54 seconds
Started Mar 26 02:40:52 PM PDT 24
Finished Mar 26 02:40:56 PM PDT 24
Peak memory 220316 kb
Host smart-ff996094-8e09-4781-bb04-6943248b3ab9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3023673560 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.keymgr_shadow_reg_errors_with_csr_rw.3023673560
Directory /workspace/11.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.keymgr_tl_errors.3393510378
Short name T993
Test name
Test status
Simulation time 466983273 ps
CPU time 4.17 seconds
Started Mar 26 02:40:50 PM PDT 24
Finished Mar 26 02:40:55 PM PDT 24
Peak memory 214012 kb
Host smart-cf6599b1-3e87-457b-b3cf-b898b8a63928
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393510378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.keymgr_tl_errors.3393510378
Directory /workspace/11.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_mem_rw_with_rand_reset.3040979141
Short name T1076
Test name
Test status
Simulation time 37531836 ps
CPU time 2.66 seconds
Started Mar 26 02:40:56 PM PDT 24
Finished Mar 26 02:40:59 PM PDT 24
Peak memory 219792 kb
Host smart-476d3d83-cf02-498b-900f-781e48d7ad0c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3040979141 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 12.keymgr_csr_mem_rw_with_rand_reset.3040979141
Directory /workspace/12.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_csr_rw.2297125446
Short name T1005
Test name
Test status
Simulation time 12865491 ps
CPU time 1.05 seconds
Started Mar 26 02:40:55 PM PDT 24
Finished Mar 26 02:40:56 PM PDT 24
Peak memory 205704 kb
Host smart-31466fdd-5ff7-4c31-b920-5399f60c0bad
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2297125446 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_csr_rw.2297125446
Directory /workspace/12.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_intr_test.1620011789
Short name T1046
Test name
Test status
Simulation time 16781073 ps
CPU time 0.83 seconds
Started Mar 26 02:40:56 PM PDT 24
Finished Mar 26 02:40:57 PM PDT 24
Peak memory 205480 kb
Host smart-5ed0e21d-c975-4672-acda-3fcc32a742fd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1620011789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_intr_test.1620011789
Directory /workspace/12.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_same_csr_outstanding.3932560454
Short name T1074
Test name
Test status
Simulation time 164154336 ps
CPU time 2.47 seconds
Started Mar 26 02:40:56 PM PDT 24
Finished Mar 26 02:40:59 PM PDT 24
Peak memory 205928 kb
Host smart-db22d0b6-8dc5-4b44-b4ca-0a1684ac2145
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3932560454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_s
ame_csr_outstanding.3932560454
Directory /workspace/12.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors.357415822
Short name T113
Test name
Test status
Simulation time 341638658 ps
CPU time 3.63 seconds
Started Mar 26 02:40:51 PM PDT 24
Finished Mar 26 02:40:55 PM PDT 24
Peak memory 214256 kb
Host smart-4cb8f11d-34ce-44dd-b787-61ee89d3c57b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=357415822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_shado
w_reg_errors.357415822
Directory /workspace/12.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_shadow_reg_errors_with_csr_rw.1490559650
Short name T953
Test name
Test status
Simulation time 1428437695 ps
CPU time 15.11 seconds
Started Mar 26 02:40:51 PM PDT 24
Finished Mar 26 02:41:06 PM PDT 24
Peak memory 214508 kb
Host smart-c888c07e-f4c4-46fe-b8a5-f55b2b034a72
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1490559650 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12
.keymgr_shadow_reg_errors_with_csr_rw.1490559650
Directory /workspace/12.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_errors.3024166652
Short name T920
Test name
Test status
Simulation time 445448621 ps
CPU time 4.08 seconds
Started Mar 26 02:40:53 PM PDT 24
Finished Mar 26 02:40:57 PM PDT 24
Peak memory 217052 kb
Host smart-a62d614e-7a85-46a9-9ea7-1679c7687714
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3024166652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_errors.3024166652
Directory /workspace/12.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.keymgr_tl_intg_err.214053733
Short name T961
Test name
Test status
Simulation time 260810130 ps
CPU time 8.56 seconds
Started Mar 26 02:40:56 PM PDT 24
Finished Mar 26 02:41:05 PM PDT 24
Peak memory 208884 kb
Host smart-aa6e9d61-eade-45e1-b64e-b0df780cd97f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=214053733 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.keymgr_tl_intg_err
.214053733
Directory /workspace/12.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_mem_rw_with_rand_reset.3762439786
Short name T1045
Test name
Test status
Simulation time 47558118 ps
CPU time 1.54 seconds
Started Mar 26 02:40:49 PM PDT 24
Finished Mar 26 02:40:51 PM PDT 24
Peak memory 214092 kb
Host smart-e5b81de0-e2dc-4fcc-97aa-8ec52a272968
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3762439786 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 13.keymgr_csr_mem_rw_with_rand_reset.3762439786
Directory /workspace/13.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_csr_rw.1114149216
Short name T965
Test name
Test status
Simulation time 23907677 ps
CPU time 1.14 seconds
Started Mar 26 02:40:52 PM PDT 24
Finished Mar 26 02:40:54 PM PDT 24
Peak memory 205836 kb
Host smart-85f4c6b7-cf78-4b2e-9373-aece5f82e7f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1114149216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_csr_rw.1114149216
Directory /workspace/13.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_intr_test.1386119532
Short name T924
Test name
Test status
Simulation time 14335191 ps
CPU time 0.72 seconds
Started Mar 26 02:40:56 PM PDT 24
Finished Mar 26 02:40:57 PM PDT 24
Peak memory 205404 kb
Host smart-20b2ceee-3f71-4630-a776-e226f0ecf9fb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1386119532 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_intr_test.1386119532
Directory /workspace/13.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_same_csr_outstanding.378272255
Short name T987
Test name
Test status
Simulation time 34851714 ps
CPU time 2.08 seconds
Started Mar 26 02:40:50 PM PDT 24
Finished Mar 26 02:40:53 PM PDT 24
Peak memory 205964 kb
Host smart-c1dd1200-5df7-476e-8492-59fd8dc3ac03
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=378272255 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_sa
me_csr_outstanding.378272255
Directory /workspace/13.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors.2711810975
Short name T954
Test name
Test status
Simulation time 197128602 ps
CPU time 6.01 seconds
Started Mar 26 02:40:55 PM PDT 24
Finished Mar 26 02:41:02 PM PDT 24
Peak memory 214348 kb
Host smart-9559bca7-c855-4830-be24-ec8aa02cd6f3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711810975 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_shad
ow_reg_errors.2711810975
Directory /workspace/13.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_shadow_reg_errors_with_csr_rw.4074408704
Short name T942
Test name
Test status
Simulation time 183865602 ps
CPU time 5.3 seconds
Started Mar 26 02:40:56 PM PDT 24
Finished Mar 26 02:41:01 PM PDT 24
Peak memory 214220 kb
Host smart-79745411-f0f7-4ab1-b128-c7a9645308d3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4074408704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13
.keymgr_shadow_reg_errors_with_csr_rw.4074408704
Directory /workspace/13.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_errors.2097341833
Short name T934
Test name
Test status
Simulation time 260134005 ps
CPU time 4.99 seconds
Started Mar 26 02:40:56 PM PDT 24
Finished Mar 26 02:41:02 PM PDT 24
Peak memory 214052 kb
Host smart-b07a793e-bbe7-4a8e-8d4e-4542e52af334
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2097341833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_errors.2097341833
Directory /workspace/13.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.keymgr_tl_intg_err.513298789
Short name T197
Test name
Test status
Simulation time 362948460 ps
CPU time 8.67 seconds
Started Mar 26 02:40:55 PM PDT 24
Finished Mar 26 02:41:03 PM PDT 24
Peak memory 213908 kb
Host smart-587c5b8a-6b39-466b-8e72-0365c5849d9a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=513298789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.keymgr_tl_intg_err
.513298789
Directory /workspace/13.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_mem_rw_with_rand_reset.1479617421
Short name T950
Test name
Test status
Simulation time 50494108 ps
CPU time 2.21 seconds
Started Mar 26 02:40:51 PM PDT 24
Finished Mar 26 02:40:53 PM PDT 24
Peak memory 214052 kb
Host smart-0ec8d132-a428-482f-b787-fd8bdf2b8193
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1479617421 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 14.keymgr_csr_mem_rw_with_rand_reset.1479617421
Directory /workspace/14.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_csr_rw.2692013545
Short name T1064
Test name
Test status
Simulation time 50193921 ps
CPU time 1.26 seconds
Started Mar 26 02:40:51 PM PDT 24
Finished Mar 26 02:40:52 PM PDT 24
Peak memory 205792 kb
Host smart-571310fe-181a-4142-8bfb-a0ca0a79b6c0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2692013545 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_csr_rw.2692013545
Directory /workspace/14.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_intr_test.738912419
Short name T990
Test name
Test status
Simulation time 12997602 ps
CPU time 0.75 seconds
Started Mar 26 02:40:49 PM PDT 24
Finished Mar 26 02:40:50 PM PDT 24
Peak memory 205460 kb
Host smart-475286b2-0fd6-4f35-8045-6b2346564ac7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=738912419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_intr_test.738912419
Directory /workspace/14.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_same_csr_outstanding.1724595252
Short name T155
Test name
Test status
Simulation time 179555586 ps
CPU time 1.73 seconds
Started Mar 26 02:40:50 PM PDT 24
Finished Mar 26 02:40:52 PM PDT 24
Peak memory 205796 kb
Host smart-fd76a628-f2d9-43fe-a2f1-09471564538e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1724595252 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_s
ame_csr_outstanding.1724595252
Directory /workspace/14.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors.22924592
Short name T975
Test name
Test status
Simulation time 868748757 ps
CPU time 4 seconds
Started Mar 26 02:40:51 PM PDT 24
Finished Mar 26 02:40:55 PM PDT 24
Peak memory 214220 kb
Host smart-b28dd59e-a8c3-4c0d-991b-a3ea150beba0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22924592 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_c
ommon_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_shadow
_reg_errors.22924592
Directory /workspace/14.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_shadow_reg_errors_with_csr_rw.2796350732
Short name T955
Test name
Test status
Simulation time 87118548 ps
CPU time 4.59 seconds
Started Mar 26 02:40:50 PM PDT 24
Finished Mar 26 02:40:55 PM PDT 24
Peak memory 214396 kb
Host smart-efc767ad-9eec-44db-8d24-66e99f4ff9f5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2796350732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.keymgr_shadow_reg_errors_with_csr_rw.2796350732
Directory /workspace/14.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_errors.1558980641
Short name T957
Test name
Test status
Simulation time 102465426 ps
CPU time 2.46 seconds
Started Mar 26 02:40:51 PM PDT 24
Finished Mar 26 02:40:54 PM PDT 24
Peak memory 217004 kb
Host smart-cef3bc47-6354-472d-ad89-4a352c3e6fb3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558980641 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_errors.1558980641
Directory /workspace/14.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.keymgr_tl_intg_err.1786434365
Short name T183
Test name
Test status
Simulation time 562616096 ps
CPU time 14.67 seconds
Started Mar 26 02:40:50 PM PDT 24
Finished Mar 26 02:41:05 PM PDT 24
Peak memory 209308 kb
Host smart-5d2dd3e9-883f-4d98-bb45-470b4e8262d7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1786434365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.keymgr_tl_intg_er
r.1786434365
Directory /workspace/14.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_mem_rw_with_rand_reset.266245632
Short name T1014
Test name
Test status
Simulation time 35839190 ps
CPU time 1.72 seconds
Started Mar 26 02:40:56 PM PDT 24
Finished Mar 26 02:40:58 PM PDT 24
Peak memory 206004 kb
Host smart-37a8aa15-b9df-4cd3-bce3-acd925a55030
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=266245632 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 15.keymgr_csr_mem_rw_with_rand_reset.266245632
Directory /workspace/15.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_csr_rw.2452798003
Short name T1052
Test name
Test status
Simulation time 56760657 ps
CPU time 1.33 seconds
Started Mar 26 02:40:53 PM PDT 24
Finished Mar 26 02:40:55 PM PDT 24
Peak memory 205788 kb
Host smart-6ddf8865-3c54-4aad-afaa-7559421cd8c9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452798003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_csr_rw.2452798003
Directory /workspace/15.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_intr_test.2760600162
Short name T922
Test name
Test status
Simulation time 49625631 ps
CPU time 0.81 seconds
Started Mar 26 02:40:48 PM PDT 24
Finished Mar 26 02:40:49 PM PDT 24
Peak memory 205452 kb
Host smart-71234f5a-a455-44ff-b339-ebe55c881f54
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2760600162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_intr_test.2760600162
Directory /workspace/15.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_same_csr_outstanding.3493207157
Short name T977
Test name
Test status
Simulation time 92811548 ps
CPU time 1.58 seconds
Started Mar 26 02:40:57 PM PDT 24
Finished Mar 26 02:40:59 PM PDT 24
Peak memory 205880 kb
Host smart-fca33358-d31a-409e-b9a0-5cbb087477a0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3493207157 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_s
ame_csr_outstanding.3493207157
Directory /workspace/15.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors.4123632515
Short name T968
Test name
Test status
Simulation time 209135597 ps
CPU time 2.2 seconds
Started Mar 26 02:40:49 PM PDT 24
Finished Mar 26 02:40:51 PM PDT 24
Peak memory 214356 kb
Host smart-65288ffe-ebbd-401f-b646-084f3fd198d2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4123632515 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_shad
ow_reg_errors.4123632515
Directory /workspace/15.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_shadow_reg_errors_with_csr_rw.1002480661
Short name T1008
Test name
Test status
Simulation time 2631802844 ps
CPU time 5.55 seconds
Started Mar 26 02:40:53 PM PDT 24
Finished Mar 26 02:40:59 PM PDT 24
Peak memory 222612 kb
Host smart-812dbf8c-5b41-476f-8e53-02902a91a5c5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1002480661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.keymgr_shadow_reg_errors_with_csr_rw.1002480661
Directory /workspace/15.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_errors.3637734218
Short name T1059
Test name
Test status
Simulation time 105589697 ps
CPU time 2.89 seconds
Started Mar 26 02:40:53 PM PDT 24
Finished Mar 26 02:40:56 PM PDT 24
Peak memory 214048 kb
Host smart-3890464c-0441-469d-b39a-7f6a77387260
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3637734218 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_errors.3637734218
Directory /workspace/15.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.keymgr_tl_intg_err.807054242
Short name T379
Test name
Test status
Simulation time 153545814 ps
CPU time 5.24 seconds
Started Mar 26 02:40:48 PM PDT 24
Finished Mar 26 02:40:54 PM PDT 24
Peak memory 208980 kb
Host smart-2d5e2c40-6aae-4297-b50b-24a22ee940e1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=807054242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.keymgr_tl_intg_err
.807054242
Directory /workspace/15.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_mem_rw_with_rand_reset.1468006767
Short name T165
Test name
Test status
Simulation time 151405617 ps
CPU time 2.64 seconds
Started Mar 26 02:41:02 PM PDT 24
Finished Mar 26 02:41:05 PM PDT 24
Peak memory 214132 kb
Host smart-73461650-6eb6-486c-a6c2-075a12798235
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1468006767 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 16.keymgr_csr_mem_rw_with_rand_reset.1468006767
Directory /workspace/16.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_csr_rw.3604027751
Short name T980
Test name
Test status
Simulation time 25542498 ps
CPU time 1.13 seconds
Started Mar 26 02:41:03 PM PDT 24
Finished Mar 26 02:41:04 PM PDT 24
Peak memory 205816 kb
Host smart-0f1c5074-3901-4702-a215-285919e4d493
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3604027751 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_csr_rw.3604027751
Directory /workspace/16.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_intr_test.3910655452
Short name T1004
Test name
Test status
Simulation time 14355123 ps
CPU time 0.74 seconds
Started Mar 26 02:40:59 PM PDT 24
Finished Mar 26 02:41:01 PM PDT 24
Peak memory 205356 kb
Host smart-a2e0684f-bf01-4e38-9ade-c66a2621d640
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3910655452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_intr_test.3910655452
Directory /workspace/16.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_same_csr_outstanding.2694097522
Short name T964
Test name
Test status
Simulation time 26137131 ps
CPU time 1.88 seconds
Started Mar 26 02:40:58 PM PDT 24
Finished Mar 26 02:41:00 PM PDT 24
Peak memory 205828 kb
Host smart-2124c231-963e-403c-bf41-7b015ad18603
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694097522 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_s
ame_csr_outstanding.2694097522
Directory /workspace/16.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors.3143254189
Short name T982
Test name
Test status
Simulation time 137164608 ps
CPU time 4.41 seconds
Started Mar 26 02:41:06 PM PDT 24
Finished Mar 26 02:41:11 PM PDT 24
Peak memory 214272 kb
Host smart-81f5f8b6-7c88-43f2-a07e-8648fbd10839
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3143254189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_shad
ow_reg_errors.3143254189
Directory /workspace/16.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_shadow_reg_errors_with_csr_rw.3415398351
Short name T117
Test name
Test status
Simulation time 218520781 ps
CPU time 9.56 seconds
Started Mar 26 02:40:57 PM PDT 24
Finished Mar 26 02:41:07 PM PDT 24
Peak memory 214404 kb
Host smart-222a7824-1caf-4b1b-84fe-50b389a49ff6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415398351 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.keymgr_shadow_reg_errors_with_csr_rw.3415398351
Directory /workspace/16.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.keymgr_tl_errors.329194885
Short name T1063
Test name
Test status
Simulation time 89083761 ps
CPU time 3.38 seconds
Started Mar 26 02:40:57 PM PDT 24
Finished Mar 26 02:41:01 PM PDT 24
Peak memory 214032 kb
Host smart-d1489b78-ba48-439b-91d7-03bb374021c8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329194885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.keymgr_tl_errors.329194885
Directory /workspace/16.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_mem_rw_with_rand_reset.2984283051
Short name T385
Test name
Test status
Simulation time 33825214 ps
CPU time 1.39 seconds
Started Mar 26 02:40:58 PM PDT 24
Finished Mar 26 02:41:00 PM PDT 24
Peak memory 214088 kb
Host smart-d77a1b60-1ca3-4271-8c63-bb6f14c5d6c7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2984283051 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 17.keymgr_csr_mem_rw_with_rand_reset.2984283051
Directory /workspace/17.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_csr_rw.3388393012
Short name T156
Test name
Test status
Simulation time 11601533 ps
CPU time 1.18 seconds
Started Mar 26 02:41:00 PM PDT 24
Finished Mar 26 02:41:01 PM PDT 24
Peak memory 205908 kb
Host smart-d610d2aa-f83f-4767-aedb-7cc681947800
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3388393012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_csr_rw.3388393012
Directory /workspace/17.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_intr_test.1028899773
Short name T1070
Test name
Test status
Simulation time 10325168 ps
CPU time 0.71 seconds
Started Mar 26 02:40:56 PM PDT 24
Finished Mar 26 02:40:58 PM PDT 24
Peak memory 205460 kb
Host smart-7073df32-5cff-43e7-bad9-ba2a78301bae
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028899773 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_intr_test.1028899773
Directory /workspace/17.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_same_csr_outstanding.1293820145
Short name T970
Test name
Test status
Simulation time 271081000 ps
CPU time 1.73 seconds
Started Mar 26 02:41:06 PM PDT 24
Finished Mar 26 02:41:08 PM PDT 24
Peak memory 205908 kb
Host smart-6becd223-4e6a-4623-ab71-873a0fbd750a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1293820145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_s
ame_csr_outstanding.1293820145
Directory /workspace/17.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors.938857115
Short name T963
Test name
Test status
Simulation time 60545740 ps
CPU time 1.92 seconds
Started Mar 26 02:40:59 PM PDT 24
Finished Mar 26 02:41:02 PM PDT 24
Peak memory 214288 kb
Host smart-3a36a20f-bd41-48bd-9343-275a922d9075
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=938857115 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_shado
w_reg_errors.938857115
Directory /workspace/17.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_shadow_reg_errors_with_csr_rw.334200575
Short name T114
Test name
Test status
Simulation time 2608281678 ps
CPU time 9.36 seconds
Started Mar 26 02:41:01 PM PDT 24
Finished Mar 26 02:41:10 PM PDT 24
Peak memory 214372 kb
Host smart-46ee0986-3416-422d-9f32-82e07db4dc02
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=334200575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.
keymgr_shadow_reg_errors_with_csr_rw.334200575
Directory /workspace/17.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_errors.2885985200
Short name T1048
Test name
Test status
Simulation time 228087379 ps
CPU time 2.71 seconds
Started Mar 26 02:41:00 PM PDT 24
Finished Mar 26 02:41:03 PM PDT 24
Peak memory 213948 kb
Host smart-3c0649e4-1d4b-4992-a4ef-250a661ae76b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2885985200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_errors.2885985200
Directory /workspace/17.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.keymgr_tl_intg_err.2306065696
Short name T997
Test name
Test status
Simulation time 75114521 ps
CPU time 3.62 seconds
Started Mar 26 02:41:00 PM PDT 24
Finished Mar 26 02:41:04 PM PDT 24
Peak memory 214072 kb
Host smart-568939fb-12f2-49ba-80a2-6d044140092e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306065696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.keymgr_tl_intg_er
r.2306065696
Directory /workspace/17.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_mem_rw_with_rand_reset.1358726068
Short name T981
Test name
Test status
Simulation time 26977604 ps
CPU time 1.48 seconds
Started Mar 26 02:41:00 PM PDT 24
Finished Mar 26 02:41:02 PM PDT 24
Peak memory 214008 kb
Host smart-dec3beeb-0247-41ad-bb4a-059775ec3a0e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1358726068 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 18.keymgr_csr_mem_rw_with_rand_reset.1358726068
Directory /workspace/18.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_csr_rw.2960921526
Short name T930
Test name
Test status
Simulation time 55585488 ps
CPU time 1.26 seconds
Started Mar 26 02:40:59 PM PDT 24
Finished Mar 26 02:41:00 PM PDT 24
Peak memory 205788 kb
Host smart-89ecf339-1c12-492d-8d5e-ce756bd9902f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2960921526 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_csr_rw.2960921526
Directory /workspace/18.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_intr_test.2278442557
Short name T918
Test name
Test status
Simulation time 37008472 ps
CPU time 0.82 seconds
Started Mar 26 02:40:56 PM PDT 24
Finished Mar 26 02:40:58 PM PDT 24
Peak memory 205548 kb
Host smart-71e0295e-76bc-424c-9869-817639c2dc91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278442557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_intr_test.2278442557
Directory /workspace/18.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_same_csr_outstanding.819962307
Short name T972
Test name
Test status
Simulation time 20535634 ps
CPU time 1.66 seconds
Started Mar 26 02:41:00 PM PDT 24
Finished Mar 26 02:41:02 PM PDT 24
Peak memory 205740 kb
Host smart-400ed531-172e-4199-a42d-c9b1c5a1512e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=819962307 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_sa
me_csr_outstanding.819962307
Directory /workspace/18.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors.1716049806
Short name T120
Test name
Test status
Simulation time 481017396 ps
CPU time 4.35 seconds
Started Mar 26 02:40:59 PM PDT 24
Finished Mar 26 02:41:04 PM PDT 24
Peak memory 214276 kb
Host smart-9e789ad1-b1da-47d1-a5ee-d3de8081a5ac
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1716049806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_shad
ow_reg_errors.1716049806
Directory /workspace/18.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_shadow_reg_errors_with_csr_rw.3326054768
Short name T1038
Test name
Test status
Simulation time 1421717406 ps
CPU time 6.92 seconds
Started Mar 26 02:40:59 PM PDT 24
Finished Mar 26 02:41:07 PM PDT 24
Peak memory 214536 kb
Host smart-85079168-8fc8-43a5-8ba3-c3d01195bc08
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3326054768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.keymgr_shadow_reg_errors_with_csr_rw.3326054768
Directory /workspace/18.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_errors.1255640345
Short name T935
Test name
Test status
Simulation time 144345260 ps
CPU time 3.17 seconds
Started Mar 26 02:40:56 PM PDT 24
Finished Mar 26 02:41:00 PM PDT 24
Peak memory 214176 kb
Host smart-499e42f7-c5c1-43f0-b344-346594e854e5
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255640345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_errors.1255640345
Directory /workspace/18.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.keymgr_tl_intg_err.1372768306
Short name T941
Test name
Test status
Simulation time 200195887 ps
CPU time 4.8 seconds
Started Mar 26 02:41:00 PM PDT 24
Finished Mar 26 02:41:05 PM PDT 24
Peak memory 209316 kb
Host smart-b0dd30b2-a3ab-477e-9928-19d8264b2801
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1372768306 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.keymgr_tl_intg_er
r.1372768306
Directory /workspace/18.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_mem_rw_with_rand_reset.1317496212
Short name T1061
Test name
Test status
Simulation time 51999876 ps
CPU time 2.21 seconds
Started Mar 26 02:41:00 PM PDT 24
Finished Mar 26 02:41:02 PM PDT 24
Peak memory 214020 kb
Host smart-95478927-9d2a-4482-af9f-1ad1bc13a40b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317496212 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 19.keymgr_csr_mem_rw_with_rand_reset.1317496212
Directory /workspace/19.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_csr_rw.1988505711
Short name T928
Test name
Test status
Simulation time 20414444 ps
CPU time 0.92 seconds
Started Mar 26 02:40:59 PM PDT 24
Finished Mar 26 02:41:01 PM PDT 24
Peak memory 205596 kb
Host smart-4b49f85f-4a56-45e4-be47-d140a4e07b4e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1988505711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_csr_rw.1988505711
Directory /workspace/19.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_intr_test.675974444
Short name T943
Test name
Test status
Simulation time 23096756 ps
CPU time 0.81 seconds
Started Mar 26 02:41:02 PM PDT 24
Finished Mar 26 02:41:02 PM PDT 24
Peak memory 205524 kb
Host smart-35d861a2-ff6d-4780-9b73-c22e02c955d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=675974444 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_intr_test.675974444
Directory /workspace/19.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_same_csr_outstanding.2229852680
Short name T1023
Test name
Test status
Simulation time 209744360 ps
CPU time 3.97 seconds
Started Mar 26 02:41:07 PM PDT 24
Finished Mar 26 02:41:11 PM PDT 24
Peak memory 205840 kb
Host smart-e266c775-a779-459c-b166-f1d4c26a8123
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229852680 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_s
ame_csr_outstanding.2229852680
Directory /workspace/19.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_shadow_reg_errors.3802629468
Short name T1050
Test name
Test status
Simulation time 872085310 ps
CPU time 2.05 seconds
Started Mar 26 02:41:00 PM PDT 24
Finished Mar 26 02:41:02 PM PDT 24
Peak memory 219264 kb
Host smart-e160ddd1-f6ea-42ac-816b-df9ce83b2be5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3802629468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_shad
ow_reg_errors.3802629468
Directory /workspace/19.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_errors.1005630414
Short name T1001
Test name
Test status
Simulation time 142818109 ps
CPU time 5.48 seconds
Started Mar 26 02:41:00 PM PDT 24
Finished Mar 26 02:41:06 PM PDT 24
Peak memory 214032 kb
Host smart-2015d028-f5f0-4aef-8210-2f209bd91827
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1005630414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_errors.1005630414
Directory /workspace/19.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.keymgr_tl_intg_err.2711640869
Short name T195
Test name
Test status
Simulation time 363945053 ps
CPU time 9.5 seconds
Started Mar 26 02:40:57 PM PDT 24
Finished Mar 26 02:41:07 PM PDT 24
Peak memory 209488 kb
Host smart-901d53d3-ac4f-4da8-b794-70c9745a8c63
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711640869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.keymgr_tl_intg_er
r.2711640869
Directory /workspace/19.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_aliasing.3575168958
Short name T1032
Test name
Test status
Simulation time 265968312 ps
CPU time 4.61 seconds
Started Mar 26 02:40:35 PM PDT 24
Finished Mar 26 02:40:40 PM PDT 24
Peak memory 205924 kb
Host smart-c9796291-82bf-4cc4-8bed-4fa0a2a35949
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3575168958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_aliasing.3
575168958
Directory /workspace/2.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_bit_bash.1357154564
Short name T931
Test name
Test status
Simulation time 3427159589 ps
CPU time 25.66 seconds
Started Mar 26 02:40:34 PM PDT 24
Finished Mar 26 02:40:59 PM PDT 24
Peak memory 205900 kb
Host smart-54f16cd7-b279-4c0d-b39c-06eadc17d76b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1357154564 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_bit_bash.1
357154564
Directory /workspace/2.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_hw_reset.3079381216
Short name T974
Test name
Test status
Simulation time 122118681 ps
CPU time 1.11 seconds
Started Mar 26 02:40:32 PM PDT 24
Finished Mar 26 02:40:33 PM PDT 24
Peak memory 205504 kb
Host smart-a903f52d-25fb-4253-8c7d-9a558f734b05
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3079381216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_hw_reset.3
079381216
Directory /workspace/2.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_mem_rw_with_rand_reset.2336063500
Short name T929
Test name
Test status
Simulation time 108563708 ps
CPU time 2.08 seconds
Started Mar 26 02:40:35 PM PDT 24
Finished Mar 26 02:40:37 PM PDT 24
Peak memory 222264 kb
Host smart-641c9ab7-945b-44d5-b37c-9bcabf62ab9e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2336063500 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 2.keymgr_csr_mem_rw_with_rand_reset.2336063500
Directory /workspace/2.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_csr_rw.115162016
Short name T154
Test name
Test status
Simulation time 60023795 ps
CPU time 0.92 seconds
Started Mar 26 02:40:35 PM PDT 24
Finished Mar 26 02:40:36 PM PDT 24
Peak memory 205588 kb
Host smart-15863c83-8565-4659-a14b-a244d3e0bb2c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115162016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_csr_rw.115162016
Directory /workspace/2.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_intr_test.2606578080
Short name T947
Test name
Test status
Simulation time 24820279 ps
CPU time 0.81 seconds
Started Mar 26 02:40:35 PM PDT 24
Finished Mar 26 02:40:36 PM PDT 24
Peak memory 205548 kb
Host smart-80fda42c-252f-40bb-afd8-cbcfae4ed927
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2606578080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_intr_test.2606578080
Directory /workspace/2.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_same_csr_outstanding.2465074830
Short name T985
Test name
Test status
Simulation time 241521168 ps
CPU time 1.63 seconds
Started Mar 26 02:40:33 PM PDT 24
Finished Mar 26 02:40:35 PM PDT 24
Peak memory 205872 kb
Host smart-0996249b-6e6b-4a14-9ba7-033e70f3d341
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465074830 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_sa
me_csr_outstanding.2465074830
Directory /workspace/2.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors.2074820834
Short name T1007
Test name
Test status
Simulation time 82847851 ps
CPU time 3.03 seconds
Started Mar 26 02:40:31 PM PDT 24
Finished Mar 26 02:40:35 PM PDT 24
Peak memory 222484 kb
Host smart-608f1070-8c1e-4529-ae43-154c25729951
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074820834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_shado
w_reg_errors.2074820834
Directory /workspace/2.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_shadow_reg_errors_with_csr_rw.3050776900
Short name T1003
Test name
Test status
Simulation time 457597037 ps
CPU time 13.14 seconds
Started Mar 26 02:40:33 PM PDT 24
Finished Mar 26 02:40:46 PM PDT 24
Peak memory 214308 kb
Host smart-7ed3a3de-7760-44ab-88b6-d3db05fc6d30
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3050776900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
keymgr_shadow_reg_errors_with_csr_rw.3050776900
Directory /workspace/2.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.keymgr_tl_errors.1690610093
Short name T1056
Test name
Test status
Simulation time 234145076 ps
CPU time 2.83 seconds
Started Mar 26 02:40:35 PM PDT 24
Finished Mar 26 02:40:38 PM PDT 24
Peak memory 213968 kb
Host smart-0b02ddca-e0fd-4acd-a614-898354dae5fc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1690610093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.keymgr_tl_errors.1690610093
Directory /workspace/2.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.keymgr_intr_test.3141838128
Short name T1054
Test name
Test status
Simulation time 74867161 ps
CPU time 0.77 seconds
Started Mar 26 02:40:58 PM PDT 24
Finished Mar 26 02:41:00 PM PDT 24
Peak memory 205540 kb
Host smart-fe7e85ef-6450-4e76-b63d-4df4e76a9667
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3141838128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.keymgr_intr_test.3141838128
Directory /workspace/20.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.keymgr_intr_test.2707256147
Short name T1006
Test name
Test status
Simulation time 12363090 ps
CPU time 0.93 seconds
Started Mar 26 02:41:07 PM PDT 24
Finished Mar 26 02:41:08 PM PDT 24
Peak memory 205544 kb
Host smart-2e45dbaf-b2cd-4eda-bcf9-fb7ade4f9b7d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2707256147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.keymgr_intr_test.2707256147
Directory /workspace/21.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.keymgr_intr_test.2241381214
Short name T923
Test name
Test status
Simulation time 9659340 ps
CPU time 0.79 seconds
Started Mar 26 02:41:00 PM PDT 24
Finished Mar 26 02:41:01 PM PDT 24
Peak memory 205516 kb
Host smart-9dff2c89-1ab5-4922-a86b-e28a61c0496a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2241381214 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.keymgr_intr_test.2241381214
Directory /workspace/22.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.keymgr_intr_test.2583350120
Short name T976
Test name
Test status
Simulation time 34651444 ps
CPU time 0.71 seconds
Started Mar 26 02:40:59 PM PDT 24
Finished Mar 26 02:41:01 PM PDT 24
Peak memory 205452 kb
Host smart-7b115c31-bc10-439e-af9f-731da71da9b5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2583350120 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.keymgr_intr_test.2583350120
Directory /workspace/23.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.keymgr_intr_test.3106493784
Short name T1066
Test name
Test status
Simulation time 18220936 ps
CPU time 0.89 seconds
Started Mar 26 02:41:02 PM PDT 24
Finished Mar 26 02:41:03 PM PDT 24
Peak memory 205448 kb
Host smart-70a03ba7-6b35-47d3-943d-c263eeefc6ad
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3106493784 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.keymgr_intr_test.3106493784
Directory /workspace/24.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.keymgr_intr_test.2430469762
Short name T988
Test name
Test status
Simulation time 42123160 ps
CPU time 0.72 seconds
Started Mar 26 02:40:59 PM PDT 24
Finished Mar 26 02:41:01 PM PDT 24
Peak memory 205560 kb
Host smart-7fa8c815-67ff-4e1c-a50a-2f3993a69d87
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2430469762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.keymgr_intr_test.2430469762
Directory /workspace/25.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.keymgr_intr_test.620289837
Short name T945
Test name
Test status
Simulation time 37575692 ps
CPU time 0.69 seconds
Started Mar 26 02:41:13 PM PDT 24
Finished Mar 26 02:41:14 PM PDT 24
Peak memory 205468 kb
Host smart-a76e77e1-3061-4e5e-9b68-c5cfddf3d763
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=620289837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.keymgr_intr_test.620289837
Directory /workspace/26.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.keymgr_intr_test.1572114766
Short name T1055
Test name
Test status
Simulation time 32389426 ps
CPU time 0.74 seconds
Started Mar 26 02:41:08 PM PDT 24
Finished Mar 26 02:41:10 PM PDT 24
Peak memory 205456 kb
Host smart-3b2ef78a-67fb-4bc3-a673-7c53dd38d96d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1572114766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.keymgr_intr_test.1572114766
Directory /workspace/27.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.keymgr_intr_test.2246471930
Short name T927
Test name
Test status
Simulation time 13321962 ps
CPU time 0.88 seconds
Started Mar 26 02:41:08 PM PDT 24
Finished Mar 26 02:41:09 PM PDT 24
Peak memory 205704 kb
Host smart-6ed5894b-bc8d-488e-a557-1e9a9cf5e348
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246471930 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.keymgr_intr_test.2246471930
Directory /workspace/28.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.keymgr_intr_test.717731278
Short name T1028
Test name
Test status
Simulation time 37809896 ps
CPU time 0.71 seconds
Started Mar 26 02:41:12 PM PDT 24
Finished Mar 26 02:41:13 PM PDT 24
Peak memory 205412 kb
Host smart-4238cbbd-5ecd-45ad-a4f1-b7e2769c754d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717731278 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.keymgr_intr_test.717731278
Directory /workspace/29.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_aliasing.4160602686
Short name T994
Test name
Test status
Simulation time 252162252 ps
CPU time 7.26 seconds
Started Mar 26 02:40:48 PM PDT 24
Finished Mar 26 02:40:56 PM PDT 24
Peak memory 205944 kb
Host smart-14ebb4bc-5d4d-4765-8a4a-550707d9ae80
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4160602686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_aliasing.4
160602686
Directory /workspace/3.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_bit_bash.2782304393
Short name T944
Test name
Test status
Simulation time 1185468471 ps
CPU time 6.78 seconds
Started Mar 26 02:40:45 PM PDT 24
Finished Mar 26 02:40:52 PM PDT 24
Peak memory 205780 kb
Host smart-fa6be5df-0978-4303-b136-3f0959363093
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2782304393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_bit_bash.2
782304393
Directory /workspace/3.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_hw_reset.507195607
Short name T938
Test name
Test status
Simulation time 20859492 ps
CPU time 1.22 seconds
Started Mar 26 02:40:33 PM PDT 24
Finished Mar 26 02:40:34 PM PDT 24
Peak memory 205856 kb
Host smart-73357a47-63d6-415f-aec5-e70dbb2f2c8b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=507195607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_hw_reset.507195607
Directory /workspace/3.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_mem_rw_with_rand_reset.1911662226
Short name T939
Test name
Test status
Simulation time 58560939 ps
CPU time 1.79 seconds
Started Mar 26 02:40:45 PM PDT 24
Finished Mar 26 02:40:47 PM PDT 24
Peak memory 214116 kb
Host smart-c5d8d132-4bb0-4156-89f1-ecdcfb60a673
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1911662226 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 3.keymgr_csr_mem_rw_with_rand_reset.1911662226
Directory /workspace/3.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_csr_rw.3470619222
Short name T973
Test name
Test status
Simulation time 66611343 ps
CPU time 1.18 seconds
Started Mar 26 02:40:46 PM PDT 24
Finished Mar 26 02:40:47 PM PDT 24
Peak memory 205788 kb
Host smart-a9930ea6-d269-494f-a171-e5e0d215bf70
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3470619222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_csr_rw.3470619222
Directory /workspace/3.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_intr_test.1219367705
Short name T917
Test name
Test status
Simulation time 22941134 ps
CPU time 0.75 seconds
Started Mar 26 02:40:37 PM PDT 24
Finished Mar 26 02:40:37 PM PDT 24
Peak memory 205480 kb
Host smart-a90b55f4-9aa1-4e53-aced-f59e12c7cbfb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1219367705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_intr_test.1219367705
Directory /workspace/3.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_same_csr_outstanding.1380520449
Short name T962
Test name
Test status
Simulation time 217354192 ps
CPU time 1.5 seconds
Started Mar 26 02:40:47 PM PDT 24
Finished Mar 26 02:40:49 PM PDT 24
Peak memory 205812 kb
Host smart-89d72e1b-8630-4eed-87fb-9163e3a090d4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1380520449 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_sa
me_csr_outstanding.1380520449
Directory /workspace/3.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_shadow_reg_errors_with_csr_rw.3642909286
Short name T177
Test name
Test status
Simulation time 998425334 ps
CPU time 8.76 seconds
Started Mar 26 02:40:35 PM PDT 24
Finished Mar 26 02:40:44 PM PDT 24
Peak memory 214200 kb
Host smart-8499d224-c5cb-41a7-b4d4-d3a62a671ffd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642909286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.
keymgr_shadow_reg_errors_with_csr_rw.3642909286
Directory /workspace/3.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.keymgr_tl_errors.485332468
Short name T1035
Test name
Test status
Simulation time 424465468 ps
CPU time 5.18 seconds
Started Mar 26 02:40:33 PM PDT 24
Finished Mar 26 02:40:38 PM PDT 24
Peak memory 222112 kb
Host smart-9e61fc45-2be0-4179-8acc-42d61fbe88ff
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=485332468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.keymgr_tl_errors.485332468
Directory /workspace/3.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.keymgr_intr_test.13252890
Short name T952
Test name
Test status
Simulation time 43607219 ps
CPU time 0.86 seconds
Started Mar 26 02:41:20 PM PDT 24
Finished Mar 26 02:41:21 PM PDT 24
Peak memory 205588 kb
Host smart-ffee15e3-1ff2-428a-8d91-85c4a7dc00f3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13252890 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.keymgr_intr_test.13252890
Directory /workspace/30.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.keymgr_intr_test.2407860623
Short name T940
Test name
Test status
Simulation time 16160114 ps
CPU time 0.73 seconds
Started Mar 26 02:41:08 PM PDT 24
Finished Mar 26 02:41:09 PM PDT 24
Peak memory 205460 kb
Host smart-db3780fd-eba9-46d1-8c03-0f414317e517
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407860623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.keymgr_intr_test.2407860623
Directory /workspace/31.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.keymgr_intr_test.353664192
Short name T989
Test name
Test status
Simulation time 10194942 ps
CPU time 0.69 seconds
Started Mar 26 02:41:09 PM PDT 24
Finished Mar 26 02:41:10 PM PDT 24
Peak memory 205512 kb
Host smart-389c709d-f162-44d6-b22a-e862f63ad783
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=353664192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.keymgr_intr_test.353664192
Directory /workspace/32.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.keymgr_intr_test.2273498121
Short name T1058
Test name
Test status
Simulation time 50053282 ps
CPU time 0.86 seconds
Started Mar 26 02:41:16 PM PDT 24
Finished Mar 26 02:41:17 PM PDT 24
Peak memory 205512 kb
Host smart-b6d55339-a38a-4623-b58a-97a184369322
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2273498121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.keymgr_intr_test.2273498121
Directory /workspace/33.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.keymgr_intr_test.379517858
Short name T1072
Test name
Test status
Simulation time 24420739 ps
CPU time 0.67 seconds
Started Mar 26 02:41:18 PM PDT 24
Finished Mar 26 02:41:18 PM PDT 24
Peak memory 205460 kb
Host smart-3347e674-ad13-445c-8d17-836618a343d3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=379517858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.keymgr_intr_test.379517858
Directory /workspace/34.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.keymgr_intr_test.3726628493
Short name T1073
Test name
Test status
Simulation time 17214462 ps
CPU time 0.78 seconds
Started Mar 26 02:41:12 PM PDT 24
Finished Mar 26 02:41:13 PM PDT 24
Peak memory 205552 kb
Host smart-cf60cf60-6cb6-47b9-b178-0aac066e13a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3726628493 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.keymgr_intr_test.3726628493
Directory /workspace/35.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.keymgr_intr_test.2596306509
Short name T956
Test name
Test status
Simulation time 22196205 ps
CPU time 0.73 seconds
Started Mar 26 02:41:16 PM PDT 24
Finished Mar 26 02:41:17 PM PDT 24
Peak memory 205740 kb
Host smart-41fb27ec-e5a9-4298-91d9-6ca74bad1546
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2596306509 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.keymgr_intr_test.2596306509
Directory /workspace/36.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.keymgr_intr_test.904038586
Short name T946
Test name
Test status
Simulation time 10873149 ps
CPU time 0.72 seconds
Started Mar 26 02:41:08 PM PDT 24
Finished Mar 26 02:41:10 PM PDT 24
Peak memory 205492 kb
Host smart-c85eede3-9d2e-419e-b158-3896874a1fee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=904038586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.keymgr_intr_test.904038586
Directory /workspace/37.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.keymgr_intr_test.1927457387
Short name T915
Test name
Test status
Simulation time 23047152 ps
CPU time 0.72 seconds
Started Mar 26 02:41:08 PM PDT 24
Finished Mar 26 02:41:10 PM PDT 24
Peak memory 205392 kb
Host smart-c2eb6995-f748-40e7-b7f4-e87dbe9562ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1927457387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.keymgr_intr_test.1927457387
Directory /workspace/38.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.keymgr_intr_test.2963649622
Short name T951
Test name
Test status
Simulation time 14177131 ps
CPU time 0.84 seconds
Started Mar 26 02:41:15 PM PDT 24
Finished Mar 26 02:41:16 PM PDT 24
Peak memory 205480 kb
Host smart-d57d8603-ddb4-4d3e-8553-a2c28fdcbaf7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963649622 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.keymgr_intr_test.2963649622
Directory /workspace/39.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_aliasing.3702391736
Short name T959
Test name
Test status
Simulation time 516493713 ps
CPU time 7.72 seconds
Started Mar 26 02:40:46 PM PDT 24
Finished Mar 26 02:40:54 PM PDT 24
Peak memory 205904 kb
Host smart-2a63fe6c-af6c-4a61-8355-0aa6a72a9876
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3702391736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_aliasing.3
702391736
Directory /workspace/4.keymgr_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_bit_bash.3207910268
Short name T1067
Test name
Test status
Simulation time 995580314 ps
CPU time 15.26 seconds
Started Mar 26 02:40:49 PM PDT 24
Finished Mar 26 02:41:04 PM PDT 24
Peak memory 205772 kb
Host smart-7fb1fc30-fe6e-4047-82d4-bd6130c9442c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3207910268 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_bit_bash.3
207910268
Directory /workspace/4.keymgr_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_hw_reset.433767355
Short name T1033
Test name
Test status
Simulation time 39360306 ps
CPU time 1.03 seconds
Started Mar 26 02:40:48 PM PDT 24
Finished Mar 26 02:40:49 PM PDT 24
Peak memory 205772 kb
Host smart-2b301af6-a5fb-4592-8059-106510a442d4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=433767355 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_hw_reset.433767355
Directory /workspace/4.keymgr_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_mem_rw_with_rand_reset.267996918
Short name T1030
Test name
Test status
Simulation time 458311875 ps
CPU time 1.23 seconds
Started Mar 26 02:40:47 PM PDT 24
Finished Mar 26 02:40:49 PM PDT 24
Peak memory 205876 kb
Host smart-5ed5e7b9-4b82-4394-96b9-e7989cafc48b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=267996918 -assert nopostproc +UVM_TESTNAME=
keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_
log /dev/null -cm_name 4.keymgr_csr_mem_rw_with_rand_reset.267996918
Directory /workspace/4.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_csr_rw.4085404356
Short name T983
Test name
Test status
Simulation time 14277103 ps
CPU time 0.9 seconds
Started Mar 26 02:40:48 PM PDT 24
Finished Mar 26 02:40:49 PM PDT 24
Peak memory 205668 kb
Host smart-a0c76e73-8c96-45cc-9a47-d35b5cdcacca
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4085404356 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_csr_rw.4085404356
Directory /workspace/4.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_intr_test.2111168777
Short name T1011
Test name
Test status
Simulation time 9824209 ps
CPU time 0.75 seconds
Started Mar 26 02:40:48 PM PDT 24
Finished Mar 26 02:40:49 PM PDT 24
Peak memory 205580 kb
Host smart-b1a4eec0-1a5a-4dc6-9a65-d2df1b18e2e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111168777 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_intr_test.2111168777
Directory /workspace/4.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_same_csr_outstanding.3352892648
Short name T1037
Test name
Test status
Simulation time 475882416 ps
CPU time 2.74 seconds
Started Mar 26 02:40:46 PM PDT 24
Finished Mar 26 02:40:48 PM PDT 24
Peak memory 205768 kb
Host smart-a0efff75-1df2-469b-b4ff-bfda42f4a26c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352892648 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_sa
me_csr_outstanding.3352892648
Directory /workspace/4.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors.3688561779
Short name T966
Test name
Test status
Simulation time 119411124 ps
CPU time 3.27 seconds
Started Mar 26 02:40:50 PM PDT 24
Finished Mar 26 02:40:53 PM PDT 24
Peak memory 214368 kb
Host smart-f7ce4b71-dcdd-4b68-a9a8-b955a8d627c6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3688561779 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_shado
w_reg_errors.3688561779
Directory /workspace/4.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_shadow_reg_errors_with_csr_rw.2140871204
Short name T1020
Test name
Test status
Simulation time 1496932585 ps
CPU time 14.47 seconds
Started Mar 26 02:40:47 PM PDT 24
Finished Mar 26 02:41:02 PM PDT 24
Peak memory 214336 kb
Host smart-c544adba-eee8-404e-bb94-8e51eb199793
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2140871204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.
keymgr_shadow_reg_errors_with_csr_rw.2140871204
Directory /workspace/4.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_errors.4195374684
Short name T1053
Test name
Test status
Simulation time 99087175 ps
CPU time 2.87 seconds
Started Mar 26 02:40:45 PM PDT 24
Finished Mar 26 02:40:48 PM PDT 24
Peak memory 214676 kb
Host smart-5d1f272d-ca67-4acd-9afe-bc475aad4ad9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4195374684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_errors.4195374684
Directory /workspace/4.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.keymgr_tl_intg_err.2726086380
Short name T182
Test name
Test status
Simulation time 227531132 ps
CPU time 3.63 seconds
Started Mar 26 02:40:49 PM PDT 24
Finished Mar 26 02:40:53 PM PDT 24
Peak memory 209356 kb
Host smart-73f00886-c0bf-4f17-91eb-70814fe6f5f1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726086380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_commo
n_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.keymgr_tl_intg_err
.2726086380
Directory /workspace/4.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.keymgr_intr_test.3336150957
Short name T986
Test name
Test status
Simulation time 11508270 ps
CPU time 0.91 seconds
Started Mar 26 02:41:18 PM PDT 24
Finished Mar 26 02:41:19 PM PDT 24
Peak memory 205464 kb
Host smart-4e88551e-ae2c-490d-b6c9-d99645521c32
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3336150957 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.keymgr_intr_test.3336150957
Directory /workspace/40.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.keymgr_intr_test.1576178676
Short name T1019
Test name
Test status
Simulation time 29228214 ps
CPU time 0.79 seconds
Started Mar 26 02:41:12 PM PDT 24
Finished Mar 26 02:41:13 PM PDT 24
Peak memory 205404 kb
Host smart-a4461292-5e8a-4c5f-bb91-0321998f3ee0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1576178676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.keymgr_intr_test.1576178676
Directory /workspace/41.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.keymgr_intr_test.2101638079
Short name T1044
Test name
Test status
Simulation time 73477377 ps
CPU time 0.69 seconds
Started Mar 26 02:41:12 PM PDT 24
Finished Mar 26 02:41:13 PM PDT 24
Peak memory 205488 kb
Host smart-7ff88a77-6066-4d43-a494-a9ecde4d37ba
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2101638079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.keymgr_intr_test.2101638079
Directory /workspace/42.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.keymgr_intr_test.208391815
Short name T1018
Test name
Test status
Simulation time 98320703 ps
CPU time 0.71 seconds
Started Mar 26 02:41:12 PM PDT 24
Finished Mar 26 02:41:13 PM PDT 24
Peak memory 205504 kb
Host smart-a4bc669a-1336-4b2c-9a71-8803364e91b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208391815 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.keymgr_intr_test.208391815
Directory /workspace/43.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.keymgr_intr_test.586916436
Short name T1010
Test name
Test status
Simulation time 32148862 ps
CPU time 0.72 seconds
Started Mar 26 02:41:10 PM PDT 24
Finished Mar 26 02:41:12 PM PDT 24
Peak memory 205480 kb
Host smart-83d2294e-9af1-49f7-a67f-be2f2a2bcabb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=586916436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.keymgr_intr_test.586916436
Directory /workspace/44.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.keymgr_intr_test.1832182455
Short name T914
Test name
Test status
Simulation time 12339355 ps
CPU time 0.83 seconds
Started Mar 26 02:41:10 PM PDT 24
Finished Mar 26 02:41:11 PM PDT 24
Peak memory 205524 kb
Host smart-df64576d-02bd-4907-a7c6-4928f6f203ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1832182455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.keymgr_intr_test.1832182455
Directory /workspace/45.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.keymgr_intr_test.3861796258
Short name T1060
Test name
Test status
Simulation time 18396667 ps
CPU time 0.81 seconds
Started Mar 26 02:41:14 PM PDT 24
Finished Mar 26 02:41:14 PM PDT 24
Peak memory 205488 kb
Host smart-a47526b3-5893-45f6-b9d9-3ac90282c69b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3861796258 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.keymgr_intr_test.3861796258
Directory /workspace/46.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.keymgr_intr_test.3537547020
Short name T978
Test name
Test status
Simulation time 40207451 ps
CPU time 0.77 seconds
Started Mar 26 02:41:17 PM PDT 24
Finished Mar 26 02:41:18 PM PDT 24
Peak memory 205516 kb
Host smart-e342dd8c-da73-4bed-b6a3-9b5f3b135a3a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3537547020 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.keymgr_intr_test.3537547020
Directory /workspace/47.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.keymgr_intr_test.2163363859
Short name T1015
Test name
Test status
Simulation time 46221145 ps
CPU time 0.84 seconds
Started Mar 26 02:41:12 PM PDT 24
Finished Mar 26 02:41:13 PM PDT 24
Peak memory 205536 kb
Host smart-5ab3b8a4-3e34-4200-8fcf-63662f749346
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2163363859 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.keymgr_intr_test.2163363859
Directory /workspace/48.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.keymgr_intr_test.1023530311
Short name T936
Test name
Test status
Simulation time 12526686 ps
CPU time 0.86 seconds
Started Mar 26 02:41:06 PM PDT 24
Finished Mar 26 02:41:07 PM PDT 24
Peak memory 205488 kb
Host smart-a57414b9-3916-4d72-a63c-1766d9866afc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1023530311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.keymgr_intr_test.1023530311
Directory /workspace/49.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_mem_rw_with_rand_reset.1255273335
Short name T1022
Test name
Test status
Simulation time 172617943 ps
CPU time 1.29 seconds
Started Mar 26 02:40:45 PM PDT 24
Finished Mar 26 02:40:47 PM PDT 24
Peak memory 214036 kb
Host smart-2a4ea80f-c866-41a4-8473-5d392eb88c7c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255273335 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 5.keymgr_csr_mem_rw_with_rand_reset.1255273335
Directory /workspace/5.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_csr_rw.1876029862
Short name T169
Test name
Test status
Simulation time 99815732 ps
CPU time 1.2 seconds
Started Mar 26 02:40:48 PM PDT 24
Finished Mar 26 02:40:49 PM PDT 24
Peak memory 205812 kb
Host smart-7f7f3e04-a8cd-45c3-8b7b-07ba6b10e535
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1876029862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_csr_rw.1876029862
Directory /workspace/5.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_intr_test.1500319048
Short name T999
Test name
Test status
Simulation time 16896435 ps
CPU time 0.76 seconds
Started Mar 26 02:40:47 PM PDT 24
Finished Mar 26 02:40:48 PM PDT 24
Peak memory 205580 kb
Host smart-dad5c182-46f2-4039-904e-fc03919b6fa1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1500319048 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_intr_test.1500319048
Directory /workspace/5.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_same_csr_outstanding.1550827311
Short name T1069
Test name
Test status
Simulation time 137643011 ps
CPU time 2.17 seconds
Started Mar 26 02:40:48 PM PDT 24
Finished Mar 26 02:40:51 PM PDT 24
Peak memory 205868 kb
Host smart-227ef751-f435-4ef7-9837-029ef18a9b48
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1550827311 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_sa
me_csr_outstanding.1550827311
Directory /workspace/5.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors.1025572694
Short name T118
Test name
Test status
Simulation time 831746723 ps
CPU time 5.08 seconds
Started Mar 26 02:40:50 PM PDT 24
Finished Mar 26 02:40:55 PM PDT 24
Peak memory 214364 kb
Host smart-683b6b44-604c-4e6c-8c24-aaf6449eed42
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1025572694 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_shado
w_reg_errors.1025572694
Directory /workspace/5.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_shadow_reg_errors_with_csr_rw.2109817956
Short name T1036
Test name
Test status
Simulation time 1957863179 ps
CPU time 9.02 seconds
Started Mar 26 02:40:48 PM PDT 24
Finished Mar 26 02:40:57 PM PDT 24
Peak memory 214372 kb
Host smart-220bd095-98cd-4181-b36e-09e8b3a50c83
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2109817956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
keymgr_shadow_reg_errors_with_csr_rw.2109817956
Directory /workspace/5.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_errors.3358533639
Short name T1016
Test name
Test status
Simulation time 34907298 ps
CPU time 2.31 seconds
Started Mar 26 02:40:46 PM PDT 24
Finished Mar 26 02:40:48 PM PDT 24
Peak memory 214120 kb
Host smart-0851f732-b970-4a4d-b1c7-af95d18b0fea
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3358533639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_errors.3358533639
Directory /workspace/5.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.keymgr_tl_intg_err.789170003
Short name T193
Test name
Test status
Simulation time 64789853 ps
CPU time 3.42 seconds
Started Mar 26 02:40:46 PM PDT 24
Finished Mar 26 02:40:49 PM PDT 24
Peak memory 213976 kb
Host smart-ff1d3317-ca33-4fd6-9756-828d25c51e83
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /w
orkspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789170003 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.keymgr_tl_intg_err.
789170003
Directory /workspace/5.keymgr_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_mem_rw_with_rand_reset.4266719616
Short name T384
Test name
Test status
Simulation time 17395530 ps
CPU time 1.3 seconds
Started Mar 26 02:40:47 PM PDT 24
Finished Mar 26 02:40:48 PM PDT 24
Peak memory 205904 kb
Host smart-cddbe99f-5738-4052-9cef-b17c260f844d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4266719616 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 6.keymgr_csr_mem_rw_with_rand_reset.4266719616
Directory /workspace/6.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_csr_rw.1607483990
Short name T1013
Test name
Test status
Simulation time 20053039 ps
CPU time 0.98 seconds
Started Mar 26 02:40:48 PM PDT 24
Finished Mar 26 02:40:49 PM PDT 24
Peak memory 205668 kb
Host smart-f86e4064-c187-4400-8666-1d2c731344e8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607483990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_csr_rw.1607483990
Directory /workspace/6.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_intr_test.1402431523
Short name T996
Test name
Test status
Simulation time 20854812 ps
CPU time 0.75 seconds
Started Mar 26 02:40:52 PM PDT 24
Finished Mar 26 02:40:53 PM PDT 24
Peak memory 205512 kb
Host smart-c546604c-7b39-4772-9636-055ea04fd09a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1402431523 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_intr_test.1402431523
Directory /workspace/6.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_same_csr_outstanding.2593624029
Short name T1047
Test name
Test status
Simulation time 320201868 ps
CPU time 1.68 seconds
Started Mar 26 02:40:46 PM PDT 24
Finished Mar 26 02:40:47 PM PDT 24
Peak memory 206064 kb
Host smart-7e0a6a13-27d7-4838-8833-e085ce81a615
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2593624029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_sa
me_csr_outstanding.2593624029
Directory /workspace/6.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors.3478811474
Short name T926
Test name
Test status
Simulation time 139263932 ps
CPU time 1.78 seconds
Started Mar 26 02:40:45 PM PDT 24
Finished Mar 26 02:40:47 PM PDT 24
Peak memory 214284 kb
Host smart-2f83a47b-a7f7-4c45-9853-9c861ea3eb42
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3478811474 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_shado
w_reg_errors.3478811474
Directory /workspace/6.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_shadow_reg_errors_with_csr_rw.2111935418
Short name T984
Test name
Test status
Simulation time 340732853 ps
CPU time 4.54 seconds
Started Mar 26 02:40:48 PM PDT 24
Finished Mar 26 02:40:53 PM PDT 24
Peak memory 220456 kb
Host smart-912cec3b-e4b5-4e6c-b511-e09499afebea
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2111935418 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
keymgr_shadow_reg_errors_with_csr_rw.2111935418
Directory /workspace/6.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.keymgr_tl_errors.2218518607
Short name T1002
Test name
Test status
Simulation time 147030373 ps
CPU time 1.39 seconds
Started Mar 26 02:40:49 PM PDT 24
Finished Mar 26 02:40:51 PM PDT 24
Peak memory 214252 kb
Host smart-4771d364-fff1-4da4-a83e-4fb296c459f2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2218518607 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.keymgr_tl_errors.2218518607
Directory /workspace/6.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_mem_rw_with_rand_reset.3235208878
Short name T164
Test name
Test status
Simulation time 25052243 ps
CPU time 1.44 seconds
Started Mar 26 02:40:49 PM PDT 24
Finished Mar 26 02:40:51 PM PDT 24
Peak memory 205996 kb
Host smart-b7efda66-7850-456f-b41a-108e95695eaf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3235208878 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 7.keymgr_csr_mem_rw_with_rand_reset.3235208878
Directory /workspace/7.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_csr_rw.926188768
Short name T1009
Test name
Test status
Simulation time 26793131 ps
CPU time 1.14 seconds
Started Mar 26 02:40:50 PM PDT 24
Finished Mar 26 02:40:51 PM PDT 24
Peak memory 205900 kb
Host smart-0f70490d-3819-45d6-8f8f-eb6eadfcc317
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=926188768 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_csr_rw.926188768
Directory /workspace/7.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_intr_test.4153853577
Short name T948
Test name
Test status
Simulation time 16924109 ps
CPU time 0.69 seconds
Started Mar 26 02:40:51 PM PDT 24
Finished Mar 26 02:40:52 PM PDT 24
Peak memory 205428 kb
Host smart-24bf457e-653a-46d7-a794-6c2c53e5fd86
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4153853577 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_intr_test.4153853577
Directory /workspace/7.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_same_csr_outstanding.2536382640
Short name T937
Test name
Test status
Simulation time 188553567 ps
CPU time 4.14 seconds
Started Mar 26 02:40:49 PM PDT 24
Finished Mar 26 02:40:53 PM PDT 24
Peak memory 205868 kb
Host smart-de252f77-d17d-48f4-82cc-e0c1a12194df
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2536382640 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_sa
me_csr_outstanding.2536382640
Directory /workspace/7.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors.2219910279
Short name T995
Test name
Test status
Simulation time 1960151009 ps
CPU time 6.16 seconds
Started Mar 26 02:40:46 PM PDT 24
Finished Mar 26 02:40:52 PM PDT 24
Peak memory 214296 kb
Host smart-52562e10-879d-435e-9334-4b4f189626e6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2219910279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_shado
w_reg_errors.2219910279
Directory /workspace/7.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_shadow_reg_errors_with_csr_rw.2818090840
Short name T1062
Test name
Test status
Simulation time 2622214564 ps
CPU time 6.55 seconds
Started Mar 26 02:40:48 PM PDT 24
Finished Mar 26 02:40:55 PM PDT 24
Peak memory 214412 kb
Host smart-d5f04742-9fc2-4305-9bba-fc0b22c02d58
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2818090840 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.
keymgr_shadow_reg_errors_with_csr_rw.2818090840
Directory /workspace/7.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.keymgr_tl_errors.665243398
Short name T992
Test name
Test status
Simulation time 121885679 ps
CPU time 2.02 seconds
Started Mar 26 02:40:53 PM PDT 24
Finished Mar 26 02:40:55 PM PDT 24
Peak memory 214104 kb
Host smart-043f0e2a-be4f-47ef-abc0-590147d51c82
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=665243398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.keymgr_tl_errors.665243398
Directory /workspace/7.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_mem_rw_with_rand_reset.1744559589
Short name T949
Test name
Test status
Simulation time 55630622 ps
CPU time 1.12 seconds
Started Mar 26 02:40:50 PM PDT 24
Finished Mar 26 02:40:51 PM PDT 24
Peak memory 205912 kb
Host smart-e3829b4f-1cdf-4af2-9428-93141505020e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1744559589 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 8.keymgr_csr_mem_rw_with_rand_reset.1744559589
Directory /workspace/8.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_csr_rw.705403010
Short name T1021
Test name
Test status
Simulation time 89643208 ps
CPU time 1.17 seconds
Started Mar 26 02:40:48 PM PDT 24
Finished Mar 26 02:40:49 PM PDT 24
Peak memory 205868 kb
Host smart-ec932d79-a164-410f-9892-31a65f2e3cab
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=705403010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_csr_rw.705403010
Directory /workspace/8.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_intr_test.4140481259
Short name T958
Test name
Test status
Simulation time 19002288 ps
CPU time 0.7 seconds
Started Mar 26 02:40:51 PM PDT 24
Finished Mar 26 02:40:52 PM PDT 24
Peak memory 205436 kb
Host smart-9537cad0-e341-4101-89af-745b4aad7fbf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4140481259 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_intr_test.4140481259
Directory /workspace/8.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_same_csr_outstanding.425272452
Short name T153
Test name
Test status
Simulation time 127718297 ps
CPU time 2.66 seconds
Started Mar 26 02:40:53 PM PDT 24
Finished Mar 26 02:40:56 PM PDT 24
Peak memory 214048 kb
Host smart-99501424-6854-4d38-9fa4-342205a0aa67
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=425272452 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keym
gr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_sam
e_csr_outstanding.425272452
Directory /workspace/8.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors.946563896
Short name T1025
Test name
Test status
Simulation time 1635355429 ps
CPU time 7.34 seconds
Started Mar 26 02:40:52 PM PDT 24
Finished Mar 26 02:41:00 PM PDT 24
Peak memory 214252 kb
Host smart-d1850819-78ed-4982-b7d4-294a1f6ce51e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=946563896 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_
common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_shadow
_reg_errors.946563896
Directory /workspace/8.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_shadow_reg_errors_with_csr_rw.1092659348
Short name T998
Test name
Test status
Simulation time 746604560 ps
CPU time 5.47 seconds
Started Mar 26 02:40:50 PM PDT 24
Finished Mar 26 02:40:56 PM PDT 24
Peak memory 214376 kb
Host smart-b962e48b-24bd-4bf5-a00c-1e8e60da9ebc
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1092659348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TES
T_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.
keymgr_shadow_reg_errors_with_csr_rw.1092659348
Directory /workspace/8.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.keymgr_tl_errors.2475155704
Short name T916
Test name
Test status
Simulation time 543171735 ps
CPU time 2.88 seconds
Started Mar 26 02:40:48 PM PDT 24
Finished Mar 26 02:40:51 PM PDT 24
Peak memory 216332 kb
Host smart-35764ef2-7db0-46af-8af9-6277e72ba563
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2475155704 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.keymgr_tl_errors.2475155704
Directory /workspace/8.keymgr_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_mem_rw_with_rand_reset.4183358868
Short name T969
Test name
Test status
Simulation time 104997296 ps
CPU time 2.33 seconds
Started Mar 26 02:40:51 PM PDT 24
Finished Mar 26 02:40:54 PM PDT 24
Peak memory 214016 kb
Host smart-905565cd-b001-4ac1-a2dc-1e599d548ff5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +
UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4183358868 -assert nopostproc +UVM_TESTNAME
=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm
_log /dev/null -cm_name 9.keymgr_csr_mem_rw_with_rand_reset.4183358868
Directory /workspace/9.keymgr_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_csr_rw.3231450548
Short name T152
Test name
Test status
Simulation time 45264772 ps
CPU time 1.16 seconds
Started Mar 26 02:40:54 PM PDT 24
Finished Mar 26 02:40:56 PM PDT 24
Peak memory 205780 kb
Host smart-aa970021-387c-4ecf-80cc-a14f8f31d552
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/
mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3231450548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_csr_rw.3231450548
Directory /workspace/9.keymgr_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_intr_test.14034488
Short name T933
Test name
Test status
Simulation time 12850196 ps
CPU time 0.71 seconds
Started Mar 26 02:40:54 PM PDT 24
Finished Mar 26 02:40:55 PM PDT 24
Peak memory 205392 kb
Host smart-506307cb-faf7-4296-bad0-d96e2995b066
User root
Command /workspace/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14034488 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_intr_test.14034488
Directory /workspace/9.keymgr_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_same_csr_outstanding.3411941231
Short name T1041
Test name
Test status
Simulation time 86841353 ps
CPU time 1.74 seconds
Started Mar 26 02:40:51 PM PDT 24
Finished Mar 26 02:40:53 PM PDT 24
Peak memory 205768 kb
Host smart-e5d88038-4ce7-4133-9f25-5952c528315e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -uc
li -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3411941231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=key
mgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_sa
me_csr_outstanding.3411941231
Directory /workspace/9.keymgr_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors.2660347579
Short name T979
Test name
Test status
Simulation time 316973611 ps
CPU time 2.74 seconds
Started Mar 26 02:40:54 PM PDT 24
Finished Mar 26 02:40:57 PM PDT 24
Peak memory 214204 kb
Host smart-c97b5c7e-37d6-4889-bf85-b5e321f88389
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli
-do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2660347579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr
_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_shado
w_reg_errors.2660347579
Directory /workspace/9.keymgr_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_shadow_reg_errors_with_csr_rw.833007776
Short name T1071
Test name
Test status
Simulation time 1123817911 ps
CPU time 7.43 seconds
Started Mar 26 02:40:47 PM PDT 24
Finished Mar 26 02:40:55 PM PDT 24
Peak memory 214368 kb
Host smart-a08e81c2-0cff-4b59-87bd-04f7fedd8a74
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -lic
queue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=833007776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST
_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.k
eymgr_shadow_reg_errors_with_csr_rw.833007776
Directory /workspace/9.keymgr_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.keymgr_tl_errors.1109495895
Short name T166
Test name
Test status
Simulation time 88987583 ps
CPU time 3.1 seconds
Started Mar 26 02:40:53 PM PDT 24
Finished Mar 26 02:40:56 PM PDT 24
Peak memory 214000 kb
Host smart-d12d1598-4c76-4936-808a-89b3f35b251a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt
/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1109495895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.keymgr_tl_errors.1109495895
Directory /workspace/9.keymgr_tl_errors/latest

Test location /workspace/coverage/default/0.keymgr_alert_test.404376352
Short name T595
Test name
Test status
Simulation time 57347407 ps
CPU time 0.84 seconds
Started Mar 26 03:28:20 PM PDT 24
Finished Mar 26 03:28:22 PM PDT 24
Peak memory 206304 kb
Host smart-9141921a-1637-4d8c-845a-da878229c027
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=404376352 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_alert_test.404376352
Directory /workspace/0.keymgr_alert_test/latest

Test location /workspace/coverage/default/0.keymgr_custom_cm.1794625086
Short name T659
Test name
Test status
Simulation time 364067899 ps
CPU time 2.14 seconds
Started Mar 26 03:28:11 PM PDT 24
Finished Mar 26 03:28:14 PM PDT 24
Peak memory 208752 kb
Host smart-085125e3-5ed2-4e67-a880-bc5f79a3779a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1794625086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_custom_cm.1794625086
Directory /workspace/0.keymgr_custom_cm/latest

Test location /workspace/coverage/default/0.keymgr_direct_to_disabled.1911849109
Short name T722
Test name
Test status
Simulation time 106115830 ps
CPU time 2.34 seconds
Started Mar 26 03:28:09 PM PDT 24
Finished Mar 26 03:28:12 PM PDT 24
Peak memory 208020 kb
Host smart-472f8fe9-8c15-4346-8788-562d71389b12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1911849109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_direct_to_disabled.1911849109
Directory /workspace/0.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/0.keymgr_kmac_rsp_err.1759088660
Short name T707
Test name
Test status
Simulation time 2178107566 ps
CPU time 32.05 seconds
Started Mar 26 03:28:10 PM PDT 24
Finished Mar 26 03:28:42 PM PDT 24
Peak memory 231060 kb
Host smart-9ce9ef63-dbc1-4a2a-b669-47c644c50bb7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1759088660 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_kmac_rsp_err.1759088660
Directory /workspace/0.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/0.keymgr_lc_disable.2894675652
Short name T54
Test name
Test status
Simulation time 133724672 ps
CPU time 3.4 seconds
Started Mar 26 03:28:08 PM PDT 24
Finished Mar 26 03:28:11 PM PDT 24
Peak memory 220492 kb
Host smart-879f318c-3e70-4ce8-9582-f2d914242000
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2894675652 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_lc_disable.2894675652
Directory /workspace/0.keymgr_lc_disable/latest

Test location /workspace/coverage/default/0.keymgr_random.566970908
Short name T617
Test name
Test status
Simulation time 37544559 ps
CPU time 2.78 seconds
Started Mar 26 03:28:08 PM PDT 24
Finished Mar 26 03:28:11 PM PDT 24
Peak memory 207640 kb
Host smart-9e7a326b-128c-421d-afcc-040217ca3e5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=566970908 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_random.566970908
Directory /workspace/0.keymgr_random/latest

Test location /workspace/coverage/default/0.keymgr_sec_cm.73139098
Short name T11
Test name
Test status
Simulation time 10695310970 ps
CPU time 56.54 seconds
Started Mar 26 03:28:08 PM PDT 24
Finished Mar 26 03:29:04 PM PDT 24
Peak memory 236676 kb
Host smart-a0bf4acd-0a41-4999-9001-fdae31b1b4e2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73139098 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sec_cm.73139098
Directory /workspace/0.keymgr_sec_cm/latest

Test location /workspace/coverage/default/0.keymgr_sideload.3655477527
Short name T780
Test name
Test status
Simulation time 216243111 ps
CPU time 5.86 seconds
Started Mar 26 03:28:09 PM PDT 24
Finished Mar 26 03:28:15 PM PDT 24
Peak memory 208224 kb
Host smart-aaada978-954f-4d79-b4de-49e0ec0afb94
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3655477527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload.3655477527
Directory /workspace/0.keymgr_sideload/latest

Test location /workspace/coverage/default/0.keymgr_sideload_kmac.2305234572
Short name T745
Test name
Test status
Simulation time 39020028 ps
CPU time 2.38 seconds
Started Mar 26 03:28:10 PM PDT 24
Finished Mar 26 03:28:12 PM PDT 24
Peak memory 207148 kb
Host smart-b455ab5e-4387-4d8b-984b-9a520ec68ffe
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2305234572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_kmac.2305234572
Directory /workspace/0.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/0.keymgr_sideload_otbn.592656798
Short name T513
Test name
Test status
Simulation time 327702376 ps
CPU time 3.02 seconds
Started Mar 26 03:28:13 PM PDT 24
Finished Mar 26 03:28:16 PM PDT 24
Peak memory 207164 kb
Host smart-ad246418-19b7-4454-b089-e73b4808b684
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=592656798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_otbn.592656798
Directory /workspace/0.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/0.keymgr_sideload_protect.1485066732
Short name T783
Test name
Test status
Simulation time 1358419478 ps
CPU time 8.54 seconds
Started Mar 26 03:28:16 PM PDT 24
Finished Mar 26 03:28:25 PM PDT 24
Peak memory 209008 kb
Host smart-7506822c-89c3-4233-bc1d-90247487e40a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1485066732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sideload_protect.1485066732
Directory /workspace/0.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/0.keymgr_smoke.3937043208
Short name T787
Test name
Test status
Simulation time 194123090 ps
CPU time 4.67 seconds
Started Mar 26 03:28:09 PM PDT 24
Finished Mar 26 03:28:14 PM PDT 24
Peak memory 208620 kb
Host smart-ac9bf975-5872-4853-97c0-c2589a8e72f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937043208 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_smoke.3937043208
Directory /workspace/0.keymgr_smoke/latest

Test location /workspace/coverage/default/0.keymgr_stress_all.1395186735
Short name T78
Test name
Test status
Simulation time 3861692732 ps
CPU time 93.18 seconds
Started Mar 26 03:28:16 PM PDT 24
Finished Mar 26 03:29:49 PM PDT 24
Peak memory 222920 kb
Host smart-0dd590dc-384c-4289-b76d-1c8213d8bf03
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395186735 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_stress_all.1395186735
Directory /workspace/0.keymgr_stress_all/latest

Test location /workspace/coverage/default/0.keymgr_sw_invalid_input.3372525242
Short name T331
Test name
Test status
Simulation time 69112357 ps
CPU time 3.24 seconds
Started Mar 26 03:28:08 PM PDT 24
Finished Mar 26 03:28:12 PM PDT 24
Peak memory 208948 kb
Host smart-603985f1-6716-429a-96a4-b301f9b840b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3372525242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sw_invalid_input.3372525242
Directory /workspace/0.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/0.keymgr_sync_async_fault_cross.116202528
Short name T40
Test name
Test status
Simulation time 194745720 ps
CPU time 4.15 seconds
Started Mar 26 03:28:07 PM PDT 24
Finished Mar 26 03:28:11 PM PDT 24
Peak memory 210704 kb
Host smart-cf7dda68-5bb3-44a0-9b2b-07a02c63d652
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116202528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.keymgr_sync_async_fault_cross.116202528
Directory /workspace/0.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/1.keymgr_alert_test.1621547797
Short name T906
Test name
Test status
Simulation time 14193668 ps
CPU time 0.98 seconds
Started Mar 26 03:28:30 PM PDT 24
Finished Mar 26 03:28:31 PM PDT 24
Peak memory 206484 kb
Host smart-56fd8b3a-a0fb-42c1-82f4-d6807910cd68
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1621547797 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_alert_test.1621547797
Directory /workspace/1.keymgr_alert_test/latest

Test location /workspace/coverage/default/1.keymgr_direct_to_disabled.1814217870
Short name T633
Test name
Test status
Simulation time 369769343 ps
CPU time 1.99 seconds
Started Mar 26 03:28:16 PM PDT 24
Finished Mar 26 03:28:18 PM PDT 24
Peak memory 209904 kb
Host smart-49487772-c24a-4065-a7b8-69db6562b46e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814217870 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_direct_to_disabled.1814217870
Directory /workspace/1.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/1.keymgr_hwsw_invalid_input.2537600078
Short name T686
Test name
Test status
Simulation time 2820754451 ps
CPU time 30.06 seconds
Started Mar 26 03:28:16 PM PDT 24
Finished Mar 26 03:28:46 PM PDT 24
Peak memory 209984 kb
Host smart-f1a85510-4b59-4e1f-9932-142e40219e12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2537600078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_hwsw_invalid_input.2537600078
Directory /workspace/1.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_lc_disable.3312038285
Short name T365
Test name
Test status
Simulation time 96632233 ps
CPU time 2.87 seconds
Started Mar 26 03:28:14 PM PDT 24
Finished Mar 26 03:28:17 PM PDT 24
Peak memory 220072 kb
Host smart-7417eb7a-b895-4b6e-b4a5-5e3d26c8a162
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3312038285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_lc_disable.3312038285
Directory /workspace/1.keymgr_lc_disable/latest

Test location /workspace/coverage/default/1.keymgr_random.1035046829
Short name T234
Test name
Test status
Simulation time 169322031 ps
CPU time 3.88 seconds
Started Mar 26 03:28:06 PM PDT 24
Finished Mar 26 03:28:11 PM PDT 24
Peak memory 207504 kb
Host smart-ec91fb6e-c5d9-4fab-8f2c-c8d6437069be
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1035046829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_random.1035046829
Directory /workspace/1.keymgr_random/latest

Test location /workspace/coverage/default/1.keymgr_sec_cm.4202162190
Short name T105
Test name
Test status
Simulation time 4050388519 ps
CPU time 10.06 seconds
Started Mar 26 03:28:05 PM PDT 24
Finished Mar 26 03:28:15 PM PDT 24
Peak memory 230172 kb
Host smart-cf0bade4-6bf6-4f71-91b7-ed6195d34919
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202162190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sec_cm.4202162190
Directory /workspace/1.keymgr_sec_cm/latest

Test location /workspace/coverage/default/1.keymgr_sideload.2246589880
Short name T292
Test name
Test status
Simulation time 236493321 ps
CPU time 6.35 seconds
Started Mar 26 03:28:16 PM PDT 24
Finished Mar 26 03:28:23 PM PDT 24
Peak memory 208856 kb
Host smart-dfbf45e8-e86f-498f-97f9-f0a752acd213
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2246589880 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload.2246589880
Directory /workspace/1.keymgr_sideload/latest

Test location /workspace/coverage/default/1.keymgr_sideload_aes.1302894471
Short name T139
Test name
Test status
Simulation time 98935947 ps
CPU time 4.28 seconds
Started Mar 26 03:28:09 PM PDT 24
Finished Mar 26 03:28:13 PM PDT 24
Peak memory 209348 kb
Host smart-2429ae29-66ed-4510-80f0-56599c585cad
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1302894471 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_aes.1302894471
Directory /workspace/1.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/1.keymgr_sideload_kmac.206801677
Short name T590
Test name
Test status
Simulation time 48516957 ps
CPU time 1.89 seconds
Started Mar 26 03:28:05 PM PDT 24
Finished Mar 26 03:28:07 PM PDT 24
Peak memory 207164 kb
Host smart-71f131a7-217b-4d9d-ba52-c141d335dea9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=206801677 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_kmac.206801677
Directory /workspace/1.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/1.keymgr_sideload_otbn.1237124595
Short name T782
Test name
Test status
Simulation time 48423573 ps
CPU time 2.53 seconds
Started Mar 26 03:28:12 PM PDT 24
Finished Mar 26 03:28:14 PM PDT 24
Peak memory 207188 kb
Host smart-a307e8b9-8a85-42c4-afa2-65bec1736aec
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1237124595 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_otbn.1237124595
Directory /workspace/1.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/1.keymgr_sideload_protect.2957320590
Short name T396
Test name
Test status
Simulation time 75161983 ps
CPU time 1.74 seconds
Started Mar 26 03:28:17 PM PDT 24
Finished Mar 26 03:28:19 PM PDT 24
Peak memory 207708 kb
Host smart-8304f0f1-acdc-49a3-afac-c7db9285225a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957320590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sideload_protect.2957320590
Directory /workspace/1.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/1.keymgr_smoke.2373441935
Short name T35
Test name
Test status
Simulation time 317894462 ps
CPU time 5.86 seconds
Started Mar 26 03:28:03 PM PDT 24
Finished Mar 26 03:28:09 PM PDT 24
Peak memory 206872 kb
Host smart-98b5e7c5-7531-45fa-ae96-e24477537d9f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2373441935 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_smoke.2373441935
Directory /workspace/1.keymgr_smoke/latest

Test location /workspace/coverage/default/1.keymgr_sw_invalid_input.2180339402
Short name T622
Test name
Test status
Simulation time 2210365169 ps
CPU time 53.16 seconds
Started Mar 26 03:28:13 PM PDT 24
Finished Mar 26 03:29:07 PM PDT 24
Peak memory 208960 kb
Host smart-7f28aa1e-2b7b-4988-9737-b8b899b5ec32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2180339402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sw_invalid_input.2180339402
Directory /workspace/1.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/1.keymgr_sync_async_fault_cross.3523052461
Short name T382
Test name
Test status
Simulation time 56534095 ps
CPU time 1.69 seconds
Started Mar 26 03:28:15 PM PDT 24
Finished Mar 26 03:28:17 PM PDT 24
Peak memory 210076 kb
Host smart-d2c22e28-a442-435d-94c3-211ec6faa3a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523052461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.keymgr_sync_async_fault_cross.3523052461
Directory /workspace/1.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/10.keymgr_alert_test.1395006051
Short name T568
Test name
Test status
Simulation time 132963246 ps
CPU time 0.89 seconds
Started Mar 26 03:28:34 PM PDT 24
Finished Mar 26 03:28:35 PM PDT 24
Peak memory 206348 kb
Host smart-99b133d9-273a-4ae7-b6b7-3099e7ecd577
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1395006051 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_alert_test.1395006051
Directory /workspace/10.keymgr_alert_test/latest

Test location /workspace/coverage/default/10.keymgr_cfg_regwen.386731712
Short name T411
Test name
Test status
Simulation time 511253783 ps
CPU time 5.06 seconds
Started Mar 26 03:28:37 PM PDT 24
Finished Mar 26 03:28:43 PM PDT 24
Peak memory 215356 kb
Host smart-b7a5ea7d-787c-4317-84ea-dff8a1fb01e7
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=386731712 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_cfg_regwen.386731712
Directory /workspace/10.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/10.keymgr_custom_cm.498453791
Short name T507
Test name
Test status
Simulation time 165176113 ps
CPU time 3.6 seconds
Started Mar 26 03:28:39 PM PDT 24
Finished Mar 26 03:28:43 PM PDT 24
Peak memory 210004 kb
Host smart-5a327bcf-9c8a-4846-bca5-d8a0cf9c4768
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498453791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_custom_cm.498453791
Directory /workspace/10.keymgr_custom_cm/latest

Test location /workspace/coverage/default/10.keymgr_direct_to_disabled.3859683052
Short name T771
Test name
Test status
Simulation time 707052547 ps
CPU time 18.11 seconds
Started Mar 26 03:28:46 PM PDT 24
Finished Mar 26 03:29:04 PM PDT 24
Peak memory 209644 kb
Host smart-51a42f64-4f77-4863-89f0-b85499377b1e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859683052 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_direct_to_disabled.3859683052
Directory /workspace/10.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/10.keymgr_hwsw_invalid_input.2202515696
Short name T654
Test name
Test status
Simulation time 2941932715 ps
CPU time 26.1 seconds
Started Mar 26 03:28:18 PM PDT 24
Finished Mar 26 03:28:44 PM PDT 24
Peak memory 214760 kb
Host smart-a8e8cd15-3cf7-4a48-bf76-b29b26f1b1ad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2202515696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_hwsw_invalid_input.2202515696
Directory /workspace/10.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/10.keymgr_random.3056275382
Short name T793
Test name
Test status
Simulation time 46124964 ps
CPU time 2.81 seconds
Started Mar 26 03:28:38 PM PDT 24
Finished Mar 26 03:28:41 PM PDT 24
Peak memory 208000 kb
Host smart-1e8bc713-44c5-48b1-ab4b-8e7dfc6a1539
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3056275382 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_random.3056275382
Directory /workspace/10.keymgr_random/latest

Test location /workspace/coverage/default/10.keymgr_sideload.1745022685
Short name T517
Test name
Test status
Simulation time 59838345 ps
CPU time 2.66 seconds
Started Mar 26 03:28:39 PM PDT 24
Finished Mar 26 03:28:42 PM PDT 24
Peak memory 207088 kb
Host smart-118343fa-6cc3-4aee-a561-cb119b8277e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1745022685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload.1745022685
Directory /workspace/10.keymgr_sideload/latest

Test location /workspace/coverage/default/10.keymgr_sideload_aes.3276666905
Short name T107
Test name
Test status
Simulation time 377994464 ps
CPU time 8.17 seconds
Started Mar 26 03:28:21 PM PDT 24
Finished Mar 26 03:28:29 PM PDT 24
Peak memory 208756 kb
Host smart-26f5d0ef-b8b1-4616-849c-13c0a07d8116
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276666905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_aes.3276666905
Directory /workspace/10.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/10.keymgr_sideload_kmac.1877228696
Short name T657
Test name
Test status
Simulation time 294328140 ps
CPU time 3.47 seconds
Started Mar 26 03:28:45 PM PDT 24
Finished Mar 26 03:28:49 PM PDT 24
Peak memory 209020 kb
Host smart-b87a9004-d5a2-4250-9cef-b5f08e9bebd2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1877228696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_kmac.1877228696
Directory /workspace/10.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/10.keymgr_sideload_otbn.2612884220
Short name T431
Test name
Test status
Simulation time 42420467 ps
CPU time 2.46 seconds
Started Mar 26 03:28:22 PM PDT 24
Finished Mar 26 03:28:25 PM PDT 24
Peak memory 207200 kb
Host smart-152c3404-63bb-44b9-8591-568afb4c5dca
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2612884220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_otbn.2612884220
Directory /workspace/10.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/10.keymgr_sideload_protect.1350050295
Short name T724
Test name
Test status
Simulation time 52078507 ps
CPU time 2.9 seconds
Started Mar 26 03:28:46 PM PDT 24
Finished Mar 26 03:28:49 PM PDT 24
Peak memory 214616 kb
Host smart-3a13e950-fb8d-4ab4-8356-ec65af35c557
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1350050295 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sideload_protect.1350050295
Directory /workspace/10.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/10.keymgr_smoke.3487631228
Short name T479
Test name
Test status
Simulation time 67834522 ps
CPU time 3.11 seconds
Started Mar 26 03:28:21 PM PDT 24
Finished Mar 26 03:28:24 PM PDT 24
Peak memory 208600 kb
Host smart-e0e8e09c-09cf-4f1a-bb8a-99a597c2fdd9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487631228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_smoke.3487631228
Directory /workspace/10.keymgr_smoke/latest

Test location /workspace/coverage/default/10.keymgr_stress_all.3521359237
Short name T226
Test name
Test status
Simulation time 1405431319 ps
CPU time 8.51 seconds
Started Mar 26 03:28:51 PM PDT 24
Finished Mar 26 03:29:00 PM PDT 24
Peak memory 218984 kb
Host smart-957eddd2-44df-4f3b-a723-c7040acb299f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3521359237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all.3521359237
Directory /workspace/10.keymgr_stress_all/latest

Test location /workspace/coverage/default/10.keymgr_stress_all_with_rand_reset.231412021
Short name T134
Test name
Test status
Simulation time 239100924 ps
CPU time 5.29 seconds
Started Mar 26 03:28:37 PM PDT 24
Finished Mar 26 03:28:42 PM PDT 24
Peak memory 223020 kb
Host smart-2b4f09f4-3f0f-41e1-8ffe-fe2af64df901
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=231412021 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 10.keymgr_stress_all_with_rand_reset.231412021
Directory /workspace/10.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.keymgr_sw_invalid_input.55367916
Short name T397
Test name
Test status
Simulation time 1997054785 ps
CPU time 15.66 seconds
Started Mar 26 03:28:18 PM PDT 24
Finished Mar 26 03:28:34 PM PDT 24
Peak memory 210152 kb
Host smart-1877e322-d33e-431c-9a73-2fd23882a4c1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=55367916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.keymgr_sw_invalid_input.55367916
Directory /workspace/10.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_alert_test.1676869900
Short name T828
Test name
Test status
Simulation time 20496364 ps
CPU time 0.97 seconds
Started Mar 26 03:28:46 PM PDT 24
Finished Mar 26 03:28:47 PM PDT 24
Peak memory 206444 kb
Host smart-abe13585-c514-4151-a392-4f870b8f1f8c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1676869900 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_alert_test.1676869900
Directory /workspace/11.keymgr_alert_test/latest

Test location /workspace/coverage/default/11.keymgr_custom_cm.543525754
Short name T897
Test name
Test status
Simulation time 213926919 ps
CPU time 5.23 seconds
Started Mar 26 03:28:49 PM PDT 24
Finished Mar 26 03:28:55 PM PDT 24
Peak memory 223012 kb
Host smart-cdf94ec6-ba6c-4a5e-9cbb-0850aefb0f70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=543525754 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_custom_cm.543525754
Directory /workspace/11.keymgr_custom_cm/latest

Test location /workspace/coverage/default/11.keymgr_direct_to_disabled.3501551711
Short name T358
Test name
Test status
Simulation time 49034309 ps
CPU time 1.76 seconds
Started Mar 26 03:28:46 PM PDT 24
Finished Mar 26 03:28:48 PM PDT 24
Peak memory 218720 kb
Host smart-f4af9e0d-9dd7-4b1c-9523-6d3345a40ab7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3501551711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_direct_to_disabled.3501551711
Directory /workspace/11.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/11.keymgr_hwsw_invalid_input.2124877696
Short name T865
Test name
Test status
Simulation time 100689825 ps
CPU time 3.68 seconds
Started Mar 26 03:28:49 PM PDT 24
Finished Mar 26 03:28:53 PM PDT 24
Peak memory 208984 kb
Host smart-e876d033-ff7e-46d5-aeda-9948bb819ff6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124877696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_hwsw_invalid_input.2124877696
Directory /workspace/11.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_kmac_rsp_err.3893616627
Short name T792
Test name
Test status
Simulation time 1837845726 ps
CPU time 6.01 seconds
Started Mar 26 03:28:43 PM PDT 24
Finished Mar 26 03:28:49 PM PDT 24
Peak memory 222744 kb
Host smart-7686b0ad-743b-4411-b130-6c48e7f8e55c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3893616627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_kmac_rsp_err.3893616627
Directory /workspace/11.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/11.keymgr_lc_disable.2842145314
Short name T600
Test name
Test status
Simulation time 223299649 ps
CPU time 5.17 seconds
Started Mar 26 03:28:55 PM PDT 24
Finished Mar 26 03:29:01 PM PDT 24
Peak memory 218608 kb
Host smart-dd3826ff-2da3-449e-a572-c6bf27bbdcdd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842145314 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_lc_disable.2842145314
Directory /workspace/11.keymgr_lc_disable/latest

Test location /workspace/coverage/default/11.keymgr_random.4289748310
Short name T643
Test name
Test status
Simulation time 246675824 ps
CPU time 5.22 seconds
Started Mar 26 03:28:49 PM PDT 24
Finished Mar 26 03:28:55 PM PDT 24
Peak memory 210052 kb
Host smart-2ad228ac-84c5-4f10-b246-0f61ca99b55a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4289748310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_random.4289748310
Directory /workspace/11.keymgr_random/latest

Test location /workspace/coverage/default/11.keymgr_sideload.2173182482
Short name T329
Test name
Test status
Simulation time 174026534 ps
CPU time 4.99 seconds
Started Mar 26 03:28:29 PM PDT 24
Finished Mar 26 03:28:34 PM PDT 24
Peak memory 208188 kb
Host smart-f1ed32ac-7855-40d6-9704-46bb759c57ac
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2173182482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload.2173182482
Directory /workspace/11.keymgr_sideload/latest

Test location /workspace/coverage/default/11.keymgr_sideload_aes.3471856940
Short name T15
Test name
Test status
Simulation time 104357108 ps
CPU time 2.26 seconds
Started Mar 26 03:28:39 PM PDT 24
Finished Mar 26 03:28:42 PM PDT 24
Peak memory 206956 kb
Host smart-7c81afe6-1253-46f1-ba0a-f0345baf05d7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471856940 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_aes.3471856940
Directory /workspace/11.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/11.keymgr_sideload_kmac.3005609249
Short name T880
Test name
Test status
Simulation time 159538649 ps
CPU time 3.06 seconds
Started Mar 26 03:28:20 PM PDT 24
Finished Mar 26 03:28:28 PM PDT 24
Peak memory 208660 kb
Host smart-048883d6-f815-47ff-8b67-a88cf5f9b317
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005609249 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_kmac.3005609249
Directory /workspace/11.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/11.keymgr_sideload_otbn.3233426854
Short name T661
Test name
Test status
Simulation time 319590978 ps
CPU time 3 seconds
Started Mar 26 03:28:38 PM PDT 24
Finished Mar 26 03:28:41 PM PDT 24
Peak memory 206972 kb
Host smart-ddfdff78-c5f8-4a5d-874a-1e4bf26945d1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3233426854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_otbn.3233426854
Directory /workspace/11.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/11.keymgr_sideload_protect.3456322576
Short name T410
Test name
Test status
Simulation time 456789514 ps
CPU time 5.45 seconds
Started Mar 26 03:28:51 PM PDT 24
Finished Mar 26 03:28:57 PM PDT 24
Peak memory 214952 kb
Host smart-19f9fa96-c9f9-48ca-984f-484b0311ae87
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3456322576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sideload_protect.3456322576
Directory /workspace/11.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/11.keymgr_smoke.1699802496
Short name T594
Test name
Test status
Simulation time 66934819 ps
CPU time 3.11 seconds
Started Mar 26 03:28:20 PM PDT 24
Finished Mar 26 03:28:23 PM PDT 24
Peak memory 208452 kb
Host smart-b7b67646-1319-4141-b786-ee09572a3083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1699802496 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_smoke.1699802496
Directory /workspace/11.keymgr_smoke/latest

Test location /workspace/coverage/default/11.keymgr_stress_all.3778646809
Short name T70
Test name
Test status
Simulation time 4059661465 ps
CPU time 116.41 seconds
Started Mar 26 03:28:28 PM PDT 24
Finished Mar 26 03:30:25 PM PDT 24
Peak memory 223008 kb
Host smart-c7d0475b-9e2b-41d7-bb08-4f14287b5336
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3778646809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all.3778646809
Directory /workspace/11.keymgr_stress_all/latest

Test location /workspace/coverage/default/11.keymgr_stress_all_with_rand_reset.3217979394
Short name T326
Test name
Test status
Simulation time 1054337229 ps
CPU time 13.35 seconds
Started Mar 26 03:28:35 PM PDT 24
Finished Mar 26 03:28:54 PM PDT 24
Peak memory 223024 kb
Host smart-ba84cac3-85c1-42e9-a6ab-cba21d4e8f15
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3217979394 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 11.keymgr_stress_all_with_rand_reset.3217979394
Directory /workspace/11.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.keymgr_sw_invalid_input.3486756260
Short name T249
Test name
Test status
Simulation time 727170038 ps
CPU time 3.48 seconds
Started Mar 26 03:28:40 PM PDT 24
Finished Mar 26 03:28:43 PM PDT 24
Peak memory 214656 kb
Host smart-1e28128d-0cc3-450e-b7ba-60238db5b67d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3486756260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sw_invalid_input.3486756260
Directory /workspace/11.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/11.keymgr_sync_async_fault_cross.1291704485
Short name T381
Test name
Test status
Simulation time 270915935 ps
CPU time 2.32 seconds
Started Mar 26 03:28:46 PM PDT 24
Finished Mar 26 03:28:49 PM PDT 24
Peak memory 210144 kb
Host smart-d61c09ee-fab9-4fd5-91aa-5fd688438a16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1291704485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.keymgr_sync_async_fault_cross.1291704485
Directory /workspace/11.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/12.keymgr_alert_test.185137874
Short name T618
Test name
Test status
Simulation time 28819169 ps
CPU time 0.81 seconds
Started Mar 26 03:28:46 PM PDT 24
Finished Mar 26 03:28:50 PM PDT 24
Peak memory 206360 kb
Host smart-b311f653-3815-480e-9df3-0b59c09e67db
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185137874 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_alert_test.185137874
Directory /workspace/12.keymgr_alert_test/latest

Test location /workspace/coverage/default/12.keymgr_direct_to_disabled.2970793800
Short name T556
Test name
Test status
Simulation time 1867699586 ps
CPU time 11.48 seconds
Started Mar 26 03:29:00 PM PDT 24
Finished Mar 26 03:29:12 PM PDT 24
Peak memory 209492 kb
Host smart-bb9d55d5-dcdf-4a0e-a588-8dff6f5b137f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2970793800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_direct_to_disabled.2970793800
Directory /workspace/12.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/12.keymgr_hwsw_invalid_input.2997070007
Short name T520
Test name
Test status
Simulation time 189187909 ps
CPU time 4.7 seconds
Started Mar 26 03:28:51 PM PDT 24
Finished Mar 26 03:28:56 PM PDT 24
Peak memory 214580 kb
Host smart-32731381-0083-445a-84a6-71b8cd8f50b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2997070007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_hwsw_invalid_input.2997070007
Directory /workspace/12.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/12.keymgr_kmac_rsp_err.2645819776
Short name T359
Test name
Test status
Simulation time 6424791178 ps
CPU time 49.63 seconds
Started Mar 26 03:28:50 PM PDT 24
Finished Mar 26 03:29:40 PM PDT 24
Peak memory 220032 kb
Host smart-0f4a86a9-6a5b-412a-8073-6f95391f0431
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2645819776 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_kmac_rsp_err.2645819776
Directory /workspace/12.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/12.keymgr_lc_disable.770548169
Short name T711
Test name
Test status
Simulation time 464241534 ps
CPU time 12.75 seconds
Started Mar 26 03:28:46 PM PDT 24
Finished Mar 26 03:28:59 PM PDT 24
Peak memory 218596 kb
Host smart-8520eeb2-92f9-4f3d-b589-df5ac063fd16
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=770548169 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_lc_disable.770548169
Directory /workspace/12.keymgr_lc_disable/latest

Test location /workspace/coverage/default/12.keymgr_random.3733936012
Short name T611
Test name
Test status
Simulation time 178912613 ps
CPU time 3.52 seconds
Started Mar 26 03:28:49 PM PDT 24
Finished Mar 26 03:28:53 PM PDT 24
Peak memory 207236 kb
Host smart-61939d16-99e0-4118-91d8-cd199f9a03ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3733936012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_random.3733936012
Directory /workspace/12.keymgr_random/latest

Test location /workspace/coverage/default/12.keymgr_sideload_aes.3886993369
Short name T624
Test name
Test status
Simulation time 123932067 ps
CPU time 3.2 seconds
Started Mar 26 03:28:48 PM PDT 24
Finished Mar 26 03:28:52 PM PDT 24
Peak memory 209344 kb
Host smart-add918db-c781-4498-ba78-64bb3802f870
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3886993369 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_aes.3886993369
Directory /workspace/12.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/12.keymgr_sideload_kmac.2788837220
Short name T508
Test name
Test status
Simulation time 129178603 ps
CPU time 1.81 seconds
Started Mar 26 03:28:47 PM PDT 24
Finished Mar 26 03:28:49 PM PDT 24
Peak memory 207168 kb
Host smart-053ffce3-2a71-4c39-97bd-c0785a2240d2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2788837220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_kmac.2788837220
Directory /workspace/12.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/12.keymgr_sideload_protect.4166845649
Short name T260
Test name
Test status
Simulation time 229588380 ps
CPU time 3.19 seconds
Started Mar 26 03:28:43 PM PDT 24
Finished Mar 26 03:28:46 PM PDT 24
Peak memory 216040 kb
Host smart-f74baf3c-ec50-42a9-b99c-3cb67a4c55e9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4166845649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sideload_protect.4166845649
Directory /workspace/12.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/12.keymgr_smoke.3988032845
Short name T403
Test name
Test status
Simulation time 187370199 ps
CPU time 2.73 seconds
Started Mar 26 03:28:36 PM PDT 24
Finished Mar 26 03:28:39 PM PDT 24
Peak memory 208716 kb
Host smart-64d6a5fd-4607-4aa6-86a4-0e47601a0b99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3988032845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_smoke.3988032845
Directory /workspace/12.keymgr_smoke/latest

Test location /workspace/coverage/default/12.keymgr_sw_invalid_input.163632434
Short name T242
Test name
Test status
Simulation time 271039352 ps
CPU time 9.49 seconds
Started Mar 26 03:28:49 PM PDT 24
Finished Mar 26 03:28:59 PM PDT 24
Peak memory 218384 kb
Host smart-6ad028bf-f3c3-4291-80a1-00bff5a1dae4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=163632434 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.keymgr_sw_invalid_input.163632434
Directory /workspace/12.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_alert_test.2607203705
Short name T488
Test name
Test status
Simulation time 38592027 ps
CPU time 0.7 seconds
Started Mar 26 03:29:00 PM PDT 24
Finished Mar 26 03:29:01 PM PDT 24
Peak memory 206328 kb
Host smart-698e77e4-78c4-487e-b974-e351b6eda4be
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2607203705 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_alert_test.2607203705
Directory /workspace/13.keymgr_alert_test/latest

Test location /workspace/coverage/default/13.keymgr_direct_to_disabled.1580061558
Short name T726
Test name
Test status
Simulation time 103246842 ps
CPU time 4.29 seconds
Started Mar 26 03:28:50 PM PDT 24
Finished Mar 26 03:28:54 PM PDT 24
Peak memory 218696 kb
Host smart-b8def18e-a519-4f3a-a188-289194f03dda
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1580061558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_direct_to_disabled.1580061558
Directory /workspace/13.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/13.keymgr_hwsw_invalid_input.3251741578
Short name T756
Test name
Test status
Simulation time 737942568 ps
CPU time 6.54 seconds
Started Mar 26 03:28:43 PM PDT 24
Finished Mar 26 03:28:49 PM PDT 24
Peak memory 221312 kb
Host smart-77d260f4-4c9e-4eec-87b3-84e254ad8ab4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3251741578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_hwsw_invalid_input.3251741578
Directory /workspace/13.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_lc_disable.1828748109
Short name T252
Test name
Test status
Simulation time 269281794 ps
CPU time 7.99 seconds
Started Mar 26 03:28:38 PM PDT 24
Finished Mar 26 03:28:46 PM PDT 24
Peak memory 218324 kb
Host smart-ce5d85ae-74c0-4004-8a97-a94c6531f635
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1828748109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_lc_disable.1828748109
Directory /workspace/13.keymgr_lc_disable/latest

Test location /workspace/coverage/default/13.keymgr_random.1205020736
Short name T565
Test name
Test status
Simulation time 2629698136 ps
CPU time 10.1 seconds
Started Mar 26 03:28:47 PM PDT 24
Finished Mar 26 03:28:57 PM PDT 24
Peak memory 208908 kb
Host smart-7535e588-de21-4123-95c0-956d4871bc26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1205020736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_random.1205020736
Directory /workspace/13.keymgr_random/latest

Test location /workspace/coverage/default/13.keymgr_sideload.3121503390
Short name T102
Test name
Test status
Simulation time 171343632 ps
CPU time 2.64 seconds
Started Mar 26 03:28:48 PM PDT 24
Finished Mar 26 03:28:51 PM PDT 24
Peak memory 208844 kb
Host smart-21053899-8d64-468d-84ec-d02184cd3b25
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3121503390 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload.3121503390
Directory /workspace/13.keymgr_sideload/latest

Test location /workspace/coverage/default/13.keymgr_sideload_aes.2878724116
Short name T444
Test name
Test status
Simulation time 117516431 ps
CPU time 2.55 seconds
Started Mar 26 03:28:52 PM PDT 24
Finished Mar 26 03:28:55 PM PDT 24
Peak memory 207104 kb
Host smart-363900f2-ba06-423b-b922-1f3107be3bda
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2878724116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_aes.2878724116
Directory /workspace/13.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/13.keymgr_sideload_kmac.3291465458
Short name T480
Test name
Test status
Simulation time 67156438 ps
CPU time 3.29 seconds
Started Mar 26 03:28:41 PM PDT 24
Finished Mar 26 03:28:45 PM PDT 24
Peak memory 209092 kb
Host smart-2ba79184-0c04-4057-8412-88223520c628
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3291465458 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_kmac.3291465458
Directory /workspace/13.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/13.keymgr_sideload_otbn.3624630998
Short name T692
Test name
Test status
Simulation time 53824860 ps
CPU time 2.97 seconds
Started Mar 26 03:28:40 PM PDT 24
Finished Mar 26 03:28:44 PM PDT 24
Peak memory 208984 kb
Host smart-35122811-ba13-4bbd-9d3e-2de36180b09a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3624630998 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_otbn.3624630998
Directory /workspace/13.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/13.keymgr_sideload_protect.907876656
Short name T681
Test name
Test status
Simulation time 58213885 ps
CPU time 2.07 seconds
Started Mar 26 03:29:00 PM PDT 24
Finished Mar 26 03:29:03 PM PDT 24
Peak memory 208560 kb
Host smart-90ba1f5d-57d6-42f7-8bb4-a3cfaeeef5e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=907876656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sideload_protect.907876656
Directory /workspace/13.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/13.keymgr_smoke.466007073
Short name T689
Test name
Test status
Simulation time 49369586 ps
CPU time 2.03 seconds
Started Mar 26 03:28:54 PM PDT 24
Finished Mar 26 03:28:57 PM PDT 24
Peak memory 208756 kb
Host smart-7d4c74c6-c6e3-4080-aeca-483cef8fdbbf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466007073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_smoke.466007073
Directory /workspace/13.keymgr_smoke/latest

Test location /workspace/coverage/default/13.keymgr_sw_invalid_input.402733682
Short name T254
Test name
Test status
Simulation time 214868433 ps
CPU time 3.73 seconds
Started Mar 26 03:28:36 PM PDT 24
Finished Mar 26 03:28:40 PM PDT 24
Peak memory 209972 kb
Host smart-95d37b8d-660a-4b40-891d-ba6c3f730fe5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=402733682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sw_invalid_input.402733682
Directory /workspace/13.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/13.keymgr_sync_async_fault_cross.1511046521
Short name T135
Test name
Test status
Simulation time 114510999 ps
CPU time 3.9 seconds
Started Mar 26 03:28:58 PM PDT 24
Finished Mar 26 03:29:02 PM PDT 24
Peak memory 210840 kb
Host smart-3494e999-67f6-442f-a521-45af27e53321
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1511046521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.keymgr_sync_async_fault_cross.1511046521
Directory /workspace/13.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/14.keymgr_alert_test.2999752715
Short name T720
Test name
Test status
Simulation time 45894914 ps
CPU time 0.76 seconds
Started Mar 26 03:28:54 PM PDT 24
Finished Mar 26 03:28:56 PM PDT 24
Peak memory 206284 kb
Host smart-39cf933b-9a58-4ca3-884e-8843d9682f2b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2999752715 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_alert_test.2999752715
Directory /workspace/14.keymgr_alert_test/latest

Test location /workspace/coverage/default/14.keymgr_cfg_regwen.3639841831
Short name T387
Test name
Test status
Simulation time 43175308 ps
CPU time 3.36 seconds
Started Mar 26 03:28:51 PM PDT 24
Finished Mar 26 03:28:55 PM PDT 24
Peak memory 222932 kb
Host smart-583db899-86a8-4ff7-9d64-bea314680f4d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3639841831 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_cfg_regwen.3639841831
Directory /workspace/14.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/14.keymgr_custom_cm.2651061954
Short name T721
Test name
Test status
Simulation time 393688466 ps
CPU time 4.96 seconds
Started Mar 26 03:29:10 PM PDT 24
Finished Mar 26 03:29:16 PM PDT 24
Peak memory 221960 kb
Host smart-2716bfdd-5076-4829-a1d5-07b15d618005
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651061954 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_custom_cm.2651061954
Directory /workspace/14.keymgr_custom_cm/latest

Test location /workspace/coverage/default/14.keymgr_direct_to_disabled.1251132745
Short name T521
Test name
Test status
Simulation time 129491297 ps
CPU time 3.81 seconds
Started Mar 26 03:28:52 PM PDT 24
Finished Mar 26 03:28:57 PM PDT 24
Peak memory 209092 kb
Host smart-a02a0892-26df-4e0d-81ea-7071aaece30b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251132745 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_direct_to_disabled.1251132745
Directory /workspace/14.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/14.keymgr_hwsw_invalid_input.816399628
Short name T390
Test name
Test status
Simulation time 55923558 ps
CPU time 2.83 seconds
Started Mar 26 03:28:56 PM PDT 24
Finished Mar 26 03:28:59 PM PDT 24
Peak memory 208916 kb
Host smart-a873008e-2b4f-4841-a2a4-b11de7d7d9f9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816399628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_hwsw_invalid_input.816399628
Directory /workspace/14.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_lc_disable.2204747339
Short name T61
Test name
Test status
Simulation time 113499005 ps
CPU time 4.97 seconds
Started Mar 26 03:28:53 PM PDT 24
Finished Mar 26 03:28:59 PM PDT 24
Peak memory 210140 kb
Host smart-bd0e1379-673c-4ab2-8e8c-08c1ce34ace4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204747339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_lc_disable.2204747339
Directory /workspace/14.keymgr_lc_disable/latest

Test location /workspace/coverage/default/14.keymgr_random.3237041478
Short name T601
Test name
Test status
Simulation time 54665233 ps
CPU time 3.61 seconds
Started Mar 26 03:28:59 PM PDT 24
Finished Mar 26 03:29:04 PM PDT 24
Peak memory 210416 kb
Host smart-2d9ae5e4-70fa-4ef6-8b54-7ab2e7df8e6e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3237041478 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_random.3237041478
Directory /workspace/14.keymgr_random/latest

Test location /workspace/coverage/default/14.keymgr_sideload.1537187962
Short name T632
Test name
Test status
Simulation time 534944267 ps
CPU time 4.21 seconds
Started Mar 26 03:28:55 PM PDT 24
Finished Mar 26 03:29:00 PM PDT 24
Peak memory 207100 kb
Host smart-e33f9e0d-e62f-407e-951f-062d632e5b83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1537187962 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload.1537187962
Directory /workspace/14.keymgr_sideload/latest

Test location /workspace/coverage/default/14.keymgr_sideload_aes.2521844571
Short name T498
Test name
Test status
Simulation time 54111968 ps
CPU time 2.86 seconds
Started Mar 26 03:28:58 PM PDT 24
Finished Mar 26 03:29:01 PM PDT 24
Peak memory 209004 kb
Host smart-a45fd85b-bbf0-40bd-857e-352a20954b73
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521844571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_aes.2521844571
Directory /workspace/14.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/14.keymgr_sideload_kmac.2270353118
Short name T494
Test name
Test status
Simulation time 78296719 ps
CPU time 2.44 seconds
Started Mar 26 03:28:45 PM PDT 24
Finished Mar 26 03:28:48 PM PDT 24
Peak memory 207092 kb
Host smart-8197bc4a-3d32-42e2-a9d9-0b77551dbc33
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270353118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_kmac.2270353118
Directory /workspace/14.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/14.keymgr_sideload_otbn.3325164730
Short name T701
Test name
Test status
Simulation time 62701932 ps
CPU time 2.54 seconds
Started Mar 26 03:28:59 PM PDT 24
Finished Mar 26 03:29:02 PM PDT 24
Peak memory 207164 kb
Host smart-8360d6ea-d335-4cfd-afe8-fb67404d10a6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3325164730 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_otbn.3325164730
Directory /workspace/14.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/14.keymgr_sideload_protect.880761514
Short name T415
Test name
Test status
Simulation time 45766428 ps
CPU time 2.94 seconds
Started Mar 26 03:29:01 PM PDT 24
Finished Mar 26 03:29:04 PM PDT 24
Peak memory 210556 kb
Host smart-2a8a1c09-92f1-4148-ba44-cfd07b4c85d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=880761514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sideload_protect.880761514
Directory /workspace/14.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/14.keymgr_smoke.3520579136
Short name T541
Test name
Test status
Simulation time 96646885 ps
CPU time 2.65 seconds
Started Mar 26 03:28:51 PM PDT 24
Finished Mar 26 03:28:55 PM PDT 24
Peak memory 207048 kb
Host smart-a65b2fb8-21fb-43e5-b5fb-5504906d6c8f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3520579136 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_smoke.3520579136
Directory /workspace/14.keymgr_smoke/latest

Test location /workspace/coverage/default/14.keymgr_stress_all_with_rand_reset.935389293
Short name T870
Test name
Test status
Simulation time 196299167 ps
CPU time 7.33 seconds
Started Mar 26 03:28:49 PM PDT 24
Finished Mar 26 03:28:57 PM PDT 24
Peak memory 218192 kb
Host smart-70c67f56-292c-4dfa-92b5-6eb1476fa598
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935389293 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 14.keymgr_stress_all_with_rand_reset.935389293
Directory /workspace/14.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.keymgr_sw_invalid_input.3207989572
Short name T355
Test name
Test status
Simulation time 231880358 ps
CPU time 4.04 seconds
Started Mar 26 03:29:08 PM PDT 24
Finished Mar 26 03:29:12 PM PDT 24
Peak memory 219108 kb
Host smart-3b804c3c-8491-4a4d-9aa8-0738d09e09a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3207989572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sw_invalid_input.3207989572
Directory /workspace/14.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/14.keymgr_sync_async_fault_cross.4225246107
Short name T598
Test name
Test status
Simulation time 190098589 ps
CPU time 2.88 seconds
Started Mar 26 03:28:50 PM PDT 24
Finished Mar 26 03:28:53 PM PDT 24
Peak memory 210668 kb
Host smart-11948d7c-3f03-43f9-a925-a0471ef73aa0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4225246107 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.keymgr_sync_async_fault_cross.4225246107
Directory /workspace/14.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/15.keymgr_alert_test.2520082786
Short name T697
Test name
Test status
Simulation time 17626963 ps
CPU time 0.98 seconds
Started Mar 26 03:28:58 PM PDT 24
Finished Mar 26 03:29:00 PM PDT 24
Peak memory 206472 kb
Host smart-acf5d74a-b2fe-4ee3-9274-c86085e3d036
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2520082786 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_alert_test.2520082786
Directory /workspace/15.keymgr_alert_test/latest

Test location /workspace/coverage/default/15.keymgr_cfg_regwen.2315586963
Short name T407
Test name
Test status
Simulation time 83567227 ps
CPU time 4.2 seconds
Started Mar 26 03:28:55 PM PDT 24
Finished Mar 26 03:29:00 PM PDT 24
Peak memory 214600 kb
Host smart-400a8b55-d420-4da8-90d7-82f7b15ce6a3
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2315586963 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_cfg_regwen.2315586963
Directory /workspace/15.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/15.keymgr_direct_to_disabled.2124994877
Short name T652
Test name
Test status
Simulation time 660174751 ps
CPU time 2.13 seconds
Started Mar 26 03:28:59 PM PDT 24
Finished Mar 26 03:29:02 PM PDT 24
Peak memory 210236 kb
Host smart-7f943f1d-5771-4dd4-beca-f1de1a334938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124994877 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_direct_to_disabled.2124994877
Directory /workspace/15.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/15.keymgr_kmac_rsp_err.930365
Short name T286
Test name
Test status
Simulation time 405808060 ps
CPU time 6.76 seconds
Started Mar 26 03:28:57 PM PDT 24
Finished Mar 26 03:29:04 PM PDT 24
Peak memory 222824 kb
Host smart-9fe0d5cf-453c-40f3-9a2d-1e0f1ef2311a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=930365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_kmac_rsp_err.930365
Directory /workspace/15.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/15.keymgr_random.1297344430
Short name T883
Test name
Test status
Simulation time 82843552 ps
CPU time 3.71 seconds
Started Mar 26 03:28:56 PM PDT 24
Finished Mar 26 03:29:00 PM PDT 24
Peak memory 209640 kb
Host smart-65397e00-951c-4b1a-84eb-eb47f9518351
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1297344430 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_random.1297344430
Directory /workspace/15.keymgr_random/latest

Test location /workspace/coverage/default/15.keymgr_sideload.1560902865
Short name T588
Test name
Test status
Simulation time 879834164 ps
CPU time 3.1 seconds
Started Mar 26 03:28:52 PM PDT 24
Finished Mar 26 03:28:57 PM PDT 24
Peak memory 207156 kb
Host smart-585f4780-664d-40d4-968d-1f24b0e927a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1560902865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload.1560902865
Directory /workspace/15.keymgr_sideload/latest

Test location /workspace/coverage/default/15.keymgr_sideload_aes.4157319086
Short name T137
Test name
Test status
Simulation time 36511318 ps
CPU time 2.61 seconds
Started Mar 26 03:28:56 PM PDT 24
Finished Mar 26 03:28:59 PM PDT 24
Peak memory 207676 kb
Host smart-32cea73f-3125-4a4d-914d-8a2515f59032
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4157319086 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_aes.4157319086
Directory /workspace/15.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/15.keymgr_sideload_kmac.3649531759
Short name T567
Test name
Test status
Simulation time 196967128 ps
CPU time 3.21 seconds
Started Mar 26 03:28:41 PM PDT 24
Finished Mar 26 03:28:45 PM PDT 24
Peak memory 208944 kb
Host smart-6a80ea6d-6ccd-40db-ba3e-c7ac3801ea55
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3649531759 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_kmac.3649531759
Directory /workspace/15.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/15.keymgr_sideload_otbn.707054149
Short name T678
Test name
Test status
Simulation time 194145539 ps
CPU time 2.89 seconds
Started Mar 26 03:28:57 PM PDT 24
Finished Mar 26 03:29:01 PM PDT 24
Peak memory 207140 kb
Host smart-e67ada6a-84e8-41b4-a452-74f7aab7b496
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=707054149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sideload_otbn.707054149
Directory /workspace/15.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/15.keymgr_smoke.1565134534
Short name T463
Test name
Test status
Simulation time 396197552 ps
CPU time 9.48 seconds
Started Mar 26 03:28:52 PM PDT 24
Finished Mar 26 03:29:03 PM PDT 24
Peak memory 208060 kb
Host smart-8843897f-e4b0-4014-84aa-8d37d759703c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565134534 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_smoke.1565134534
Directory /workspace/15.keymgr_smoke/latest

Test location /workspace/coverage/default/15.keymgr_sw_invalid_input.2843791093
Short name T402
Test name
Test status
Simulation time 482838493 ps
CPU time 3.49 seconds
Started Mar 26 03:28:46 PM PDT 24
Finished Mar 26 03:28:50 PM PDT 24
Peak memory 208600 kb
Host smart-64c24859-e4de-4004-b4a8-4102830a1ee4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2843791093 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sw_invalid_input.2843791093
Directory /workspace/15.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/15.keymgr_sync_async_fault_cross.2002354864
Short name T53
Test name
Test status
Simulation time 179978946 ps
CPU time 2.21 seconds
Started Mar 26 03:29:02 PM PDT 24
Finished Mar 26 03:29:04 PM PDT 24
Peak memory 210448 kb
Host smart-7160fdcf-6845-4724-8519-13f03f6691a9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2002354864 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.keymgr_sync_async_fault_cross.2002354864
Directory /workspace/15.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/16.keymgr_alert_test.3550391045
Short name T837
Test name
Test status
Simulation time 22745483 ps
CPU time 0.85 seconds
Started Mar 26 03:28:54 PM PDT 24
Finished Mar 26 03:28:56 PM PDT 24
Peak memory 206296 kb
Host smart-b81eac14-76d9-464d-828d-d2bf8a61ae7e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3550391045 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_alert_test.3550391045
Directory /workspace/16.keymgr_alert_test/latest

Test location /workspace/coverage/default/16.keymgr_direct_to_disabled.371718061
Short name T860
Test name
Test status
Simulation time 161063728 ps
CPU time 1.79 seconds
Started Mar 26 03:28:47 PM PDT 24
Finished Mar 26 03:28:49 PM PDT 24
Peak memory 207808 kb
Host smart-bf12a5a3-f5db-471a-a72f-933d5553317d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=371718061 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_direct_to_disabled.371718061
Directory /workspace/16.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/16.keymgr_hwsw_invalid_input.4210688902
Short name T704
Test name
Test status
Simulation time 37547780 ps
CPU time 2.71 seconds
Started Mar 26 03:28:52 PM PDT 24
Finished Mar 26 03:28:55 PM PDT 24
Peak memory 209668 kb
Host smart-9228b50f-bd82-4fdc-90cb-e6fbff64c84d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210688902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_hwsw_invalid_input.4210688902
Directory /workspace/16.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_kmac_rsp_err.2289808823
Short name T299
Test name
Test status
Simulation time 74776616 ps
CPU time 4.78 seconds
Started Mar 26 03:28:54 PM PDT 24
Finished Mar 26 03:29:00 PM PDT 24
Peak memory 214696 kb
Host smart-419ee7be-4091-44c2-90e0-264a07c80298
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289808823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_kmac_rsp_err.2289808823
Directory /workspace/16.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/16.keymgr_lc_disable.2473684664
Short name T49
Test name
Test status
Simulation time 95292309 ps
CPU time 2.46 seconds
Started Mar 26 03:28:58 PM PDT 24
Finished Mar 26 03:29:01 PM PDT 24
Peak memory 214688 kb
Host smart-cdf44d55-4a8c-4241-92b7-d8801d245e1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2473684664 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_lc_disable.2473684664
Directory /workspace/16.keymgr_lc_disable/latest

Test location /workspace/coverage/default/16.keymgr_random.1314208671
Short name T895
Test name
Test status
Simulation time 838196981 ps
CPU time 20.7 seconds
Started Mar 26 03:29:03 PM PDT 24
Finished Mar 26 03:29:24 PM PDT 24
Peak memory 208948 kb
Host smart-0175266e-95ef-41c7-842c-174e6ec97f46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1314208671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_random.1314208671
Directory /workspace/16.keymgr_random/latest

Test location /workspace/coverage/default/16.keymgr_sideload.746985961
Short name T773
Test name
Test status
Simulation time 970783156 ps
CPU time 4.26 seconds
Started Mar 26 03:28:58 PM PDT 24
Finished Mar 26 03:29:03 PM PDT 24
Peak memory 207168 kb
Host smart-fd25c7ef-e7e2-438f-a8c4-34791112e28e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=746985961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload.746985961
Directory /workspace/16.keymgr_sideload/latest

Test location /workspace/coverage/default/16.keymgr_sideload_aes.449737276
Short name T754
Test name
Test status
Simulation time 71520324 ps
CPU time 3.19 seconds
Started Mar 26 03:28:49 PM PDT 24
Finished Mar 26 03:28:53 PM PDT 24
Peak memory 208912 kb
Host smart-eebb111b-ff8a-42ae-a630-1ba1b5b53b69
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449737276 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_aes.449737276
Directory /workspace/16.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/16.keymgr_sideload_kmac.4258726253
Short name T315
Test name
Test status
Simulation time 104105528 ps
CPU time 4.43 seconds
Started Mar 26 03:28:59 PM PDT 24
Finished Mar 26 03:29:04 PM PDT 24
Peak memory 208792 kb
Host smart-bb0d7f9b-5f6e-4794-8f92-88b708c1efa2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4258726253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_kmac.4258726253
Directory /workspace/16.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/16.keymgr_sideload_otbn.2833652321
Short name T538
Test name
Test status
Simulation time 579595244 ps
CPU time 4.27 seconds
Started Mar 26 03:28:52 PM PDT 24
Finished Mar 26 03:28:56 PM PDT 24
Peak memory 208884 kb
Host smart-5fb26065-bc88-40d0-9c40-9d29eda16c8b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2833652321 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_otbn.2833652321
Directory /workspace/16.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/16.keymgr_sideload_protect.3149268256
Short name T903
Test name
Test status
Simulation time 1000671893 ps
CPU time 6.53 seconds
Started Mar 26 03:28:57 PM PDT 24
Finished Mar 26 03:29:04 PM PDT 24
Peak memory 208476 kb
Host smart-dcc7d4e9-5a2f-4d67-8b09-ee900b8b9bb9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149268256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sideload_protect.3149268256
Directory /workspace/16.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/16.keymgr_smoke.2944413628
Short name T439
Test name
Test status
Simulation time 779073511 ps
CPU time 5.45 seconds
Started Mar 26 03:28:56 PM PDT 24
Finished Mar 26 03:29:02 PM PDT 24
Peak memory 208220 kb
Host smart-dd069759-95b6-480f-8b36-a0141dee8053
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2944413628 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_smoke.2944413628
Directory /workspace/16.keymgr_smoke/latest

Test location /workspace/coverage/default/16.keymgr_stress_all.3115787978
Short name T312
Test name
Test status
Simulation time 24096482373 ps
CPU time 139.1 seconds
Started Mar 26 03:29:10 PM PDT 24
Finished Mar 26 03:31:30 PM PDT 24
Peak memory 217276 kb
Host smart-2355ef6f-63ff-46ef-8447-46a4ba8f3767
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3115787978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_stress_all.3115787978
Directory /workspace/16.keymgr_stress_all/latest

Test location /workspace/coverage/default/16.keymgr_sw_invalid_input.2675464023
Short name T271
Test name
Test status
Simulation time 134221076 ps
CPU time 2.76 seconds
Started Mar 26 03:28:56 PM PDT 24
Finished Mar 26 03:29:00 PM PDT 24
Peak memory 209616 kb
Host smart-df8e989e-109b-4bad-b423-134262d95331
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2675464023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sw_invalid_input.2675464023
Directory /workspace/16.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/16.keymgr_sync_async_fault_cross.1925020046
Short name T453
Test name
Test status
Simulation time 208395246 ps
CPU time 2.89 seconds
Started Mar 26 03:28:53 PM PDT 24
Finished Mar 26 03:28:56 PM PDT 24
Peak memory 210332 kb
Host smart-d2cfffaf-085f-423c-a140-50a0f12f56b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925020046 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.keymgr_sync_async_fault_cross.1925020046
Directory /workspace/16.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/17.keymgr_alert_test.3769332997
Short name T551
Test name
Test status
Simulation time 15869008 ps
CPU time 0.82 seconds
Started Mar 26 03:28:57 PM PDT 24
Finished Mar 26 03:28:59 PM PDT 24
Peak memory 206296 kb
Host smart-7342de79-6f7b-4dbf-8450-b234c0fc2cb8
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769332997 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_alert_test.3769332997
Directory /workspace/17.keymgr_alert_test/latest

Test location /workspace/coverage/default/17.keymgr_cfg_regwen.927027326
Short name T836
Test name
Test status
Simulation time 43447629 ps
CPU time 3.15 seconds
Started Mar 26 03:28:56 PM PDT 24
Finished Mar 26 03:28:59 PM PDT 24
Peak memory 214700 kb
Host smart-46ee5dc9-b724-453d-8952-dbe4c7850821
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=927027326 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_cfg_regwen.927027326
Directory /workspace/17.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/17.keymgr_custom_cm.3127646484
Short name T885
Test name
Test status
Simulation time 98851995 ps
CPU time 2.43 seconds
Started Mar 26 03:28:53 PM PDT 24
Finished Mar 26 03:28:56 PM PDT 24
Peak memory 209428 kb
Host smart-22edc32d-95b2-40ea-b763-09db4fc52f74
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127646484 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_custom_cm.3127646484
Directory /workspace/17.keymgr_custom_cm/latest

Test location /workspace/coverage/default/17.keymgr_direct_to_disabled.256918112
Short name T878
Test name
Test status
Simulation time 195584980 ps
CPU time 1.9 seconds
Started Mar 26 03:28:53 PM PDT 24
Finished Mar 26 03:28:55 PM PDT 24
Peak memory 207504 kb
Host smart-5b0c5319-2592-4186-8ef1-c8139848c581
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256918112 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_direct_to_disabled.256918112
Directory /workspace/17.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/17.keymgr_hwsw_invalid_input.3419490960
Short name T323
Test name
Test status
Simulation time 88811105 ps
CPU time 3.88 seconds
Started Mar 26 03:28:50 PM PDT 24
Finished Mar 26 03:28:54 PM PDT 24
Peak memory 214696 kb
Host smart-6ad9d365-241e-434e-a3b3-5304b53a0533
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419490960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_hwsw_invalid_input.3419490960
Directory /workspace/17.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_kmac_rsp_err.3572285345
Short name T200
Test name
Test status
Simulation time 1794132524 ps
CPU time 10.34 seconds
Started Mar 26 03:28:55 PM PDT 24
Finished Mar 26 03:29:06 PM PDT 24
Peak memory 214576 kb
Host smart-ee075577-5a7a-4092-bd32-09badfff428b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572285345 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_kmac_rsp_err.3572285345
Directory /workspace/17.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/17.keymgr_lc_disable.1231755426
Short name T579
Test name
Test status
Simulation time 217149832 ps
CPU time 2.45 seconds
Started Mar 26 03:28:53 PM PDT 24
Finished Mar 26 03:28:56 PM PDT 24
Peak memory 214708 kb
Host smart-44d7018d-4f11-418b-82cf-70f53c8f62b0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1231755426 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_lc_disable.1231755426
Directory /workspace/17.keymgr_lc_disable/latest

Test location /workspace/coverage/default/17.keymgr_random.3262619556
Short name T482
Test name
Test status
Simulation time 302400036 ps
CPU time 4.74 seconds
Started Mar 26 03:28:58 PM PDT 24
Finished Mar 26 03:29:03 PM PDT 24
Peak memory 209368 kb
Host smart-dfe8ff30-0ea6-40ec-87a2-28bc6752ddd3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3262619556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_random.3262619556
Directory /workspace/17.keymgr_random/latest

Test location /workspace/coverage/default/17.keymgr_sideload.3387058477
Short name T130
Test name
Test status
Simulation time 404680615 ps
CPU time 8.08 seconds
Started Mar 26 03:28:57 PM PDT 24
Finished Mar 26 03:29:05 PM PDT 24
Peak memory 208676 kb
Host smart-ce4edf0a-f896-4a91-80bd-4443f9c5d82a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3387058477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload.3387058477
Directory /workspace/17.keymgr_sideload/latest

Test location /workspace/coverage/default/17.keymgr_sideload_aes.3826645584
Short name T504
Test name
Test status
Simulation time 487107890 ps
CPU time 5.61 seconds
Started Mar 26 03:28:48 PM PDT 24
Finished Mar 26 03:28:54 PM PDT 24
Peak memory 207348 kb
Host smart-8b8b6a87-ece7-4c65-9aad-19e64aa891c4
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3826645584 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_aes.3826645584
Directory /workspace/17.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/17.keymgr_sideload_kmac.770546265
Short name T84
Test name
Test status
Simulation time 36611373 ps
CPU time 2.64 seconds
Started Mar 26 03:28:55 PM PDT 24
Finished Mar 26 03:28:58 PM PDT 24
Peak memory 209040 kb
Host smart-51389826-ded3-4ff0-acb7-c1e64d84e971
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=770546265 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_kmac.770546265
Directory /workspace/17.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/17.keymgr_sideload_otbn.279949137
Short name T304
Test name
Test status
Simulation time 2061916346 ps
CPU time 68.49 seconds
Started Mar 26 03:29:01 PM PDT 24
Finished Mar 26 03:30:10 PM PDT 24
Peak memory 208656 kb
Host smart-a181e6a8-031a-434a-a352-7a02bc5578f9
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=279949137 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_otbn.279949137
Directory /workspace/17.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/17.keymgr_sideload_protect.151860175
Short name T845
Test name
Test status
Simulation time 62965971 ps
CPU time 2.89 seconds
Started Mar 26 03:28:53 PM PDT 24
Finished Mar 26 03:28:56 PM PDT 24
Peak memory 214708 kb
Host smart-2139c085-7eed-4e4a-b518-ea4edd4d5d43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=151860175 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sideload_protect.151860175
Directory /workspace/17.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/17.keymgr_smoke.392304732
Short name T583
Test name
Test status
Simulation time 521692675 ps
CPU time 2.84 seconds
Started Mar 26 03:29:08 PM PDT 24
Finished Mar 26 03:29:16 PM PDT 24
Peak memory 208184 kb
Host smart-8c2fc948-3727-444b-964a-fead11fd195d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=392304732 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_smoke.392304732
Directory /workspace/17.keymgr_smoke/latest

Test location /workspace/coverage/default/17.keymgr_stress_all.836243177
Short name T571
Test name
Test status
Simulation time 308103672 ps
CPU time 11.56 seconds
Started Mar 26 03:28:49 PM PDT 24
Finished Mar 26 03:29:01 PM PDT 24
Peak memory 215796 kb
Host smart-92502197-d691-48c6-bf5a-1eff1cf93a34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=836243177 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all.836243177
Directory /workspace/17.keymgr_stress_all/latest

Test location /workspace/coverage/default/17.keymgr_stress_all_with_rand_reset.21702492
Short name T127
Test name
Test status
Simulation time 2773197407 ps
CPU time 24.88 seconds
Started Mar 26 03:28:58 PM PDT 24
Finished Mar 26 03:29:23 PM PDT 24
Peak memory 223060 kb
Host smart-298941ad-cff8-49af-9e91-1dc9a303b3e7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21702492 -assert nopostp
roc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/defa
ult.vdb -cm_log /dev/null -cm_name 17.keymgr_stress_all_with_rand_reset.21702492
Directory /workspace/17.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.keymgr_sw_invalid_input.1941280630
Short name T683
Test name
Test status
Simulation time 94633369 ps
CPU time 4.48 seconds
Started Mar 26 03:28:58 PM PDT 24
Finished Mar 26 03:29:02 PM PDT 24
Peak memory 209148 kb
Host smart-b525846a-a237-4f53-a6a4-eb824c50e9c7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1941280630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sw_invalid_input.1941280630
Directory /workspace/17.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/17.keymgr_sync_async_fault_cross.743134816
Short name T668
Test name
Test status
Simulation time 361736435 ps
CPU time 2.45 seconds
Started Mar 26 03:28:59 PM PDT 24
Finished Mar 26 03:29:02 PM PDT 24
Peak memory 210616 kb
Host smart-6252e120-bd56-4550-9651-0e9fbecf29af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=743134816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.keymgr_sync_async_fault_cross.743134816
Directory /workspace/17.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/18.keymgr_alert_test.3966706516
Short name T751
Test name
Test status
Simulation time 12899127 ps
CPU time 0.87 seconds
Started Mar 26 03:29:18 PM PDT 24
Finished Mar 26 03:29:19 PM PDT 24
Peak memory 206304 kb
Host smart-c436644a-b16e-45bf-af84-36ac15c4077a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3966706516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_alert_test.3966706516
Directory /workspace/18.keymgr_alert_test/latest

Test location /workspace/coverage/default/18.keymgr_cfg_regwen.3579057274
Short name T421
Test name
Test status
Simulation time 130114080 ps
CPU time 6.75 seconds
Started Mar 26 03:29:02 PM PDT 24
Finished Mar 26 03:29:09 PM PDT 24
Peak memory 214664 kb
Host smart-e4efe1d1-9e2f-4d4f-a442-6cfb13a856c5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3579057274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_cfg_regwen.3579057274
Directory /workspace/18.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/18.keymgr_custom_cm.4179305154
Short name T22
Test name
Test status
Simulation time 785707739 ps
CPU time 2.91 seconds
Started Mar 26 03:28:53 PM PDT 24
Finished Mar 26 03:28:58 PM PDT 24
Peak memory 217048 kb
Host smart-79c4452b-2e28-43ef-96ac-b48e434a6c48
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4179305154 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_custom_cm.4179305154
Directory /workspace/18.keymgr_custom_cm/latest

Test location /workspace/coverage/default/18.keymgr_direct_to_disabled.1154949668
Short name T293
Test name
Test status
Simulation time 1546876371 ps
CPU time 5.2 seconds
Started Mar 26 03:28:57 PM PDT 24
Finished Mar 26 03:29:02 PM PDT 24
Peak memory 208592 kb
Host smart-79a1101b-9053-483f-9421-9fb89e0a987a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1154949668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_direct_to_disabled.1154949668
Directory /workspace/18.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/18.keymgr_hwsw_invalid_input.2825278133
Short name T93
Test name
Test status
Simulation time 797067113 ps
CPU time 6.56 seconds
Started Mar 26 03:28:50 PM PDT 24
Finished Mar 26 03:28:57 PM PDT 24
Peak memory 222788 kb
Host smart-5bb4c150-2d14-4cd3-a8f2-cd14c7acc02b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2825278133 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_hwsw_invalid_input.2825278133
Directory /workspace/18.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/18.keymgr_kmac_rsp_err.934086846
Short name T298
Test name
Test status
Simulation time 137245866 ps
CPU time 4.13 seconds
Started Mar 26 03:29:11 PM PDT 24
Finished Mar 26 03:29:15 PM PDT 24
Peak memory 214676 kb
Host smart-61ade200-be84-4241-abc9-a6f32015b3b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=934086846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_kmac_rsp_err.934086846
Directory /workspace/18.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/18.keymgr_lc_disable.1862771881
Short name T493
Test name
Test status
Simulation time 459080232 ps
CPU time 3.66 seconds
Started Mar 26 03:28:52 PM PDT 24
Finished Mar 26 03:28:56 PM PDT 24
Peak memory 214716 kb
Host smart-85421409-5d9f-41a3-a6cb-013416c20c45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1862771881 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_lc_disable.1862771881
Directory /workspace/18.keymgr_lc_disable/latest

Test location /workspace/coverage/default/18.keymgr_random.2905630244
Short name T742
Test name
Test status
Simulation time 155034165 ps
CPU time 4.79 seconds
Started Mar 26 03:28:55 PM PDT 24
Finished Mar 26 03:29:01 PM PDT 24
Peak memory 207588 kb
Host smart-0da61442-4b45-42c7-8bcf-c1fd187bcf9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905630244 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_random.2905630244
Directory /workspace/18.keymgr_random/latest

Test location /workspace/coverage/default/18.keymgr_sideload.2141551505
Short name T809
Test name
Test status
Simulation time 166188360 ps
CPU time 4.82 seconds
Started Mar 26 03:28:53 PM PDT 24
Finished Mar 26 03:28:59 PM PDT 24
Peak memory 208244 kb
Host smart-6ac9cefd-42d5-468f-9767-7324923749e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2141551505 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload.2141551505
Directory /workspace/18.keymgr_sideload/latest

Test location /workspace/coverage/default/18.keymgr_sideload_aes.2226298885
Short name T316
Test name
Test status
Simulation time 35819681 ps
CPU time 2.36 seconds
Started Mar 26 03:28:49 PM PDT 24
Finished Mar 26 03:28:52 PM PDT 24
Peak memory 207124 kb
Host smart-057de6fa-8b60-4e7d-91d1-6977a9f4b7ea
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226298885 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_aes.2226298885
Directory /workspace/18.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/18.keymgr_sideload_kmac.29436006
Short name T372
Test name
Test status
Simulation time 44834559 ps
CPU time 1.82 seconds
Started Mar 26 03:28:58 PM PDT 24
Finished Mar 26 03:29:00 PM PDT 24
Peak memory 207064 kb
Host smart-136797b4-ad29-4e47-9bf4-6de725d2f882
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29436006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_kmac.29436006
Directory /workspace/18.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/18.keymgr_sideload_otbn.4164791684
Short name T620
Test name
Test status
Simulation time 157943700 ps
CPU time 2.6 seconds
Started Mar 26 03:28:52 PM PDT 24
Finished Mar 26 03:28:56 PM PDT 24
Peak memory 208792 kb
Host smart-68f29eb1-a099-4f78-a057-ed508ac870b6
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4164791684 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_otbn.4164791684
Directory /workspace/18.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/18.keymgr_sideload_protect.3563010893
Short name T122
Test name
Test status
Simulation time 1027531054 ps
CPU time 6.66 seconds
Started Mar 26 03:29:08 PM PDT 24
Finished Mar 26 03:29:15 PM PDT 24
Peak memory 209644 kb
Host smart-17b35018-bf0a-4550-a429-9849a182575c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3563010893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sideload_protect.3563010893
Directory /workspace/18.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/18.keymgr_smoke.4113922035
Short name T499
Test name
Test status
Simulation time 89500445 ps
CPU time 2.44 seconds
Started Mar 26 03:28:56 PM PDT 24
Finished Mar 26 03:28:59 PM PDT 24
Peak memory 207084 kb
Host smart-32f9decc-a9bc-4e0b-b242-ec64abc8eed4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4113922035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_smoke.4113922035
Directory /workspace/18.keymgr_smoke/latest

Test location /workspace/coverage/default/18.keymgr_stress_all.1247644599
Short name T414
Test name
Test status
Simulation time 103584236 ps
CPU time 3.06 seconds
Started Mar 26 03:28:53 PM PDT 24
Finished Mar 26 03:29:02 PM PDT 24
Peak memory 208124 kb
Host smart-b7de1e83-3953-499a-a568-ba717aedeb5f
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1247644599 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all.1247644599
Directory /workspace/18.keymgr_stress_all/latest

Test location /workspace/coverage/default/18.keymgr_stress_all_with_rand_reset.4012234139
Short name T699
Test name
Test status
Simulation time 1869342495 ps
CPU time 22.51 seconds
Started Mar 26 03:29:14 PM PDT 24
Finished Mar 26 03:29:37 PM PDT 24
Peak memory 222944 kb
Host smart-4b356379-b4b0-489b-a4be-1c8db9c0aa7f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4012234139 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 18.keymgr_stress_all_with_rand_reset.4012234139
Directory /workspace/18.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.keymgr_sw_invalid_input.1587523153
Short name T785
Test name
Test status
Simulation time 7388703004 ps
CPU time 18.25 seconds
Started Mar 26 03:28:54 PM PDT 24
Finished Mar 26 03:29:13 PM PDT 24
Peak memory 219068 kb
Host smart-17c9f53b-c353-45be-b043-91bc33364034
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587523153 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.keymgr_sw_invalid_input.1587523153
Directory /workspace/18.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_alert_test.3132021521
Short name T770
Test name
Test status
Simulation time 69428686 ps
CPU time 0.88 seconds
Started Mar 26 03:29:01 PM PDT 24
Finished Mar 26 03:29:02 PM PDT 24
Peak memory 206328 kb
Host smart-43dd2c79-0803-4649-bacf-70351825b3d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3132021521 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_alert_test.3132021521
Directory /workspace/19.keymgr_alert_test/latest

Test location /workspace/coverage/default/19.keymgr_cfg_regwen.2717965185
Short name T386
Test name
Test status
Simulation time 253335018 ps
CPU time 2.97 seconds
Started Mar 26 03:29:02 PM PDT 24
Finished Mar 26 03:29:05 PM PDT 24
Peak memory 215768 kb
Host smart-cf65de69-3596-44de-adcf-0583bfa22810
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2717965185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_cfg_regwen.2717965185
Directory /workspace/19.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/19.keymgr_custom_cm.361818421
Short name T606
Test name
Test status
Simulation time 73844158 ps
CPU time 3.31 seconds
Started Mar 26 03:28:56 PM PDT 24
Finished Mar 26 03:29:00 PM PDT 24
Peak memory 210036 kb
Host smart-a77e3189-c3c7-4b70-b802-728a5681b882
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=361818421 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_custom_cm.361818421
Directory /workspace/19.keymgr_custom_cm/latest

Test location /workspace/coverage/default/19.keymgr_direct_to_disabled.3369212853
Short name T75
Test name
Test status
Simulation time 79828985 ps
CPU time 3.43 seconds
Started Mar 26 03:29:05 PM PDT 24
Finished Mar 26 03:29:09 PM PDT 24
Peak memory 218216 kb
Host smart-37228a1e-bcb9-4755-971b-fd95fa7ee320
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3369212853 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_direct_to_disabled.3369212853
Directory /workspace/19.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/19.keymgr_hwsw_invalid_input.3714921895
Short name T306
Test name
Test status
Simulation time 877964284 ps
CPU time 3.76 seconds
Started Mar 26 03:29:06 PM PDT 24
Finished Mar 26 03:29:10 PM PDT 24
Peak memory 210116 kb
Host smart-031f9ffd-d26d-4c94-9003-c7289fdee1e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3714921895 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_hwsw_invalid_input.3714921895
Directory /workspace/19.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_lc_disable.3795865906
Short name T477
Test name
Test status
Simulation time 33705388 ps
CPU time 1.96 seconds
Started Mar 26 03:29:09 PM PDT 24
Finished Mar 26 03:29:11 PM PDT 24
Peak memory 206940 kb
Host smart-47a40782-19ff-4ecd-a7a2-2bbcb1706bd4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3795865906 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_lc_disable.3795865906
Directory /workspace/19.keymgr_lc_disable/latest

Test location /workspace/coverage/default/19.keymgr_random.3041678103
Short name T905
Test name
Test status
Simulation time 965878469 ps
CPU time 22.54 seconds
Started Mar 26 03:28:58 PM PDT 24
Finished Mar 26 03:29:21 PM PDT 24
Peak memory 208220 kb
Host smart-9b0363e9-5c66-4441-b979-392abba32f15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3041678103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_random.3041678103
Directory /workspace/19.keymgr_random/latest

Test location /workspace/coverage/default/19.keymgr_sideload.3813307432
Short name T262
Test name
Test status
Simulation time 1827072829 ps
CPU time 23.3 seconds
Started Mar 26 03:28:58 PM PDT 24
Finished Mar 26 03:29:22 PM PDT 24
Peak memory 208856 kb
Host smart-a68244a2-5fcd-49ee-a901-0970e0ffe918
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3813307432 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload.3813307432
Directory /workspace/19.keymgr_sideload/latest

Test location /workspace/coverage/default/19.keymgr_sideload_aes.2786101513
Short name T817
Test name
Test status
Simulation time 344759824 ps
CPU time 4.39 seconds
Started Mar 26 03:29:04 PM PDT 24
Finished Mar 26 03:29:09 PM PDT 24
Peak memory 207580 kb
Host smart-f9653c1f-3ab3-440c-98ff-d3d16b83afb9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2786101513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_aes.2786101513
Directory /workspace/19.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/19.keymgr_sideload_kmac.1719181013
Short name T476
Test name
Test status
Simulation time 181221933 ps
CPU time 2.6 seconds
Started Mar 26 03:28:51 PM PDT 24
Finished Mar 26 03:28:59 PM PDT 24
Peak memory 207008 kb
Host smart-9fc21cd4-14a0-4be1-98bd-5a6ad2f7c98e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1719181013 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_kmac.1719181013
Directory /workspace/19.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/19.keymgr_sideload_otbn.3842805626
Short name T694
Test name
Test status
Simulation time 259807152 ps
CPU time 3.15 seconds
Started Mar 26 03:29:11 PM PDT 24
Finished Mar 26 03:29:15 PM PDT 24
Peak memory 207172 kb
Host smart-b143165d-c740-4eb1-b70f-fe7a2bb58753
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842805626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_otbn.3842805626
Directory /workspace/19.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/19.keymgr_sideload_protect.3996827657
Short name T834
Test name
Test status
Simulation time 73224058 ps
CPU time 2.27 seconds
Started Mar 26 03:29:03 PM PDT 24
Finished Mar 26 03:29:05 PM PDT 24
Peak memory 216168 kb
Host smart-c3c53e63-221f-4a6b-9cb4-0a987caa0492
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3996827657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sideload_protect.3996827657
Directory /workspace/19.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/19.keymgr_smoke.2951700280
Short name T467
Test name
Test status
Simulation time 353167682 ps
CPU time 8.27 seconds
Started Mar 26 03:29:09 PM PDT 24
Finished Mar 26 03:29:18 PM PDT 24
Peak memory 206988 kb
Host smart-dbd94a59-1d57-4907-8c33-8fbe81153f83
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951700280 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_smoke.2951700280
Directory /workspace/19.keymgr_smoke/latest

Test location /workspace/coverage/default/19.keymgr_stress_all.751946124
Short name T335
Test name
Test status
Simulation time 1753618105 ps
CPU time 34.3 seconds
Started Mar 26 03:29:00 PM PDT 24
Finished Mar 26 03:29:35 PM PDT 24
Peak memory 215716 kb
Host smart-f33d1c28-fce6-4951-84b9-6b110b1ac0dd
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=751946124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all.751946124
Directory /workspace/19.keymgr_stress_all/latest

Test location /workspace/coverage/default/19.keymgr_stress_all_with_rand_reset.2414519612
Short name T126
Test name
Test status
Simulation time 185932911 ps
CPU time 6.71 seconds
Started Mar 26 03:29:00 PM PDT 24
Finished Mar 26 03:29:07 PM PDT 24
Peak memory 222904 kb
Host smart-f10797c5-8c79-4bb1-884a-5f137c91adf0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2414519612 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 19.keymgr_stress_all_with_rand_reset.2414519612
Directory /workspace/19.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.keymgr_sw_invalid_input.1323234222
Short name T534
Test name
Test status
Simulation time 241747752 ps
CPU time 4.01 seconds
Started Mar 26 03:28:56 PM PDT 24
Finished Mar 26 03:29:01 PM PDT 24
Peak memory 210136 kb
Host smart-e54af7b6-d004-4fb8-88a1-bbb138472e79
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1323234222 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sw_invalid_input.1323234222
Directory /workspace/19.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/19.keymgr_sync_async_fault_cross.4150301433
Short name T474
Test name
Test status
Simulation time 147462114 ps
CPU time 2.48 seconds
Started Mar 26 03:28:58 PM PDT 24
Finished Mar 26 03:29:01 PM PDT 24
Peak memory 210196 kb
Host smart-7397ccca-4470-4f3e-a7cf-ac1f7f4f4e51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4150301433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.keymgr_sync_async_fault_cross.4150301433
Directory /workspace/19.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/2.keymgr_cfg_regwen.2713062726
Short name T412
Test name
Test status
Simulation time 58132834 ps
CPU time 3.22 seconds
Started Mar 26 03:28:06 PM PDT 24
Finished Mar 26 03:28:09 PM PDT 24
Peak memory 214976 kb
Host smart-059c7e01-b514-4b71-b018-cbd985482268
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2713062726 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_cfg_regwen.2713062726
Directory /workspace/2.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/2.keymgr_custom_cm.787510139
Short name T706
Test name
Test status
Simulation time 1159176062 ps
CPU time 10.2 seconds
Started Mar 26 03:28:17 PM PDT 24
Finished Mar 26 03:28:28 PM PDT 24
Peak memory 221764 kb
Host smart-3362d242-c1bd-4b51-8c95-5d99725577b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=787510139 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_custom_cm.787510139
Directory /workspace/2.keymgr_custom_cm/latest

Test location /workspace/coverage/default/2.keymgr_direct_to_disabled.2837064047
Short name T398
Test name
Test status
Simulation time 261256560 ps
CPU time 2.25 seconds
Started Mar 26 03:28:18 PM PDT 24
Finished Mar 26 03:28:20 PM PDT 24
Peak memory 210096 kb
Host smart-a023e218-bcfa-4da8-9b9d-2a77a5c44e46
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2837064047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_direct_to_disabled.2837064047
Directory /workspace/2.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/2.keymgr_hwsw_invalid_input.2782512371
Short name T389
Test name
Test status
Simulation time 980317290 ps
CPU time 12.8 seconds
Started Mar 26 03:28:07 PM PDT 24
Finished Mar 26 03:28:20 PM PDT 24
Peak memory 214692 kb
Host smart-48984d85-11fd-4d45-9c08-b34cd92c1831
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2782512371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_hwsw_invalid_input.2782512371
Directory /workspace/2.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_kmac_rsp_err.2593641809
Short name T246
Test name
Test status
Simulation time 1592094225 ps
CPU time 15.29 seconds
Started Mar 26 03:28:06 PM PDT 24
Finished Mar 26 03:28:21 PM PDT 24
Peak memory 214580 kb
Host smart-5acc8406-efab-4e75-bae7-ed4dd9eca4d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593641809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_kmac_rsp_err.2593641809
Directory /workspace/2.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/2.keymgr_lc_disable.3846970332
Short name T455
Test name
Test status
Simulation time 438737715 ps
CPU time 4.05 seconds
Started Mar 26 03:28:17 PM PDT 24
Finished Mar 26 03:28:21 PM PDT 24
Peak memory 210192 kb
Host smart-6a021d9b-d2db-4b92-9f40-a35bdfd6fbb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846970332 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_lc_disable.3846970332
Directory /workspace/2.keymgr_lc_disable/latest

Test location /workspace/coverage/default/2.keymgr_random.3254075676
Short name T605
Test name
Test status
Simulation time 998141428 ps
CPU time 11.49 seconds
Started Mar 26 03:28:03 PM PDT 24
Finished Mar 26 03:28:15 PM PDT 24
Peak memory 218792 kb
Host smart-39191cc9-afd2-43f8-9d06-bdd9ba023782
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3254075676 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_random.3254075676
Directory /workspace/2.keymgr_random/latest

Test location /workspace/coverage/default/2.keymgr_sec_cm.638080596
Short name T12
Test name
Test status
Simulation time 4517402923 ps
CPU time 24.62 seconds
Started Mar 26 03:28:07 PM PDT 24
Finished Mar 26 03:28:32 PM PDT 24
Peak memory 233664 kb
Host smart-09403a98-4d7d-4b63-82f7-103980947f33
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=638080596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sec_cm.638080596
Directory /workspace/2.keymgr_sec_cm/latest

Test location /workspace/coverage/default/2.keymgr_sideload.2190838073
Short name T890
Test name
Test status
Simulation time 220461438 ps
CPU time 4.52 seconds
Started Mar 26 03:28:08 PM PDT 24
Finished Mar 26 03:28:12 PM PDT 24
Peak memory 207136 kb
Host smart-bd7fe098-bfdc-4e06-9da2-ce651c261275
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2190838073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload.2190838073
Directory /workspace/2.keymgr_sideload/latest

Test location /workspace/coverage/default/2.keymgr_sideload_aes.1321860964
Short name T554
Test name
Test status
Simulation time 61504889 ps
CPU time 3.25 seconds
Started Mar 26 03:28:16 PM PDT 24
Finished Mar 26 03:28:19 PM PDT 24
Peak memory 209180 kb
Host smart-4a8a7eb0-330d-46f7-b045-8aa34d55e283
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1321860964 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_aes.1321860964
Directory /workspace/2.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/2.keymgr_sideload_kmac.2245403653
Short name T373
Test name
Test status
Simulation time 201891052 ps
CPU time 2.9 seconds
Started Mar 26 03:28:10 PM PDT 24
Finished Mar 26 03:28:13 PM PDT 24
Peak memory 207184 kb
Host smart-c2a20a3f-2ab1-4a2d-9b0b-e669b999a629
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2245403653 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_kmac.2245403653
Directory /workspace/2.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/2.keymgr_sideload_otbn.3485020094
Short name T346
Test name
Test status
Simulation time 133724398 ps
CPU time 4.39 seconds
Started Mar 26 03:28:14 PM PDT 24
Finished Mar 26 03:28:19 PM PDT 24
Peak memory 208912 kb
Host smart-f6211613-52dc-4c9d-a5e6-2cbf28e68323
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3485020094 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_otbn.3485020094
Directory /workspace/2.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/2.keymgr_sideload_protect.3682209192
Short name T495
Test name
Test status
Simulation time 992744393 ps
CPU time 6.82 seconds
Started Mar 26 03:28:06 PM PDT 24
Finished Mar 26 03:28:14 PM PDT 24
Peak memory 218568 kb
Host smart-aa8d643a-af4b-43dd-b214-9f9365825818
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3682209192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sideload_protect.3682209192
Directory /workspace/2.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/2.keymgr_smoke.298896741
Short name T884
Test name
Test status
Simulation time 58734609 ps
CPU time 2.14 seconds
Started Mar 26 03:28:16 PM PDT 24
Finished Mar 26 03:28:19 PM PDT 24
Peak memory 207192 kb
Host smart-d6e578cd-0fcb-4641-b27a-9f7989da3616
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=298896741 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_smoke.298896741
Directory /workspace/2.keymgr_smoke/latest

Test location /workspace/coverage/default/2.keymgr_sw_invalid_input.1995147620
Short name T627
Test name
Test status
Simulation time 56337850 ps
CPU time 3.63 seconds
Started Mar 26 03:28:05 PM PDT 24
Finished Mar 26 03:28:14 PM PDT 24
Peak memory 208060 kb
Host smart-a745892e-9bc7-4a29-bd45-a67a540ccf20
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995147620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sw_invalid_input.1995147620
Directory /workspace/2.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/2.keymgr_sync_async_fault_cross.304887462
Short name T56
Test name
Test status
Simulation time 391911970 ps
CPU time 2.74 seconds
Started Mar 26 03:28:13 PM PDT 24
Finished Mar 26 03:28:15 PM PDT 24
Peak memory 210784 kb
Host smart-49237119-d968-4c6a-9fa9-8c0128d4970f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=304887462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.keymgr_sync_async_fault_cross.304887462
Directory /workspace/2.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/20.keymgr_alert_test.103515717
Short name T533
Test name
Test status
Simulation time 21236330 ps
CPU time 0.85 seconds
Started Mar 26 03:28:54 PM PDT 24
Finished Mar 26 03:28:56 PM PDT 24
Peak memory 206284 kb
Host smart-1e39e9fb-dce3-4306-94a5-721674bcbdd6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=103515717 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_alert_test.103515717
Directory /workspace/20.keymgr_alert_test/latest

Test location /workspace/coverage/default/20.keymgr_direct_to_disabled.886945851
Short name T575
Test name
Test status
Simulation time 22404704 ps
CPU time 1.59 seconds
Started Mar 26 03:28:54 PM PDT 24
Finished Mar 26 03:28:57 PM PDT 24
Peak memory 208192 kb
Host smart-027a5b87-224e-49f8-82be-6f3c8e671b82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=886945851 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_direct_to_disabled.886945851
Directory /workspace/20.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/20.keymgr_hwsw_invalid_input.831689339
Short name T690
Test name
Test status
Simulation time 34019783 ps
CPU time 2.53 seconds
Started Mar 26 03:29:09 PM PDT 24
Finished Mar 26 03:29:11 PM PDT 24
Peak memory 209892 kb
Host smart-d7976002-28cc-45df-8a64-0545a679d32e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=831689339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_hwsw_invalid_input.831689339
Directory /workspace/20.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_kmac_rsp_err.3937698681
Short name T283
Test name
Test status
Simulation time 538486381 ps
CPU time 5.68 seconds
Started Mar 26 03:28:53 PM PDT 24
Finished Mar 26 03:28:59 PM PDT 24
Peak memory 211752 kb
Host smart-6d249b0b-2cd7-424d-81cd-6289b72d9fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3937698681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_kmac_rsp_err.3937698681
Directory /workspace/20.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/20.keymgr_lc_disable.3109683514
Short name T211
Test name
Test status
Simulation time 464716185 ps
CPU time 12.25 seconds
Started Mar 26 03:29:12 PM PDT 24
Finished Mar 26 03:29:24 PM PDT 24
Peak memory 219772 kb
Host smart-594c1b6e-4935-456c-a73c-66f10eef4ca3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3109683514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_lc_disable.3109683514
Directory /workspace/20.keymgr_lc_disable/latest

Test location /workspace/coverage/default/20.keymgr_random.3310127837
Short name T558
Test name
Test status
Simulation time 599773103 ps
CPU time 11.84 seconds
Started Mar 26 03:28:59 PM PDT 24
Finished Mar 26 03:29:12 PM PDT 24
Peak memory 210076 kb
Host smart-35bf82b8-4014-4150-98a8-0bfafafada5c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3310127837 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_random.3310127837
Directory /workspace/20.keymgr_random/latest

Test location /workspace/coverage/default/20.keymgr_sideload.2144899387
Short name T552
Test name
Test status
Simulation time 155939590 ps
CPU time 2.7 seconds
Started Mar 26 03:29:02 PM PDT 24
Finished Mar 26 03:29:05 PM PDT 24
Peak memory 208856 kb
Host smart-c0e3cc72-7e37-4fcf-bfeb-5053a638f1f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144899387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload.2144899387
Directory /workspace/20.keymgr_sideload/latest

Test location /workspace/coverage/default/20.keymgr_sideload_aes.1646800022
Short name T564
Test name
Test status
Simulation time 93609910 ps
CPU time 2.3 seconds
Started Mar 26 03:29:11 PM PDT 24
Finished Mar 26 03:29:13 PM PDT 24
Peak memory 209264 kb
Host smart-38dc1d8a-58a1-42be-8a9d-938e523af724
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1646800022 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_aes.1646800022
Directory /workspace/20.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/20.keymgr_sideload_kmac.1640411468
Short name T547
Test name
Test status
Simulation time 4614842309 ps
CPU time 35.59 seconds
Started Mar 26 03:29:10 PM PDT 24
Finished Mar 26 03:29:47 PM PDT 24
Peak memory 209212 kb
Host smart-4b21a017-244d-44c1-a24b-6894682893ee
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1640411468 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_kmac.1640411468
Directory /workspace/20.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/20.keymgr_sideload_otbn.2181492016
Short name T732
Test name
Test status
Simulation time 135875773 ps
CPU time 4.12 seconds
Started Mar 26 03:29:11 PM PDT 24
Finished Mar 26 03:29:15 PM PDT 24
Peak memory 208440 kb
Host smart-a363f129-19d3-4746-86e1-be0bf0151399
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2181492016 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_otbn.2181492016
Directory /workspace/20.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/20.keymgr_sideload_protect.2410015443
Short name T332
Test name
Test status
Simulation time 63611570 ps
CPU time 2.73 seconds
Started Mar 26 03:29:05 PM PDT 24
Finished Mar 26 03:29:08 PM PDT 24
Peak memory 218536 kb
Host smart-ef122be0-b5b7-4026-bf93-be842b811db1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410015443 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sideload_protect.2410015443
Directory /workspace/20.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/20.keymgr_smoke.3481996823
Short name T527
Test name
Test status
Simulation time 73078312 ps
CPU time 3.29 seconds
Started Mar 26 03:29:10 PM PDT 24
Finished Mar 26 03:29:13 PM PDT 24
Peak memory 208280 kb
Host smart-ca797824-f376-43e6-9356-3b3e6db04702
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3481996823 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_smoke.3481996823
Directory /workspace/20.keymgr_smoke/latest

Test location /workspace/coverage/default/20.keymgr_stress_all.768127683
Short name T71
Test name
Test status
Simulation time 2381805915 ps
CPU time 73.36 seconds
Started Mar 26 03:29:06 PM PDT 24
Finished Mar 26 03:30:19 PM PDT 24
Peak memory 220604 kb
Host smart-e839378f-0224-4360-905a-e19c4b49afe3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=768127683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_stress_all.768127683
Directory /workspace/20.keymgr_stress_all/latest

Test location /workspace/coverage/default/20.keymgr_sw_invalid_input.1180259211
Short name T529
Test name
Test status
Simulation time 195366300 ps
CPU time 2.86 seconds
Started Mar 26 03:29:00 PM PDT 24
Finished Mar 26 03:29:03 PM PDT 24
Peak memory 208452 kb
Host smart-5bee80c5-975d-4b4a-97f2-f1a850cf611c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1180259211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sw_invalid_input.1180259211
Directory /workspace/20.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/20.keymgr_sync_async_fault_cross.486145346
Short name T57
Test name
Test status
Simulation time 355236936 ps
CPU time 1.93 seconds
Started Mar 26 03:29:01 PM PDT 24
Finished Mar 26 03:29:08 PM PDT 24
Peak memory 210204 kb
Host smart-d2483d23-efac-487c-9752-267481fac77b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486145346 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.keymgr_sync_async_fault_cross.486145346
Directory /workspace/20.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/21.keymgr_alert_test.2286241315
Short name T16
Test name
Test status
Simulation time 91907802 ps
CPU time 0.75 seconds
Started Mar 26 03:29:09 PM PDT 24
Finished Mar 26 03:29:10 PM PDT 24
Peak memory 206284 kb
Host smart-43ca30fc-1af3-4611-b215-5428053c817d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286241315 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_alert_test.2286241315
Directory /workspace/21.keymgr_alert_test/latest

Test location /workspace/coverage/default/21.keymgr_custom_cm.2922792225
Short name T563
Test name
Test status
Simulation time 177942571 ps
CPU time 4.58 seconds
Started Mar 26 03:29:17 PM PDT 24
Finished Mar 26 03:29:21 PM PDT 24
Peak memory 215048 kb
Host smart-02a2aba8-998a-4761-bff4-5b4d916c8473
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2922792225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_custom_cm.2922792225
Directory /workspace/21.keymgr_custom_cm/latest

Test location /workspace/coverage/default/21.keymgr_direct_to_disabled.1644055911
Short name T481
Test name
Test status
Simulation time 1164838757 ps
CPU time 6.86 seconds
Started Mar 26 03:29:01 PM PDT 24
Finished Mar 26 03:29:08 PM PDT 24
Peak memory 214644 kb
Host smart-831ec686-4f5d-4b47-8610-10ec64477fa1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1644055911 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_direct_to_disabled.1644055911
Directory /workspace/21.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/21.keymgr_hwsw_invalid_input.1631781839
Short name T26
Test name
Test status
Simulation time 217101593 ps
CPU time 2.59 seconds
Started Mar 26 03:29:30 PM PDT 24
Finished Mar 26 03:29:33 PM PDT 24
Peak memory 208716 kb
Host smart-04d4091a-7e23-4dbb-99d4-b63ff326230d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1631781839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_hwsw_invalid_input.1631781839
Directory /workspace/21.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_lc_disable.1452307847
Short name T64
Test name
Test status
Simulation time 132284441 ps
CPU time 2.37 seconds
Started Mar 26 03:28:59 PM PDT 24
Finished Mar 26 03:29:02 PM PDT 24
Peak memory 210044 kb
Host smart-c2daea08-386b-4975-a76a-04e18fa711b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1452307847 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_lc_disable.1452307847
Directory /workspace/21.keymgr_lc_disable/latest

Test location /workspace/coverage/default/21.keymgr_random.2798237620
Short name T636
Test name
Test status
Simulation time 181445422 ps
CPU time 4.61 seconds
Started Mar 26 03:29:01 PM PDT 24
Finished Mar 26 03:29:06 PM PDT 24
Peak memory 207860 kb
Host smart-049d62ec-938c-4500-9da7-43c51d5d761f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2798237620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_random.2798237620
Directory /workspace/21.keymgr_random/latest

Test location /workspace/coverage/default/21.keymgr_sideload.1313121516
Short name T799
Test name
Test status
Simulation time 195306514 ps
CPU time 2.63 seconds
Started Mar 26 03:29:01 PM PDT 24
Finished Mar 26 03:29:03 PM PDT 24
Peak memory 207292 kb
Host smart-27da2319-f36d-479e-9201-0d30e563c7dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1313121516 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload.1313121516
Directory /workspace/21.keymgr_sideload/latest

Test location /workspace/coverage/default/21.keymgr_sideload_aes.99501575
Short name T712
Test name
Test status
Simulation time 80899301 ps
CPU time 3.72 seconds
Started Mar 26 03:29:08 PM PDT 24
Finished Mar 26 03:29:17 PM PDT 24
Peak memory 209272 kb
Host smart-afdc1673-6da9-4ad9-b05f-da4aa002fa4f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99501575 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_aes.99501575
Directory /workspace/21.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/21.keymgr_sideload_kmac.1238915091
Short name T496
Test name
Test status
Simulation time 3108782235 ps
CPU time 32.24 seconds
Started Mar 26 03:29:02 PM PDT 24
Finished Mar 26 03:29:34 PM PDT 24
Peak memory 208380 kb
Host smart-7fec528c-2d18-4dfd-b7a1-de76d5b1f33f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1238915091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_kmac.1238915091
Directory /workspace/21.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/21.keymgr_sideload_otbn.2779843172
Short name T82
Test name
Test status
Simulation time 432165284 ps
CPU time 9.11 seconds
Started Mar 26 03:29:04 PM PDT 24
Finished Mar 26 03:29:13 PM PDT 24
Peak memory 208992 kb
Host smart-224db641-edab-4501-b9fc-8a8ea83d7195
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2779843172 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_otbn.2779843172
Directory /workspace/21.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/21.keymgr_sideload_protect.4018325192
Short name T274
Test name
Test status
Simulation time 150963080 ps
CPU time 3.51 seconds
Started Mar 26 03:28:59 PM PDT 24
Finished Mar 26 03:29:02 PM PDT 24
Peak memory 209992 kb
Host smart-51665e2c-3d17-499e-a63e-57292f4beb44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018325192 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sideload_protect.4018325192
Directory /workspace/21.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/21.keymgr_smoke.1358274055
Short name T691
Test name
Test status
Simulation time 381233766 ps
CPU time 2.91 seconds
Started Mar 26 03:28:55 PM PDT 24
Finished Mar 26 03:28:59 PM PDT 24
Peak memory 206916 kb
Host smart-e46dec6d-8e6f-48d2-8178-c9cca1a7b2e0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358274055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_smoke.1358274055
Directory /workspace/21.keymgr_smoke/latest

Test location /workspace/coverage/default/21.keymgr_stress_all.866453414
Short name T296
Test name
Test status
Simulation time 875413537 ps
CPU time 13.28 seconds
Started Mar 26 03:29:12 PM PDT 24
Finished Mar 26 03:29:25 PM PDT 24
Peak memory 222748 kb
Host smart-bdde4dd2-b08e-4f00-863c-45777821929a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=866453414 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all.866453414
Directory /workspace/21.keymgr_stress_all/latest

Test location /workspace/coverage/default/21.keymgr_stress_all_with_rand_reset.2465745031
Short name T898
Test name
Test status
Simulation time 879532935 ps
CPU time 16.79 seconds
Started Mar 26 03:29:05 PM PDT 24
Finished Mar 26 03:29:22 PM PDT 24
Peak memory 221636 kb
Host smart-680eb10a-da44-4b5e-bd1a-f7610e36605a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2465745031 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 21.keymgr_stress_all_with_rand_reset.2465745031
Directory /workspace/21.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.keymgr_sw_invalid_input.343025817
Short name T251
Test name
Test status
Simulation time 2855738280 ps
CPU time 31.63 seconds
Started Mar 26 03:29:10 PM PDT 24
Finished Mar 26 03:29:41 PM PDT 24
Peak memory 219012 kb
Host smart-c059a2ba-8e73-4798-b9b7-d2bb5247047c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=343025817 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sw_invalid_input.343025817
Directory /workspace/21.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/21.keymgr_sync_async_fault_cross.156030007
Short name T395
Test name
Test status
Simulation time 233529754 ps
CPU time 1.89 seconds
Started Mar 26 03:28:59 PM PDT 24
Finished Mar 26 03:29:02 PM PDT 24
Peak memory 210084 kb
Host smart-5af0de28-bba0-4d3d-aab4-b5d312f6e067
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=156030007 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.keymgr_sync_async_fault_cross.156030007
Directory /workspace/21.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/22.keymgr_alert_test.1577199556
Short name T844
Test name
Test status
Simulation time 33262795 ps
CPU time 0.76 seconds
Started Mar 26 03:29:03 PM PDT 24
Finished Mar 26 03:29:03 PM PDT 24
Peak memory 206316 kb
Host smart-6a5b8d0e-76aa-4af3-b01c-707cbb923242
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1577199556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_alert_test.1577199556
Directory /workspace/22.keymgr_alert_test/latest

Test location /workspace/coverage/default/22.keymgr_direct_to_disabled.2111915297
Short name T69
Test name
Test status
Simulation time 470814236 ps
CPU time 3.14 seconds
Started Mar 26 03:29:02 PM PDT 24
Finished Mar 26 03:29:06 PM PDT 24
Peak memory 209240 kb
Host smart-f687c204-01a9-4f3b-befd-bd249b5f75ab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2111915297 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_direct_to_disabled.2111915297
Directory /workspace/22.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/22.keymgr_kmac_rsp_err.248453100
Short name T205
Test name
Test status
Simulation time 161508264 ps
CPU time 4.25 seconds
Started Mar 26 03:29:13 PM PDT 24
Finished Mar 26 03:29:17 PM PDT 24
Peak memory 211856 kb
Host smart-5e6e723f-3a3c-4070-9294-8ea3cad9939d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=248453100 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_kmac_rsp_err.248453100
Directory /workspace/22.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/22.keymgr_lc_disable.774464990
Short name T48
Test name
Test status
Simulation time 384132293 ps
CPU time 2.4 seconds
Started Mar 26 03:29:11 PM PDT 24
Finished Mar 26 03:29:14 PM PDT 24
Peak memory 214644 kb
Host smart-cabdb89e-4817-4a5f-9ffd-349a8734d820
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=774464990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_lc_disable.774464990
Directory /workspace/22.keymgr_lc_disable/latest

Test location /workspace/coverage/default/22.keymgr_random.462761816
Short name T313
Test name
Test status
Simulation time 583047692 ps
CPU time 4.56 seconds
Started Mar 26 03:29:01 PM PDT 24
Finished Mar 26 03:29:06 PM PDT 24
Peak memory 209644 kb
Host smart-e0aae294-bafa-4518-a8e6-5a127bcf888e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462761816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_random.462761816
Directory /workspace/22.keymgr_random/latest

Test location /workspace/coverage/default/22.keymgr_sideload.1421208002
Short name T442
Test name
Test status
Simulation time 442115631 ps
CPU time 5.49 seconds
Started Mar 26 03:29:09 PM PDT 24
Finished Mar 26 03:29:15 PM PDT 24
Peak memory 208176 kb
Host smart-5c8ceeb2-6ce2-4b8e-945e-d1742f9ac669
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421208002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload.1421208002
Directory /workspace/22.keymgr_sideload/latest

Test location /workspace/coverage/default/22.keymgr_sideload_aes.1605990960
Short name T719
Test name
Test status
Simulation time 1033978532 ps
CPU time 5.4 seconds
Started Mar 26 03:29:06 PM PDT 24
Finished Mar 26 03:29:12 PM PDT 24
Peak memory 208760 kb
Host smart-985563f9-6932-4ff2-9b1a-73e6fd121445
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605990960 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_aes.1605990960
Directory /workspace/22.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/22.keymgr_sideload_kmac.1994058789
Short name T275
Test name
Test status
Simulation time 95613082 ps
CPU time 2.49 seconds
Started Mar 26 03:29:09 PM PDT 24
Finished Mar 26 03:29:12 PM PDT 24
Peak memory 208940 kb
Host smart-cac4a26b-3fe4-4ce0-a58d-9800860cc170
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1994058789 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_kmac.1994058789
Directory /workspace/22.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/22.keymgr_sideload_otbn.4260875221
Short name T808
Test name
Test status
Simulation time 80478409 ps
CPU time 3.16 seconds
Started Mar 26 03:29:00 PM PDT 24
Finished Mar 26 03:29:04 PM PDT 24
Peak memory 207144 kb
Host smart-0b9d0465-69f3-4b28-bc3b-a72ff3aa56d1
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4260875221 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_otbn.4260875221
Directory /workspace/22.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/22.keymgr_sideload_protect.905701071
Short name T831
Test name
Test status
Simulation time 155296137 ps
CPU time 5.15 seconds
Started Mar 26 03:29:07 PM PDT 24
Finished Mar 26 03:29:12 PM PDT 24
Peak memory 209704 kb
Host smart-209513cb-09e0-43aa-a0e8-e2956b771545
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=905701071 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sideload_protect.905701071
Directory /workspace/22.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/22.keymgr_smoke.1877642721
Short name T789
Test name
Test status
Simulation time 182648734 ps
CPU time 3.15 seconds
Started Mar 26 03:29:01 PM PDT 24
Finished Mar 26 03:29:05 PM PDT 24
Peak memory 208832 kb
Host smart-93801998-b699-408b-83db-591796b7d584
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877642721 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_smoke.1877642721
Directory /workspace/22.keymgr_smoke/latest

Test location /workspace/coverage/default/22.keymgr_stress_all.3101705331
Short name T859
Test name
Test status
Simulation time 559273736 ps
CPU time 29.56 seconds
Started Mar 26 03:29:07 PM PDT 24
Finished Mar 26 03:29:37 PM PDT 24
Peak memory 216540 kb
Host smart-0b2c96fb-fe24-4b49-83be-eeef8880d10a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3101705331 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all.3101705331
Directory /workspace/22.keymgr_stress_all/latest

Test location /workspace/coverage/default/22.keymgr_stress_all_with_rand_reset.150783531
Short name T911
Test name
Test status
Simulation time 602780939 ps
CPU time 8.12 seconds
Started Mar 26 03:29:10 PM PDT 24
Finished Mar 26 03:29:19 PM PDT 24
Peak memory 221164 kb
Host smart-5982bb19-fa75-4df6-9787-a7c0966ee4a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=150783531 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 22.keymgr_stress_all_with_rand_reset.150783531
Directory /workspace/22.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.keymgr_sw_invalid_input.2762329655
Short name T544
Test name
Test status
Simulation time 177302641 ps
CPU time 3.52 seconds
Started Mar 26 03:28:56 PM PDT 24
Finished Mar 26 03:29:00 PM PDT 24
Peak memory 209288 kb
Host smart-86a11248-d410-4f33-a524-c60cf10417ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2762329655 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sw_invalid_input.2762329655
Directory /workspace/22.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/22.keymgr_sync_async_fault_cross.3799124225
Short name T893
Test name
Test status
Simulation time 74487426 ps
CPU time 3.29 seconds
Started Mar 26 03:29:22 PM PDT 24
Finished Mar 26 03:29:25 PM PDT 24
Peak memory 210492 kb
Host smart-2a3228cb-3cc2-471f-b55c-e29c41a2ae2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799124225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.keymgr_sync_async_fault_cross.3799124225
Directory /workspace/22.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/23.keymgr_alert_test.1288638427
Short name T432
Test name
Test status
Simulation time 16686180 ps
CPU time 0.85 seconds
Started Mar 26 03:29:04 PM PDT 24
Finished Mar 26 03:29:05 PM PDT 24
Peak memory 206300 kb
Host smart-53e8db84-a6f4-4bc0-86b8-4ec1ad6b0349
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288638427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_alert_test.1288638427
Directory /workspace/23.keymgr_alert_test/latest

Test location /workspace/coverage/default/23.keymgr_cfg_regwen.4114250967
Short name T424
Test name
Test status
Simulation time 212799740 ps
CPU time 5.91 seconds
Started Mar 26 03:29:10 PM PDT 24
Finished Mar 26 03:29:16 PM PDT 24
Peak memory 214692 kb
Host smart-24b6885d-7d88-4504-825d-09bd4cdae491
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=4114250967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_cfg_regwen.4114250967
Directory /workspace/23.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/23.keymgr_custom_cm.3292571263
Short name T29
Test name
Test status
Simulation time 508006178 ps
CPU time 8.57 seconds
Started Mar 26 03:28:58 PM PDT 24
Finished Mar 26 03:29:06 PM PDT 24
Peak memory 222172 kb
Host smart-dbb08274-8921-428c-ab27-4604e648f23e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3292571263 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_custom_cm.3292571263
Directory /workspace/23.keymgr_custom_cm/latest

Test location /workspace/coverage/default/23.keymgr_direct_to_disabled.4138006465
Short name T73
Test name
Test status
Simulation time 350522059 ps
CPU time 3.89 seconds
Started Mar 26 03:29:24 PM PDT 24
Finished Mar 26 03:29:28 PM PDT 24
Peak memory 210480 kb
Host smart-4cda72b8-99b6-49db-98e6-806e97485f45
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138006465 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_direct_to_disabled.4138006465
Directory /workspace/23.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/23.keymgr_hwsw_invalid_input.4245488232
Short name T305
Test name
Test status
Simulation time 38602858 ps
CPU time 2.73 seconds
Started Mar 26 03:29:20 PM PDT 24
Finished Mar 26 03:29:23 PM PDT 24
Peak memory 214684 kb
Host smart-3f4c9fd4-fd9a-4e98-8d39-ab9cd3ed8e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245488232 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_hwsw_invalid_input.4245488232
Directory /workspace/23.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_lc_disable.2877675201
Short name T142
Test name
Test status
Simulation time 190239277 ps
CPU time 4.07 seconds
Started Mar 26 03:29:03 PM PDT 24
Finished Mar 26 03:29:08 PM PDT 24
Peak memory 209644 kb
Host smart-57ceb9df-17b4-42a2-b11c-3eef097cce5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2877675201 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_lc_disable.2877675201
Directory /workspace/23.keymgr_lc_disable/latest

Test location /workspace/coverage/default/23.keymgr_random.1310947956
Short name T535
Test name
Test status
Simulation time 164582177 ps
CPU time 3 seconds
Started Mar 26 03:29:10 PM PDT 24
Finished Mar 26 03:29:13 PM PDT 24
Peak memory 209980 kb
Host smart-c236046f-22e1-4dfa-ae4c-6c945a07429e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310947956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_random.1310947956
Directory /workspace/23.keymgr_random/latest

Test location /workspace/coverage/default/23.keymgr_sideload.3911863299
Short name T272
Test name
Test status
Simulation time 119663727 ps
CPU time 3.09 seconds
Started Mar 26 03:29:08 PM PDT 24
Finished Mar 26 03:29:12 PM PDT 24
Peak memory 207160 kb
Host smart-62e393e2-a605-430a-b5f9-642fc360fd6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3911863299 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload.3911863299
Directory /workspace/23.keymgr_sideload/latest

Test location /workspace/coverage/default/23.keymgr_sideload_kmac.1304310456
Short name T797
Test name
Test status
Simulation time 24857350 ps
CPU time 2.15 seconds
Started Mar 26 03:29:11 PM PDT 24
Finished Mar 26 03:29:13 PM PDT 24
Peak memory 209060 kb
Host smart-b86e0fcc-0e10-419a-99a5-bb873b93f107
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1304310456 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_kmac.1304310456
Directory /workspace/23.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/23.keymgr_sideload_otbn.2935217181
Short name T399
Test name
Test status
Simulation time 168870662 ps
CPU time 4.97 seconds
Started Mar 26 03:29:18 PM PDT 24
Finished Mar 26 03:29:23 PM PDT 24
Peak memory 208024 kb
Host smart-a4efd8d5-4da9-4b05-8835-f6b3c4d80094
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2935217181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_otbn.2935217181
Directory /workspace/23.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/23.keymgr_sideload_protect.660642021
Short name T458
Test name
Test status
Simulation time 482505488 ps
CPU time 11.45 seconds
Started Mar 26 03:29:11 PM PDT 24
Finished Mar 26 03:29:23 PM PDT 24
Peak memory 220748 kb
Host smart-698e9e65-033f-4f64-9973-bfb8a709be44
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=660642021 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sideload_protect.660642021
Directory /workspace/23.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/23.keymgr_smoke.2353291835
Short name T501
Test name
Test status
Simulation time 396018307 ps
CPU time 2.66 seconds
Started Mar 26 03:29:07 PM PDT 24
Finished Mar 26 03:29:10 PM PDT 24
Peak memory 208620 kb
Host smart-7235f571-0d46-4f1f-933e-3a8d10188f7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2353291835 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_smoke.2353291835
Directory /workspace/23.keymgr_smoke/latest

Test location /workspace/coverage/default/23.keymgr_stress_all.728570651
Short name T65
Test name
Test status
Simulation time 413013660 ps
CPU time 9.13 seconds
Started Mar 26 03:29:18 PM PDT 24
Finished Mar 26 03:29:28 PM PDT 24
Peak memory 220416 kb
Host smart-4aff077d-edd1-49c7-bcb7-ff14c083b15a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728570651 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_stress_all.728570651
Directory /workspace/23.keymgr_stress_all/latest

Test location /workspace/coverage/default/23.keymgr_sw_invalid_input.1673209196
Short name T635
Test name
Test status
Simulation time 541607823 ps
CPU time 5.78 seconds
Started Mar 26 03:29:01 PM PDT 24
Finished Mar 26 03:29:07 PM PDT 24
Peak memory 214644 kb
Host smart-ebb82f90-359d-4f12-bed2-85f251d0da6a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1673209196 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sw_invalid_input.1673209196
Directory /workspace/23.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/23.keymgr_sync_async_fault_cross.306412494
Short name T616
Test name
Test status
Simulation time 59840414 ps
CPU time 2 seconds
Started Mar 26 03:29:19 PM PDT 24
Finished Mar 26 03:29:21 PM PDT 24
Peak memory 210212 kb
Host smart-3c4bcf19-6546-4168-9c35-60cc6d8c8e43
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=306412494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.keymgr_sync_async_fault_cross.306412494
Directory /workspace/23.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/24.keymgr_alert_test.119441937
Short name T650
Test name
Test status
Simulation time 9724146 ps
CPU time 0.84 seconds
Started Mar 26 03:29:04 PM PDT 24
Finished Mar 26 03:29:05 PM PDT 24
Peak memory 206312 kb
Host smart-c3f3e2bb-476f-4af8-8bd2-a7da78f231f1
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119441937 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_alert_test.119441937
Directory /workspace/24.keymgr_alert_test/latest

Test location /workspace/coverage/default/24.keymgr_custom_cm.663121271
Short name T21
Test name
Test status
Simulation time 80569592 ps
CPU time 3.66 seconds
Started Mar 26 03:29:05 PM PDT 24
Finished Mar 26 03:29:08 PM PDT 24
Peak memory 217532 kb
Host smart-55a26d4b-b15a-4f71-8344-c2dce45eae7a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663121271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_custom_cm.663121271
Directory /workspace/24.keymgr_custom_cm/latest

Test location /workspace/coverage/default/24.keymgr_direct_to_disabled.1243587373
Short name T638
Test name
Test status
Simulation time 17705932 ps
CPU time 1.48 seconds
Started Mar 26 03:28:56 PM PDT 24
Finished Mar 26 03:28:58 PM PDT 24
Peak memory 207504 kb
Host smart-9a8590bd-5f7a-44ef-ba47-d8d306a0d08f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1243587373 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_direct_to_disabled.1243587373
Directory /workspace/24.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/24.keymgr_kmac_rsp_err.1619422029
Short name T337
Test name
Test status
Simulation time 487502002 ps
CPU time 8.16 seconds
Started Mar 26 03:29:01 PM PDT 24
Finished Mar 26 03:29:09 PM PDT 24
Peak memory 211836 kb
Host smart-b94e0518-f6b7-4dc0-9416-ee1b87e5704b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619422029 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_kmac_rsp_err.1619422029
Directory /workspace/24.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/24.keymgr_lc_disable.128264231
Short name T758
Test name
Test status
Simulation time 98617133 ps
CPU time 3.68 seconds
Started Mar 26 03:29:12 PM PDT 24
Finished Mar 26 03:29:15 PM PDT 24
Peak memory 210008 kb
Host smart-3ff93d0b-65cf-4255-b5cf-3be96cbbce2f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=128264231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_lc_disable.128264231
Directory /workspace/24.keymgr_lc_disable/latest

Test location /workspace/coverage/default/24.keymgr_random.954656069
Short name T813
Test name
Test status
Simulation time 411636231 ps
CPU time 2.69 seconds
Started Mar 26 03:29:06 PM PDT 24
Finished Mar 26 03:29:08 PM PDT 24
Peak memory 208552 kb
Host smart-1bf078dd-339d-4373-94b0-f81ce5289753
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=954656069 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_random.954656069
Directory /workspace/24.keymgr_random/latest

Test location /workspace/coverage/default/24.keymgr_sideload.782021002
Short name T626
Test name
Test status
Simulation time 113236807 ps
CPU time 4.99 seconds
Started Mar 26 03:28:56 PM PDT 24
Finished Mar 26 03:29:02 PM PDT 24
Peak memory 209036 kb
Host smart-f5f2f492-fedc-440b-b0e5-4576e8107e71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782021002 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload.782021002
Directory /workspace/24.keymgr_sideload/latest

Test location /workspace/coverage/default/24.keymgr_sideload_aes.790254454
Short name T469
Test name
Test status
Simulation time 57501910 ps
CPU time 2.95 seconds
Started Mar 26 03:29:03 PM PDT 24
Finished Mar 26 03:29:11 PM PDT 24
Peak memory 208952 kb
Host smart-d6939ff1-5b3c-4252-877e-c173645aabd3
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790254454 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_aes.790254454
Directory /workspace/24.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/24.keymgr_sideload_kmac.1129787666
Short name T437
Test name
Test status
Simulation time 270171169 ps
CPU time 3.91 seconds
Started Mar 26 03:29:11 PM PDT 24
Finished Mar 26 03:29:15 PM PDT 24
Peak memory 208756 kb
Host smart-a7a82df2-a408-4c1c-b33c-d7a223f1d6d9
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1129787666 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_kmac.1129787666
Directory /workspace/24.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/24.keymgr_sideload_otbn.88548500
Short name T354
Test name
Test status
Simulation time 71124228 ps
CPU time 3.5 seconds
Started Mar 26 03:29:10 PM PDT 24
Finished Mar 26 03:29:15 PM PDT 24
Peak memory 208300 kb
Host smart-8680c3c6-48c9-45b9-918c-9951b11a5140
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88548500 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_otbn.88548500
Directory /workspace/24.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/24.keymgr_sideload_protect.1799139825
Short name T747
Test name
Test status
Simulation time 247223316 ps
CPU time 2.47 seconds
Started Mar 26 03:29:05 PM PDT 24
Finished Mar 26 03:29:07 PM PDT 24
Peak memory 209736 kb
Host smart-61b6f69d-ff9f-42c2-886d-560e3ee9f638
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799139825 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sideload_protect.1799139825
Directory /workspace/24.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/24.keymgr_smoke.1771779377
Short name T465
Test name
Test status
Simulation time 475389169 ps
CPU time 12.87 seconds
Started Mar 26 03:29:02 PM PDT 24
Finished Mar 26 03:29:14 PM PDT 24
Peak memory 208896 kb
Host smart-fb6b3ea0-e2d4-4faa-b3ec-e80b17ddecb1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771779377 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_smoke.1771779377
Directory /workspace/24.keymgr_smoke/latest

Test location /workspace/coverage/default/24.keymgr_stress_all_with_rand_reset.699058537
Short name T675
Test name
Test status
Simulation time 502719244 ps
CPU time 15.69 seconds
Started Mar 26 03:29:06 PM PDT 24
Finished Mar 26 03:29:22 PM PDT 24
Peak memory 221940 kb
Host smart-68970be4-6779-4f74-9d2b-8b29da2d5e08
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=699058537 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 24.keymgr_stress_all_with_rand_reset.699058537
Directory /workspace/24.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.keymgr_sw_invalid_input.1725971009
Short name T168
Test name
Test status
Simulation time 229377974 ps
CPU time 3.99 seconds
Started Mar 26 03:29:10 PM PDT 24
Finished Mar 26 03:29:14 PM PDT 24
Peak memory 209712 kb
Host smart-a9e7aee1-1bae-4fd3-b646-8ea5e4b3d713
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725971009 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sw_invalid_input.1725971009
Directory /workspace/24.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/24.keymgr_sync_async_fault_cross.3205162398
Short name T185
Test name
Test status
Simulation time 294637782 ps
CPU time 2.79 seconds
Started Mar 26 03:29:12 PM PDT 24
Finished Mar 26 03:29:15 PM PDT 24
Peak memory 210240 kb
Host smart-a604be28-d64f-4a6e-b8c6-0b2775e1bc56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3205162398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.keymgr_sync_async_fault_cross.3205162398
Directory /workspace/24.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/25.keymgr_alert_test.3240130226
Short name T100
Test name
Test status
Simulation time 9827974 ps
CPU time 0.74 seconds
Started Mar 26 03:29:32 PM PDT 24
Finished Mar 26 03:29:33 PM PDT 24
Peak memory 206284 kb
Host smart-33f8a5ba-fab0-470c-9d83-9e29e1c3632a
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240130226 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_alert_test.3240130226
Directory /workspace/25.keymgr_alert_test/latest

Test location /workspace/coverage/default/25.keymgr_cfg_regwen.3569360980
Short name T310
Test name
Test status
Simulation time 582900620 ps
CPU time 8.71 seconds
Started Mar 26 03:29:19 PM PDT 24
Finished Mar 26 03:29:27 PM PDT 24
Peak memory 215564 kb
Host smart-9156218a-067e-4322-ae4c-5ad8f21c1461
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3569360980 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_cfg_regwen.3569360980
Directory /workspace/25.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/25.keymgr_custom_cm.3228679055
Short name T587
Test name
Test status
Simulation time 122501390 ps
CPU time 2.8 seconds
Started Mar 26 03:29:21 PM PDT 24
Finished Mar 26 03:29:24 PM PDT 24
Peak memory 209184 kb
Host smart-eeebad3c-ad47-49e6-a1b8-fe1941c04bbb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228679055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_custom_cm.3228679055
Directory /workspace/25.keymgr_custom_cm/latest

Test location /workspace/coverage/default/25.keymgr_direct_to_disabled.1596876681
Short name T881
Test name
Test status
Simulation time 206531023 ps
CPU time 3.51 seconds
Started Mar 26 03:29:11 PM PDT 24
Finished Mar 26 03:29:15 PM PDT 24
Peak memory 208492 kb
Host smart-cfdc59d3-9f8c-4e4d-a0e6-d7af2b539439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1596876681 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_direct_to_disabled.1596876681
Directory /workspace/25.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/25.keymgr_hwsw_invalid_input.501650246
Short name T24
Test name
Test status
Simulation time 8500965482 ps
CPU time 56.75 seconds
Started Mar 26 03:29:03 PM PDT 24
Finished Mar 26 03:30:00 PM PDT 24
Peak memory 214784 kb
Host smart-20ad036f-94d2-4376-8b87-66935bac0439
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=501650246 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_hwsw_invalid_input.501650246
Directory /workspace/25.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_kmac_rsp_err.4194680025
Short name T377
Test name
Test status
Simulation time 199697651 ps
CPU time 3.7 seconds
Started Mar 26 03:29:08 PM PDT 24
Finished Mar 26 03:29:12 PM PDT 24
Peak memory 221468 kb
Host smart-3d911e36-6ec2-46b1-a7f3-ca327dd08d36
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4194680025 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_kmac_rsp_err.4194680025
Directory /workspace/25.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/25.keymgr_lc_disable.3635970812
Short name T671
Test name
Test status
Simulation time 2257363185 ps
CPU time 12.11 seconds
Started Mar 26 03:29:11 PM PDT 24
Finished Mar 26 03:29:24 PM PDT 24
Peak memory 218896 kb
Host smart-1d7b1496-72c2-42e7-ad84-efe08ce281d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635970812 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_lc_disable.3635970812
Directory /workspace/25.keymgr_lc_disable/latest

Test location /workspace/coverage/default/25.keymgr_random.563112845
Short name T416
Test name
Test status
Simulation time 653740389 ps
CPU time 7.23 seconds
Started Mar 26 03:29:21 PM PDT 24
Finished Mar 26 03:29:28 PM PDT 24
Peak memory 209556 kb
Host smart-65453e81-bed3-4f14-a8a9-62930171e897
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=563112845 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_random.563112845
Directory /workspace/25.keymgr_random/latest

Test location /workspace/coverage/default/25.keymgr_sideload.1612246761
Short name T776
Test name
Test status
Simulation time 3131043357 ps
CPU time 21.64 seconds
Started Mar 26 03:29:30 PM PDT 24
Finished Mar 26 03:29:51 PM PDT 24
Peak memory 208644 kb
Host smart-ed5d36be-0e56-44c2-b7fe-2e859a54ffce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1612246761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload.1612246761
Directory /workspace/25.keymgr_sideload/latest

Test location /workspace/coverage/default/25.keymgr_sideload_aes.1492113739
Short name T546
Test name
Test status
Simulation time 44091884 ps
CPU time 2.52 seconds
Started Mar 26 03:28:59 PM PDT 24
Finished Mar 26 03:29:01 PM PDT 24
Peak memory 208196 kb
Host smart-5497c612-2890-472a-ad3a-e62a08f034e9
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1492113739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_aes.1492113739
Directory /workspace/25.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/25.keymgr_sideload_kmac.3957943189
Short name T848
Test name
Test status
Simulation time 453684834 ps
CPU time 5.48 seconds
Started Mar 26 03:29:10 PM PDT 24
Finished Mar 26 03:29:15 PM PDT 24
Peak memory 208872 kb
Host smart-6bcc0877-9d3a-4101-b45e-2ef9ee8b0970
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3957943189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_kmac.3957943189
Directory /workspace/25.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/25.keymgr_sideload_otbn.1849582905
Short name T549
Test name
Test status
Simulation time 83947664 ps
CPU time 3.2 seconds
Started Mar 26 03:29:12 PM PDT 24
Finished Mar 26 03:29:15 PM PDT 24
Peak memory 207136 kb
Host smart-8a344521-5d8a-4923-9095-7e845a8253a0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1849582905 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_otbn.1849582905
Directory /workspace/25.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/25.keymgr_sideload_protect.620115184
Short name T877
Test name
Test status
Simulation time 1782649962 ps
CPU time 8.11 seconds
Started Mar 26 03:29:25 PM PDT 24
Finished Mar 26 03:29:34 PM PDT 24
Peak memory 209324 kb
Host smart-c305755f-cb59-4340-9ac9-ef097e676df7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=620115184 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sideload_protect.620115184
Directory /workspace/25.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/25.keymgr_smoke.1337507475
Short name T775
Test name
Test status
Simulation time 110515671 ps
CPU time 3.71 seconds
Started Mar 26 03:29:12 PM PDT 24
Finished Mar 26 03:29:16 PM PDT 24
Peak memory 208656 kb
Host smart-27b85711-fd40-4a84-ad01-4eef23065725
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1337507475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_smoke.1337507475
Directory /workspace/25.keymgr_smoke/latest

Test location /workspace/coverage/default/25.keymgr_stress_all.1936759761
Short name T174
Test name
Test status
Simulation time 1716278122 ps
CPU time 45.07 seconds
Started Mar 26 03:29:14 PM PDT 24
Finished Mar 26 03:30:00 PM PDT 24
Peak memory 222876 kb
Host smart-655b2752-5ce9-4a5e-a52f-80826d205112
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1936759761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_stress_all.1936759761
Directory /workspace/25.keymgr_stress_all/latest

Test location /workspace/coverage/default/25.keymgr_sw_invalid_input.2321678527
Short name T334
Test name
Test status
Simulation time 665110052 ps
CPU time 8.12 seconds
Started Mar 26 03:29:11 PM PDT 24
Finished Mar 26 03:29:19 PM PDT 24
Peak memory 209708 kb
Host smart-d4172b24-0916-4a4c-9fd6-cf35b8d11894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321678527 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sw_invalid_input.2321678527
Directory /workspace/25.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/25.keymgr_sync_async_fault_cross.1149377448
Short name T830
Test name
Test status
Simulation time 125075105 ps
CPU time 1.84 seconds
Started Mar 26 03:29:20 PM PDT 24
Finished Mar 26 03:29:22 PM PDT 24
Peak memory 210376 kb
Host smart-ce393137-a7a7-46bd-9bac-68b872f8215d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149377448 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.keymgr_sync_async_fault_cross.1149377448
Directory /workspace/25.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/26.keymgr_alert_test.1590497620
Short name T448
Test name
Test status
Simulation time 52859326 ps
CPU time 0.77 seconds
Started Mar 26 03:29:02 PM PDT 24
Finished Mar 26 03:29:03 PM PDT 24
Peak memory 206328 kb
Host smart-5e3929bb-67a4-4b36-921b-8c25ad3e7e42
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1590497620 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_alert_test.1590497620
Directory /workspace/26.keymgr_alert_test/latest

Test location /workspace/coverage/default/26.keymgr_cfg_regwen.2276207125
Short name T684
Test name
Test status
Simulation time 273122806 ps
CPU time 3.2 seconds
Started Mar 26 03:29:00 PM PDT 24
Finished Mar 26 03:29:04 PM PDT 24
Peak memory 214888 kb
Host smart-73fb3121-1574-4e52-8f91-f92b3b5ccc40
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2276207125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_cfg_regwen.2276207125
Directory /workspace/26.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/26.keymgr_custom_cm.4270210809
Short name T225
Test name
Test status
Simulation time 7418188764 ps
CPU time 40.54 seconds
Started Mar 26 03:29:18 PM PDT 24
Finished Mar 26 03:29:59 PM PDT 24
Peak memory 219684 kb
Host smart-7fc34489-faa1-473f-ad99-64109f815751
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4270210809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_custom_cm.4270210809
Directory /workspace/26.keymgr_custom_cm/latest

Test location /workspace/coverage/default/26.keymgr_direct_to_disabled.3792620548
Short name T322
Test name
Test status
Simulation time 103424441 ps
CPU time 3.22 seconds
Started Mar 26 03:28:59 PM PDT 24
Finished Mar 26 03:29:03 PM PDT 24
Peak memory 209996 kb
Host smart-afe6be21-3306-416e-a13f-f404722690b1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3792620548 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_direct_to_disabled.3792620548
Directory /workspace/26.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/26.keymgr_hwsw_invalid_input.2751044121
Short name T655
Test name
Test status
Simulation time 16172282209 ps
CPU time 81.58 seconds
Started Mar 26 03:29:12 PM PDT 24
Finished Mar 26 03:30:33 PM PDT 24
Peak memory 219572 kb
Host smart-e67c6dc1-a83b-4393-be4b-cd03de81e612
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2751044121 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_hwsw_invalid_input.2751044121
Directory /workspace/26.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_kmac_rsp_err.3462705869
Short name T297
Test name
Test status
Simulation time 576233138 ps
CPU time 8.43 seconds
Started Mar 26 03:29:26 PM PDT 24
Finished Mar 26 03:29:35 PM PDT 24
Peak memory 212100 kb
Host smart-910decf9-972a-4c76-92fb-6c5b7f6db05a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3462705869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_kmac_rsp_err.3462705869
Directory /workspace/26.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/26.keymgr_lc_disable.4056236861
Short name T221
Test name
Test status
Simulation time 492953391 ps
CPU time 3.68 seconds
Started Mar 26 03:29:14 PM PDT 24
Finished Mar 26 03:29:18 PM PDT 24
Peak memory 221012 kb
Host smart-b9b12196-e5b8-4004-9d15-743a9e543e9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056236861 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_lc_disable.4056236861
Directory /workspace/26.keymgr_lc_disable/latest

Test location /workspace/coverage/default/26.keymgr_random.2125270699
Short name T899
Test name
Test status
Simulation time 114947733 ps
CPU time 2.27 seconds
Started Mar 26 03:29:10 PM PDT 24
Finished Mar 26 03:29:12 PM PDT 24
Peak memory 207900 kb
Host smart-07ac7f32-2c0f-4063-b6b3-d25768c2a23d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2125270699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_random.2125270699
Directory /workspace/26.keymgr_random/latest

Test location /workspace/coverage/default/26.keymgr_sideload.582124992
Short name T502
Test name
Test status
Simulation time 933093698 ps
CPU time 7.61 seconds
Started Mar 26 03:29:10 PM PDT 24
Finished Mar 26 03:29:18 PM PDT 24
Peak memory 208264 kb
Host smart-c15c10d5-b8c5-4037-9024-95e7aed8e1b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582124992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload.582124992
Directory /workspace/26.keymgr_sideload/latest

Test location /workspace/coverage/default/26.keymgr_sideload_aes.2780113349
Short name T846
Test name
Test status
Simulation time 991742430 ps
CPU time 4.42 seconds
Started Mar 26 03:29:11 PM PDT 24
Finished Mar 26 03:29:16 PM PDT 24
Peak memory 208968 kb
Host smart-1850a60d-c0af-48f7-85ec-4f1f1abc3def
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780113349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_aes.2780113349
Directory /workspace/26.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/26.keymgr_sideload_kmac.4274919036
Short name T524
Test name
Test status
Simulation time 67372392 ps
CPU time 2.72 seconds
Started Mar 26 03:29:00 PM PDT 24
Finished Mar 26 03:29:03 PM PDT 24
Peak memory 207148 kb
Host smart-b044ed96-564a-493c-ab11-adf907ccd3ff
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4274919036 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_kmac.4274919036
Directory /workspace/26.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/26.keymgr_sideload_otbn.1040842248
Short name T736
Test name
Test status
Simulation time 119750770 ps
CPU time 2.73 seconds
Started Mar 26 03:29:32 PM PDT 24
Finished Mar 26 03:29:34 PM PDT 24
Peak memory 209068 kb
Host smart-ffd40093-620f-4d07-bbb9-13d555ec394e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040842248 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_otbn.1040842248
Directory /workspace/26.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/26.keymgr_sideload_protect.3999866431
Short name T592
Test name
Test status
Simulation time 526963295 ps
CPU time 2.92 seconds
Started Mar 26 03:29:16 PM PDT 24
Finished Mar 26 03:29:19 PM PDT 24
Peak memory 208656 kb
Host smart-ce0bca5e-5954-4df1-b202-e63edc409e1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3999866431 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sideload_protect.3999866431
Directory /workspace/26.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/26.keymgr_smoke.120456804
Short name T515
Test name
Test status
Simulation time 265125595 ps
CPU time 3.16 seconds
Started Mar 26 03:29:22 PM PDT 24
Finished Mar 26 03:29:25 PM PDT 24
Peak memory 208820 kb
Host smart-61115ed7-9120-4d7b-95ad-d6aef130265b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=120456804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_smoke.120456804
Directory /workspace/26.keymgr_smoke/latest

Test location /workspace/coverage/default/26.keymgr_stress_all.1554467992
Short name T244
Test name
Test status
Simulation time 230174421 ps
CPU time 12.6 seconds
Started Mar 26 03:29:25 PM PDT 24
Finished Mar 26 03:29:38 PM PDT 24
Peak memory 221444 kb
Host smart-ac961034-d976-4cec-88a3-29fac24a1474
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1554467992 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_stress_all.1554467992
Directory /workspace/26.keymgr_stress_all/latest

Test location /workspace/coverage/default/26.keymgr_sw_invalid_input.3561022939
Short name T753
Test name
Test status
Simulation time 112485099 ps
CPU time 3.17 seconds
Started Mar 26 03:29:13 PM PDT 24
Finished Mar 26 03:29:16 PM PDT 24
Peak memory 207744 kb
Host smart-225f6f4d-2900-4fba-8fd5-3fd4c148015b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561022939 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sw_invalid_input.3561022939
Directory /workspace/26.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/26.keymgr_sync_async_fault_cross.1678785822
Short name T679
Test name
Test status
Simulation time 50639674 ps
CPU time 2.14 seconds
Started Mar 26 03:29:29 PM PDT 24
Finished Mar 26 03:29:32 PM PDT 24
Peak memory 209832 kb
Host smart-c6cceff0-b0ae-4db9-9c5a-c12269a49dcc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1678785822 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.keymgr_sync_async_fault_cross.1678785822
Directory /workspace/26.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/27.keymgr_alert_test.3659933903
Short name T492
Test name
Test status
Simulation time 23713878 ps
CPU time 0.86 seconds
Started Mar 26 03:29:23 PM PDT 24
Finished Mar 26 03:29:24 PM PDT 24
Peak memory 206276 kb
Host smart-84837ab4-2767-4c69-b781-75298d7243cd
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3659933903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_alert_test.3659933903
Directory /workspace/27.keymgr_alert_test/latest

Test location /workspace/coverage/default/27.keymgr_custom_cm.1317677495
Short name T231
Test name
Test status
Simulation time 649257486 ps
CPU time 6.77 seconds
Started Mar 26 03:29:02 PM PDT 24
Finished Mar 26 03:29:09 PM PDT 24
Peak memory 211264 kb
Host smart-3dbce92e-0143-42e0-a371-95763bef47d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317677495 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_custom_cm.1317677495
Directory /workspace/27.keymgr_custom_cm/latest

Test location /workspace/coverage/default/27.keymgr_direct_to_disabled.354811902
Short name T51
Test name
Test status
Simulation time 399277843 ps
CPU time 11.03 seconds
Started Mar 26 03:29:09 PM PDT 24
Finished Mar 26 03:29:20 PM PDT 24
Peak memory 214772 kb
Host smart-c9870dfa-47d4-4e4b-a635-c3f86460c188
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354811902 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_direct_to_disabled.354811902
Directory /workspace/27.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/27.keymgr_hwsw_invalid_input.2819239293
Short name T609
Test name
Test status
Simulation time 31544153 ps
CPU time 2.24 seconds
Started Mar 26 03:29:10 PM PDT 24
Finished Mar 26 03:29:13 PM PDT 24
Peak memory 210068 kb
Host smart-2ef79ab8-4426-4418-88d3-8d4e6832a8d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2819239293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_hwsw_invalid_input.2819239293
Directory /workspace/27.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_lc_disable.4123610747
Short name T230
Test name
Test status
Simulation time 681245595 ps
CPU time 7.75 seconds
Started Mar 26 03:29:20 PM PDT 24
Finished Mar 26 03:29:28 PM PDT 24
Peak memory 222828 kb
Host smart-8c61e428-625e-425d-8f71-83be32329ffc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4123610747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_lc_disable.4123610747
Directory /workspace/27.keymgr_lc_disable/latest

Test location /workspace/coverage/default/27.keymgr_random.1581999385
Short name T604
Test name
Test status
Simulation time 1007432147 ps
CPU time 5.15 seconds
Started Mar 26 03:29:11 PM PDT 24
Finished Mar 26 03:29:21 PM PDT 24
Peak memory 214600 kb
Host smart-aae9e9c6-6266-4aec-8573-1fe8bc47c9d7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1581999385 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_random.1581999385
Directory /workspace/27.keymgr_random/latest

Test location /workspace/coverage/default/27.keymgr_sideload.1598911578
Short name T748
Test name
Test status
Simulation time 701748541 ps
CPU time 3.69 seconds
Started Mar 26 03:29:09 PM PDT 24
Finished Mar 26 03:29:13 PM PDT 24
Peak memory 206968 kb
Host smart-85356126-2d4f-4344-89cb-0f11e8737a5e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1598911578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload.1598911578
Directory /workspace/27.keymgr_sideload/latest

Test location /workspace/coverage/default/27.keymgr_sideload_aes.3725552703
Short name T553
Test name
Test status
Simulation time 172183039 ps
CPU time 2.65 seconds
Started Mar 26 03:29:11 PM PDT 24
Finished Mar 26 03:29:14 PM PDT 24
Peak memory 207720 kb
Host smart-49fb974b-7e35-44be-b4d2-e5fd4d9f7040
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3725552703 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_aes.3725552703
Directory /workspace/27.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/27.keymgr_sideload_kmac.2104194462
Short name T543
Test name
Test status
Simulation time 195606565 ps
CPU time 2.92 seconds
Started Mar 26 03:29:14 PM PDT 24
Finished Mar 26 03:29:17 PM PDT 24
Peak memory 208804 kb
Host smart-625a1879-f50e-4fd1-b196-10dbc5e7d11f
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2104194462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_kmac.2104194462
Directory /workspace/27.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/27.keymgr_sideload_otbn.4067353282
Short name T810
Test name
Test status
Simulation time 159543619 ps
CPU time 2.77 seconds
Started Mar 26 03:29:23 PM PDT 24
Finished Mar 26 03:29:26 PM PDT 24
Peak memory 208912 kb
Host smart-76436962-e53b-4753-b9a9-c0140c53499c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4067353282 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_otbn.4067353282
Directory /workspace/27.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/27.keymgr_sideload_protect.3427475893
Short name T176
Test name
Test status
Simulation time 323444235 ps
CPU time 3.98 seconds
Started Mar 26 03:29:13 PM PDT 24
Finished Mar 26 03:29:17 PM PDT 24
Peak memory 218724 kb
Host smart-e2d527f5-dc93-49f0-97f5-67bc1ec74982
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3427475893 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sideload_protect.3427475893
Directory /workspace/27.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/27.keymgr_smoke.3004489231
Short name T536
Test name
Test status
Simulation time 47836881 ps
CPU time 2.35 seconds
Started Mar 26 03:29:01 PM PDT 24
Finished Mar 26 03:29:04 PM PDT 24
Peak memory 207092 kb
Host smart-7eb48864-76d0-4fbd-b24f-ea9f9b3534a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004489231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_smoke.3004489231
Directory /workspace/27.keymgr_smoke/latest

Test location /workspace/coverage/default/27.keymgr_stress_all.580353806
Short name T171
Test name
Test status
Simulation time 789558413 ps
CPU time 20.01 seconds
Started Mar 26 03:29:15 PM PDT 24
Finished Mar 26 03:29:35 PM PDT 24
Peak memory 215004 kb
Host smart-0caaa85a-e270-4a3d-9020-117cdf5a569d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=580353806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_stress_all.580353806
Directory /workspace/27.keymgr_stress_all/latest

Test location /workspace/coverage/default/27.keymgr_sw_invalid_input.2280399293
Short name T631
Test name
Test status
Simulation time 193942713 ps
CPU time 5.63 seconds
Started Mar 26 03:29:12 PM PDT 24
Finished Mar 26 03:29:17 PM PDT 24
Peak memory 208928 kb
Host smart-5da16561-af0f-4e40-b4f3-de1205e623f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280399293 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sw_invalid_input.2280399293
Directory /workspace/27.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/27.keymgr_sync_async_fault_cross.3580306586
Short name T380
Test name
Test status
Simulation time 136447902 ps
CPU time 3.24 seconds
Started Mar 26 03:29:22 PM PDT 24
Finished Mar 26 03:29:25 PM PDT 24
Peak memory 210720 kb
Host smart-ff2cd5fe-55cb-445e-bd6c-96ba091a8a4a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3580306586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.keymgr_sync_async_fault_cross.3580306586
Directory /workspace/27.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/28.keymgr_alert_test.3276261272
Short name T537
Test name
Test status
Simulation time 19323113 ps
CPU time 0.78 seconds
Started Mar 26 03:29:16 PM PDT 24
Finished Mar 26 03:29:17 PM PDT 24
Peak memory 206312 kb
Host smart-4b7cb65b-c474-45bd-98bd-05b2279f7597
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3276261272 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_alert_test.3276261272
Directory /workspace/28.keymgr_alert_test/latest

Test location /workspace/coverage/default/28.keymgr_cfg_regwen.1246050220
Short name T295
Test name
Test status
Simulation time 1390816047 ps
CPU time 72.84 seconds
Started Mar 26 03:29:03 PM PDT 24
Finished Mar 26 03:30:15 PM PDT 24
Peak memory 215600 kb
Host smart-da098796-3f51-47ad-be19-a7b0f5af42f6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1246050220 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_cfg_regwen.1246050220
Directory /workspace/28.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/28.keymgr_direct_to_disabled.3500118123
Short name T646
Test name
Test status
Simulation time 74340037 ps
CPU time 1.9 seconds
Started Mar 26 03:29:55 PM PDT 24
Finished Mar 26 03:29:57 PM PDT 24
Peak memory 208888 kb
Host smart-8e66c93f-bcc7-44d1-b7ee-83ffa00b7017
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3500118123 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_direct_to_disabled.3500118123
Directory /workspace/28.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/28.keymgr_hwsw_invalid_input.1555633199
Short name T621
Test name
Test status
Simulation time 39731187 ps
CPU time 2.55 seconds
Started Mar 26 03:29:02 PM PDT 24
Finished Mar 26 03:29:04 PM PDT 24
Peak memory 208904 kb
Host smart-17b202c0-a60e-4e7d-8708-d88d00d0c6d4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1555633199 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_hwsw_invalid_input.1555633199
Directory /workspace/28.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_kmac_rsp_err.4175476417
Short name T648
Test name
Test status
Simulation time 386016734 ps
CPU time 4.53 seconds
Started Mar 26 03:29:02 PM PDT 24
Finished Mar 26 03:29:06 PM PDT 24
Peak memory 222700 kb
Host smart-5bfb71e9-47cb-4031-aa93-b259bbb86a1d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175476417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_kmac_rsp_err.4175476417
Directory /workspace/28.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/28.keymgr_lc_disable.1701493223
Short name T864
Test name
Test status
Simulation time 148146896 ps
CPU time 6.44 seconds
Started Mar 26 03:29:11 PM PDT 24
Finished Mar 26 03:29:17 PM PDT 24
Peak memory 222876 kb
Host smart-c0b9979a-dd2a-441e-a1f6-9b63916a2e88
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1701493223 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_lc_disable.1701493223
Directory /workspace/28.keymgr_lc_disable/latest

Test location /workspace/coverage/default/28.keymgr_random.1310905649
Short name T550
Test name
Test status
Simulation time 479169273 ps
CPU time 12.85 seconds
Started Mar 26 03:29:03 PM PDT 24
Finished Mar 26 03:29:16 PM PDT 24
Peak memory 207840 kb
Host smart-7ce933a0-ed48-4ccc-b93e-d95c805b2d33
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310905649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_random.1310905649
Directory /workspace/28.keymgr_random/latest

Test location /workspace/coverage/default/28.keymgr_sideload.1617194828
Short name T364
Test name
Test status
Simulation time 1934668125 ps
CPU time 24.22 seconds
Started Mar 26 03:29:20 PM PDT 24
Finished Mar 26 03:29:44 PM PDT 24
Peak memory 209288 kb
Host smart-c4d618f4-34eb-451d-97fc-65280e179969
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617194828 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload.1617194828
Directory /workspace/28.keymgr_sideload/latest

Test location /workspace/coverage/default/28.keymgr_sideload_aes.2825077546
Short name T555
Test name
Test status
Simulation time 154969520 ps
CPU time 2.35 seconds
Started Mar 26 03:29:09 PM PDT 24
Finished Mar 26 03:29:11 PM PDT 24
Peak memory 207492 kb
Host smart-4ab22a4e-19ad-4b98-9aea-48a9826c419f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2825077546 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_aes.2825077546
Directory /workspace/28.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/28.keymgr_sideload_kmac.3021934544
Short name T506
Test name
Test status
Simulation time 152025181 ps
CPU time 2.76 seconds
Started Mar 26 03:29:11 PM PDT 24
Finished Mar 26 03:29:14 PM PDT 24
Peak memory 208668 kb
Host smart-b32aeffa-9126-4a30-b970-1f31edb702ac
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3021934544 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_kmac.3021934544
Directory /workspace/28.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/28.keymgr_sideload_otbn.1728337722
Short name T559
Test name
Test status
Simulation time 77980308 ps
CPU time 3.03 seconds
Started Mar 26 03:29:16 PM PDT 24
Finished Mar 26 03:29:19 PM PDT 24
Peak memory 208844 kb
Host smart-208ed7da-4193-47a5-bad1-b875249cc6e3
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1728337722 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_otbn.1728337722
Directory /workspace/28.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/28.keymgr_sideload_protect.3921209325
Short name T717
Test name
Test status
Simulation time 138546353 ps
CPU time 2.4 seconds
Started Mar 26 03:29:30 PM PDT 24
Finished Mar 26 03:29:33 PM PDT 24
Peak memory 214724 kb
Host smart-1dea92e8-0e2c-4c9f-a5a5-3a9d05d6ac19
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3921209325 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sideload_protect.3921209325
Directory /workspace/28.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/28.keymgr_smoke.865781049
Short name T109
Test name
Test status
Simulation time 2089986437 ps
CPU time 41.27 seconds
Started Mar 26 03:29:11 PM PDT 24
Finished Mar 26 03:29:53 PM PDT 24
Peak memory 208988 kb
Host smart-714bee80-9346-4097-8e55-7b6869d667a2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=865781049 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_smoke.865781049
Directory /workspace/28.keymgr_smoke/latest

Test location /workspace/coverage/default/28.keymgr_sw_invalid_input.49283473
Short name T512
Test name
Test status
Simulation time 195891619 ps
CPU time 4.67 seconds
Started Mar 26 03:29:27 PM PDT 24
Finished Mar 26 03:29:32 PM PDT 24
Peak memory 214708 kb
Host smart-7401547d-69c5-480f-8042-75bcaad194fe
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=49283473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sw_invalid_input.49283473
Directory /workspace/28.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/28.keymgr_sync_async_fault_cross.2553597927
Short name T133
Test name
Test status
Simulation time 32606289 ps
CPU time 1.85 seconds
Started Mar 26 03:29:11 PM PDT 24
Finished Mar 26 03:29:13 PM PDT 24
Peak memory 210224 kb
Host smart-a21a94dd-3360-4ece-9232-deed02f5db90
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2553597927 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.keymgr_sync_async_fault_cross.2553597927
Directory /workspace/28.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/29.keymgr_alert_test.1934357350
Short name T446
Test name
Test status
Simulation time 16027957 ps
CPU time 0.75 seconds
Started Mar 26 03:29:30 PM PDT 24
Finished Mar 26 03:29:31 PM PDT 24
Peak memory 206248 kb
Host smart-bc0ddee0-bcfc-45af-9376-702624ea8928
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1934357350 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_alert_test.1934357350
Directory /workspace/29.keymgr_alert_test/latest

Test location /workspace/coverage/default/29.keymgr_cfg_regwen.491618336
Short name T270
Test name
Test status
Simulation time 49249534 ps
CPU time 3.62 seconds
Started Mar 26 03:29:12 PM PDT 24
Finished Mar 26 03:29:16 PM PDT 24
Peak memory 214748 kb
Host smart-c2fdae68-d114-4358-a20f-766d4498b86a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=491618336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_cfg_regwen.491618336
Directory /workspace/29.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/29.keymgr_custom_cm.3090483453
Short name T218
Test name
Test status
Simulation time 87933692 ps
CPU time 2.88 seconds
Started Mar 26 03:29:15 PM PDT 24
Finished Mar 26 03:29:20 PM PDT 24
Peak memory 208900 kb
Host smart-3ba416c9-745b-49ef-b9ef-4e26511f3128
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3090483453 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_custom_cm.3090483453
Directory /workspace/29.keymgr_custom_cm/latest

Test location /workspace/coverage/default/29.keymgr_direct_to_disabled.2900618338
Short name T409
Test name
Test status
Simulation time 55743851 ps
CPU time 2.01 seconds
Started Mar 26 03:29:20 PM PDT 24
Finished Mar 26 03:29:22 PM PDT 24
Peak memory 209960 kb
Host smart-2b7dfb7a-fdb6-44e4-a82a-aac916d763e4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2900618338 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_direct_to_disabled.2900618338
Directory /workspace/29.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/29.keymgr_hwsw_invalid_input.1767321943
Short name T516
Test name
Test status
Simulation time 18946168891 ps
CPU time 65.27 seconds
Started Mar 26 03:29:17 PM PDT 24
Finished Mar 26 03:30:22 PM PDT 24
Peak memory 222904 kb
Host smart-6afce07c-2ee7-46d4-82a5-ec8649d1a197
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1767321943 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_hwsw_invalid_input.1767321943
Directory /workspace/29.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_kmac_rsp_err.1058594637
Short name T265
Test name
Test status
Simulation time 482593097 ps
CPU time 4.71 seconds
Started Mar 26 03:29:15 PM PDT 24
Finished Mar 26 03:29:20 PM PDT 24
Peak memory 222688 kb
Host smart-a51c58a2-6c93-4861-9597-1078f90236e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058594637 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_kmac_rsp_err.1058594637
Directory /workspace/29.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/29.keymgr_lc_disable.3556831562
Short name T889
Test name
Test status
Simulation time 1119834880 ps
CPU time 3.59 seconds
Started Mar 26 03:29:11 PM PDT 24
Finished Mar 26 03:29:15 PM PDT 24
Peak memory 218640 kb
Host smart-0ddfada6-97d7-45f7-89ad-8aa5bc401f56
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3556831562 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_lc_disable.3556831562
Directory /workspace/29.keymgr_lc_disable/latest

Test location /workspace/coverage/default/29.keymgr_random.1058447191
Short name T483
Test name
Test status
Simulation time 61132641 ps
CPU time 3.49 seconds
Started Mar 26 03:29:09 PM PDT 24
Finished Mar 26 03:29:13 PM PDT 24
Peak memory 218648 kb
Host smart-4b000338-7514-4b5a-82c4-963cfbc745ba
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058447191 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_random.1058447191
Directory /workspace/29.keymgr_random/latest

Test location /workspace/coverage/default/29.keymgr_sideload.2565174206
Short name T806
Test name
Test status
Simulation time 461638797 ps
CPU time 13.82 seconds
Started Mar 26 03:29:03 PM PDT 24
Finished Mar 26 03:29:17 PM PDT 24
Peak memory 208960 kb
Host smart-56ab5a94-cec4-4891-9569-179e014dd97a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565174206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload.2565174206
Directory /workspace/29.keymgr_sideload/latest

Test location /workspace/coverage/default/29.keymgr_sideload_aes.2814124494
Short name T599
Test name
Test status
Simulation time 219764738 ps
CPU time 7.1 seconds
Started Mar 26 03:29:01 PM PDT 24
Finished Mar 26 03:29:08 PM PDT 24
Peak memory 208080 kb
Host smart-729161e4-59c4-4e20-b9ed-04e11fd82286
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2814124494 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_aes.2814124494
Directory /workspace/29.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/29.keymgr_sideload_kmac.2954175055
Short name T839
Test name
Test status
Simulation time 209954408 ps
CPU time 4.7 seconds
Started Mar 26 03:29:09 PM PDT 24
Finished Mar 26 03:29:14 PM PDT 24
Peak memory 207344 kb
Host smart-40e1b166-15ed-4cbe-bfbc-bc75471e7023
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2954175055 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_kmac.2954175055
Directory /workspace/29.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/29.keymgr_sideload_otbn.2568989081
Short name T175
Test name
Test status
Simulation time 1741040057 ps
CPU time 43.5 seconds
Started Mar 26 03:29:10 PM PDT 24
Finished Mar 26 03:29:54 PM PDT 24
Peak memory 208840 kb
Host smart-92a75344-d250-4052-944d-6215eca78277
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2568989081 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_otbn.2568989081
Directory /workspace/29.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/29.keymgr_sideload_protect.1542560433
Short name T794
Test name
Test status
Simulation time 103959869 ps
CPU time 3.06 seconds
Started Mar 26 03:29:14 PM PDT 24
Finished Mar 26 03:29:17 PM PDT 24
Peak memory 214740 kb
Host smart-e99557b7-c757-4906-9476-d931576fb194
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1542560433 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sideload_protect.1542560433
Directory /workspace/29.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/29.keymgr_smoke.2581298419
Short name T85
Test name
Test status
Simulation time 207307669 ps
CPU time 3.31 seconds
Started Mar 26 03:29:25 PM PDT 24
Finished Mar 26 03:29:28 PM PDT 24
Peak memory 207032 kb
Host smart-3e3d7c84-53e6-4df2-a7bf-c201254e4769
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2581298419 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_smoke.2581298419
Directory /workspace/29.keymgr_smoke/latest

Test location /workspace/coverage/default/29.keymgr_stress_all.713135035
Short name T63
Test name
Test status
Simulation time 1085657397 ps
CPU time 14.74 seconds
Started Mar 26 03:29:12 PM PDT 24
Finished Mar 26 03:29:27 PM PDT 24
Peak memory 216272 kb
Host smart-312670b0-1abd-40af-8f64-96c6a9ae61a1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713135035 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all.713135035
Directory /workspace/29.keymgr_stress_all/latest

Test location /workspace/coverage/default/29.keymgr_stress_all_with_rand_reset.243763387
Short name T125
Test name
Test status
Simulation time 618634638 ps
CPU time 18.88 seconds
Started Mar 26 03:29:11 PM PDT 24
Finished Mar 26 03:29:30 PM PDT 24
Peak memory 222980 kb
Host smart-42699da0-ce8e-41d4-bfd0-9ca672e890ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=243763387 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 29.keymgr_stress_all_with_rand_reset.243763387
Directory /workspace/29.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.keymgr_sw_invalid_input.3821476606
Short name T309
Test name
Test status
Simulation time 239228108 ps
CPU time 3.64 seconds
Started Mar 26 03:29:11 PM PDT 24
Finished Mar 26 03:29:15 PM PDT 24
Peak memory 218500 kb
Host smart-61020c0f-4eb6-4bc0-b95e-7eec4f6fb604
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3821476606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sw_invalid_input.3821476606
Directory /workspace/29.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/29.keymgr_sync_async_fault_cross.15346848
Short name T378
Test name
Test status
Simulation time 72535222 ps
CPU time 2.85 seconds
Started Mar 26 03:29:19 PM PDT 24
Finished Mar 26 03:29:22 PM PDT 24
Peak memory 210204 kb
Host smart-9884315a-7a84-4e69-83bf-2c424425d719
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=15346848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.keymgr_sync_async_fault_cross.15346848
Directory /workspace/29.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/3.keymgr_alert_test.2726348053
Short name T531
Test name
Test status
Simulation time 18153281 ps
CPU time 0.78 seconds
Started Mar 26 03:28:08 PM PDT 24
Finished Mar 26 03:28:09 PM PDT 24
Peak memory 206268 kb
Host smart-639f7b95-5f0d-48c4-b9b0-01635c4409c2
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2726348053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_alert_test.2726348053
Directory /workspace/3.keymgr_alert_test/latest

Test location /workspace/coverage/default/3.keymgr_custom_cm.1094628023
Short name T227
Test name
Test status
Simulation time 191701507 ps
CPU time 8.53 seconds
Started Mar 26 03:28:08 PM PDT 24
Finished Mar 26 03:28:16 PM PDT 24
Peak memory 214952 kb
Host smart-aaee9708-f1fe-49df-90b2-07fce618e9f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1094628023 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_custom_cm.1094628023
Directory /workspace/3.keymgr_custom_cm/latest

Test location /workspace/coverage/default/3.keymgr_direct_to_disabled.3244077974
Short name T45
Test name
Test status
Simulation time 61382367 ps
CPU time 2.04 seconds
Started Mar 26 03:28:23 PM PDT 24
Finished Mar 26 03:28:25 PM PDT 24
Peak memory 214732 kb
Host smart-4d65f788-f7d3-4af2-82a5-c5f837628977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3244077974 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_direct_to_disabled.3244077974
Directory /workspace/3.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/3.keymgr_hwsw_invalid_input.2902108804
Short name T750
Test name
Test status
Simulation time 63875325 ps
CPU time 3.77 seconds
Started Mar 26 03:28:17 PM PDT 24
Finished Mar 26 03:28:21 PM PDT 24
Peak memory 214596 kb
Host smart-2cb587af-e6bd-443d-a108-77ddc8e2cb3a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2902108804 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_hwsw_invalid_input.2902108804
Directory /workspace/3.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/3.keymgr_lc_disable.1666480800
Short name T209
Test name
Test status
Simulation time 606971520 ps
CPU time 4.39 seconds
Started Mar 26 03:28:19 PM PDT 24
Finished Mar 26 03:28:23 PM PDT 24
Peak memory 215544 kb
Host smart-eac3e9b0-a5b5-41b2-8ebd-872783c824bc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1666480800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_lc_disable.1666480800
Directory /workspace/3.keymgr_lc_disable/latest

Test location /workspace/coverage/default/3.keymgr_random.1603828349
Short name T368
Test name
Test status
Simulation time 336564560 ps
CPU time 4.34 seconds
Started Mar 26 03:28:10 PM PDT 24
Finished Mar 26 03:28:14 PM PDT 24
Peak memory 207532 kb
Host smart-c9962359-930d-4496-8bab-a69a0cb7eec1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1603828349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_random.1603828349
Directory /workspace/3.keymgr_random/latest

Test location /workspace/coverage/default/3.keymgr_sideload.3451886982
Short name T269
Test name
Test status
Simulation time 30002128 ps
CPU time 2.12 seconds
Started Mar 26 03:28:24 PM PDT 24
Finished Mar 26 03:28:27 PM PDT 24
Peak memory 209140 kb
Host smart-abb0d340-c746-42ba-a90d-db7007afac06
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3451886982 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload.3451886982
Directory /workspace/3.keymgr_sideload/latest

Test location /workspace/coverage/default/3.keymgr_sideload_aes.1538194401
Short name T838
Test name
Test status
Simulation time 83546915 ps
CPU time 3.74 seconds
Started Mar 26 03:28:16 PM PDT 24
Finished Mar 26 03:28:21 PM PDT 24
Peak memory 208928 kb
Host smart-de72f424-126f-4bdf-99db-186e487ded8e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538194401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_aes.1538194401
Directory /workspace/3.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/3.keymgr_sideload_kmac.1769074671
Short name T696
Test name
Test status
Simulation time 4404615339 ps
CPU time 44.53 seconds
Started Mar 26 03:28:14 PM PDT 24
Finished Mar 26 03:29:04 PM PDT 24
Peak memory 208808 kb
Host smart-7d370df3-72ae-4089-a85b-395577613c35
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1769074671 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_kmac.1769074671
Directory /workspace/3.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/3.keymgr_sideload_otbn.262376848
Short name T900
Test name
Test status
Simulation time 37200598 ps
CPU time 2.53 seconds
Started Mar 26 03:28:16 PM PDT 24
Finished Mar 26 03:28:19 PM PDT 24
Peak memory 208940 kb
Host smart-4120ddcb-1d63-4fad-b091-33fbebdee22d
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=262376848 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_otbn.262376848
Directory /workspace/3.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/3.keymgr_sideload_protect.1781438761
Short name T408
Test name
Test status
Simulation time 553795689 ps
CPU time 4.57 seconds
Started Mar 26 03:28:17 PM PDT 24
Finished Mar 26 03:28:22 PM PDT 24
Peak memory 209956 kb
Host smart-d90e9cdc-8cf0-483a-a025-bf3e7ab5524d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1781438761 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sideload_protect.1781438761
Directory /workspace/3.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/3.keymgr_smoke.251075334
Short name T457
Test name
Test status
Simulation time 30765421 ps
CPU time 2.08 seconds
Started Mar 26 03:28:08 PM PDT 24
Finished Mar 26 03:28:10 PM PDT 24
Peak memory 207080 kb
Host smart-47151068-5d15-44d4-90cc-53a22e089c97
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=251075334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_smoke.251075334
Directory /workspace/3.keymgr_smoke/latest

Test location /workspace/coverage/default/3.keymgr_stress_all.4001712417
Short name T7
Test name
Test status
Simulation time 2093348607 ps
CPU time 46.83 seconds
Started Mar 26 03:28:19 PM PDT 24
Finished Mar 26 03:29:06 PM PDT 24
Peak memory 222944 kb
Host smart-0deaa52c-4cb3-4cd2-9de4-3fe826dc788d
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4001712417 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all.4001712417
Directory /workspace/3.keymgr_stress_all/latest

Test location /workspace/coverage/default/3.keymgr_stress_all_with_rand_reset.398828248
Short name T60
Test name
Test status
Simulation time 7098633332 ps
CPU time 17.11 seconds
Started Mar 26 03:28:21 PM PDT 24
Finished Mar 26 03:28:38 PM PDT 24
Peak memory 223004 kb
Host smart-bb880434-7601-42d3-a867-f86d18cca94f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=398828248 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 3.keymgr_stress_all_with_rand_reset.398828248
Directory /workspace/3.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.keymgr_sync_async_fault_cross.274374991
Short name T909
Test name
Test status
Simulation time 54327682 ps
CPU time 1.78 seconds
Started Mar 26 03:28:16 PM PDT 24
Finished Mar 26 03:28:18 PM PDT 24
Peak memory 210144 kb
Host smart-80af2a71-4d19-4111-af78-be0dfb9655a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274374991 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.keymgr_sync_async_fault_cross.274374991
Directory /workspace/3.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/30.keymgr_alert_test.115236054
Short name T629
Test name
Test status
Simulation time 54140445 ps
CPU time 0.8 seconds
Started Mar 26 03:29:33 PM PDT 24
Finished Mar 26 03:29:34 PM PDT 24
Peak memory 206320 kb
Host smart-28034845-d0e5-44fe-b8a0-d47b282ed56f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=115236054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_alert_test.115236054
Directory /workspace/30.keymgr_alert_test/latest

Test location /workspace/coverage/default/30.keymgr_direct_to_disabled.2192710109
Short name T74
Test name
Test status
Simulation time 211124514 ps
CPU time 2.73 seconds
Started Mar 26 03:29:15 PM PDT 24
Finished Mar 26 03:29:18 PM PDT 24
Peak memory 209680 kb
Host smart-867fbdcb-14d9-4b83-8cdf-fc3a503eca51
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192710109 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_direct_to_disabled.2192710109
Directory /workspace/30.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/30.keymgr_hwsw_invalid_input.975415225
Short name T96
Test name
Test status
Simulation time 979985397 ps
CPU time 8.32 seconds
Started Mar 26 03:29:35 PM PDT 24
Finished Mar 26 03:29:43 PM PDT 24
Peak memory 214632 kb
Host smart-0a82d994-266a-4884-be98-e0ac3a56022a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=975415225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_hwsw_invalid_input.975415225
Directory /workspace/30.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_kmac_rsp_err.2226596274
Short name T285
Test name
Test status
Simulation time 65196763 ps
CPU time 3.88 seconds
Started Mar 26 03:29:45 PM PDT 24
Finished Mar 26 03:29:49 PM PDT 24
Peak memory 222692 kb
Host smart-11c4629b-81ec-4cac-8f52-2b766f3672ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2226596274 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_kmac_rsp_err.2226596274
Directory /workspace/30.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/30.keymgr_lc_disable.1043846237
Short name T826
Test name
Test status
Simulation time 91940762 ps
CPU time 2.19 seconds
Started Mar 26 03:29:29 PM PDT 24
Finished Mar 26 03:29:37 PM PDT 24
Peak memory 219412 kb
Host smart-1b42b403-089b-438c-8004-49f60d9e3d30
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1043846237 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_lc_disable.1043846237
Directory /workspace/30.keymgr_lc_disable/latest

Test location /workspace/coverage/default/30.keymgr_random.829578393
Short name T665
Test name
Test status
Simulation time 82876113 ps
CPU time 3.17 seconds
Started Mar 26 03:29:19 PM PDT 24
Finished Mar 26 03:29:23 PM PDT 24
Peak memory 209580 kb
Host smart-b3355031-7f0b-4e8e-8877-a7b37073070b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=829578393 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_random.829578393
Directory /workspace/30.keymgr_random/latest

Test location /workspace/coverage/default/30.keymgr_sideload.1339532762
Short name T581
Test name
Test status
Simulation time 657692675 ps
CPU time 7.31 seconds
Started Mar 26 03:29:20 PM PDT 24
Finished Mar 26 03:29:27 PM PDT 24
Peak memory 208840 kb
Host smart-ef243335-425b-48a7-a74d-7942ae8c6325
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1339532762 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload.1339532762
Directory /workspace/30.keymgr_sideload/latest

Test location /workspace/coverage/default/30.keymgr_sideload_aes.2149675303
Short name T733
Test name
Test status
Simulation time 89873038 ps
CPU time 1.77 seconds
Started Mar 26 03:29:34 PM PDT 24
Finished Mar 26 03:29:36 PM PDT 24
Peak memory 207192 kb
Host smart-71898404-5ef3-4eca-9616-be7ac09882dc
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2149675303 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_aes.2149675303
Directory /workspace/30.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/30.keymgr_sideload_kmac.884518977
Short name T833
Test name
Test status
Simulation time 109745679 ps
CPU time 3.78 seconds
Started Mar 26 03:29:22 PM PDT 24
Finished Mar 26 03:29:26 PM PDT 24
Peak memory 206976 kb
Host smart-353289f4-ddad-4093-a0d3-bcd4abc763ca
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884518977 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_kmac.884518977
Directory /workspace/30.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/30.keymgr_sideload_otbn.2320678763
Short name T852
Test name
Test status
Simulation time 231398939 ps
CPU time 3.48 seconds
Started Mar 26 03:29:36 PM PDT 24
Finished Mar 26 03:29:40 PM PDT 24
Peak memory 207680 kb
Host smart-f3632f5b-2f81-4afa-b470-a016d58c2491
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320678763 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_otbn.2320678763
Directory /workspace/30.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/30.keymgr_sideload_protect.636964461
Short name T840
Test name
Test status
Simulation time 149941360 ps
CPU time 2.31 seconds
Started Mar 26 03:29:12 PM PDT 24
Finished Mar 26 03:29:15 PM PDT 24
Peak memory 216080 kb
Host smart-10b37c4e-098b-4e4b-a9b4-3892384cd6ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=636964461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sideload_protect.636964461
Directory /workspace/30.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/30.keymgr_smoke.1506854266
Short name T672
Test name
Test status
Simulation time 893252222 ps
CPU time 4.67 seconds
Started Mar 26 03:29:34 PM PDT 24
Finished Mar 26 03:29:39 PM PDT 24
Peak memory 206988 kb
Host smart-606fb553-09b7-42dd-b956-bfc1bc4b94af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506854266 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_smoke.1506854266
Directory /workspace/30.keymgr_smoke/latest

Test location /workspace/coverage/default/30.keymgr_stress_all.1928450517
Short name T693
Test name
Test status
Simulation time 5567044599 ps
CPU time 58.83 seconds
Started Mar 26 03:29:23 PM PDT 24
Finished Mar 26 03:30:22 PM PDT 24
Peak memory 222952 kb
Host smart-1eed643b-e4c8-4581-9b5c-427a76c0e52e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1928450517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_stress_all.1928450517
Directory /workspace/30.keymgr_stress_all/latest

Test location /workspace/coverage/default/30.keymgr_sw_invalid_input.2383821623
Short name T585
Test name
Test status
Simulation time 57545810 ps
CPU time 3.48 seconds
Started Mar 26 03:29:15 PM PDT 24
Finished Mar 26 03:29:19 PM PDT 24
Peak memory 209620 kb
Host smart-1df0919c-5412-4286-b335-c29bbe0670e3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2383821623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sw_invalid_input.2383821623
Directory /workspace/30.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/30.keymgr_sync_async_fault_cross.3510244758
Short name T181
Test name
Test status
Simulation time 308134010 ps
CPU time 1.3 seconds
Started Mar 26 03:29:31 PM PDT 24
Finished Mar 26 03:29:32 PM PDT 24
Peak memory 209680 kb
Host smart-5189a4bf-c6c3-4cd2-b0c8-3c472fe32ffb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3510244758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.keymgr_sync_async_fault_cross.3510244758
Directory /workspace/30.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/31.keymgr_alert_test.528052305
Short name T824
Test name
Test status
Simulation time 34975012 ps
CPU time 0.81 seconds
Started Mar 26 03:29:24 PM PDT 24
Finished Mar 26 03:29:25 PM PDT 24
Peak memory 206296 kb
Host smart-31254cc6-efa8-413e-850b-c0974e1e0b51
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=528052305 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_alert_test.528052305
Directory /workspace/31.keymgr_alert_test/latest

Test location /workspace/coverage/default/31.keymgr_direct_to_disabled.496128125
Short name T774
Test name
Test status
Simulation time 1649206393 ps
CPU time 9.68 seconds
Started Mar 26 03:29:15 PM PDT 24
Finished Mar 26 03:29:25 PM PDT 24
Peak memory 209376 kb
Host smart-9f9d3736-498a-40cb-a80a-6201acc948e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496128125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_direct_to_disabled.496128125
Directory /workspace/31.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/31.keymgr_lc_disable.2076521938
Short name T50
Test name
Test status
Simulation time 126560161 ps
CPU time 5.41 seconds
Started Mar 26 03:29:29 PM PDT 24
Finished Mar 26 03:29:34 PM PDT 24
Peak memory 220808 kb
Host smart-190e3e68-15e5-4a85-b8e5-89778346d1f2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2076521938 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_lc_disable.2076521938
Directory /workspace/31.keymgr_lc_disable/latest

Test location /workspace/coverage/default/31.keymgr_random.1367522508
Short name T141
Test name
Test status
Simulation time 33037637276 ps
CPU time 49.13 seconds
Started Mar 26 03:29:19 PM PDT 24
Finished Mar 26 03:30:09 PM PDT 24
Peak memory 210324 kb
Host smart-5ba39ed5-3fba-4232-bff3-52045f8e12ce
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1367522508 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_random.1367522508
Directory /workspace/31.keymgr_random/latest

Test location /workspace/coverage/default/31.keymgr_sideload.2873434806
Short name T814
Test name
Test status
Simulation time 51532679 ps
CPU time 2.61 seconds
Started Mar 26 03:29:30 PM PDT 24
Finished Mar 26 03:29:33 PM PDT 24
Peak memory 208220 kb
Host smart-e2efaa62-9eac-4034-9812-f485f53e841c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2873434806 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload.2873434806
Directory /workspace/31.keymgr_sideload/latest

Test location /workspace/coverage/default/31.keymgr_sideload_aes.3608563339
Short name T728
Test name
Test status
Simulation time 328496833 ps
CPU time 3.61 seconds
Started Mar 26 03:29:25 PM PDT 24
Finished Mar 26 03:29:28 PM PDT 24
Peak memory 209016 kb
Host smart-9eb5a01f-17f9-45ee-8888-1dde2eb04e08
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3608563339 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_aes.3608563339
Directory /workspace/31.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/31.keymgr_sideload_kmac.208004616
Short name T735
Test name
Test status
Simulation time 1145300894 ps
CPU time 8.82 seconds
Started Mar 26 03:29:16 PM PDT 24
Finished Mar 26 03:29:25 PM PDT 24
Peak memory 208420 kb
Host smart-0f845aa5-dacb-4fa4-9dde-01e86e865500
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=208004616 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_kmac.208004616
Directory /workspace/31.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/31.keymgr_sideload_otbn.3733322251
Short name T459
Test name
Test status
Simulation time 7449101297 ps
CPU time 11.49 seconds
Started Mar 26 03:29:39 PM PDT 24
Finished Mar 26 03:29:50 PM PDT 24
Peak memory 209012 kb
Host smart-bac48f7c-c9e2-4700-836b-9f7cfbf729db
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733322251 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_otbn.3733322251
Directory /workspace/31.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/31.keymgr_sideload_protect.2831182572
Short name T505
Test name
Test status
Simulation time 3036626929 ps
CPU time 26.8 seconds
Started Mar 26 03:29:29 PM PDT 24
Finished Mar 26 03:29:56 PM PDT 24
Peak memory 208816 kb
Host smart-e8491f4c-1038-49a4-96ab-f85d59a04f1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2831182572 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sideload_protect.2831182572
Directory /workspace/31.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/31.keymgr_smoke.592746027
Short name T832
Test name
Test status
Simulation time 1021202426 ps
CPU time 7.25 seconds
Started Mar 26 03:29:33 PM PDT 24
Finished Mar 26 03:29:40 PM PDT 24
Peak memory 209040 kb
Host smart-0d24f73b-28f4-4ef9-89d2-776f383220fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=592746027 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_smoke.592746027
Directory /workspace/31.keymgr_smoke/latest

Test location /workspace/coverage/default/31.keymgr_stress_all.3240734687
Short name T341
Test name
Test status
Simulation time 181224624 ps
CPU time 6.87 seconds
Started Mar 26 03:29:12 PM PDT 24
Finished Mar 26 03:29:19 PM PDT 24
Peak memory 218868 kb
Host smart-20ba7011-5c60-4492-b9e3-efacd4bc617e
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3240734687 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all.3240734687
Directory /workspace/31.keymgr_stress_all/latest

Test location /workspace/coverage/default/31.keymgr_stress_all_with_rand_reset.3449199347
Short name T128
Test name
Test status
Simulation time 359549132 ps
CPU time 8.45 seconds
Started Mar 26 03:29:49 PM PDT 24
Finished Mar 26 03:29:58 PM PDT 24
Peak memory 219656 kb
Host smart-a2feb5f4-a3c0-45ed-988e-e5c92836df64
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3449199347 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 31.keymgr_stress_all_with_rand_reset.3449199347
Directory /workspace/31.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.keymgr_sw_invalid_input.1051984185
Short name T276
Test name
Test status
Simulation time 327826870 ps
CPU time 4.06 seconds
Started Mar 26 03:29:12 PM PDT 24
Finished Mar 26 03:29:16 PM PDT 24
Peak memory 207972 kb
Host smart-c8fc3dd7-b6b4-437a-a6f2-1562392a8e8b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1051984185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sw_invalid_input.1051984185
Directory /workspace/31.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/31.keymgr_sync_async_fault_cross.3738519603
Short name T802
Test name
Test status
Simulation time 89160146 ps
CPU time 2.48 seconds
Started Mar 26 03:29:35 PM PDT 24
Finished Mar 26 03:29:37 PM PDT 24
Peak memory 210372 kb
Host smart-48b2e081-a335-4621-98c7-e313695f2bf4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3738519603 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.keymgr_sync_async_fault_cross.3738519603
Directory /workspace/31.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/32.keymgr_alert_test.3340902336
Short name T461
Test name
Test status
Simulation time 34775891 ps
CPU time 0.78 seconds
Started Mar 26 03:29:32 PM PDT 24
Finished Mar 26 03:29:33 PM PDT 24
Peak memory 206348 kb
Host smart-c676a211-1397-4671-9cd1-b27295b7f5aa
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3340902336 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_alert_test.3340902336
Directory /workspace/32.keymgr_alert_test/latest

Test location /workspace/coverage/default/32.keymgr_cfg_regwen.2096716204
Short name T891
Test name
Test status
Simulation time 1030904824 ps
CPU time 13.67 seconds
Started Mar 26 03:29:36 PM PDT 24
Finished Mar 26 03:29:50 PM PDT 24
Peak memory 215676 kb
Host smart-38d39873-c3be-4062-9734-e63589274bc6
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2096716204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_cfg_regwen.2096716204
Directory /workspace/32.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/32.keymgr_direct_to_disabled.651291401
Short name T400
Test name
Test status
Simulation time 114881963 ps
CPU time 2.1 seconds
Started Mar 26 03:29:17 PM PDT 24
Finished Mar 26 03:29:19 PM PDT 24
Peak memory 214640 kb
Host smart-d20b843a-145e-4dae-85a7-a7cab4c67977
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651291401 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_direct_to_disabled.651291401
Directory /workspace/32.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/32.keymgr_hwsw_invalid_input.512154633
Short name T308
Test name
Test status
Simulation time 276806217 ps
CPU time 5.57 seconds
Started Mar 26 03:29:34 PM PDT 24
Finished Mar 26 03:29:39 PM PDT 24
Peak memory 220720 kb
Host smart-7376e29f-524d-4a83-8df5-c5b9bd60cb29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512154633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_hwsw_invalid_input.512154633
Directory /workspace/32.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_lc_disable.1455807334
Short name T55
Test name
Test status
Simulation time 131086419 ps
CPU time 3.17 seconds
Started Mar 26 03:29:19 PM PDT 24
Finished Mar 26 03:29:23 PM PDT 24
Peak memory 208916 kb
Host smart-41d4f504-1f9f-4cb5-b1cb-68d5060bd25b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455807334 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_lc_disable.1455807334
Directory /workspace/32.keymgr_lc_disable/latest

Test location /workspace/coverage/default/32.keymgr_random.524019327
Short name T497
Test name
Test status
Simulation time 89714986 ps
CPU time 2.94 seconds
Started Mar 26 03:29:15 PM PDT 24
Finished Mar 26 03:29:18 PM PDT 24
Peak memory 215608 kb
Host smart-e3f224c6-1d2e-48f5-b296-0510d1527354
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=524019327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_random.524019327
Directory /workspace/32.keymgr_random/latest

Test location /workspace/coverage/default/32.keymgr_sideload.983732583
Short name T360
Test name
Test status
Simulation time 4452803680 ps
CPU time 28.48 seconds
Started Mar 26 03:29:23 PM PDT 24
Finished Mar 26 03:29:52 PM PDT 24
Peak memory 208812 kb
Host smart-db12aac4-c105-4306-a7b8-df229c232e29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983732583 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload.983732583
Directory /workspace/32.keymgr_sideload/latest

Test location /workspace/coverage/default/32.keymgr_sideload_aes.1773975956
Short name T503
Test name
Test status
Simulation time 76305954 ps
CPU time 2.95 seconds
Started Mar 26 03:29:27 PM PDT 24
Finished Mar 26 03:29:30 PM PDT 24
Peak memory 208868 kb
Host smart-f8260916-7427-4d37-ace2-bb7ea9d1eb51
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1773975956 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_aes.1773975956
Directory /workspace/32.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/32.keymgr_sideload_kmac.694771682
Short name T653
Test name
Test status
Simulation time 899495884 ps
CPU time 24.33 seconds
Started Mar 26 03:29:31 PM PDT 24
Finished Mar 26 03:29:55 PM PDT 24
Peak memory 208524 kb
Host smart-e71b26fa-882c-4873-8114-b24bbb281b93
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=694771682 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_kmac.694771682
Directory /workspace/32.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/32.keymgr_sideload_otbn.4113815436
Short name T518
Test name
Test status
Simulation time 158635885 ps
CPU time 5.25 seconds
Started Mar 26 03:29:15 PM PDT 24
Finished Mar 26 03:29:20 PM PDT 24
Peak memory 207156 kb
Host smart-c2afdfa9-ac0c-4fa5-8b5a-3badea82237a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4113815436 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_otbn.4113815436
Directory /workspace/32.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/32.keymgr_sideload_protect.1934458092
Short name T345
Test name
Test status
Simulation time 380775800 ps
CPU time 3.27 seconds
Started Mar 26 03:29:20 PM PDT 24
Finished Mar 26 03:29:23 PM PDT 24
Peak memory 216356 kb
Host smart-63c7f424-d740-4982-8212-24548e24bb7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1934458092 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sideload_protect.1934458092
Directory /workspace/32.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/32.keymgr_smoke.2846933919
Short name T89
Test name
Test status
Simulation time 98234080 ps
CPU time 2.52 seconds
Started Mar 26 03:29:12 PM PDT 24
Finished Mar 26 03:29:15 PM PDT 24
Peak memory 207056 kb
Host smart-ef36f9b7-62e2-4f3a-b0c2-83deaa07e696
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2846933919 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_smoke.2846933919
Directory /workspace/32.keymgr_smoke/latest

Test location /workspace/coverage/default/32.keymgr_stress_all.3755777639
Short name T303
Test name
Test status
Simulation time 321941842 ps
CPU time 12.87 seconds
Started Mar 26 03:29:12 PM PDT 24
Finished Mar 26 03:29:25 PM PDT 24
Peak memory 220744 kb
Host smart-485a9676-12ce-4c8d-a7fd-839fb4bacb6a
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3755777639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_stress_all.3755777639
Directory /workspace/32.keymgr_stress_all/latest

Test location /workspace/coverage/default/32.keymgr_sw_invalid_input.926390012
Short name T237
Test name
Test status
Simulation time 160046168 ps
CPU time 3.9 seconds
Started Mar 26 03:29:14 PM PDT 24
Finished Mar 26 03:29:18 PM PDT 24
Peak memory 210380 kb
Host smart-e3c717a2-09bd-438d-92aa-89a856c90922
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926390012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sw_invalid_input.926390012
Directory /workspace/32.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/32.keymgr_sync_async_fault_cross.663237499
Short name T603
Test name
Test status
Simulation time 732934105 ps
CPU time 17.04 seconds
Started Mar 26 03:29:17 PM PDT 24
Finished Mar 26 03:29:34 PM PDT 24
Peak memory 211436 kb
Host smart-3ffa8a5f-ddab-45ac-8947-4685a29e383a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=663237499 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.keymgr_sync_async_fault_cross.663237499
Directory /workspace/32.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/33.keymgr_alert_test.3475491860
Short name T485
Test name
Test status
Simulation time 13148095 ps
CPU time 0.75 seconds
Started Mar 26 03:29:37 PM PDT 24
Finished Mar 26 03:29:38 PM PDT 24
Peak memory 206216 kb
Host smart-f0bf8f0a-70ee-4eff-b01d-6cc95ad0ca7f
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3475491860 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_alert_test.3475491860
Directory /workspace/33.keymgr_alert_test/latest

Test location /workspace/coverage/default/33.keymgr_custom_cm.2642223091
Short name T20
Test name
Test status
Simulation time 110554949 ps
CPU time 2.78 seconds
Started Mar 26 03:29:17 PM PDT 24
Finished Mar 26 03:29:19 PM PDT 24
Peak memory 214972 kb
Host smart-abdfc2ba-5b08-463f-b56d-69b5b6c295cf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642223091 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_custom_cm.2642223091
Directory /workspace/33.keymgr_custom_cm/latest

Test location /workspace/coverage/default/33.keymgr_direct_to_disabled.3886366889
Short name T532
Test name
Test status
Simulation time 65214883 ps
CPU time 1.59 seconds
Started Mar 26 03:29:36 PM PDT 24
Finished Mar 26 03:29:38 PM PDT 24
Peak memory 208308 kb
Host smart-4903eb8f-2d07-471c-88f3-0792167402bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3886366889 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_direct_to_disabled.3886366889
Directory /workspace/33.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/33.keymgr_hwsw_invalid_input.1758424739
Short name T92
Test name
Test status
Simulation time 454115852 ps
CPU time 4.33 seconds
Started Mar 26 03:29:16 PM PDT 24
Finished Mar 26 03:29:21 PM PDT 24
Peak memory 214748 kb
Host smart-2192f192-f40e-46db-beda-0b288f686444
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1758424739 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_hwsw_invalid_input.1758424739
Directory /workspace/33.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_kmac_rsp_err.3631264659
Short name T203
Test name
Test status
Simulation time 526861121 ps
CPU time 20.73 seconds
Started Mar 26 03:29:31 PM PDT 24
Finished Mar 26 03:29:51 PM PDT 24
Peak memory 211408 kb
Host smart-498d5716-e1f4-495f-8654-31b8a26f8dd2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3631264659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_kmac_rsp_err.3631264659
Directory /workspace/33.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/33.keymgr_lc_disable.1597018409
Short name T44
Test name
Test status
Simulation time 993423239 ps
CPU time 7.01 seconds
Started Mar 26 03:29:31 PM PDT 24
Finished Mar 26 03:29:38 PM PDT 24
Peak memory 210660 kb
Host smart-6723d614-64cb-4674-a302-8a0bad2a1a1c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1597018409 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_lc_disable.1597018409
Directory /workspace/33.keymgr_lc_disable/latest

Test location /workspace/coverage/default/33.keymgr_random.602766463
Short name T871
Test name
Test status
Simulation time 257346625 ps
CPU time 8.51 seconds
Started Mar 26 03:29:41 PM PDT 24
Finished Mar 26 03:29:49 PM PDT 24
Peak memory 208740 kb
Host smart-8085cae8-8418-4e14-8851-f5dc7267e739
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=602766463 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_random.602766463
Directory /workspace/33.keymgr_random/latest

Test location /workspace/coverage/default/33.keymgr_sideload.683169096
Short name T433
Test name
Test status
Simulation time 89308969 ps
CPU time 1.9 seconds
Started Mar 26 03:29:13 PM PDT 24
Finished Mar 26 03:29:15 PM PDT 24
Peak memory 207252 kb
Host smart-1b8a8764-edec-4305-b112-05105c98f9ca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=683169096 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload.683169096
Directory /workspace/33.keymgr_sideload/latest

Test location /workspace/coverage/default/33.keymgr_sideload_aes.2774244758
Short name T330
Test name
Test status
Simulation time 325973071 ps
CPU time 6.58 seconds
Started Mar 26 03:29:29 PM PDT 24
Finished Mar 26 03:29:36 PM PDT 24
Peak memory 208448 kb
Host smart-891f38c7-7168-4a67-9533-db9dcd960d74
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2774244758 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_aes.2774244758
Directory /workspace/33.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/33.keymgr_sideload_kmac.4072000561
Short name T875
Test name
Test status
Simulation time 245740167 ps
CPU time 5.56 seconds
Started Mar 26 03:29:32 PM PDT 24
Finished Mar 26 03:29:37 PM PDT 24
Peak memory 208820 kb
Host smart-10824d69-ab1d-41e8-a672-c5e0af97ff69
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4072000561 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_kmac.4072000561
Directory /workspace/33.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/33.keymgr_sideload_otbn.4261838212
Short name T14
Test name
Test status
Simulation time 234419666 ps
CPU time 7.74 seconds
Started Mar 26 03:29:35 PM PDT 24
Finished Mar 26 03:29:43 PM PDT 24
Peak memory 208256 kb
Host smart-7c1918d6-db90-4e78-9c13-de2e4e4fbbd4
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4261838212 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_otbn.4261838212
Directory /workspace/33.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/33.keymgr_sideload_protect.1216181555
Short name T441
Test name
Test status
Simulation time 83653427 ps
CPU time 1.57 seconds
Started Mar 26 03:29:30 PM PDT 24
Finished Mar 26 03:29:32 PM PDT 24
Peak memory 207256 kb
Host smart-252b9abc-697f-4bb1-8706-ed9aac73fb26
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1216181555 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sideload_protect.1216181555
Directory /workspace/33.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/33.keymgr_smoke.2665274125
Short name T394
Test name
Test status
Simulation time 121670548 ps
CPU time 3.54 seconds
Started Mar 26 03:29:33 PM PDT 24
Finished Mar 26 03:29:37 PM PDT 24
Peak memory 208396 kb
Host smart-7f46c5a5-997e-475e-85b5-63073456fd99
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2665274125 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_smoke.2665274125
Directory /workspace/33.keymgr_smoke/latest

Test location /workspace/coverage/default/33.keymgr_stress_all.2905036073
Short name T79
Test name
Test status
Simulation time 833235484 ps
CPU time 9.22 seconds
Started Mar 26 03:29:25 PM PDT 24
Finished Mar 26 03:29:34 PM PDT 24
Peak memory 216400 kb
Host smart-4f0db220-b5cd-4ba8-b845-75018cdad9a0
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2905036073 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all.2905036073
Directory /workspace/33.keymgr_stress_all/latest

Test location /workspace/coverage/default/33.keymgr_stress_all_with_rand_reset.3812828205
Short name T124
Test name
Test status
Simulation time 967740187 ps
CPU time 23.74 seconds
Started Mar 26 03:29:15 PM PDT 24
Finished Mar 26 03:29:39 PM PDT 24
Peak memory 220664 kb
Host smart-d2a96280-3b78-4adb-8092-7960fee789e4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812828205 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 33.keymgr_stress_all_with_rand_reset.3812828205
Directory /workspace/33.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.keymgr_sw_invalid_input.3796048611
Short name T108
Test name
Test status
Simulation time 442833042 ps
CPU time 6.16 seconds
Started Mar 26 03:29:13 PM PDT 24
Finished Mar 26 03:29:19 PM PDT 24
Peak memory 207716 kb
Host smart-3f5b3331-2619-419d-b6ca-3136abad1008
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3796048611 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sw_invalid_input.3796048611
Directory /workspace/33.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/33.keymgr_sync_async_fault_cross.2950137769
Short name T180
Test name
Test status
Simulation time 228461309 ps
CPU time 1.98 seconds
Started Mar 26 03:29:35 PM PDT 24
Finished Mar 26 03:29:37 PM PDT 24
Peak memory 211140 kb
Host smart-bb6f6172-1266-4e97-a20b-e000405f1009
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950137769 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.keymgr_sync_async_fault_cross.2950137769
Directory /workspace/33.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/34.keymgr_alert_test.3834996601
Short name T746
Test name
Test status
Simulation time 42642004 ps
CPU time 0.72 seconds
Started Mar 26 03:29:46 PM PDT 24
Finished Mar 26 03:29:47 PM PDT 24
Peak memory 206360 kb
Host smart-d77c71be-282c-4367-996d-13baefbdeb69
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3834996601 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_alert_test.3834996601
Directory /workspace/34.keymgr_alert_test/latest

Test location /workspace/coverage/default/34.keymgr_direct_to_disabled.4233671004
Short name T278
Test name
Test status
Simulation time 262732569 ps
CPU time 4.4 seconds
Started Mar 26 03:29:37 PM PDT 24
Finished Mar 26 03:29:41 PM PDT 24
Peak memory 209616 kb
Host smart-18e60e02-0104-47f6-9a25-6a72e51e6364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233671004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_direct_to_disabled.4233671004
Directory /workspace/34.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/34.keymgr_hwsw_invalid_input.3495752189
Short name T258
Test name
Test status
Simulation time 233255731 ps
CPU time 5.46 seconds
Started Mar 26 03:29:35 PM PDT 24
Finished Mar 26 03:29:41 PM PDT 24
Peak memory 214648 kb
Host smart-ff93e4c7-fc09-4523-811d-b471e8e34786
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495752189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_hwsw_invalid_input.3495752189
Directory /workspace/34.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_lc_disable.1353217531
Short name T788
Test name
Test status
Simulation time 155808947 ps
CPU time 3.97 seconds
Started Mar 26 03:29:45 PM PDT 24
Finished Mar 26 03:29:49 PM PDT 24
Peak memory 206520 kb
Host smart-b7401b55-6039-4b9d-85df-dff1d63209ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1353217531 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_lc_disable.1353217531
Directory /workspace/34.keymgr_lc_disable/latest

Test location /workspace/coverage/default/34.keymgr_random.2950230700
Short name T731
Test name
Test status
Simulation time 661996735 ps
CPU time 10.01 seconds
Started Mar 26 03:29:33 PM PDT 24
Finished Mar 26 03:29:43 PM PDT 24
Peak memory 214788 kb
Host smart-cc21a349-96c1-4e8b-b9f4-4718d7864123
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2950230700 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_random.2950230700
Directory /workspace/34.keymgr_random/latest

Test location /workspace/coverage/default/34.keymgr_sideload.2765150310
Short name T772
Test name
Test status
Simulation time 240693410 ps
CPU time 3.68 seconds
Started Mar 26 03:29:42 PM PDT 24
Finished Mar 26 03:29:45 PM PDT 24
Peak memory 206956 kb
Host smart-5694e8eb-2ed8-4858-8703-6dfb5f8d0e61
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2765150310 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload.2765150310
Directory /workspace/34.keymgr_sideload/latest

Test location /workspace/coverage/default/34.keymgr_sideload_aes.270657342
Short name T88
Test name
Test status
Simulation time 1051158442 ps
CPU time 27.82 seconds
Started Mar 26 03:29:42 PM PDT 24
Finished Mar 26 03:30:10 PM PDT 24
Peak memory 208764 kb
Host smart-e21a7100-ca8c-406a-8084-9cde8bd4845e
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=270657342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_aes.270657342
Directory /workspace/34.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/34.keymgr_sideload_kmac.3330817685
Short name T698
Test name
Test status
Simulation time 1695623682 ps
CPU time 36.44 seconds
Started Mar 26 03:29:35 PM PDT 24
Finished Mar 26 03:30:12 PM PDT 24
Peak memory 209296 kb
Host smart-5fc81344-6151-4aa2-bc87-4087db69aa25
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3330817685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_kmac.3330817685
Directory /workspace/34.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/34.keymgr_sideload_otbn.2823933143
Short name T768
Test name
Test status
Simulation time 566852800 ps
CPU time 16.04 seconds
Started Mar 26 03:29:51 PM PDT 24
Finished Mar 26 03:30:07 PM PDT 24
Peak memory 208624 kb
Host smart-2c1832a8-0647-410d-b8a3-0e3d6efb8ece
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2823933143 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_otbn.2823933143
Directory /workspace/34.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/34.keymgr_sideload_protect.50804988
Short name T710
Test name
Test status
Simulation time 125052004 ps
CPU time 2.9 seconds
Started Mar 26 03:29:50 PM PDT 24
Finished Mar 26 03:29:54 PM PDT 24
Peak memory 208788 kb
Host smart-43ce162b-38c7-4017-9822-51df4a1f337d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=50804988 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sideload_protect.50804988
Directory /workspace/34.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/34.keymgr_smoke.4198454358
Short name T730
Test name
Test status
Simulation time 171250458 ps
CPU time 5.64 seconds
Started Mar 26 03:29:30 PM PDT 24
Finished Mar 26 03:29:36 PM PDT 24
Peak memory 208420 kb
Host smart-1979062f-bd8a-4c4e-ba6c-63c525b0268d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198454358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_smoke.4198454358
Directory /workspace/34.keymgr_smoke/latest

Test location /workspace/coverage/default/34.keymgr_stress_all.690158656
Short name T867
Test name
Test status
Simulation time 2873681956 ps
CPU time 54.41 seconds
Started Mar 26 03:29:32 PM PDT 24
Finished Mar 26 03:30:26 PM PDT 24
Peak memory 221672 kb
Host smart-6b58a249-b4e7-4c02-8cd1-21a628c53eee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=690158656 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all.690158656
Directory /workspace/34.keymgr_stress_all/latest

Test location /workspace/coverage/default/34.keymgr_stress_all_with_rand_reset.893211065
Short name T660
Test name
Test status
Simulation time 232735270 ps
CPU time 10.45 seconds
Started Mar 26 03:29:33 PM PDT 24
Finished Mar 26 03:29:43 PM PDT 24
Peak memory 223008 kb
Host smart-8190177e-5082-44af-b7b8-82ec09251333
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=893211065 -assert nopost
proc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/def
ault.vdb -cm_log /dev/null -cm_name 34.keymgr_stress_all_with_rand_reset.893211065
Directory /workspace/34.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.keymgr_sw_invalid_input.2281647615
Short name T426
Test name
Test status
Simulation time 71493281 ps
CPU time 4.15 seconds
Started Mar 26 03:29:46 PM PDT 24
Finished Mar 26 03:29:50 PM PDT 24
Peak memory 218688 kb
Host smart-908650e8-1834-4413-a8b4-480a39cce426
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2281647615 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sw_invalid_input.2281647615
Directory /workspace/34.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/34.keymgr_sync_async_fault_cross.2029573571
Short name T827
Test name
Test status
Simulation time 482661721 ps
CPU time 3.63 seconds
Started Mar 26 03:29:39 PM PDT 24
Finished Mar 26 03:29:42 PM PDT 24
Peak memory 210712 kb
Host smart-1788e82b-d694-4b5d-8fe0-26dbc13ae02d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2029573571 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.keymgr_sync_async_fault_cross.2029573571
Directory /workspace/34.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/35.keymgr_alert_test.1072723240
Short name T472
Test name
Test status
Simulation time 20336061 ps
CPU time 0.83 seconds
Started Mar 26 03:29:45 PM PDT 24
Finished Mar 26 03:29:46 PM PDT 24
Peak memory 206216 kb
Host smart-78effff2-dd35-47a4-b978-b79b52bda702
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1072723240 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_alert_test.1072723240
Directory /workspace/35.keymgr_alert_test/latest

Test location /workspace/coverage/default/35.keymgr_custom_cm.891590189
Short name T38
Test name
Test status
Simulation time 38427366 ps
CPU time 2.65 seconds
Started Mar 26 03:29:47 PM PDT 24
Finished Mar 26 03:29:50 PM PDT 24
Peak memory 214696 kb
Host smart-319c75d6-3914-401f-b14f-aa34dfd442af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891590189 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_custom_cm.891590189
Directory /workspace/35.keymgr_custom_cm/latest

Test location /workspace/coverage/default/35.keymgr_direct_to_disabled.3731227711
Short name T76
Test name
Test status
Simulation time 878095834 ps
CPU time 3.09 seconds
Started Mar 26 03:29:38 PM PDT 24
Finished Mar 26 03:29:41 PM PDT 24
Peak memory 208144 kb
Host smart-4373dd6d-fdef-4e8d-9af8-01997f269a4b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3731227711 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_direct_to_disabled.3731227711
Directory /workspace/35.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/35.keymgr_hwsw_invalid_input.3125118661
Short name T767
Test name
Test status
Simulation time 1283684234 ps
CPU time 6.43 seconds
Started Mar 26 03:29:45 PM PDT 24
Finished Mar 26 03:29:51 PM PDT 24
Peak memory 217572 kb
Host smart-cb184c18-480f-4f9e-b10d-a69b6770ca1a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3125118661 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_hwsw_invalid_input.3125118661
Directory /workspace/35.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/35.keymgr_kmac_rsp_err.612992439
Short name T97
Test name
Test status
Simulation time 142268352 ps
CPU time 6.18 seconds
Started Mar 26 03:29:52 PM PDT 24
Finished Mar 26 03:29:59 PM PDT 24
Peak memory 222692 kb
Host smart-c4831b42-f7e3-434f-b56e-47a9e34bd88b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=612992439 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_kmac_rsp_err.612992439
Directory /workspace/35.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/35.keymgr_lc_disable.1193215491
Short name T570
Test name
Test status
Simulation time 102121555 ps
CPU time 2.02 seconds
Started Mar 26 03:29:32 PM PDT 24
Finished Mar 26 03:29:35 PM PDT 24
Peak memory 214672 kb
Host smart-8ae2c3df-d2cf-4aba-b2c9-8467358844da
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1193215491 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_lc_disable.1193215491
Directory /workspace/35.keymgr_lc_disable/latest

Test location /workspace/coverage/default/35.keymgr_random.650526623
Short name T243
Test name
Test status
Simulation time 2045156779 ps
CPU time 12 seconds
Started Mar 26 03:29:36 PM PDT 24
Finished Mar 26 03:29:48 PM PDT 24
Peak memory 218868 kb
Host smart-18efe028-a01b-40ff-90d3-5465a4c6ac4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=650526623 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_random.650526623
Directory /workspace/35.keymgr_random/latest

Test location /workspace/coverage/default/35.keymgr_sideload.4207210004
Short name T327
Test name
Test status
Simulation time 101253693 ps
CPU time 4.22 seconds
Started Mar 26 03:29:47 PM PDT 24
Finished Mar 26 03:29:51 PM PDT 24
Peak memory 208748 kb
Host smart-ccd08a1b-a5ba-4d59-80d3-af8ed51b5956
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4207210004 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload.4207210004
Directory /workspace/35.keymgr_sideload/latest

Test location /workspace/coverage/default/35.keymgr_sideload_aes.112791398
Short name T695
Test name
Test status
Simulation time 44254378 ps
CPU time 2.65 seconds
Started Mar 26 03:29:38 PM PDT 24
Finished Mar 26 03:29:41 PM PDT 24
Peak memory 207144 kb
Host smart-4d1177b3-d8f4-4eaa-92e8-c3da82940e24
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=112791398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_aes.112791398
Directory /workspace/35.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/35.keymgr_sideload_kmac.1687476489
Short name T490
Test name
Test status
Simulation time 217116199 ps
CPU time 6.07 seconds
Started Mar 26 03:29:37 PM PDT 24
Finished Mar 26 03:29:43 PM PDT 24
Peak memory 209164 kb
Host smart-67ada683-b6dc-4536-917f-4e75e6e8f5e1
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1687476489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_kmac.1687476489
Directory /workspace/35.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/35.keymgr_sideload_otbn.1831883816
Short name T658
Test name
Test status
Simulation time 62061718 ps
CPU time 2.9 seconds
Started Mar 26 03:29:52 PM PDT 24
Finished Mar 26 03:29:56 PM PDT 24
Peak memory 207832 kb
Host smart-bdc473ea-0236-43b3-82da-60d7e8e47fcf
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1831883816 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_otbn.1831883816
Directory /workspace/35.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/35.keymgr_sideload_protect.290046489
Short name T625
Test name
Test status
Simulation time 733794435 ps
CPU time 3.01 seconds
Started Mar 26 03:29:50 PM PDT 24
Finished Mar 26 03:29:54 PM PDT 24
Peak memory 218688 kb
Host smart-8327b176-fdb9-4d47-aaeb-28334d257cea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=290046489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sideload_protect.290046489
Directory /workspace/35.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/35.keymgr_smoke.3705329792
Short name T912
Test name
Test status
Simulation time 6498001342 ps
CPU time 36.92 seconds
Started Mar 26 03:29:37 PM PDT 24
Finished Mar 26 03:30:14 PM PDT 24
Peak memory 208632 kb
Host smart-7d6475c4-2b07-4b26-b541-399777e1dfd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3705329792 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_smoke.3705329792
Directory /workspace/35.keymgr_smoke/latest

Test location /workspace/coverage/default/35.keymgr_stress_all.558568743
Short name T347
Test name
Test status
Simulation time 5478414003 ps
CPU time 31.65 seconds
Started Mar 26 03:29:47 PM PDT 24
Finished Mar 26 03:30:18 PM PDT 24
Peak memory 215468 kb
Host smart-93d1c30c-ed87-4c55-b386-5210de3042b9
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558568743 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_stress_all.558568743
Directory /workspace/35.keymgr_stress_all/latest

Test location /workspace/coverage/default/35.keymgr_sw_invalid_input.2561044145
Short name T27
Test name
Test status
Simulation time 692428243 ps
CPU time 11.86 seconds
Started Mar 26 03:29:49 PM PDT 24
Finished Mar 26 03:30:01 PM PDT 24
Peak memory 214676 kb
Host smart-796f7b50-f9c8-44b0-8818-8fcecd8fa7c2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2561044145 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.keymgr_sw_invalid_input.2561044145
Directory /workspace/35.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_alert_test.4027611206
Short name T430
Test name
Test status
Simulation time 44517493 ps
CPU time 0.85 seconds
Started Mar 26 03:29:46 PM PDT 24
Finished Mar 26 03:29:47 PM PDT 24
Peak memory 206140 kb
Host smart-7493e9ce-a2a2-4448-8c13-eb4dd6cfe1d6
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4027611206 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_alert_test.4027611206
Directory /workspace/36.keymgr_alert_test/latest

Test location /workspace/coverage/default/36.keymgr_cfg_regwen.1012938399
Short name T777
Test name
Test status
Simulation time 98657032 ps
CPU time 3.72 seconds
Started Mar 26 03:29:58 PM PDT 24
Finished Mar 26 03:30:02 PM PDT 24
Peak memory 214664 kb
Host smart-e1c29795-802b-4966-aeaf-c237d03b4f8d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1012938399 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_cfg_regwen.1012938399
Directory /workspace/36.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/36.keymgr_custom_cm.1394128990
Short name T30
Test name
Test status
Simulation time 212976951 ps
CPU time 6 seconds
Started Mar 26 03:29:49 PM PDT 24
Finished Mar 26 03:29:55 PM PDT 24
Peak memory 218740 kb
Host smart-a4e99410-af16-4704-9b2a-c02ecfb80f71
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1394128990 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_custom_cm.1394128990
Directory /workspace/36.keymgr_custom_cm/latest

Test location /workspace/coverage/default/36.keymgr_direct_to_disabled.4158301118
Short name T374
Test name
Test status
Simulation time 602847906 ps
CPU time 13.39 seconds
Started Mar 26 03:29:51 PM PDT 24
Finished Mar 26 03:30:05 PM PDT 24
Peak memory 210472 kb
Host smart-0f75d109-2592-4c2a-b460-15263f5929dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4158301118 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_direct_to_disabled.4158301118
Directory /workspace/36.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/36.keymgr_hwsw_invalid_input.1748845362
Short name T98
Test name
Test status
Simulation time 402502405 ps
CPU time 6.07 seconds
Started Mar 26 03:29:50 PM PDT 24
Finished Mar 26 03:29:57 PM PDT 24
Peak memory 214680 kb
Host smart-90080c69-e1b6-486c-a320-97de06e2b6f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1748845362 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_hwsw_invalid_input.1748845362
Directory /workspace/36.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_kmac_rsp_err.2321126391
Short name T281
Test name
Test status
Simulation time 675636457 ps
CPU time 5.55 seconds
Started Mar 26 03:29:45 PM PDT 24
Finished Mar 26 03:29:51 PM PDT 24
Peak memory 222788 kb
Host smart-3bf0d5b6-bca3-4039-b415-d538c333da7c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2321126391 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_kmac_rsp_err.2321126391
Directory /workspace/36.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/36.keymgr_lc_disable.2449377320
Short name T566
Test name
Test status
Simulation time 77647141 ps
CPU time 2.97 seconds
Started Mar 26 03:29:50 PM PDT 24
Finished Mar 26 03:29:54 PM PDT 24
Peak memory 207552 kb
Host smart-8ceb5812-46a7-4383-b512-d5a9fc74ce32
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2449377320 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_lc_disable.2449377320
Directory /workspace/36.keymgr_lc_disable/latest

Test location /workspace/coverage/default/36.keymgr_random.3025510541
Short name T582
Test name
Test status
Simulation time 102894971 ps
CPU time 4.62 seconds
Started Mar 26 03:29:47 PM PDT 24
Finished Mar 26 03:29:53 PM PDT 24
Peak memory 218516 kb
Host smart-b1bc0173-f7b3-492f-babf-9720daf520b5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025510541 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_random.3025510541
Directory /workspace/36.keymgr_random/latest

Test location /workspace/coverage/default/36.keymgr_sideload.969071198
Short name T849
Test name
Test status
Simulation time 1078087941 ps
CPU time 15.19 seconds
Started Mar 26 03:29:46 PM PDT 24
Finished Mar 26 03:30:01 PM PDT 24
Peak memory 208348 kb
Host smart-2262c9c0-68c4-4b38-b21a-adb047c6363e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=969071198 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload.969071198
Directory /workspace/36.keymgr_sideload/latest

Test location /workspace/coverage/default/36.keymgr_sideload_aes.3570863685
Short name T651
Test name
Test status
Simulation time 231013539 ps
CPU time 3.52 seconds
Started Mar 26 03:29:50 PM PDT 24
Finished Mar 26 03:29:55 PM PDT 24
Peak memory 208620 kb
Host smart-920eae45-c345-47b8-aabd-a91446406959
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570863685 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_aes.3570863685
Directory /workspace/36.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/36.keymgr_sideload_kmac.2306157178
Short name T811
Test name
Test status
Simulation time 37860528 ps
CPU time 2.64 seconds
Started Mar 26 03:29:48 PM PDT 24
Finished Mar 26 03:29:52 PM PDT 24
Peak memory 208656 kb
Host smart-8c1323a6-ca9f-4d6f-9ffd-31101a66bdd2
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306157178 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_kmac.2306157178
Directory /workspace/36.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/36.keymgr_sideload_otbn.3532374858
Short name T766
Test name
Test status
Simulation time 403619237 ps
CPU time 4.08 seconds
Started Mar 26 03:29:49 PM PDT 24
Finished Mar 26 03:29:53 PM PDT 24
Peak memory 208984 kb
Host smart-35e8940c-6177-496d-b7c7-0288171b3ff7
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3532374858 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_otbn.3532374858
Directory /workspace/36.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/36.keymgr_sideload_protect.3970064793
Short name T478
Test name
Test status
Simulation time 3633211823 ps
CPU time 20.03 seconds
Started Mar 26 03:29:47 PM PDT 24
Finished Mar 26 03:30:07 PM PDT 24
Peak memory 214740 kb
Host smart-3f6926f4-2c39-4d07-ae7d-0d98d6056801
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3970064793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sideload_protect.3970064793
Directory /workspace/36.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/36.keymgr_smoke.1270942538
Short name T428
Test name
Test status
Simulation time 22226662 ps
CPU time 1.68 seconds
Started Mar 26 03:29:54 PM PDT 24
Finished Mar 26 03:29:56 PM PDT 24
Peak memory 207020 kb
Host smart-8d9d5ac1-cff5-4b7b-b4b9-426637183fd1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1270942538 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_smoke.1270942538
Directory /workspace/36.keymgr_smoke/latest

Test location /workspace/coverage/default/36.keymgr_stress_all.2294260827
Short name T530
Test name
Test status
Simulation time 332415872 ps
CPU time 8.19 seconds
Started Mar 26 03:29:44 PM PDT 24
Finished Mar 26 03:29:52 PM PDT 24
Peak memory 208780 kb
Host smart-ca28812d-887c-4c38-a086-fddd54ad97d3
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2294260827 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all.2294260827
Directory /workspace/36.keymgr_stress_all/latest

Test location /workspace/coverage/default/36.keymgr_stress_all_with_rand_reset.4255268928
Short name T835
Test name
Test status
Simulation time 402033148 ps
CPU time 15.93 seconds
Started Mar 26 03:29:47 PM PDT 24
Finished Mar 26 03:30:05 PM PDT 24
Peak memory 223088 kb
Host smart-ce5c32d8-9fa6-4299-93e4-a0098cc3d9e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4255268928 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 36.keymgr_stress_all_with_rand_reset.4255268928
Directory /workspace/36.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.keymgr_sw_invalid_input.1575146387
Short name T634
Test name
Test status
Simulation time 386305197 ps
CPU time 6.72 seconds
Started Mar 26 03:29:53 PM PDT 24
Finished Mar 26 03:30:00 PM PDT 24
Peak memory 208708 kb
Host smart-8bd56fe5-f02e-4837-9d3e-0680d5e32ff8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1575146387 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sw_invalid_input.1575146387
Directory /workspace/36.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/36.keymgr_sync_async_fault_cross.2855470610
Short name T4
Test name
Test status
Simulation time 41925624 ps
CPU time 2.43 seconds
Started Mar 26 03:29:43 PM PDT 24
Finished Mar 26 03:29:46 PM PDT 24
Peak memory 210260 kb
Host smart-63a88331-86af-417e-b001-858c6f72fb24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2855470610 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.keymgr_sync_async_fault_cross.2855470610
Directory /workspace/36.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/37.keymgr_alert_test.2934191699
Short name T452
Test name
Test status
Simulation time 43275386 ps
CPU time 0.77 seconds
Started Mar 26 03:29:49 PM PDT 24
Finished Mar 26 03:29:51 PM PDT 24
Peak memory 206252 kb
Host smart-f3901de4-2959-42f4-8e1c-5600d1b6d55c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934191699 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_alert_test.2934191699
Directory /workspace/37.keymgr_alert_test/latest

Test location /workspace/coverage/default/37.keymgr_cfg_regwen.2582275319
Short name T842
Test name
Test status
Simulation time 885577874 ps
CPU time 3.71 seconds
Started Mar 26 03:29:50 PM PDT 24
Finished Mar 26 03:29:54 PM PDT 24
Peak memory 214636 kb
Host smart-037cb18c-b15e-4ec8-ad3b-2142c24df369
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2582275319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_cfg_regwen.2582275319
Directory /workspace/37.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/37.keymgr_custom_cm.146969750
Short name T36
Test name
Test status
Simulation time 1181698844 ps
CPU time 7.17 seconds
Started Mar 26 03:29:42 PM PDT 24
Finished Mar 26 03:29:50 PM PDT 24
Peak memory 209136 kb
Host smart-b5cd9259-8f3d-40f3-aae8-d1436541ac13
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=146969750 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_custom_cm.146969750
Directory /workspace/37.keymgr_custom_cm/latest

Test location /workspace/coverage/default/37.keymgr_direct_to_disabled.1493206028
Short name T375
Test name
Test status
Simulation time 883207558 ps
CPU time 10.39 seconds
Started Mar 26 03:30:13 PM PDT 24
Finished Mar 26 03:30:24 PM PDT 24
Peak memory 210028 kb
Host smart-0782205f-bb03-4177-8087-e4a8e56ad3ae
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1493206028 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_direct_to_disabled.1493206028
Directory /workspace/37.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/37.keymgr_hwsw_invalid_input.2689877720
Short name T344
Test name
Test status
Simulation time 1475304984 ps
CPU time 4.24 seconds
Started Mar 26 03:29:58 PM PDT 24
Finished Mar 26 03:30:02 PM PDT 24
Peak memory 210068 kb
Host smart-1dd7e930-eb7b-4726-998f-c393d4895717
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2689877720 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_hwsw_invalid_input.2689877720
Directory /workspace/37.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_kmac_rsp_err.1998286477
Short name T280
Test name
Test status
Simulation time 1038343697 ps
CPU time 13.36 seconds
Started Mar 26 03:29:59 PM PDT 24
Finished Mar 26 03:30:14 PM PDT 24
Peak memory 216272 kb
Host smart-9c31d45f-281a-4ddd-a336-969c7cb5c970
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1998286477 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_kmac_rsp_err.1998286477
Directory /workspace/37.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/37.keymgr_lc_disable.995170609
Short name T210
Test name
Test status
Simulation time 110790595 ps
CPU time 3.54 seconds
Started Mar 26 03:29:48 PM PDT 24
Finished Mar 26 03:29:52 PM PDT 24
Peak memory 214744 kb
Host smart-761ddf80-f6cc-48da-8e04-824f167530e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=995170609 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_lc_disable.995170609
Directory /workspace/37.keymgr_lc_disable/latest

Test location /workspace/coverage/default/37.keymgr_random.1318634649
Short name T250
Test name
Test status
Simulation time 35650542 ps
CPU time 2.44 seconds
Started Mar 26 03:29:54 PM PDT 24
Finished Mar 26 03:29:57 PM PDT 24
Peak memory 214712 kb
Host smart-39a21866-ef1f-4f96-9955-56834ccc16b2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1318634649 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_random.1318634649
Directory /workspace/37.keymgr_random/latest

Test location /workspace/coverage/default/37.keymgr_sideload.2245560570
Short name T256
Test name
Test status
Simulation time 1994081552 ps
CPU time 6.01 seconds
Started Mar 26 03:29:52 PM PDT 24
Finished Mar 26 03:29:59 PM PDT 24
Peak memory 207036 kb
Host smart-df5d2c7b-6c58-4de9-b5ee-9660a1ff3076
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2245560570 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload.2245560570
Directory /workspace/37.keymgr_sideload/latest

Test location /workspace/coverage/default/37.keymgr_sideload_aes.4003590764
Short name T815
Test name
Test status
Simulation time 456849318 ps
CPU time 3.16 seconds
Started Mar 26 03:29:51 PM PDT 24
Finished Mar 26 03:29:55 PM PDT 24
Peak memory 209016 kb
Host smart-1c5b2bc4-eabd-447c-849c-b857732e8604
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003590764 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_aes.4003590764
Directory /workspace/37.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/37.keymgr_sideload_kmac.3941848371
Short name T757
Test name
Test status
Simulation time 69269988 ps
CPU time 3.16 seconds
Started Mar 26 03:30:04 PM PDT 24
Finished Mar 26 03:30:07 PM PDT 24
Peak memory 207100 kb
Host smart-fa915f48-774d-4cf4-a310-1c878a3559cf
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3941848371 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_kmac.3941848371
Directory /workspace/37.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/37.keymgr_sideload_otbn.3930837060
Short name T644
Test name
Test status
Simulation time 393091793 ps
CPU time 8.34 seconds
Started Mar 26 03:30:06 PM PDT 24
Finished Mar 26 03:30:14 PM PDT 24
Peak memory 208364 kb
Host smart-7c2531b7-90a3-4800-bfe4-bcb38432af80
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3930837060 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sideload_otbn.3930837060
Directory /workspace/37.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/37.keymgr_smoke.526326795
Short name T850
Test name
Test status
Simulation time 2214042712 ps
CPU time 15.67 seconds
Started Mar 26 03:29:52 PM PDT 24
Finished Mar 26 03:30:08 PM PDT 24
Peak memory 209044 kb
Host smart-e4024625-ad9c-490e-8cf0-5e75c9abc938
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=526326795 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_smoke.526326795
Directory /workspace/37.keymgr_smoke/latest

Test location /workspace/coverage/default/37.keymgr_stress_all.3952458659
Short name T219
Test name
Test status
Simulation time 10142947685 ps
CPU time 44.53 seconds
Started Mar 26 03:29:49 PM PDT 24
Finished Mar 26 03:30:34 PM PDT 24
Peak memory 216524 kb
Host smart-de2e15a9-98ea-45d9-a877-ca86c4f0f6de
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3952458659 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_stress_all.3952458659
Directory /workspace/37.keymgr_stress_all/latest

Test location /workspace/coverage/default/37.keymgr_sw_invalid_input.4171087104
Short name T856
Test name
Test status
Simulation time 94299608 ps
CPU time 4.33 seconds
Started Mar 26 03:29:57 PM PDT 24
Finished Mar 26 03:30:07 PM PDT 24
Peak memory 209100 kb
Host smart-bad6e3b9-9a18-48e8-bb51-c2ce5be25780
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4171087104 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sw_invalid_input.4171087104
Directory /workspace/37.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/37.keymgr_sync_async_fault_cross.890952543
Short name T112
Test name
Test status
Simulation time 60202408 ps
CPU time 2.08 seconds
Started Mar 26 03:29:55 PM PDT 24
Finished Mar 26 03:29:57 PM PDT 24
Peak memory 210440 kb
Host smart-173341c3-77fa-4d56-990d-c434103949e1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=890952543 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.keymgr_sync_async_fault_cross.890952543
Directory /workspace/37.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/38.keymgr_alert_test.927692605
Short name T450
Test name
Test status
Simulation time 12978255 ps
CPU time 0.73 seconds
Started Mar 26 03:29:49 PM PDT 24
Finished Mar 26 03:29:50 PM PDT 24
Peak memory 206284 kb
Host smart-90221df9-4f72-4f69-ad4e-f4c8d4673444
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=927692605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_alert_test.927692605
Directory /workspace/38.keymgr_alert_test/latest

Test location /workspace/coverage/default/38.keymgr_cfg_regwen.2856011729
Short name T422
Test name
Test status
Simulation time 538223962 ps
CPU time 3.71 seconds
Started Mar 26 03:29:50 PM PDT 24
Finished Mar 26 03:29:54 PM PDT 24
Peak memory 214584 kb
Host smart-d4c58ea5-5349-4e0c-812d-80b5b760f60a
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2856011729 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_cfg_regwen.2856011729
Directory /workspace/38.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/38.keymgr_custom_cm.1627982348
Short name T28
Test name
Test status
Simulation time 319103331 ps
CPU time 1.72 seconds
Started Mar 26 03:29:50 PM PDT 24
Finished Mar 26 03:29:52 PM PDT 24
Peak memory 223148 kb
Host smart-f550de9d-04cb-4aed-9ffb-d62a659e534f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1627982348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_custom_cm.1627982348
Directory /workspace/38.keymgr_custom_cm/latest

Test location /workspace/coverage/default/38.keymgr_direct_to_disabled.2618225855
Short name T522
Test name
Test status
Simulation time 501323903 ps
CPU time 2.36 seconds
Started Mar 26 03:29:51 PM PDT 24
Finished Mar 26 03:29:54 PM PDT 24
Peak memory 209532 kb
Host smart-d162fa45-081a-416d-8315-917beaff05f4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2618225855 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_direct_to_disabled.2618225855
Directory /workspace/38.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/38.keymgr_hwsw_invalid_input.2756469396
Short name T723
Test name
Test status
Simulation time 1985427655 ps
CPU time 7.2 seconds
Started Mar 26 03:30:01 PM PDT 24
Finished Mar 26 03:30:08 PM PDT 24
Peak memory 209300 kb
Host smart-3772936a-4e06-483e-b130-79c27557c63b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2756469396 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_hwsw_invalid_input.2756469396
Directory /workspace/38.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_kmac_rsp_err.1933758513
Short name T207
Test name
Test status
Simulation time 153506775 ps
CPU time 5.35 seconds
Started Mar 26 03:29:48 PM PDT 24
Finished Mar 26 03:29:54 PM PDT 24
Peak memory 209632 kb
Host smart-5eb1f6c0-dff6-4648-aa8a-2a911f94bfeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1933758513 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_kmac_rsp_err.1933758513
Directory /workspace/38.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/38.keymgr_lc_disable.4008792576
Short name T784
Test name
Test status
Simulation time 343079604 ps
CPU time 2.84 seconds
Started Mar 26 03:29:39 PM PDT 24
Finished Mar 26 03:29:42 PM PDT 24
Peak memory 218696 kb
Host smart-c919a696-f2f4-4648-becd-dcdfec4712c9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4008792576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_lc_disable.4008792576
Directory /workspace/38.keymgr_lc_disable/latest

Test location /workspace/coverage/default/38.keymgr_random.498258229
Short name T340
Test name
Test status
Simulation time 2015621836 ps
CPU time 7.49 seconds
Started Mar 26 03:29:53 PM PDT 24
Finished Mar 26 03:30:06 PM PDT 24
Peak memory 214596 kb
Host smart-39a20b7a-6c91-48d1-9847-adbf3f7e3973
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498258229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_random.498258229
Directory /workspace/38.keymgr_random/latest

Test location /workspace/coverage/default/38.keymgr_sideload.2204916618
Short name T577
Test name
Test status
Simulation time 50296157 ps
CPU time 2.69 seconds
Started Mar 26 03:30:02 PM PDT 24
Finished Mar 26 03:30:05 PM PDT 24
Peak memory 206944 kb
Host smart-aea76ee4-ef32-4aaa-9506-1668ad1bc438
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2204916618 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload.2204916618
Directory /workspace/38.keymgr_sideload/latest

Test location /workspace/coverage/default/38.keymgr_sideload_aes.254361457
Short name T484
Test name
Test status
Simulation time 161490407 ps
CPU time 5.9 seconds
Started Mar 26 03:29:53 PM PDT 24
Finished Mar 26 03:30:00 PM PDT 24
Peak memory 208188 kb
Host smart-3a0df054-04b6-4966-8a0a-b5b057c9337a
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=254361457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_aes.254361457
Directory /workspace/38.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/38.keymgr_sideload_kmac.1493463591
Short name T685
Test name
Test status
Simulation time 202053918 ps
CPU time 6.97 seconds
Started Mar 26 03:29:56 PM PDT 24
Finished Mar 26 03:30:03 PM PDT 24
Peak memory 208068 kb
Host smart-44896a4d-b4c8-4157-aa51-43a393d60288
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1493463591 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_kmac.1493463591
Directory /workspace/38.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/38.keymgr_sideload_otbn.4138519728
Short name T129
Test name
Test status
Simulation time 2991202866 ps
CPU time 5.57 seconds
Started Mar 26 03:29:52 PM PDT 24
Finished Mar 26 03:29:58 PM PDT 24
Peak memory 208936 kb
Host smart-dd1cc15c-c1af-41d8-8edf-6f72d3485604
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4138519728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_otbn.4138519728
Directory /workspace/38.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/38.keymgr_sideload_protect.4163425286
Short name T259
Test name
Test status
Simulation time 76957269 ps
CPU time 3.02 seconds
Started Mar 26 03:29:50 PM PDT 24
Finished Mar 26 03:29:54 PM PDT 24
Peak memory 208296 kb
Host smart-d7aadb5b-0cab-4db6-9f81-d874921cbcad
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4163425286 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sideload_protect.4163425286
Directory /workspace/38.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/38.keymgr_smoke.380421497
Short name T435
Test name
Test status
Simulation time 99954932 ps
CPU time 3.03 seconds
Started Mar 26 03:30:00 PM PDT 24
Finished Mar 26 03:30:04 PM PDT 24
Peak memory 208304 kb
Host smart-6974402d-3ac8-4113-9532-e091e4dc11a1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=380421497 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_smoke.380421497
Directory /workspace/38.keymgr_smoke/latest

Test location /workspace/coverage/default/38.keymgr_sw_invalid_input.2280950794
Short name T351
Test name
Test status
Simulation time 159622778 ps
CPU time 6.42 seconds
Started Mar 26 03:29:44 PM PDT 24
Finished Mar 26 03:29:51 PM PDT 24
Peak memory 210080 kb
Host smart-0dcff1f0-aced-4965-a5fd-d2db6905ae12
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2280950794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sw_invalid_input.2280950794
Directory /workspace/38.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/38.keymgr_sync_async_fault_cross.3736986447
Short name T729
Test name
Test status
Simulation time 405852816 ps
CPU time 9.41 seconds
Started Mar 26 03:29:50 PM PDT 24
Finished Mar 26 03:30:00 PM PDT 24
Peak memory 211184 kb
Host smart-e076812c-a972-43b3-965e-76084620f0ea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3736986447 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.keymgr_sync_async_fault_cross.3736986447
Directory /workspace/38.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/39.keymgr_alert_test.3416957200
Short name T427
Test name
Test status
Simulation time 8088468 ps
CPU time 0.72 seconds
Started Mar 26 03:30:03 PM PDT 24
Finished Mar 26 03:30:04 PM PDT 24
Peak memory 206292 kb
Host smart-cb7b9a0e-db98-4035-91a6-604d94d6649c
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3416957200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_alert_test.3416957200
Directory /workspace/39.keymgr_alert_test/latest

Test location /workspace/coverage/default/39.keymgr_cfg_regwen.3145275606
Short name T324
Test name
Test status
Simulation time 606354489 ps
CPU time 9.02 seconds
Started Mar 26 03:29:50 PM PDT 24
Finished Mar 26 03:30:00 PM PDT 24
Peak memory 222812 kb
Host smart-8e93b0c4-bec4-4b25-85d2-eab0c8df1fed
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3145275606 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_cfg_regwen.3145275606
Directory /workspace/39.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/39.keymgr_custom_cm.1234517876
Short name T816
Test name
Test status
Simulation time 43576708 ps
CPU time 2.26 seconds
Started Mar 26 03:29:51 PM PDT 24
Finished Mar 26 03:29:54 PM PDT 24
Peak memory 210892 kb
Host smart-061400dc-8c24-4d8c-a61d-c872affca34b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1234517876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_custom_cm.1234517876
Directory /workspace/39.keymgr_custom_cm/latest

Test location /workspace/coverage/default/39.keymgr_hwsw_invalid_input.2641584668
Short name T307
Test name
Test status
Simulation time 141669591 ps
CPU time 5.71 seconds
Started Mar 26 03:29:53 PM PDT 24
Finished Mar 26 03:30:00 PM PDT 24
Peak memory 214692 kb
Host smart-50a1a691-2e89-4020-9c11-ca75c901d799
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2641584668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_hwsw_invalid_input.2641584668
Directory /workspace/39.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_lc_disable.732582933
Short name T224
Test name
Test status
Simulation time 450685873 ps
CPU time 3.22 seconds
Started Mar 26 03:29:52 PM PDT 24
Finished Mar 26 03:29:56 PM PDT 24
Peak memory 220824 kb
Host smart-b5a17a57-81b2-4d04-8545-dbb4ce5a75f6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=732582933 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_lc_disable.732582933
Directory /workspace/39.keymgr_lc_disable/latest

Test location /workspace/coverage/default/39.keymgr_random.3673621085
Short name T821
Test name
Test status
Simulation time 173193066 ps
CPU time 5.17 seconds
Started Mar 26 03:29:49 PM PDT 24
Finished Mar 26 03:29:54 PM PDT 24
Peak memory 209140 kb
Host smart-0544aacf-8a25-49b3-9282-eced6c9993b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3673621085 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_random.3673621085
Directory /workspace/39.keymgr_random/latest

Test location /workspace/coverage/default/39.keymgr_sideload.1587529683
Short name T822
Test name
Test status
Simulation time 30146632 ps
CPU time 2.23 seconds
Started Mar 26 03:29:50 PM PDT 24
Finished Mar 26 03:29:53 PM PDT 24
Peak memory 207056 kb
Host smart-dc162c7e-723a-4db1-8db7-18dcf86e4eeb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1587529683 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload.1587529683
Directory /workspace/39.keymgr_sideload/latest

Test location /workspace/coverage/default/39.keymgr_sideload_aes.4087371542
Short name T876
Test name
Test status
Simulation time 23080890 ps
CPU time 2 seconds
Started Mar 26 03:29:56 PM PDT 24
Finished Mar 26 03:29:58 PM PDT 24
Peak memory 208832 kb
Host smart-d4eeb4ce-94dd-4340-a0b5-e9efd95282ef
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4087371542 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_aes.4087371542
Directory /workspace/39.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/39.keymgr_sideload_kmac.2702615146
Short name T526
Test name
Test status
Simulation time 1057474305 ps
CPU time 7.1 seconds
Started Mar 26 03:29:55 PM PDT 24
Finished Mar 26 03:30:02 PM PDT 24
Peak memory 208996 kb
Host smart-033f3822-d36c-4436-8b42-60c1c781a81e
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2702615146 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_kmac.2702615146
Directory /workspace/39.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/39.keymgr_sideload_otbn.2121349461
Short name T509
Test name
Test status
Simulation time 53114629 ps
CPU time 2.7 seconds
Started Mar 26 03:29:50 PM PDT 24
Finished Mar 26 03:29:54 PM PDT 24
Peak memory 207152 kb
Host smart-0a3adb9a-537a-4aa6-bc8f-47adc9c99f8c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2121349461 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_otbn.2121349461
Directory /workspace/39.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/39.keymgr_sideload_protect.4189232981
Short name T267
Test name
Test status
Simulation time 81262117 ps
CPU time 4.14 seconds
Started Mar 26 03:29:54 PM PDT 24
Finished Mar 26 03:29:59 PM PDT 24
Peak memory 209888 kb
Host smart-807ff939-e25a-45a8-90d9-204e92a991d6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4189232981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sideload_protect.4189232981
Directory /workspace/39.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/39.keymgr_smoke.447899231
Short name T700
Test name
Test status
Simulation time 921155829 ps
CPU time 17.51 seconds
Started Mar 26 03:29:53 PM PDT 24
Finished Mar 26 03:30:12 PM PDT 24
Peak memory 208600 kb
Host smart-60dc5c6a-d618-4981-8a23-cd7edc07f0fd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447899231 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_smoke.447899231
Directory /workspace/39.keymgr_smoke/latest

Test location /workspace/coverage/default/39.keymgr_sw_invalid_input.4227973654
Short name T820
Test name
Test status
Simulation time 1301578608 ps
CPU time 34.14 seconds
Started Mar 26 03:29:49 PM PDT 24
Finished Mar 26 03:30:24 PM PDT 24
Peak memory 209668 kb
Host smart-caf46d54-2807-4646-87c9-d423f17f6132
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4227973654 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sw_invalid_input.4227973654
Directory /workspace/39.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/39.keymgr_sync_async_fault_cross.2951791833
Short name T779
Test name
Test status
Simulation time 111513181 ps
CPU time 1.8 seconds
Started Mar 26 03:30:09 PM PDT 24
Finished Mar 26 03:30:11 PM PDT 24
Peak memory 210144 kb
Host smart-03317aeb-207b-432c-9c1d-f42216ca710f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2951791833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.keymgr_sync_async_fault_cross.2951791833
Directory /workspace/39.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/4.keymgr_alert_test.1226773462
Short name T647
Test name
Test status
Simulation time 18460117 ps
CPU time 0.86 seconds
Started Mar 26 03:28:09 PM PDT 24
Finished Mar 26 03:28:10 PM PDT 24
Peak memory 206200 kb
Host smart-d5d2e5e9-f2ad-4797-bd79-3287b7a25365
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1226773462 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_alert_test.1226773462
Directory /workspace/4.keymgr_alert_test/latest

Test location /workspace/coverage/default/4.keymgr_cfg_regwen.1760961033
Short name T405
Test name
Test status
Simulation time 1114117869 ps
CPU time 16.38 seconds
Started Mar 26 03:28:25 PM PDT 24
Finished Mar 26 03:28:42 PM PDT 24
Peak memory 216028 kb
Host smart-c33c9558-695d-49f8-9c74-33665196173d
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1760961033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_cfg_regwen.1760961033
Directory /workspace/4.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/4.keymgr_custom_cm.355498642
Short name T9
Test name
Test status
Simulation time 40803658 ps
CPU time 2.02 seconds
Started Mar 26 03:28:16 PM PDT 24
Finished Mar 26 03:28:18 PM PDT 24
Peak memory 209896 kb
Host smart-b8e8a8fa-4993-4013-886a-eb97c4c9c285
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=355498642 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_custom_cm.355498642
Directory /workspace/4.keymgr_custom_cm/latest

Test location /workspace/coverage/default/4.keymgr_direct_to_disabled.622645228
Short name T613
Test name
Test status
Simulation time 14156857 ps
CPU time 1.42 seconds
Started Mar 26 03:28:06 PM PDT 24
Finished Mar 26 03:28:09 PM PDT 24
Peak memory 207960 kb
Host smart-a8256039-74aa-4a3a-b51d-64d26dd3e8af
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=622645228 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_direct_to_disabled.622645228
Directory /workspace/4.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/4.keymgr_hwsw_invalid_input.1486337190
Short name T908
Test name
Test status
Simulation time 3820735885 ps
CPU time 23.55 seconds
Started Mar 26 03:28:07 PM PDT 24
Finished Mar 26 03:28:30 PM PDT 24
Peak memory 222964 kb
Host smart-d5b929c8-6395-4f66-b84f-37569e0eec0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1486337190 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_hwsw_invalid_input.1486337190
Directory /workspace/4.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_lc_disable.691098590
Short name T462
Test name
Test status
Simulation time 205337202 ps
CPU time 2.97 seconds
Started Mar 26 03:28:09 PM PDT 24
Finished Mar 26 03:28:12 PM PDT 24
Peak memory 219784 kb
Host smart-30df4e30-f10a-43a2-b579-fb2af0387114
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=691098590 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_lc_disable.691098590
Directory /workspace/4.keymgr_lc_disable/latest

Test location /workspace/coverage/default/4.keymgr_random.4122817787
Short name T759
Test name
Test status
Simulation time 218045490 ps
CPU time 4.33 seconds
Started Mar 26 03:28:20 PM PDT 24
Finished Mar 26 03:28:24 PM PDT 24
Peak memory 208088 kb
Host smart-1b20ae06-5f45-43b9-9b53-710ea6fa2cdc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4122817787 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_random.4122817787
Directory /workspace/4.keymgr_random/latest

Test location /workspace/coverage/default/4.keymgr_sec_cm.3315842995
Short name T104
Test name
Test status
Simulation time 2278476415 ps
CPU time 20.87 seconds
Started Mar 26 03:28:33 PM PDT 24
Finished Mar 26 03:28:54 PM PDT 24
Peak memory 232600 kb
Host smart-db971702-bb72-4641-9e32-6b7468fae45d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace
/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3315842995 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sec_cm.3315842995
Directory /workspace/4.keymgr_sec_cm/latest

Test location /workspace/coverage/default/4.keymgr_sideload.3391909605
Short name T623
Test name
Test status
Simulation time 128488034 ps
CPU time 3.12 seconds
Started Mar 26 03:28:21 PM PDT 24
Finished Mar 26 03:28:24 PM PDT 24
Peak memory 208784 kb
Host smart-99b20f20-a7f7-491d-96c0-c381291792e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391909605 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload.3391909605
Directory /workspace/4.keymgr_sideload/latest

Test location /workspace/coverage/default/4.keymgr_sideload_aes.4169869365
Short name T791
Test name
Test status
Simulation time 56584508 ps
CPU time 2.81 seconds
Started Mar 26 03:28:21 PM PDT 24
Finished Mar 26 03:28:24 PM PDT 24
Peak memory 208888 kb
Host smart-ac8f0915-4c84-4aa4-9b11-83be7b77f623
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4169869365 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_aes.4169869365
Directory /workspace/4.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/4.keymgr_sideload_kmac.4217745793
Short name T607
Test name
Test status
Simulation time 118490160 ps
CPU time 2.1 seconds
Started Mar 26 03:28:06 PM PDT 24
Finished Mar 26 03:28:09 PM PDT 24
Peak memory 208952 kb
Host smart-c8160f54-f859-4f9a-bbd9-34973b925eb5
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4217745793 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_kmac.4217745793
Directory /workspace/4.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/4.keymgr_sideload_otbn.2105566574
Short name T401
Test name
Test status
Simulation time 181645305 ps
CPU time 2.6 seconds
Started Mar 26 03:28:18 PM PDT 24
Finished Mar 26 03:28:20 PM PDT 24
Peak memory 207152 kb
Host smart-d5a3be1b-8c16-4e35-b05d-868f3e15289a
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2105566574 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_otbn.2105566574
Directory /workspace/4.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/4.keymgr_sideload_protect.1033669279
Short name T872
Test name
Test status
Simulation time 155184807 ps
CPU time 3.59 seconds
Started Mar 26 03:28:17 PM PDT 24
Finished Mar 26 03:28:21 PM PDT 24
Peak memory 208344 kb
Host smart-e9c52a9b-8a18-4b87-a935-477abd01b2e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1033669279 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sideload_protect.1033669279
Directory /workspace/4.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/4.keymgr_smoke.4212733079
Short name T790
Test name
Test status
Simulation time 419636583 ps
CPU time 2.75 seconds
Started Mar 26 03:28:18 PM PDT 24
Finished Mar 26 03:28:21 PM PDT 24
Peak memory 207132 kb
Host smart-dfb80e81-fabb-4efe-a4bf-dd59b16f706c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4212733079 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_smoke.4212733079
Directory /workspace/4.keymgr_smoke/latest

Test location /workspace/coverage/default/4.keymgr_stress_all_with_rand_reset.3733678854
Short name T103
Test name
Test status
Simulation time 643815854 ps
CPU time 7.73 seconds
Started Mar 26 03:28:16 PM PDT 24
Finished Mar 26 03:28:29 PM PDT 24
Peak memory 223080 kb
Host smart-a78e9854-a075-4f1e-abfe-be1ee370d83f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3733678854 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 4.keymgr_stress_all_with_rand_reset.3733678854
Directory /workspace/4.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.keymgr_sw_invalid_input.2911687234
Short name T801
Test name
Test status
Simulation time 84643649 ps
CPU time 3.93 seconds
Started Mar 26 03:28:42 PM PDT 24
Finished Mar 26 03:28:46 PM PDT 24
Peak memory 209004 kb
Host smart-bb47afed-d231-4514-9e14-47230ec49f21
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2911687234 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sw_invalid_input.2911687234
Directory /workspace/4.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/4.keymgr_sync_async_fault_cross.1126771455
Short name T593
Test name
Test status
Simulation time 128565813 ps
CPU time 2.47 seconds
Started Mar 26 03:28:08 PM PDT 24
Finished Mar 26 03:28:11 PM PDT 24
Peak memory 211180 kb
Host smart-9070c6bf-bd11-49a2-8017-9ffd86a5820e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1126771455 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.keymgr_sync_async_fault_cross.1126771455
Directory /workspace/4.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/40.keymgr_alert_test.1433072556
Short name T438
Test name
Test status
Simulation time 23531237 ps
CPU time 0.91 seconds
Started Mar 26 03:30:08 PM PDT 24
Finished Mar 26 03:30:10 PM PDT 24
Peak memory 206412 kb
Host smart-f7b9b21d-6b31-4895-8431-47bb0601a43e
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1433072556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_alert_test.1433072556
Directory /workspace/40.keymgr_alert_test/latest

Test location /workspace/coverage/default/40.keymgr_cfg_regwen.3854526256
Short name T236
Test name
Test status
Simulation time 92961588 ps
CPU time 3.25 seconds
Started Mar 26 03:29:59 PM PDT 24
Finished Mar 26 03:30:04 PM PDT 24
Peak memory 215132 kb
Host smart-7c64941c-395b-4eac-8629-7465aceff980
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3854526256 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_cfg_regwen.3854526256
Directory /workspace/40.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/40.keymgr_custom_cm.3899034398
Short name T637
Test name
Test status
Simulation time 830640695 ps
CPU time 6.88 seconds
Started Mar 26 03:30:05 PM PDT 24
Finished Mar 26 03:30:12 PM PDT 24
Peak memory 223072 kb
Host smart-b1e8e0a0-4069-468e-8fc0-61abad506886
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3899034398 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_custom_cm.3899034398
Directory /workspace/40.keymgr_custom_cm/latest

Test location /workspace/coverage/default/40.keymgr_direct_to_disabled.2410959087
Short name T584
Test name
Test status
Simulation time 14654392694 ps
CPU time 47.33 seconds
Started Mar 26 03:29:56 PM PDT 24
Finished Mar 26 03:30:44 PM PDT 24
Peak memory 208576 kb
Host smart-44cba7a2-2739-4c6c-a2a4-25c779ebfb9d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2410959087 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_direct_to_disabled.2410959087
Directory /workspace/40.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/40.keymgr_hwsw_invalid_input.2557099756
Short name T749
Test name
Test status
Simulation time 230650332 ps
CPU time 5.21 seconds
Started Mar 26 03:30:09 PM PDT 24
Finished Mar 26 03:30:14 PM PDT 24
Peak memory 220924 kb
Host smart-fc3d3a7b-3132-42a5-8566-98d78900f843
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2557099756 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_hwsw_invalid_input.2557099756
Directory /workspace/40.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_lc_disable.3290300438
Short name T216
Test name
Test status
Simulation time 333880904 ps
CPU time 2.4 seconds
Started Mar 26 03:29:57 PM PDT 24
Finished Mar 26 03:29:59 PM PDT 24
Peak memory 214880 kb
Host smart-021d1ec3-4517-4ec2-a5ba-d35c3de10cca
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3290300438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_lc_disable.3290300438
Directory /workspace/40.keymgr_lc_disable/latest

Test location /workspace/coverage/default/40.keymgr_random.3479006482
Short name T663
Test name
Test status
Simulation time 295452468 ps
CPU time 6.89 seconds
Started Mar 26 03:29:53 PM PDT 24
Finished Mar 26 03:30:01 PM PDT 24
Peak memory 219324 kb
Host smart-9d58f0e3-a935-414a-93e5-b9b8cf43fe42
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3479006482 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_random.3479006482
Directory /workspace/40.keymgr_random/latest

Test location /workspace/coverage/default/40.keymgr_sideload.3116545978
Short name T823
Test name
Test status
Simulation time 62733590 ps
CPU time 3.25 seconds
Started Mar 26 03:29:56 PM PDT 24
Finished Mar 26 03:30:00 PM PDT 24
Peak memory 208712 kb
Host smart-534bdc99-4e09-40a2-888d-8455339ec750
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3116545978 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload.3116545978
Directory /workspace/40.keymgr_sideload/latest

Test location /workspace/coverage/default/40.keymgr_sideload_aes.3976432010
Short name T843
Test name
Test status
Simulation time 165871018 ps
CPU time 5.02 seconds
Started Mar 26 03:29:52 PM PDT 24
Finished Mar 26 03:29:58 PM PDT 24
Peak memory 208956 kb
Host smart-513d8b08-ef60-47e1-b5b9-b9bc36fb455c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3976432010 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_aes.3976432010
Directory /workspace/40.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/40.keymgr_sideload_kmac.2311486358
Short name T288
Test name
Test status
Simulation time 288151552 ps
CPU time 3.56 seconds
Started Mar 26 03:30:01 PM PDT 24
Finished Mar 26 03:30:05 PM PDT 24
Peak memory 209044 kb
Host smart-121a1368-32ee-4099-b0a9-052fd2453725
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2311486358 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_kmac.2311486358
Directory /workspace/40.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/40.keymgr_sideload_otbn.1721171342
Short name T612
Test name
Test status
Simulation time 205748070 ps
CPU time 5.61 seconds
Started Mar 26 03:30:00 PM PDT 24
Finished Mar 26 03:30:06 PM PDT 24
Peak memory 208712 kb
Host smart-bda96597-cb6f-4c70-8acb-faf3cf4fac16
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1721171342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_otbn.1721171342
Directory /workspace/40.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/40.keymgr_sideload_protect.11658327
Short name T311
Test name
Test status
Simulation time 97499103 ps
CPU time 2.93 seconds
Started Mar 26 03:30:01 PM PDT 24
Finished Mar 26 03:30:05 PM PDT 24
Peak memory 208912 kb
Host smart-9733e585-7cd9-4fbd-b002-8a54229ae6f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11658327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sideload_protect.11658327
Directory /workspace/40.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/40.keymgr_smoke.2816939227
Short name T436
Test name
Test status
Simulation time 63166518 ps
CPU time 2.11 seconds
Started Mar 26 03:30:04 PM PDT 24
Finished Mar 26 03:30:06 PM PDT 24
Peak memory 207132 kb
Host smart-20c1aab1-57e2-4a76-af8c-5a19a52ad488
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2816939227 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_smoke.2816939227
Directory /workspace/40.keymgr_smoke/latest

Test location /workspace/coverage/default/40.keymgr_stress_all.1000105388
Short name T393
Test name
Test status
Simulation time 112758130 ps
CPU time 5.45 seconds
Started Mar 26 03:30:01 PM PDT 24
Finished Mar 26 03:30:07 PM PDT 24
Peak memory 208492 kb
Host smart-2bc61b5e-84f2-4bfd-98e3-ba622e5bc246
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1000105388 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_stress_all.1000105388
Directory /workspace/40.keymgr_stress_all/latest

Test location /workspace/coverage/default/40.keymgr_sw_invalid_input.584358457
Short name T841
Test name
Test status
Simulation time 33646905 ps
CPU time 2.63 seconds
Started Mar 26 03:30:05 PM PDT 24
Finished Mar 26 03:30:08 PM PDT 24
Peak memory 209968 kb
Host smart-ea272223-9bd2-4ea6-bcee-02f78fb85ee7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=584358457 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sw_invalid_input.584358457
Directory /workspace/40.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/40.keymgr_sync_async_fault_cross.315232313
Short name T796
Test name
Test status
Simulation time 146686060 ps
CPU time 3.11 seconds
Started Mar 26 03:29:58 PM PDT 24
Finished Mar 26 03:30:02 PM PDT 24
Peak memory 210132 kb
Host smart-e5c4a830-e426-4ab7-aee8-2a4047aafe4e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=315232313 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.keymgr_sync_async_fault_cross.315232313
Directory /workspace/40.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/41.keymgr_alert_test.3596865865
Short name T528
Test name
Test status
Simulation time 25728289 ps
CPU time 0.85 seconds
Started Mar 26 03:29:58 PM PDT 24
Finished Mar 26 03:30:01 PM PDT 24
Peak memory 206252 kb
Host smart-eba844fa-34b8-4dec-a6b4-7b7bb9de14a0
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3596865865 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_alert_test.3596865865
Directory /workspace/41.keymgr_alert_test/latest

Test location /workspace/coverage/default/41.keymgr_cfg_regwen.854257994
Short name T420
Test name
Test status
Simulation time 425718010 ps
CPU time 19.32 seconds
Started Mar 26 03:29:48 PM PDT 24
Finished Mar 26 03:30:08 PM PDT 24
Peak memory 215896 kb
Host smart-b2926fec-9145-4a95-8492-d48bf28f87f2
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=854257994 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_cfg_regwen.854257994
Directory /workspace/41.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/41.keymgr_custom_cm.1141417489
Short name T853
Test name
Test status
Simulation time 74786527 ps
CPU time 2.88 seconds
Started Mar 26 03:30:01 PM PDT 24
Finished Mar 26 03:30:04 PM PDT 24
Peak memory 208436 kb
Host smart-659965ff-a3c2-4d85-82d6-6d89805c1733
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1141417489 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_custom_cm.1141417489
Directory /workspace/41.keymgr_custom_cm/latest

Test location /workspace/coverage/default/41.keymgr_direct_to_disabled.1637784958
Short name T491
Test name
Test status
Simulation time 367083272 ps
CPU time 4.11 seconds
Started Mar 26 03:29:55 PM PDT 24
Finished Mar 26 03:29:59 PM PDT 24
Peak memory 210472 kb
Host smart-7ed084f4-f0ba-4abe-8e50-32f94c0da241
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1637784958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_direct_to_disabled.1637784958
Directory /workspace/41.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/41.keymgr_hwsw_invalid_input.4010510374
Short name T557
Test name
Test status
Simulation time 663574076 ps
CPU time 4.95 seconds
Started Mar 26 03:30:00 PM PDT 24
Finished Mar 26 03:30:06 PM PDT 24
Peak memory 209796 kb
Host smart-a8f3c31b-228d-4be5-a862-c2dde4a6f443
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4010510374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_hwsw_invalid_input.4010510374
Directory /workspace/41.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_lc_disable.3658289342
Short name T769
Test name
Test status
Simulation time 78429002 ps
CPU time 3.4 seconds
Started Mar 26 03:29:54 PM PDT 24
Finished Mar 26 03:29:58 PM PDT 24
Peak memory 207080 kb
Host smart-671fd098-a335-46c0-977b-9b928ed7c106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3658289342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_lc_disable.3658289342
Directory /workspace/41.keymgr_lc_disable/latest

Test location /workspace/coverage/default/41.keymgr_random.3810525147
Short name T235
Test name
Test status
Simulation time 305461934 ps
CPU time 11.04 seconds
Started Mar 26 03:29:58 PM PDT 24
Finished Mar 26 03:30:10 PM PDT 24
Peak memory 208436 kb
Host smart-b60ad1b0-19d5-4279-8c68-d91b26742ccf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3810525147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_random.3810525147
Directory /workspace/41.keymgr_random/latest

Test location /workspace/coverage/default/41.keymgr_sideload.2978813634
Short name T80
Test name
Test status
Simulation time 2663961559 ps
CPU time 31.61 seconds
Started Mar 26 03:29:56 PM PDT 24
Finished Mar 26 03:30:28 PM PDT 24
Peak memory 208444 kb
Host smart-8ab4ef61-ea7a-468d-8fff-9e68032bcc92
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978813634 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload.2978813634
Directory /workspace/41.keymgr_sideload/latest

Test location /workspace/coverage/default/41.keymgr_sideload_aes.1249860857
Short name T578
Test name
Test status
Simulation time 94573702 ps
CPU time 3.45 seconds
Started Mar 26 03:29:55 PM PDT 24
Finished Mar 26 03:29:59 PM PDT 24
Peak memory 207096 kb
Host smart-c453e079-a53b-471e-aae4-a498a23fc66f
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249860857 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_aes.1249860857
Directory /workspace/41.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/41.keymgr_sideload_kmac.3013773766
Short name T705
Test name
Test status
Simulation time 328533988 ps
CPU time 2.7 seconds
Started Mar 26 03:29:56 PM PDT 24
Finished Mar 26 03:29:59 PM PDT 24
Peak memory 208888 kb
Host smart-a2069b88-8cc3-4cb9-92cd-a53ed51abe2d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013773766 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_kmac.3013773766
Directory /workspace/41.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/41.keymgr_sideload_otbn.1370070916
Short name T744
Test name
Test status
Simulation time 145320670 ps
CPU time 2.66 seconds
Started Mar 26 03:29:58 PM PDT 24
Finished Mar 26 03:30:02 PM PDT 24
Peak memory 209116 kb
Host smart-bcffef3f-f659-4e9c-8824-8499bb6024ba
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370070916 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_otbn.1370070916
Directory /workspace/41.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/41.keymgr_sideload_protect.3208866932
Short name T589
Test name
Test status
Simulation time 45001753 ps
CPU time 1.82 seconds
Started Mar 26 03:29:53 PM PDT 24
Finished Mar 26 03:29:56 PM PDT 24
Peak memory 215920 kb
Host smart-2528eecd-c958-4f19-9bc9-9fb7e3eab3f0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208866932 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sideload_protect.3208866932
Directory /workspace/41.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/41.keymgr_smoke.4199003043
Short name T392
Test name
Test status
Simulation time 171180798 ps
CPU time 4.09 seconds
Started Mar 26 03:29:58 PM PDT 24
Finished Mar 26 03:30:03 PM PDT 24
Peak memory 208612 kb
Host smart-1964f0e1-6f14-4a15-b664-9a5f9a503da7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4199003043 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_smoke.4199003043
Directory /workspace/41.keymgr_smoke/latest

Test location /workspace/coverage/default/41.keymgr_sw_invalid_input.1494457844
Short name T333
Test name
Test status
Simulation time 4177657718 ps
CPU time 35.47 seconds
Started Mar 26 03:29:56 PM PDT 24
Finished Mar 26 03:30:32 PM PDT 24
Peak memory 208948 kb
Host smart-2278820a-840a-4b32-9f97-2f395328010e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1494457844 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sw_invalid_input.1494457844
Directory /workspace/41.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/41.keymgr_sync_async_fault_cross.2229661511
Short name T140
Test name
Test status
Simulation time 96170466 ps
CPU time 1.99 seconds
Started Mar 26 03:29:57 PM PDT 24
Finished Mar 26 03:29:59 PM PDT 24
Peak memory 210072 kb
Host smart-3ca40120-79e4-46c5-a5ae-a987503f1eb6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229661511 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.keymgr_sync_async_fault_cross.2229661511
Directory /workspace/41.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/42.keymgr_alert_test.918147985
Short name T447
Test name
Test status
Simulation time 16021393 ps
CPU time 0.78 seconds
Started Mar 26 03:30:02 PM PDT 24
Finished Mar 26 03:30:03 PM PDT 24
Peak memory 206320 kb
Host smart-a15ca9bd-441c-400d-8428-c5e3216609ce
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=918147985 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_alert_test.918147985
Directory /workspace/42.keymgr_alert_test/latest

Test location /workspace/coverage/default/42.keymgr_cfg_regwen.1914891736
Short name T157
Test name
Test status
Simulation time 596979420 ps
CPU time 5.84 seconds
Started Mar 26 03:29:57 PM PDT 24
Finished Mar 26 03:30:03 PM PDT 24
Peak memory 214652 kb
Host smart-6d91048e-1f9e-45c8-828c-674437f945cc
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1914891736 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_cfg_regwen.1914891736
Directory /workspace/42.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/42.keymgr_custom_cm.408669910
Short name T66
Test name
Test status
Simulation time 251507774 ps
CPU time 2.63 seconds
Started Mar 26 03:30:02 PM PDT 24
Finished Mar 26 03:30:05 PM PDT 24
Peak memory 215912 kb
Host smart-98e0d0f4-bbec-40ea-a64a-fc2ad984dbdf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=408669910 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_custom_cm.408669910
Directory /workspace/42.keymgr_custom_cm/latest

Test location /workspace/coverage/default/42.keymgr_direct_to_disabled.1228263765
Short name T715
Test name
Test status
Simulation time 148667272 ps
CPU time 1.95 seconds
Started Mar 26 03:29:56 PM PDT 24
Finished Mar 26 03:29:58 PM PDT 24
Peak memory 210024 kb
Host smart-09248a4e-a396-4f3a-89de-0db51bd5d763
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228263765 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_direct_to_disabled.1228263765
Directory /workspace/42.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/42.keymgr_hwsw_invalid_input.3391054728
Short name T443
Test name
Test status
Simulation time 345444669 ps
CPU time 6.67 seconds
Started Mar 26 03:30:06 PM PDT 24
Finished Mar 26 03:30:13 PM PDT 24
Peak memory 209924 kb
Host smart-1bb70d86-8bbd-4349-8dd5-25c059003dab
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3391054728 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_hwsw_invalid_input.3391054728
Directory /workspace/42.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/42.keymgr_kmac_rsp_err.2093490832
Short name T336
Test name
Test status
Simulation time 9375141324 ps
CPU time 35.55 seconds
Started Mar 26 03:29:57 PM PDT 24
Finished Mar 26 03:30:33 PM PDT 24
Peak memory 222848 kb
Host smart-611e963d-c9b7-4c58-89c8-74f45ed6dd00
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2093490832 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_kmac_rsp_err.2093490832
Directory /workspace/42.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/42.keymgr_lc_disable.1625558131
Short name T645
Test name
Test status
Simulation time 465899487 ps
CPU time 3.7 seconds
Started Mar 26 03:30:24 PM PDT 24
Finished Mar 26 03:30:28 PM PDT 24
Peak memory 209940 kb
Host smart-cdc7f8e8-c66e-43b9-b6ca-149c2d4022f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1625558131 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_lc_disable.1625558131
Directory /workspace/42.keymgr_lc_disable/latest

Test location /workspace/coverage/default/42.keymgr_random.2535100327
Short name T615
Test name
Test status
Simulation time 564761224 ps
CPU time 7.75 seconds
Started Mar 26 03:30:05 PM PDT 24
Finished Mar 26 03:30:13 PM PDT 24
Peak memory 208320 kb
Host smart-c4fca2c6-bd9b-4748-bf4c-8209ebbc6884
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2535100327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_random.2535100327
Directory /workspace/42.keymgr_random/latest

Test location /workspace/coverage/default/42.keymgr_sideload.635305668
Short name T667
Test name
Test status
Simulation time 230230823 ps
CPU time 3 seconds
Started Mar 26 03:30:00 PM PDT 24
Finished Mar 26 03:30:04 PM PDT 24
Peak memory 207052 kb
Host smart-90d14906-4de2-45ce-a680-32cb1190c894
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635305668 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload.635305668
Directory /workspace/42.keymgr_sideload/latest

Test location /workspace/coverage/default/42.keymgr_sideload_aes.3415244099
Short name T569
Test name
Test status
Simulation time 89286476 ps
CPU time 3.2 seconds
Started Mar 26 03:29:56 PM PDT 24
Finished Mar 26 03:29:59 PM PDT 24
Peak memory 206992 kb
Host smart-10336b32-9c77-4ead-a9ed-545304ae7a5d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3415244099 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_aes.3415244099
Directory /workspace/42.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/42.keymgr_sideload_kmac.3248398876
Short name T352
Test name
Test status
Simulation time 365805726 ps
CPU time 5.62 seconds
Started Mar 26 03:30:00 PM PDT 24
Finished Mar 26 03:30:06 PM PDT 24
Peak memory 208268 kb
Host smart-d9c99bd2-b0f5-421c-bdea-168b8aade573
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3248398876 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_kmac.3248398876
Directory /workspace/42.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/42.keymgr_sideload_otbn.3958738993
Short name T725
Test name
Test status
Simulation time 860894136 ps
CPU time 3.64 seconds
Started Mar 26 03:30:01 PM PDT 24
Finished Mar 26 03:30:05 PM PDT 24
Peak memory 207228 kb
Host smart-6cd2cfb9-ca5c-442d-add5-289b4554a022
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3958738993 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_otbn.3958738993
Directory /workspace/42.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/42.keymgr_sideload_protect.1790319578
Short name T111
Test name
Test status
Simulation time 520914601 ps
CPU time 4.03 seconds
Started Mar 26 03:29:58 PM PDT 24
Finished Mar 26 03:30:03 PM PDT 24
Peak memory 209904 kb
Host smart-e7f856a1-18d5-4294-85bb-105d3b5d284d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790319578 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sideload_protect.1790319578
Directory /workspace/42.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/42.keymgr_smoke.3744412181
Short name T829
Test name
Test status
Simulation time 160403731 ps
CPU time 2.61 seconds
Started Mar 26 03:30:01 PM PDT 24
Finished Mar 26 03:30:04 PM PDT 24
Peak memory 208900 kb
Host smart-9c36a83a-e8ca-46de-be9d-a5a4f0d1325a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3744412181 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_smoke.3744412181
Directory /workspace/42.keymgr_smoke/latest

Test location /workspace/coverage/default/42.keymgr_sync_async_fault_cross.2962224537
Short name T804
Test name
Test status
Simulation time 736574806 ps
CPU time 15.92 seconds
Started Mar 26 03:30:03 PM PDT 24
Finished Mar 26 03:30:19 PM PDT 24
Peak memory 211148 kb
Host smart-235927b3-72c8-4cb9-849c-b99098c554f3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2962224537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.keymgr_sync_async_fault_cross.2962224537
Directory /workspace/42.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/43.keymgr_alert_test.3155874829
Short name T614
Test name
Test status
Simulation time 55027607 ps
CPU time 0.86 seconds
Started Mar 26 03:30:12 PM PDT 24
Finished Mar 26 03:30:13 PM PDT 24
Peak memory 206320 kb
Host smart-4f9f3f16-5d25-48e8-9f31-2d2a6663e2f5
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3155874829 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_alert_test.3155874829
Directory /workspace/43.keymgr_alert_test/latest

Test location /workspace/coverage/default/43.keymgr_custom_cm.288562033
Short name T913
Test name
Test status
Simulation time 221878625 ps
CPU time 5.59 seconds
Started Mar 26 03:29:58 PM PDT 24
Finished Mar 26 03:30:05 PM PDT 24
Peak memory 217540 kb
Host smart-a2cb16aa-0c2e-44dd-8b2f-d8f7f6ba128a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=288562033 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_custom_cm.288562033
Directory /workspace/43.keymgr_custom_cm/latest

Test location /workspace/coverage/default/43.keymgr_direct_to_disabled.3799347951
Short name T892
Test name
Test status
Simulation time 160996186 ps
CPU time 5.81 seconds
Started Mar 26 03:30:03 PM PDT 24
Finished Mar 26 03:30:09 PM PDT 24
Peak memory 208564 kb
Host smart-58027f81-e209-4acc-9733-e8e3167d7b29
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3799347951 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_direct_to_disabled.3799347951
Directory /workspace/43.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/43.keymgr_hwsw_invalid_input.4155555216
Short name T388
Test name
Test status
Simulation time 223302432 ps
CPU time 4.16 seconds
Started Mar 26 03:30:04 PM PDT 24
Finished Mar 26 03:30:08 PM PDT 24
Peak memory 214620 kb
Host smart-fb874f7b-284f-400a-9ca5-a0f5aef15dfb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4155555216 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_hwsw_invalid_input.4155555216
Directory /workspace/43.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_kmac_rsp_err.3229523264
Short name T338
Test name
Test status
Simulation time 211902676 ps
CPU time 5.96 seconds
Started Mar 26 03:30:01 PM PDT 24
Finished Mar 26 03:30:08 PM PDT 24
Peak memory 222848 kb
Host smart-67d11a6e-c172-48c3-a1bf-515feae4ef96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3229523264 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_kmac_rsp_err.3229523264
Directory /workspace/43.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/43.keymgr_lc_disable.68408193
Short name T445
Test name
Test status
Simulation time 119669709 ps
CPU time 2.41 seconds
Started Mar 26 03:30:00 PM PDT 24
Finished Mar 26 03:30:03 PM PDT 24
Peak memory 209372 kb
Host smart-120697d7-ea18-40aa-9f54-c341a940d330
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=68408193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_lc_disable.68408193
Directory /workspace/43.keymgr_lc_disable/latest

Test location /workspace/coverage/default/43.keymgr_random.2157712969
Short name T356
Test name
Test status
Simulation time 410113398 ps
CPU time 8.25 seconds
Started Mar 26 03:30:01 PM PDT 24
Finished Mar 26 03:30:10 PM PDT 24
Peak memory 208680 kb
Host smart-3ed5e1d4-3f5b-42d3-8160-e31b255aa82e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2157712969 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_random.2157712969
Directory /workspace/43.keymgr_random/latest

Test location /workspace/coverage/default/43.keymgr_sideload.791657380
Short name T539
Test name
Test status
Simulation time 48697529 ps
CPU time 2.57 seconds
Started Mar 26 03:30:00 PM PDT 24
Finished Mar 26 03:30:03 PM PDT 24
Peak memory 207428 kb
Host smart-59a71569-1b76-4c10-af3b-2f72532b1fc3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=791657380 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload.791657380
Directory /workspace/43.keymgr_sideload/latest

Test location /workspace/coverage/default/43.keymgr_sideload_aes.157144747
Short name T510
Test name
Test status
Simulation time 216212896 ps
CPU time 4.09 seconds
Started Mar 26 03:30:12 PM PDT 24
Finished Mar 26 03:30:16 PM PDT 24
Peak memory 208924 kb
Host smart-b8325bcf-fcf6-4ee2-aa0c-85d6e25c0545
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157144747 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_aes.157144747
Directory /workspace/43.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/43.keymgr_sideload_kmac.2139640328
Short name T795
Test name
Test status
Simulation time 255858617 ps
CPU time 3.16 seconds
Started Mar 26 03:29:59 PM PDT 24
Finished Mar 26 03:30:03 PM PDT 24
Peak memory 207108 kb
Host smart-37cff6f5-eb89-4cca-919a-c7e7864378be
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2139640328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_kmac.2139640328
Directory /workspace/43.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/43.keymgr_sideload_otbn.796738147
Short name T904
Test name
Test status
Simulation time 158522110 ps
CPU time 3.97 seconds
Started Mar 26 03:30:04 PM PDT 24
Finished Mar 26 03:30:08 PM PDT 24
Peak memory 208868 kb
Host smart-a02ecd63-a70f-4952-9853-097bc6346d6f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=796738147 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_otbn.796738147
Directory /workspace/43.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/43.keymgr_sideload_protect.486959361
Short name T591
Test name
Test status
Simulation time 80729315 ps
CPU time 3.38 seconds
Started Mar 26 03:29:58 PM PDT 24
Finished Mar 26 03:30:02 PM PDT 24
Peak memory 207824 kb
Host smart-acd57443-f88d-4fda-9fd7-6c405af9fc49
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=486959361 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sideload_protect.486959361
Directory /workspace/43.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/43.keymgr_smoke.3894943200
Short name T873
Test name
Test status
Simulation time 118110525 ps
CPU time 2.95 seconds
Started Mar 26 03:30:01 PM PDT 24
Finished Mar 26 03:30:05 PM PDT 24
Peak memory 207120 kb
Host smart-2c3d060a-cc60-4f38-9292-f713ecdcccbc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3894943200 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_smoke.3894943200
Directory /workspace/43.keymgr_smoke/latest

Test location /workspace/coverage/default/43.keymgr_stress_all.1255370821
Short name T349
Test name
Test status
Simulation time 1601253567 ps
CPU time 57.33 seconds
Started Mar 26 03:30:04 PM PDT 24
Finished Mar 26 03:31:01 PM PDT 24
Peak memory 222928 kb
Host smart-d2ecd9a4-e179-481b-8a33-4f0fb8ee3426
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1255370821 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all.1255370821
Directory /workspace/43.keymgr_stress_all/latest

Test location /workspace/coverage/default/43.keymgr_stress_all_with_rand_reset.2993717226
Short name T861
Test name
Test status
Simulation time 1013694662 ps
CPU time 9.04 seconds
Started Mar 26 03:29:56 PM PDT 24
Finished Mar 26 03:30:06 PM PDT 24
Peak memory 222916 kb
Host smart-b6d593a7-f298-48bd-a281-0f73932dc137
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993717226 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 43.keymgr_stress_all_with_rand_reset.2993717226
Directory /workspace/43.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.keymgr_sw_invalid_input.98399162
Short name T642
Test name
Test status
Simulation time 1777897445 ps
CPU time 61.27 seconds
Started Mar 26 03:30:04 PM PDT 24
Finished Mar 26 03:31:05 PM PDT 24
Peak memory 214668 kb
Host smart-abb64280-71af-4d10-b50c-02e91ad24b1f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=98399162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sw_invalid_input.98399162
Directory /workspace/43.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/43.keymgr_sync_async_fault_cross.1629391968
Short name T666
Test name
Test status
Simulation time 239267118 ps
CPU time 2.6 seconds
Started Mar 26 03:29:59 PM PDT 24
Finished Mar 26 03:30:02 PM PDT 24
Peak memory 210080 kb
Host smart-3754024f-a79f-42d6-88cd-8a148672d6ed
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1629391968 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.keymgr_sync_async_fault_cross.1629391968
Directory /workspace/43.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/44.keymgr_alert_test.658019427
Short name T456
Test name
Test status
Simulation time 43510310 ps
CPU time 0.86 seconds
Started Mar 26 03:29:59 PM PDT 24
Finished Mar 26 03:30:01 PM PDT 24
Peak memory 206212 kb
Host smart-c1365ceb-ab0a-4510-952e-cf01a2b179e9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=658019427 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_alert_test.658019427
Directory /workspace/44.keymgr_alert_test/latest

Test location /workspace/coverage/default/44.keymgr_custom_cm.272757150
Short name T32
Test name
Test status
Simulation time 235258591 ps
CPU time 2.86 seconds
Started Mar 26 03:29:57 PM PDT 24
Finished Mar 26 03:30:01 PM PDT 24
Peak memory 208164 kb
Host smart-7ef7ab5f-662c-414d-a83e-dd3261e68807
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=272757150 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_custom_cm.272757150
Directory /workspace/44.keymgr_custom_cm/latest

Test location /workspace/coverage/default/44.keymgr_direct_to_disabled.1115256517
Short name T263
Test name
Test status
Simulation time 57940800 ps
CPU time 2.73 seconds
Started Mar 26 03:29:54 PM PDT 24
Finished Mar 26 03:29:58 PM PDT 24
Peak memory 209112 kb
Host smart-86f5b136-a433-4aaa-8ae0-b8166c097781
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1115256517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_direct_to_disabled.1115256517
Directory /workspace/44.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/44.keymgr_hwsw_invalid_input.2905202869
Short name T738
Test name
Test status
Simulation time 15713486725 ps
CPU time 42.35 seconds
Started Mar 26 03:30:18 PM PDT 24
Finished Mar 26 03:31:00 PM PDT 24
Peak memory 214784 kb
Host smart-0d7bb281-1a99-456c-aa81-c17fb47a1c54
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2905202869 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_hwsw_invalid_input.2905202869
Directory /workspace/44.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_kmac_rsp_err.3566270920
Short name T245
Test name
Test status
Simulation time 397263449 ps
CPU time 3.85 seconds
Started Mar 26 03:29:58 PM PDT 24
Finished Mar 26 03:30:02 PM PDT 24
Peak memory 210964 kb
Host smart-c4f5a517-9893-48d1-9888-76e9ae84c7eb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3566270920 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_kmac_rsp_err.3566270920
Directory /workspace/44.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/44.keymgr_lc_disable.677079152
Short name T542
Test name
Test status
Simulation time 1150834365 ps
CPU time 4.07 seconds
Started Mar 26 03:30:05 PM PDT 24
Finished Mar 26 03:30:09 PM PDT 24
Peak memory 220272 kb
Host smart-aa1aa5f0-820e-46b5-bc9f-34869b95b499
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=677079152 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_lc_disable.677079152
Directory /workspace/44.keymgr_lc_disable/latest

Test location /workspace/coverage/default/44.keymgr_random.1250127074
Short name T1
Test name
Test status
Simulation time 477467928 ps
CPU time 3.64 seconds
Started Mar 26 03:30:04 PM PDT 24
Finished Mar 26 03:30:08 PM PDT 24
Peak memory 214648 kb
Host smart-4441e0c1-35cf-48d2-b1f9-2071bcb725db
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250127074 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_random.1250127074
Directory /workspace/44.keymgr_random/latest

Test location /workspace/coverage/default/44.keymgr_sideload.2984880078
Short name T489
Test name
Test status
Simulation time 97145159 ps
CPU time 3.83 seconds
Started Mar 26 03:29:59 PM PDT 24
Finished Mar 26 03:30:04 PM PDT 24
Peak memory 208724 kb
Host smart-b238663f-44e9-4f69-81b1-ad5876da321d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2984880078 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload.2984880078
Directory /workspace/44.keymgr_sideload/latest

Test location /workspace/coverage/default/44.keymgr_sideload_aes.2629861185
Short name T740
Test name
Test status
Simulation time 65021460 ps
CPU time 3.19 seconds
Started Mar 26 03:30:06 PM PDT 24
Finished Mar 26 03:30:09 PM PDT 24
Peak memory 207268 kb
Host smart-44ff8327-7369-463c-b515-4f53b1afecc8
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2629861185 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_aes.2629861185
Directory /workspace/44.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/44.keymgr_sideload_kmac.783859053
Short name T136
Test name
Test status
Simulation time 840380398 ps
CPU time 3.4 seconds
Started Mar 26 03:30:00 PM PDT 24
Finished Mar 26 03:30:04 PM PDT 24
Peak memory 207044 kb
Host smart-dccbeea1-667e-42ee-aa70-ea4315d86029
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=783859053 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_kmac.783859053
Directory /workspace/44.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/44.keymgr_sideload_otbn.491377450
Short name T511
Test name
Test status
Simulation time 88638013 ps
CPU time 3.97 seconds
Started Mar 26 03:29:56 PM PDT 24
Finished Mar 26 03:30:00 PM PDT 24
Peak memory 208724 kb
Host smart-b5730a07-8f50-4634-b58d-e8afe8cebcd0
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491377450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_otbn.491377450
Directory /workspace/44.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/44.keymgr_sideload_protect.1943077047
Short name T662
Test name
Test status
Simulation time 1884657492 ps
CPU time 10.62 seconds
Started Mar 26 03:29:53 PM PDT 24
Finished Mar 26 03:30:04 PM PDT 24
Peak memory 214608 kb
Host smart-69af4338-13f9-4623-9181-07071bc8996b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1943077047 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sideload_protect.1943077047
Directory /workspace/44.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/44.keymgr_smoke.2650158406
Short name T132
Test name
Test status
Simulation time 435196751 ps
CPU time 6 seconds
Started Mar 26 03:30:02 PM PDT 24
Finished Mar 26 03:30:09 PM PDT 24
Peak memory 207032 kb
Host smart-0883036b-d4f4-456f-9fe1-ae48bcf4e0e2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650158406 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_smoke.2650158406
Directory /workspace/44.keymgr_smoke/latest

Test location /workspace/coverage/default/44.keymgr_sw_invalid_input.764858135
Short name T702
Test name
Test status
Simulation time 763227154 ps
CPU time 9.96 seconds
Started Mar 26 03:30:05 PM PDT 24
Finished Mar 26 03:30:15 PM PDT 24
Peak memory 214676 kb
Host smart-6a198f98-7213-41a0-a599-a64938acb4e7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=764858135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sw_invalid_input.764858135
Directory /workspace/44.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/44.keymgr_sync_async_fault_cross.1648118375
Short name T52
Test name
Test status
Simulation time 327007799 ps
CPU time 2.56 seconds
Started Mar 26 03:30:05 PM PDT 24
Finished Mar 26 03:30:08 PM PDT 24
Peak memory 210416 kb
Host smart-f6572cbc-241b-4f55-bce8-95d60e87c29c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648118375 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.keymgr_sync_async_fault_cross.1648118375
Directory /workspace/44.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/45.keymgr_alert_test.2791671809
Short name T101
Test name
Test status
Simulation time 30065805 ps
CPU time 0.85 seconds
Started Mar 26 03:29:51 PM PDT 24
Finished Mar 26 03:29:53 PM PDT 24
Peak memory 206316 kb
Host smart-bca4d8f2-d11c-4deb-92b4-fb19add4845d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791671809 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_alert_test.2791671809
Directory /workspace/45.keymgr_alert_test/latest

Test location /workspace/coverage/default/45.keymgr_custom_cm.353313348
Short name T19
Test name
Test status
Simulation time 64621162 ps
CPU time 3.08 seconds
Started Mar 26 03:29:57 PM PDT 24
Finished Mar 26 03:30:00 PM PDT 24
Peak memory 210564 kb
Host smart-38c7fc00-526d-4d1f-8e33-9da0e9c51fb3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=353313348 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_custom_cm.353313348
Directory /workspace/45.keymgr_custom_cm/latest

Test location /workspace/coverage/default/45.keymgr_direct_to_disabled.4011258755
Short name T560
Test name
Test status
Simulation time 84617252 ps
CPU time 2.66 seconds
Started Mar 26 03:30:03 PM PDT 24
Finished Mar 26 03:30:06 PM PDT 24
Peak memory 209312 kb
Host smart-55d6da39-b8c6-4a8e-9bd5-da8a1b1dc3d2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4011258755 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_direct_to_disabled.4011258755
Directory /workspace/45.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/45.keymgr_hwsw_invalid_input.4140169485
Short name T328
Test name
Test status
Simulation time 293500570 ps
CPU time 3.73 seconds
Started Mar 26 03:30:03 PM PDT 24
Finished Mar 26 03:30:07 PM PDT 24
Peak memory 209640 kb
Host smart-6a2f88d8-5868-4ddf-b0ed-ab2c386c7c9b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4140169485 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_hwsw_invalid_input.4140169485
Directory /workspace/45.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/45.keymgr_lc_disable.3584458012
Short name T222
Test name
Test status
Simulation time 595439593 ps
CPU time 15.37 seconds
Started Mar 26 03:30:02 PM PDT 24
Finished Mar 26 03:30:18 PM PDT 24
Peak memory 210420 kb
Host smart-4b6e6d2d-d89a-41d4-b678-33e1166417c5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3584458012 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_lc_disable.3584458012
Directory /workspace/45.keymgr_lc_disable/latest

Test location /workspace/coverage/default/45.keymgr_random.2361778512
Short name T290
Test name
Test status
Simulation time 17119475816 ps
CPU time 66.61 seconds
Started Mar 26 03:29:59 PM PDT 24
Finished Mar 26 03:31:07 PM PDT 24
Peak memory 223024 kb
Host smart-8b77f9d9-a62e-4e56-ac96-1af3ef46a138
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2361778512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_random.2361778512
Directory /workspace/45.keymgr_random/latest

Test location /workspace/coverage/default/45.keymgr_sideload.2391671528
Short name T273
Test name
Test status
Simulation time 405188466 ps
CPU time 3.22 seconds
Started Mar 26 03:30:00 PM PDT 24
Finished Mar 26 03:30:04 PM PDT 24
Peak memory 207132 kb
Host smart-534f4993-bb19-4dfe-9570-6c67d3178a8a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2391671528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload.2391671528
Directory /workspace/45.keymgr_sideload/latest

Test location /workspace/coverage/default/45.keymgr_sideload_aes.1924280006
Short name T807
Test name
Test status
Simulation time 60073637 ps
CPU time 3.08 seconds
Started Mar 26 03:29:57 PM PDT 24
Finished Mar 26 03:30:01 PM PDT 24
Peak memory 209080 kb
Host smart-57ba8d83-072f-4853-bd55-20354f44ab1d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1924280006 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_aes.1924280006
Directory /workspace/45.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/45.keymgr_sideload_kmac.3514619820
Short name T464
Test name
Test status
Simulation time 182859266 ps
CPU time 5.43 seconds
Started Mar 26 03:30:03 PM PDT 24
Finished Mar 26 03:30:09 PM PDT 24
Peak memory 208008 kb
Host smart-52d53ba5-3c50-4577-9559-f5b35aaa6151
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3514619820 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_kmac.3514619820
Directory /workspace/45.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/45.keymgr_sideload_otbn.3864445576
Short name T818
Test name
Test status
Simulation time 190741316 ps
CPU time 2.76 seconds
Started Mar 26 03:30:02 PM PDT 24
Finished Mar 26 03:30:05 PM PDT 24
Peak memory 207244 kb
Host smart-60a62c70-385f-421d-89fd-a71e8560f8bd
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3864445576 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_otbn.3864445576
Directory /workspace/45.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/45.keymgr_sideload_protect.2346764341
Short name T86
Test name
Test status
Simulation time 214530354 ps
CPU time 3.28 seconds
Started Mar 26 03:30:11 PM PDT 24
Finished Mar 26 03:30:15 PM PDT 24
Peak memory 208396 kb
Host smart-8416cff8-9c4b-4056-843d-368ed819f15e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2346764341 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sideload_protect.2346764341
Directory /workspace/45.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/45.keymgr_smoke.3588974203
Short name T131
Test name
Test status
Simulation time 59447126 ps
CPU time 2.27 seconds
Started Mar 26 03:30:15 PM PDT 24
Finished Mar 26 03:30:18 PM PDT 24
Peak memory 208820 kb
Host smart-d873def3-574b-4c6a-a618-d2c5f1f198bf
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3588974203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_smoke.3588974203
Directory /workspace/45.keymgr_smoke/latest

Test location /workspace/coverage/default/45.keymgr_sw_invalid_input.3818167814
Short name T608
Test name
Test status
Simulation time 2621732795 ps
CPU time 87.38 seconds
Started Mar 26 03:30:03 PM PDT 24
Finished Mar 26 03:31:31 PM PDT 24
Peak memory 220852 kb
Host smart-6bdc493a-3a83-4811-9901-b9e34ff1fa6f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3818167814 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.keymgr_sw_invalid_input.3818167814
Directory /workspace/45.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_alert_test.2478844987
Short name T762
Test name
Test status
Simulation time 38212982 ps
CPU time 0.83 seconds
Started Mar 26 03:30:03 PM PDT 24
Finished Mar 26 03:30:04 PM PDT 24
Peak memory 206336 kb
Host smart-3c9f28fe-53f6-444f-89e5-aaddd0b0d291
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478844987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_alert_test.2478844987
Directory /workspace/46.keymgr_alert_test/latest

Test location /workspace/coverage/default/46.keymgr_direct_to_disabled.3717861337
Short name T302
Test name
Test status
Simulation time 233005958 ps
CPU time 3.39 seconds
Started Mar 26 03:29:59 PM PDT 24
Finished Mar 26 03:30:03 PM PDT 24
Peak memory 214688 kb
Host smart-12dd15c2-41b1-4922-955f-3ec0de399a6c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3717861337 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_direct_to_disabled.3717861337
Directory /workspace/46.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/46.keymgr_hwsw_invalid_input.2662848696
Short name T361
Test name
Test status
Simulation time 275554576 ps
CPU time 8.95 seconds
Started Mar 26 03:30:12 PM PDT 24
Finished Mar 26 03:30:21 PM PDT 24
Peak memory 214680 kb
Host smart-853c69f8-89a5-460e-9687-90e987b3e428
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662848696 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_hwsw_invalid_input.2662848696
Directory /workspace/46.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_kmac_rsp_err.903191473
Short name T763
Test name
Test status
Simulation time 56737547 ps
CPU time 2.49 seconds
Started Mar 26 03:30:11 PM PDT 24
Finished Mar 26 03:30:14 PM PDT 24
Peak memory 211036 kb
Host smart-ad22ecaa-8fe0-4cca-811a-ccf8bb953cd8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=903191473 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_kmac_rsp_err.903191473
Directory /workspace/46.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/46.keymgr_lc_disable.4221852862
Short name T879
Test name
Test status
Simulation time 85538193 ps
CPU time 4.25 seconds
Started Mar 26 03:30:05 PM PDT 24
Finished Mar 26 03:30:09 PM PDT 24
Peak memory 210716 kb
Host smart-5c761be1-2993-4dc7-a875-22e054c3c1ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4221852862 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_lc_disable.4221852862
Directory /workspace/46.keymgr_lc_disable/latest

Test location /workspace/coverage/default/46.keymgr_random.3172431981
Short name T240
Test name
Test status
Simulation time 181413514 ps
CPU time 2.37 seconds
Started Mar 26 03:29:58 PM PDT 24
Finished Mar 26 03:30:02 PM PDT 24
Peak memory 208692 kb
Host smart-78b99170-6985-4bd1-a059-3e56cf42df7e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3172431981 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_random.3172431981
Directory /workspace/46.keymgr_random/latest

Test location /workspace/coverage/default/46.keymgr_sideload.783748327
Short name T907
Test name
Test status
Simulation time 128601489 ps
CPU time 2.42 seconds
Started Mar 26 03:29:59 PM PDT 24
Finished Mar 26 03:30:03 PM PDT 24
Peak memory 207316 kb
Host smart-a8ac08c0-137f-45fa-af65-4e319c4ea4b4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=783748327 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload.783748327
Directory /workspace/46.keymgr_sideload/latest

Test location /workspace/coverage/default/46.keymgr_sideload_aes.645752586
Short name T708
Test name
Test status
Simulation time 65647276 ps
CPU time 3.04 seconds
Started Mar 26 03:29:58 PM PDT 24
Finished Mar 26 03:30:02 PM PDT 24
Peak memory 207176 kb
Host smart-d3000822-f463-4a62-a21b-824862b5d42c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=645752586 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_aes.645752586
Directory /workspace/46.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/46.keymgr_sideload_kmac.1579188867
Short name T239
Test name
Test status
Simulation time 359364760 ps
CPU time 3.36 seconds
Started Mar 26 03:29:56 PM PDT 24
Finished Mar 26 03:30:00 PM PDT 24
Peak memory 208744 kb
Host smart-83169e3c-ae87-459e-a024-09483ee9fb4c
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1579188867 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_kmac.1579188867
Directory /workspace/46.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/46.keymgr_sideload_otbn.1464237669
Short name T862
Test name
Test status
Simulation time 137062304 ps
CPU time 2.91 seconds
Started Mar 26 03:29:59 PM PDT 24
Finished Mar 26 03:30:03 PM PDT 24
Peak memory 209016 kb
Host smart-d44280c5-a316-415b-bc08-b97eed53937f
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464237669 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_otbn.1464237669
Directory /workspace/46.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/46.keymgr_sideload_protect.459038161
Short name T857
Test name
Test status
Simulation time 525033203 ps
CPU time 5.58 seconds
Started Mar 26 03:30:24 PM PDT 24
Finished Mar 26 03:30:30 PM PDT 24
Peak memory 207492 kb
Host smart-c4ddb599-4551-4916-8f0a-c0952d707ade
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459038161 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sideload_protect.459038161
Directory /workspace/46.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/46.keymgr_smoke.313205312
Short name T902
Test name
Test status
Simulation time 85351716 ps
CPU time 2.83 seconds
Started Mar 26 03:30:10 PM PDT 24
Finished Mar 26 03:30:19 PM PDT 24
Peak memory 206960 kb
Host smart-d8dc06c5-6e7e-4529-8988-68ea8d2cad15
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=313205312 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_smoke.313205312
Directory /workspace/46.keymgr_smoke/latest

Test location /workspace/coverage/default/46.keymgr_stress_all.409916450
Short name T888
Test name
Test status
Simulation time 1335131429 ps
CPU time 34.63 seconds
Started Mar 26 03:30:03 PM PDT 24
Finished Mar 26 03:30:38 PM PDT 24
Peak memory 216948 kb
Host smart-32835c0b-10a0-4933-98ca-33f551915f9c
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=409916450 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_all
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_stress_all.409916450
Directory /workspace/46.keymgr_stress_all/latest

Test location /workspace/coverage/default/46.keymgr_sw_invalid_input.2542235873
Short name T882
Test name
Test status
Simulation time 134122572 ps
CPU time 2.9 seconds
Started Mar 26 03:30:05 PM PDT 24
Finished Mar 26 03:30:08 PM PDT 24
Peak memory 208344 kb
Host smart-2610c3e3-4893-4494-beb7-f252e58458d1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2542235873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sw_invalid_input.2542235873
Directory /workspace/46.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/46.keymgr_sync_async_fault_cross.725906846
Short name T170
Test name
Test status
Simulation time 594046098 ps
CPU time 7.13 seconds
Started Mar 26 03:29:59 PM PDT 24
Finished Mar 26 03:30:07 PM PDT 24
Peak memory 211316 kb
Host smart-7e9990a1-d1d2-44b5-a11a-40fe79f278cd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=725906846 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.keymgr_sync_async_fault_cross.725906846
Directory /workspace/46.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/47.keymgr_alert_test.3384842287
Short name T610
Test name
Test status
Simulation time 35643098 ps
CPU time 0.73 seconds
Started Mar 26 03:30:04 PM PDT 24
Finished Mar 26 03:30:05 PM PDT 24
Peak memory 206328 kb
Host smart-771f3013-ed3c-4335-abd6-480a7c385149
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384842287 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_alert_test.3384842287
Directory /workspace/47.keymgr_alert_test/latest

Test location /workspace/coverage/default/47.keymgr_cfg_regwen.2017112080
Short name T348
Test name
Test status
Simulation time 45443521 ps
CPU time 3.37 seconds
Started Mar 26 03:30:05 PM PDT 24
Finished Mar 26 03:30:08 PM PDT 24
Peak memory 215816 kb
Host smart-7ca3a992-2011-492b-9f75-5fb66b8854f5
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=2017112080 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_cfg_regwen.2017112080
Directory /workspace/47.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/47.keymgr_direct_to_disabled.2440696724
Short name T449
Test name
Test status
Simulation time 888638034 ps
CPU time 2.55 seconds
Started Mar 26 03:30:09 PM PDT 24
Finished Mar 26 03:30:11 PM PDT 24
Peak memory 209696 kb
Host smart-0b653f29-2c7b-4dac-8b88-aacb9d11ca04
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2440696724 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_direct_to_disabled.2440696724
Directory /workspace/47.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/47.keymgr_hwsw_invalid_input.64427050
Short name T81
Test name
Test status
Simulation time 225731771 ps
CPU time 5.74 seconds
Started Mar 26 03:30:06 PM PDT 24
Finished Mar 26 03:30:12 PM PDT 24
Peak memory 209804 kb
Host smart-71e37792-d85b-46b0-bc09-9c8ac17a2087
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=64427050 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_hwsw_invalid_input.64427050
Directory /workspace/47.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_kmac_rsp_err.2023575039
Short name T279
Test name
Test status
Simulation time 147256083 ps
CPU time 5.93 seconds
Started Mar 26 03:30:20 PM PDT 24
Finished Mar 26 03:30:26 PM PDT 24
Peak memory 214584 kb
Host smart-a150e687-984c-4fd9-a60f-1b80d2f127f7
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023575039 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_kmac_rsp_err.2023575039
Directory /workspace/47.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/47.keymgr_lc_disable.4101579349
Short name T687
Test name
Test status
Simulation time 119403212 ps
CPU time 5.18 seconds
Started Mar 26 03:30:02 PM PDT 24
Finished Mar 26 03:30:08 PM PDT 24
Peak memory 209260 kb
Host smart-39acd5b9-88e3-4fda-a2f0-40dbc1b10def
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4101579349 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_lc_disable.4101579349
Directory /workspace/47.keymgr_lc_disable/latest

Test location /workspace/coverage/default/47.keymgr_random.3950425512
Short name T255
Test name
Test status
Simulation time 321142670 ps
CPU time 4.11 seconds
Started Mar 26 03:30:05 PM PDT 24
Finished Mar 26 03:30:09 PM PDT 24
Peak memory 208120 kb
Host smart-eb47eef8-6f86-48c2-bc66-1ef6ff5f3145
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950425512 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_random.3950425512
Directory /workspace/47.keymgr_random/latest

Test location /workspace/coverage/default/47.keymgr_sideload.1071731420
Short name T362
Test name
Test status
Simulation time 88536931 ps
CPU time 1.95 seconds
Started Mar 26 03:30:07 PM PDT 24
Finished Mar 26 03:30:09 PM PDT 24
Peak memory 207792 kb
Host smart-56f2839a-cae6-4d43-aecc-ad8c27488c96
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071731420 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload.1071731420
Directory /workspace/47.keymgr_sideload/latest

Test location /workspace/coverage/default/47.keymgr_sideload_aes.3979236168
Short name T429
Test name
Test status
Simulation time 129463023 ps
CPU time 4.62 seconds
Started Mar 26 03:30:04 PM PDT 24
Finished Mar 26 03:30:09 PM PDT 24
Peak memory 207136 kb
Host smart-f9741e05-90c9-4f02-a684-acf7e567bb3d
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3979236168 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_aes.3979236168
Directory /workspace/47.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/47.keymgr_sideload_kmac.3350804285
Short name T404
Test name
Test status
Simulation time 77829300 ps
CPU time 2.28 seconds
Started Mar 26 03:30:03 PM PDT 24
Finished Mar 26 03:30:06 PM PDT 24
Peak memory 206876 kb
Host smart-01cfa1bd-78c5-41e2-9dae-2e4b4049f160
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3350804285 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_kmac.3350804285
Directory /workspace/47.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/47.keymgr_sideload_otbn.840770102
Short name T576
Test name
Test status
Simulation time 2121971276 ps
CPU time 26.14 seconds
Started Mar 26 03:29:53 PM PDT 24
Finished Mar 26 03:30:19 PM PDT 24
Peak memory 208352 kb
Host smart-61f14d77-e535-46df-9b02-7a822d2dea63
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=840770102 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_otbn.840770102
Directory /workspace/47.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/47.keymgr_sideload_protect.412549944
Short name T896
Test name
Test status
Simulation time 328978558 ps
CPU time 4.19 seconds
Started Mar 26 03:30:06 PM PDT 24
Finished Mar 26 03:30:11 PM PDT 24
Peak memory 210196 kb
Host smart-805aad58-efbd-42e7-b129-4fcbebbe6093
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412549944 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sideload_protect.412549944
Directory /workspace/47.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/47.keymgr_smoke.1578475626
Short name T709
Test name
Test status
Simulation time 343112220 ps
CPU time 2.85 seconds
Started Mar 26 03:30:07 PM PDT 24
Finished Mar 26 03:30:10 PM PDT 24
Peak memory 207044 kb
Host smart-a5d3ed83-f8fd-4d2b-8cfd-2bdab2c9207f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1578475626 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_smoke.1578475626
Directory /workspace/47.keymgr_smoke/latest

Test location /workspace/coverage/default/47.keymgr_sw_invalid_input.3424928596
Short name T277
Test name
Test status
Simulation time 367737364 ps
CPU time 9.82 seconds
Started Mar 26 03:30:04 PM PDT 24
Finished Mar 26 03:30:14 PM PDT 24
Peak memory 218800 kb
Host smart-5a351d4d-f1f3-4ade-89af-db43111a0aea
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3424928596 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sw_invalid_input.3424928596
Directory /workspace/47.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/47.keymgr_sync_async_fault_cross.103214438
Short name T743
Test name
Test status
Simulation time 47114470 ps
CPU time 1.68 seconds
Started Mar 26 03:30:11 PM PDT 24
Finished Mar 26 03:30:13 PM PDT 24
Peak memory 210324 kb
Host smart-fcfc3e0f-d589-434e-a688-13ddcc15e9f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=103214438 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.keymgr_sync_async_fault_cross.103214438
Directory /workspace/47.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/48.keymgr_alert_test.2189081909
Short name T778
Test name
Test status
Simulation time 10635301 ps
CPU time 0.72 seconds
Started Mar 26 03:30:16 PM PDT 24
Finished Mar 26 03:30:17 PM PDT 24
Peak memory 206336 kb
Host smart-c3194725-1157-41d5-9b30-5c6d8ca88fa9
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2189081909 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_alert_test.2189081909
Directory /workspace/48.keymgr_alert_test/latest

Test location /workspace/coverage/default/48.keymgr_custom_cm.1967043528
Short name T214
Test name
Test status
Simulation time 222207083 ps
CPU time 6.4 seconds
Started Mar 26 03:30:26 PM PDT 24
Finished Mar 26 03:30:33 PM PDT 24
Peak memory 210388 kb
Host smart-e23df692-e33d-4721-9a9e-60bf0e2262ef
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1967043528 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_custom_cm.1967043528
Directory /workspace/48.keymgr_custom_cm/latest

Test location /workspace/coverage/default/48.keymgr_direct_to_disabled.1206601931
Short name T67
Test name
Test status
Simulation time 147984918 ps
CPU time 3.36 seconds
Started Mar 26 03:30:09 PM PDT 24
Finished Mar 26 03:30:12 PM PDT 24
Peak memory 210044 kb
Host smart-aeb3be66-91b8-4334-aa22-52bf7f198cbd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1206601931 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_direct_to_disabled.1206601931
Directory /workspace/48.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/48.keymgr_hwsw_invalid_input.965395281
Short name T825
Test name
Test status
Simulation time 225604634 ps
CPU time 6.16 seconds
Started Mar 26 03:30:19 PM PDT 24
Finished Mar 26 03:30:25 PM PDT 24
Peak memory 214688 kb
Host smart-b936bdf7-7ca2-4988-8193-6c46a14eccc9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=965395281 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_hwsw_invalid_input.965395281
Directory /workspace/48.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_lc_disable.4017031557
Short name T649
Test name
Test status
Simulation time 152144469 ps
CPU time 2.02 seconds
Started Mar 26 03:30:24 PM PDT 24
Finished Mar 26 03:30:26 PM PDT 24
Peak memory 220160 kb
Host smart-b169c62c-4198-4a05-ade8-f93eb65ffd1b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4017031557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_lc_disable.4017031557
Directory /workspace/48.keymgr_lc_disable/latest

Test location /workspace/coverage/default/48.keymgr_random.3672820428
Short name T819
Test name
Test status
Simulation time 47200326 ps
CPU time 3.22 seconds
Started Mar 26 03:30:23 PM PDT 24
Finished Mar 26 03:30:26 PM PDT 24
Peak memory 208168 kb
Host smart-6f76f72a-cb91-404a-a74f-9ef5880bdbe8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3672820428 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_random.3672820428
Directory /workspace/48.keymgr_random/latest

Test location /workspace/coverage/default/48.keymgr_sideload.1089221961
Short name T752
Test name
Test status
Simulation time 358032130 ps
CPU time 3.76 seconds
Started Mar 26 03:30:33 PM PDT 24
Finished Mar 26 03:30:37 PM PDT 24
Peak memory 208980 kb
Host smart-52afdcfe-4a07-4f9b-9a72-a3af119f06dc
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1089221961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload.1089221961
Directory /workspace/48.keymgr_sideload/latest

Test location /workspace/coverage/default/48.keymgr_sideload_aes.3307671101
Short name T656
Test name
Test status
Simulation time 2298270840 ps
CPU time 21.82 seconds
Started Mar 26 03:30:05 PM PDT 24
Finished Mar 26 03:30:27 PM PDT 24
Peak memory 209588 kb
Host smart-57ae2686-1016-445c-9798-18e21499e285
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307671101 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_aes.3307671101
Directory /workspace/48.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/48.keymgr_sideload_kmac.345078242
Short name T514
Test name
Test status
Simulation time 843020597 ps
CPU time 7.44 seconds
Started Mar 26 03:30:04 PM PDT 24
Finished Mar 26 03:30:11 PM PDT 24
Peak memory 209032 kb
Host smart-71066bd0-869b-4f0a-94db-a8f963e4e961
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=345078242 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_kmac.345078242
Directory /workspace/48.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/48.keymgr_sideload_otbn.823513366
Short name T640
Test name
Test status
Simulation time 113154581 ps
CPU time 3.66 seconds
Started Mar 26 03:30:05 PM PDT 24
Finished Mar 26 03:30:09 PM PDT 24
Peak memory 207028 kb
Host smart-b280634a-ca6c-4e28-becb-9543a4468e1c
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=823513366 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_otbn.823513366
Directory /workspace/48.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/48.keymgr_sideload_protect.354732283
Short name T470
Test name
Test status
Simulation time 266893325 ps
CPU time 2.89 seconds
Started Mar 26 03:30:07 PM PDT 24
Finished Mar 26 03:30:10 PM PDT 24
Peak memory 207660 kb
Host smart-f949a81d-dc98-4741-833c-2510a4a3930f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=354732283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sideload_protect.354732283
Directory /workspace/48.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/48.keymgr_smoke.2731306416
Short name T475
Test name
Test status
Simulation time 553079299 ps
CPU time 3.08 seconds
Started Mar 26 03:30:04 PM PDT 24
Finished Mar 26 03:30:07 PM PDT 24
Peak memory 208852 kb
Host smart-5123a3f1-50e0-4d35-8e7b-64034f6bf716
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731306416 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_smoke.2731306416
Directory /workspace/48.keymgr_smoke/latest

Test location /workspace/coverage/default/48.keymgr_stress_all.1027464483
Short name T580
Test name
Test status
Simulation time 10810016757 ps
CPU time 109.4 seconds
Started Mar 26 03:30:09 PM PDT 24
Finished Mar 26 03:31:59 PM PDT 24
Peak memory 222868 kb
Host smart-ffc59082-682a-4e45-b50e-9dc89933a7ee
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1027464483 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all.1027464483
Directory /workspace/48.keymgr_stress_all/latest

Test location /workspace/coverage/default/48.keymgr_stress_all_with_rand_reset.1803904535
Short name T910
Test name
Test status
Simulation time 570381882 ps
CPU time 16.21 seconds
Started Mar 26 03:30:13 PM PDT 24
Finished Mar 26 03:30:29 PM PDT 24
Peak memory 220732 kb
Host smart-fca46304-f84c-4d61-a624-787f61368a91
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1803904535 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 48.keymgr_stress_all_with_rand_reset.1803904535
Directory /workspace/48.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.keymgr_sw_invalid_input.1067988304
Short name T855
Test name
Test status
Simulation time 1973144803 ps
CPU time 26.18 seconds
Started Mar 26 03:30:08 PM PDT 24
Finished Mar 26 03:30:34 PM PDT 24
Peak memory 209188 kb
Host smart-5f06b009-faf5-4f1b-9fad-cfc7161b3608
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1067988304 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sw_invalid_input.1067988304
Directory /workspace/48.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/48.keymgr_sync_async_fault_cross.3591239791
Short name T676
Test name
Test status
Simulation time 50171690 ps
CPU time 1.96 seconds
Started Mar 26 03:30:04 PM PDT 24
Finished Mar 26 03:30:06 PM PDT 24
Peak memory 210068 kb
Host smart-c180117f-d6c7-4eff-9d67-e7f171af2a24
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591239791 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.keymgr_sync_async_fault_cross.3591239791
Directory /workspace/48.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/49.keymgr_alert_test.3113817378
Short name T586
Test name
Test status
Simulation time 42635133 ps
CPU time 0.82 seconds
Started Mar 26 03:30:07 PM PDT 24
Finished Mar 26 03:30:08 PM PDT 24
Peak memory 206284 kb
Host smart-54bfac26-7aec-452d-b54e-ac0e6c3d8a4d
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3113817378 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_alert_test.3113817378
Directory /workspace/49.keymgr_alert_test/latest

Test location /workspace/coverage/default/49.keymgr_cfg_regwen.1976061374
Short name T413
Test name
Test status
Simulation time 131578078 ps
CPU time 7.95 seconds
Started Mar 26 03:30:35 PM PDT 24
Finished Mar 26 03:30:43 PM PDT 24
Peak memory 222880 kb
Host smart-bbbb2464-0a88-4cdb-97db-96d3f7bce766
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=1976061374 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_cfg_regwen.1976061374
Directory /workspace/49.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/49.keymgr_custom_cm.2037521502
Short name T42
Test name
Test status
Simulation time 335016533 ps
CPU time 5.34 seconds
Started Mar 26 03:30:04 PM PDT 24
Finished Mar 26 03:30:10 PM PDT 24
Peak memory 214992 kb
Host smart-a812527c-226b-493a-ba68-42c363d95f3f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2037521502 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_custom_cm.2037521502
Directory /workspace/49.keymgr_custom_cm/latest

Test location /workspace/coverage/default/49.keymgr_direct_to_disabled.2034201245
Short name T739
Test name
Test status
Simulation time 41679361 ps
CPU time 1.58 seconds
Started Mar 26 03:30:18 PM PDT 24
Finished Mar 26 03:30:20 PM PDT 24
Peak memory 208088 kb
Host smart-9ca1b5aa-365d-40ed-99f8-85c1b8bd0ac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034201245 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_direct_to_disabled.2034201245
Directory /workspace/49.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/49.keymgr_hwsw_invalid_input.1821102517
Short name T90
Test name
Test status
Simulation time 89785901 ps
CPU time 4.21 seconds
Started Mar 26 03:30:08 PM PDT 24
Finished Mar 26 03:30:13 PM PDT 24
Peak memory 209404 kb
Host smart-079fd742-b4f7-482e-856b-e9f371e3f4a3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1821102517 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_hwsw_invalid_input.1821102517
Directory /workspace/49.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_kmac_rsp_err.502867557
Short name T760
Test name
Test status
Simulation time 716330683 ps
CPU time 9.18 seconds
Started Mar 26 03:30:04 PM PDT 24
Finished Mar 26 03:30:13 PM PDT 24
Peak memory 222764 kb
Host smart-ad33b2f0-2e48-40f6-adac-e5f16e95f580
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=502867557 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_kmac_rsp_err.502867557
Directory /workspace/49.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/49.keymgr_lc_disable.2187726633
Short name T229
Test name
Test status
Simulation time 112129230 ps
CPU time 3.71 seconds
Started Mar 26 03:30:04 PM PDT 24
Finished Mar 26 03:30:08 PM PDT 24
Peak memory 220480 kb
Host smart-affdd3a9-de4b-46d5-823c-a51703b61a85
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2187726633 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_lc_disable.2187726633
Directory /workspace/49.keymgr_lc_disable/latest

Test location /workspace/coverage/default/49.keymgr_random.964625116
Short name T734
Test name
Test status
Simulation time 425726036 ps
CPU time 9.17 seconds
Started Mar 26 03:30:32 PM PDT 24
Finished Mar 26 03:30:41 PM PDT 24
Peak memory 214592 kb
Host smart-4beb0851-a515-4678-9135-843556b45e23
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=964625116 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_random.964625116
Directory /workspace/49.keymgr_random/latest

Test location /workspace/coverage/default/49.keymgr_sideload.1500539958
Short name T673
Test name
Test status
Simulation time 322413247 ps
CPU time 4.38 seconds
Started Mar 26 03:30:16 PM PDT 24
Finished Mar 26 03:30:20 PM PDT 24
Peak memory 206968 kb
Host smart-d4a30cb0-3b98-4020-9c45-0c83a437fbaa
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1500539958 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload.1500539958
Directory /workspace/49.keymgr_sideload/latest

Test location /workspace/coverage/default/49.keymgr_sideload_aes.340095996
Short name T523
Test name
Test status
Simulation time 50754739 ps
CPU time 3.01 seconds
Started Mar 26 03:30:07 PM PDT 24
Finished Mar 26 03:30:11 PM PDT 24
Peak memory 207184 kb
Host smart-6ec8cd41-4d14-4807-80b5-58454086c210
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=340095996 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_aes.340095996
Directory /workspace/49.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/49.keymgr_sideload_kmac.1669074686
Short name T525
Test name
Test status
Simulation time 205081852 ps
CPU time 7.72 seconds
Started Mar 26 03:30:16 PM PDT 24
Finished Mar 26 03:30:24 PM PDT 24
Peak memory 207092 kb
Host smart-1920aa9f-4be9-4a56-8c4f-15618009daaa
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1669074686 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_kmac.1669074686
Directory /workspace/49.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/49.keymgr_sideload_otbn.31247556
Short name T677
Test name
Test status
Simulation time 450074778 ps
CPU time 4.39 seconds
Started Mar 26 03:30:33 PM PDT 24
Finished Mar 26 03:30:37 PM PDT 24
Peak memory 207136 kb
Host smart-0ae025df-f50c-49dd-87b5-6c006b2be095
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31247556 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_otbn.31247556
Directory /workspace/49.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/49.keymgr_sideload_protect.3853413211
Short name T238
Test name
Test status
Simulation time 508094300 ps
CPU time 8.77 seconds
Started Mar 26 03:30:25 PM PDT 24
Finished Mar 26 03:30:34 PM PDT 24
Peak memory 209708 kb
Host smart-7a6bcd46-b910-467b-9d56-8ff317069106
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853413211 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sideload_protect.3853413211
Directory /workspace/49.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/49.keymgr_smoke.2957899558
Short name T471
Test name
Test status
Simulation time 356025475 ps
CPU time 3.07 seconds
Started Mar 26 03:30:07 PM PDT 24
Finished Mar 26 03:30:10 PM PDT 24
Peak memory 209032 kb
Host smart-d095ec5f-698d-4c50-99d1-b5faa0771aa4
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957899558 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_smoke.2957899558
Directory /workspace/49.keymgr_smoke/latest

Test location /workspace/coverage/default/49.keymgr_stress_all.3519775229
Short name T58
Test name
Test status
Simulation time 1416622349 ps
CPU time 27.94 seconds
Started Mar 26 03:30:12 PM PDT 24
Finished Mar 26 03:30:45 PM PDT 24
Peak memory 214700 kb
Host smart-d6c56892-925e-4ca1-8d2e-ed6b412a4b67
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3519775229 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_stress_all.3519775229
Directory /workspace/49.keymgr_stress_all/latest

Test location /workspace/coverage/default/49.keymgr_sw_invalid_input.3920335363
Short name T737
Test name
Test status
Simulation time 234493095 ps
CPU time 5.46 seconds
Started Mar 26 03:30:03 PM PDT 24
Finished Mar 26 03:30:09 PM PDT 24
Peak memory 210204 kb
Host smart-df5598d1-c409-4dd0-a978-74409557fa57
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3920335363 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sw_invalid_input.3920335363
Directory /workspace/49.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/49.keymgr_sync_async_fault_cross.1277828394
Short name T741
Test name
Test status
Simulation time 46417184 ps
CPU time 2.23 seconds
Started Mar 26 03:30:07 PM PDT 24
Finished Mar 26 03:30:09 PM PDT 24
Peak memory 210324 kb
Host smart-40ea766f-dea5-4c35-9f5c-2badb7db41a0
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1277828394 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.keymgr_sync_async_fault_cross.1277828394
Directory /workspace/49.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/5.keymgr_alert_test.3993301407
Short name T886
Test name
Test status
Simulation time 11250885 ps
CPU time 0.82 seconds
Started Mar 26 03:28:19 PM PDT 24
Finished Mar 26 03:28:20 PM PDT 24
Peak memory 206312 kb
Host smart-e1f6805b-0172-4dfc-86b5-99c72a0b6b33
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3993301407 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_alert_test.3993301407
Directory /workspace/5.keymgr_alert_test/latest

Test location /workspace/coverage/default/5.keymgr_cfg_regwen.3928573805
Short name T266
Test name
Test status
Simulation time 227279275 ps
CPU time 4.15 seconds
Started Mar 26 03:28:17 PM PDT 24
Finished Mar 26 03:28:22 PM PDT 24
Peak memory 215980 kb
Host smart-639b1714-ea66-4373-8811-a43998e2f122
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3928573805 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_cfg_regwen.3928573805
Directory /workspace/5.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/5.keymgr_custom_cm.3004902903
Short name T37
Test name
Test status
Simulation time 322537871 ps
CPU time 10.26 seconds
Started Mar 26 03:28:21 PM PDT 24
Finished Mar 26 03:28:32 PM PDT 24
Peak memory 214732 kb
Host smart-87fee154-8c64-48f8-9a44-f24cbcb562a6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3004902903 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_custom_cm.3004902903
Directory /workspace/5.keymgr_custom_cm/latest

Test location /workspace/coverage/default/5.keymgr_direct_to_disabled.412252160
Short name T486
Test name
Test status
Simulation time 55624643 ps
CPU time 2.09 seconds
Started Mar 26 03:28:18 PM PDT 24
Finished Mar 26 03:28:20 PM PDT 24
Peak memory 207588 kb
Host smart-335243ed-f5ce-496d-b0d0-0303bc9bf8ec
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=412252160 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_direct_to_disabled.412252160
Directory /workspace/5.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/5.keymgr_hwsw_invalid_input.1497634794
Short name T343
Test name
Test status
Simulation time 1379708702 ps
CPU time 13.28 seconds
Started Mar 26 03:28:19 PM PDT 24
Finished Mar 26 03:28:33 PM PDT 24
Peak memory 219948 kb
Host smart-9e014e68-488f-484e-b22f-a90ab65d8c07
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1497634794 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_hwsw_invalid_input.1497634794
Directory /workspace/5.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_kmac_rsp_err.2755320077
Short name T680
Test name
Test status
Simulation time 154566179 ps
CPU time 7.06 seconds
Started Mar 26 03:28:06 PM PDT 24
Finished Mar 26 03:28:13 PM PDT 24
Peak memory 222784 kb
Host smart-83e6392b-70f3-46c3-81d4-e6d27631dda1
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2755320077 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_kmac_rsp_err.2755320077
Directory /workspace/5.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/5.keymgr_lc_disable.2729489429
Short name T500
Test name
Test status
Simulation time 80339499 ps
CPU time 2.5 seconds
Started Mar 26 03:28:26 PM PDT 24
Finished Mar 26 03:28:29 PM PDT 24
Peak memory 209964 kb
Host smart-903b73f0-3439-42d9-905c-02e7a1f234de
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2729489429 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_lc_disable.2729489429
Directory /workspace/5.keymgr_lc_disable/latest

Test location /workspace/coverage/default/5.keymgr_random.162569973
Short name T241
Test name
Test status
Simulation time 181410217 ps
CPU time 4.57 seconds
Started Mar 26 03:28:20 PM PDT 24
Finished Mar 26 03:28:25 PM PDT 24
Peak memory 207856 kb
Host smart-65319424-6224-4603-8a9e-4a9a59fb415e
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=162569973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_random.162569973
Directory /workspace/5.keymgr_random/latest

Test location /workspace/coverage/default/5.keymgr_sideload.3359396537
Short name T764
Test name
Test status
Simulation time 983295877 ps
CPU time 7.2 seconds
Started Mar 26 03:28:18 PM PDT 24
Finished Mar 26 03:28:25 PM PDT 24
Peak memory 208524 kb
Host smart-04687228-04de-4d60-a929-e215239dcdf9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359396537 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload.3359396537
Directory /workspace/5.keymgr_sideload/latest

Test location /workspace/coverage/default/5.keymgr_sideload_aes.1591717798
Short name T473
Test name
Test status
Simulation time 503734437 ps
CPU time 2.63 seconds
Started Mar 26 03:28:18 PM PDT 24
Finished Mar 26 03:28:21 PM PDT 24
Peak memory 207796 kb
Host smart-7bdd6f1f-9334-4d9c-9929-46feb8d537aa
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1591717798 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_aes.1591717798
Directory /workspace/5.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/5.keymgr_sideload_kmac.2254985328
Short name T572
Test name
Test status
Simulation time 448492312 ps
CPU time 6.61 seconds
Started Mar 26 03:28:17 PM PDT 24
Finished Mar 26 03:28:24 PM PDT 24
Peak memory 208092 kb
Host smart-52750fe1-618c-47eb-8b14-1e94139c8399
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2254985328 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_kmac.2254985328
Directory /workspace/5.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/5.keymgr_sideload_otbn.131122639
Short name T369
Test name
Test status
Simulation time 2025708659 ps
CPU time 7.68 seconds
Started Mar 26 03:28:17 PM PDT 24
Finished Mar 26 03:28:25 PM PDT 24
Peak memory 208136 kb
Host smart-a93c048d-8c8c-40b8-b9c5-76767328243b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=131122639 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_otbn.131122639
Directory /workspace/5.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/5.keymgr_sideload_protect.1487753912
Short name T854
Test name
Test status
Simulation time 147088812 ps
CPU time 3.17 seconds
Started Mar 26 03:28:17 PM PDT 24
Finished Mar 26 03:28:20 PM PDT 24
Peak memory 222820 kb
Host smart-726e5302-9bc5-44c0-8297-80eea2d8aa64
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1487753912 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sideload_protect.1487753912
Directory /workspace/5.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/5.keymgr_smoke.2716223887
Short name T451
Test name
Test status
Simulation time 648472136 ps
CPU time 4.39 seconds
Started Mar 26 03:28:18 PM PDT 24
Finished Mar 26 03:28:22 PM PDT 24
Peak memory 207116 kb
Host smart-19b546c9-9126-4ed1-b72c-a8cf9e58b1d3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2716223887 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_smoke.2716223887
Directory /workspace/5.keymgr_smoke/latest

Test location /workspace/coverage/default/5.keymgr_stress_all.2000562800
Short name T786
Test name
Test status
Simulation time 1555506059 ps
CPU time 5.18 seconds
Started Mar 26 03:28:16 PM PDT 24
Finished Mar 26 03:28:21 PM PDT 24
Peak memory 208952 kb
Host smart-f81df61c-d179-4058-b2e9-0b8f561d67d4
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2000562800 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_stress_all.2000562800
Directory /workspace/5.keymgr_stress_all/latest

Test location /workspace/coverage/default/5.keymgr_sw_invalid_input.2218364553
Short name T248
Test name
Test status
Simulation time 405645361 ps
CPU time 3.47 seconds
Started Mar 26 03:28:11 PM PDT 24
Finished Mar 26 03:28:14 PM PDT 24
Peak memory 214700 kb
Host smart-52076187-5bb4-4828-8ed7-c7d976e0c183
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2218364553 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sw_invalid_input.2218364553
Directory /workspace/5.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/5.keymgr_sync_async_fault_cross.1412442162
Short name T755
Test name
Test status
Simulation time 177746195 ps
CPU time 3.26 seconds
Started Mar 26 03:28:18 PM PDT 24
Finished Mar 26 03:28:21 PM PDT 24
Peak memory 210096 kb
Host smart-af70fd32-5cc7-4457-93fa-9a6d021a98b3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1412442162 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.keymgr_sync_async_fault_cross.1412442162
Directory /workspace/5.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/6.keymgr_alert_test.1159753014
Short name T487
Test name
Test status
Simulation time 14989658 ps
CPU time 0.71 seconds
Started Mar 26 03:28:41 PM PDT 24
Finished Mar 26 03:28:42 PM PDT 24
Peak memory 206312 kb
Host smart-dd6463d5-cb5a-4189-8f4b-96f6192f2823
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1159753014 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_alert_test.1159753014
Directory /workspace/6.keymgr_alert_test/latest

Test location /workspace/coverage/default/6.keymgr_cfg_regwen.634469834
Short name T406
Test name
Test status
Simulation time 1501582857 ps
CPU time 81.14 seconds
Started Mar 26 03:28:16 PM PDT 24
Finished Mar 26 03:29:37 PM PDT 24
Peak memory 215712 kb
Host smart-75cfe38b-ec91-4562-a1af-82422d5bff85
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=634469834 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_cfg_regwen.634469834
Directory /workspace/6.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/6.keymgr_custom_cm.3561565803
Short name T33
Test name
Test status
Simulation time 107780260 ps
CPU time 3.11 seconds
Started Mar 26 03:28:15 PM PDT 24
Finished Mar 26 03:28:18 PM PDT 24
Peak memory 223168 kb
Host smart-8a8ba6d1-3720-482f-94d7-b1c30d8e4e66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3561565803 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_custom_cm.3561565803
Directory /workspace/6.keymgr_custom_cm/latest

Test location /workspace/coverage/default/6.keymgr_direct_to_disabled.487783917
Short name T682
Test name
Test status
Simulation time 58750854 ps
CPU time 2.44 seconds
Started Mar 26 03:28:33 PM PDT 24
Finished Mar 26 03:28:36 PM PDT 24
Peak memory 210152 kb
Host smart-1b83f750-dae8-4066-bb2a-770609fe0b5a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=487783917 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_direct_to_disabled.487783917
Directory /workspace/6.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/6.keymgr_hwsw_invalid_input.2890361961
Short name T639
Test name
Test status
Simulation time 582451630 ps
CPU time 8.46 seconds
Started Mar 26 03:28:12 PM PDT 24
Finished Mar 26 03:28:20 PM PDT 24
Peak memory 214784 kb
Host smart-aad4f9d5-5856-45f2-9973-8de580e81a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2890361961 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_hwsw_invalid_input.2890361961
Directory /workspace/6.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_kmac_rsp_err.3062933987
Short name T319
Test name
Test status
Simulation time 777450918 ps
CPU time 11.34 seconds
Started Mar 26 03:28:21 PM PDT 24
Finished Mar 26 03:28:32 PM PDT 24
Peak memory 222812 kb
Host smart-6a990b69-637f-45da-aa58-72c67ae00646
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3062933987 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_kmac_rsp_err.3062933987
Directory /workspace/6.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/6.keymgr_lc_disable.69360901
Short name T573
Test name
Test status
Simulation time 209402283 ps
CPU time 3.4 seconds
Started Mar 26 03:28:18 PM PDT 24
Finished Mar 26 03:28:26 PM PDT 24
Peak memory 220684 kb
Host smart-1dfa69f4-b33b-4016-bac5-284c9d49c01d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=69360901 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_lc_disable.69360901
Directory /workspace/6.keymgr_lc_disable/latest

Test location /workspace/coverage/default/6.keymgr_random.990825135
Short name T548
Test name
Test status
Simulation time 150566278 ps
CPU time 4.69 seconds
Started Mar 26 03:28:20 PM PDT 24
Finished Mar 26 03:28:25 PM PDT 24
Peak memory 209416 kb
Host smart-fa55e4b1-21e8-40ae-97ed-c5a4cb3cb364
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=990825135 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_random.990825135
Directory /workspace/6.keymgr_random/latest

Test location /workspace/coverage/default/6.keymgr_sideload.144496826
Short name T366
Test name
Test status
Simulation time 85222962 ps
CPU time 2.84 seconds
Started Mar 26 03:28:09 PM PDT 24
Finished Mar 26 03:28:12 PM PDT 24
Peak memory 208892 kb
Host smart-626953f3-dc66-461c-b0cd-f6c652eb4a0d
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=144496826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload.144496826
Directory /workspace/6.keymgr_sideload/latest

Test location /workspace/coverage/default/6.keymgr_sideload_aes.412109742
Short name T545
Test name
Test status
Simulation time 117325732 ps
CPU time 4.64 seconds
Started Mar 26 03:28:10 PM PDT 24
Finished Mar 26 03:28:14 PM PDT 24
Peak memory 207728 kb
Host smart-d33e6a4b-7a21-44f4-a56d-d666e4cc0444
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=412109742 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_aes.412109742
Directory /workspace/6.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/6.keymgr_sideload_kmac.2002935342
Short name T641
Test name
Test status
Simulation time 63063029 ps
CPU time 2.47 seconds
Started Mar 26 03:28:34 PM PDT 24
Finished Mar 26 03:28:36 PM PDT 24
Peak memory 206988 kb
Host smart-de637cfc-e9a8-487f-b185-73aae50e483a
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2002935342 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_kmac.2002935342
Directory /workspace/6.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/6.keymgr_sideload_otbn.919382319
Short name T670
Test name
Test status
Simulation time 180872459 ps
CPU time 3.19 seconds
Started Mar 26 03:28:18 PM PDT 24
Finished Mar 26 03:28:21 PM PDT 24
Peak memory 208800 kb
Host smart-7daae55f-0a6e-4b06-a36c-f59fa577f1c8
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=919382319 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_otbn.919382319
Directory /workspace/6.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/6.keymgr_sideload_protect.3986772498
Short name T83
Test name
Test status
Simulation time 34465942 ps
CPU time 1.48 seconds
Started Mar 26 03:28:18 PM PDT 24
Finished Mar 26 03:28:20 PM PDT 24
Peak memory 214596 kb
Host smart-b719281e-e683-4f8d-ac39-3776e807a74a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986772498 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sideload_protect.3986772498
Directory /workspace/6.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/6.keymgr_smoke.1846379600
Short name T434
Test name
Test status
Simulation time 773780345 ps
CPU time 5.97 seconds
Started Mar 26 03:28:08 PM PDT 24
Finished Mar 26 03:28:14 PM PDT 24
Peak memory 209012 kb
Host smart-b9b5b388-7633-46e8-8350-cb0f8e8390e6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1846379600 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_smoke.1846379600
Directory /workspace/6.keymgr_smoke/latest

Test location /workspace/coverage/default/6.keymgr_stress_all.3555812579
Short name T674
Test name
Test status
Simulation time 2570249028 ps
CPU time 44.7 seconds
Started Mar 26 03:28:33 PM PDT 24
Finished Mar 26 03:29:18 PM PDT 24
Peak memory 222984 kb
Host smart-29e75787-82b0-43f2-b98e-9a18fb785c34
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3555812579 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all.3555812579
Directory /workspace/6.keymgr_stress_all/latest

Test location /workspace/coverage/default/6.keymgr_stress_all_with_rand_reset.2188437066
Short name T863
Test name
Test status
Simulation time 265751679 ps
CPU time 10.82 seconds
Started Mar 26 03:28:12 PM PDT 24
Finished Mar 26 03:28:23 PM PDT 24
Peak memory 220296 kb
Host smart-42f11408-782f-4197-8306-c2380132ce6f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2188437066 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 6.keymgr_stress_all_with_rand_reset.2188437066
Directory /workspace/6.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.keymgr_sw_invalid_input.376640357
Short name T13
Test name
Test status
Simulation time 242675378 ps
CPU time 6.68 seconds
Started Mar 26 03:28:18 PM PDT 24
Finished Mar 26 03:28:25 PM PDT 24
Peak memory 209148 kb
Host smart-7d737ff5-2c19-468b-9f78-1a9de4a3cdc2
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376640357 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sw_invalid_input.376640357
Directory /workspace/6.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/6.keymgr_sync_async_fault_cross.2284776082
Short name T602
Test name
Test status
Simulation time 142971535 ps
CPU time 2.13 seconds
Started Mar 26 03:28:35 PM PDT 24
Finished Mar 26 03:28:37 PM PDT 24
Peak memory 210480 kb
Host smart-9e3d4c3d-4845-4ce1-8073-af5c9397b035
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284776082 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.keymgr_sync_async_fault_cross.2284776082
Directory /workspace/6.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/7.keymgr_alert_test.3001092119
Short name T561
Test name
Test status
Simulation time 16933448 ps
CPU time 0.77 seconds
Started Mar 26 03:28:37 PM PDT 24
Finished Mar 26 03:28:38 PM PDT 24
Peak memory 206280 kb
Host smart-cc967588-e778-4a9e-bcda-920b71fae540
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3001092119 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_alert_test.3001092119
Directory /workspace/7.keymgr_alert_test/latest

Test location /workspace/coverage/default/7.keymgr_cfg_regwen.3812629005
Short name T353
Test name
Test status
Simulation time 45858611 ps
CPU time 3.64 seconds
Started Mar 26 03:28:29 PM PDT 24
Finished Mar 26 03:28:32 PM PDT 24
Peak memory 214660 kb
Host smart-20a08c69-8338-410b-8e31-6c2e2b91b986
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3812629005 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_cfg_regwen.3812629005
Directory /workspace/7.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/7.keymgr_custom_cm.1006793271
Short name T34
Test name
Test status
Simulation time 78145177 ps
CPU time 1.87 seconds
Started Mar 26 03:28:34 PM PDT 24
Finished Mar 26 03:28:36 PM PDT 24
Peak memory 217512 kb
Host smart-1efdd9cb-f2dc-496c-b7f4-bf45c0ac7de3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006793271 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_custom_cm.1006793271
Directory /workspace/7.keymgr_custom_cm/latest

Test location /workspace/coverage/default/7.keymgr_direct_to_disabled.4243181103
Short name T68
Test name
Test status
Simulation time 242204365 ps
CPU time 2.31 seconds
Started Mar 26 03:28:23 PM PDT 24
Finished Mar 26 03:28:26 PM PDT 24
Peak memory 207432 kb
Host smart-b76f0381-728b-43ff-8f4b-f65a098bcac3
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243181103 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_direct_to_disabled.4243181103
Directory /workspace/7.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/7.keymgr_hwsw_invalid_input.147467627
Short name T25
Test name
Test status
Simulation time 5115236935 ps
CPU time 59.36 seconds
Started Mar 26 03:28:40 PM PDT 24
Finished Mar 26 03:29:40 PM PDT 24
Peak memory 210264 kb
Host smart-a7a804aa-ad97-4fc6-a80d-a5d7bf5c0346
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=147467627 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_hwsw_invalid_input.147467627
Directory /workspace/7.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_kmac_rsp_err.2753270149
Short name T199
Test name
Test status
Simulation time 15277515642 ps
CPU time 88.99 seconds
Started Mar 26 03:28:20 PM PDT 24
Finished Mar 26 03:29:49 PM PDT 24
Peak memory 227684 kb
Host smart-4ed92e81-79a5-48d9-b205-699977875371
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2753270149 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_kmac_rsp_err.2753270149
Directory /workspace/7.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/7.keymgr_lc_disable.1735819568
Short name T765
Test name
Test status
Simulation time 275502378 ps
CPU time 3.62 seconds
Started Mar 26 03:28:33 PM PDT 24
Finished Mar 26 03:28:37 PM PDT 24
Peak memory 209768 kb
Host smart-20414c80-c262-43dd-8df3-f2fe36960200
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1735819568 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_lc_disable.1735819568
Directory /workspace/7.keymgr_lc_disable/latest

Test location /workspace/coverage/default/7.keymgr_random.437145737
Short name T468
Test name
Test status
Simulation time 49806240 ps
CPU time 3.22 seconds
Started Mar 26 03:28:40 PM PDT 24
Finished Mar 26 03:28:44 PM PDT 24
Peak memory 216464 kb
Host smart-c1ae2fb0-02fe-40dc-9dbc-b0610dd93f5f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=437145737 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_random.437145737
Directory /workspace/7.keymgr_random/latest

Test location /workspace/coverage/default/7.keymgr_sideload.3302674124
Short name T688
Test name
Test status
Simulation time 1681690727 ps
CPU time 41.3 seconds
Started Mar 26 03:28:25 PM PDT 24
Finished Mar 26 03:29:07 PM PDT 24
Peak memory 209036 kb
Host smart-0e19f58b-84c3-4c75-8d79-57860d51de2b
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302674124 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload.3302674124
Directory /workspace/7.keymgr_sideload/latest

Test location /workspace/coverage/default/7.keymgr_sideload_aes.3162668986
Short name T887
Test name
Test status
Simulation time 92110404 ps
CPU time 2.61 seconds
Started Mar 26 03:28:17 PM PDT 24
Finished Mar 26 03:28:20 PM PDT 24
Peak memory 207232 kb
Host smart-d95a58fc-0a35-4a46-b1bc-f2b5824d3f0c
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3162668986 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_aes.3162668986
Directory /workspace/7.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/7.keymgr_sideload_kmac.2988289225
Short name T519
Test name
Test status
Simulation time 50497942 ps
CPU time 2.84 seconds
Started Mar 26 03:28:38 PM PDT 24
Finished Mar 26 03:28:41 PM PDT 24
Peak memory 207192 kb
Host smart-36195a79-c1cc-4557-85b7-d6fbd2357517
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2988289225 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_kmac.2988289225
Directory /workspace/7.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/7.keymgr_sideload_otbn.1548714475
Short name T597
Test name
Test status
Simulation time 331441191 ps
CPU time 3.46 seconds
Started Mar 26 03:28:22 PM PDT 24
Finished Mar 26 03:28:26 PM PDT 24
Peak memory 207612 kb
Host smart-ef672f05-ba33-452d-bb28-1775fd354c99
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1548714475 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_otbn.1548714475
Directory /workspace/7.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/7.keymgr_sideload_protect.48081159
Short name T417
Test name
Test status
Simulation time 41336206 ps
CPU time 1.86 seconds
Started Mar 26 03:28:32 PM PDT 24
Finished Mar 26 03:28:34 PM PDT 24
Peak memory 214688 kb
Host smart-925ad4ea-10e8-45d4-b626-411bea50b4dd
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=48081159 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sideload_protect.48081159
Directory /workspace/7.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/7.keymgr_smoke.1335231333
Short name T713
Test name
Test status
Simulation time 139466855 ps
CPU time 2.19 seconds
Started Mar 26 03:28:20 PM PDT 24
Finished Mar 26 03:28:23 PM PDT 24
Peak memory 207048 kb
Host smart-d5935c29-a7fa-47fc-9e12-6ef9bdd2dc4f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1335231333 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_smoke.1335231333
Directory /workspace/7.keymgr_smoke/latest

Test location /workspace/coverage/default/7.keymgr_sw_invalid_input.3070228064
Short name T257
Test name
Test status
Simulation time 277185747 ps
CPU time 3.94 seconds
Started Mar 26 03:28:20 PM PDT 24
Finished Mar 26 03:28:24 PM PDT 24
Peak memory 209560 kb
Host smart-80a37b9a-a66e-4853-bc54-cda37871944c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3070228064 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sw_invalid_input.3070228064
Directory /workspace/7.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/7.keymgr_sync_async_fault_cross.2008535193
Short name T198
Test name
Test status
Simulation time 116517156 ps
CPU time 1.64 seconds
Started Mar 26 03:28:40 PM PDT 24
Finished Mar 26 03:28:41 PM PDT 24
Peak memory 209944 kb
Host smart-ee0b6119-2c17-468e-a769-3d88c1156f67
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2008535193 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.keymgr_sync_async_fault_cross.2008535193
Directory /workspace/7.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/8.keymgr_alert_test.2350066203
Short name T812
Test name
Test status
Simulation time 13044843 ps
CPU time 1.01 seconds
Started Mar 26 03:28:39 PM PDT 24
Finished Mar 26 03:28:41 PM PDT 24
Peak memory 206396 kb
Host smart-ece5e09d-da26-4bc6-8d42-0b2cee54373b
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2350066203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_alert_test.2350066203
Directory /workspace/8.keymgr_alert_test/latest

Test location /workspace/coverage/default/8.keymgr_cfg_regwen.3117626833
Short name T146
Test name
Test status
Simulation time 4186128401 ps
CPU time 50.31 seconds
Started Mar 26 03:28:20 PM PDT 24
Finished Mar 26 03:29:11 PM PDT 24
Peak memory 214852 kb
Host smart-f89e047b-e219-4ffe-97c2-0006e30f7a06
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=3117626833 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_cfg_regwen.3117626833
Directory /workspace/8.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/8.keymgr_custom_cm.4053178826
Short name T163
Test name
Test status
Simulation time 241105986 ps
CPU time 2.45 seconds
Started Mar 26 03:28:34 PM PDT 24
Finished Mar 26 03:28:37 PM PDT 24
Peak memory 223268 kb
Host smart-b784952c-2a1c-469b-9198-1f8aa5200a66
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053178826 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_custom_cm.4053178826
Directory /workspace/8.keymgr_custom_cm/latest

Test location /workspace/coverage/default/8.keymgr_direct_to_disabled.2946973839
Short name T466
Test name
Test status
Simulation time 83941572 ps
CPU time 3.24 seconds
Started Mar 26 03:28:43 PM PDT 24
Finished Mar 26 03:28:46 PM PDT 24
Peak memory 218780 kb
Host smart-dd8c04fe-a906-40c8-83f3-31e97f0dfd2a
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946973839 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_direct_to_disabled.2946973839
Directory /workspace/8.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/8.keymgr_hwsw_invalid_input.928499967
Short name T540
Test name
Test status
Simulation time 106410374 ps
CPU time 4.27 seconds
Started Mar 26 03:28:40 PM PDT 24
Finished Mar 26 03:28:45 PM PDT 24
Peak memory 209868 kb
Host smart-f7e62dc3-fd9f-4d45-8ac6-fcce78dfb303
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=928499967 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_hwsw_invalid_input_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_hwsw_invalid_input.928499967
Directory /workspace/8.keymgr_hwsw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_kmac_rsp_err.3616659254
Short name T320
Test name
Test status
Simulation time 274837920 ps
CPU time 8.81 seconds
Started Mar 26 03:28:17 PM PDT 24
Finished Mar 26 03:28:26 PM PDT 24
Peak memory 222812 kb
Host smart-54067d11-473c-4660-ab4d-baa35df3fb82
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3616659254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_kmac_rsp_err.3616659254
Directory /workspace/8.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/8.keymgr_lc_disable.536345253
Short name T630
Test name
Test status
Simulation time 90676758 ps
CPU time 3.99 seconds
Started Mar 26 03:28:40 PM PDT 24
Finished Mar 26 03:28:45 PM PDT 24
Peak memory 209672 kb
Host smart-fd81c508-bcd2-4a16-9573-dad1278324e8
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=536345253 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_lc_disable.536345253
Directory /workspace/8.keymgr_lc_disable/latest

Test location /workspace/coverage/default/8.keymgr_random.3161135197
Short name T440
Test name
Test status
Simulation time 68449952 ps
CPU time 4.12 seconds
Started Mar 26 03:28:19 PM PDT 24
Finished Mar 26 03:28:24 PM PDT 24
Peak memory 209444 kb
Host smart-11a806ba-019c-4ca0-af03-e18dc106a948
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3161135197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_random.3161135197
Directory /workspace/8.keymgr_random/latest

Test location /workspace/coverage/default/8.keymgr_sideload.230383472
Short name T714
Test name
Test status
Simulation time 65711951 ps
CPU time 1.77 seconds
Started Mar 26 03:28:40 PM PDT 24
Finished Mar 26 03:28:42 PM PDT 24
Peak memory 207080 kb
Host smart-fae805cc-b6b3-4ded-ab52-c5a6fcb2689c
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230383472 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload.230383472
Directory /workspace/8.keymgr_sideload/latest

Test location /workspace/coverage/default/8.keymgr_sideload_aes.2748761415
Short name T596
Test name
Test status
Simulation time 99742904 ps
CPU time 2.79 seconds
Started Mar 26 03:28:19 PM PDT 24
Finished Mar 26 03:28:23 PM PDT 24
Peak memory 207648 kb
Host smart-61e03ec9-90be-423b-88ad-0f151da73106
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2748761415 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_aes.2748761415
Directory /workspace/8.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/8.keymgr_sideload_kmac.976590204
Short name T858
Test name
Test status
Simulation time 107274389 ps
CPU time 3.33 seconds
Started Mar 26 03:28:19 PM PDT 24
Finished Mar 26 03:28:23 PM PDT 24
Peak memory 207056 kb
Host smart-9742cf13-c6c9-429a-8e9e-7072b2b4f327
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976590204 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_kmac.976590204
Directory /workspace/8.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/8.keymgr_sideload_otbn.3732320364
Short name T253
Test name
Test status
Simulation time 194371139 ps
CPU time 5.36 seconds
Started Mar 26 03:28:45 PM PDT 24
Finished Mar 26 03:28:51 PM PDT 24
Peak memory 208052 kb
Host smart-4828b1a7-a1de-496d-8eed-534cdde2481b
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3732320364 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_otbn.3732320364
Directory /workspace/8.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/8.keymgr_sideload_protect.1070296873
Short name T460
Test name
Test status
Simulation time 348381660 ps
CPU time 2.33 seconds
Started Mar 26 03:28:23 PM PDT 24
Finished Mar 26 03:28:26 PM PDT 24
Peak memory 208400 kb
Host smart-a7e2d646-6bed-4dae-9fc3-898d22fc16fb
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1070296873 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sideload_protect.1070296873
Directory /workspace/8.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/8.keymgr_smoke.229067203
Short name T800
Test name
Test status
Simulation time 49054235 ps
CPU time 2.59 seconds
Started Mar 26 03:28:42 PM PDT 24
Finished Mar 26 03:28:45 PM PDT 24
Peak memory 207136 kb
Host smart-bf42bbcb-d97e-4006-ab6f-8e2d1491e0c6
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=229067203 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_smoke.229067203
Directory /workspace/8.keymgr_smoke/latest

Test location /workspace/coverage/default/8.keymgr_stress_all.2780446630
Short name T574
Test name
Test status
Simulation time 316268696 ps
CPU time 12.95 seconds
Started Mar 26 03:28:34 PM PDT 24
Finished Mar 26 03:28:47 PM PDT 24
Peak memory 219080 kb
Host smart-0cfd6611-08e3-4ff9-87d5-8dd7aafda934
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2780446630 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all.2780446630
Directory /workspace/8.keymgr_stress_all/latest

Test location /workspace/coverage/default/8.keymgr_stress_all_with_rand_reset.1730557546
Short name T798
Test name
Test status
Simulation time 502464468 ps
CPU time 11.3 seconds
Started Mar 26 03:28:41 PM PDT 24
Finished Mar 26 03:28:52 PM PDT 24
Peak memory 222864 kb
Host smart-6a4f0cf8-0824-4b1d-b335-aec673f5b57f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1730557546 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 8.keymgr_stress_all_with_rand_reset.1730557546
Directory /workspace/8.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.keymgr_sw_invalid_input.3059846731
Short name T761
Test name
Test status
Simulation time 91032156 ps
CPU time 3.19 seconds
Started Mar 26 03:28:38 PM PDT 24
Finished Mar 26 03:28:41 PM PDT 24
Peak memory 207872 kb
Host smart-ed37befe-6947-4452-9f59-038c3dcbe083
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3059846731 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sw_invalid_input.3059846731
Directory /workspace/8.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/8.keymgr_sync_async_fault_cross.1790904000
Short name T669
Test name
Test status
Simulation time 420649934 ps
CPU time 2.46 seconds
Started Mar 26 03:28:18 PM PDT 24
Finished Mar 26 03:28:20 PM PDT 24
Peak memory 210684 kb
Host smart-c71545be-a23f-445b-b307-50df3c25e9f5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790904000 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.keymgr_sync_async_fault_cross.1790904000
Directory /workspace/8.keymgr_sync_async_fault_cross/latest

Test location /workspace/coverage/default/9.keymgr_alert_test.2928835283
Short name T781
Test name
Test status
Simulation time 15731641 ps
CPU time 0.75 seconds
Started Mar 26 03:28:39 PM PDT 24
Finished Mar 26 03:28:40 PM PDT 24
Peak memory 206316 kb
Host smart-817c7117-ee3a-45e3-b463-41d1c331b545
User root
Command /workspace/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspac
e/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2928835283 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_alert_test.2928835283
Directory /workspace/9.keymgr_alert_test/latest

Test location /workspace/coverage/default/9.keymgr_cfg_regwen.485631945
Short name T419
Test name
Test status
Simulation time 1076284826 ps
CPU time 54.88 seconds
Started Mar 26 03:28:17 PM PDT 24
Finished Mar 26 03:29:12 PM PDT 24
Peak memory 214656 kb
Host smart-75aecff3-ca2b-4bdb-9efd-1a39c3191bb8
User root
Command /workspace/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_
top/hw/dv/tools/sim.tcl +ntb_random_seed=485631945 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_cfg_regwen_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_cfg_regwen.485631945
Directory /workspace/9.keymgr_cfg_regwen/latest

Test location /workspace/coverage/default/9.keymgr_custom_cm.1445247514
Short name T805
Test name
Test status
Simulation time 333301445 ps
CPU time 3.18 seconds
Started Mar 26 03:28:27 PM PDT 24
Finished Mar 26 03:28:30 PM PDT 24
Peak memory 221640 kb
Host smart-bbd71f2e-c572-4c70-b1b9-5a02fd8df112
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445247514 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_custom_cm_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_custom_cm.1445247514
Directory /workspace/9.keymgr_custom_cm/latest

Test location /workspace/coverage/default/9.keymgr_direct_to_disabled.1679002260
Short name T894
Test name
Test status
Simulation time 78701453 ps
CPU time 2.59 seconds
Started Mar 26 03:28:22 PM PDT 24
Finished Mar 26 03:28:26 PM PDT 24
Peak memory 209600 kb
Host smart-18ab5448-794d-426d-bac2-95e24baff2e5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1679002260 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_direct_to_disabled_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_direct_to_disabled.1679002260
Directory /workspace/9.keymgr_direct_to_disabled/latest

Test location /workspace/coverage/default/9.keymgr_kmac_rsp_err.2864116854
Short name T318
Test name
Test status
Simulation time 263287985 ps
CPU time 3.56 seconds
Started Mar 26 03:28:18 PM PDT 24
Finished Mar 26 03:28:22 PM PDT 24
Peak memory 214924 kb
Host smart-55b13fa4-0384-4412-8e66-cd35cb12ac70
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2864116854 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_kmac_rsp_err_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_kmac_rsp_err.2864116854
Directory /workspace/9.keymgr_kmac_rsp_err/latest

Test location /workspace/coverage/default/9.keymgr_lc_disable.347235725
Short name T454
Test name
Test status
Simulation time 80280962 ps
CPU time 2.52 seconds
Started Mar 26 03:28:39 PM PDT 24
Finished Mar 26 03:28:42 PM PDT 24
Peak memory 209892 kb
Host smart-192ff057-6f7d-4a99-bd6a-a2cc604696d9
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347235725 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_lc_disable_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_lc_disable.347235725
Directory /workspace/9.keymgr_lc_disable/latest

Test location /workspace/coverage/default/9.keymgr_random.3846448254
Short name T718
Test name
Test status
Simulation time 3762636911 ps
CPU time 10.99 seconds
Started Mar 26 03:28:33 PM PDT 24
Finished Mar 26 03:28:44 PM PDT 24
Peak memory 210232 kb
Host smart-5bdbd9ca-199b-4282-85a7-f02d7ff5111f
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3846448254 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_random_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_random.3846448254
Directory /workspace/9.keymgr_random/latest

Test location /workspace/coverage/default/9.keymgr_sideload.3152149144
Short name T716
Test name
Test status
Simulation time 242434377 ps
CPU time 3.45 seconds
Started Mar 26 03:28:38 PM PDT 24
Finished Mar 26 03:28:42 PM PDT 24
Peak memory 207104 kb
Host smart-0d669272-179d-4436-ae5f-8a963de9b3d5
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3152149144 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload.3152149144
Directory /workspace/9.keymgr_sideload/latest

Test location /workspace/coverage/default/9.keymgr_sideload_aes.1396792871
Short name T866
Test name
Test status
Simulation time 309404984 ps
CPU time 4.73 seconds
Started Mar 26 03:28:34 PM PDT 24
Finished Mar 26 03:28:39 PM PDT 24
Peak memory 208904 kb
Host smart-a17a087c-5172-4dfd-a047-6095ede635d7
User root
Command /workspace/default/simv +sideload_dest=Aes +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/r
epo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1396792871 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_aes.1396792871
Directory /workspace/9.keymgr_sideload_aes/latest

Test location /workspace/coverage/default/9.keymgr_sideload_kmac.1518756054
Short name T869
Test name
Test status
Simulation time 9105468483 ps
CPU time 70.35 seconds
Started Mar 26 03:28:19 PM PDT 24
Finished Mar 26 03:29:30 PM PDT 24
Peak memory 209528 kb
Host smart-dfed8998-2948-446b-94d4-1c85725c573d
User root
Command /workspace/default/simv +sideload_dest=Kmac +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1518756054 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_kmac.1518756054
Directory /workspace/9.keymgr_sideload_kmac/latest

Test location /workspace/coverage/default/9.keymgr_sideload_otbn.3632351882
Short name T874
Test name
Test status
Simulation time 933774097 ps
CPU time 4.72 seconds
Started Mar 26 03:28:36 PM PDT 24
Finished Mar 26 03:28:40 PM PDT 24
Peak memory 207212 kb
Host smart-7bb5bba7-4b99-4afe-9a76-e0064a6a634e
User root
Command /workspace/default/simv +sideload_dest=Otbn +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/
repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3632351882 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_one_intf_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_otbn.3632351882
Directory /workspace/9.keymgr_sideload_otbn/latest

Test location /workspace/coverage/default/9.keymgr_sideload_protect.173023197
Short name T619
Test name
Test status
Simulation time 144912998 ps
CPU time 2.24 seconds
Started Mar 26 03:28:19 PM PDT 24
Finished Mar 26 03:28:22 PM PDT 24
Peak memory 209464 kb
Host smart-46263df1-824e-47cd-99ec-e291f8b92208
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173023197 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sideload_protect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sideload_protect.173023197
Directory /workspace/9.keymgr_sideload_protect/latest

Test location /workspace/coverage/default/9.keymgr_smoke.1841084657
Short name T851
Test name
Test status
Simulation time 49998462 ps
CPU time 2.49 seconds
Started Mar 26 03:28:19 PM PDT 24
Finished Mar 26 03:28:22 PM PDT 24
Peak memory 208196 kb
Host smart-774f703b-b505-4092-9ce0-e319a2106150
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841084657 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_smoke_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_smoke.1841084657
Directory /workspace/9.keymgr_smoke/latest

Test location /workspace/coverage/default/9.keymgr_stress_all.1502827973
Short name T77
Test name
Test status
Simulation time 7909687722 ps
CPU time 236.02 seconds
Started Mar 26 03:28:40 PM PDT 24
Finished Mar 26 03:32:37 PM PDT 24
Peak memory 217784 kb
Host smart-243c07dd-5125-4811-9005-beb1217bfcb1
User root
Command /workspace/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
pace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1502827973 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_stress_al
l_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all.1502827973
Directory /workspace/9.keymgr_stress_all/latest

Test location /workspace/coverage/default/9.keymgr_stress_all_with_rand_reset.2061919844
Short name T703
Test name
Test status
Simulation time 356175511 ps
CPU time 7.12 seconds
Started Mar 26 03:28:51 PM PDT 24
Finished Mar 26 03:28:59 PM PDT 24
Peak memory 223016 kb
Host smart-296366f2-423a-4a22-ae61-b476c2135949
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=keymgr_stress_all_vseq +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2061919844 -assert nopos
tproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/de
fault.vdb -cm_log /dev/null -cm_name 9.keymgr_stress_all_with_rand_reset.2061919844
Directory /workspace/9.keymgr_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.keymgr_sw_invalid_input.1841843402
Short name T370
Test name
Test status
Simulation time 1536038374 ps
CPU time 25.23 seconds
Started Mar 26 03:28:18 PM PDT 24
Finished Mar 26 03:28:43 PM PDT 24
Peak memory 209712 kb
Host smart-7f590693-a586-4121-aba3-c417e9eb6199
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1841843402 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sw_invalid_input_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sw_invalid_input.1841843402
Directory /workspace/9.keymgr_sw_invalid_input/latest

Test location /workspace/coverage/default/9.keymgr_sync_async_fault_cross.3203019128
Short name T664
Test name
Test status
Simulation time 94457599 ps
CPU time 2.64 seconds
Started Mar 26 03:28:18 PM PDT 24
Finished Mar 26 03:28:20 PM PDT 24
Peak memory 210484 kb
Host smart-00390f45-1b0a-4d74-b8e7-108715f99672
User root
Command /workspace/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3203019128 -assert nopostproc +UVM_TESTNAME=keymgr_base_test +UVM_TEST_SEQ=keymgr_sync_async_fault_cross_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.keymgr_sync_async_fault_cross.3203019128
Directory /workspace/9.keymgr_sync_async_fault_cross/latest
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