SCORE | WEIGHT | GOAL | AT LEAST | AUTO BIN MAX | PRINT MISSING |
100.00 | 1 | 100 | 1 | 64 | 64 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Variables | 8 | 0 | 8 | 100.00 |
VARIABLE | EXPECTED | UNCOVERED | COVERED | PERCENT | GOAL | WEIGHT | AT LEAST | AUTO BIN MAX | COMMENT |
invalid_hw_input_cp | 8 | 0 | 8 | 100.00 | 100 | 1 | 1 | 0 |
CATEGORY | EXPECTED | UNCOVERED | COVERED | PERCENT |
Automatically Generated Bins | 8 | 0 | 8 | 100.00 |
NAME | COUNT | AT LEAST | STATUS | TEST | COUNT | TEST | COUNT | TEST | COUNT | |||
auto[OtpRootKeyInvalid] | 805 | 1 | T24 | 60 | T25 | 30 | T88 | 50 | ||||
auto[OtpRootKeyValidLow] | 180 | 1 | T22 | 7 | T24 | 7 | T25 | 7 | ||||
auto[LcStateInvalid] | 108 | 1 | T89 | 12 | T394 | 12 | T395 | 24 | ||||
auto[OtpDevIdInvalid] | 60 | 1 | T85 | 12 | T396 | 24 | T397 | 12 | ||||
auto[RomDigestInvalid] | 48 | 1 | T397 | 36 | T395 | 12 | - | - | ||||
auto[RomDigestValidLow] | 60 | 1 | T398 | 12 | T399 | 24 | T400 | 24 | ||||
auto[FlashCreatorSeedInvalid] | 120 | 1 | T85 | 24 | T89 | 12 | T401 | 84 | ||||
auto[FlashOwnerSeedInvalid] | 48 | 1 | T91 | 12 | T92 | 24 | T93 | 12 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |