Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

Group : keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
74.60	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	1	13	92.86
Crosses	49	15	34	69.39

Variables for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
op_cp	5	1	4	80.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0
wip_cp	2	0	2	100.00	100	1	1	2

Crosses for Group keymgr_env_pkg::keymgr_env_cov::lc_disable_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
state_x_wip_cross	14	1	13	92.86	100	1	1	0
state_x_op_cross	35	14	21	60.00	100	1	1	0

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	1	4	80.00

Automatically Generated Bins for op_cp

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
auto[OpDisable]	0	1	1

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	43	1			T37	1		T46	1		T47	2
auto[OpGenId]	12	1			T42	3		T62	1		T73	1
auto[OpGenSwOut]	25	1			T53	1		T60	1		T8	1
auto[OpGenHwOut]	23	1			T39	1		T7	1		T8	2

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	1641	1			T42	1		T47	1		T48	2
auto[StInit]	91	1			T38	1		T46	1		T53	1
auto[StCreatorRootKey]	61	1			T57	1		T47	2		T48	2
auto[StOwnerIntKey]	35	1			T42	1		T34	1		T35	1
auto[StOwnerKey]	37	1			T42	2		T41	1		T65	1
auto[StDisabled]	493	1			T42	6		T37	1		T68	1
auto[StInvalid]	45	1			T54	1		T58	1		T95	1

---

Summary for Variable wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for wip_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

3374

1

T1

1

T2

1

T3

1

auto[1]

103

1

T42

3

T37

1

T46

1

---

Summary for Cross state_x_wip_cross

Samples crossed: state_cp wip_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	14	1	13	92.86	1

Automatically Generated Cross Bins for state_x_wip_cross

Uncovered bins

state_cp	wip_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	[auto[1]]	0	1	1

Covered bins

state_cp	wip_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[0]	1638	1			T42	1		T47	1		T48	2
auto[StReset]	auto[1]	3	1			T237	1		T51	1		T52	1
auto[StInit]	auto[0]	35	1			T38	1		T55	1		T156	1
auto[StInit]	auto[1]	56	1			T46	1		T53	1		T47	1
auto[StCreatorRootKey]	auto[0]	49	1			T57	1		T47	1		T48	1
auto[StCreatorRootKey]	auto[1]	12	1			T47	1		T48	1		T60	1
auto[StOwnerIntKey]	auto[0]	25	1			T34	1		T35	1		T36	1
auto[StOwnerIntKey]	auto[1]	10	1			T42	1		T30	1		T62	2
auto[StOwnerKey]	auto[0]	26	1			T41	1		T65	1		T28	1
auto[StOwnerKey]	auto[1]	11	1			T42	2		T66	1		T238	1
auto[StDisabled]	auto[0]	482	1			T42	6		T68	1		T47	9
auto[StDisabled]	auto[1]	11	1			T37	1		T70	1		T239	1
auto[StInvalid]	auto[0]	45	1			T54	1		T58	1		T95	1

---

Summary for Cross state_x_op_cross

Samples crossed: state_cp op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	35	14	21	60.00	14

Automatically Generated Cross Bins for state_x_op_cross

Element holes

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StInvalid]]	*	--	--	5

Uncovered bins

state_cp	op_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[StReset]]	[auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	--	--	3
[auto[StInit]]	[auto[OpDisable]]	0	1	1
[auto[StCreatorRootKey]]	[auto[OpGenId]]	0	1	1
[auto[StCreatorRootKey]]	[auto[OpDisable]]	0	1	1
[auto[StOwnerIntKey] , auto[StOwnerKey] , auto[StDisabled]]	[auto[OpDisable]]	--	--	3

Covered bins

state_cp	op_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	auto[OpAdvance]	2	1			T51	1		T52	1		-	-
auto[StReset]	auto[OpGenId]	1	1			T237	1		-	-		-	-
auto[StInit]	auto[OpAdvance]	21	1			T46	1		T47	1		T60	3
auto[StInit]	auto[OpGenId]	3	1			T9	1		T240	1		T241	1
auto[StInit]	auto[OpGenSwOut]	16	1			T53	1		T8	1		T242	1
auto[StInit]	auto[OpGenHwOut]	16	1			T39	1		T7	1		T8	2
auto[StCreatorRootKey]	auto[OpAdvance]	8	1			T47	1		T48	1		T243	1
auto[StCreatorRootKey]	auto[OpGenSwOut]	2	1			T60	1		T244	1		-	-
auto[StCreatorRootKey]	auto[OpGenHwOut]	2	1			T244	1		T245	1		-	-
auto[StOwnerIntKey]	auto[OpAdvance]	4	1			T30	1		T246	1		T247	1
auto[StOwnerIntKey]	auto[OpGenId]	3	1			T42	1		T62	1		T160	1
auto[StOwnerIntKey]	auto[OpGenSwOut]	2	1			T62	1		T82	1		-	-
auto[StOwnerIntKey]	auto[OpGenHwOut]	1	1			T248	1		-	-		-	-
auto[StOwnerKey]	auto[OpAdvance]	2	1			T249	1		T162	1		-	-
auto[StOwnerKey]	auto[OpGenId]	3	1			T42	2		T248	1		-	-
auto[StOwnerKey]	auto[OpGenSwOut]	4	1			T66	1		T81	1		T250	1
auto[StOwnerKey]	auto[OpGenHwOut]	2	1			T238	1		T251	1		-	-
auto[StDisabled]	auto[OpAdvance]	6	1			T37	1		T70	1		T239	1
auto[StDisabled]	auto[OpGenId]	2	1			T73	1		T252	1		-	-
auto[StDisabled]	auto[OpGenSwOut]	1	1			T253	1		-	-		-	-
auto[StDisabled]	auto[OpGenHwOut]	2	1			T254	1		T77	1		-	-