Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

Group : keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
80.58	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	51	0	51	100.00
Crosses	330	74	256	77.58

Variables for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
aes_sl_avail	2	0	2	100.00	100	1	1	2
aes_sl_avail_cp	2	0	2	100.00	100	1	1	2
kmac_sl_avail	2	0	2	100.00	100	1	1	2
kmac_sl_avail_cp	2	0	2	100.00	100	1	1	2
op	5	0	5	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
otbn_sl_avail	2	0	2	100.00	100	1	1	2
otbn_sl_avail_cp	2	0	2	100.00	100	1	1	2
regwen_cp	2	0	2	100.00	100	1	1	2
sideload_clear	8	0	8	100.00	100	1	1	8
sideload_clear_cp	5	0	5	100.00	100	1	1	0
state	7	0	7	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::sideload_clear_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
sideload_clear_x_state_op_cross	280	55	225	80.36	100	1	1	0
sideload_clear_x_sl_avail_cross	40	19	21	52.50	100	1	1	0
sideload_clear_x_regwen_cross	10	0	10	100.00	100	1	1	0

Summary for Variable aes_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4891

1

T3

4

T4

5

T5

8

auto[1]

555

1

T26

2

T27

1

T45

4

---

Summary for Variable aes_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for aes_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4891

1

T3

4

T4

5

T5

8

auto[1]

555

1

T26

2

T27

1

T45

4

---

Summary for Variable kmac_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4892

1

T3

3

T4

5

T5

4

auto[1]

554

1

T3

1

T5

4

T16

4

---

Summary for Variable kmac_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for kmac_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4892

1

T3

3

T4

5

T5

4

auto[1]

554

1

T3

1

T5

4

T16

4

---

Summary for Variable op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	398	1			T26	1		T99	2		T42	4
auto[OpGenId]	1200	1			T4	2		T18	2		T27	1
auto[OpGenSwOut]	1156	1			T3	2		T4	2		T27	1
auto[OpGenHwOut]	2614	1			T3	1		T4	1		T5	8
auto[OpDisable]	78	1			T3	1		T42	1		T64	1

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	398	1			T26	1		T99	2		T42	4
auto[OpGenId]	1200	1			T4	2		T18	2		T27	1
auto[OpGenSwOut]	1156	1			T3	2		T4	2		T27	1
auto[OpGenHwOut]	2614	1			T3	1		T4	1		T5	8
auto[OpDisable]	78	1			T3	1		T42	1		T64	1

---

Summary for Variable otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4847

1

T3

4

T4

5

T5

8

auto[1]

599

1

T26

1

T42

9

T43

3

---

Summary for Variable otbn_sl_avail_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for otbn_sl_avail_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

4847

1

T3

4

T4

5

T5

8

auto[1]

599

1

T26

1

T42

9

T43

3

---

Summary for Variable regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for regwen_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

5137

1

T3

4

T4

5

T5

8

auto[1]

309

1

T114

10

T115

9

T116

2

---

Summary for Variable sideload_clear

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	8	0	8	100.00

Automatically Generated Bins for sideload_clear

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	1821	1			T3	1		T4	1		T5	3
auto[1]	724	1			T3	1		T5	1		T16	2
auto[2]	700	1			T3	1		T5	2		T16	1
auto[3]	723	1			T5	1		T17	2		T27	2
auto[4]	364	1			T4	3		T5	1		T16	1
auto[5]	356	1			T3	1		T4	1		T16	1
auto[6]	372	1			T17	1		T84	1		T27	1
auto[7]	386	1			T99	1		T106	1		T42	3

---

Summary for Variable sideload_clear_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	5	0	5	100.00

User Defined Bins for sideload_clear_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	1478	1			T3	1		T4	4		T5	1
clear_one[1]	724	1			T3	1		T5	1		T16	2
clear_one[2]	700	1			T3	1		T5	2		T16	1
clear_one[3]	723	1			T5	1		T17	2		T27	2
clear_none	1821	1			T3	1		T4	1		T5	3

---

Summary for Variable state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	999	1			T3	1		T27	4		T99	1
auto[StInit]	757	1			T4	1		T5	1		T16	1
auto[StCreatorRootKey]	580	1			T3	1		T5	1		T16	1
auto[StOwnerIntKey]	519	1			T5	1		T16	1		T17	1
auto[StOwnerKey]	501	1			T4	1		T5	1		T16	1
auto[StDisabled]	1935	1			T3	2		T4	3		T5	4
auto[StInvalid]	155	1			T54	3		T58	3		T95	3

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	999	1			T3	1		T27	4		T99	1
auto[StInit]	757	1			T4	1		T5	1		T16	1
auto[StCreatorRootKey]	580	1			T3	1		T5	1		T16	1
auto[StOwnerIntKey]	519	1			T5	1		T16	1		T17	1
auto[StOwnerKey]	501	1			T4	1		T5	1		T16	1
auto[StDisabled]	1935	1			T3	2		T4	3		T5	4
auto[StInvalid]	155	1			T54	3		T58	3		T95	3

---

Summary for Cross sideload_clear_x_state_op_cross

Samples crossed: sideload_clear state op

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	55	225	80.36	55

Automatically Generated Cross Bins for sideload_clear_x_state_op_cross

Uncovered bins

sideload_clear	state	op	COUNT	AT LEAST	NUMBER	STATUS
[auto[0] - auto[1]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	10
[auto[0] - auto[1]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	2
[auto[2] - auto[4]]	[auto[StReset]]	[auto[OpAdvance]]	--	--	3
[auto[2] - auto[4]]	[auto[StReset]]	[auto[OpDisable]]	--	--	3
[auto[2] - auto[4]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	12
[auto[2] - auto[4]]	[auto[StInvalid]]	[auto[OpDisable]]	--	--	3
[auto[5]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[5]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[5]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[5]]	[auto[StInvalid]]	[auto[OpAdvance]]	0	1	1
[auto[5]]	[auto[StInvalid]]	[auto[OpGenHwOut] , auto[OpDisable]]	--	--	2
[auto[6]]	[auto[StReset]]	[auto[OpAdvance]]	0	1	1
[auto[6]]	[auto[StReset]]	[auto[OpDisable]]	0	1	1
[auto[6]]	[auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	4
[auto[6]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1
[auto[7]]	[auto[StReset] , auto[StInit] , auto[StCreatorRootKey] , auto[StOwnerIntKey] , auto[StOwnerKey]]	[auto[OpDisable]]	--	--	5
[auto[7]]	[auto[StInvalid]]	[auto[OpDisable]]	0	1	1

Covered bins

sideload_clear	state	op	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[StReset]	auto[OpAdvance]	2	1			T255	1		T256	1		-	-
auto[0]	auto[StReset]	auto[OpGenId]	151	1			T42	1		T114	1		T64	1
auto[0]	auto[StReset]	auto[OpGenSwOut]	167	1			T3	1		T42	2		T142	1
auto[0]	auto[StReset]	auto[OpGenHwOut]	255	1			T27	1		T99	1		T106	1
auto[0]	auto[StInit]	auto[OpAdvance]	36	1			T140	1		T229	1		T155	1
auto[0]	auto[StInit]	auto[OpGenId]	114	1			T42	1		T50	1		T226	1
auto[0]	auto[StInit]	auto[OpGenSwOut]	106	1			T4	1		T42	1		T68	1
auto[0]	auto[StInit]	auto[OpGenHwOut]	178	1			T5	1		T16	1		T17	1
auto[0]	auto[StCreatorRootKey]	auto[OpAdvance]	18	1			T42	1		T257	1		T258	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenId]	52	1			T42	1		T143	1		T108	2
auto[0]	auto[StCreatorRootKey]	auto[OpGenSwOut]	47	1			T42	1		T222	1		T159	1
auto[0]	auto[StCreatorRootKey]	auto[OpGenHwOut]	72	1			T42	1		T146	1		T64	1
auto[0]	auto[StOwnerIntKey]	auto[OpAdvance]	14	1			T140	1		T150	1		T259	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenId]	39	1			T42	1		T43	1		T61	1
auto[0]	auto[StOwnerIntKey]	auto[OpGenSwOut]	33	1			T141	1		T69	1		T48	2
auto[0]	auto[StOwnerIntKey]	auto[OpGenHwOut]	57	1			T16	1		T260	1		T47	1
auto[0]	auto[StOwnerKey]	auto[OpAdvance]	9	1			T26	1		T261	1		T262	1
auto[0]	auto[StOwnerKey]	auto[OpGenId]	26	1			T68	1		T47	1		T263	1
auto[0]	auto[StOwnerKey]	auto[OpGenSwOut]	28	1			T226	1		T47	1		T7	1
auto[0]	auto[StOwnerKey]	auto[OpGenHwOut]	43	1			T235	1		T260	1		T47	1
auto[0]	auto[StDisabled]	auto[OpAdvance]	25	1			T42	2		T116	1		T48	1
auto[0]	auto[StDisabled]	auto[OpGenId]	67	1			T18	1		T27	1		T45	1
auto[0]	auto[StDisabled]	auto[OpGenSwOut]	51	1			T45	1		T42	1		T232	1
auto[0]	auto[StDisabled]	auto[OpGenHwOut]	162	1			T5	2		T16	1		T26	1
auto[0]	auto[StDisabled]	auto[OpDisable]	22	1			T134	1		T56	1		T8	1
auto[0]	auto[StInvalid]	auto[OpAdvance]	7	1			T95	1		T220	2		T264	1
auto[0]	auto[StInvalid]	auto[OpGenId]	10	1			T54	1		T95	1		T231	1
auto[0]	auto[StInvalid]	auto[OpGenSwOut]	14	1			T218	2		T265	1		T221	1
auto[0]	auto[StInvalid]	auto[OpGenHwOut]	16	1			T58	1		T227	1		T208	1
auto[1]	auto[StReset]	auto[OpAdvance]	1	1			T266	1		-	-		-	-
auto[1]	auto[StReset]	auto[OpGenId]	19	1			T48	2		T224	1		T267	1
auto[1]	auto[StReset]	auto[OpGenSwOut]	23	1			T42	1		T224	1		T62	1
auto[1]	auto[StReset]	auto[OpGenHwOut]	56	1			T42	1		T235	1		T268	1
auto[1]	auto[StInit]	auto[OpAdvance]	8	1			T114	1		T88	1		T227	1
auto[1]	auto[StInit]	auto[OpGenId]	18	1			T22	1		T94	1		T224	1
auto[1]	auto[StInit]	auto[OpGenSwOut]	12	1			T23	1		T48	1		T224	1
auto[1]	auto[StInit]	auto[OpGenHwOut]	22	1			T260	1		T269	1		T136	1
auto[1]	auto[StCreatorRootKey]	auto[OpAdvance]	5	1			T138	1		T270	1		T271	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenId]	19	1			T60	2		T67	1		T104	1
auto[1]	auto[StCreatorRootKey]	auto[OpGenSwOut]	21	1			T219	1		T155	1		T224	2
auto[1]	auto[StCreatorRootKey]	auto[OpGenHwOut]	38	1			T3	1		T144	1		T114	1
auto[1]	auto[StOwnerIntKey]	auto[OpAdvance]	9	1			T115	1		T198	1		T128	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenId]	13	1			T60	1		T272	1		T273	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenSwOut]	13	1			T42	1		T108	1		T8	1
auto[1]	auto[StOwnerIntKey]	auto[OpGenHwOut]	37	1			T235	1		T115	1		T269	1
auto[1]	auto[StOwnerKey]	auto[OpAdvance]	12	1			T115	2		T214	1		T274	1
auto[1]	auto[StOwnerKey]	auto[OpGenId]	11	1			T115	1		T60	1		T211	1
auto[1]	auto[StOwnerKey]	auto[OpGenSwOut]	9	1			T48	1		T124	1		T275	1
auto[1]	auto[StOwnerKey]	auto[OpGenHwOut]	54	1			T42	1		T146	1		T276	1
auto[1]	auto[StDisabled]	auto[OpAdvance]	18	1			T115	1		T47	2		T239	1
auto[1]	auto[StDisabled]	auto[OpGenId]	69	1			T43	1		T68	1		T115	2
auto[1]	auto[StDisabled]	auto[OpGenSwOut]	65	1			T42	2		T133	1		T277	1
auto[1]	auto[StDisabled]	auto[OpGenHwOut]	138	1			T5	1		T16	2		T84	1
auto[1]	auto[StDisabled]	auto[OpDisable]	10	1			T42	1		T224	1		T7	1
auto[1]	auto[StInvalid]	auto[OpAdvance]	1	1			T278	1		-	-		-	-
auto[1]	auto[StInvalid]	auto[OpGenId]	9	1			T54	1		T218	1		T91	1
auto[1]	auto[StInvalid]	auto[OpGenSwOut]	6	1			T221	1		T230	1		T279	1
auto[1]	auto[StInvalid]	auto[OpGenHwOut]	8	1			T95	1		T223	1		T231	1
auto[2]	auto[StReset]	auto[OpGenId]	22	1			T133	1		T25	1		T224	2
auto[2]	auto[StReset]	auto[OpGenSwOut]	13	1			T48	1		T8	1		T280	1
auto[2]	auto[StReset]	auto[OpGenHwOut]	29	1			T42	2		T281	1		T132	1
auto[2]	auto[StInit]	auto[OpAdvance]	8	1			T25	1		T94	1		T282	1
auto[2]	auto[StInit]	auto[OpGenId]	19	1			T114	2		T24	1		T25	1
auto[2]	auto[StInit]	auto[OpGenSwOut]	13	1			T88	1		T73	1		T272	2
auto[2]	auto[StInit]	auto[OpGenHwOut]	21	1			T23	1		T132	1		T268	1
auto[2]	auto[StCreatorRootKey]	auto[OpAdvance]	5	1			T99	1		T48	1		T272	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenId]	14	1			T130	1		T108	1		T283	1
auto[2]	auto[StCreatorRootKey]	auto[OpGenSwOut]	17	1			T224	1		T73	1		T282	2
auto[2]	auto[StCreatorRootKey]	auto[OpGenHwOut]	36	1			T37	1		T281	1		T284	1
auto[2]	auto[StOwnerIntKey]	auto[OpAdvance]	6	1			T130	1		T206	1		T214	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenId]	10	1			T224	1		T157	1		T285	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenSwOut]	12	1			T286	1		T274	1		T287	1
auto[2]	auto[StOwnerIntKey]	auto[OpGenHwOut]	42	1			T5	1		T42	1		T68	1
auto[2]	auto[StOwnerKey]	auto[OpAdvance]	10	1			T130	1		T277	1		T272	1
auto[2]	auto[StOwnerKey]	auto[OpGenId]	11	1			T73	1		T138	1		T288	1
auto[2]	auto[StOwnerKey]	auto[OpGenSwOut]	12	1			T42	1		T234	1		T224	1
auto[2]	auto[StOwnerKey]	auto[OpGenHwOut]	41	1			T16	1		T99	1		T43	1
auto[2]	auto[StDisabled]	auto[OpAdvance]	19	1			T47	1		T239	1		T272	2
auto[2]	auto[StDisabled]	auto[OpGenId]	46	1			T61	1		T47	1		T67	1
auto[2]	auto[StDisabled]	auto[OpGenSwOut]	66	1			T42	1		T43	1		T232	1
auto[2]	auto[StDisabled]	auto[OpGenHwOut]	190	1			T5	1		T17	1		T84	2
auto[2]	auto[StDisabled]	auto[OpDisable]	17	1			T3	1		T108	1		T214	1
auto[2]	auto[StInvalid]	auto[OpAdvance]	4	1			T220	1		T289	1		T290	1
auto[2]	auto[StInvalid]	auto[OpGenId]	9	1			T230	1		T291	1		T292	1
auto[2]	auto[StInvalid]	auto[OpGenSwOut]	7	1			T54	1		T218	1		T91	1
auto[2]	auto[StInvalid]	auto[OpGenHwOut]	1	1			T264	1		-	-		-	-
auto[3]	auto[StReset]	auto[OpGenId]	26	1			T42	1		T224	1		T108	1
auto[3]	auto[StReset]	auto[OpGenSwOut]	23	1			T47	1		T147	1		T224	1
auto[3]	auto[StReset]	auto[OpGenHwOut]	50	1			T27	2		T42	1		T23	1
auto[3]	auto[StInit]	auto[OpAdvance]	4	1			T293	1		T294	1		T295	1
auto[3]	auto[StInit]	auto[OpGenId]	14	1			T86	1		T197	1		T296	1
auto[3]	auto[StInit]	auto[OpGenSwOut]	10	1			T108	1		T297	1		T298	1
auto[3]	auto[StInit]	auto[OpGenHwOut]	35	1			T22	1		T299	1		T24	1
auto[3]	auto[StCreatorRootKey]	auto[OpAdvance]	11	1			T114	2		T91	1		T201	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenId]	11	1			T224	1		T300	1		T262	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenSwOut]	12	1			T68	1		T239	1		T73	1
auto[3]	auto[StCreatorRootKey]	auto[OpGenHwOut]	49	1			T5	1		T106	1		T145	1
auto[3]	auto[StOwnerIntKey]	auto[OpAdvance]	6	1			T143	1		T48	1		T147	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenId]	20	1			T142	1		T94	1		T301	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenSwOut]	4	1			T126	1		T302	1		T303	1
auto[3]	auto[StOwnerIntKey]	auto[OpGenHwOut]	35	1			T17	1		T145	1		T304	1
auto[3]	auto[StOwnerKey]	auto[OpAdvance]	7	1			T155	2		T124	1		T244	1
auto[3]	auto[StOwnerKey]	auto[OpGenId]	13	1			T143	1		T305	1		T306	1
auto[3]	auto[StOwnerKey]	auto[OpGenSwOut]	14	1			T114	3		T307	1		T63	1
auto[3]	auto[StOwnerKey]	auto[OpGenHwOut]	47	1			T17	1		T144	1		T304	1
auto[3]	auto[StDisabled]	auto[OpAdvance]	29	1			T68	1		T147	2		T63	1
auto[3]	auto[StDisabled]	auto[OpGenId]	62	1			T99	1		T60	1		T224	2
auto[3]	auto[StDisabled]	auto[OpGenSwOut]	56	1			T42	1		T114	1		T116	1
auto[3]	auto[StDisabled]	auto[OpGenHwOut]	161	1			T45	1		T144	1		T68	1
auto[3]	auto[StDisabled]	auto[OpDisable]	11	1			T47	1		T8	1		T73	1
auto[3]	auto[StInvalid]	auto[OpAdvance]	2	1			T308	1		T309	1		-	-
auto[3]	auto[StInvalid]	auto[OpGenId]	4	1			T220	1		T290	1		T310	1
auto[3]	auto[StInvalid]	auto[OpGenSwOut]	3	1			T278	1		T311	1		T279	1
auto[3]	auto[StInvalid]	auto[OpGenHwOut]	4	1			T312	1		T308	1		T313	1
auto[4]	auto[StReset]	auto[OpGenId]	10	1			T47	1		T108	1		T8	1
auto[4]	auto[StReset]	auto[OpGenSwOut]	7	1			T287	1		T314	1		T315	1
auto[4]	auto[StReset]	auto[OpGenHwOut]	15	1			T42	1		T48	1		T136	1
auto[4]	auto[StInit]	auto[OpAdvance]	7	1			T99	1		T316	1		T317	1
auto[4]	auto[StInit]	auto[OpGenId]	11	1			T318	1		T128	1		T319	1
auto[4]	auto[StInit]	auto[OpGenSwOut]	6	1			T47	1		T262	1		T77	1
auto[4]	auto[StInit]	auto[OpGenHwOut]	19	1			T23	1		T235	1		T276	1
auto[4]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T320	1		T321	1		T322	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenId]	9	1			T108	1		T273	1		T128	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenSwOut]	7	1			T307	1		T214	2		T323	1
auto[4]	auto[StCreatorRootKey]	auto[OpGenHwOut]	22	1			T16	1		T17	1		T236	1
auto[4]	auto[StOwnerIntKey]	auto[OpAdvance]	1	1			T125	1		-	-		-	-
auto[4]	auto[StOwnerIntKey]	auto[OpGenId]	12	1			T42	1		T64	1		T131	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenSwOut]	4	1			T48	1		T324	1		T325	1
auto[4]	auto[StOwnerIntKey]	auto[OpGenHwOut]	24	1			T84	1		T106	1		T236	1
auto[4]	auto[StOwnerKey]	auto[OpAdvance]	2	1			T222	1		T326	1		-	-
auto[4]	auto[StOwnerKey]	auto[OpGenId]	9	1			T4	1		T232	1		T60	1
auto[4]	auto[StOwnerKey]	auto[OpGenSwOut]	9	1			T37	1		T320	1		T63	1
auto[4]	auto[StOwnerKey]	auto[OpGenHwOut]	20	1			T5	1		T84	1		T42	1
auto[4]	auto[StDisabled]	auto[OpAdvance]	10	1			T206	1		T327	1		T328	1
auto[4]	auto[StDisabled]	auto[OpGenId]	26	1			T4	1		T18	1		T70	1
auto[4]	auto[StDisabled]	auto[OpGenSwOut]	32	1			T4	1		T143	1		T147	1
auto[4]	auto[StDisabled]	auto[OpGenHwOut]	72	1			T17	2		T222	1		T232	1
auto[4]	auto[StDisabled]	auto[OpDisable]	8	1			T64	1		T63	1		T197	1
auto[4]	auto[StInvalid]	auto[OpAdvance]	4	1			T227	1		T289	1		T290	1
auto[4]	auto[StInvalid]	auto[OpGenId]	6	1			T292	1		T290	1		T329	2
auto[4]	auto[StInvalid]	auto[OpGenSwOut]	3	1			T330	1		T311	1		T309	1
auto[4]	auto[StInvalid]	auto[OpGenHwOut]	5	1			T58	1		T227	1		T264	1
auto[5]	auto[StReset]	auto[OpGenId]	6	1			T108	1		T73	1		T125	1
auto[5]	auto[StReset]	auto[OpGenSwOut]	2	1			T23	1		T331	1		-	-
auto[5]	auto[StReset]	auto[OpGenHwOut]	25	1			T235	1		T268	1		T332	1
auto[5]	auto[StInit]	auto[OpAdvance]	2	1			T207	1		T255	1		-	-
auto[5]	auto[StInit]	auto[OpGenId]	4	1			T277	1		T333	1		T334	1
auto[5]	auto[StInit]	auto[OpGenSwOut]	5	1			T287	1		T335	1		T336	1
auto[5]	auto[StInit]	auto[OpGenHwOut]	13	1			T199	1		T337	1		T127	1
auto[5]	auto[StCreatorRootKey]	auto[OpAdvance]	5	1			T63	1		T230	1		T255	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenId]	4	1			T42	1		T47	1		T8	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenSwOut]	7	1			T105	1		T338	1		T294	1
auto[5]	auto[StCreatorRootKey]	auto[OpGenHwOut]	29	1			T235	1		T210	1		T339	1
auto[5]	auto[StOwnerIntKey]	auto[OpAdvance]	5	1			T340	1		T262	1		T341	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenId]	8	1			T255	1		T262	1		T342	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenSwOut]	11	1			T27	1		T103	1		T343	1
auto[5]	auto[StOwnerIntKey]	auto[OpGenHwOut]	29	1			T226	1		T344	1		T345	1
auto[5]	auto[StOwnerKey]	auto[OpAdvance]	5	1			T48	1		T293	1		T346	1
auto[5]	auto[StOwnerKey]	auto[OpGenId]	10	1			T48	1		T67	1		T224	1
auto[5]	auto[StOwnerKey]	auto[OpGenSwOut]	13	1			T42	1		T262	1		T328	1
auto[5]	auto[StOwnerKey]	auto[OpGenHwOut]	14	1			T145	1		T347	1		T125	1
auto[5]	auto[StDisabled]	auto[OpAdvance]	13	1			T42	1		T105	1		T224	1
auto[5]	auto[StDisabled]	auto[OpGenId]	25	1			T47	1		T8	1		T280	1
auto[5]	auto[StDisabled]	auto[OpGenSwOut]	27	1			T3	1		T7	1		T8	1
auto[5]	auto[StDisabled]	auto[OpGenHwOut]	83	1			T4	1		T16	1		T84	1
auto[5]	auto[StDisabled]	auto[OpDisable]	3	1			T126	1		T77	1		T336	1
auto[5]	auto[StInvalid]	auto[OpGenId]	4	1			T221	1		T330	1		T291	1
auto[5]	auto[StInvalid]	auto[OpGenSwOut]	4	1			T58	1		T265	1		T313	1
auto[6]	auto[StReset]	auto[OpGenId]	12	1			T42	1		T73	1		T348	1
auto[6]	auto[StReset]	auto[OpGenSwOut]	15	1			T48	1		T133	1		T301	1
auto[6]	auto[StReset]	auto[OpGenHwOut]	22	1			T27	1		T42	1		T64	1
auto[6]	auto[StInit]	auto[OpAdvance]	4	1			T88	2		T348	1		T89	1
auto[6]	auto[StInit]	auto[OpGenId]	9	1			T25	1		T87	1		T349	1
auto[6]	auto[StInit]	auto[OpGenSwOut]	5	1			T224	1		T88	1		T77	2
auto[6]	auto[StInit]	auto[OpGenHwOut]	8	1			T60	1		T350	1		T351	1
auto[6]	auto[StCreatorRootKey]	auto[OpAdvance]	4	1			T70	1		T254	1		T352	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenId]	4	1			T82	1		T353	2		T354	1
auto[6]	auto[StCreatorRootKey]	auto[OpGenSwOut]	1	1			T248	1		-	-		-	-
auto[6]	auto[StCreatorRootKey]	auto[OpGenHwOut]	17	1			T84	1		T226	1		T48	1
auto[6]	auto[StOwnerIntKey]	auto[OpAdvance]	3	1			T77	1		T81	1		T355	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenId]	7	1			T306	1		T356	1		T357	2
auto[6]	auto[StOwnerIntKey]	auto[OpGenSwOut]	6	1			T224	1		T76	1		T358	1
auto[6]	auto[StOwnerIntKey]	auto[OpGenHwOut]	18	1			T146	1		T281	1		T239	1
auto[6]	auto[StOwnerKey]	auto[OpAdvance]	3	1			T47	1		T80	1		T317	1
auto[6]	auto[StOwnerKey]	auto[OpGenId]	8	1			T318	1		T60	1		T214	1
auto[6]	auto[StOwnerKey]	auto[OpGenSwOut]	12	1			T63	1		T359	1		T319	1
auto[6]	auto[StOwnerKey]	auto[OpGenHwOut]	15	1			T269	1		T108	1		T63	1
auto[6]	auto[StDisabled]	auto[OpAdvance]	17	1			T114	1		T155	1		T47	1
auto[6]	auto[StDisabled]	auto[OpGenId]	37	1			T42	1		T143	1		T47	1
auto[6]	auto[StDisabled]	auto[OpGenSwOut]	42	1			T42	2		T48	2		T60	1
auto[6]	auto[StDisabled]	auto[OpGenHwOut]	89	1			T17	1		T37	1		T144	1
auto[6]	auto[StDisabled]	auto[OpDisable]	4	1			T360	1		T361	1		T362	1
auto[6]	auto[StInvalid]	auto[OpAdvance]	2	1			T231	1		T289	1		-	-
auto[6]	auto[StInvalid]	auto[OpGenId]	1	1			T363	1		-	-		-	-
auto[6]	auto[StInvalid]	auto[OpGenSwOut]	3	1			T311	1		T279	1		T363	1
auto[6]	auto[StInvalid]	auto[OpGenHwOut]	4	1			T208	1		T264	1		T312	1
auto[7]	auto[StReset]	auto[OpAdvance]	1	1			T364	1		-	-		-	-
auto[7]	auto[StReset]	auto[OpGenId]	12	1			T42	1		T47	1		T365	1
auto[7]	auto[StReset]	auto[OpGenSwOut]	11	1			T366	1		T230	2		T287	1
auto[7]	auto[StReset]	auto[OpGenHwOut]	24	1			T88	1		T280	1		T332	1
auto[7]	auto[StInit]	auto[OpAdvance]	4	1			T25	1		T367	1		T368	1
auto[7]	auto[StInit]	auto[OpGenId]	6	1			T42	1		T219	1		T86	1
auto[7]	auto[StInit]	auto[OpGenSwOut]	8	1			T115	1		T208	1		T358	1
auto[7]	auto[StInit]	auto[OpGenHwOut]	28	1			T146	1		T94	1		T369	1
auto[7]	auto[StCreatorRootKey]	auto[OpAdvance]	5	1			T131	1		T206	2		T77	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenId]	7	1			T115	3		T370	1		T371	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenSwOut]	6	1			T133	1		T94	1		T372	1
auto[7]	auto[StCreatorRootKey]	auto[OpGenHwOut]	22	1			T276	1		T136	1		T199	1
auto[7]	auto[StOwnerIntKey]	auto[OpAdvance]	2	1			T373	1		T374	1		-	-
auto[7]	auto[StOwnerIntKey]	auto[OpGenId]	10	1			T318	1		T224	1		T375	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenSwOut]	9	1			T42	1		T206	1		T376	1
auto[7]	auto[StOwnerIntKey]	auto[OpGenHwOut]	20	1			T144	1		T206	2		T209	1
auto[7]	auto[StOwnerKey]	auto[OpAdvance]	3	1			T377	1		T378	1		T379	1
auto[7]	auto[StOwnerKey]	auto[OpGenId]	8	1			T283	1		T377	2		T262	1
auto[7]	auto[StOwnerKey]	auto[OpGenSwOut]	6	1			T69	1		T224	1		T287	2
auto[7]	auto[StOwnerKey]	auto[OpGenHwOut]	17	1			T106	1		T299	1		T380	1
auto[7]	auto[StDisabled]	auto[OpAdvance]	15	1			T141	1		T116	1		T131	1
auto[7]	auto[StDisabled]	auto[OpGenId]	29	1			T222	1		T155	1		T47	2
auto[7]	auto[StDisabled]	auto[OpGenSwOut]	36	1			T99	1		T114	2		T48	1
auto[7]	auto[StDisabled]	auto[OpGenHwOut]	80	1			T144	1		T146	1		T260	1
auto[7]	auto[StDisabled]	auto[OpDisable]	3	1			T262	1		T321	1		T381	1
auto[7]	auto[StInvalid]	auto[OpAdvance]	1	1			T223	1		-	-		-	-
auto[7]	auto[StInvalid]	auto[OpGenId]	8	1			T230	1		T296	1		T311	1
auto[7]	auto[StInvalid]	auto[OpGenSwOut]	2	1			T208	1		T382	1		-	-
auto[7]	auto[StInvalid]	auto[OpGenHwOut]	3	1			T383	2		T384	1		-	-

---

Summary for Cross sideload_clear_x_sl_avail_cross

Samples crossed: sideload_clear_cp aes_sl_avail kmac_sl_avail otbn_sl_avail

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	19	21	52.50	19

Automatically Generated Cross Bins for sideload_clear_x_sl_avail_cross

Element holes

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[1]]	*	--	--	2
[clear_all]	[auto[1]]	*	*	--	--	4
[clear_one[1]]	[auto[1]]	*	*	--	--	4
[clear_one[2]]	*	[auto[1]]	*	--	--	4
[clear_one[3]]	*	*	[auto[1]]	--	--	4

Uncovered bins

sideload_clear_cp	aes_sl_avail	kmac_sl_avail	otbn_sl_avail	COUNT	AT LEAST	NUMBER	STATUS
[clear_all]	[auto[0]]	[auto[0]]	[auto[1]]	0	1	1

Covered bins

sideload_clear_cp

aes_sl_avail

kmac_sl_avail

otbn_sl_avail

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

clear_all

auto[0]

auto[0]

auto[0]

1478

1

T3

1

T4

4

T5

1

clear_one[1]

auto[0]

auto[0]

auto[0]

419

1

T42

2

T144

1

T114

2

clear_one[1]

auto[0]

auto[0]

auto[1]

125

1

T42

3

T43

1

T146

3

clear_one[1]

auto[0]

auto[1]

auto[0]

129

1

T3

1

T5

1

T16

2

clear_one[1]

auto[0]

auto[1]

auto[1]

51

1

T68

1

T115

1

T48

1

clear_one[2]

auto[0]

auto[0]

auto[0]

387

1

T3

1

T5

2

T16

1

clear_one[2]

auto[0]

auto[0]

auto[1]

149

1

T42

2

T43

2

T146

1

clear_one[2]

auto[1]

auto[0]

auto[0]

110

1

T106

3

T142

2

T260

1

clear_one[2]

auto[1]

auto[0]

auto[1]

54

1

T42

1

T47

1

T48

1

clear_one[3]

auto[0]

auto[0]

auto[0]

430

1

T27

2

T99

1

T42

2

clear_one[3]

auto[0]

auto[1]

auto[0]

121

1

T5

1

T17

2

T42

1

clear_one[3]

auto[1]

auto[0]

auto[0]

133

1

T106

1

T144

2

T143

1

clear_one[3]

auto[1]

auto[1]

auto[0]

39

1

T45

1

T143

1

T147

4

clear_none

auto[0]

auto[0]

auto[0]

1312

1

T3

1

T4

1

T5

1

clear_none

auto[0]

auto[0]

auto[1]

133

1

T42

1

T146

1

T64

1

clear_none

auto[0]

auto[1]

auto[0]

130

1

T5

2

T16

2

T18

1

clear_none

auto[0]

auto[1]

auto[1]

27

1

T42

1

T149

1

T8

1

clear_none

auto[1]

auto[0]

auto[0]

126

1

T106

1

T42

1

T144

1

clear_none

auto[1]

auto[0]

auto[1]

36

1

T42

1

T219

1

T47

1

clear_none

auto[1]

auto[1]

auto[0]

33

1

T26

1

T27

1

T45

3

clear_none

auto[1]

auto[1]

auto[1]

24

1

T26

1

T233

1

T47

1

---

Summary for Cross sideload_clear_x_regwen_cross

Samples crossed: sideload_clear_cp regwen_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	10	0	10	100.00

Automatically Generated Cross Bins for sideload_clear_x_regwen_cross

Bins

sideload_clear_cp	regwen_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
clear_all	auto[0]	1385	1			T3	1		T4	4		T5	1
clear_all	auto[1]	93	1			T114	3		T115	3		T155	1
clear_one[1]	auto[0]	664	1			T3	1		T5	1		T16	2
clear_one[1]	auto[1]	60	1			T114	1		T115	6		T155	1
clear_one[2]	auto[0]	646	1			T3	1		T5	2		T16	1
clear_one[2]	auto[1]	54	1			T114	1		T130	5		T385	2
clear_one[3]	auto[0]	670	1			T5	1		T17	2		T27	2
clear_one[3]	auto[1]	53	1			T114	5		T155	2		T147	5
clear_none	auto[0]	1772	1			T3	1		T4	1		T5	3
clear_none	auto[1]	49	1			T116	2		T320	1		T385	5