Unified Coverage Report :: Group :: keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

Group : keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
43.16	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_keymgr_env_0.1/keymgr_env_cov.sv

---

Summary for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	360	216	144	40.00

Variables for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cdi_cp	2	0	2	100.00	100	1	1	0
dest_cp	4	0	4	100.00	100	1	1	0
op_cp	5	0	5	100.00	100	1	1	0
op_status_cp	2	0	2	100.00	100	1	1	0
state_cp	7	0	7	100.00	100	1	1	0

Crosses for Group keymgr_env_pkg::keymgr_env_cov::state_and_op_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
op_x_state_cross	280	168	112	40.00	100	1	1	0
op_x_status_cross	80	48	32	40.00	100	1	1	0

Summary for Variable cdi_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cdi_cp

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[Sealing]

11993

1

T1

5

T2

16

T3

10

auto[Attestation]

8660

1

T1

3

T2

5

T3

2

---

Summary for Variable dest_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	4	0	4	100.00

Automatically Generated Bins for dest_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[None]	3093	1			T1	2		T2	3		T3	3
auto[Aes]	3570	1			T1	1		T2	1		T3	1
auto[Kmac]	3666	1			T2	2		T3	3		T5	8
auto[Otbn]	3722	1			T1	1		T2	1		T3	3

---

Summary for Variable op_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	5	0	5	100.00

Automatically Generated Bins for op_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpAdvance]	8360	1			T1	8		T2	8		T3	3
auto[OpGenId]	6602	1			T1	4		T2	14		T3	2
auto[OpGenSwOut]	6552	1			T1	4		T2	7		T3	4
auto[OpGenHwOut]	7499	1			T3	6		T4	3		T5	8
auto[OpDisable]	151	1			T3	1		T42	1		T50	1

---

Summary for Variable op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for op_status_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
auto[OpIdle]	0	Excluded
auto[OpWip]	0	Excluded
illegal	0	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[OpDoneSuccess]

10880

1

T1

8

T2

8

T3

9

auto[OpDoneFail]

18284

1

T1

8

T2

21

T3

7

---

Summary for Variable state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	7	0	7	100.00

Automatically Generated Bins for state_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[StReset]	6710	1			T1	1		T2	14		T3	4
auto[StInit]	4602	1			T1	2		T2	2		T3	2
auto[StCreatorRootKey]	3214	1			T1	2		T2	2		T3	4
auto[StOwnerIntKey]	2890	1			T1	2		T2	2		T3	3
auto[StOwnerKey]	2524	1			T1	2		T2	2		T4	2
auto[StDisabled]	8196	1			T1	7		T2	7		T3	3
auto[StInvalid]	1028	1			T54	24		T58	23		T95	17

---

Summary for Cross op_x_state_cross

Samples crossed: op_cp cdi_cp dest_cp state_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	280	168	112	40.00	168

Automatically Generated Cross Bins for op_x_state_cross

Element holes

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	112
[auto[OpDisable]]	*	*	*	--	--	56

Covered bins

op_cp	cdi_cp	dest_cp	state_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StReset]	348	1			T2	2		T42	3		T38	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInit]	119	1			T4	1		T57	1		T50	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	90	1			T3	1		T42	3		T68	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	76	1			T2	1		T27	1		T42	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	74	1			T18	1		T37	1		T114	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	218	1			T1	2		T99	2		T42	2
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	26	1			T54	3		T58	3		T218	2
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	344	1			T27	1		T42	2		T38	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	154	1			T34	1		T36	1		T22	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	62	1			T142	1		T47	1		T69	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	63	1			T42	1		T141	1		T219	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	59	1			T42	2		T114	1		T48	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	211	1			T1	1		T42	1		T141	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	27	1			T220	1		T208	1		T221	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	353	1			T2	1		T42	3		T35	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	107	1			T68	1		T222	1		T22	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	80	1			T27	1		T68	1		T140	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	75	1			T3	1		T34	1		T35	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	69	1			T37	1		T64	1		T115	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	222	1			T3	1		T26	1		T42	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	28	1			T58	1		T223	2		T218	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	332	1			T3	1		T99	1		T42	3
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	138	1			T42	3		T41	1		T142	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	102	1			T18	1		T43	1		T35	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	70	1			T99	1		T42	3		T41	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	52	1			T140	1		T116	1		T69	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	214	1			T2	1		T4	1		T15	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	39	1			T54	1		T58	1		T95	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StReset]	92	1			T47	1		T60	1		T224	7
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInit]	127	1			T45	1		T68	1		T141	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	82	1			T26	1		T42	1		T34	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	72	1			T18	1		T47	1		T225	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	77	1			T42	2		T143	1		T226	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	249	1			T15	1		T42	2		T43	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	32	1			T54	1		T58	1		T227	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	86	1			T42	2		T47	2		T224	3
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	131	1			T2	1		T42	2		T35	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	86	1			T26	1		T27	1		T42	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	74	1			T15	1		T18	1		T27	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	49	1			T42	1		T228	1		T69	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	225	1			T27	1		T45	1		T68	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	26	1			T54	2		T58	1		T223	2
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	84	1			T48	1		T224	2		T108	6
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	130	1			T42	3		T141	1		T22	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	80	1			T27	1		T222	1		T48	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	72	1			T42	1		T35	1		T41	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	82	1			T27	1		T141	1		T229	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	246	1			T2	1		T18	1		T27	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	23	1			T54	1		T218	2		T230	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	87	1			T42	3		T48	1		T60	2
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	128	1			T26	1		T42	2		T46	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	74	1			T15	1		T26	1		T42	3
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	65	1			T42	1		T36	1		T130	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	68	1			T1	1		T42	2		T140	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	223	1			T15	2		T42	5		T114	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	30	1			T95	1		T218	1		T231	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StReset]	282	1			T27	1		T99	1		T42	6
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInit]	125	1			T42	2		T141	1		T232	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StCreatorRootKey]	89	1			T3	1		T42	1		T41	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerIntKey]	67	1			T27	1		T42	1		T233	2
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StOwnerKey]	63	1			T42	1		T116	1		T234	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StDisabled]	172	1			T18	1		T222	1		T47	3
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[StInvalid]	26	1			T223	1		T218	3		T231	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StReset]	433	1			T27	1		T99	1		T106	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInit]	144	1			T106	1		T42	1		T144	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StCreatorRootKey]	89	1			T27	1		T42	2		T144	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerIntKey]	86	1			T26	1		T106	1		T222	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StOwnerKey]	85	1			T106	1		T42	2		T140	3
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StDisabled]	273	1			T18	1		T26	1		T106	3
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[StInvalid]	38	1			T95	1		T227	2		T218	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StReset]	434	1			T27	4		T42	3		T140	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInit]	142	1			T5	1		T16	1		T17	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StCreatorRootKey]	127	1			T3	1		T5	1		T45	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerIntKey]	107	1			T5	1		T26	1		T42	3
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StOwnerKey]	95	1			T5	1		T17	1		T18	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StDisabled]	276	1			T16	3		T17	2		T18	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[StInvalid]	30	1			T54	1		T58	2		T223	3
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StReset]	479	1			T3	2		T27	1		T99	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInit]	144	1			T27	1		T42	2		T146	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StCreatorRootKey]	115	1			T42	1		T146	1		T57	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerIntKey]	111	1			T4	1		T42	5		T146	1
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StOwnerKey]	78	1			T42	2		T146	1		T140	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StDisabled]	296	1			T4	1		T26	1		T42	2
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[StInvalid]	44	1			T54	1		T95	2		T227	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StReset]	61	1			T42	3		T224	5		T108	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInit]	118	1			T42	1		T43	1		T68	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StCreatorRootKey]	67	1			T27	1		T233	1		T23	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerIntKey]	73	1			T3	1		T99	1		T42	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StOwnerKey]	56	1			T42	1		T47	1		T69	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StDisabled]	180	1			T4	1		T27	1		T99	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[StInvalid]	32	1			T58	2		T95	2		T227	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StReset]	60	1			T42	3		T47	1		T48	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInit]	152	1			T3	1		T34	1		T141	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StCreatorRootKey]	102	1			T106	1		T41	1		T235	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerIntKey]	96	1			T144	1		T36	1		T141	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StOwnerKey]	102	1			T27	1		T99	1		T42	3
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StDisabled]	277	1			T99	1		T45	1		T106	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[StInvalid]	36	1			T218	1		T91	1		T231	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StReset]	62	1			T42	4		T48	3		T224	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInit]	138	1			T84	1		T42	1		T145	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StCreatorRootKey]	117	1			T16	1		T17	1		T84	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerIntKey]	93	1			T16	1		T17	1		T84	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StOwnerKey]	84	1			T16	1		T27	1		T145	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StDisabled]	288	1			T5	4		T16	1		T17	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[StInvalid]	22	1			T58	1		T223	1		T218	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StReset]	73	1			T42	4		T47	1		T48	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInit]	150	1			T18	1		T42	2		T222	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StCreatorRootKey]	111	1			T18	1		T42	1		T222	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerIntKey]	100	1			T18	1		T42	3		T222	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StOwnerKey]	84	1			T42	2		T43	1		T236	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StDisabled]	285	1			T18	1		T26	2		T42	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[StInvalid]	30	1			T95	1		T227	1		T218	1

---

Summary for Cross op_x_status_cross

Samples crossed: op_cp cdi_cp dest_cp op_status_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	80	48	32	40.00	48

Automatically Generated Cross Bins for op_x_status_cross

Element holes

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	NUMBER	STATUS
[auto[OpAdvance] , auto[OpGenId]]	*	*	*	--	--	32
[auto[OpDisable]]	*	*	*	--	--	16

Excluded/Illegal bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	STATUS
[auto[OpAdvance] , auto[OpGenId] , auto[OpGenSwOut] , auto[OpGenHwOut] , auto[OpDisable]]	[auto[Sealing] , auto[Attestation]]	[auto[None] , auto[Aes] , auto[Kmac] , auto[Otbn]]	[auto[OpIdle] , auto[OpWip]]	--	Excluded	(80 bins)

Covered bins

op_cp	cdi_cp	dest_cp	op_status_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	220	1			T2	1		T3	1		T27	1
auto[OpGenSwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	731	1			T1	2		T2	2		T4	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	165	1			T42	2		T114	1		T142	1
auto[OpGenSwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	755	1			T1	1		T27	1		T42	4
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	211	1			T3	1		T27	1		T34	1
auto[OpGenSwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	723	1			T2	1		T3	1		T26	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	209	1			T42	3		T43	1		T35	1
auto[OpGenSwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	738	1			T2	1		T3	1		T4	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	213	1			T42	1		T34	1		T226	1
auto[OpGenSwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	518	1			T15	1		T18	1		T26	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	193	1			T15	1		T18	1		T26	1
auto[OpGenSwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	484	1			T2	1		T27	1		T45	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	221	1			T27	2		T42	1		T35	1
auto[OpGenSwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	496	1			T2	1		T18	1		T27	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	190	1			T1	1		T15	1		T26	1
auto[OpGenSwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	485	1			T15	2		T26	1		T42	11
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneSuccess]	204	1			T3	1		T42	3		T41	1
auto[OpGenHwOut]	auto[Sealing]	auto[None]	auto[OpDoneFail]	620	1			T18	1		T27	2		T99	1
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneSuccess]	244	1			T26	1		T27	1		T106	2
auto[OpGenHwOut]	auto[Sealing]	auto[Aes]	auto[OpDoneFail]	904	1			T18	1		T26	1		T27	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneSuccess]	309	1			T3	1		T5	3		T17	1
auto[OpGenHwOut]	auto[Sealing]	auto[Kmac]	auto[OpDoneFail]	902	1			T5	1		T16	4		T17	3
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneSuccess]	285	1			T4	1		T42	5		T146	3
auto[OpGenHwOut]	auto[Sealing]	auto[Otbn]	auto[OpDoneFail]	982	1			T3	2		T4	1		T26	1
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneSuccess]	178	1			T3	1		T99	1		T42	2
auto[OpGenHwOut]	auto[Attestation]	auto[None]	auto[OpDoneFail]	409	1			T4	1		T27	2		T99	1
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneSuccess]	280	1			T27	1		T106	1		T42	3
auto[OpGenHwOut]	auto[Attestation]	auto[Aes]	auto[OpDoneFail]	545	1			T3	1		T99	2		T45	1
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneSuccess]	274	1			T16	3		T17	2		T84	2
auto[OpGenHwOut]	auto[Attestation]	auto[Kmac]	auto[OpDoneFail]	530	1			T5	4		T16	1		T17	2
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneSuccess]	272	1			T42	6		T43	1		T222	1
auto[OpGenHwOut]	auto[Attestation]	auto[Otbn]	auto[OpDoneFail]	561	1			T18	4		T26	2		T42	7